commit d15f4e2ef3b1b4c01a490a00b0f6dc744741ce01
author Mingyao Yang <mingyao@google.com> Thu Apr 17 18:46:24 2014 -0700
committer Mingyao Yang <mingyao@google.com> Thu Apr 17 18:49:43 2014 -0700
tree d175bb7b1027107c9abfb48f7f4f0a8c0c4e47a4
parent 9d46314a309aff327f9913789b5f61200c162609

Fix a use of OpCondBranch that breaks the MIPS build.

Change-Id: I09e19cb00c1e3f4bc0b0293f58674c9160094f7f

compiler/dex/quick/gen_common.cc

diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc
index 68f606b..bb19516 100644
--- a/compiler/dex/quick/gen_common.cc
+++ b/compiler/dex/quick/gen_common.cc
@@ -1591,7 +1591,7 @@
       rl_src1 = LoadValue(rl_src1, kCoreReg);
       rl_src2 = LoadValue(rl_src2, kCoreReg);
       if (check_zero) {
-          GenDivZeroCheck(rl_src2.reg);
+        GenDivZeroCheck(rl_src2.reg);
       }
       rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv);
       done = true;
@@ -1602,7 +1602,7 @@
         rl_src1 = LoadValue(rl_src1, kCoreReg);
         rl_src2 = LoadValue(rl_src2, kCoreReg);
         if (check_zero) {
-            GenDivZeroCheck(rl_src2.reg);
+          GenDivZeroCheck(rl_src2.reg);
         }
         rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv);
         done = true;

compiler/dex/quick/mips/int_mips.cc

diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index 968965b..2375720 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -346,7 +346,7 @@
   DCHECK(reg.IsPair());   // TODO: support k64BitSolo.
   RegStorage t_reg = AllocTemp();
   OpRegRegReg(kOpOr, t_reg, reg.GetLow(), reg.GetHigh());
-  GenDivZeroCheck(kCondEq);
+  GenDivZeroCheck(t_reg);
   FreeTemp(t_reg);
 }