commit b72c723bfb21e05cb9b0a7999db805df93fcaee8
author Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Tue Oct 28 19:29:52 2014 -0700
committer Ian Rogers <irogers@google.com> Fri Nov 21 16:13:40 2014 -0800
tree b61db90dcb0d7c77fe4a0a31e280c4268a91128e
parent 1d56c84657a9ba35222f4b6f1f606a0a7f0fe7e0

ART: X86 vectorized reduce may use incorrect extract index

In the case of reduction to memory VR, the extract index is ignored.
However, it should not be ignored because it is needed for pextr instruction.

Change-Id: I46a0c76218a0553e677225e403786522c079d27d
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>

compiler/dex/mir_graph.cc

diff --git a/compiler/dex/mir_graph.cc b/compiler/dex/mir_graph.cc
index 82a2408..29972dd 100644
--- a/compiler/dex/mir_graph.cc
+++ b/compiler/dex/mir_graph.cc
@@ -1344,9 +1344,10 @@
           decoded_mir->append(", ");
           decoded_mir->append(GetSSANameWithConst(ssa_rep->defs[1], false));
         }
-        decoded_mir->append(StringPrintf(" = vect%d", mir->dalvikInsn.vB));
+        decoded_mir->append(StringPrintf(" = vect%d (extr_idx:%d)", mir->dalvikInsn.vB, mir->dalvikInsn.arg[0]));
       } else {
-        decoded_mir->append(StringPrintf(" v%d = vect%d", mir->dalvikInsn.vA, mir->dalvikInsn.vB));
+        decoded_mir->append(StringPrintf(" v%d = vect%d (extr_idx:%d)", mir->dalvikInsn.vA,
+                                         mir->dalvikInsn.vB, mir->dalvikInsn.arg[0]));
       }
       FillTypeSizeString(mir->dalvikInsn.vC, decoded_mir);
       break;

compiler/dex/quick/x86/target_x86.cc

diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index ead31b3..998aeff 100755
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -2263,7 +2263,8 @@
       StoreFinalValue(rl_dest, rl_result);
     } else {
       int displacement = SRegOffset(rl_result.s_reg_low);
-      LIR *l = NewLIR3(extr_opcode, rs_rX86_SP_32.GetReg(), displacement, vector_src.GetReg());
+      LIR *l = NewLIR4(extr_opcode, rs_rX86_SP_32.GetReg(), displacement, vector_src.GetReg(),
+                       extract_index);
       AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is_wide /* is_64bit */);
       AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is_wide /* is_64bit */);
     }