commit 41cdd43bd6968a06b1344efdd57ccf302f997a0e
author Ian Rogers <irogers@google.com> Fri Oct 11 08:44:13 2013 -0700
committer Ian Rogers <irogers@google.com> Fri Oct 11 08:44:13 2013 -0700
tree 82cb81b241a3dd8bfe845c057c9b37f0f917cde6
parent 775c496f989f0e37d2e9a43274c0b55f201b4116

Disable select instruction generation on ARM.

Change-Id: I114547d44605b06b2fed396b2fbad03935f66ebc

compiler/dex/mir_optimization.cc

diff --git a/compiler/dex/mir_optimization.cc b/compiler/dex/mir_optimization.cc
index 05e428e..0b4f041 100644
--- a/compiler/dex/mir_optimization.cc
+++ b/compiler/dex/mir_optimization.cc
@@ -325,7 +325,8 @@
       // Is this the select pattern?
       // TODO: flesh out support for Mips and X86.  NOTE: llvm's select op doesn't quite work here.
       // TUNING: expand to support IF_xx compare & branches
-      if (!(cu_->compiler_backend == kPortable) && (cu_->instruction_set == kThumb2) &&
+      if (false &&
+          !(cu_->compiler_backend == kPortable) && (cu_->instruction_set == kThumb2) &&
           ((mir->dalvikInsn.opcode == Instruction::IF_EQZ) ||
           (mir->dalvikInsn.opcode == Instruction::IF_NEZ))) {
         BasicBlock* ft = bb->fall_through;