riscv64: define general-purpose and floating-point registers.
Registers on RISC-V have two naming schemes: ordinary names X0 - X31,
F0 - F31 and semantic names that reflect the use of each register per
RISC-V calling convention. In ART, we choose to use semantic names, e.g.
RA for return address register X1, S0 - S11 for callee-saved registers
X8 - X9 and X18 - X27, etc. The use of semantic names simplifes the code
and falls in line with other tools like compilers and debuggers.
This CL also defines ART thread register TR (not to be confused with
plaform thread register TP, which is used by libc and points to the TLS
area of the current thread). TR is defined as X9/S1, which is the first
callee-saved register that does not have a special purpose (X8 is the
frame pointer FP).
Test: lunch aosp_riscv64-userdebug && m dist
Co-authored-by: Ulya Trafimovich <skvadrik@google.com>
Change-Id: Iaccaa67b04d91f96d6c46c80fc7eaac65987141a
3 files changed
