Fix cpplint whitespace/operators issues
Change-Id: I730bd87b476bfa36e93b42e816ef358006b69ba5
diff --git a/Android.mk b/Android.mk
index ff08dca..0b530fa 100644
--- a/Android.mk
+++ b/Android.mk
@@ -334,7 +334,7 @@
.PHONY: cpplint-art
cpplint-art:
./art/tools/cpplint.py \
- --filter=-,+build/header_guard,+whitespace/braces,+whitespace/comma,+runtime/explicit,+whitespace/newline,+whitespace/parens,+build/namespaces,+readability/fn_size \
+ --filter=-,+build/header_guard,+whitespace/braces,+whitespace/comma,+runtime/explicit,+whitespace/newline,+whitespace/parens,+build/namespaces,+readability/fn_size,+whitespace/operators \
$(shell find art -name *.h -o -name *$(ART_CPP_EXTENSION) | grep -v art/compiler/llvm/generated/)
# "mm cpplint-art-aspirational" to see warnings we would like to fix
diff --git a/compiler/dex/mir_dataflow.cc b/compiler/dex/mir_dataflow.cc
index be19d5a..c3a33ff 100644
--- a/compiler/dex/mir_dataflow.cc
+++ b/compiler/dex/mir_dataflow.cc
@@ -1022,19 +1022,19 @@
if (df_attributes & DF_UA) {
num_uses++;
if (df_attributes & DF_A_WIDE) {
- num_uses ++;
+ num_uses++;
}
}
if (df_attributes & DF_UB) {
num_uses++;
if (df_attributes & DF_B_WIDE) {
- num_uses ++;
+ num_uses++;
}
}
if (df_attributes & DF_UC) {
num_uses++;
if (df_attributes & DF_C_WIDE) {
- num_uses ++;
+ num_uses++;
}
}
}
diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc
index 441445d..5296f30 100644
--- a/compiler/dex/quick/arm/target_arm.cc
+++ b/compiler/dex/quick/arm/target_arm.cc
@@ -315,7 +315,7 @@
fmt++;
DCHECK_LT(fmt, fmt_end);
nc = *fmt++;
- if (nc=='!') {
+ if (nc == '!') {
strcpy(tbuf, "!");
} else {
DCHECK_LT(fmt, fmt_end);
@@ -357,7 +357,7 @@
break;
case 'b':
strcpy(tbuf, "0000");
- for (i=3; i>= 0; i--) {
+ for (i = 3; i >= 0; i--) {
tbuf[i] += operand & 1;
operand >>= 1;
}
diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc
index 305a1479..f2317f3 100644
--- a/compiler/dex/quick/arm/utility_arm.cc
+++ b/compiler/dex/quick/arm/utility_arm.cc
@@ -448,10 +448,10 @@
return NewLIR3(kThumb2RorRRI5, r_dest, r_src1, value);
case kOpAdd:
if (ARM_LOWREG(r_dest) && (r_src1 == r13sp) &&
- (value <= 1020) && ((value & 0x3)==0)) {
+ (value <= 1020) && ((value & 0x3) == 0)) {
return NewLIR3(kThumbAddSpRel, r_dest, r_src1, value >> 2);
} else if (ARM_LOWREG(r_dest) && (r_src1 == r15pc) &&
- (value <= 1020) && ((value & 0x3)==0)) {
+ (value <= 1020) && ((value & 0x3) == 0)) {
return NewLIR3(kThumbAddPcRel, r_dest, r_src1, value >> 2);
}
// Note: intentional fallthrough
diff --git a/compiler/dex/quick/mips/assemble_mips.cc b/compiler/dex/quick/mips/assemble_mips.cc
index dcfb13f..cd25232 100644
--- a/compiler/dex/quick/mips/assemble_mips.cc
+++ b/compiler/dex/quick/mips/assemble_mips.cc
@@ -146,7 +146,7 @@
kFmtUnused, -1, -1, kFmtUnused, -1, -1, kFmtBitBlt, 25, 21,
kFmtBitBlt, 20, 16, IS_QUAD_OP | REG_DEF01 | REG_USE23,
"div", "!2r,!3r", 4),
-#if __mips_isa_rev>=2
+#if __mips_isa_rev >= 2
ENCODING_MAP(kMipsExt, 0x7c000000,
kFmtBitBlt, 20, 16, kFmtBitBlt, 25, 21, kFmtBitBlt, 10, 6,
kFmtBitBlt, 15, 11, IS_QUAD_OP | REG_DEF0 | REG_USE1,
@@ -240,7 +240,7 @@
kFmtBitBlt, 20, 16, kFmtBitBlt, 15, 0, kFmtBitBlt, 25, 21,
kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_USE02 | IS_STORE,
"sb", "!0r,!1d(!2r)", 4),
-#if __mips_isa_rev>=2
+#if __mips_isa_rev >= 2
ENCODING_MAP(kMipsSeb, 0x7c000420,
kFmtBitBlt, 15, 11, kFmtBitBlt, 20, 16, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
diff --git a/compiler/dex/quick/mips/mips_lir.h b/compiler/dex/quick/mips/mips_lir.h
index ce25d73..c3709b7 100644
--- a/compiler/dex/quick/mips/mips_lir.h
+++ b/compiler/dex/quick/mips/mips_lir.h
@@ -323,7 +323,7 @@
kMipsBnez, // bnez s,o [000101] s[25..21] [00000] o[15..0].
kMipsBne, // bne s,t,o [000101] s[25..21] t[20..16] o[15..0].
kMipsDiv, // div s,t [000000] s[25..21] t[20..16] [0000000000011010].
-#if __mips_isa_rev>=2
+#if __mips_isa_rev >= 2
kMipsExt, // ext t,s,p,z [011111] s[25..21] t[20..16] z[15..11] p[10..6] [000000].
#endif
kMipsJal, // jal t [000011] t[25..0].
@@ -348,7 +348,7 @@
kMipsOri, // ori t,s,imm16 [001001] s[25..21] t[20..16] imm16[15..0].
kMipsPref, // pref h,o(b) [101011] b[25..21] h[20..16] o[15..0].
kMipsSb, // sb t,o(b) [101000] b[25..21] t[20..16] o[15..0].
-#if __mips_isa_rev>=2
+#if __mips_isa_rev >= 2
kMipsSeb, // seb d,t [01111100000] t[20..16] d[15..11] [10000100000].
kMipsSeh, // seh d,t [01111100000] t[20..16] d[15..11] [11000100000].
#endif
diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc
index 43e905c..21ba69c 100644
--- a/compiler/dex/quick/mips/target_mips.cc
+++ b/compiler/dex/quick/mips/target_mips.cc
@@ -164,7 +164,7 @@
fmt++;
DCHECK_LT(fmt, fmt_end);
nc = *fmt++;
- if (nc=='!') {
+ if (nc == '!') {
strcpy(tbuf, "!");
} else {
DCHECK_LT(fmt, fmt_end);
@@ -173,7 +173,7 @@
switch (*fmt++) {
case 'b':
strcpy(tbuf, "0000");
- for (i=3; i>= 0; i--) {
+ for (i = 3; i >= 0; i--) {
tbuf[i] += operand & 1;
operand >>= 1;
}
diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc
index 127d191..b7546b7 100644
--- a/compiler/dex/quick/mips/utility_mips.cc
+++ b/compiler/dex/quick/mips/utility_mips.cc
@@ -301,7 +301,7 @@
case kOpXor:
return OpRegRegReg(op, r_dest_src1, r_dest_src1, r_src2);
case kOp2Byte:
-#if __mips_isa_rev>=2
+#if __mips_isa_rev >= 2
res = NewLIR2(kMipsSeb, r_dest_src1, r_src2);
#else
res = OpRegRegImm(kOpLsl, r_dest_src1, r_src2, 24);
@@ -309,7 +309,7 @@
#endif
return res;
case kOp2Short:
-#if __mips_isa_rev>=2
+#if __mips_isa_rev >= 2
res = NewLIR2(kMipsSeh, r_dest_src1, r_src2);
#else
res = OpRegRegImm(kOpLsl, r_dest_src1, r_src2, 16);
diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc
index bc3740a..67989a1 100644
--- a/compiler/dex/quick/ralloc_util.cc
+++ b/compiler/dex/quick/ralloc_util.cc
@@ -28,12 +28,11 @@
* live until it is either explicitly killed or reallocated.
*/
void Mir2Lir::ResetRegPool() {
- int i;
- for (i=0; i < reg_pool_->num_core_regs; i++) {
+ for (int i = 0; i < reg_pool_->num_core_regs; i++) {
if (reg_pool_->core_regs[i].is_temp)
reg_pool_->core_regs[i].in_use = false;
}
- for (i=0; i < reg_pool_->num_fp_regs; i++) {
+ for (int i = 0; i < reg_pool_->num_fp_regs; i++) {
if (reg_pool_->FPRegs[i].is_temp)
reg_pool_->FPRegs[i].in_use = false;
}
@@ -48,8 +47,7 @@
* Note: num_regs may be zero.
*/
void Mir2Lir::CompilerInitPool(RegisterInfo* regs, int* reg_nums, int num) {
- int i;
- for (i=0; i < num; i++) {
+ for (int i = 0; i < num; i++) {
regs[i].reg = reg_nums[i];
regs[i].in_use = false;
regs[i].is_temp = false;
@@ -81,8 +79,7 @@
}
void Mir2Lir::ClobberSRegBody(RegisterInfo* p, int num_regs, int s_reg) {
- int i;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (p[i].s_reg == s_reg) {
if (p[i].is_temp) {
p[i].live = false;
@@ -271,9 +268,8 @@
int Mir2Lir::AllocTempBody(RegisterInfo* p, int num_regs, int* next_temp,
bool required) {
- int i;
int next = *next_temp;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (next >= num_regs)
next = 0;
if (p[next].is_temp && !p[next].in_use && !p[next].live) {
@@ -286,7 +282,7 @@
next++;
}
next = *next_temp;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (next >= num_regs)
next = 0;
if (p[next].is_temp && !p[next].in_use) {
@@ -315,7 +311,7 @@
int next = reg_pool_->next_fp_reg & ~0x1;
// First try to avoid allocating live registers
- for (int i=0; i < num_regs; i+=2) {
+ for (int i = 0; i < num_regs; i+=2) {
if (next >= num_regs)
next = 0;
if ((p[next].is_temp && !p[next].in_use && !p[next].live) &&
@@ -337,7 +333,7 @@
next = reg_pool_->next_fp_reg & ~0x1;
// No choice - find a pair and kill it.
- for (int i=0; i < num_regs; i+=2) {
+ for (int i = 0; i < num_regs; i+=2) {
if (next >= num_regs)
next = 0;
if (p[next].is_temp && !p[next].in_use && p[next+1].is_temp &&
@@ -380,10 +376,9 @@
}
Mir2Lir::RegisterInfo* Mir2Lir::AllocLiveBody(RegisterInfo* p, int num_regs, int s_reg) {
- int i;
if (s_reg == -1)
return NULL;
- for (i=0; i < num_regs; i++) {
+ for (int i = 0; i < num_regs; i++) {
if (p[i].live && (p[i].s_reg == s_reg)) {
if (p[i].is_temp)
p[i].in_use = true;
@@ -419,8 +414,7 @@
void Mir2Lir::FreeTemp(int reg) {
RegisterInfo* p = reg_pool_->core_regs;
int num_regs = reg_pool_->num_core_regs;
- int i;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (p[i].reg == reg) {
if (p[i].is_temp) {
p[i].in_use = false;
@@ -431,7 +425,7 @@
}
p = reg_pool_->FPRegs;
num_regs = reg_pool_->num_fp_regs;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (p[i].reg == reg) {
if (p[i].is_temp) {
p[i].in_use = false;
@@ -446,15 +440,14 @@
Mir2Lir::RegisterInfo* Mir2Lir::IsLive(int reg) {
RegisterInfo* p = reg_pool_->core_regs;
int num_regs = reg_pool_->num_core_regs;
- int i;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (p[i].reg == reg) {
return p[i].live ? &p[i] : NULL;
}
}
p = reg_pool_->FPRegs;
num_regs = reg_pool_->num_fp_regs;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (p[i].reg == reg) {
return p[i].live ? &p[i] : NULL;
}
@@ -485,8 +478,7 @@
void Mir2Lir::LockTemp(int reg) {
RegisterInfo* p = reg_pool_->core_regs;
int num_regs = reg_pool_->num_core_regs;
- int i;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (p[i].reg == reg) {
DCHECK(p[i].is_temp);
p[i].in_use = true;
@@ -496,7 +488,7 @@
}
p = reg_pool_->FPRegs;
num_regs = reg_pool_->num_fp_regs;
- for (i=0; i< num_regs; i++) {
+ for (int i = 0; i< num_regs; i++) {
if (p[i].reg == reg) {
DCHECK(p[i].is_temp);
p[i].in_use = true;
@@ -598,29 +590,26 @@
}
void Mir2Lir::ResetDefTracking() {
- int i;
- for (i=0; i< reg_pool_->num_core_regs; i++) {
+ for (int i = 0; i< reg_pool_->num_core_regs; i++) {
ResetDefBody(®_pool_->core_regs[i]);
}
- for (i=0; i< reg_pool_->num_fp_regs; i++) {
+ for (int i = 0; i< reg_pool_->num_fp_regs; i++) {
ResetDefBody(®_pool_->FPRegs[i]);
}
}
void Mir2Lir::ClobberAllRegs() {
- int i;
- for (i=0; i< reg_pool_->num_core_regs; i++) {
+ for (int i = 0; i< reg_pool_->num_core_regs; i++) {
ClobberBody(®_pool_->core_regs[i]);
}
- for (i=0; i< reg_pool_->num_fp_regs; i++) {
+ for (int i = 0; i< reg_pool_->num_fp_regs; i++) {
ClobberBody(®_pool_->FPRegs[i]);
}
}
// Make sure nothing is live and dirty
void Mir2Lir::FlushAllRegsBody(RegisterInfo* info, int num_regs) {
- int i;
- for (i=0; i < num_regs; i++) {
+ for (int i = 0; i < num_regs; i++) {
if (info[i].live && info[i].dirty) {
if (info[i].pair) {
FlushRegWide(info[i].reg, info[i].partner);
diff --git a/compiler/dex/vreg_analysis.cc b/compiler/dex/vreg_analysis.cc
index f361dd7..a97d1ec 100644
--- a/compiler/dex/vreg_analysis.cc
+++ b/compiler/dex/vreg_analysis.cc
@@ -258,11 +258,11 @@
}
}
- for (int i=0; ssa_rep->fp_use && i< ssa_rep->num_uses; i++) {
+ for (int i = 0; ssa_rep->fp_use && i< ssa_rep->num_uses; i++) {
if (ssa_rep->fp_use[i])
changed |= SetFp(ssa_rep->uses[i], true);
}
- for (int i=0; ssa_rep->fp_def && i< ssa_rep->num_defs; i++) {
+ for (int i = 0; ssa_rep->fp_def && i< ssa_rep->num_defs; i++) {
if (ssa_rep->fp_def[i])
changed |= SetFp(ssa_rep->defs[i], true);
}
@@ -373,13 +373,10 @@
* type inference here.
*/
void MIRGraph::BuildRegLocations() {
- int i;
- RegLocation* loc;
-
/* Allocate the location map */
- loc = static_cast<RegLocation*>(arena_->NewMem(GetNumSSARegs() * sizeof(*loc), true,
- ArenaAllocator::kAllocRegAlloc));
- for (i=0; i < GetNumSSARegs(); i++) {
+ RegLocation* loc = static_cast<RegLocation*>(arena_->NewMem(GetNumSSARegs() * sizeof(*loc), true,
+ ArenaAllocator::kAllocRegAlloc));
+ for (int i = 0; i < GetNumSSARegs(); i++) {
loc[i] = fresh_loc;
loc[i].s_reg_low = i;
loc[i].is_const = is_constant_v_->IsBitSet(i);
@@ -388,7 +385,7 @@
/* Patch up the locations for Method* and the compiler temps */
loc[method_sreg_].location = kLocCompilerTemp;
loc[method_sreg_].defined = true;
- for (i = 0; i < cu_->num_compiler_temps; i++) {
+ for (int i = 0; i < cu_->num_compiler_temps; i++) {
CompilerTemp* ct = compiler_temps_.Get(i);
loc[ct->s_reg].location = kLocCompilerTemp;
loc[ct->s_reg].defined = true;
@@ -458,7 +455,7 @@
* base Dalvik virtual register. Once we add a better register
* allocator, remove this remapping.
*/
- for (i=0; i < GetNumSSARegs(); i++) {
+ for (int i = 0; i < GetNumSSARegs(); i++) {
if (reg_location_[i].location != kLocCompilerTemp) {
int orig_sreg = reg_location_[i].s_reg_low;
reg_location_[i].orig_sreg = orig_sreg;
diff --git a/runtime/atomic_integer.h b/runtime/atomic_integer.h
index 05024b4..f31e166 100644
--- a/runtime/atomic_integer.h
+++ b/runtime/atomic_integer.h
@@ -58,11 +58,11 @@
return android_atomic_and(-value, &value_);
}
- int32_t operator ++ () {
+ int32_t operator++ () {
return android_atomic_inc(&value_) + 1;
}
- int32_t operator -- () {
+ int32_t operator-- () {
return android_atomic_dec(&value_) - 1;
}
diff --git a/runtime/jdwp/jdwp_event.cc b/runtime/jdwp/jdwp_event.cc
index 77434e1..52dd782 100644
--- a/runtime/jdwp/jdwp_event.cc
+++ b/runtime/jdwp/jdwp_event.cc
@@ -1070,7 +1070,7 @@
Thread* self = Thread::Current();
bool safe_to_release_mutator_lock_over_send = !Locks::mutator_lock_->IsExclusiveHeld(self);
if (safe_to_release_mutator_lock_over_send) {
- for (size_t i=0; i < kMutatorLock; ++i) {
+ for (size_t i = 0; i < kMutatorLock; ++i) {
if (self->GetHeldMutex(static_cast<LockLevel>(i)) != NULL) {
safe_to_release_mutator_lock_over_send = false;
break;
