Continuing Quick compiler refactoring
With this CL, we no longer include any .cc files - all source
files compile stand-alone. We still build a separate .so for
each target, but all code in the target-independent "codegen"
directory is now truly independent and doesn't rely on any
target-specific macros to compile.
Header file inclusion is still a bit of a mess, but that will be
addressed in a subsequent CL.
Next up: create a codegen class to hold code generator routines
overrideable by target.
Change-Id: I3a93118d11afeab11f310950a6a73381a99e26e1
diff --git a/build/Android.libart-compiler-llvm.mk b/build/Android.libart-compiler-llvm.mk
index a36962d..b278310 100644
--- a/build/Android.libart-compiler-llvm.mk
+++ b/build/Android.libart-compiler-llvm.mk
@@ -37,25 +37,35 @@
ifeq ($(ART_USE_PORTABLE_COMPILER),true)
LIBART_COMPILER_LLVM_SRC_FILES += \
- src/compiler/dataflow.cc \
- src/compiler/frontend.cc \
- src/compiler/intermediate_rep.cc \
- src/compiler/ralloc.cc \
- src/compiler/ssa_transformation.cc \
- src/compiler/compiler_utility.cc \
- src/compiler/codegen/ralloc_util.cc \
- src/compiler/codegen/arm/target_arm.cc \
- src/compiler/codegen/arm/assemble_arm.cc \
- src/compiler/codegen/arm/backend_arm.cc \
- src/compiler_llvm/dalvik_reg.cc \
- src/compiler_llvm/gbc_expander.cc \
- src/compiler_llvm/method_compiler.cc \
- src/greenland/intrinsic_helper.cc \
- src/greenland/ir_builder.cc
+ src/compiler/dataflow.cc \
+ src/compiler/frontend.cc \
+ src/compiler/intermediate_rep.cc \
+ src/compiler/ralloc.cc \
+ src/compiler/ssa_transformation.cc \
+ src/compiler/compiler_utility.cc \
+ src/compiler/codegen/ralloc_util.cc \
+ src/compiler/codegen/codegen_util.cc \
+ src/compiler/codegen/gen_loadstore.cc \
+ src/compiler/codegen/gen_common.cc \
+ src/compiler/codegen/gen_invoke.cc \
+ src/compiler/codegen/method_bitcode.cc \
+ src/compiler/codegen/method_codegen_driver.cc \
+ src/compiler/codegen/local_optimizations.cc \
+ src/compiler/codegen/arm/target_arm.cc \
+ src/compiler/codegen/arm/assemble_arm.cc \
+ src/compiler/codegen/arm/utility_arm.cc \
+ src/compiler/codegen/arm/call_arm.cc \
+ src/compiler/codegen/arm/fp_arm.cc \
+ src/compiler/codegen/arm/int_arm.cc \
+ src/compiler_llvm/dalvik_reg.cc \
+ src/compiler_llvm/gbc_expander.cc \
+ src/compiler_llvm/method_compiler.cc \
+ src/greenland/intrinsic_helper.cc \
+ src/greenland/ir_builder.cc
else
LIBART_COMPILER_LLVM_SRC_FILES += \
- src/compiler_llvm/dalvik_reg.cc \
- src/compiler_llvm/method_compiler.cc
+ src/compiler_llvm/dalvik_reg.cc \
+ src/compiler_llvm/method_compiler.cc
endif
# $(1): target or host
diff --git a/build/Android.libart-compiler.mk b/build/Android.libart-compiler.mk
index f94b8b6..c940a42 100644
--- a/build/Android.libart-compiler.mk
+++ b/build/Android.libart-compiler.mk
@@ -22,6 +22,13 @@
src/compiler/ssa_transformation.cc \
src/compiler/compiler_utility.cc \
src/compiler/codegen/ralloc_util.cc \
+ src/compiler/codegen/codegen_util.cc \
+ src/compiler/codegen/gen_loadstore.cc \
+ src/compiler/codegen/gen_common.cc \
+ src/compiler/codegen/gen_invoke.cc \
+ src/compiler/codegen/method_bitcode.cc \
+ src/compiler/codegen/method_codegen_driver.cc \
+ src/compiler/codegen/local_optimizations.cc \
src/oat/jni/calling_convention.cc \
src/oat/jni/jni_compiler.cc \
src/oat/jni/arm/calling_convention_arm.cc \
@@ -34,21 +41,30 @@
$(LIBART_COMPILER_COMMON_SRC_FILES) \
src/compiler/codegen/arm/target_arm.cc \
src/compiler/codegen/arm/assemble_arm.cc \
- src/compiler/codegen/arm/backend_arm.cc \
+ src/compiler/codegen/arm/utility_arm.cc \
+ src/compiler/codegen/arm/call_arm.cc \
+ src/compiler/codegen/arm/fp_arm.cc \
+ src/compiler/codegen/arm/int_arm.cc \
src/oat/jni/arm/jni_internal_arm.cc
LIBART_COMPILER_mips_SRC_FILES += \
$(LIBART_COMPILER_COMMON_SRC_FILES) \
src/compiler/codegen/mips/target_mips.cc \
src/compiler/codegen/mips/assemble_mips.cc \
- src/compiler/codegen/mips/backend_mips.cc \
+ src/compiler/codegen/mips/utility_mips.cc \
+ src/compiler/codegen/mips/call_mips.cc \
+ src/compiler/codegen/mips/fp_mips.cc \
+ src/compiler/codegen/mips/int_mips.cc \
src/oat/jni/mips/jni_internal_mips.cc
LIBART_COMPILER_x86_SRC_FILES += \
$(LIBART_COMPILER_COMMON_SRC_FILES) \
src/compiler/codegen/x86/target_x86.cc \
src/compiler/codegen/x86/assemble_x86.cc \
- src/compiler/codegen/x86/backend_x86.cc \
+ src/compiler/codegen/x86/utility_x86.cc \
+ src/compiler/codegen/x86/call_x86.cc \
+ src/compiler/codegen/x86/fp_x86.cc \
+ src/compiler/codegen/x86/int_x86.cc \
src/oat/jni/x86/jni_internal_x86.cc
# $(1): target or host
diff --git a/src/compiler/codegen/arm/arm_lir.h b/src/compiler/codegen/arm/arm_lir.h
index a3c4ca1..bc3277f 100644
--- a/src/compiler/codegen/arm/arm_lir.h
+++ b/src/compiler/codegen/arm/arm_lir.h
@@ -232,8 +232,6 @@
kArmRor = 0x3
};
-#define isPseudoOpcode(opcode) (static_cast<int>(opcode) < 0)
-
/*
* The following enum defines the list of supported Thumb instructions by the
* assembler. Their corresponding EncodingMap positions will be defined in
diff --git a/src/compiler/codegen/arm/backend_arm.cc b/src/compiler/codegen/arm/backend_arm.cc
deleted file mode 100644
index 47d1967..0000000
--- a/src/compiler/codegen/arm/backend_arm.cc
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2011 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#define _CODEGEN_C
-#define _ARMV7_A
-
-#include "arm_lir.h"
-#include "../ralloc_util.h"
-
-/* Common codegen utility code */
-#include "../codegen_util.cc"
-
-#include "utility_arm.cc"
-#include "../gen_loadstore.cc"
-#include "../gen_common.cc"
-#include "../gen_invoke.cc"
-#include "call_arm.cc"
-#include "fp_arm.cc"
-#include "int_arm.cc"
-
-/* Bitcode conversion */
-#include "../method_bitcode.cc"
-
-/* MIR2LIR dispatcher and architectural independent codegen routines */
-#include "../method_codegen_driver.cc"
-
-/* Target-independent local optimizations */
-#include "../local_optimizations.cc"
diff --git a/src/compiler/codegen/arm/call_arm.cc b/src/compiler/codegen/arm/call_arm.cc
index acf825a..0964226 100644
--- a/src/compiler/codegen/arm/call_arm.cc
+++ b/src/compiler/codegen/arm/call_arm.cc
@@ -18,6 +18,9 @@
#include "oat_compilation_unit.h"
#include "oat/runtime/oat_support_entrypoints.h"
+#include "arm_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
namespace art {
@@ -504,7 +507,7 @@
oatClobberCalleeSave(cUnit);
LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
markSafepointPC(cUnit, callInst);
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kLoadLoad);
}
/*
@@ -536,7 +539,7 @@
oatClobberCalleeSave(cUnit);
LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
markSafepointPC(cUnit, callInst);
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kStoreLoad);
}
/*
diff --git a/src/compiler/codegen/arm/fp_arm.cc b/src/compiler/codegen/arm/fp_arm.cc
index 70783a4..3b0d540 100644
--- a/src/compiler/codegen/arm/fp_arm.cc
+++ b/src/compiler/codegen/arm/fp_arm.cc
@@ -14,6 +14,10 @@
* limitations under the License.
*/
+#include "arm_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
+
namespace art {
bool genArithOpFloat(CompilationUnit* cUnit, Instruction::Code opcode, RegLocation rlDest,
diff --git a/src/compiler/codegen/arm/int_arm.cc b/src/compiler/codegen/arm/int_arm.cc
index 159b329..f54c58c 100644
--- a/src/compiler/codegen/arm/int_arm.cc
+++ b/src/compiler/codegen/arm/int_arm.cc
@@ -18,6 +18,9 @@
#include "oat_compilation_unit.h"
#include "oat/runtime/oat_support_entrypoints.h"
+#include "arm_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
namespace art {
@@ -378,8 +381,8 @@
RegLocation rlDest = inlineTarget(cUnit, info); // boolean place for result
- // Release store semantics, get the barrier out of the way.
- oatGenMemBarrier(cUnit, kSY);
+ // Release store semantics, get the barrier out of the way. TODO: revisit
+ oatGenMemBarrier(cUnit, kStoreLoad);
RegLocation rlObject = loadValue(cUnit, rlSrcObj, kCoreReg);
RegLocation rlNewValue = loadValue(cUnit, rlSrcNewValue, kCoreReg);
@@ -474,10 +477,22 @@
return opCondBranch(cUnit, cCode, target);
}
-void oatGenMemBarrier(CompilationUnit* cUnit, int barrierKind)
+void oatGenMemBarrier(CompilationUnit* cUnit, MemBarrierKind barrierKind)
{
#if ANDROID_SMP != 0
- LIR* dmb = newLIR1(cUnit, kThumb2Dmb, barrierKind);
+ int dmbFlavor;
+ // TODO: revisit Arm barrier kinds
+ switch (barrierKind) {
+ case kLoadStore: dmbFlavor = kSY; break;
+ case kLoadLoad: dmbFlavor = kSY; break;
+ case kStoreStore: dmbFlavor = kST; break;
+ case kStoreLoad: dmbFlavor = kSY; break;
+ default:
+ LOG(FATAL) << "Unexpected MemBarrierKind: " << barrierKind;
+ dmbFlavor = kSY; // quiet gcc.
+ break;
+ }
+ LIR* dmb = newLIR1(cUnit, kThumb2Dmb, dmbFlavor);
dmb->defMask = ENCODE_ALL;
#endif
}
diff --git a/src/compiler/codegen/arm/target_arm.cc b/src/compiler/codegen/arm/target_arm.cc
index 6640707..aa67be1 100644
--- a/src/compiler/codegen/arm/target_arm.cc
+++ b/src/compiler/codegen/arm/target_arm.cc
@@ -802,4 +802,19 @@
return rARM_LR;
}
+uint64_t getTargetInstFlags(int opcode)
+{
+ return EncodingMap[opcode].flags;
+}
+
+const char* getTargetInstName(int opcode)
+{
+ return EncodingMap[opcode].name;
+}
+
+const char* getTargetInstFmt(int opcode)
+{
+ return EncodingMap[opcode].fmt;
+}
+
} // namespace art
diff --git a/src/compiler/codegen/arm/utility_arm.cc b/src/compiler/codegen/arm/utility_arm.cc
index 1873c2a..35f4a2d 100644
--- a/src/compiler/codegen/arm/utility_arm.cc
+++ b/src/compiler/codegen/arm/utility_arm.cc
@@ -14,6 +14,10 @@
* limitations under the License.
*/
+#include "arm_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
+
namespace art {
/* This file contains codegen for the Thumb ISA. */
diff --git a/src/compiler/codegen/codegen_util.cc b/src/compiler/codegen/codegen_util.cc
index 5da552c..c6c8af1 100644
--- a/src/compiler/codegen/codegen_util.cc
+++ b/src/compiler/codegen/codegen_util.cc
@@ -14,9 +14,11 @@
* limitations under the License.
*/
+#include "../compiler_internals.h"
#include "gc_map.h"
#include "verifier/dex_gc_map.h"
#include "verifier/method_verifier.h"
+#include "ralloc_util.h"
#include "codegen_util.h"
namespace art {
@@ -31,7 +33,7 @@
{
uint64_t *maskPtr;
uint64_t mask = ENCODE_MEM;;
- DCHECK(EncodingMap[lir->opcode].flags & (IS_LOAD | IS_STORE));
+ DCHECK(getTargetInstFlags(lir->opcode) & (IS_LOAD | IS_STORE));
if (isLoad) {
maskPtr = &lir->useMask;
} else {
@@ -53,7 +55,7 @@
break;
case kMustNotAlias:
/* Currently only loads can be marked as kMustNotAlias */
- DCHECK(!(EncodingMap[lir->opcode].flags & IS_STORE));
+ DCHECK(!(getTargetInstFlags(lir->opcode) & IS_STORE));
*maskPtr |= ENCODE_MUST_NOT_ALIAS;
break;
default:
@@ -106,7 +108,7 @@
return;
}
- uint64_t flags = EncodingMap[opcode].flags;
+ uint64_t flags = getTargetInstFlags(opcode);
if (flags & NEEDS_FIXUP) {
lir->flags.pcRelFixup = true;
@@ -237,10 +239,10 @@
if (lir->flags.isNop && !dumpNop) {
break;
} else {
- std::string op_name(buildInsnString(EncodingMap[lir->opcode].name,
+ std::string op_name(buildInsnString(getTargetInstName(lir->opcode),
lir, baseAddr));
- std::string op_operands(buildInsnString(EncodingMap[lir->opcode].fmt
- , lir, baseAddr));
+ std::string op_operands(buildInsnString(getTargetInstFmt(lir->opcode),
+ lir, baseAddr));
LOG(INFO) << StringPrintf("%05x: %-9s%s%s",
reinterpret_cast<unsigned int>(baseAddr + offset),
op_name.c_str(), op_operands.c_str(),
@@ -368,8 +370,8 @@
*/
LIR* newLIR0(CompilationUnit* cUnit, int opcode)
{
- DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND))
- << EncodingMap[opcode].name << " " << opcode << " "
+ DCHECK(isPseudoOpcode(opcode) || (getTargetInstFlags(opcode) & NO_OPERAND))
+ << getTargetInstName(opcode) << " " << opcode << " "
<< PrettyMethod(cUnit->method_idx, *cUnit->dex_file) << " "
<< cUnit->currentDalvikOffset;
LIR* insn = rawLIR(cUnit, cUnit->currentDalvikOffset, opcode);
@@ -380,8 +382,8 @@
LIR* newLIR1(CompilationUnit* cUnit, int opcode,
int dest)
{
- DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_UNARY_OP))
- << EncodingMap[opcode].name << " " << opcode << " "
+ DCHECK(isPseudoOpcode(opcode) || (getTargetInstFlags(opcode) & IS_UNARY_OP))
+ << getTargetInstName(opcode) << " " << opcode << " "
<< PrettyMethod(cUnit->method_idx, *cUnit->dex_file) << " "
<< cUnit->currentDalvikOffset;
LIR* insn = rawLIR(cUnit, cUnit->currentDalvikOffset, opcode, dest);
@@ -392,8 +394,8 @@
LIR* newLIR2(CompilationUnit* cUnit, int opcode,
int dest, int src1)
{
- DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_BINARY_OP))
- << EncodingMap[opcode].name << " " << opcode << " "
+ DCHECK(isPseudoOpcode(opcode) || (getTargetInstFlags(opcode) & IS_BINARY_OP))
+ << getTargetInstName(opcode) << " " << opcode << " "
<< PrettyMethod(cUnit->method_idx, *cUnit->dex_file) << " "
<< cUnit->currentDalvikOffset;
LIR* insn = rawLIR(cUnit, cUnit->currentDalvikOffset, opcode, dest, src1);
@@ -404,8 +406,8 @@
LIR* newLIR3(CompilationUnit* cUnit, int opcode,
int dest, int src1, int src2)
{
- DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_TERTIARY_OP))
- << EncodingMap[opcode].name << " " << opcode << " "
+ DCHECK(isPseudoOpcode(opcode) || (getTargetInstFlags(opcode) & IS_TERTIARY_OP))
+ << getTargetInstName(opcode) << " " << opcode << " "
<< PrettyMethod(cUnit->method_idx, *cUnit->dex_file) << " "
<< cUnit->currentDalvikOffset;
LIR* insn = rawLIR(cUnit, cUnit->currentDalvikOffset, opcode, dest, src1, src2);
@@ -416,8 +418,8 @@
LIR* newLIR4(CompilationUnit* cUnit, int opcode,
int dest, int src1, int src2, int info)
{
- DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_QUAD_OP))
- << EncodingMap[opcode].name << " " << opcode << " "
+ DCHECK(isPseudoOpcode(opcode) || (getTargetInstFlags(opcode) & IS_QUAD_OP))
+ << getTargetInstName(opcode) << " " << opcode << " "
<< PrettyMethod(cUnit->method_idx, *cUnit->dex_file) << " "
<< cUnit->currentDalvikOffset;
LIR* insn = rawLIR(cUnit, cUnit->currentDalvikOffset, opcode, dest, src1, src2, info);
@@ -428,8 +430,8 @@
LIR* newLIR5(CompilationUnit* cUnit, int opcode,
int dest, int src1, int src2, int info1, int info2)
{
- DCHECK(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_QUIN_OP))
- << EncodingMap[opcode].name << " " << opcode << " "
+ DCHECK(isPseudoOpcode(opcode) || (getTargetInstFlags(opcode) & IS_QUIN_OP))
+ << getTargetInstName(opcode) << " " << opcode << " "
<< PrettyMethod(cUnit->method_idx, *cUnit->dex_file) << " "
<< cUnit->currentDalvikOffset;
LIR* insn = rawLIR(cUnit, cUnit->currentDalvikOffset, opcode, dest, src1, src2, info1, info2);
diff --git a/src/compiler/codegen/gen_common.cc b/src/compiler/codegen/gen_common.cc
index c548376..649ae82 100644
--- a/src/compiler/codegen/gen_common.cc
+++ b/src/compiler/codegen/gen_common.cc
@@ -15,6 +15,9 @@
*/
#include "oat/runtime/oat_support_entrypoints.h"
+#include "../compiler_ir.h"
+#include "ralloc_util.h"
+#include "codegen_util.h"
namespace art {
@@ -610,9 +613,8 @@
} else {
rlSrc = loadValue(cUnit, rlSrc, kAnyReg);
}
-//FIXME: need to generalize the barrier call
if (isVolatile) {
- oatGenMemBarrier(cUnit, kST);
+ oatGenMemBarrier(cUnit, kStoreStore);
}
if (isLongOrDouble) {
storeBaseDispWide(cUnit, rBase, fieldOffset, rlSrc.lowReg,
@@ -621,7 +623,7 @@
storeWordDisp(cUnit, rBase, fieldOffset, rlSrc.lowReg);
}
if (isVolatile) {
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kStoreLoad);
}
if (isObject) {
markGCCard(cUnit, rlSrc.lowReg, rBase);
@@ -698,7 +700,7 @@
// rBase now holds static storage base
RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kAnyReg, true);
if (isVolatile) {
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kLoadLoad);
}
if (isLongOrDouble) {
loadBaseDispWide(cUnit, rBase, fieldOffset, rlResult.lowReg,
@@ -894,7 +896,7 @@
loadBaseDispWide(cUnit, rlObj.lowReg, fieldOffset, rlResult.lowReg,
rlResult.highReg, rlObj.sRegLow);
if (isVolatile) {
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kLoadLoad);
}
} else {
int regPtr = oatAllocTemp(cUnit);
@@ -902,7 +904,7 @@
rlResult = oatEvalLoc(cUnit, rlDest, regClass, true);
loadPair(cUnit, regPtr, rlResult.lowReg, rlResult.highReg);
if (isVolatile) {
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kLoadLoad);
}
oatFreeTemp(cUnit, regPtr);
}
@@ -913,7 +915,7 @@
loadBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlResult.lowReg,
kWord, rlObj.sRegLow);
if (isVolatile) {
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kLoadLoad);
}
storeValue(cUnit, rlDest, rlResult);
}
@@ -951,22 +953,22 @@
regPtr = oatAllocTemp(cUnit);
opRegRegImm(cUnit, kOpAdd, regPtr, rlObj.lowReg, fieldOffset);
if (isVolatile) {
- oatGenMemBarrier(cUnit, kST);
+ oatGenMemBarrier(cUnit, kStoreStore);
}
storeBaseDispWide(cUnit, regPtr, 0, rlSrc.lowReg, rlSrc.highReg);
if (isVolatile) {
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kLoadLoad);
}
oatFreeTemp(cUnit, regPtr);
} else {
rlSrc = loadValue(cUnit, rlSrc, regClass);
genNullCheck(cUnit, rlObj.sRegLow, rlObj.lowReg, optFlags);
if (isVolatile) {
- oatGenMemBarrier(cUnit, kST);
+ oatGenMemBarrier(cUnit, kStoreStore);
}
storeBaseDisp(cUnit, rlObj.lowReg, fieldOffset, rlSrc.lowReg, kWord);
if (isVolatile) {
- oatGenMemBarrier(cUnit, kSY);
+ oatGenMemBarrier(cUnit, kLoadLoad);
}
if (isObject) {
markGCCard(cUnit, rlSrc.lowReg, rlObj.lowReg);
diff --git a/src/compiler/codegen/gen_invoke.cc b/src/compiler/codegen/gen_invoke.cc
index fbab59f..90fc14b 100644
--- a/src/compiler/codegen/gen_invoke.cc
+++ b/src/compiler/codegen/gen_invoke.cc
@@ -15,6 +15,9 @@
*/
#include "oat/runtime/oat_support_entrypoints.h"
+#include "../compiler_ir.h"
+#include "ralloc_util.h"
+#include "codegen_util.h"
namespace art {
@@ -999,5 +1002,157 @@
return false;
}
+void genInvoke(CompilationUnit* cUnit, CallInfo* info)
+{
+ if (genIntrinsic(cUnit, info)) {
+ return;
+ }
+ InvokeType originalType = info->type; // avoiding mutation by ComputeInvokeInfo
+ int callState = 0;
+ LIR* nullCk;
+ LIR** pNullCk = NULL;
+ NextCallInsn nextCallInsn;
+ oatFlushAllRegs(cUnit); /* Everything to home location */
+ // Explicit register usage
+ oatLockCallTemps(cUnit);
+
+ OatCompilationUnit mUnit(cUnit->class_loader, cUnit->class_linker,
+ *cUnit->dex_file,
+ cUnit->code_item, cUnit->method_idx,
+ cUnit->access_flags);
+
+ uint32_t dexMethodIdx = info->index;
+ int vtableIdx;
+ uintptr_t directCode;
+ uintptr_t directMethod;
+ bool skipThis;
+ bool fastPath =
+ cUnit->compiler->ComputeInvokeInfo(dexMethodIdx, &mUnit, info->type,
+ vtableIdx, directCode,
+ directMethod)
+ && !SLOW_INVOKE_PATH;
+ if (info->type == kInterface) {
+ if (fastPath) {
+ pNullCk = &nullCk;
+ }
+ nextCallInsn = fastPath ? nextInterfaceCallInsn
+ : nextInterfaceCallInsnWithAccessCheck;
+ skipThis = false;
+ } else if (info->type == kDirect) {
+ if (fastPath) {
+ pNullCk = &nullCk;
+ }
+ nextCallInsn = fastPath ? nextSDCallInsn : nextDirectCallInsnSP;
+ skipThis = false;
+ } else if (info->type == kStatic) {
+ nextCallInsn = fastPath ? nextSDCallInsn : nextStaticCallInsnSP;
+ skipThis = false;
+ } else if (info->type == kSuper) {
+ DCHECK(!fastPath); // Fast path is a direct call.
+ nextCallInsn = nextSuperCallInsnSP;
+ skipThis = false;
+ } else {
+ DCHECK_EQ(info->type, kVirtual);
+ nextCallInsn = fastPath ? nextVCallInsn : nextVCallInsnSP;
+ skipThis = fastPath;
+ }
+ if (!info->isRange) {
+ callState = genDalvikArgsNoRange(cUnit, info, callState, pNullCk,
+ nextCallInsn, dexMethodIdx,
+ vtableIdx, directCode, directMethod,
+ originalType, skipThis);
+ } else {
+ callState = genDalvikArgsRange(cUnit, info, callState, pNullCk,
+ nextCallInsn, dexMethodIdx, vtableIdx,
+ directCode, directMethod, originalType,
+ skipThis);
+ }
+ // Finish up any of the call sequence not interleaved in arg loading
+ while (callState >= 0) {
+ callState = nextCallInsn(cUnit, info, callState, dexMethodIdx,
+ vtableIdx, directCode, directMethod,
+ originalType);
+ }
+ if (cUnit->enableDebug & (1 << kDebugDisplayMissingTargets)) {
+ genShowTarget(cUnit);
+ }
+ LIR* callInst;
+ if (cUnit->instructionSet != kX86) {
+ callInst = opReg(cUnit, kOpBlx, targetReg(kInvokeTgt));
+ } else {
+ if (fastPath && info->type != kInterface) {
+ callInst = opMem(cUnit, kOpBlx, targetReg(kArg0),
+ AbstractMethod::GetCodeOffset().Int32Value());
+ } else {
+ int trampoline = 0;
+ switch (info->type) {
+ case kInterface:
+ trampoline = fastPath ? ENTRYPOINT_OFFSET(pInvokeInterfaceTrampoline)
+ : ENTRYPOINT_OFFSET(pInvokeInterfaceTrampolineWithAccessCheck);
+ break;
+ case kDirect:
+ trampoline = ENTRYPOINT_OFFSET(pInvokeDirectTrampolineWithAccessCheck);
+ break;
+ case kStatic:
+ trampoline = ENTRYPOINT_OFFSET(pInvokeStaticTrampolineWithAccessCheck);
+ break;
+ case kSuper:
+ trampoline = ENTRYPOINT_OFFSET(pInvokeSuperTrampolineWithAccessCheck);
+ break;
+ case kVirtual:
+ trampoline = ENTRYPOINT_OFFSET(pInvokeVirtualTrampolineWithAccessCheck);
+ break;
+ default:
+ LOG(FATAL) << "Unexpected invoke type";
+ }
+ callInst = opThreadMem(cUnit, kOpBlx, trampoline);
+ }
+ }
+ markSafepointPC(cUnit, callInst);
+
+ oatClobberCalleeSave(cUnit);
+ if (info->result.location != kLocInvalid) {
+ // We have a following MOVE_RESULT - do it now.
+ if (info->result.wide) {
+ RegLocation retLoc = oatGetReturnWide(cUnit, info->result.fp);
+ storeValueWide(cUnit, info->result, retLoc);
+ } else {
+ RegLocation retLoc = oatGetReturn(cUnit, info->result.fp);
+ storeValue(cUnit, info->result, retLoc);
+ }
+ }
+}
+
+/*
+ * Build an array of location records for the incoming arguments.
+ * Note: one location record per word of arguments, with dummy
+ * high-word loc for wide arguments. Also pull up any following
+ * MOVE_RESULT and incorporate it into the invoke.
+ */
+CallInfo* oatNewCallInfo(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
+ InvokeType type, bool isRange)
+{
+ CallInfo* info = static_cast<CallInfo*>(oatNew(cUnit, sizeof(CallInfo), true, kAllocMisc));
+ MIR* moveResultMIR = oatFindMoveResult(cUnit, bb, mir);
+ if (moveResultMIR == NULL) {
+ info->result.location = kLocInvalid;
+ } else {
+ info->result = oatGetRawDest(cUnit, moveResultMIR);
+ moveResultMIR->dalvikInsn.opcode = Instruction::NOP;
+ }
+ info->numArgWords = mir->ssaRep->numUses;
+ info->args = (info->numArgWords == 0) ? NULL : static_cast<RegLocation*>
+ (oatNew(cUnit, sizeof(RegLocation) * info->numArgWords, false, kAllocMisc));
+ for (int i = 0; i < info->numArgWords; i++) {
+ info->args[i] = oatGetRawSrc(cUnit, mir, i);
+ }
+ info->optFlags = mir->optimizationFlags;
+ info->type = type;
+ info->isRange = isRange;
+ info->index = mir->dalvikInsn.vB;
+ info->offset = mir->offset;
+ return info;
+}
+
} // namespace art
diff --git a/src/compiler/codegen/gen_invoke.h b/src/compiler/codegen/gen_invoke.h
index d4a348c..ffff0b8 100644
--- a/src/compiler/codegen/gen_invoke.h
+++ b/src/compiler/codegen/gen_invoke.h
@@ -35,5 +35,7 @@
bool genInlinedIndexOf(CompilationUnit* cUnit, CallInfo* info, bool zeroBased);
bool genInlinedStringCompareTo(CompilationUnit* cUnit, CallInfo* info);
bool genIntrinsic(CompilationUnit* cUnit, CallInfo* info);
+void genInvoke(CompilationUnit* cUnit, CallInfo* info);
+CallInfo* oatNewCallInfo(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir, InvokeType type, bool isRange);
#endif // ART_SRC_COMPILER_CODEGEN_GENINVOKE_H_
diff --git a/src/compiler/codegen/gen_loadstore.cc b/src/compiler/codegen/gen_loadstore.cc
index b5802ae..996b5b7 100644
--- a/src/compiler/codegen/gen_loadstore.cc
+++ b/src/compiler/codegen/gen_loadstore.cc
@@ -14,6 +14,10 @@
* limitations under the License.
*/
+#include "../compiler_ir.h"
+#include "ralloc_util.h"
+#include "codegen_util.h"
+
namespace art {
/* This file contains target-independent codegen and support. */
diff --git a/src/compiler/codegen/local_optimizations.cc b/src/compiler/codegen/local_optimizations.cc
index 03f9463..7956c05 100644
--- a/src/compiler/codegen/local_optimizations.cc
+++ b/src/compiler/codegen/local_optimizations.cc
@@ -14,6 +14,8 @@
* limitations under the License.
*/
+#include "../compiler_internals.h"
+
namespace art {
#define DEBUG_OPT(X)
@@ -86,20 +88,20 @@
/* Skip non-interesting instructions */
if ((thisLIR->flags.isNop == true) ||
isPseudoOpcode(thisLIR->opcode) ||
- (EncodingMap[thisLIR->opcode].flags & IS_BRANCH) ||
- !(EncodingMap[thisLIR->opcode].flags & (IS_LOAD | IS_STORE))) {
+ (getTargetInstFlags(thisLIR->opcode) & IS_BRANCH) ||
+ !(getTargetInstFlags(thisLIR->opcode) & (IS_LOAD | IS_STORE))) {
continue;
}
int nativeRegId;
if (cUnit->instructionSet == kX86) {
// If x86, location differs depending on whether memory/reg operation.
- nativeRegId = (EncodingMap[thisLIR->opcode].flags & IS_STORE) ? thisLIR->operands[2]
+ nativeRegId = (getTargetInstFlags(thisLIR->opcode) & IS_STORE) ? thisLIR->operands[2]
: thisLIR->operands[0];
} else {
nativeRegId = thisLIR->operands[0];
}
- bool isThisLIRLoad = EncodingMap[thisLIR->opcode].flags & IS_LOAD;
+ bool isThisLIRLoad = getTargetInstFlags(thisLIR->opcode) & IS_LOAD;
LIR* checkLIR;
/* Use the mem mask to determine the rough memory location */
uint64_t thisMemMask = (thisLIR->useMask | thisLIR->defMask) & ENCODE_MEM;
@@ -142,13 +144,13 @@
* Potential aliases seen - check the alias relations
*/
if (checkMemMask != ENCODE_MEM && aliasCondition != 0) {
- bool isCheckLIRLoad = EncodingMap[checkLIR->opcode].flags & IS_LOAD;
+ bool isCheckLIRLoad = getTargetInstFlags(checkLIR->opcode) & IS_LOAD;
if (aliasCondition == ENCODE_LITERAL) {
/*
* Should only see literal loads in the instruction
* stream.
*/
- DCHECK(!(EncodingMap[checkLIR->opcode].flags & IS_STORE));
+ DCHECK(!(getTargetInstFlags(checkLIR->opcode) & IS_STORE));
/* Same value && same register type */
if (checkLIR->aliasInfo == thisLIR->aliasInfo &&
sameRegType(checkLIR->operands[0], nativeRegId)) {
@@ -231,7 +233,7 @@
if (cUnit->instructionSet == kX86) {
// Prevent stores from being sunk between ops that generate ccodes and
// ops that use them.
- uint64_t flags = EncodingMap[checkLIR->opcode].flags;
+ uint64_t flags = getTargetInstFlags(checkLIR->opcode);
if (sinkDistance > 0 && (flags & IS_BRANCH) && (flags & USES_CCODES)) {
checkLIR = PREV_LIR(checkLIR);
sinkDistance--;
@@ -282,7 +284,7 @@
/* Skip non-interesting instructions */
if ((thisLIR->flags.isNop == true) ||
isPseudoOpcode(thisLIR->opcode) ||
- !(EncodingMap[thisLIR->opcode].flags & IS_LOAD)) {
+ !(getTargetInstFlags(thisLIR->opcode) & IS_LOAD)) {
continue;
}
@@ -382,7 +384,7 @@
LIR* depLIR = prevInstList[nextSlot-1];
/* If there is ld-ld dependency, wait LDLD_DISTANCE cycles */
if (!isPseudoOpcode(depLIR->opcode) &&
- (EncodingMap[depLIR->opcode].flags & IS_LOAD)) {
+ (getTargetInstFlags(depLIR->opcode) & IS_LOAD)) {
firstSlot -= LDLD_DISTANCE;
}
/*
@@ -399,7 +401,7 @@
* If the first instruction is a load, don't hoist anything
* above it since it is unlikely to be beneficial.
*/
- if (EncodingMap[curLIR->opcode].flags & IS_LOAD) continue;
+ if (getTargetInstFlags(curLIR->opcode) & IS_LOAD) continue;
/*
* If the remaining number of slots is less than LD_LATENCY,
* insert the hoisted load here.
@@ -419,7 +421,7 @@
* the remaining instructions are less than LD_LATENCY.
*/
bool prevIsLoad = isPseudoOpcode(prevLIR->opcode) ? false :
- (EncodingMap[prevLIR->opcode].flags & IS_LOAD);
+ (getTargetInstFlags(prevLIR->opcode) & IS_LOAD);
if (((curLIR->useMask & prevLIR->defMask) && prevIsLoad) || (slot < LD_LATENCY)) {
break;
}
diff --git a/src/compiler/codegen/method_bitcode.cc b/src/compiler/codegen/method_bitcode.cc
index 2996e9a..72e3e68 100644
--- a/src/compiler/codegen/method_bitcode.cc
+++ b/src/compiler/codegen/method_bitcode.cc
@@ -27,8 +27,11 @@
#include <llvm/Support/Casting.h>
#include <llvm/Support/InstIterator.h>
+#include "../compiler_internals.h"
#include "method_codegen_driver.h"
#include "local_optimizations.h"
+#include "codegen_util.h"
+#include "ralloc_util.h"
static const char* kLabelFormat = "%c0x%x_%d";
static const char kInvalidBlock = 0xff;
@@ -36,7 +39,10 @@
static const char kCatchBlock = 'C';
namespace art {
-extern const RegLocation badLoc;
+// TODO: unify badLoc
+const RegLocation badLoc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0, 0,
+ INVALID_REG, INVALID_REG, INVALID_SREG,
+ INVALID_SREG};
RegLocation getLoc(CompilationUnit* cUnit, llvm::Value* val);
llvm::BasicBlock* getLLVMBlock(CompilationUnit* cUnit, int id)
diff --git a/src/compiler/codegen/method_codegen_driver.cc b/src/compiler/codegen/method_codegen_driver.cc
index b41bd83..4bf5a40 100644
--- a/src/compiler/codegen/method_codegen_driver.cc
+++ b/src/compiler/codegen/method_codegen_driver.cc
@@ -16,10 +16,14 @@
#include "object_utils.h"
+#include "../compiler_internals.h"
#include "local_optimizations.h"
+#include "codegen_util.h"
+#include "ralloc_util.h"
namespace art {
+// TODO: unify badLoc
const RegLocation badLoc = {kLocDalvikFrame, 0, 0, 0, 0, 0, 0, 0, 0,
INVALID_REG, INVALID_REG, INVALID_SREG,
INVALID_SREG};
@@ -52,160 +56,6 @@
return res;
}
-// TODO: move to gen_invoke.cc
-void genInvoke(CompilationUnit* cUnit, CallInfo* info)
-{
- if (genIntrinsic(cUnit, info)) {
- return;
- }
- InvokeType originalType = info->type; // avoiding mutation by ComputeInvokeInfo
- int callState = 0;
- LIR* nullCk;
- LIR** pNullCk = NULL;
- NextCallInsn nextCallInsn;
- oatFlushAllRegs(cUnit); /* Everything to home location */
- // Explicit register usage
- oatLockCallTemps(cUnit);
-
- OatCompilationUnit mUnit(cUnit->class_loader, cUnit->class_linker,
- *cUnit->dex_file,
- cUnit->code_item, cUnit->method_idx,
- cUnit->access_flags);
-
- uint32_t dexMethodIdx = info->index;
- int vtableIdx;
- uintptr_t directCode;
- uintptr_t directMethod;
- bool skipThis;
- bool fastPath =
- cUnit->compiler->ComputeInvokeInfo(dexMethodIdx, &mUnit, info->type,
- vtableIdx, directCode,
- directMethod)
- && !SLOW_INVOKE_PATH;
- if (info->type == kInterface) {
- if (fastPath) {
- pNullCk = &nullCk;
- }
- nextCallInsn = fastPath ? nextInterfaceCallInsn
- : nextInterfaceCallInsnWithAccessCheck;
- skipThis = false;
- } else if (info->type == kDirect) {
- if (fastPath) {
- pNullCk = &nullCk;
- }
- nextCallInsn = fastPath ? nextSDCallInsn : nextDirectCallInsnSP;
- skipThis = false;
- } else if (info->type == kStatic) {
- nextCallInsn = fastPath ? nextSDCallInsn : nextStaticCallInsnSP;
- skipThis = false;
- } else if (info->type == kSuper) {
- DCHECK(!fastPath); // Fast path is a direct call.
- nextCallInsn = nextSuperCallInsnSP;
- skipThis = false;
- } else {
- DCHECK_EQ(info->type, kVirtual);
- nextCallInsn = fastPath ? nextVCallInsn : nextVCallInsnSP;
- skipThis = fastPath;
- }
- if (!info->isRange) {
- callState = genDalvikArgsNoRange(cUnit, info, callState, pNullCk,
- nextCallInsn, dexMethodIdx,
- vtableIdx, directCode, directMethod,
- originalType, skipThis);
- } else {
- callState = genDalvikArgsRange(cUnit, info, callState, pNullCk,
- nextCallInsn, dexMethodIdx, vtableIdx,
- directCode, directMethod, originalType,
- skipThis);
- }
- // Finish up any of the call sequence not interleaved in arg loading
- while (callState >= 0) {
- callState = nextCallInsn(cUnit, info, callState, dexMethodIdx,
- vtableIdx, directCode, directMethod,
- originalType);
- }
- if (cUnit->enableDebug & (1 << kDebugDisplayMissingTargets)) {
- genShowTarget(cUnit);
- }
- LIR* callInst;
- if (cUnit->instructionSet != kX86) {
- callInst = opReg(cUnit, kOpBlx, targetReg(kInvokeTgt));
- } else {
- if (fastPath && info->type != kInterface) {
- callInst = opMem(cUnit, kOpBlx, targetReg(kArg0),
- AbstractMethod::GetCodeOffset().Int32Value());
- } else {
- int trampoline = 0;
- switch (info->type) {
- case kInterface:
- trampoline = fastPath ? ENTRYPOINT_OFFSET(pInvokeInterfaceTrampoline)
- : ENTRYPOINT_OFFSET(pInvokeInterfaceTrampolineWithAccessCheck);
- break;
- case kDirect:
- trampoline = ENTRYPOINT_OFFSET(pInvokeDirectTrampolineWithAccessCheck);
- break;
- case kStatic:
- trampoline = ENTRYPOINT_OFFSET(pInvokeStaticTrampolineWithAccessCheck);
- break;
- case kSuper:
- trampoline = ENTRYPOINT_OFFSET(pInvokeSuperTrampolineWithAccessCheck);
- break;
- case kVirtual:
- trampoline = ENTRYPOINT_OFFSET(pInvokeVirtualTrampolineWithAccessCheck);
- break;
- default:
- LOG(FATAL) << "Unexpected invoke type";
- }
- callInst = opThreadMem(cUnit, kOpBlx, trampoline);
- }
- }
- markSafepointPC(cUnit, callInst);
-
- oatClobberCalleeSave(cUnit);
- if (info->result.location != kLocInvalid) {
- // We have a following MOVE_RESULT - do it now.
- if (info->result.wide) {
- RegLocation retLoc = oatGetReturnWide(cUnit, info->result.fp);
- storeValueWide(cUnit, info->result, retLoc);
- } else {
- RegLocation retLoc = oatGetReturn(cUnit, info->result.fp);
- storeValue(cUnit, info->result, retLoc);
- }
- }
-}
-
-/*
- * Build an array of location records for the incoming arguments.
- * Note: one location record per word of arguments, with dummy
- * high-word loc for wide arguments. Also pull up any following
- * MOVE_RESULT and incorporate it into the invoke.
- */
-//TODO: move to gen_invoke.cc or utils
-CallInfo* oatNewCallInfo(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
- InvokeType type, bool isRange)
-{
- CallInfo* info = static_cast<CallInfo*>(oatNew(cUnit, sizeof(CallInfo), true, kAllocMisc));
- MIR* moveResultMIR = oatFindMoveResult(cUnit, bb, mir);
- if (moveResultMIR == NULL) {
- info->result.location = kLocInvalid;
- } else {
- info->result = oatGetRawDest(cUnit, moveResultMIR);
- moveResultMIR->dalvikInsn.opcode = Instruction::NOP;
- }
- info->numArgWords = mir->ssaRep->numUses;
- info->args = (info->numArgWords == 0) ? NULL : static_cast<RegLocation*>
- (oatNew(cUnit, sizeof(RegLocation) * info->numArgWords, false, kAllocMisc));
- for (int i = 0; i < info->numArgWords; i++) {
- info->args[i] = oatGetRawSrc(cUnit, mir, i);
- }
- info->optFlags = mir->optimizationFlags;
- info->type = type;
- info->isRange = isRange;
- info->index = mir->dalvikInsn.vB;
- info->offset = mir->offset;
- return info;
-}
-
/*
* Target-independent code generation. Use only high-level
* load/store utilities here, or target-dependent genXX() handlers
diff --git a/src/compiler/codegen/mips/backend_mips.cc b/src/compiler/codegen/mips/backend_mips.cc
deleted file mode 100644
index 596a5f7..0000000
--- a/src/compiler/codegen/mips/backend_mips.cc
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2012 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#define _CODEGEN_C
-
-#include "mips_lir.h"
-#include "../ralloc_util.h"
-
-/* Common codegen building blocks */
-#include "../codegen_util.cc"
-
-#include "utility_mips.cc"
-#include "../gen_loadstore.cc"
-#include "../gen_common.cc"
-#include "../gen_invoke.cc"
-#include "call_mips.cc"
-#include "fp_mips.cc"
-#include "int_mips.cc"
-
-/* Bitcode conversion */
-#include "../method_bitcode.cc"
-
-/* MIR2LIR dispatcher and architectural independent codegen routines */
-#include "../method_codegen_driver.cc"
-
-/* Target-independent local optimizations */
-#include "../local_optimizations.cc"
diff --git a/src/compiler/codegen/mips/call_mips.cc b/src/compiler/codegen/mips/call_mips.cc
index 1db4eee..5049eec 100644
--- a/src/compiler/codegen/mips/call_mips.cc
+++ b/src/compiler/codegen/mips/call_mips.cc
@@ -17,6 +17,9 @@
/* This file contains codegen for the Mips ISA */
#include "oat/runtime/oat_support_entrypoints.h"
+#include "mips_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
namespace art {
diff --git a/src/compiler/codegen/mips/fp_mips.cc b/src/compiler/codegen/mips/fp_mips.cc
index 1954824..268a88d 100644
--- a/src/compiler/codegen/mips/fp_mips.cc
+++ b/src/compiler/codegen/mips/fp_mips.cc
@@ -15,6 +15,9 @@
*/
#include "oat/runtime/oat_support_entrypoints.h"
+#include "mips_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
namespace art {
diff --git a/src/compiler/codegen/mips/int_mips.cc b/src/compiler/codegen/mips/int_mips.cc
index 82ac547..297a5d92 100644
--- a/src/compiler/codegen/mips/int_mips.cc
+++ b/src/compiler/codegen/mips/int_mips.cc
@@ -17,6 +17,9 @@
/* This file contains codegen for the Mips ISA */
#include "oat/runtime/oat_support_entrypoints.h"
+#include "mips_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
namespace art {
diff --git a/src/compiler/codegen/mips/mips_lir.h b/src/compiler/codegen/mips/mips_lir.h
index b6f686d..de39b7f 100644
--- a/src/compiler/codegen/mips/mips_lir.h
+++ b/src/compiler/codegen/mips/mips_lir.h
@@ -303,8 +303,6 @@
#define kST kSYNC0
#define kSY kSYNC0
-#define isPseudoOpcode(opCode) (static_cast<int>(opCode) < 0)
-
/*
* The following enum defines the list of supported Thumb instructions by the
* assembler. Their corresponding EncodingMap positions will be defined in
diff --git a/src/compiler/codegen/mips/target_mips.cc b/src/compiler/codegen/mips/target_mips.cc
index e157760..a3621f5 100644
--- a/src/compiler/codegen/mips/target_mips.cc
+++ b/src/compiler/codegen/mips/target_mips.cc
@@ -481,10 +481,10 @@
return true;
}
-void oatGenMemBarrier(CompilationUnit *cUnit, int barrierKind)
+void oatGenMemBarrier(CompilationUnit *cUnit, MemBarrierKind barrierKind)
{
#if ANDROID_SMP != 0
- newLIR1(cUnit, kMipsSync, barrierKind);
+ newLIR1(cUnit, kMipsSync, 0 /* Only stype currently supported */);
#endif
}
@@ -655,4 +655,19 @@
return oatArchVariantInit();
}
+uint64_t getTargetInstFlags(int opcode)
+{
+ return EncodingMap[opcode].flags;
+}
+
+const char* getTargetInstName(int opcode)
+{
+ return EncodingMap[opcode].name;
+}
+
+const char* getTargetInstFmt(int opcode)
+{
+ return EncodingMap[opcode].fmt;
+}
+
} // namespace art
diff --git a/src/compiler/codegen/mips/utility_mips.cc b/src/compiler/codegen/mips/utility_mips.cc
index a7faa1d..7a018c5 100644
--- a/src/compiler/codegen/mips/utility_mips.cc
+++ b/src/compiler/codegen/mips/utility_mips.cc
@@ -14,6 +14,10 @@
* limitations under the License.
*/
+#include "mips_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
+
namespace art {
/* This file contains codegen for the MIPS32 ISA. */
diff --git a/src/compiler/codegen/target_list.h b/src/compiler/codegen/target_list.h
index dba00f5..5fc3891 100644
--- a/src/compiler/codegen/target_list.h
+++ b/src/compiler/codegen/target_list.h
@@ -128,7 +128,7 @@
void oatDumpResourceMask(LIR* lir, uint64_t mask, const char* prefix);
void oatFlushReg(CompilationUnit* cUnit, int reg);
void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2);
-void oatGenMemBarrier(CompilationUnit* cUnit, int barrierKind);
+void oatGenMemBarrier(CompilationUnit* cUnit, MemBarrierKind barrierKind);
void oatInitializeRegAlloc(CompilationUnit* cUnit);
void oatMarkPreservedSingle(CompilationUnit* cUnit, int vReg, int reg);
void oatNopLIR( LIR* lir);
@@ -141,3 +141,6 @@
void spillCoreRegs(CompilationUnit* cUnit);
void unSpillCoreRegs(CompilationUnit* cUnit);
X86ConditionCode oatX86ConditionEncoding(ConditionCode cond);
+uint64_t getTargetInstFlags(int opcode);
+const char* getTargetInstName(int opcode);
+const char* getTargetInstFmt(int opcode);
diff --git a/src/compiler/codegen/x86/backend_x86.cc b/src/compiler/codegen/x86/backend_x86.cc
deleted file mode 100644
index 13388ff..0000000
--- a/src/compiler/codegen/x86/backend_x86.cc
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2012 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#define _CODEGEN_C
-
-#include "x86_lir.h"
-#include "../ralloc_util.h"
-
-/* Common codegen utility code */
-#include "../codegen_util.cc"
-
-#include "utility_x86.cc"
-#include "../gen_loadstore.cc"
-#include "../gen_common.cc"
-#include "../gen_invoke.cc"
-#include "call_x86.cc"
-#include "fp_x86.cc"
-#include "int_x86.cc"
-
-/* Bitcode conversion */
-#include "../method_bitcode.cc"
-
-/* MIR2LIR dispatcher and architectural independent codegen routines */
-#include "../method_codegen_driver.cc"
-
-/* Target-independent local optimizations */
-#include "../local_optimizations.cc"
diff --git a/src/compiler/codegen/x86/call_x86.cc b/src/compiler/codegen/x86/call_x86.cc
index c2b456f..51dda66 100644
--- a/src/compiler/codegen/x86/call_x86.cc
+++ b/src/compiler/codegen/x86/call_x86.cc
@@ -16,6 +16,10 @@
/* This file contains codegen for the X86 ISA */
+#include "x86_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
+
namespace art {
void genSpecialCase(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
diff --git a/src/compiler/codegen/x86/fp_x86.cc b/src/compiler/codegen/x86/fp_x86.cc
index 37e9168..92190cc 100644
--- a/src/compiler/codegen/x86/fp_x86.cc
+++ b/src/compiler/codegen/x86/fp_x86.cc
@@ -14,6 +14,10 @@
* limitations under the License.
*/
+#include "x86_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
+
namespace art {
bool genArithOpFloat(CompilationUnit *cUnit, Instruction::Code opcode,
diff --git a/src/compiler/codegen/x86/int_x86.cc b/src/compiler/codegen/x86/int_x86.cc
index bcb51c4..adde482 100644
--- a/src/compiler/codegen/x86/int_x86.cc
+++ b/src/compiler/codegen/x86/int_x86.cc
@@ -16,6 +16,10 @@
/* This file contains codegen for the X86 ISA */
+#include "x86_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
+
namespace art {
/*
diff --git a/src/compiler/codegen/x86/target_x86.cc b/src/compiler/codegen/x86/target_x86.cc
index b6440a7..7c2adf1 100644
--- a/src/compiler/codegen/x86/target_x86.cc
+++ b/src/compiler/codegen/x86/target_x86.cc
@@ -451,7 +451,7 @@
return true;
}
-void oatGenMemBarrier(CompilationUnit *cUnit, int /* barrierKind */)
+void oatGenMemBarrier(CompilationUnit *cUnit, MemBarrierKind barrierKind)
{
#if ANDROID_SMP != 0
// TODO: optimize fences
@@ -605,4 +605,19 @@
return INVALID_REG;
}
+uint64_t getTargetInstFlags(int opcode)
+{
+ return EncodingMap[opcode].flags;
+}
+
+const char* getTargetInstName(int opcode)
+{
+ return EncodingMap[opcode].name;
+}
+
+const char* getTargetInstFmt(int opcode)
+{
+ return EncodingMap[opcode].fmt;
+}
+
} // namespace art
diff --git a/src/compiler/codegen/x86/utility_x86.cc b/src/compiler/codegen/x86/utility_x86.cc
index 418a6fe..9d24dda 100644
--- a/src/compiler/codegen/x86/utility_x86.cc
+++ b/src/compiler/codegen/x86/utility_x86.cc
@@ -14,6 +14,10 @@
* limitations under the License.
*/
+#include "x86_lir.h"
+#include "../codegen_util.h"
+#include "../ralloc_util.h"
+
namespace art {
/* This file contains codegen for the X86 ISA */
diff --git a/src/compiler/codegen/x86/x86_lir.h b/src/compiler/codegen/x86/x86_lir.h
index 9f29d08..53d69ad 100644
--- a/src/compiler/codegen/x86/x86_lir.h
+++ b/src/compiler/codegen/x86/x86_lir.h
@@ -220,8 +220,6 @@
#define rX86_COUNT rCX
#define rX86_PC INVALID_REG
-#define isPseudoOpcode(opCode) (static_cast<int>(opCode) < 0)
-
/*
* The following enum defines the list of supported X86 instructions by the
* assembler. Their corresponding EncodingMap positions will be defined in
diff --git a/src/compiler/compiler_enums.h b/src/compiler/compiler_enums.h
index 3895924..15336cd 100644
--- a/src/compiler/compiler_enums.h
+++ b/src/compiler/compiler_enums.h
@@ -338,6 +338,16 @@
std::ostream& operator<<(std::ostream& os, const DataFlowAnalysisMode& mode);
+// Memory barrier types (see "The JSR-133 Cookbook for Compiler Writers")
+enum MemBarrierKind {
+ kLoadStore,
+ kLoadLoad,
+ kStoreStore,
+ kStoreLoad
+};
+
+std::ostream& operator<<(std::ostream& os, const MemBarrierKind& kind);
+
} // namespace art
#endif // ART_SRC_COMPILER_COMPILERENUMS_H_
diff --git a/src/compiler/compiler_ir.h b/src/compiler/compiler_ir.h
index bc09a9c..df0bd77 100644
--- a/src/compiler/compiler_ir.h
+++ b/src/compiler/compiler_ir.h
@@ -162,6 +162,8 @@
#define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \
ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS)
+#define isPseudoOpcode(opcode) (static_cast<int>(opcode) < 0)
+
struct LIR {
int offset; // Offset of this instruction
int dalvikOffset; // Offset of Dalvik opcode
