Merge android-msm-wahoo-4.4-qt-qpr3 into android-msm-wahoo-4.4
Change-Id: I42c2e2f63819d9cd30e9a5ebcc2f2677391070fa
Signed-off-by: Petri Gynther <pgynther@google.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 104b4cd..42d55c5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7564,6 +7564,12 @@
F: Documentation/scsi/NinjaSCSI.txt
F: drivers/scsi/nsp32*
+NINTENDO HID DRIVER
+M: Daniel J. Ogorchock <djogorchock@gmail.com>
+L: linux-input@vger.kernel.org
+S: Maintained
+F: drivers/hid/hid-nintendo*
+
NIOS2 ARCHITECTURE
M: Ley Foon Tan <lftan@altera.com>
L: nios2-dev@lists.rocketboards.org (moderated for non-subscribers)
diff --git a/Makefile b/Makefile
index 982391a..0d04bcd 100644
--- a/Makefile
+++ b/Makefile
@@ -1082,11 +1082,15 @@
uts_len := 64
define filechk_utsrelease.h
- if [ `echo -n "$(KERNELRELEASE)" | wc -c ` -gt $(uts_len) ]; then \
- echo '"$(KERNELRELEASE)" exceeds $(uts_len) characters' >&2; \
- exit 1; \
- fi; \
- (echo \#define UTS_RELEASE \"$(KERNELRELEASE)\";)
+ if [ `echo -n "$(KERNELRELEASE)" | wc -c ` -gt $(uts_len) ]; then \
+ echo '"$(KERNELRELEASE)" exceeds $(uts_len) characters' >&2; \
+ exit 1; \
+ fi; \
+ if [ -n "$(BUILD_NUMBER)" ]; then \
+ (echo \#define UTS_RELEASE \"$(KERNELRELEASE)-ab$(BUILD_NUMBER)\";) \
+ else \
+ (echo \#define UTS_RELEASE \"$(KERNELRELEASE)\";) \
+ fi
endef
define filechk_version.h
diff --git a/arch/arm64/configs/wahoo_defconfig b/arch/arm64/configs/wahoo_defconfig
index da88be9..978a32a 100644
--- a/arch/arm64/configs/wahoo_defconfig
+++ b/arch/arm64/configs/wahoo_defconfig
@@ -532,6 +532,7 @@
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_MICROSOFT=y
CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NINTENDO=y
CONFIG_HID_NTRIG=y
CONFIG_HID_PANTHERLORD=y
CONFIG_PANTHERLORD_FF=y
diff --git a/build.config.common b/build.config.common
index 632d09e..63f1441 100644
--- a/build.config.common
+++ b/build.config.common
@@ -4,8 +4,8 @@
CROSS_COMPILE_ARM32=arm-linux-androideabi-
DEFCONFIG=wahoo_defconfig
EXTRA_CMDS=''
-CLANG_PREBUILT_BIN=prebuilts-master/clang/host/linux-x86/clang-r353983c/bin/
-LD_LIBRARY_PATH=${ROOT_DIR}/prebuilts-master/clang/host/linux-x86/clang-r353983c/lib64:$LD_LIBRARY_PATH
+CLANG_PREBUILT_BIN=prebuilts-master/clang/host/linux-x86/clang-r377782b/bin/
+LD_LIBRARY_PATH=${ROOT_DIR}/prebuilts-master/clang/host/linux-x86/clang-r377782b/lib64:$LD_LIBRARY_PATH
export LD_LIBRARY_PATH
LINUX_GCC_CROSS_COMPILE_PREBUILTS_BIN=prebuilts/gcc/linux-x86/aarch64/aarch64-linux-android-4.9/bin
LINUX_GCC_CROSS_COMPILE_ARM32_PREBUILTS_BIN=prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.9/bin
diff --git a/build.config.debug_api b/build.config.debug_api
index 43f6377..d832b95 100644
--- a/build.config.debug_api
+++ b/build.config.debug_api
@@ -1,5 +1,5 @@
KERNEL_DIR=private/msm-google
-. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common
+. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common.clang
POST_DEFCONFIG_CMDS="check_defconfig && update_debug_config"
function update_debug_config() {
@@ -15,5 +15,5 @@
-e CONFIG_PANIC_ON_WARN_DEFAULT_ENABLE \
-d CONFIG_KERNEL_LZ4
(cd ${OUT_DIR} && \
- make O=${OUT_DIR} $archsubarch CROSS_COMPILE=${CROSS_COMPILE} olddefconfig)
+ make ${CC_LD_ARG} O=${OUT_DIR} olddefconfig)
}
diff --git a/build.config.debug_hang b/build.config.debug_hang
index 801613a..8585c65 100644
--- a/build.config.debug_hang
+++ b/build.config.debug_hang
@@ -1,5 +1,5 @@
KERNEL_DIR=private/msm-google
-. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common
+. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common.clang
POST_DEFCONFIG_CMDS="check_defconfig && update_debug_config"
function update_debug_config() {
@@ -17,5 +17,5 @@
-e CONFIG_PANIC_ON_WARN_DEFAULT_ENABLE \
-d CONFIG_KERNEL_LZ4
(cd ${OUT_DIR} && \
- make O=${OUT_DIR} $archsubarch CROSS_COMPILE=${CROSS_COMPILE} olddefconfig)
+ make ${CC_LD_ARG} O=${OUT_DIR} olddefconfig)
}
diff --git a/build.config.debug_locking b/build.config.debug_locking
index bae928a..e9dccea 100644
--- a/build.config.debug_locking
+++ b/build.config.debug_locking
@@ -1,5 +1,5 @@
KERNEL_DIR=private/msm-google
-. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common
+. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common.clang
POST_DEFCONFIG_CMDS="check_defconfig && update_debug_config"
function update_debug_config() {
@@ -13,5 +13,5 @@
-e CONFIG_PANIC_ON_WARN_DEFAULT_ENABLE \
-d CONFIG_KERNEL_LZ4
(cd ${OUT_DIR} && \
- make O=${OUT_DIR} $archsubarch CROSS_COMPILE=${CROSS_COMPILE} olddefconfig)
+ make ${CC_LD_ARG} O=${OUT_DIR} olddefconfig)
}
diff --git a/build.config.debug_memory b/build.config.debug_memory
index 774e79d..49fc594 100644
--- a/build.config.debug_memory
+++ b/build.config.debug_memory
@@ -1,5 +1,5 @@
KERNEL_DIR=private/msm-google
-. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common
+. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common.clang
POST_DEFCONFIG_CMDS="check_defconfig && update_debug_config"
function update_debug_config() {
@@ -37,5 +37,5 @@
-e CONFIG_PANIC_ON_WARN_DEFAULT_ENABLE \
-d CONFIG_KERNEL_LZ4
(cd ${OUT_DIR} && \
- make O=${OUT_DIR} $archsubarch CROSS_COMPILE=${CROSS_COMPILE} olddefconfig)
+ make ${CC_LD_ARG} O=${OUT_DIR} olddefconfig)
}
diff --git a/build.config.kasan b/build.config.kasan
index 6505347..df6ead1 100644
--- a/build.config.kasan
+++ b/build.config.kasan
@@ -1,11 +1,11 @@
KERNEL_DIR=private/msm-google
-. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common
+. ${ROOT_DIR}/${KERNEL_DIR}/build.config.common.clang
POST_DEFCONFIG_CMDS="check_defconfig && update_kasan_config"
function update_kasan_config() {
${KERNEL_DIR}/scripts/config --file ${OUT_DIR}/.config \
-e CONFIG_KASAN \
- -e CONFIG_KASAN_INLINE \
+ -e CONFIG_KASAN_OUTLINE \
-e CONFIG_TEST_KASAN \
-e CONFIG_KCOV \
-e CONFIG_SLUB \
@@ -14,7 +14,9 @@
-d CONFIG_SLUB_DEBUG_PANIC_ON \
-d CONFIG_KASAN_OUTLINE \
-d CONFIG_KERNEL_LZ4 \
- -d CONFIG_RANDOMIZE_BASE
+ -d CONFIG_RANDOMIZE_BASE \
+ -d CONFIG_CC_WERROR \
+ --set-val CONFIG_FRAME_WARN 0
(cd ${OUT_DIR} && \
- make O=${OUT_DIR} $archsubarch CROSS_COMPILE=${CROSS_COMPILE} olddefconfig)
+ make ${CC_LD_ARG} O=${OUT_DIR} olddefconfig)
}
diff --git a/drivers/crypto/msm/qce50.c b/drivers/crypto/msm/qce50.c
index 33adaab..8f0473d 100644
--- a/drivers/crypto/msm/qce50.c
+++ b/drivers/crypto/msm/qce50.c
@@ -4675,7 +4675,7 @@
pce_dev->intr_cadence = 0;
atomic_set(&pce_dev->bunch_cmd_seq, 0);
atomic_set(&pce_dev->last_intr_seq, 0);
- pce_dev->cadence_flag = ~pce_dev->cadence_flag;
+ pce_dev->cadence_flag = !pce_dev->cadence_flag;
}
}
diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig
index 8ad246d..2db3376 100644
--- a/drivers/hid/Kconfig
+++ b/drivers/hid/Kconfig
@@ -542,6 +542,17 @@
To compile this driver as a module, choose M here: the
module will be called hid-multitouch.
+config HID_NINTENDO
+ tristate "Nintendo Joy-Con and Pro Controller support"
+ depends on HID
+ help
+ Adds support for the Nintendo Switch Joy-Cons and Pro Controller.
+ All controllers support bluetooth, and the Pro Controller also supports
+ its USB mode.
+
+ To compile this driver as a module, choose M here: the
+ module will be called hid-nintendo.
+
config HID_NTRIG
tristate "N-Trig touch screen"
depends on USB_HID
diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile
index 7ad46a1..4fd757f 100644
--- a/drivers/hid/Makefile
+++ b/drivers/hid/Makefile
@@ -59,6 +59,7 @@
obj-$(CONFIG_HID_MICROSOFT) += hid-microsoft.o
obj-$(CONFIG_HID_MONTEREY) += hid-monterey.o
obj-$(CONFIG_HID_MULTITOUCH) += hid-multitouch.o
+obj-$(CONFIG_HID_NINTENDO) += hid-nintendo.o
obj-$(CONFIG_HID_NTRIG) += hid-ntrig.o
obj-$(CONFIG_HID_ORTEK) += hid-ortek.o
obj-$(CONFIG_HID_PRODIKEYS) += hid-prodikeys.o
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
index 384db34..e512508 100644
--- a/drivers/hid/hid-core.c
+++ b/drivers/hid/hid-core.c
@@ -2012,6 +2012,16 @@
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_POWER_COVER) },
{ HID_USB_DEVICE(USB_VENDOR_ID_MONTEREY, USB_DEVICE_ID_GENIUS_KB29E) },
{ HID_USB_DEVICE(USB_VENDOR_ID_MSI, USB_DEVICE_ID_MSI_GT683R_LED_PANEL) },
+#if IS_ENABLED(CONFIG_HID_NINTENDO)
+ { HID_USB_DEVICE(USB_VENDOR_ID_NINTENDO,
+ USB_DEVICE_ID_NINTENDO_PROCON) },
+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
+ USB_DEVICE_ID_NINTENDO_PROCON) },
+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
+ USB_DEVICE_ID_NINTENDO_JOYCONL) },
+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
+ USB_DEVICE_ID_NINTENDO_JOYCONR) },
+#endif
{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN) },
{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_1) },
{ HID_USB_DEVICE(USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_TOUCH_SCREEN_2) },
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index f9a08ea..1bebfc6 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -732,6 +732,9 @@
#define USB_VENDOR_ID_NINTENDO 0x057e
#define USB_DEVICE_ID_NINTENDO_WIIMOTE 0x0306
#define USB_DEVICE_ID_NINTENDO_WIIMOTE2 0x0330
+#define USB_DEVICE_ID_NINTENDO_JOYCONL 0x2006
+#define USB_DEVICE_ID_NINTENDO_JOYCONR 0x2007
+#define USB_DEVICE_ID_NINTENDO_PROCON 0x2009
#define USB_VENDOR_ID_NOVATEK 0x0603
#define USB_DEVICE_ID_NOVATEK_PCT 0x0600
diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c
index 3331bf8..ff435d5 100644
--- a/drivers/hid/hid-input.c
+++ b/drivers/hid/hid-input.c
@@ -303,6 +303,7 @@
#define HID_BATTERY_QUIRK_PERCENT (1 << 0) /* always reports percent */
#define HID_BATTERY_QUIRK_FEATURE (1 << 1) /* ask for feature report */
+#define HID_BATTERY_QUIRK_IGNORE (1 << 2) /* completely ignore the battery */
static const struct hid_device_id hid_battery_quirks[] = {
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE,
@@ -320,6 +321,9 @@
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE,
USB_DEVICE_ID_APPLE_ALU_WIRELESS_ANSI),
HID_BATTERY_QUIRK_PERCENT | HID_BATTERY_QUIRK_FEATURE },
+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_ELECOM,
+ USB_DEVICE_ID_ELECOM_BM084),
+ HID_BATTERY_QUIRK_IGNORE },
{}
};
@@ -335,13 +339,45 @@
return quirks;
}
+static int hidinput_scale_battery_capacity(struct hid_device *dev,
+ int value)
+{
+ if (dev->battery_min < dev->battery_max &&
+ value >= dev->battery_min && value <= dev->battery_max)
+ value = ((value - dev->battery_min) * 100) /
+ (dev->battery_max - dev->battery_min);
+
+ return value;
+}
+
+static int hidinput_query_battery_capacity(struct hid_device *dev)
+{
+ u8 *buf;
+ int ret;
+
+ buf = kmalloc(2, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ ret = hid_hw_raw_request(dev, dev->battery_report_id, buf, 2,
+ dev->battery_report_type, HID_REQ_GET_REPORT);
+ if (ret != 2) {
+ kfree(buf);
+ return -ENODATA;
+ }
+
+ ret = hidinput_scale_battery_capacity(dev, buf[1]);
+ kfree(buf);
+ return ret;
+}
+
static int hidinput_get_battery_property(struct power_supply *psy,
enum power_supply_property prop,
union power_supply_propval *val)
{
struct hid_device *dev = power_supply_get_drvdata(psy);
+ int value;
int ret = 0;
- __u8 *buf;
switch (prop) {
case POWER_SUPPLY_PROP_PRESENT:
@@ -350,29 +386,15 @@
break;
case POWER_SUPPLY_PROP_CAPACITY:
-
- buf = kmalloc(2 * sizeof(__u8), GFP_KERNEL);
- if (!buf) {
- ret = -ENOMEM;
- break;
+ if (dev->battery_report_type == HID_FEATURE_REPORT) {
+ value = hidinput_query_battery_capacity(dev);
+ if (value < 0)
+ return value;
+ } else {
+ value = dev->battery_capacity;
}
- ret = hid_hw_raw_request(dev, dev->battery_report_id, buf, 2,
- dev->battery_report_type,
- HID_REQ_GET_REPORT);
- if (ret != 2) {
- ret = -ENODATA;
- kfree(buf);
- break;
- }
- ret = 0;
-
- if (dev->battery_min < dev->battery_max &&
- buf[1] >= dev->battery_min &&
- buf[1] <= dev->battery_max)
- val->intval = (100 * (buf[1] - dev->battery_min)) /
- (dev->battery_max - dev->battery_min);
- kfree(buf);
+ val->intval = value;
break;
case POWER_SUPPLY_PROP_MODEL_NAME:
@@ -380,7 +402,22 @@
break;
case POWER_SUPPLY_PROP_STATUS:
- val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
+ if (!dev->battery_reported &&
+ dev->battery_report_type == HID_FEATURE_REPORT) {
+ value = hidinput_query_battery_capacity(dev);
+ if (value < 0)
+ return value;
+
+ dev->battery_capacity = value;
+ dev->battery_reported = true;
+ }
+
+ if (!dev->battery_reported)
+ val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+ else if (dev->battery_capacity == 100)
+ val->intval = POWER_SUPPLY_STATUS_FULL;
+ else
+ val->intval = POWER_SUPPLY_STATUS_DISCHARGING;
break;
case POWER_SUPPLY_PROP_SCOPE:
@@ -395,27 +432,33 @@
return ret;
}
-static bool hidinput_setup_battery(struct hid_device *dev, unsigned report_type, struct hid_field *field)
+static int hidinput_setup_battery(struct hid_device *dev, unsigned report_type, struct hid_field *field)
{
- struct power_supply_desc *psy_desc = NULL;
+ struct power_supply_desc *psy_desc;
struct power_supply_config psy_cfg = { .drv_data = dev, };
unsigned quirks;
s32 min, max;
+ int error;
- if (field->usage->hid != HID_DC_BATTERYSTRENGTH)
- return false; /* no match */
+ if (dev->battery)
+ return 0; /* already initialized? */
- if (dev->battery != NULL)
- goto out; /* already initialized? */
+ quirks = find_battery_quirk(dev);
+
+ hid_dbg(dev, "device %x:%x:%x %d quirks %d\n",
+ dev->bus, dev->vendor, dev->product, dev->version, quirks);
+
+ if (quirks & HID_BATTERY_QUIRK_IGNORE)
+ return 0;
psy_desc = kzalloc(sizeof(*psy_desc), GFP_KERNEL);
- if (psy_desc == NULL)
- goto out;
+ if (!psy_desc)
+ return -ENOMEM;
psy_desc->name = kasprintf(GFP_KERNEL, "hid-%s-battery", dev->uniq);
- if (psy_desc->name == NULL) {
- kfree(psy_desc);
- goto out;
+ if (!psy_desc->name) {
+ error = -ENOMEM;
+ goto err_free_mem;
}
psy_desc->type = POWER_SUPPLY_TYPE_BATTERY;
@@ -424,11 +467,6 @@
psy_desc->use_for_apm = 0;
psy_desc->get_property = hidinput_get_battery_property;
- quirks = find_battery_quirk(dev);
-
- hid_dbg(dev, "device %x:%x:%x %d quirks %d\n",
- dev->bus, dev->vendor, dev->product, dev->version, quirks);
-
min = field->logical_minimum;
max = field->logical_maximum;
@@ -447,17 +485,20 @@
dev->battery = power_supply_register(&dev->dev, psy_desc, &psy_cfg);
if (IS_ERR(dev->battery)) {
- hid_warn(dev, "can't register power supply: %ld\n",
- PTR_ERR(dev->battery));
- kfree(psy_desc->name);
- kfree(psy_desc);
- dev->battery = NULL;
- } else {
- power_supply_powers(dev->battery, &dev->dev);
+ error = PTR_ERR(dev->battery);
+ hid_warn(dev, "can't register power supply: %d\n", error);
+ goto err_free_name;
}
-out:
- return true;
+ power_supply_powers(dev->battery, &dev->dev);
+ return 0;
+
+err_free_name:
+ kfree(psy_desc->name);
+err_free_mem:
+ kfree(psy_desc);
+ dev->battery = NULL;
+ return error;
}
static void hidinput_cleanup_battery(struct hid_device *dev)
@@ -473,16 +514,33 @@
kfree(psy_desc);
dev->battery = NULL;
}
-#else /* !CONFIG_HID_BATTERY_STRENGTH */
-static bool hidinput_setup_battery(struct hid_device *dev, unsigned report_type,
- struct hid_field *field)
+
+static void hidinput_update_battery(struct hid_device *dev, int value)
{
- return false;
+ if (!dev->battery)
+ return;
+
+ if (value == 0 || value < dev->battery_min || value > dev->battery_max)
+ return;
+
+ dev->battery_capacity = hidinput_scale_battery_capacity(dev, value);
+ dev->battery_reported = true;
+ power_supply_changed(dev->battery);
+}
+#else /* !CONFIG_HID_BATTERY_STRENGTH */
+static int hidinput_setup_battery(struct hid_device *dev, unsigned report_type,
+ struct hid_field *field)
+{
+ return 0;
}
static void hidinput_cleanup_battery(struct hid_device *dev)
{
}
+
+static void hidinput_update_battery(struct hid_device *dev, int value)
+{
+}
#endif /* CONFIG_HID_BATTERY_STRENGTH */
static void hidinput_configure_usage(struct hid_input *hidinput, struct hid_field *field,
@@ -684,6 +742,11 @@
}
break;
+ case 0x3b: /* Battery Strength */
+ hidinput_setup_battery(device, HID_INPUT_REPORT, field);
+ usage->type = EV_PWR;
+ goto ignore;
+
case 0x3c: /* Invert */
map_key_clear(BTN_TOOL_RUBBER);
break;
@@ -924,11 +987,13 @@
break;
case HID_UP_GENDEVCTRLS:
- if (hidinput_setup_battery(device, HID_INPUT_REPORT, field))
+ switch (usage->hid) {
+ case HID_DC_BATTERYSTRENGTH:
+ hidinput_setup_battery(device, HID_INPUT_REPORT, field);
+ usage->type = EV_PWR;
goto ignore;
- else
- goto unknown;
- break;
+ }
+ goto unknown;
case HID_UP_HPVENDOR: /* Reported on a Dutch layout HP5308 */
set_bit(EV_REP, input->evbit);
@@ -1012,7 +1077,6 @@
if (usage->code > max)
goto ignore;
-
if (usage->type == EV_ABS) {
int a = field->logical_minimum;
@@ -1073,14 +1137,19 @@
struct input_dev *input;
unsigned *quirks = &hid->quirks;
+ if (!usage->type)
+ return;
+
+ if (usage->type == EV_PWR) {
+ hidinput_update_battery(hid, value);
+ return;
+ }
+
if (!field->hidinput)
return;
input = field->hidinput->input;
- if (!usage->type)
- return;
-
if (usage->hat_min < usage->hat_max || usage->hat_dir) {
int hat_dir = usage->hat_dir;
if (!hat_dir)
@@ -1357,6 +1426,7 @@
struct hid_driver *drv = hid->driver;
struct hid_report_enum *rep_enum;
struct hid_report *rep;
+ struct hid_usage *usage;
int i, j;
rep_enum = &hid->report_enum[HID_FEATURE_REPORT];
@@ -1367,12 +1437,15 @@
continue;
for (j = 0; j < rep->field[i]->maxusage; j++) {
+ usage = &rep->field[i]->usage[j];
+
/* Verify if Battery Strength feature is available */
- hidinput_setup_battery(hid, HID_FEATURE_REPORT, rep->field[i]);
+ if (usage->hid == HID_DC_BATTERYSTRENGTH)
+ hidinput_setup_battery(hid, HID_FEATURE_REPORT,
+ rep->field[i]);
if (drv->feature_mapping)
- drv->feature_mapping(hid, rep->field[i],
- rep->field[i]->usage + j);
+ drv->feature_mapping(hid, rep->field[i], usage);
}
}
}
diff --git a/drivers/hid/hid-nintendo.c b/drivers/hid/hid-nintendo.c
new file mode 100644
index 0000000..3695b96
--- /dev/null
+++ b/drivers/hid/hid-nintendo.c
@@ -0,0 +1,820 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * HID driver for Nintendo Switch Joy-Cons and Pro Controllers
+ *
+ * Copyright (c) 2019 Daniel J. Ogorchock <djogorchock@gmail.com>
+ *
+ * The following resources/projects were referenced for this driver:
+ * https://github.com/dekuNukem/Nintendo_Switch_Reverse_Engineering
+ * https://gitlab.com/pjranki/joycon-linux-kernel (Peter Rankin)
+ * https://github.com/FrotBot/SwitchProConLinuxUSB
+ * https://github.com/MTCKC/ProconXInput
+ * hid-wiimote kernel hid driver
+ * hid-logitech-hidpp driver
+ *
+ * This driver supports the Nintendo Switch Joy-Cons and Pro Controllers. The
+ * Pro Controllers can either be used over USB or Bluetooth.
+ *
+ * The driver will retrieve the factory calibration info from the controllers,
+ * so little to no user calibration should be required.
+ *
+ */
+
+#include "hid-ids.h"
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/hid.h>
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+/*
+ * Reference the url below for the following HID report defines:
+ * https://github.com/dekuNukem/Nintendo_Switch_Reverse_Engineering
+ */
+
+/* Output Reports */
+static const u8 JC_OUTPUT_RUMBLE_AND_SUBCMD = 0x01;
+static const u8 JC_OUTPUT_FW_UPDATE_PKT = 0x03;
+static const u8 JC_OUTPUT_RUMBLE_ONLY = 0x10;
+static const u8 JC_OUTPUT_MCU_DATA = 0x11;
+static const u8 JC_OUTPUT_USB_CMD = 0x80;
+
+/* Subcommand IDs */
+static const u8 JC_SUBCMD_STATE /*= 0x00*/;
+static const u8 JC_SUBCMD_MANUAL_BT_PAIRING = 0x01;
+static const u8 JC_SUBCMD_REQ_DEV_INFO = 0x02;
+static const u8 JC_SUBCMD_SET_REPORT_MODE = 0x03;
+static const u8 JC_SUBCMD_TRIGGERS_ELAPSED = 0x04;
+static const u8 JC_SUBCMD_GET_PAGE_LIST_STATE = 0x05;
+static const u8 JC_SUBCMD_SET_HCI_STATE = 0x06;
+static const u8 JC_SUBCMD_RESET_PAIRING_INFO = 0x07;
+static const u8 JC_SUBCMD_LOW_POWER_MODE = 0x08;
+static const u8 JC_SUBCMD_SPI_FLASH_READ = 0x10;
+static const u8 JC_SUBCMD_SPI_FLASH_WRITE = 0x11;
+static const u8 JC_SUBCMD_RESET_MCU = 0x20;
+static const u8 JC_SUBCMD_SET_MCU_CONFIG = 0x21;
+static const u8 JC_SUBCMD_SET_MCU_STATE = 0x22;
+static const u8 JC_SUBCMD_SET_PLAYER_LIGHTS = 0x30;
+static const u8 JC_SUBCMD_GET_PLAYER_LIGHTS = 0x31;
+static const u8 JC_SUBCMD_SET_HOME_LIGHT = 0x38;
+static const u8 JC_SUBCMD_ENABLE_IMU = 0x40;
+static const u8 JC_SUBCMD_SET_IMU_SENSITIVITY = 0x41;
+static const u8 JC_SUBCMD_WRITE_IMU_REG = 0x42;
+static const u8 JC_SUBCMD_READ_IMU_REG = 0x43;
+static const u8 JC_SUBCMD_ENABLE_VIBRATION = 0x48;
+static const u8 JC_SUBCMD_GET_REGULATED_VOLTAGE = 0x50;
+
+/* Input Reports */
+static const u8 JC_INPUT_BUTTON_EVENT = 0x3F;
+static const u8 JC_INPUT_SUBCMD_REPLY = 0x21;
+static const u8 JC_INPUT_IMU_DATA = 0x30;
+static const u8 JC_INPUT_MCU_DATA = 0x31;
+static const u8 JC_INPUT_USB_RESPONSE = 0x81;
+
+/* Feature Reports */
+static const u8 JC_FEATURE_LAST_SUBCMD = 0x02;
+static const u8 JC_FEATURE_OTA_FW_UPGRADE = 0x70;
+static const u8 JC_FEATURE_SETUP_MEM_READ = 0x71;
+static const u8 JC_FEATURE_MEM_READ = 0x72;
+static const u8 JC_FEATURE_ERASE_MEM_SECTOR = 0x73;
+static const u8 JC_FEATURE_MEM_WRITE = 0x74;
+static const u8 JC_FEATURE_LAUNCH = 0x75;
+
+/* USB Commands */
+static const u8 JC_USB_CMD_CONN_STATUS = 0x01;
+static const u8 JC_USB_CMD_HANDSHAKE = 0x02;
+static const u8 JC_USB_CMD_BAUDRATE_3M = 0x03;
+static const u8 JC_USB_CMD_NO_TIMEOUT = 0x04;
+static const u8 JC_USB_CMD_EN_TIMEOUT = 0x05;
+static const u8 JC_USB_RESET = 0x06;
+static const u8 JC_USB_PRE_HANDSHAKE = 0x91;
+static const u8 JC_USB_SEND_UART = 0x92;
+
+/* SPI storage addresses of factory calibration data */
+static const u16 JC_CAL_DATA_START = 0x603d;
+static const u16 JC_CAL_DATA_END = 0x604e;
+#define JC_CAL_DATA_SIZE (JC_CAL_DATA_END - JC_CAL_DATA_START + 1)
+
+
+/* The raw analog joystick values will be mapped in terms of this magnitude */
+static const u16 JC_MAX_STICK_MAG = 32767;
+static const u16 JC_STICK_FUZZ = 250;
+static const u16 JC_STICK_FLAT = 500;
+
+/* States for controller state machine */
+enum joycon_ctlr_state {
+ JOYCON_CTLR_STATE_INIT,
+ JOYCON_CTLR_STATE_READ,
+};
+
+struct joycon_stick_cal {
+ s32 max;
+ s32 min;
+ s32 center;
+};
+
+/*
+ * All the controller's button values are stored in a u32.
+ * They can be accessed with bitwise ANDs.
+ */
+static const u32 JC_BTN_Y = BIT(0);
+static const u32 JC_BTN_X = BIT(1);
+static const u32 JC_BTN_B = BIT(2);
+static const u32 JC_BTN_A = BIT(3);
+static const u32 JC_BTN_SR_R = BIT(4);
+static const u32 JC_BTN_SL_R = BIT(5);
+static const u32 JC_BTN_R = BIT(6);
+static const u32 JC_BTN_ZR = BIT(7);
+static const u32 JC_BTN_MINUS = BIT(8);
+static const u32 JC_BTN_PLUS = BIT(9);
+static const u32 JC_BTN_RSTICK = BIT(10);
+static const u32 JC_BTN_LSTICK = BIT(11);
+static const u32 JC_BTN_HOME = BIT(12);
+static const u32 JC_BTN_CAP = BIT(13); /* capture button */
+static const u32 JC_BTN_DOWN = BIT(16);
+static const u32 JC_BTN_UP = BIT(17);
+static const u32 JC_BTN_RIGHT = BIT(18);
+static const u32 JC_BTN_LEFT = BIT(19);
+static const u32 JC_BTN_SR_L = BIT(20);
+static const u32 JC_BTN_SL_L = BIT(21);
+static const u32 JC_BTN_L = BIT(22);
+static const u32 JC_BTN_ZL = BIT(23);
+
+enum joycon_msg_type {
+ JOYCON_MSG_TYPE_NONE,
+ JOYCON_MSG_TYPE_USB,
+ JOYCON_MSG_TYPE_SUBCMD,
+};
+
+struct joycon_subcmd_request {
+ u8 output_id; /* must be 0x01 for subcommand, 0x10 for rumble only */
+ u8 packet_num; /* incremented every send */
+ u8 rumble_data[8];
+ u8 subcmd_id;
+ u8 data[0]; /* length depends on the subcommand */
+} __packed;
+
+struct joycon_subcmd_reply {
+ u8 ack; /* MSB 1 for ACK, 0 for NACK */
+ u8 id; /* id of requested subcmd */
+ u8 data[0]; /* will be at most 35 bytes */
+} __packed;
+
+struct joycon_input_report {
+ u8 id;
+ u8 timer;
+ u8 bat_con; /* battery and connection info */
+ u8 button_status[3];
+ u8 left_stick[3];
+ u8 right_stick[3];
+ u8 vibrator_report;
+
+ /*
+ * If support for firmware updates, gyroscope data, and/or NFC/IR
+ * are added in the future, this can be swapped for a union.
+ */
+ struct joycon_subcmd_reply reply;
+} __packed;
+
+#define JC_MAX_RESP_SIZE (sizeof(struct joycon_input_report) + 35)
+
+/* Each physical controller is associated with a joycon_ctlr struct */
+struct joycon_ctlr {
+ struct hid_device *hdev;
+ struct input_dev *input;
+ enum joycon_ctlr_state ctlr_state;
+
+ /* The following members are used for synchronous sends/receives */
+ enum joycon_msg_type msg_type;
+ u8 subcmd_num;
+ struct mutex output_mutex;
+ u8 input_buf[JC_MAX_RESP_SIZE];
+ wait_queue_head_t wait;
+ bool received_resp;
+ u8 usb_ack_match;
+ u8 subcmd_ack_match;
+
+ /* factory calibration data */
+ struct joycon_stick_cal left_stick_cal_x;
+ struct joycon_stick_cal left_stick_cal_y;
+ struct joycon_stick_cal right_stick_cal_x;
+ struct joycon_stick_cal right_stick_cal_y;
+
+};
+
+static int __joycon_hid_send(struct hid_device *hdev, u8 *data, size_t len)
+{
+ u8 *buf;
+ int ret;
+
+ buf = kmemdup(data, len, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+ ret = hid_hw_output_report(hdev, buf, len);
+ kfree(buf);
+ if (ret < 0)
+ hid_dbg(hdev, "Failed to send output report ret=%d\n", ret);
+ return ret;
+}
+
+static int joycon_hid_send_sync(struct joycon_ctlr *ctlr, u8 *data, size_t len)
+{
+ int ret;
+
+ ret = __joycon_hid_send(ctlr->hdev, data, len);
+ if (ret < 0) {
+ memset(ctlr->input_buf, 0, JC_MAX_RESP_SIZE);
+ return ret;
+ }
+
+ if (!wait_event_timeout(ctlr->wait, ctlr->received_resp, HZ)) {
+ hid_dbg(ctlr->hdev, "synchronous send/receive timed out\n");
+ memset(ctlr->input_buf, 0, JC_MAX_RESP_SIZE);
+ return -ETIMEDOUT;
+ }
+
+ ctlr->received_resp = false;
+ return 0;
+}
+
+static int joycon_send_usb(struct joycon_ctlr *ctlr, u8 cmd)
+{
+ int ret;
+ u8 buf[2] = {JC_OUTPUT_USB_CMD};
+
+ buf[1] = cmd;
+ ctlr->usb_ack_match = cmd;
+ ctlr->msg_type = JOYCON_MSG_TYPE_USB;
+ ret = joycon_hid_send_sync(ctlr, buf, sizeof(buf));
+ if (ret)
+ hid_dbg(ctlr->hdev, "send usb command failed; ret=%d\n", ret);
+ return ret;
+}
+
+static int joycon_send_subcmd(struct joycon_ctlr *ctlr,
+ struct joycon_subcmd_request *subcmd,
+ size_t data_len)
+{
+ int ret;
+
+ subcmd->output_id = JC_OUTPUT_RUMBLE_AND_SUBCMD;
+ subcmd->packet_num = ctlr->subcmd_num;
+ if (++ctlr->subcmd_num > 0xF)
+ ctlr->subcmd_num = 0;
+ ctlr->subcmd_ack_match = subcmd->subcmd_id;
+ ctlr->msg_type = JOYCON_MSG_TYPE_SUBCMD;
+
+ ret = joycon_hid_send_sync(ctlr, (u8 *)subcmd,
+ sizeof(*subcmd) + data_len);
+ if (ret < 0)
+ hid_dbg(ctlr->hdev, "send subcommand failed; ret=%d\n", ret);
+ else
+ ret = 0;
+ return ret;
+}
+
+/* Supply nibbles for flash and on. Ones correspond to active */
+static int joycon_set_player_leds(struct joycon_ctlr *ctlr, u8 flash, u8 on)
+{
+ struct joycon_subcmd_request *req;
+ u8 buffer[sizeof(*req) + 1] = { 0 };
+
+ req = (struct joycon_subcmd_request *)buffer;
+ req->subcmd_id = JC_SUBCMD_SET_PLAYER_LIGHTS;
+ req->data[0] = (flash << 4) | on;
+
+ hid_dbg(ctlr->hdev, "setting player leds\n");
+ return joycon_send_subcmd(ctlr, req, 1);
+}
+
+static const u16 DFLT_STICK_CAL_CEN = 2000;
+static const u16 DFLT_STICK_CAL_MAX = 3500;
+static const u16 DFLT_STICK_CAL_MIN = 500;
+static int joycon_request_calibration(struct joycon_ctlr *ctlr)
+{
+ struct joycon_subcmd_request *req;
+ u8 buffer[sizeof(*req) + 5] = { 0 };
+ struct joycon_input_report *report;
+ struct joycon_stick_cal *cal_x;
+ struct joycon_stick_cal *cal_y;
+ s32 x_max_above;
+ s32 x_min_below;
+ s32 y_max_above;
+ s32 y_min_below;
+ u8 *data;
+ u8 *raw_cal;
+ int ret;
+
+ req = (struct joycon_subcmd_request *)buffer;
+ req->subcmd_id = JC_SUBCMD_SPI_FLASH_READ;
+ data = req->data;
+ data[0] = 0xFF & JC_CAL_DATA_START;
+ data[1] = 0xFF & (JC_CAL_DATA_START >> 8);
+ data[2] = 0xFF & (JC_CAL_DATA_START >> 16);
+ data[3] = 0xFF & (JC_CAL_DATA_START >> 24);
+ data[4] = JC_CAL_DATA_SIZE;
+
+ hid_dbg(ctlr->hdev, "requesting cal data\n");
+ ret = joycon_send_subcmd(ctlr, req, 5);
+ if (ret) {
+ hid_warn(ctlr->hdev,
+ "Failed to read stick cal, using defaults; ret=%d\n",
+ ret);
+
+ ctlr->left_stick_cal_x.center = DFLT_STICK_CAL_CEN;
+ ctlr->left_stick_cal_x.max = DFLT_STICK_CAL_MAX;
+ ctlr->left_stick_cal_x.min = DFLT_STICK_CAL_MIN;
+
+ ctlr->left_stick_cal_y.center = DFLT_STICK_CAL_CEN;
+ ctlr->left_stick_cal_y.max = DFLT_STICK_CAL_MAX;
+ ctlr->left_stick_cal_y.min = DFLT_STICK_CAL_MIN;
+
+ ctlr->right_stick_cal_x.center = DFLT_STICK_CAL_CEN;
+ ctlr->right_stick_cal_x.max = DFLT_STICK_CAL_MAX;
+ ctlr->right_stick_cal_x.min = DFLT_STICK_CAL_MIN;
+
+ ctlr->right_stick_cal_y.center = DFLT_STICK_CAL_CEN;
+ ctlr->right_stick_cal_y.max = DFLT_STICK_CAL_MAX;
+ ctlr->right_stick_cal_y.min = DFLT_STICK_CAL_MIN;
+
+ return ret;
+ }
+
+ report = (struct joycon_input_report *)ctlr->input_buf;
+ raw_cal = &report->reply.data[5];
+
+ /* left stick calibration parsing */
+ cal_x = &ctlr->left_stick_cal_x;
+ cal_y = &ctlr->left_stick_cal_y;
+
+ x_max_above = hid_field_extract(ctlr->hdev, (raw_cal + 0), 0, 12);
+ y_max_above = hid_field_extract(ctlr->hdev, (raw_cal + 1), 4, 12);
+ cal_x->center = hid_field_extract(ctlr->hdev, (raw_cal + 3), 0, 12);
+ cal_y->center = hid_field_extract(ctlr->hdev, (raw_cal + 4), 4, 12);
+ x_min_below = hid_field_extract(ctlr->hdev, (raw_cal + 6), 0, 12);
+ y_min_below = hid_field_extract(ctlr->hdev, (raw_cal + 7), 4, 12);
+ cal_x->max = cal_x->center + x_max_above;
+ cal_x->min = cal_x->center - x_min_below;
+ cal_y->max = cal_y->center + y_max_above;
+ cal_y->min = cal_y->center - y_min_below;
+
+ /* right stick calibration parsing */
+ raw_cal += 9;
+ cal_x = &ctlr->right_stick_cal_x;
+ cal_y = &ctlr->right_stick_cal_y;
+
+ cal_x->center = hid_field_extract(ctlr->hdev, (raw_cal + 0), 0, 12);
+ cal_y->center = hid_field_extract(ctlr->hdev, (raw_cal + 1), 4, 12);
+ x_min_below = hid_field_extract(ctlr->hdev, (raw_cal + 3), 0, 12);
+ y_min_below = hid_field_extract(ctlr->hdev, (raw_cal + 4), 4, 12);
+ x_max_above = hid_field_extract(ctlr->hdev, (raw_cal + 6), 0, 12);
+ y_max_above = hid_field_extract(ctlr->hdev, (raw_cal + 7), 4, 12);
+ cal_x->max = cal_x->center + x_max_above;
+ cal_x->min = cal_x->center - x_min_below;
+ cal_y->max = cal_y->center + y_max_above;
+ cal_y->min = cal_y->center - y_min_below;
+
+ hid_dbg(ctlr->hdev, "calibration:\n"
+ "l_x_c=%d l_x_max=%d l_x_min=%d\n"
+ "l_y_c=%d l_y_max=%d l_y_min=%d\n"
+ "r_x_c=%d r_x_max=%d r_x_min=%d\n"
+ "r_y_c=%d r_y_max=%d r_y_min=%d\n",
+ ctlr->left_stick_cal_x.center,
+ ctlr->left_stick_cal_x.max,
+ ctlr->left_stick_cal_x.min,
+ ctlr->left_stick_cal_y.center,
+ ctlr->left_stick_cal_y.max,
+ ctlr->left_stick_cal_y.min,
+ ctlr->right_stick_cal_x.center,
+ ctlr->right_stick_cal_x.max,
+ ctlr->right_stick_cal_x.min,
+ ctlr->right_stick_cal_y.center,
+ ctlr->right_stick_cal_y.max,
+ ctlr->right_stick_cal_y.min);
+
+ return 0;
+}
+
+static int joycon_set_report_mode(struct joycon_ctlr *ctlr)
+{
+ struct joycon_subcmd_request *req;
+ u8 buffer[sizeof(*req) + 1] = { 0 };
+
+ req = (struct joycon_subcmd_request *)buffer;
+ req->subcmd_id = JC_SUBCMD_SET_REPORT_MODE;
+ req->data[0] = 0x30; /* standard, full report mode */
+
+ hid_dbg(ctlr->hdev, "setting controller report mode\n");
+ return joycon_send_subcmd(ctlr, req, 1);
+}
+
+static s32 joycon_map_stick_val(struct joycon_stick_cal *cal, s32 val)
+{
+ s32 center = cal->center;
+ s32 min = cal->min;
+ s32 max = cal->max;
+ s32 new_val;
+
+ if (val > center) {
+ new_val = (val - center) * JC_MAX_STICK_MAG;
+ new_val /= (max - center);
+ } else {
+ new_val = (center - val) * -JC_MAX_STICK_MAG;
+ new_val /= (center - min);
+ }
+ new_val = clamp(new_val, (s32)-JC_MAX_STICK_MAG, (s32)JC_MAX_STICK_MAG);
+ return new_val;
+}
+
+static void joycon_parse_report(struct joycon_ctlr *ctlr,
+ struct joycon_input_report *rep)
+{
+ struct input_dev *dev = ctlr->input;
+ u32 btns;
+ u32 id = ctlr->hdev->product;
+
+ btns = hid_field_extract(ctlr->hdev, rep->button_status, 0, 24);
+
+ if (id != USB_DEVICE_ID_NINTENDO_JOYCONR) {
+ u16 raw_x;
+ u16 raw_y;
+ s32 x;
+ s32 y;
+
+ /* get raw stick values */
+ raw_x = hid_field_extract(ctlr->hdev, rep->left_stick, 0, 12);
+ raw_y = hid_field_extract(ctlr->hdev,
+ rep->left_stick + 1, 4, 12);
+ /* map the stick values */
+ x = joycon_map_stick_val(&ctlr->left_stick_cal_x, raw_x);
+ y = -joycon_map_stick_val(&ctlr->left_stick_cal_y, raw_y);
+ /* report sticks */
+ input_report_abs(dev, ABS_X, x);
+ input_report_abs(dev, ABS_Y, y);
+
+ /* report buttons */
+ input_report_key(dev, BTN_TL, btns & JC_BTN_L);
+ input_report_key(dev, BTN_TL2, btns & JC_BTN_ZL);
+ if (id != USB_DEVICE_ID_NINTENDO_PROCON) {
+ /* Report the S buttons as the non-existent triggers */
+ input_report_key(dev, BTN_TR, btns & JC_BTN_SL_L);
+ input_report_key(dev, BTN_TR2, btns & JC_BTN_SR_L);
+ }
+ input_report_key(dev, BTN_SELECT, btns & JC_BTN_MINUS);
+ input_report_key(dev, BTN_THUMBL, btns & JC_BTN_LSTICK);
+ input_report_key(dev, BTN_Z, btns & JC_BTN_CAP);
+ input_report_key(dev, BTN_DPAD_DOWN, btns & JC_BTN_DOWN);
+ input_report_key(dev, BTN_DPAD_UP, btns & JC_BTN_UP);
+ input_report_key(dev, BTN_DPAD_RIGHT, btns & JC_BTN_RIGHT);
+ input_report_key(dev, BTN_DPAD_LEFT, btns & JC_BTN_LEFT);
+ }
+ if (id != USB_DEVICE_ID_NINTENDO_JOYCONL) {
+ u16 raw_x;
+ u16 raw_y;
+ s32 x;
+ s32 y;
+
+ /* get raw stick values */
+ raw_x = hid_field_extract(ctlr->hdev, rep->right_stick, 0, 12);
+ raw_y = hid_field_extract(ctlr->hdev,
+ rep->right_stick + 1, 4, 12);
+ /* map stick values */
+ x = joycon_map_stick_val(&ctlr->right_stick_cal_x, raw_x);
+ y = -joycon_map_stick_val(&ctlr->right_stick_cal_y, raw_y);
+ /* report sticks */
+ input_report_abs(dev, ABS_RX, x);
+ input_report_abs(dev, ABS_RY, y);
+
+ /* report buttons */
+ input_report_key(dev, BTN_TR, btns & JC_BTN_R);
+ input_report_key(dev, BTN_TR2, btns & JC_BTN_ZR);
+ if (id != USB_DEVICE_ID_NINTENDO_PROCON) {
+ /* Report the S buttons as the non-existent triggers */
+ input_report_key(dev, BTN_TL, btns & JC_BTN_SL_R);
+ input_report_key(dev, BTN_TL2, btns & JC_BTN_SR_R);
+ }
+ input_report_key(dev, BTN_START, btns & JC_BTN_PLUS);
+ input_report_key(dev, BTN_THUMBR, btns & JC_BTN_RSTICK);
+ input_report_key(dev, BTN_MODE, btns & JC_BTN_HOME);
+ input_report_key(dev, BTN_WEST, btns & JC_BTN_Y);
+ input_report_key(dev, BTN_NORTH, btns & JC_BTN_X);
+ input_report_key(dev, BTN_EAST, btns & JC_BTN_A);
+ input_report_key(dev, BTN_SOUTH, btns & JC_BTN_B);
+ }
+
+ input_sync(dev);
+}
+
+
+static const unsigned int joycon_button_inputs_l[] = {
+ BTN_SELECT, BTN_Z, BTN_THUMBL,
+ BTN_DPAD_UP, BTN_DPAD_DOWN, BTN_DPAD_LEFT, BTN_DPAD_RIGHT,
+ BTN_TL, BTN_TL2,
+ 0 /* 0 signals end of array */
+};
+
+static const unsigned int joycon_button_inputs_r[] = {
+ BTN_START, BTN_MODE, BTN_THUMBR,
+ BTN_SOUTH, BTN_EAST, BTN_NORTH, BTN_WEST,
+ BTN_TR, BTN_TR2,
+ 0 /* 0 signals end of array */
+};
+
+static DEFINE_MUTEX(joycon_input_num_mutex);
+static int joycon_input_create(struct joycon_ctlr *ctlr)
+{
+ struct hid_device *hdev;
+ static int input_num = 1;
+ const char *name;
+ int ret;
+ int i;
+
+ hdev = ctlr->hdev;
+
+ switch (hdev->product) {
+ case USB_DEVICE_ID_NINTENDO_PROCON:
+ name = "Nintendo Switch Pro Controller";
+ break;
+ case USB_DEVICE_ID_NINTENDO_JOYCONL:
+ name = "Nintendo Switch Left Joy-Con";
+ break;
+ case USB_DEVICE_ID_NINTENDO_JOYCONR:
+ name = "Nintendo Switch Right Joy-Con";
+ break;
+ default: /* Should be impossible */
+ hid_err(hdev, "Invalid hid product\n");
+ return -EINVAL;
+ }
+
+ ctlr->input = devm_input_allocate_device(&hdev->dev);
+ if (!ctlr->input)
+ return -ENOMEM;
+ ctlr->input->id.bustype = hdev->bus;
+ ctlr->input->id.vendor = hdev->vendor;
+ ctlr->input->id.product = hdev->product;
+ ctlr->input->id.version = hdev->version;
+ ctlr->input->name = name;
+ input_set_drvdata(ctlr->input, ctlr);
+
+
+ /* set up sticks */
+ if (hdev->product != USB_DEVICE_ID_NINTENDO_JOYCONR) {
+ input_set_abs_params(ctlr->input, ABS_X,
+ -JC_MAX_STICK_MAG, JC_MAX_STICK_MAG,
+ JC_STICK_FUZZ, JC_STICK_FLAT);
+ input_set_abs_params(ctlr->input, ABS_Y,
+ -JC_MAX_STICK_MAG, JC_MAX_STICK_MAG,
+ JC_STICK_FUZZ, JC_STICK_FLAT);
+ }
+ if (hdev->product != USB_DEVICE_ID_NINTENDO_JOYCONL) {
+ input_set_abs_params(ctlr->input, ABS_RX,
+ -JC_MAX_STICK_MAG, JC_MAX_STICK_MAG,
+ JC_STICK_FUZZ, JC_STICK_FLAT);
+ input_set_abs_params(ctlr->input, ABS_RY,
+ -JC_MAX_STICK_MAG, JC_MAX_STICK_MAG,
+ JC_STICK_FUZZ, JC_STICK_FLAT);
+ }
+
+ /* set up buttons */
+ if (hdev->product != USB_DEVICE_ID_NINTENDO_JOYCONR) {
+ for (i = 0; joycon_button_inputs_l[i] > 0; i++)
+ input_set_capability(ctlr->input, EV_KEY,
+ joycon_button_inputs_l[i]);
+ }
+ if (hdev->product != USB_DEVICE_ID_NINTENDO_JOYCONL) {
+ for (i = 0; joycon_button_inputs_r[i] > 0; i++)
+ input_set_capability(ctlr->input, EV_KEY,
+ joycon_button_inputs_r[i]);
+ }
+
+ ret = input_register_device(ctlr->input);
+ if (ret)
+ return ret;
+
+ /* Set the default controller player leds based on controller number */
+ mutex_lock(&joycon_input_num_mutex);
+ mutex_lock(&ctlr->output_mutex);
+ ret = joycon_set_player_leds(ctlr, 0, 0xF >> (4 - input_num));
+ if (ret)
+ hid_warn(ctlr->hdev, "Failed to set leds; ret=%d\n", ret);
+ mutex_unlock(&ctlr->output_mutex);
+ if (++input_num > 4)
+ input_num = 1;
+ mutex_unlock(&joycon_input_num_mutex);
+
+ return 0;
+}
+
+/* Common handler for parsing inputs */
+static int joycon_ctlr_read_handler(struct joycon_ctlr *ctlr, u8 *data,
+ int size)
+{
+ int ret = 0;
+
+ if (data[0] == JC_INPUT_SUBCMD_REPLY || data[0] == JC_INPUT_IMU_DATA ||
+ data[0] == JC_INPUT_MCU_DATA) {
+ if (size >= 12) /* make sure it contains the input report */
+ joycon_parse_report(ctlr,
+ (struct joycon_input_report *)data);
+ }
+
+ return ret;
+}
+
+static int joycon_ctlr_handle_event(struct joycon_ctlr *ctlr, u8 *data,
+ int size)
+{
+ int ret = 0;
+ bool match = false;
+ struct joycon_input_report *report;
+
+ if (unlikely(mutex_is_locked(&ctlr->output_mutex)) &&
+ ctlr->msg_type != JOYCON_MSG_TYPE_NONE) {
+ switch (ctlr->msg_type) {
+ case JOYCON_MSG_TYPE_USB:
+ if (size < 2)
+ break;
+ if (data[0] == JC_INPUT_USB_RESPONSE &&
+ data[1] == ctlr->usb_ack_match)
+ match = true;
+ break;
+ case JOYCON_MSG_TYPE_SUBCMD:
+ if (size < sizeof(struct joycon_input_report) ||
+ data[0] != JC_INPUT_SUBCMD_REPLY)
+ break;
+ report = (struct joycon_input_report *)data;
+ if (report->reply.id == ctlr->subcmd_ack_match)
+ match = true;
+ break;
+ default:
+ break;
+ }
+
+ if (match) {
+ memcpy(ctlr->input_buf, data,
+ min(size, (int)JC_MAX_RESP_SIZE));
+ ctlr->msg_type = JOYCON_MSG_TYPE_NONE;
+ ctlr->received_resp = true;
+ wake_up(&ctlr->wait);
+
+ /* This message has been handled */
+ return 1;
+ }
+ }
+
+ if (ctlr->ctlr_state == JOYCON_CTLR_STATE_READ)
+ ret = joycon_ctlr_read_handler(ctlr, data, size);
+
+ return ret;
+}
+
+static int nintendo_hid_event(struct hid_device *hdev,
+ struct hid_report *report, u8 *raw_data, int size)
+{
+ struct joycon_ctlr *ctlr = hid_get_drvdata(hdev);
+
+ if (size < 1)
+ return -EINVAL;
+
+ return joycon_ctlr_handle_event(ctlr, raw_data, size);
+}
+
+static int nintendo_hid_probe(struct hid_device *hdev,
+ const struct hid_device_id *id)
+{
+ int ret;
+ struct joycon_ctlr *ctlr;
+
+ hid_dbg(hdev, "probe - start\n");
+
+ ctlr = devm_kzalloc(&hdev->dev, sizeof(*ctlr), GFP_KERNEL);
+ if (!ctlr) {
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ctlr->hdev = hdev;
+ ctlr->ctlr_state = JOYCON_CTLR_STATE_INIT;
+ hid_set_drvdata(hdev, ctlr);
+ mutex_init(&ctlr->output_mutex);
+ init_waitqueue_head(&ctlr->wait);
+
+ ret = hid_parse(hdev);
+ if (ret) {
+ hid_err(hdev, "HID parse failed\n");
+ goto err;
+ }
+
+ ret = hid_hw_start(hdev, HID_CONNECT_HIDRAW);
+ if (ret) {
+ hid_err(hdev, "HW start failed\n");
+ goto err;
+ }
+
+ ret = hid_hw_open(hdev);
+ if (ret) {
+ hid_err(hdev, "cannot start hardware I/O\n");
+ goto err_stop;
+ }
+
+ hid_device_io_start(hdev);
+
+ /* Initialize the controller */
+ mutex_lock(&ctlr->output_mutex);
+ /* if handshake command fails, assume ble pro controller */
+ if (hdev->product == USB_DEVICE_ID_NINTENDO_PROCON &&
+ !joycon_send_usb(ctlr, JC_USB_CMD_HANDSHAKE)) {
+ hid_dbg(hdev, "detected USB controller\n");
+ /* set baudrate for improved latency */
+ ret = joycon_send_usb(ctlr, JC_USB_CMD_BAUDRATE_3M);
+ if (ret) {
+ hid_err(hdev, "Failed to set baudrate; ret=%d\n", ret);
+ goto err_mutex;
+ }
+ /* handshake */
+ ret = joycon_send_usb(ctlr, JC_USB_CMD_HANDSHAKE);
+ if (ret) {
+ hid_err(hdev, "Failed handshake; ret=%d\n", ret);
+ goto err_mutex;
+ }
+ /*
+ * Set no timeout (to keep controller in USB mode).
+ * This doesn't send a response, so ignore the timeout.
+ */
+ joycon_send_usb(ctlr, JC_USB_CMD_NO_TIMEOUT);
+ }
+
+ /* get controller calibration data, and parse it */
+ ret = joycon_request_calibration(ctlr);
+ if (ret) {
+ /*
+ * We can function with default calibration, but it may be
+ * inaccurate. Provide a warning, and continue on.
+ */
+ hid_warn(hdev, "Analog stick positions may be inaccurate\n");
+ }
+
+ /* Set the reporting mode to 0x30, which is the full report mode */
+ ret = joycon_set_report_mode(ctlr);
+ if (ret) {
+ hid_err(hdev, "Failed to set report mode; ret=%d\n", ret);
+ goto err_mutex;
+ }
+
+ mutex_unlock(&ctlr->output_mutex);
+
+ ret = joycon_input_create(ctlr);
+ if (ret) {
+ hid_err(hdev, "Failed to create input device; ret=%d\n", ret);
+ goto err_close;
+ }
+
+ ctlr->ctlr_state = JOYCON_CTLR_STATE_READ;
+
+ hid_dbg(hdev, "probe - success\n");
+ return 0;
+
+err_mutex:
+ mutex_unlock(&ctlr->output_mutex);
+err_close:
+ hid_hw_close(hdev);
+err_stop:
+ hid_hw_stop(hdev);
+err:
+ hid_err(hdev, "probe - fail = %d\n", ret);
+ return ret;
+}
+
+static void nintendo_hid_remove(struct hid_device *hdev)
+{
+ hid_dbg(hdev, "remove\n");
+ hid_hw_close(hdev);
+ hid_hw_stop(hdev);
+}
+
+static const struct hid_device_id nintendo_hid_devices[] = {
+ { HID_USB_DEVICE(USB_VENDOR_ID_NINTENDO,
+ USB_DEVICE_ID_NINTENDO_PROCON) },
+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
+ USB_DEVICE_ID_NINTENDO_PROCON) },
+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
+ USB_DEVICE_ID_NINTENDO_JOYCONL) },
+ { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
+ USB_DEVICE_ID_NINTENDO_JOYCONR) },
+ { }
+};
+MODULE_DEVICE_TABLE(hid, nintendo_hid_devices);
+
+static struct hid_driver nintendo_hid_driver = {
+ .name = "nintendo",
+ .id_table = nintendo_hid_devices,
+ .probe = nintendo_hid_probe,
+ .remove = nintendo_hid_remove,
+ .raw_event = nintendo_hid_event,
+};
+module_hid_driver(nintendo_hid_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Daniel J. Ogorchock <djogorchock@gmail.com>");
+MODULE_DESCRIPTION("Driver for Nintendo Switch Controllers");
diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c
index bc6ad5f..fa1f56b 100644
--- a/drivers/hid/hid-sony.c
+++ b/drivers/hid/hid-sony.c
@@ -576,10 +576,14 @@
static inline void sony_schedule_work(struct sony_sc *sc,
enum sony_worker which)
{
+ unsigned long flags;
+
switch (which) {
case SONY_WORKER_STATE:
- if (!sc->defer_initialization)
+ spin_lock_irqsave(&sc->lock, flags);
+ if (!sc->defer_initialization && sc->state_worker_initialized)
schedule_work(&sc->state_worker);
+ spin_unlock_irqrestore(&sc->lock, flags);
break;
case SONY_WORKER_HOTPLUG:
if (sc->hotplug_worker_initialized)
@@ -2489,13 +2493,18 @@
static inline void sony_cancel_work_sync(struct sony_sc *sc)
{
+ unsigned long flags;
+
if (sc->hotplug_worker_initialized)
cancel_work_sync(&sc->hotplug_worker);
- if (sc->state_worker_initialized)
+ if (sc->state_worker_initialized) {
+ spin_lock_irqsave(&sc->lock, flags);
+ sc->state_worker_initialized = 0;
+ spin_unlock_irqrestore(&sc->lock, flags);
cancel_work_sync(&sc->state_worker);
+ }
}
-
static int sony_input_configured(struct hid_device *hdev,
struct hid_input *hidinput)
{
diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c
index e9ae3d5..3fd2185 100644
--- a/drivers/input/evdev.c
+++ b/drivers/input/evdev.c
@@ -28,13 +28,6 @@
#include <linux/cdev.h>
#include "input-compat.h"
-enum evdev_clock_type {
- EV_CLK_REAL = 0,
- EV_CLK_MONO,
- EV_CLK_BOOT,
- EV_CLK_MAX
-};
-
struct evdev {
int open;
struct input_handle handle;
@@ -56,7 +49,7 @@
struct fasync_struct *fasync;
struct evdev *evdev;
struct list_head node;
- unsigned int clk_type;
+ enum input_clock_type clk_type;
bool revoked;
unsigned long *evmasks[EV_CNT];
unsigned int bufsize;
@@ -155,16 +148,12 @@
static void __evdev_queue_syn_dropped(struct evdev_client *client)
{
+ ktime_t *ev_time = input_get_timestamp(client->evdev->handle.dev);
+ struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]);
struct input_event ev;
- ktime_t time;
- time = client->clk_type == EV_CLK_REAL ?
- ktime_get_real() :
- client->clk_type == EV_CLK_MONO ?
- ktime_get() :
- ktime_get_boottime();
-
- ev.time = ktime_to_timeval(time);
+ ev.time.tv_sec = ts.tv_sec;
+ ev.time.tv_usec = ts.tv_nsec / NSEC_PER_USEC;
ev.type = EV_SYN;
ev.code = SYN_DROPPED;
ev.value = 0;
@@ -191,18 +180,18 @@
static int evdev_set_clk_type(struct evdev_client *client, unsigned int clkid)
{
unsigned long flags;
- unsigned int clk_type;
+ enum input_clock_type clk_type;
switch (clkid) {
case CLOCK_REALTIME:
- clk_type = EV_CLK_REAL;
+ clk_type = INPUT_CLK_REAL;
break;
case CLOCK_MONOTONIC:
- clk_type = EV_CLK_MONO;
+ clk_type = INPUT_CLK_MONO;
break;
case CLOCK_BOOTTIME:
- clk_type = EV_CLK_BOOT;
+ clk_type = INPUT_CLK_BOOT;
break;
default:
return -EINVAL;
@@ -304,12 +293,7 @@
{
struct evdev *evdev = handle->private;
struct evdev_client *client;
- ktime_t ev_time[EV_CLK_MAX];
-
- ev_time[EV_CLK_MONO] = ktime_get();
- ev_time[EV_CLK_REAL] = ktime_mono_to_real(ev_time[EV_CLK_MONO]);
- ev_time[EV_CLK_BOOT] = ktime_mono_to_any(ev_time[EV_CLK_MONO],
- TK_OFFS_BOOT);
+ ktime_t *ev_time = input_get_timestamp(handle->dev);
rcu_read_lock();
diff --git a/drivers/input/input.c b/drivers/input/input.c
index 8579170..18d6d8f 100644
--- a/drivers/input/input.c
+++ b/drivers/input/input.c
@@ -401,6 +401,13 @@
if (dev->num_vals >= 2)
input_pass_values(dev, dev->vals, dev->num_vals);
dev->num_vals = 0;
+ /*
+ * Reset the timestamp on flush so we won't end up
+ * with a stale one. Note we only need to reset the
+ * monolithic one as we use its presence when deciding
+ * whether to generate a synthetic timestamp.
+ */
+ dev->timestamp[INPUT_CLK_MONO] = ktime_set(0, 0);
} else if (dev->num_vals >= dev->max_vals - 2) {
dev->vals[dev->num_vals++] = input_value_sync;
input_pass_values(dev, dev->vals, dev->num_vals);
@@ -1910,6 +1917,47 @@
EXPORT_SYMBOL(input_free_device);
/**
+ * input_set_timestamp - set timestamp for input events
+ * @dev: input device to set timestamp for
+ * @timestamp: the time at which the event has occurred
+ * in CLOCK_MONOTONIC
+ *
+ * This function is intended to provide to the input system a more
+ * accurate time of when an event actually occurred. The driver should
+ * call this function as soon as a timestamp is acquired ensuring
+ * clock conversions in input_set_timestamp are done correctly.
+ *
+ * The system entering a suspend between timestamp acquisition and
+ * calling input_set_timestamp can result in inaccurate conversions.
+ *
+ */
+void input_set_timestamp(struct input_dev *dev, ktime_t timestamp)
+{
+ dev->timestamp[INPUT_CLK_MONO] = timestamp;
+ dev->timestamp[INPUT_CLK_REAL] = ktime_mono_to_real(timestamp);
+ dev->timestamp[INPUT_CLK_BOOT] = ktime_mono_to_any(
+ timestamp, TK_OFFS_BOOT);
+}
+EXPORT_SYMBOL(input_set_timestamp);
+
+/**
+ * input_get_timestamp - get timestamp for input events
+ * @dev: input device to get timestamp from
+ *
+ * A valid timestamp is a timestamp of non-zero value.
+ */
+ktime_t *input_get_timestamp(struct input_dev *dev)
+{
+ const ktime_t invalid_timestamp = ktime_set(0, 0);
+
+ if (!ktime_compare(dev->timestamp[INPUT_CLK_MONO], invalid_timestamp))
+ input_set_timestamp(dev, ktime_get());
+
+ return dev->timestamp;
+}
+EXPORT_SYMBOL(input_get_timestamp);
+
+/**
* input_set_capability - mark device as capable of a certain event
* @dev: device that is capable of emitting or accepting event
* @type: type of the event (EV_KEY, EV_REL, etc...)
diff --git a/drivers/input/touchscreen/stm/ftm4_ts.c b/drivers/input/touchscreen/stm/ftm4_ts.c
index fa2b59a..b2786f6 100644
--- a/drivers/input/touchscreen/stm/ftm4_ts.c
+++ b/drivers/input/touchscreen/stm/ftm4_ts.c
@@ -1314,6 +1314,21 @@
#endif
/**
+ * fts_hard_interrupt_handler()
+ * Called by the kernel when the touch interrupt occurs.
+ * This represents the top half of the interrupt.
+ *
+ * Set the input event timestamp here to ensure that we have an accurate
+ * estimate of when the touch event actually occurred.
+ */
+static irqreturn_t fts_hard_interrupt_handler(int irq, void *handle)
+{
+ struct fts_ts_info *info = handle;
+ input_set_timestamp(info->input_dev, ktime_get());
+ return IRQ_WAKE_THREAD;
+}
+
+/**
* fts_interrupt_handler()
*
* Called by the kernel when an interrupt occurs (when the sensor
@@ -1932,7 +1947,7 @@
goto err_enable_irq;
}
- retval = request_threaded_irq(info->irq, NULL,
+ retval = request_threaded_irq(info->irq, fts_hard_interrupt_handler,
fts_interrupt_handler, info->board->irq_type,
FTS_TS_DRV_NAME, info);
if (retval < 0) {
diff --git a/drivers/input/touchscreen/synaptics_dsx_htc/synaptics_dsx_core_htc.c b/drivers/input/touchscreen/synaptics_dsx_htc/synaptics_dsx_core_htc.c
index c070590..494aa5f 100644
--- a/drivers/input/touchscreen/synaptics_dsx_htc/synaptics_dsx_core_htc.c
+++ b/drivers/input/touchscreen/synaptics_dsx_htc/synaptics_dsx_core_htc.c
@@ -2488,6 +2488,20 @@
return;
}
+/**
+ * Called by the kernel when the touch interrupt occurs.
+ * This represents the top half of the interrupt.
+ *
+ * Set the input event timestamp here to ensure that we have an accurate
+ * estimate of when the touch event actually occurred.
+ */
+static irqreturn_t synaptics_rmi4_hardirq(int irq, void *data)
+{
+ struct synaptics_rmi4_data *rmi4_data = data;
+ input_set_timestamp(rmi4_data->input_dev, ktime_get());
+ return IRQ_WAKE_THREAD;
+}
+
static irqreturn_t synaptics_rmi4_irq(int irq, void *data)
{
struct synaptics_rmi4_data *rmi4_data = data;
@@ -2588,7 +2602,8 @@
#if IS_ENABLED(CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_HTC)
enable_irq(rmi4_data->irq);
#else
- retval = request_threaded_irq(rmi4_data->irq, NULL,
+ retval = request_threaded_irq(rmi4_data->irq,
+ synaptics_rmi4_hardirq,
synaptics_rmi4_irq, bdata->irq_flags,
PLATFORM_DRIVER_NAME, rmi4_data);
if (retval < 0) {
@@ -5683,7 +5698,7 @@
"tp_direct_interrupt");
#if IS_ENABLED(CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_HTC)
- retval = request_threaded_irq(rmi4_data->irq, NULL,
+ retval = request_threaded_irq(rmi4_data->irq, synaptics_rmi4_hardirq,
synaptics_rmi4_irq,
IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
PLATFORM_DRIVER_NAME,
diff --git a/drivers/media/platform/msm/camera_v2/camera/camera.c b/drivers/media/platform/msm/camera_v2/camera/camera.c
index c620e44..f97e3ed 100644
--- a/drivers/media/platform/msm/camera_v2/camera/camera.c
+++ b/drivers/media/platform/msm/camera_v2/camera/camera.c
@@ -636,6 +636,7 @@
unsigned long opn_idx, idx;
BUG_ON(!pvdev);
+ mutex_lock(&pvdev->video_drvdata_mutex);
rc = camera_v4l2_fh_open(filep);
if (rc < 0) {
pr_err("%s : camera_v4l2_fh_open failed Line %d rc %d\n",
@@ -706,6 +707,7 @@
idx |= (1 << find_first_zero_bit((const unsigned long *)&opn_idx,
MSM_CAMERA_STREAM_CNT_BITS));
atomic_cmpxchg(&pvdev->opened, opn_idx, idx);
+ mutex_unlock(&pvdev->video_drvdata_mutex);
return rc;
@@ -720,6 +722,7 @@
vb2_q_fail:
camera_v4l2_fh_release(filep);
fh_open_fail:
+ mutex_unlock(&pvdev->video_drvdata_mutex);
return rc;
}
@@ -750,6 +753,7 @@
if (WARN_ON(!session))
return -EIO;
+ mutex_lock(&pvdev->video_drvdata_mutex);
mutex_lock(&session->close_lock);
opn_idx = atomic_read(&pvdev->opened);
mask = (1 << sp->stream_id);
@@ -791,6 +795,7 @@
}
camera_v4l2_fh_release(filep);
+ mutex_unlock(&pvdev->video_drvdata_mutex);
return 0;
}
@@ -937,6 +942,7 @@
*session = pvdev->vdev->num;
atomic_set(&pvdev->opened, 0);
+ mutex_init(&pvdev->video_drvdata_mutex);
video_set_drvdata(pvdev->vdev, pvdev);
device_init_wakeup(&pvdev->vdev->dev, 1);
goto init_end;
diff --git a/drivers/media/platform/msm/camera_v2/fd/Makefile b/drivers/media/platform/msm/camera_v2/fd/Makefile
index 8d01d3a..a1d33da 100644
--- a/drivers/media/platform/msm/camera_v2/fd/Makefile
+++ b/drivers/media/platform/msm/camera_v2/fd/Makefile
@@ -1,4 +1,3 @@
-GCC_VERSION := $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CROSS_COMPILE)gcc)
ccflags-y += -Idrivers/media/video/msm
ccflags-y += -Idrivers/media/platform/msm/camera_v2/common
ccflags-y += -Idrivers/media/platform/msm/camera_v2
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_10/Makefile b/drivers/media/platform/msm/camera_v2/jpeg_10/Makefile
index 0b8dc1d..72808f9 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_10/Makefile
+++ b/drivers/media/platform/msm/camera_v2/jpeg_10/Makefile
@@ -1,5 +1,3 @@
-GCC_VERSION := $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CROSS_COMPILE)gcc)
-
ccflags-y += -Idrivers/media/platform/msm/camera_v2/jpeg_10
ccflags-y += -Idrivers/media/platform/msm/camera_v2/sensor/io
ccflags-y += -Idrivers/media/platform/msm/camera_v2/common
diff --git a/drivers/media/platform/msm/camera_v2/jpeg_dma/Makefile b/drivers/media/platform/msm/camera_v2/jpeg_dma/Makefile
index 21cbadb..239b664 100644
--- a/drivers/media/platform/msm/camera_v2/jpeg_dma/Makefile
+++ b/drivers/media/platform/msm/camera_v2/jpeg_dma/Makefile
@@ -1,4 +1,3 @@
-GCC_VERSION := $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CROSS_COMPILE)gcc)
ccflags-y += -Idrivers/media/video/msm
ccflags-y += -Idrivers/media/platform/msm/camera_v2/common
obj-$(CONFIG_MSM_JPEGDMA) += msm_jpeg_dma_dev.o msm_jpeg_dma_hw.o
diff --git a/drivers/media/platform/msm/camera_v2/msm.h b/drivers/media/platform/msm/camera_v2/msm.h
index dce47bc..8bdb14f5 100644
--- a/drivers/media/platform/msm/camera_v2/msm.h
+++ b/drivers/media/platform/msm/camera_v2/msm.h
@@ -46,6 +46,7 @@
struct msm_video_device {
struct video_device *vdev;
atomic_t opened;
+ struct mutex video_drvdata_mutex;
};
struct msm_queue_head {
diff --git a/drivers/misc/mnh/mnh-clk.c b/drivers/misc/mnh/mnh-clk.c
index 4bb51cf..9f82b14 100644
--- a/drivers/misc/mnh/mnh-clk.c
+++ b/drivers/misc/mnh/mnh-clk.c
@@ -1,7 +1,7 @@
/*
*
* MNH Clock Driver
- * Copyright (c) 2016-2017, Intel Corporation.
+ * Copyright (c) 2016-2018, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -24,6 +24,8 @@
#include "mnh-hwio.h"
#include "mnh-hwio-bases.h"
#include "mnh-hwio-scu.h"
+#include "mnh-hwio-cpu.h"
+#include "mnh-hwio-ddr-ctl.h"
#include "mnh-clk.h"
#include "mnh-ddr.h"
@@ -38,6 +40,17 @@
#define SCU_OUTf(...) \
HW_OUTf(HWIO_SCU_BASE_ADDR, SCU, __VA_ARGS__)
+#define MNH_CPU_IN(reg) \
+ HW_IN(HWIO_CPU_BASE_ADDR, CPU, reg)
+#define MNH_DDR_CTL_IN(reg) \
+ HW_IN(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, reg)
+#define MNH_DDR_CTL_INf(reg, fld) \
+ HW_INf(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, reg, fld)
+#define MNH_DDR_CTL_OUTf(reg, fld, val) \
+ HW_OUTf(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, reg, fld, val)
+#define MNH_DDR_CTL_OUT(reg, val) \
+ HW_OUT(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, reg, val)
+
#define PLL_UNLOCK 0x4CD9
#define LP4_LPC_FREQ_SWITCH 0x8A
#define REF_CLK_KHZ 19200
@@ -531,74 +544,7 @@
*/
int mnh_lpddr_freq_change(int index)
{
- int status = 0;
- int timeout = 0;
- enum mnh_lpddr_freq_type ddr_freq;
-
- if (!mnh_clk)
- return -ENODEV;
-
- dev_dbg(mnh_clk->dev, "%s: %d\n", __func__, index);
-
- if (index < LPDDR_FREQ_MIN || index > LPDDR_FREQ_MAX)
- return -EINVAL;
-
- /* Check the requested FSP is already in use */
- ddr_freq = SCU_INf(LPDDR4_LOW_POWER_STS, LPDDR4_CUR_FSP);
- if (ddr_freq == index) {
- dev_dbg(mnh_clk->dev, "%s: requested fsp%d is in use\n",
- __func__, index);
- return 0;
- }
-
- /* Power up LPDDR PLL if the FSP setting uses it */
- if (!SCU_INxf(LPDDR4_FSP_SETTING, index, FSP_SYS200_MODE))
- mnh_lpddr_sys200_mode(false);
-
- /* Disable LPC SW override */
- SCU_OUTf(LPDDR4_LOW_POWER_CFG, LP4_FSP_SW_OVERRIDE, 0);
-
- /* Configure FSP index */
- SCU_OUTf(LPDDR4_LOW_POWER_CFG, LPC_FREQ_CHG_COPY_NUM, index);
-
- /* Configure LPC cmd for frequency switch */
- SCU_OUTf(LPDDR4_LOW_POWER_CFG, LPC_EXT_CMD, LP4_LPC_FREQ_SWITCH);
-
- /* Initiate LPC cmd to LPDDR controller */
- dev_dbg(mnh_clk->dev, "%s: lpddr freq switching from fsp%d to fsp%d\n",
- __func__, ddr_freq, index);
- SCU_OUTf(LPDDR4_LOW_POWER_CFG, LPC_EXT_CMD_REQ, 1);
-
- /* Wait until LPC cmd process is done */
- do {
- status = SCU_INf(LPDDR4_LOW_POWER_STS, LPC_CMD_DONE);
- } while ((++timeout < PLL_LOCK_TIMEOUT) && (status != 1));
-
- /* Clear LPC cmd status */
- SCU_OUTf(LPDDR4_LOW_POWER_STS, LPC_CMD_DONE, 1);
-
- /* Check LPC error status */
- if (SCU_INf(LPDDR4_LOW_POWER_STS, LPC_CMD_RSP) == LPC_CMD_ERR) {
- /* Clear error status */
- SCU_OUTf(LPDDR4_LOW_POWER_STS, LPC_CMD_RSP, 1);
- dev_err(mnh_clk->dev, "Failed to process lpc cmd:0x%x\n",
- LP4_LPC_FREQ_SWITCH);
- return -EIO;
- }
-
- /* Check FSPx switch status */
- if (SCU_INf(LPDDR4_LOW_POWER_STS, LPDDR4_CUR_FSP) != index) {
- dev_err(mnh_clk->dev, "Failed to switch to fsp%d\n", index);
- return -EIO;
- }
-
- /* Power down LPDDR PLL if the FSP setting doesn't use it */
- if (SCU_INxf(LPDDR4_FSP_SETTING, index, FSP_SYS200_MODE))
- mnh_lpddr_sys200_mode(true);
-
- mnh_ddr_clr_int_status(mnh_clk->dev);
-
- return 0;
+ return mnh_ddr_sw_switch(index);
}
EXPORT_SYMBOL_GPL(mnh_lpddr_freq_change);
@@ -881,8 +827,7 @@
struct device_attribute *attr,
char *buf)
{
- uint32_t var = SCU_INf(LPDDR4_LOW_POWER_STS,
- LPDDR4_CUR_FSP);
+ uint32_t var = MNH_DDR_CTL_INf(133, CURRENT_REG_COPY);
dev_dbg(mnh_clk->dev, "%s: %d\n", __func__, var);
return snprintf(buf, PAGE_SIZE, "FSP%d\n", var);
diff --git a/drivers/misc/mnh/mnh-ddr-33-100-400-600.h b/drivers/misc/mnh/mnh-ddr-33-100-400-600.h
index f5b42e9..db3b540 100644
--- a/drivers/misc/mnh/mnh-ddr-33-100-400-600.h
+++ b/drivers/misc/mnh/mnh-ddr-33-100-400-600.h
@@ -79,10 +79,10 @@
0x0c000002 /* ctl 66 */,
0x00030103 /* ctl 67 */,
0x01031100 /* ctl 68 */,
- 0x000a0003 /* ctl 69 */,
- 0x001c0003 /* ctl 70 */,
- 0x006e0006 /* ctl 71 */,
- 0x00a6000a /* ctl 72 */,
+ 0x000a000a /* ctl 69 */,
+ 0x001c001c /* ctl 70 */,
+ 0x006e006e /* ctl 71 */,
+ 0x00a600a6 /* ctl 72 */,
0x03050505 /* ctl 73 */,
0x03010302 /* ctl 74 */,
0x03050505 /* ctl 75 */,
@@ -124,9 +124,9 @@
0x06030303 /* ctl 111 */,
0x00030a03 /* ctl 112 */,
0x02030200 /* ctl 113 */,
- 0x00070703 /* ctl 114 */,
+ 0x00070903 /* ctl 114 */,
0x03020302 /* ctl 115 */,
- 0x02000707 /* ctl 116 */,
+ 0x02000709 /* ctl 116 */,
0x07030203 /* ctl 117 */,
0x03020007 /* ctl 118 */,
0x07070302 /* ctl 119 */,
@@ -174,12 +174,12 @@
0x00313131 /* ctl 161 */,
0x00000000 /* ctl 162 */,
0x4d4d4d4d /* ctl 163 */,
- 0x4d4d4dc0 /* ctl 164 */,
+ 0x4d4d4dd0 /* ctl 164 */,
0x0000004d /* ctl 165 */,
0x00000000 /* ctl 166 */,
0x06060606 /* ctl 167 */,
0x01000000 /* ctl 168 */,
- 0x00000001 /* ctl 169 */,
+ 0x01010001 /* ctl 169 */,
0x00000000 /* ctl 170 */,
0x01000000 /* ctl 171 */,
0x00000001 /* ctl 172 */,
@@ -644,7 +644,7 @@
0x01000000 /* pi 70 */,
0x04040401 /* pi 71 */,
0x0a000004 /* pi 72 */,
- 0x01010128 /* pi 73 */,
+ 0x01000028 /* pi 73 */,
0x00000001 /* pi 74 */,
0x00000000 /* pi 75 */,
0x00030003 /* pi 76 */,
@@ -663,8 +663,8 @@
0x00000000 /* pi 89 */,
0x001e0303 /* pi 90 */,
0x000007d0 /* pi 91 */,
- 0x01010300 /* pi 92 */,
- 0x01010101 /* pi 93 */,
+ 0x00000300 /* pi 92 */,
+ 0x01010000 /* pi 93 */,
0x00000101 /* pi 94 */,
0x00000000 /* pi 95 */,
0x00000000 /* pi 96 */,
@@ -688,7 +688,7 @@
0x00120024 /* pi 114 */,
0x00000000 /* pi 115 */,
0x00000000 /* pi 116 */,
- 0x01010100 /* pi 117 */,
+ 0x01010000 /* pi 117 */,
0x00000001 /* pi 118 */,
0x010a140a /* pi 119 */,
0x00010011 /* pi 120 */,
@@ -719,7 +719,7 @@
0x34000000 /* pi 145 */,
0x00000000 /* pi 146 */,
0x00000000 /* pi 147 */,
- 0x01010000 /* pi 148 */,
+ 0x00000000 /* pi 148 */,
0x00000101 /* pi 149 */,
0x31000600 /* pi 150 */,
0x064d4d00 /* pi 151 */,
@@ -766,7 +766,7 @@
},
{
0x76543210 /* phy 0 */,
- 0x0004f008 /* phy 1 */,
+ 0x00051008 /* phy 1 */,
0x00020133 /* phy 2 */,
0x00000000 /* phy 3 */,
0x00000000 /* phy 4 */,
@@ -779,7 +779,7 @@
0x00000000 /* phy 11 */,
0x00000000 /* phy 12 */,
0x00000100 /* phy 13 */,
- 0x001700c0 /* phy 14 */,
+ 0x00170080 /* phy 14 */,
0x020100cc /* phy 15 */,
0x00030066 /* phy 16 */,
0x00000000 /* phy 17 */,
@@ -848,7 +848,7 @@
0x00800080 /* phy 80 */,
0x00800080 /* phy 81 */,
0x00800080 /* phy 82 */,
- 0x00010019 /* phy 83 */,
+ 0x00000019 /* phy 83 */,
0x000001d0 /* phy 84 */,
0x00000000 /* phy 85 */,
0x00000200 /* phy 86 */,
@@ -856,7 +856,7 @@
0x51816152 /* phy 88 */,
0xc0c08161 /* phy 89 */,
0x00010000 /* phy 90 */,
- 0x02001000 /* phy 91 */,
+ 0x0200100c /* phy 91 */,
0x0c0432ff /* phy 92 */,
0x000f0c18 /* phy 93 */,
0x01000140 /* phy 94 */,
@@ -894,7 +894,7 @@
0x00000000 /* phy 126 */,
0x00000000 /* phy 127 */,
0x76543210 /* phy 128 */,
- 0x0004f008 /* phy 129 */,
+ 0x00051008 /* phy 129 */,
0x00020133 /* phy 130 */,
0x00000000 /* phy 131 */,
0x00000000 /* phy 132 */,
@@ -907,7 +907,7 @@
0x00000000 /* phy 139 */,
0x00000000 /* phy 140 */,
0x00000100 /* phy 141 */,
- 0x001700c0 /* phy 142 */,
+ 0x00170080 /* phy 142 */,
0x020100cc /* phy 143 */,
0x00030066 /* phy 144 */,
0x00000000 /* phy 145 */,
@@ -976,7 +976,7 @@
0x00800080 /* phy 208 */,
0x00800080 /* phy 209 */,
0x00800080 /* phy 210 */,
- 0x00010019 /* phy 211 */,
+ 0x00000019 /* phy 211 */,
0x000001d0 /* phy 212 */,
0x00000000 /* phy 213 */,
0x00000200 /* phy 214 */,
@@ -984,7 +984,7 @@
0x51816152 /* phy 216 */,
0xc0c08161 /* phy 217 */,
0x00010000 /* phy 218 */,
- 0x02001000 /* phy 219 */,
+ 0x0200100c /* phy 219 */,
0x0c0432ff /* phy 220 */,
0x000f0c18 /* phy 221 */,
0x01000140 /* phy 222 */,
@@ -1022,7 +1022,7 @@
0x00000000 /* phy 254 */,
0x00000000 /* phy 255 */,
0x76543210 /* phy 256 */,
- 0x0004f008 /* phy 257 */,
+ 0x00051008 /* phy 257 */,
0x00020133 /* phy 258 */,
0x00000000 /* phy 259 */,
0x00000000 /* phy 260 */,
@@ -1035,7 +1035,7 @@
0x00000000 /* phy 267 */,
0x00000000 /* phy 268 */,
0x00000100 /* phy 269 */,
- 0x001700c0 /* phy 270 */,
+ 0x00170080 /* phy 270 */,
0x020100cc /* phy 271 */,
0x00030066 /* phy 272 */,
0x00000000 /* phy 273 */,
@@ -1104,7 +1104,7 @@
0x00800080 /* phy 336 */,
0x00800080 /* phy 337 */,
0x00800080 /* phy 338 */,
- 0x00010019 /* phy 339 */,
+ 0x00000019 /* phy 339 */,
0x000001d0 /* phy 340 */,
0x00000000 /* phy 341 */,
0x00000200 /* phy 342 */,
@@ -1112,7 +1112,7 @@
0x51816152 /* phy 344 */,
0xc0c08161 /* phy 345 */,
0x00010000 /* phy 346 */,
- 0x02001000 /* phy 347 */,
+ 0x0200100c /* phy 347 */,
0x0c0432ff /* phy 348 */,
0x000f0c18 /* phy 349 */,
0x01000140 /* phy 350 */,
@@ -1150,7 +1150,7 @@
0x00000000 /* phy 382 */,
0x00000000 /* phy 383 */,
0x76543210 /* phy 384 */,
- 0x0004f008 /* phy 385 */,
+ 0x00051008 /* phy 385 */,
0x00020133 /* phy 386 */,
0x00000000 /* phy 387 */,
0x00000000 /* phy 388 */,
@@ -1163,7 +1163,7 @@
0x00000000 /* phy 395 */,
0x00000000 /* phy 396 */,
0x00000100 /* phy 397 */,
- 0x001700c0 /* phy 398 */,
+ 0x00170080 /* phy 398 */,
0x020100cc /* phy 399 */,
0x00030066 /* phy 400 */,
0x00000000 /* phy 401 */,
@@ -1232,7 +1232,7 @@
0x00800080 /* phy 464 */,
0x00800080 /* phy 465 */,
0x00800080 /* phy 466 */,
- 0x00010019 /* phy 467 */,
+ 0x00000019 /* phy 467 */,
0x000001d0 /* phy 468 */,
0x00000000 /* phy 469 */,
0x00000200 /* phy 470 */,
@@ -1240,7 +1240,7 @@
0x51816152 /* phy 472 */,
0xc0c08161 /* phy 473 */,
0x00010000 /* phy 474 */,
- 0x02001000 /* phy 475 */,
+ 0x0200100c /* phy 475 */,
0x0c0432ff /* phy 476 */,
0x000f0c18 /* phy 477 */,
0x01000140 /* phy 478 */,
@@ -1311,7 +1311,7 @@
0x000300ce /* phy 543 */,
0x03000300 /* phy 544 */,
0x03000300 /* phy 545 */,
- 0x00000300 /* phy 546 */,
+ 0x000c0300 /* phy 546 */,
0xff020010 /* phy 547 */,
0x00000332 /* phy 548 */,
0x00000000 /* phy 549 */,
@@ -1439,7 +1439,7 @@
0x000300ce /* phy 671 */,
0x03000300 /* phy 672 */,
0x03000300 /* phy 673 */,
- 0x00000300 /* phy 674 */,
+ 0x000c0300 /* phy 674 */,
0xff020010 /* phy 675 */,
0x00000332 /* phy 676 */,
0x00000000 /* phy 677 */,
@@ -1567,7 +1567,7 @@
0x000300ce /* phy 799 */,
0x03000300 /* phy 800 */,
0x03000300 /* phy 801 */,
- 0x00000300 /* phy 802 */,
+ 0x000c0300 /* phy 802 */,
0xff020010 /* phy 803 */,
0x00000332 /* phy 804 */,
0x00000000 /* phy 805 */,
@@ -1695,7 +1695,7 @@
0x000300ce /* phy 927 */,
0x03000300 /* phy 928 */,
0x03000300 /* phy 929 */,
- 0x00000300 /* phy 930 */,
+ 0x000c0300 /* phy 930 */,
0xff020010 /* phy 931 */,
0x00000332 /* phy 932 */,
0x00000000 /* phy 933 */,
@@ -1818,12 +1818,12 @@
0x0f1f0f1f /* phy 1050 */,
0x03000003 /* phy 1051 */,
0x00000300 /* phy 1052 */,
- 0x0b221b02 /* phy 1053 */,
- 0x09240b22 /* phy 1054 */,
+ 0x07221702 /* phy 1053 */,
+ 0x07240722 /* phy 1054 */,
0x00000000 /* phy 1055 */,
0x00000000 /* phy 1056 */,
0x05030000 /* phy 1057 */,
- 0x14000001 /* phy 1058 */,
+ 0x14000801 /* phy 1058 */,
0x63c0ce00 /* phy 1059 */,
0x0000000e /* phy 1060 */,
0x001f0fc0 /* phy 1061 */,
@@ -1847,7 +1847,7 @@
0x00000000 /* phy 1079 */,
0x00000000 /* phy 1080 */,
0x00000000 /* phy 1081 */,
- 0x00000078 /* phy 1082 */,
+ 0x0000007a /* phy 1082 */,
0x00000000 /* phy 1083 */,
0x00010108 /* phy 1084 */,
0x00000000 /* phy 1085 */,
@@ -1870,19 +1870,27 @@
{
{ 83, 0x00020119 } /* setA */,
{ 90, 0x01020000 } /* setA */,
+ { 91, 0x02001000 } /* setA */,
{ 92, 0x0c053eff } /* setA */,
{ 211, 0x00020119 } /* setA */,
{ 218, 0x01020000 } /* setA */,
+ { 219, 0x02001000 } /* setA */,
{ 220, 0x0c053eff } /* setA */,
{ 339, 0x00020119 } /* setA */,
{ 346, 0x01020000 } /* setA */,
+ { 347, 0x02001000 } /* setA */,
{ 348, 0x0c053eff } /* setA */,
{ 467, 0x00020119 } /* setA */,
{ 474, 0x01020000 } /* setA */,
+ { 475, 0x02001000 } /* setA */,
{ 476, 0x0c053eff } /* setA */,
+ { 546, 0x00000300 } /* setA */,
{ 548, 0x0000033e } /* setA */,
+ { 674, 0x00000300 } /* setA */,
{ 676, 0x0000033e } /* setA */,
+ { 802, 0x00000300 } /* setA */,
{ 804, 0x0000033e } /* setA */,
+ { 930, 0x00000300 } /* setA */,
{ 932, 0x0000033e } /* setA */,
{ 1045, 0x01221102 } /* setA */,
{ 1046, 0x00000122 } /* setA */,
@@ -1893,22 +1901,30 @@
{ 83, 0x0003011a } /* setB */,
{ 85, 0x01000000 } /* setB */,
{ 90, 0x02030000 } /* setB */,
+ { 91, 0x02001000 } /* setB */,
{ 92, 0x0c073eff } /* setB */,
{ 211, 0x0003011a } /* setB */,
{ 213, 0x01000000 } /* setB */,
{ 218, 0x02030000 } /* setB */,
+ { 219, 0x02001000 } /* setB */,
{ 220, 0x0c073eff } /* setB */,
{ 339, 0x0003011a } /* setB */,
{ 341, 0x01000000 } /* setB */,
{ 346, 0x02030000 } /* setB */,
+ { 347, 0x02001000 } /* setB */,
{ 348, 0x0c073eff } /* setB */,
{ 467, 0x0003011a } /* setB */,
{ 469, 0x01000000 } /* setB */,
{ 474, 0x02030000 } /* setB */,
+ { 475, 0x02001000 } /* setB */,
{ 476, 0x0c073eff } /* setB */,
+ { 546, 0x00000300 } /* setB */,
{ 548, 0x0000033e } /* setB */,
+ { 674, 0x00000300 } /* setB */,
{ 676, 0x0000033e } /* setB */,
+ { 802, 0x00000300 } /* setB */,
{ 804, 0x0000033e } /* setB */,
+ { 930, 0x00000300 } /* setB */,
{ 932, 0x0000033e } /* setB */,
{ 1045, 0x01221102 } /* setB */,
{ 1046, 0x00000122 } /* setB */,
diff --git a/drivers/misc/mnh/mnh-ddr.c b/drivers/misc/mnh/mnh-ddr.c
index 47f04c0..5d9a937 100644
--- a/drivers/misc/mnh/mnh-ddr.c
+++ b/drivers/misc/mnh/mnh-ddr.c
@@ -1,7 +1,7 @@
/*
*
* MNH DDR Driver
-* Copyright (c) 2016-2017, Intel Corporation.
+* Copyright (c) 2016-2018, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -28,48 +28,52 @@
#define MNH_DDR_CTL_IN(reg) \
HW_IN(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, reg)
-#define MNH_DDR_CTL_INf(...) \
- HW_INf(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, __VA_ARGS__)
-#define MNH_DDR_CTL_OUT(...) \
- HW_OUT(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, __VA_ARGS__)
-#define MNH_DDR_CTL_OUTf(...) \
- HW_OUTf(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, __VA_ARGS__)
+#define MNH_DDR_CTL_INf(reg, fld) \
+ HW_INf(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, reg, fld)
+#define MNH_DDR_CTL_OUT(reg, val) \
+ HW_OUT(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, reg, val)
+#define MNH_DDR_CTL_OUTf(reg, fld, val) \
+ HW_OUTf(HWIO_DDR_CTL_BASE_ADDR, DDR_CTL, reg, fld, val)
-#define MNH_DDR_PI_INf(...) \
- HW_INf(HWIO_DDR_PI_BASE_ADDR, DDR_PI, __VA_ARGS__)
-#define MNH_DDR_PI_OUTf(...) \
- HW_OUTf(HWIO_DDR_PI_BASE_ADDR, DDR_PI, __VA_ARGS__)
-#define MNH_DDR_PI_OUT(...) \
- HW_OUT(HWIO_DDR_PI_BASE_ADDR, DDR_PI, __VA_ARGS__)
+#define MNH_DDR_PI_INf(reg, fld) \
+ HW_INf(HWIO_DDR_PI_BASE_ADDR, DDR_PI, reg, fld)
+#define MNH_DDR_PI_OUTf(reg, fld, val) \
+ HW_OUTf(HWIO_DDR_PI_BASE_ADDR, DDR_PI, reg, fld, val)
+#define MNH_DDR_PI_OUT(reg, val) \
+ HW_OUT(HWIO_DDR_PI_BASE_ADDR, DDR_PI, reg, val)
-#define MNH_DDR_PHY_INf(...) \
- HW_INf(HWIO_DDR_PHY_BASE_ADDR, DDR_PHY, __VA_ARGS__)
-#define MNH_DDR_PHY_OUTf(...) \
- HW_OUTf(HWIO_DDR_PHY_BASE_ADDR, DDR_PHY, __VA_ARGS__)
-#define MNH_DDR_PHY_OUT(...) \
- HW_OUT(HWIO_DDR_PHY_BASE_ADDR, DDR_PHY, __VA_ARGS__)
+#define MNH_DDR_PHY_INf(reg, fld) \
+ HW_INf(HWIO_DDR_PHY_BASE_ADDR, DDR_PHY, reg, fld)
+#define MNH_DDR_PHY_IN(reg) \
+ HW_IN(HWIO_DDR_PHY_BASE_ADDR, DDR_PHY, reg)
+#define MNH_DDR_PHY_OUTf(reg, fld, val) \
+ HW_OUTf(HWIO_DDR_PHY_BASE_ADDR, DDR_PHY, reg, fld, val)
+#define MNH_DDR_PHY_OUT(reg, val) \
+ HW_OUT(HWIO_DDR_PHY_BASE_ADDR, DDR_PHY, reg, val)
#define MNH_SCU_IN(reg) \
HW_IN(HWIO_SCU_BASE_ADDR, SCU, reg)
-#define MNH_SCU_INf(...) \
- HW_INf(HWIO_SCU_BASE_ADDR, SCU, __VA_ARGS__)
-#define MNH_SCU_INx(...) \
- HW_INx(HWIO_SCU_BASE_ADDR, SCU, __VA_ARGS__)
-#define MNH_SCU_INxf(...) \
- HW_INxf(HWIO_SCU_BASE_ADDR, SCU, __VA_ARGS__)
-#define MNH_SCU_OUTf(...) \
- HW_OUTf(HWIO_SCU_BASE_ADDR, SCU, __VA_ARGS__)
-#define MNH_SCU_OUT(...) \
- HW_OUT(HWIO_SCU_BASE_ADDR, SCU, __VA_ARGS__)
-#define MNH_SCU_OUTx(...) \
- HW_OUTx(HWIO_SCU_BASE_ADDR, SCU, __VA_ARGS__)
+#define MNH_SCU_INf(reg, fld) \
+ HW_INf(HWIO_SCU_BASE_ADDR, SCU, reg, fld)
+#define MNH_SCU_INx(reg, inst) \
+ HW_INx(HWIO_SCU_BASE_ADDR, SCU, reg, inst)
+#define MNH_SCU_INxf(reg, inst, fld) \
+ HW_INxf(HWIO_SCU_BASE_ADDR, SCU, reg, inst, fld)
+#define MNH_SCU_OUTf(reg, fld, val) \
+ HW_OUTf(HWIO_SCU_BASE_ADDR, SCU, reg, fld, val)
+#define MNH_SCU_OUT(reg, val) \
+ HW_OUT(HWIO_SCU_BASE_ADDR, SCU, reg, val)
+#define MNH_SCU_OUTx(reg, inst, val) \
+ HW_OUTx(HWIO_SCU_BASE_ADDR, SCU, reg, inst, val)
+#define MNH_SCU_OUTxf(reg, inst, fld, val) \
+ HW_OUTxf(HWIO_SCU_BASE_ADDR, SCU, reg, inst, fld, val)
#define MNH_RSTC_INf(fld) \
HW_INf(HWIO_SCU_BASE_ADDR, SCU, RSTC, fld)
-#define MNH_RSTC_OUTf(...) \
- HW_OUTf(HWIO_SCU_BASE_ADDR, SCU, RSTC, __VA_ARGS__)
+#define MNH_RSTC_OUTf(fld, val) \
+ HW_OUTf(HWIO_SCU_BASE_ADDR, SCU, RSTC, fld, val)
-#define WRITE_DDR_REG_CONFIG(_state, ddrblock, regindex) \
+#define WRITE_DDR_REG_CONFIG(ddrblock, regindex) \
do { \
if (_state->ddrblock[regindex]) { \
mnh_reg_write(_state->ddrblock##_base + \
@@ -78,7 +82,7 @@
} \
} while (0)
-#define WRITE_DDR_PHY_CONFIG(_state, fsp, regindex) \
+#define WRITE_DDR_PHY_CONFIG(fsp, regindex) \
do { \
if (_state->phy[fsp][regindex]) { \
mnh_reg_write(_state->phy_base + (regindex * sizeof(u32)), \
@@ -86,92 +90,178 @@
} \
} while (0)
-#define WRITE_SET_ELEMENT(_state, regindex, regvalue) \
+#define WRITE_SET_ELEMENT(regindex, regvalue) \
mnh_reg_write(_state->phy_base + (regindex * sizeof(u32)),\
regvalue)
-#define WRITE_SCU_FSP(_state, fsp) \
+#define WRITE_SCU_FSP(fsp) \
do { \
_state->fsps[fsp] &= 0xFFFFFF00;\
_state->fsps[fsp] |= 0x7d;\
MNH_SCU_OUTx(LPDDR4_FSP_SETTING, fsp, _state->fsps[fsp]); \
} while (0)
-#define SAVE_CURRENT_FSP(dev, _state) \
-do { \
- _state->suspend_fsp = \
- MNH_SCU_INf(LPDDR4_LOW_POWER_STS, LPDDR4_CUR_FSP); \
- dev_dbg(dev, "%s: saved fsp: %d\n", __func__, _state->suspend_fsp); \
-} while (0)
+#define WRITE_CLK_FROM_FSP(fsp) mnh_ddr_write_clk_from_fsp(fsp, 1)
+#define WRITE_CLK_FROM_FSP_NO_LOCK(fsp) mnh_ddr_write_clk_from_fsp(fsp, 0)
-#define SAVED_FSP(_state) _state->suspend_fsp
-
-#define WRITE_CLK_FROM_FSP(dev, _state, fsp) \
-do { \
- if (fsp < (MNH_DDR_NUM_FSPS)) { \
- MNH_SCU_OUTf(CCU_CLK_DIV, LPDDR4_REFCLK_DIV, \
- MNH_SCU_INxf(LPDDR4_FSP_SETTING, fsp, \
- FSP_LPDDR4_REFCLK_DIV)); \
- MNH_SCU_OUTf(CCU_CLK_DIV, AXI_FABRIC_CLK_DIV, \
- MNH_SCU_INxf(LPDDR4_FSP_SETTING, fsp, \
- FSP_AXI_FABRIC_CLK_DIV)); \
- MNH_SCU_OUTf(CCU_CLK_DIV, PCIE_AXI_CLK_DIV, \
- MNH_SCU_INxf(LPDDR4_FSP_SETTING, fsp, \
- FSP_PCIE_AXI_CLK_DIV)); \
- MNH_SCU_OUTf(CCU_CLK_CTL, LP4_AXI_SYS200_MODE, \
- MNH_SCU_INxf(LPDDR4_FSP_SETTING, fsp, \
- FSP_SYS200_MODE)); \
- } else \
- dev_err(dev, "%s: invalid fsp 0x%x", __func__, fsp); \
-} while (0)
-
-#define SAVE_DDR_REG_CONFIG(_state, ddrblock, regindex) \
+#define SAVE_DDR_REG_CONFIG(ddrblock, regindex) \
do { \
_state->ddrblock[regindex] = \
mnh_reg_read(_state->ddrblock##_base + \
- (regindex * sizeof(u32))); \
+ ((regindex) * sizeof(u32))); \
} while (0)
-#define SAVE_DDR_PHY_REG_CONFIG(_state, fsp, regindex) \
+#define SAVE_DDR_PHY_REG_CONFIG(fsp, regindex) \
do { \
_state->phy[fsp][regindex] = \
- mnh_reg_read(_state->phy_base + (regindex * sizeof(u32))); \
+ mnh_reg_read(_state->phy_base + ((regindex) * sizeof(u32))); \
} while (0)
-#define CLR_START(_state, ddrblock) (_state->ddrblock[0] &= (0xFFFFFFFE))
+#define CLR_START(ddrblock) (_state->ddrblock[0] &= (0xFFFFFFFE))
/* timeout for training all FSPs */
#define TRAINING_TIMEOUT msecs_to_jiffies(45)
+#define RESUME_TIMEOUT msecs_to_jiffies(7)
+#define MNH_DDR_ASSERT_ISO_N() \
+ do { \
+ gpiod_set_value_cansleep(_state->iso_n, 0); \
+ udelay(20); \
+ } while (0)
+
+#define MNH_DDR_DEASSERT_ISO_N() \
+ do { \
+ gpiod_set_value_cansleep(_state->iso_n, 1); \
+ udelay(20); \
+ } while (0)
+
+#define LP_CMD_FREQ_SWITCH 0x8A
#define LP_CMD_EXIT_LP 0x81
#define LP_CMD_DSRPD 0xFE
+#define LP_CMD_SRPD 0x3A
+#define LP_CMD_EXIT_SRPD 0x01
/* INT status bits */
+#define DFS_COMPLETE_SBIT 31
+#define DFI_STATE_CHANGE_SBIT 28
+#define INHIBIT_DRAM_CMD_SBIT 27
#define MR_WRITE_SBIT 26
#define MR_READ_SBIT 23
+#define DFI_UPDATE_ERROR_SBIT 13
#define BIST_SBIT 6
#define LP_CMD_SBIT 5
#define INIT_DONE_SBIT 4
+/* PI_INT_STATUS bits */
+#define PI_CONTROL_ERROR_BIT 1
+#define PI_INIT_DONE_BIT 0
+
+static struct mnh_ddr_internal_state *_state;
+
+static void mnh_ddr_disable_lp(void);
+static void mnh_ddr_enable_lp(void);
+
+/*
+ * Write the clk dividers from given FSP index.
+ * fsp: the fsp index [0-3]
+ * pll_freeze: define whether the function uses HW PLL freeze funtionality
+ * inside the function to set all the dividers in one operation (with unfreeze)
+ * 0 to set it off
+ * 1 to set it on
+ */
+void mnh_ddr_write_clk_from_fsp(unsigned int fsp, int pll_freeze)
+{
+ if (fsp >= MNH_DDR_NUM_FSPS) {
+ pr_err("%s invalid fsp 0x%x", __func__, fsp);
+ return;
+ }
+
+ if (pll_freeze) {
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x4CD9);
+ MNH_SCU_OUTf(LPDDR4_REFCLK_PLL_CTRL, FRZ_PLL_IN, 1);
+ }
+ MNH_SCU_OUTf(CCU_CLK_DIV, LPDDR4_REFCLK_DIV,
+ MNH_SCU_INxf(LPDDR4_FSP_SETTING, fsp, FSP_LPDDR4_REFCLK_DIV));
+ MNH_SCU_OUTf(CCU_CLK_DIV, AXI_FABRIC_CLK_DIV,
+ MNH_SCU_INxf(LPDDR4_FSP_SETTING, fsp, FSP_AXI_FABRIC_CLK_DIV));
+ MNH_SCU_OUTf(CCU_CLK_DIV, PCIE_AXI_CLK_DIV,
+ MNH_SCU_INxf(LPDDR4_FSP_SETTING, fsp, FSP_PCIE_AXI_CLK_DIV));
+ MNH_SCU_OUTf(CCU_CLK_CTL, LP4_AXI_SYS200_MODE,
+ MNH_SCU_INxf(LPDDR4_FSP_SETTING, fsp, FSP_SYS200_MODE));
+ if (pll_freeze) {
+ MNH_SCU_OUTf(LPDDR4_REFCLK_PLL_CTRL, FRZ_PLL_IN, 0);
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0);
+ }
+}
+
+static u32 mnh_ddr_sanity_check(void)
+{
+ /* just verify comm is actually up */
+ u32 val = MNH_DDR_CTL_IN(00);
+
+ /*
+ * If above register reads either 0 or all FF, it indicates that
+ * access to DDR CTL registers are not ready.
+ */
+ if ((val == 0) || (val == 0xFFFFFFFF))
+ return 0;
+ else
+ return 1;
+}
+
/* read entire int_status */
-u64 mnh_ddr_int_status(struct device *dev)
+u64 mnh_ddr_int_status(void)
{
u64 int_stat = ((u64)MNH_DDR_CTL_IN(228) << 32) | MNH_DDR_CTL_IN(227);
return int_stat;
}
EXPORT_SYMBOL(mnh_ddr_int_status);
+int mnh_ddr_print_phy_status(void)
+{
+ int ret = 0;
+ /* call from a context where lp has already been disabled
+ * so ctl and phy reg can be accessed. don't do it here
+ */
+ if ((MNH_DDR_PHY_IN(00) != 0x76543210) ||
+ (MNH_DDR_PHY_IN(256) != 0x76543210) ||
+ (MNH_DDR_PHY_IN(384) != 0x76543210)) {
+ pr_err("%s ERROR PHY 00: 0x%08x 256: 0x%08x 384: 0x%08x\n",
+ __func__,
+ MNH_DDR_PHY_IN(00),
+ MNH_DDR_PHY_IN(256),
+ MNH_DDR_PHY_IN(384));
+ ret = -1;
+ }
+
+ if (MNH_DDR_PHY_INf(1099, PHY_AC_INIT_COMPLETE_OBS) != 0x000003f1) {
+ pr_info("%s PHY_AC_INIT_COMPLETE_OBS: 0x%08x\n",
+ __func__, MNH_DDR_PHY_INf(1099,
+ PHY_AC_INIT_COMPLETE_OBS));
+ ret = -1;
+ }
+ if (MNH_DDR_PHY_INf(1100, PHY_DS_INIT_COMPLETE_OBS) != 0x0000000f) {
+ pr_info("%s PHY_DS_INIT_COMPLETE_OBS: 0x%08x\n",
+ __func__, MNH_DDR_PHY_INf(1100,
+ PHY_DS_INIT_COMPLETE_OBS));
+ ret = -1;
+ }
+ return ret;
+}
+EXPORT_SYMBOL(mnh_ddr_print_phy_status);
+
+
/* clear entire int_status */
-int mnh_ddr_clr_int_status(struct device *dev)
+int mnh_ddr_clr_int_status(void)
{
u64 stat = 0;
- MNH_DDR_CTL_OUT(230, 0x0F);
MNH_DDR_CTL_OUT(229, 0xFFFFFFFF);
- stat = mnh_ddr_int_status(dev);
+ MNH_DDR_CTL_OUT(230, 0x0F);
+ stat = mnh_ddr_int_status();
if (stat) {
- dev_err(dev, "%s: int stat not all clear: %llx\n", __func__,
- stat);
+ pr_err("%s: int stat not all clear: %llx\n",
+ __func__, stat);
return -EIO;
}
return 0;
@@ -202,7 +292,7 @@
}
/* clear single bit in int_status */
-static int mnh_ddr_clr_int_status_bit(struct device *dev, u8 sbit)
+static int mnh_ddr_clr_int_status_bit(u8 sbit)
{
const u32 max_int_status_bit = 35;
const u32 first_upper_bit = 32;
@@ -216,17 +306,33 @@
MNH_DDR_CTL_OUT(229, 1 << sbit);
if (mnh_ddr_int_status_bit(sbit)) {
- dev_err(dev, "%s: bit %d is still set.\n", __func__, sbit);
+ pr_err("%s: bit %d is still set.\n", __func__, sbit);
return -EIO;
}
return 0;
}
-static int mnh_ddr_send_lp_cmd(struct device *dev, u8 cmd)
+/* read single bit in PI_INT_STATUS */
+static u32 mnh_ddr_pi_int_status_bit(u8 sbit)
+{
+ u32 status = 0;
+ const u32 max_int_status_bit = 24;
+
+ if (sbit > max_int_status_bit)
+ return -EINVAL;
+
+ status = MNH_DDR_PI_INf(172, PI_INT_STATUS);
+ pr_debug("%s: PI_INT_STATUS = 0x%x.\n", __func__, status);
+
+ status &= (1 << sbit);
+ return status;
+}
+
+static int mnh_ddr_send_lp_cmd(u8 cmd)
{
u32 timeout = 100000;
- dev_dbg(dev, "%s sending cmd: 0x%x\n", __func__, cmd);
+ pr_debug("%s sending cmd: 0x%x\n", __func__, cmd);
MNH_DDR_CTL_OUTf(112, LP_CMD, cmd);
while (!mnh_ddr_int_status_bit(LP_CMD_SBIT) && --timeout)
@@ -235,29 +341,85 @@
if (!mnh_ddr_int_status_bit(LP_CMD_SBIT))
return -ETIMEDOUT;
- return mnh_ddr_clr_int_status_bit(dev, LP_CMD_SBIT);
+ return mnh_ddr_clr_int_status_bit(LP_CMD_SBIT);
+}
+
+/*
+ * Both chip 0 and chip 1 are written.
+ */
+int mnh_ddr_write_mode_reg(u8 modereg, u8 modevalue)
+{
+ const u64 writeable = 0x0000010101D3FE1E;
+ u32 val = 0;
+ unsigned long timeout = 0;
+ int ret = 0;
+
+ if ((modereg >= 64) ||
+ ((writeable & (1ULL << modereg)) == 0)) {
+ pr_err("%s %d is not writeable.\n",
+ __func__, modereg);
+ return -EIO;
+ }
+
+ pr_debug("%s LP_STATE is 0x%x\n",
+ __func__, MNH_DDR_CTL_INf(121, LP_STATE));
+ val = 0xFF & modereg;
+
+ /*
+ * bit 24 indicates all chip selects
+ * bit 23 indicates indicates a single mode reg
+ */
+ val |= (1 << 23) | (1 << 24);
+ MNH_DDR_CTL_OUTf(140, WRITE_MODEREG, val);
+ MNH_DDR_CTL_OUTf(160, MRSINGLE_DATA_0, modevalue);
+ /* trigger write */
+ val |= (1 << 25);
+ MNH_DDR_CTL_OUTf(140, WRITE_MODEREG, val);
+
+ timeout = jiffies + msecs_to_jiffies(500);
+ while (!mnh_ddr_int_status_bit(MR_WRITE_SBIT) &&
+ time_before(jiffies, timeout)) {
+ udelay(100);
+ }
+
+ if (mnh_ddr_int_status_bit(MR_WRITE_SBIT)) {
+ mnh_ddr_clr_int_status_bit(MR_WRITE_SBIT);
+ } else {
+ pr_err("%s timeout on MR write done. %llx.",
+ __func__, mnh_ddr_int_status());
+ ret = -EIO;
+ }
+ val = MNH_DDR_CTL_INf(141, MRW_STATUS);
+ if (val) {
+ pr_err("%s ERROR status: 0x%x", __func__, val);
+ ret = -EIO;
+ }
+
+ return ret;
}
static void mnh_ddr_enable_lp(void)
{
MNH_DDR_CTL_OUTf(124, LP_AUTO_SR_MC_GATE_IDLE, 0xFF);
- MNH_DDR_CTL_OUTf(122, LP_AUTO_MEM_GATE_EN, 0x4);
- MNH_DDR_CTL_OUTf(122, LP_AUTO_ENTRY_EN, 0x4);
- MNH_DDR_CTL_OUTf(122, LP_AUTO_EXIT_EN, 0xF);
+ if (MNH_DDR_CTL_INf(122, LP_AUTO_EXIT_EN) == 0)
+ MNH_DDR_CTL_OUTf(122, LP_AUTO_EXIT_EN, 0xF);
+ if (MNH_DDR_CTL_INf(122, LP_AUTO_MEM_GATE_EN) == 0)
+ MNH_DDR_CTL_OUTf(122, LP_AUTO_MEM_GATE_EN, 0x4);
+ if (MNH_DDR_CTL_INf(122, LP_AUTO_ENTRY_EN) == 0)
+ MNH_DDR_CTL_OUTf(122, LP_AUTO_ENTRY_EN, 0x4);
}
-static void mnh_ddr_disable_lp(struct device *dev)
+static void mnh_ddr_disable_lp(void)
{
- MNH_DDR_CTL_OUTf(124, LP_AUTO_SR_MC_GATE_IDLE, 0x00);
- MNH_DDR_CTL_OUTf(122, LP_AUTO_MEM_GATE_EN, 0x0);
MNH_DDR_CTL_OUTf(122, LP_AUTO_ENTRY_EN, 0x0);
- MNH_DDR_CTL_OUTf(122, LP_AUTO_EXIT_EN, 0x0);
- mnh_ddr_send_lp_cmd(dev, LP_CMD_EXIT_LP);
+ mnh_ddr_send_lp_cmd(LP_CMD_EXIT_LP);
}
static void mnh_ddr_init_internal_state(struct mnh_ddr_internal_state *_state,
- const struct mnh_ddr_reg_config *cfg)
+ const struct mnh_ddr_reg_config *cfg,
+ struct gpio_desc *iso_n)
{
+ _state->iso_n = iso_n;
_state->ctl_base = HWIO_DDR_CTL_BASE_ADDR;
_state->pi_base = HWIO_DDR_PI_BASE_ADDR;
_state->phy_base = HWIO_DDR_PHY_BASE_ADDR;
@@ -278,18 +440,14 @@
&(cfg->pi[0]),
MNH_DDR_NUM_PI_REG * sizeof(u32));
- _state->suspend_fsp = 0;
_state->tref[0] = cfg->ctl[56] & 0xFFFF;
_state->tref[1] = cfg->ctl[57] & 0xFFFF;
_state->tref[2] = cfg->ctl[58] & 0xFFFF;
_state->tref[3] = cfg->ctl[59] & 0xFFFF;
}
-static void mnh_ddr_init_clocks(struct mnh_ddr_data *data)
+static void mnh_ddr_init_clocks(struct device *dev, int fsp)
{
- struct device *dev = &data->pdev->dev;
- struct mnh_ddr_internal_state *_state = &data->_state;
-
int timeout = 0;
/* MNH_PLL_PASSCODE_SET */
@@ -312,44 +470,327 @@
dev_dbg(dev, "%s lpddr4 pll locked after %d iterations",
__func__, timeout);
- WRITE_SCU_FSP(_state, 0);
- WRITE_SCU_FSP(_state, 1);
- WRITE_SCU_FSP(_state, 2);
- WRITE_SCU_FSP(_state, 3);
+ /* WA for old HW bug to keep AXI, PCIE_AXI clk divs as nonzero
+ * during the first FSP switch
+ */
+ MNH_SCU_OUTf(CCU_CLK_DIV, AXI_FABRIC_CLK_DIV, 0x1);
+ MNH_SCU_OUTf(CCU_CLK_DIV, PCIE_AXI_CLK_DIV, 0x3);
- WRITE_CLK_FROM_FSP(dev, _state, SAVED_FSP(_state));
+ WRITE_SCU_FSP(0);
+ WRITE_SCU_FSP(1);
+ WRITE_SCU_FSP(2);
+ WRITE_SCU_FSP(3);
+
+ WRITE_CLK_FROM_FSP(fsp);
dev_dbg(dev, "%s lpddr4 pll locked", __func__);
MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG, LP4_FSP_SW_OVERRIDE, 0);
/* MNH_PLL_PASSCODE_CLR */
MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x0);
}
-static void mnh_ddr_pull_config(struct mnh_ddr_data *data)
+static void mnh_ddr_clear_lpc_status(void)
{
- struct mnh_ddr_internal_state *_state = &data->_state;
-
- int index, fsp;
- for (index = 0; index < MNH_DDR_NUM_CTL_REG; index++)
- SAVE_DDR_REG_CONFIG(_state, ctl, index);
- CLR_START(_state, ctl);
-
- for (index = 0; index < MNH_DDR_NUM_PI_REG; index++)
- SAVE_DDR_REG_CONFIG(_state, pi, index);
- CLR_START(_state, pi);
-
- for (fsp = 0; fsp < MNH_DDR_NUM_FSPS; fsp++) {
- MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, fsp);
- for (index = 0; index < MNH_DDR_NUM_PHY_REG; index++)
- SAVE_DDR_PHY_REG_CONFIG(_state, fsp, index);
+ /* Paranoia */
+ if (MNH_SCU_INf(SCU_IRQ_STATUS, LP4_FREQ_CHG_REQ)) {
+ pr_info("%s LP4_FREQ_CHG_REQ already set, clearing", __func__);
+ MNH_SCU_OUTf(SCU_IRQ_STATUS, LP4_FREQ_CHG_REQ, 1);
+ }
+ if (MNH_SCU_INf(SCU_IRQ_STATUS, LP4_LPC_CMD_DONE)) {
+ pr_info("%s LP4_LPC_CMD_DONE already set, clearing", __func__);
+ MNH_SCU_OUTf(SCU_IRQ_STATUS, LP4_LPC_CMD_DONE, 1);
+ }
+ if (MNH_SCU_INf(LPDDR4_LOW_POWER_STS, LPC_CMD_RSP)) {
+ pr_info("%s LPC_CMD_RSP already set, clearing", __func__);
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_STS, LPC_CMD_RSP, 1);
+ }
+ if (MNH_SCU_INf(LPDDR4_LOW_POWER_STS, LPC_CMD_DONE)) {
+ pr_info("%s LPC_CMD_DONE already set, clearing", __func__);
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_STS, LPC_CMD_DONE, 1);
}
}
-int mnh_ddr_suspend(struct mnh_ddr_data *data, struct gpio_desc *iso_n)
-{
- struct device *dev = &data->pdev->dev;
- struct mnh_ddr_internal_state *_state = &data->_state;
+#define MR_TABLE_LEN 5
+const u8 mrw_fsps[MNH_DDR_NUM_FSPS][MR_TABLE_LEN][2] = {
+ {
+ { 1, 0x06 },
+ { 2, 0x00 },
+ { 3, 0x31 },
+ { 11, 0x00 },
+ { 22, 0x00 }
+ },
+ {
+ { 1, 0x06 },
+ { 2, 0x00 },
+ { 3, 0x31 },
+ { 11, 0x00 },
+ { 22, 0x00 },
+ },
+ {
+ { 1, 0x26 },
+ { 2, 0x12 },
+ { 3, 0x31 },
+ { 11, 0x00 },
+ { 22, 0x00 },
+ },
+ {
+ { 1, 0x46 },
+ { 2, 0x24 },
+ { 3, 0x31 },
+ { 11, 0x00 },
+ { 22, 0x00 },
+ }
+};
- mnh_ddr_disable_lp(dev);
+int mnh_ddr_sw_switch(int index)
+{
+ static int iteration;
+ u8 fsop, fswr;
+ u8 mr13val;
+ int old_lpi_wakeup_en, show_log, timeout;
+ int i, ret = -EIO;
+
+ uint16_t upd_high[MNH_DDR_NUM_FSPS];
+ uint16_t upd_norm[MNH_DDR_NUM_FSPS];
+
+ if ((index < 0) || (index >= MNH_DDR_NUM_FSPS)) {
+ pr_err("%s %d is not a valid FSP\n",
+ __func__, index);
+ return -EINVAL;
+ } else if (MNH_DDR_CTL_INf(133, CURRENT_REG_COPY) == index) {
+ pr_info("%s %d is already in use - skipping\n",
+ __func__, index);
+ return 0;
+ }
+ show_log = iteration++ % 1000;
+ if ((show_log == 0) || (show_log == 1)) {
+ pr_info("%s #%d fsp %d -> %d DLL RESET\n",
+ __func__, (iteration - 1),
+ MNH_DDR_CTL_INf(133, CURRENT_REG_COPY), index);
+ }
+
+ if (!MNH_SCU_INxf(LPDDR4_FSP_SETTING, index, FSP_SYS200_MODE))
+ mnh_lpddr_sys200_mode(false);
+
+ old_lpi_wakeup_en = MNH_DDR_CTL_INf(120, LPI_WAKEUP_EN);
+ /* need to make sure to disable lp, so phy regs
+ * and DRAM mode regs can be accessed.
+ */
+ mnh_ddr_disable_lp();
+ mnh_ddr_clr_int_status();
+
+ /* set software control */
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x4CD9);
+ MNH_SCU_OUTxf(LPDDR4_FSP_SETTING, index, FSP_SW_CTRL, 1);
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0);
+
+ mnh_ddr_clear_lpc_status();
+
+ /* step 0 */
+ MNH_DDR_CTL_OUTf(221, INHIBIT_DRAM_CMD, 3);
+ MNH_DDR_CTL_OUTf(120, LPI_WAKEUP_EN, 0);
+ udelay(10);
+ MNH_DDR_CTL_OUTf(54, AREFRESH, 1);
+ /* CDNS added this line */
+ MNH_DDR_PHY_OUTf(1098, PHY_INIT_UPDATE_CONFIG, 0);
+
+ timeout = 1000;
+ udelay(1); /* CDNS addition start */
+ MNH_DDR_CTL_OUTf(112, LP_CMD, 1);
+ while (!mnh_ddr_int_status_bit(LP_CMD_SBIT) &&
+ timeout-- > 0) {
+ udelay(1);
+ }
+ if (mnh_ddr_clr_int_status_bit(LP_CMD_SBIT)) {
+ pr_err("%s %d LP_CMD not clearing\n",
+ __func__, __LINE__);
+ ret = -EIO;
+ goto sw_switch_error_exit;
+ } /* CDNS addition end */
+
+ timeout = 1000;
+ while (!mnh_ddr_int_status_bit(INHIBIT_DRAM_CMD_SBIT) && timeout-- > 0)
+ udelay(1);
+ if (mnh_ddr_clr_int_status_bit(INHIBIT_DRAM_CMD_SBIT)) {
+ pr_err("%s %d INHIBIT not clearing\n",
+ __func__, __LINE__);
+ ret = -EIO;
+ goto sw_switch_error_exit;
+ }
+
+ MNH_DDR_CTL_OUTf(223, CTRLUPD_REQ_PER_AREF_EN, 0);
+ MNH_DDR_CTL_OUTf(525, CTRLUPD_AREF_HP_ENABLE, 0);
+ MNH_DDR_PHY_OUTf(1100, PHY_UPDATE_MASK, 1);
+ /* step 1 */
+ upd_high[0] = MNH_DDR_CTL_INf(88, UPD_CTRLUPD_HIGH_THRESHOLD_F0);
+ upd_norm[0] = MNH_DDR_CTL_INf(88, UPD_CTRLUPD_NORM_THRESHOLD_F0);
+ upd_high[1] = MNH_DDR_CTL_INf(91, UPD_CTRLUPD_HIGH_THRESHOLD_F1);
+ upd_norm[1] = MNH_DDR_CTL_INf(90, UPD_CTRLUPD_NORM_THRESHOLD_F1);
+ upd_high[2] = MNH_DDR_CTL_INf(93, UPD_CTRLUPD_HIGH_THRESHOLD_F2);
+ upd_norm[2] = MNH_DDR_CTL_INf(93, UPD_CTRLUPD_NORM_THRESHOLD_F2);
+ upd_high[3] = MNH_DDR_CTL_INf(96, UPD_CTRLUPD_HIGH_THRESHOLD_F3);
+ upd_norm[3] = MNH_DDR_CTL_INf(95, UPD_CTRLUPD_NORM_THRESHOLD_F3);
+
+ MNH_DDR_CTL_OUTf(88, UPD_CTRLUPD_HIGH_THRESHOLD_F0, 0);
+ MNH_DDR_CTL_OUTf(88, UPD_CTRLUPD_NORM_THRESHOLD_F0, 0);
+ MNH_DDR_CTL_OUTf(91, UPD_CTRLUPD_HIGH_THRESHOLD_F1, 0);
+ MNH_DDR_CTL_OUTf(90, UPD_CTRLUPD_NORM_THRESHOLD_F1, 0);
+ MNH_DDR_CTL_OUTf(93, UPD_CTRLUPD_HIGH_THRESHOLD_F2, 0);
+ MNH_DDR_CTL_OUTf(93, UPD_CTRLUPD_NORM_THRESHOLD_F2, 0);
+ MNH_DDR_CTL_OUTf(96, UPD_CTRLUPD_HIGH_THRESHOLD_F3, 0);
+ MNH_DDR_CTL_OUTf(95, UPD_CTRLUPD_NORM_THRESHOLD_F3, 0);
+
+ fsop = MNH_DDR_CTL_INf(169, FSP_OP_CURRENT);
+ fswr = !MNH_DDR_CTL_INf(169, FSP_WR_CURRENT);
+
+ mr13val = (fsop << 7) | (fswr << 6) | (1 << 4);
+ if (mnh_ddr_write_mode_reg(13, mr13val)) {
+ pr_err("%s %d error writing MR13\n",
+ __func__, __LINE__);
+ ret = -EIO;
+ goto sw_switch_error_exit;
+ }
+
+ /* step 2 */
+ for (i = 0; i < MR_TABLE_LEN; i++) {
+ if (mnh_ddr_write_mode_reg(mrw_fsps[index][i][0],
+ mrw_fsps[index][i][1])) {
+ pr_err("%s %d error (%d %d) writing mr: 0x%02x\n",
+ __func__, __LINE__, index, i,
+ mrw_fsps[index][i][0]);
+ ret = -EIO;
+ goto sw_switch_error_exit;
+ }
+ }
+
+ /* step 3 */
+ fsop = (fsop == 1) ? 0 : 1;
+ mr13val = (fsop << 7) | (fswr << 6) | (1 << 4) | (1 << 3);
+ if (mnh_ddr_write_mode_reg(13, mr13val)) {
+ pr_err("%s %d error writing MR13\n",
+ __func__, __LINE__);
+ ret = -EIO;
+ goto sw_switch_error_exit;
+ }
+ fswr = (fswr == 1) ? 0 : 1;
+
+ /* step 4 */
+ mnh_ddr_send_lp_cmd(LP_CMD_SRPD);
+ /* step 5 */
+ /* removed using iso for switch */
+ /* step 6 moved to step 0 */
+ /* step 7 */
+ MNH_DDR_PHY_OUTf(1099, PHY_DLL_RST_EN, 1);
+
+ /* step 8 */
+ /* Prepare memory controller for switch */
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG, LPC_FREQ_CHG_COPY_NUM, index);
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG, LPC_EXT_CMD, LP_CMD_FREQ_SWITCH);
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG, LPC_EXT_CMD_REQ, 1);
+
+ timeout = 1000;
+ while (!MNH_SCU_INf(SCU_IRQ_STATUS, LP4_FREQ_CHG_REQ) &&
+ (timeout-- > 0))
+ udelay(1);
+
+ if (!MNH_SCU_INf(SCU_IRQ_STATUS, LP4_FREQ_CHG_REQ)) {
+ pr_err("%s: Missed SCU_IRQ_STATUS.LP4_FREQ_CHG_REQ!\n",
+ __func__);
+ ret = -ETIME;
+ goto sw_switch_error_exit;
+ }
+
+ /* clear it */
+ MNH_SCU_OUTf(SCU_IRQ_STATUS, LP4_FREQ_CHG_REQ, 1);
+ /* load clock settings from the fsp of interest */
+ WRITE_CLK_FROM_FSP(index);
+ /* effect the clock change */
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG, LP4_FSP_SW_OVERRIDE, 1);
+ udelay(100);
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG, LP4_FSP_SW_OVERRIDE, 0);
+
+ /* step 9 */
+ MNH_DDR_PHY_OUTf(1099, PHY_DLL_RST_EN, 2);
+ /* step 10 */
+ /* inform memory controller freq change is done */
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG, LP4_FREQ_CHG_ACK, 1);
+ timeout = 1000;
+ while (!MNH_SCU_INf(LPDDR4_LOW_POWER_STS, LPC_CMD_DONE) &&
+ (timeout-- > 0))
+ udelay(1);
+
+ if (!MNH_SCU_INf(LPDDR4_LOW_POWER_STS, LPC_CMD_DONE)) {
+ pr_err("%s Missed: LPDDR4_LOW_POWER_STS.LPC_CMD_DONE\n",
+ __func__);
+ ret = -ETIME;
+ goto sw_switch_error_exit;
+ }
+
+ /* steps 11 - 13 removed because we're not using iso */
+
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG, LP4_FSP_SW_OVERRIDE, 0);
+ /* clear done */
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_STS, LPC_CMD_DONE, 1);
+ /* step 14 */
+ /* undo previous changes. */
+ MNH_DDR_CTL_OUTf(223, CTRLUPD_REQ_PER_AREF_EN, 1);
+ MNH_DDR_CTL_OUTf(525, CTRLUPD_AREF_HP_ENABLE, 1);
+ /* CDNS added this line */
+ MNH_DDR_PHY_OUTf(1098, PHY_INIT_UPDATE_CONFIG, 7);
+ MNH_DDR_PHY_OUTf(1100, PHY_UPDATE_MASK, 0);
+ MNH_DDR_CTL_OUTf(221, INHIBIT_DRAM_CMD, 0);
+ MNH_DDR_CTL_OUTf(88, UPD_CTRLUPD_HIGH_THRESHOLD_F0, upd_high[0]);
+ MNH_DDR_CTL_OUTf(88, UPD_CTRLUPD_NORM_THRESHOLD_F0, upd_norm[0]);
+ MNH_DDR_CTL_OUTf(91, UPD_CTRLUPD_HIGH_THRESHOLD_F1, upd_high[1]);
+ MNH_DDR_CTL_OUTf(90, UPD_CTRLUPD_NORM_THRESHOLD_F1, upd_norm[1]);
+ MNH_DDR_CTL_OUTf(93, UPD_CTRLUPD_HIGH_THRESHOLD_F2, upd_high[2]);
+ MNH_DDR_CTL_OUTf(93, UPD_CTRLUPD_NORM_THRESHOLD_F2, upd_norm[2]);
+ MNH_DDR_CTL_OUTf(96, UPD_CTRLUPD_HIGH_THRESHOLD_F3, upd_high[3]);
+ MNH_DDR_CTL_OUTf(95, UPD_CTRLUPD_NORM_THRESHOLD_F3, upd_norm[3]);
+
+ MNH_DDR_CTL_OUTf(120, LPI_WAKEUP_EN, old_lpi_wakeup_en);
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x4CD9);
+ MNH_SCU_OUTxf(LPDDR4_FSP_SETTING, index, FSP_SW_CTRL, 0);
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0);
+
+ mnh_ddr_clr_int_status_bit(DFI_UPDATE_ERROR_SBIT);
+ mnh_ddr_clr_int_status_bit(DFS_COMPLETE_SBIT);
+ mnh_ddr_clr_int_status_bit(DFI_STATE_CHANGE_SBIT);
+ ret = 0;
+
+ if (MNH_SCU_INxf(LPDDR4_FSP_SETTING, index, FSP_SYS200_MODE))
+ mnh_lpddr_sys200_mode(true);
+
+sw_switch_error_exit:
+ if (mnh_ddr_print_phy_status())
+ ret = -EIO;
+
+ return ret;
+}
+
+static void mnh_ddr_pull_config(void)
+{
+ int index, fsp;
+ for (index = 0; index < MNH_DDR_NUM_CTL_REG; index++)
+ SAVE_DDR_REG_CONFIG(ctl, index);
+ CLR_START(ctl);
+
+ for (index = 0; index < MNH_DDR_NUM_PI_REG; index++)
+ SAVE_DDR_REG_CONFIG(pi, index);
+ CLR_START(pi);
+
+ for (fsp = 0; fsp < MNH_DDR_NUM_BANKED_FSPS; fsp++) {
+ MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, fsp);
+ for (index = 0; index < MNH_DDR_NUM_PHY_REG; index++)
+ SAVE_DDR_PHY_REG_CONFIG(fsp, index);
+ }
+}
+
+int mnh_ddr_suspend(struct device *dev)
+{
+ if (WARN_ON(!_state))
+ return -ENOMEM;
+
+ mnh_ddr_disable_lp();
dev_dbg(dev, "%s: tref 0x%04x 0x%04x 0x%04x 0x%04x\n",
__func__, MNH_DDR_CTL_INf(56, TREF_F0),
@@ -368,12 +809,18 @@
MNH_DDR_CTL_OUTf(58, TREF_F2, _state->tref[2]);
MNH_DDR_CTL_OUTf(59, TREF_F3, _state->tref[3]);
- /* resume to fsp3 */
- mnh_lpddr_freq_change(LPDDR_FREQ_FSP3);
- SAVE_CURRENT_FSP(dev, _state);
- mnh_ddr_pull_config(data);
+ if (MNH_DDR_CTL_INf(133, CURRENT_REG_COPY) !=
+ LPDDR_FREQ_FSP3) {
+ /* resume to fsp3 */
+ if (mnh_lpddr_freq_change(LPDDR_FREQ_FSP3)) {
+ dev_err(dev, "%s ERROR suspend clock switch failed.",
+ __func__);
+ return -EIO;
+ }
+ }
+ mnh_ddr_pull_config();
- mnh_ddr_send_lp_cmd(dev, LP_CMD_DSRPD);
+ mnh_ddr_send_lp_cmd(LP_CMD_DSRPD);
dev_dbg(dev, "%s LP_STATE is 0x%x", __func__,
MNH_DDR_CTL_INf(121, LP_STATE));
@@ -384,44 +831,40 @@
MNH_SCU_OUTf(CCU_CLK_CTL, LP4_REFCLKEN, 0);
udelay(1);
- gpiod_set_value_cansleep(iso_n, 0);
- udelay(1);
-
- dev_dbg(dev, "%s done.", __func__);
+ MNH_DDR_ASSERT_ISO_N();
+ dev_dbg(dev, "%s iso is asserted", __func__);
return 0;
}
EXPORT_SYMBOL(mnh_ddr_suspend);
-int mnh_ddr_resume(struct mnh_ddr_data *data, struct gpio_desc *iso_n)
+int mnh_ddr_resume(struct device *dev)
{
- struct device *dev = &data->pdev->dev;
- struct mnh_ddr_internal_state *_state = &data->_state;
-
int index, fsp;
- int timeout = 0;
+ unsigned long timeout = 0;
+ unsigned long start_jiff, end_jiff;
- mnh_ddr_init_clocks(data);
+ if (WARN_ON(!_state))
+ return -ENOMEM;
+
+ mnh_ddr_init_clocks(dev, LPDDR_FREQ_FSP3);
+
+ if (!mnh_ddr_sanity_check())
+ return -EIO;
for (index = 0; index < MNH_DDR_NUM_CTL_REG; index++)
- WRITE_DDR_REG_CONFIG(_state, ctl, index);
-
- MNH_DDR_CTL_OUTf(23, DFIBUS_FREQ_INIT, SAVED_FSP(_state));
- MNH_DDR_CTL_OUTf(23, DFIBUS_BOOT_FREQ, 0);
-
- MNH_DDR_CTL_OUTf(23, PHY_INDEP_TRAIN_MODE, 0);
- MNH_DDR_CTL_OUTf(23, CDNS_INTRL0, 1);
+ WRITE_DDR_REG_CONFIG(ctl, index);
for (index = 0; index < MNH_DDR_NUM_PI_REG; index++)
- WRITE_DDR_REG_CONFIG(_state, pi, index);
+ WRITE_DDR_REG_CONFIG(pi, index);
- for (fsp = 0; fsp < MNH_DDR_NUM_FSPS; fsp++) {
+ for (fsp = 0; fsp < MNH_DDR_NUM_BANKED_FSPS; fsp++) {
MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_MULTICAST_EN, 0);
MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, fsp);
for (index = 0; index < MNH_DDR_NUM_PHY_REG; index++) {
if (index != 1025)
- WRITE_DDR_PHY_CONFIG(_state, fsp, index);
+ WRITE_DDR_PHY_CONFIG(fsp, index);
}
MNH_DDR_PHY_OUTf(1084, PHY_CAL_CLK_SELECT_0, 0x4);
}
@@ -441,75 +884,68 @@
udelay(1000);
MNH_DDR_PHY_OUTf(1051, PHY_SET_DFI_INPUT_RST_PAD, 1);
- gpiod_set_value_cansleep(iso_n, 1);
+ MNH_DDR_DEASSERT_ISO_N();
udelay(1000);
-
MNH_DDR_CTL_OUTf(00, START, 1);
+ start_jiff = jiffies;
+ timeout = start_jiff + RESUME_TIMEOUT;
- dev_dbg(dev, "%s waiting for init done.", __func__);
+ dev_dbg(dev, "%s waiting for ctl init done.", __func__);
+ while ((!mnh_ddr_int_status_bit(INIT_DONE_SBIT)) &&
+ time_before(jiffies, timeout))
+ udelay(10);
- timeout = 0;
- while ((timeout < 1000) && (!mnh_ddr_int_status_bit(INIT_DONE_SBIT))) {
- udelay(1);
- timeout++;
- }
+ end_jiff = jiffies;
+ dev_dbg(dev, "%s time elapsed is %u ms",
+ __func__, jiffies_to_msecs(end_jiff - start_jiff));
if (!mnh_ddr_int_status_bit(INIT_DONE_SBIT)) {
dev_err(dev, "%s time out on init done %llx.\n",
- __func__, mnh_ddr_int_status(dev));
+ __func__, mnh_ddr_int_status());
return -ETIMEDOUT;
}
/* need to clear PWRUP_SREFRESH_EXIT to clear interrupt status bit 0 */
MNH_DDR_CTL_OUTf(81, PWRUP_SREFRESH_EXIT, 0);
dev_dbg(dev, "%s got init done %llx.\n", __func__,
- mnh_ddr_int_status(dev));
- mnh_ddr_clr_int_status(dev);
- mnh_lpddr_freq_change(SAVED_FSP(_state));
-
- dev_dbg(dev, "%s: tref 0x%04x 0x%04x 0x%04x 0x%04x\n",
- __func__, MNH_DDR_CTL_INf(56, TREF_F0),
- MNH_DDR_CTL_INf(57, TREF_F1), MNH_DDR_CTL_INf(58, TREF_F2),
- MNH_DDR_CTL_INf(59, TREF_F3));
-
+ mnh_ddr_int_status());
+ mnh_ddr_clr_int_status();
mnh_ddr_enable_lp();
return 0;
}
EXPORT_SYMBOL(mnh_ddr_resume);
-int mnh_ddr_po_init(struct mnh_ddr_data *data, struct gpio_desc *iso_n)
+int mnh_ddr_po_init(struct device *dev, struct gpio_desc *iso_n)
{
- struct device *dev = &data->pdev->dev;
- struct mnh_ddr_internal_state *_state = &data->_state;
-
- int index, setindex;
+ int index, setindex, pi_step;
unsigned long timeout;
const struct mnh_ddr_reg_config *cfg = &mnh_ddr_33_100_400_600;
- mnh_ddr_init_internal_state(_state, cfg);
+ if (WARN_ON(!_state))
+ return -ENOMEM;
+ mnh_ddr_init_internal_state(_state, cfg, iso_n);
dev_dbg(dev, "%s start.", __func__);
/* deassert iso_n */
- gpiod_set_value_cansleep(iso_n, 1);
+ MNH_DDR_DEASSERT_ISO_N();
+ mnh_ddr_init_clocks(dev, LPDDR_FREQ_FSP0);
- mnh_ddr_init_clocks(data);
+ if (!mnh_ddr_sanity_check())
+ return -EIO;
for (index = 0; index < MNH_DDR_NUM_CTL_REG; index++)
- WRITE_DDR_REG_CONFIG(_state, ctl, index);
-
- /* Make sure DRAM will request refresh rate adjustments */
- MNH_DDR_CTL_OUTf(164, MR13_DATA_0, 0xD0);
+ WRITE_DDR_REG_CONFIG(ctl, index);
for (index = 0; index < MNH_DDR_NUM_PI_REG; index++)
- WRITE_DDR_REG_CONFIG(_state, pi, index);
+ WRITE_DDR_REG_CONFIG(pi, index);
MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_MULTICAST_EN, 1);
MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, 0);
for (index = 0; index < MNH_DDR_NUM_PHY_REG; index++)
- WRITE_DDR_PHY_CONFIG(_state, 0, index);
+ WRITE_DDR_PHY_CONFIG(0, index);
MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_MULTICAST_EN, 0);
MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, 1);
@@ -518,9 +954,8 @@
setindex = 0;
while ((setindex < MNH_DDR_PHY_SET_SIZE) &&
(cfg->phy_setA[setindex][0] != 0xFFFFFFFF)) {
- WRITE_SET_ELEMENT(_state,
- cfg->phy_setA[setindex][0],
- cfg->phy_setA[setindex][1]);
+ WRITE_SET_ELEMENT(cfg->phy_setA[setindex][0],
+ cfg->phy_setA[setindex][1]);
setindex++;
}
@@ -530,40 +965,148 @@
setindex = 0;
while ((setindex < MNH_DDR_PHY_SET_SIZE) &&
(cfg->phy_setB[setindex][0] != 0xFFFFFFFF)) {
- WRITE_SET_ELEMENT(_state,
- cfg->phy_setB[setindex][0],
- cfg->phy_setB[setindex][1]);
+ WRITE_SET_ELEMENT(cfg->phy_setB[setindex][0],
+ cfg->phy_setB[setindex][1]);
setindex++;
}
+ /* set the index back to 1 to enable PI WA training */
+ MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, 1);
+ /* Add SCU register change to enable SW switching for all 4 FSPs. */
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x4CD9);
+ MNH_SCU_OUTxf(LPDDR4_FSP_SETTING, 0, FSP_SW_CTRL, 1);
+ MNH_SCU_OUTxf(LPDDR4_FSP_SETTING, 1, FSP_SW_CTRL, 1);
+ MNH_SCU_OUTxf(LPDDR4_FSP_SETTING, 2, FSP_SW_CTRL, 1);
+ MNH_SCU_OUTxf(LPDDR4_FSP_SETTING, 3, FSP_SW_CTRL, 1);
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x0);
+
dev_dbg(dev, "%s begin training,", __func__);
MNH_DDR_PI_OUTf(00, PI_START, 1);
MNH_DDR_CTL_OUTf(00, START, 1);
- timeout = jiffies + TRAINING_TIMEOUT;
- while (time_before(jiffies, timeout) &&
- (!mnh_ddr_int_status_bit(INIT_DONE_SBIT)))
- usleep_range(100, 200);
+ /*
+ * The 11 DFS events during PI training are to be tracked,
+ * and apply WA at correct points.
+ * 1. FSP0 to FSP1
+ * 2. FSP1 to FSP2
+ * 3. FSP2 to FSP1
+ * 4. FSP1 to FSP2
+ * 5. FSP2 to FSP1 - Program POSTDIV of FSP2 to 1 at
+ * pi_freq_change_req event
+ * 6. FSP1 to FSP2 - Program POSTDIV of FSP2 to 0 at
+ * pi_freq_change_req event, provide 400 MHz, set pi_freq_change_ack = 1
+ * 7. FSP2 to FSP3
+ * 8. FSP3 to FSP2
+ * 9. FSP2 to FSP3
+ * 10. FSP3 to FSP2 - Program POSTDIV of FSP2&FSP3 to 1 at
+ * pi_freq_change_req event, Provide 300 MHz clock instead of usual
+ * 400 MHz clock, set pi_freq_change_ack = 1
+ * 11. FSP2 to FSP3 - Program POSTDIV of FSP2&FSP3 to 0 at
+ * pi_freq_change_req event, provide 600 MHz, set pi_freq_change_ack = 1
+ *
+ */
+ dev_info(dev, "%s PI WA training,", __func__);
+ for (pi_step = 1; pi_step <= 11; pi_step++) {
+ timeout = 10000;
+ while (!MNH_SCU_INf(SCU_IRQ_STATUS, LP4_FREQ_CHG_REQ) &&
+ (timeout-- > 0))
+ udelay(1);
+ if (!MNH_SCU_INf(SCU_IRQ_STATUS, LP4_FREQ_CHG_REQ)) {
+ dev_err(dev, "%s: Missed SCU_IRQ_STATUS.LP4_FREQ_CHG_REQ! pi_step=%d, LPDDR4_REQ_FSP=0x%x\n",
+ __func__,
+ pi_step,
+ MNH_SCU_INf(LPDDR4_LOW_POWER_STS, LPDDR4_REQ_FSP));
+ return -ETIME;
+ }
+ dev_dbg(dev, "%s: pi_step=%d, LPDDR4_REQ_FSP=0x%x, INDEX=%d\n",
+ __func__,
+ pi_step,
+ MNH_SCU_INf(LPDDR4_LOW_POWER_STS, LPDDR4_REQ_FSP),
+ MNH_DDR_PHY_INf(1025, PHY_FREQ_SEL_INDEX));
+ /* clear it */
+ MNH_SCU_OUTf(SCU_IRQ_STATUS, LP4_FREQ_CHG_REQ, 1);
- if (!mnh_ddr_int_status_bit(INIT_DONE_SBIT)) {
- dev_err(dev, "%s timed out on init done.\n", __func__);
+ /* Change PHY PLL POSTDIV at Step 5,6,10,11 */
+ switch (pi_step) {
+ case 5:
+ /* change postdiv of CA PLL */
+ MNH_DDR_PHY_OUTf(1046, PHY_PLL_CTRL_CA, 0x322);
+ break;
+ case 6:
+ /* change postdiv of CA PLL for f2 register set */
+ MNH_DDR_PHY_OUTf(1046, PHY_PLL_CTRL_CA, 0x122);
+ break;
+ case 10:
+ /* change postdiv of CA PLL for f2/f3 register set */
+ MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, 1);
+ MNH_DDR_PHY_OUTf(1046, PHY_PLL_CTRL_CA, 0x322);
+ MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, 2);
+ MNH_DDR_PHY_OUTf(1046, PHY_PLL_CTRL_CA, 0x322);
+ break;
+ case 11:
+ /* change postdiv of CA PLL for f2 register set */
+ MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, 1);
+ MNH_DDR_PHY_OUTf(1046, PHY_PLL_CTRL_CA, 0x122);
+ MNH_DDR_PHY_OUTf(1025, PHY_FREQ_SEL_INDEX, 2);
+ MNH_DDR_PHY_OUTf(1046, PHY_PLL_CTRL_CA, 0x122);
+ break;
+ }
+
+ /* Freeze the divider settings till all registers are updated */
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x4CD9);
+ MNH_SCU_OUTf(LPDDR4_REFCLK_PLL_CTRL, FRZ_PLL_IN, 1);
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x0);
+ /* load clock settings from the fsp of interest based on PI's
+ * fsp request
+ */
+ WRITE_CLK_FROM_FSP_NO_LOCK((MNH_SCU_INf(LPDDR4_LOW_POWER_STS,
+ LPDDR4_REQ_FSP)));
+ /* Provide 300 MHz clock */
+ if (pi_step == 10)
+ /* 1200 MHz div by 4 */
+ MNH_SCU_OUTf(CCU_CLK_DIV, LPDDR4_REFCLK_DIV, 3);
+ /* UnFreeze the divider settings till all regs are updated */
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x4CD9);
+ MNH_SCU_OUTf(LPDDR4_REFCLK_PLL_CTRL, FRZ_PLL_IN, 0);
+ MNH_SCU_OUTf(PLL_PASSCODE, PASSCODE, 0x0);
+ /* effect the clock change */
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG,
+ LP4_FSP_SW_OVERRIDE, 1);
+ /* inform memory controller freq change is done */
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG,
+ LP4_FREQ_CHG_ACK, 1);
+ MNH_SCU_OUTf(LPDDR4_LOW_POWER_CFG,
+ LP4_FSP_SW_OVERRIDE, 0);
+ }
+
+ timeout = jiffies + msecs_to_jiffies(50);
+ while (!(mnh_ddr_int_status_bit(INIT_DONE_SBIT) &&
+ mnh_ddr_pi_int_status_bit(PI_INIT_DONE_BIT)) &&
+ time_before(jiffies, timeout))
+ udelay(100);
+
+ if (!mnh_ddr_int_status_bit(INIT_DONE_SBIT) ||
+ !mnh_ddr_pi_int_status_bit(PI_INIT_DONE_BIT)) {
+ dev_err(dev, "%s timed out on init done. 0x%llx 0x%08x\n",
+ __func__,
+ mnh_ddr_int_status(),
+ MNH_DDR_PI_INf(172, PI_INT_STATUS));
return -ETIMEDOUT;
}
dev_dbg(dev, "%s got init done %llx.\n", __func__,
- mnh_ddr_int_status(dev));
+ mnh_ddr_int_status());
- mnh_ddr_clr_int_status(dev);
+ mnh_ddr_clr_int_status();
MNH_DDR_CTL_OUTf(165, MR_FSP_DATA_VALID_F0_0, 1);
MNH_DDR_CTL_OUTf(165, MR_FSP_DATA_VALID_F1_0, 1);
MNH_DDR_CTL_OUTf(165, MR_FSP_DATA_VALID_F2_0, 1);
MNH_DDR_CTL_OUTf(166, MR_FSP_DATA_VALID_F3_0, 1);
- dev_dbg(dev, "%s: tref 0x%04x 0x%04x 0x%04x 0x%04x\n",
- __func__, MNH_DDR_CTL_INf(56, TREF_F0),
- MNH_DDR_CTL_INf(57, TREF_F1), MNH_DDR_CTL_INf(58, TREF_F2),
- MNH_DDR_CTL_INf(59, TREF_F3));
-
+ dev_dbg(dev, "%s done\n", __func__);
+ /* settings to take effect on resume */
+ MNH_DDR_CTL_OUTf(23, PHY_INDEP_TRAIN_MODE, 0);
+ MNH_DDR_CTL_OUTf(23, CDNS_INTRL0, 1);
mnh_ddr_enable_lp();
/* Enable FSP3 => 2400 */
@@ -573,10 +1116,8 @@
}
EXPORT_SYMBOL(mnh_ddr_po_init);
-u32 mnh_ddr_mbist(struct mnh_ddr_data *data, enum mnh_ddr_bist_type bist_type)
+u32 mnh_ddr_mbist(struct device *dev, enum mnh_ddr_bist_type bist_type)
{
- struct device *dev = &data->pdev->dev;
-
u32 result = 0;
u32 timeout = 1000000;
const u32 pattern[] = {
@@ -595,7 +1136,7 @@
return 0;
}
- mnh_ddr_disable_lp(dev);
+ mnh_ddr_disable_lp();
old_in_order_accept = MNH_DDR_CTL_INf(223, IN_ORDER_ACCEPT);
MNH_DDR_CTL_OUTf(223, IN_ORDER_ACCEPT, 1);
@@ -625,14 +1166,14 @@
if (!mnh_ddr_int_status_bit(BIST_SBIT)) {
dev_err(dev, "%s: BIST timedout: %llx\n",
- __func__, mnh_ddr_int_status(dev));
+ __func__, mnh_ddr_int_status());
} else {
result = MNH_DDR_CTL_INf(171, BIST_RESULT);
dev_info(dev, "%s: result 0x%02x\n", __func__, result);
}
MNH_DDR_CTL_OUTf(171, BIST_GO, 0);
- mnh_ddr_clr_int_status(dev);
+ mnh_ddr_clr_int_status();
MNH_DDR_CTL_OUTf(223, IN_ORDER_ACCEPT,
old_in_order_accept);
@@ -642,10 +1183,15 @@
}
EXPORT_SYMBOL(mnh_ddr_mbist);
-int mnh_ddr_platform_init(struct platform_device *pdev,
- struct mnh_ddr_data *data)
+int mnh_ddr_platform_init(struct device *dev)
{
- data->pdev = pdev;
+ dev_dbg(dev, "%s\n", __func__);
+
+ _state = devm_kzalloc(dev, sizeof(struct mnh_ddr_internal_state),
+ GFP_KERNEL);
+ if (!_state)
+ return -ENOMEM;
+
return 0;
}
EXPORT_SYMBOL_GPL(mnh_ddr_platform_init);
diff --git a/drivers/misc/mnh/mnh-ddr.h b/drivers/misc/mnh/mnh-ddr.h
index 372ca55..c609cc4 100644
--- a/drivers/misc/mnh/mnh-ddr.h
+++ b/drivers/misc/mnh/mnh-ddr.h
@@ -20,13 +20,13 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio/consumer.h>
-#include <linux/platform_device.h>
#define MNH_DDR_NUM_CTL_REG (558 + 1)
#define MNH_DDR_NUM_PHY_REG (1100 + 1)
#define MNH_DDR_NUM_PI_REG (191 + 1)
#define MNH_DDR_NUM_FSPS (4)
+#define MNH_DDR_NUM_BANKED_FSPS (3)
#define MNH_DDR_NUM_BASES (3)
/* arbitrary but sufficient size for phy deltas */
@@ -48,10 +48,10 @@
u32 pi_base;
u32 pi[MNH_DDR_NUM_PI_REG];
u32 phy_base;
- u32 phy[MNH_DDR_NUM_FSPS][MNH_DDR_NUM_PHY_REG];
+ u32 phy[MNH_DDR_NUM_BANKED_FSPS][MNH_DDR_NUM_PHY_REG];
u32 fsps[MNH_DDR_NUM_FSPS];
- u32 suspend_fsp;
u32 tref[MNH_DDR_NUM_FSPS];
+ struct gpio_desc *iso_n;
};
enum mnh_ddr_bist_type {
@@ -59,18 +59,15 @@
LIMITED_MOVI1_3N,
};
-struct mnh_ddr_data {
- struct platform_device *pdev;
- struct mnh_ddr_internal_state _state;
-};
+/* mnh-ddr driver init called during mnh-sm probe */
+int mnh_ddr_platform_init(struct device *dev);
-int mnh_ddr_platform_init(struct platform_device *pdev,
- struct mnh_ddr_data *data);
-int mnh_ddr_po_init(struct mnh_ddr_data *data, struct gpio_desc *iso_n);
-int mnh_ddr_resume(struct mnh_ddr_data *data, struct gpio_desc *iso_n);
-int mnh_ddr_suspend(struct mnh_ddr_data *data, struct gpio_desc *iso_n);
-int mnh_ddr_clr_int_status(struct device *dev);
-u64 mnh_ddr_int_status(struct device *dev);
-u32 mnh_ddr_mbist(struct mnh_ddr_data *data, enum mnh_ddr_bist_type bist_type);
+int mnh_ddr_po_init(struct device *dev, struct gpio_desc *iso_n);
+int mnh_ddr_resume(struct device *dev);
+int mnh_ddr_suspend(struct device *dev);
+int mnh_ddr_clr_int_status(void);
+u64 mnh_ddr_int_status(void);
+u32 mnh_ddr_mbist(struct device *dev, enum mnh_ddr_bist_type bist_type);
+int mnh_ddr_sw_switch(int index);
#endif /* __MNH_DDR_H__ */
diff --git a/drivers/misc/mnh/mnh-hwio-cpu.h b/drivers/misc/mnh/mnh-hwio-cpu.h
new file mode 100644
index 0000000..3644dea
--- /dev/null
+++ b/drivers/misc/mnh/mnh-hwio-cpu.h
@@ -0,0 +1,136 @@
+/* auto generated: Monday, August 15th, 2016 12:26:47pm */
+/* gucheng: edit 11/07/2018 for checkpatch */
+/*
+ * Copyright (c) 2016, Intel Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of Intel nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef __MNH_HWIO_CPU_
+#define __MNH_HWIO_CPU_
+
+#define HWIO_CPU_CFG_REGOFF 0x0
+#define HWIO_CPU_CFG_ADDR(bAddr, regX) (bAddr + HWIO_CPU_CFG_REGOFF)
+#define HWIO_CPU_CFG_CLUSTERIDAFF2_FLDMASK (0xff000000)
+#define HWIO_CPU_CFG_CLUSTERIDAFF2_FLDSHFT (24)
+#define HWIO_CPU_CFG_CLUSTERIDAFF1_FLDMASK (0xff0000)
+#define HWIO_CPU_CFG_CLUSTERIDAFF1_FLDSHFT (16)
+#define HWIO_CPU_CFG_RSVD0_FLDMASK (0xfff0)
+#define HWIO_CPU_CFG_RSVD0_FLDSHFT (4)
+#define HWIO_CPU_CFG_VINITHI_FLDMASK (0x8)
+#define HWIO_CPU_CFG_VINITHI_FLDSHFT (3)
+#define HWIO_CPU_CFG_CFGTE_FLDMASK (0x4)
+#define HWIO_CPU_CFG_CFGTE_FLDSHFT (2)
+#define HWIO_CPU_CFG_CFGEND_FLDMASK (0x2)
+#define HWIO_CPU_CFG_CFGEND_FLDSHFT (1)
+#define HWIO_CPU_CFG_AA64nAA32_FLDMASK (0x1)
+#define HWIO_CPU_CFG_AA64nAA32_FLDSHFT (0)
+
+#define HWIO_CPU_RST_CFG_REGOFF 0x4
+#define HWIO_CPU_RST_CFG_ADDR(bAddr, regX) (bAddr + HWIO_CPU_RST_CFG_REGOFF)
+#define HWIO_CPU_RST_CFG_RSVD0_FLDMASK (0xfffffffc)
+#define HWIO_CPU_RST_CFG_RSVD0_FLDSHFT (2)
+#define HWIO_CPU_RST_CFG_DBGL1RSTDISABLE_FLDMASK (0x2)
+#define HWIO_CPU_RST_CFG_DBGL1RSTDISABLE_FLDSHFT (1)
+#define HWIO_CPU_RST_CFG_L2RSTDISABLE_FLDMASK (0x1)
+#define HWIO_CPU_RST_CFG_L2RSTDISABLE_FLDSHFT (0)
+
+#define HWIO_CPU_RST_STS_REGOFF 0x8
+#define HWIO_CPU_RST_STS_ADDR(bAddr, regX) (bAddr + HWIO_CPU_RST_STS_REGOFF)
+#define HWIO_CPU_RST_STS_RSVD0_FLDMASK (0xfffffffc)
+#define HWIO_CPU_RST_STS_RSVD0_FLDSHFT (2)
+#define HWIO_CPU_RST_STS_DBGRSTREQ_FLDMASK (0x2)
+#define HWIO_CPU_RST_STS_DBGRSTREQ_FLDSHFT (1)
+#define HWIO_CPU_RST_STS_WARMRSTREQ_FLDMASK (0x1)
+#define HWIO_CPU_RST_STS_WARMRSTREQ_FLDSHFT (0)
+
+#define HWIO_CPU_PWR_MGMT_CFG_REGOFF 0x0C
+#define HWIO_CPU_PWR_MGMT_CFG_ADDR(bAddr, regX) \
+ (bAddr + HWIO_CPU_PWR_MGMT_CFG_REGOFF)
+#define HWIO_CPU_PWR_MGMT_CFG_RSVD0_FLDMASK (0xfffffffc)
+#define HWIO_CPU_PWR_MGMT_CFG_RSVD0_FLDSHFT (2)
+#define HWIO_CPU_PWR_MGMT_CFG_L2FLUSHREQ_FLDMASK (0x2)
+#define HWIO_CPU_PWR_MGMT_CFG_L2FLUSHREQ_FLDSHFT (1)
+#define HWIO_CPU_PWR_MGMT_CFG_EVENTI_FLDMASK (0x1)
+#define HWIO_CPU_PWR_MGMT_CFG_EVENTI_FLDSHFT (0)
+
+#define HWIO_CPU_PWR_MGMT_STS_REGOFF 0x10
+#define HWIO_CPU_PWR_MGMT_STS_ADDR(bAddr, regX) \
+ (bAddr + HWIO_CPU_PWR_MGMT_STS_REGOFF)
+#define HWIO_CPU_PWR_MGMT_STS_RSVD0_FLDMASK (0xffffff00)
+#define HWIO_CPU_PWR_MGMT_STS_RSVD0_FLDSHFT (8)
+#define HWIO_CPU_PWR_MGMT_STS_CPUQACTIVE_FLDMASK (0x80)
+#define HWIO_CPU_PWR_MGMT_STS_CPUQACTIVE_FLDSHFT (7)
+#define HWIO_CPU_PWR_MGMT_STS_DBGPWRUPREQ_FLDMASK (0x40)
+#define HWIO_CPU_PWR_MGMT_STS_DBGPWRUPREQ_FLDSHFT (6)
+#define HWIO_CPU_PWR_MGMT_STS_DBGNOPWRDWN_FLDMASK (0x20)
+#define HWIO_CPU_PWR_MGMT_STS_DBGNOPWRDWN_FLDSHFT (5)
+#define HWIO_CPU_PWR_MGMT_STS_SMPEN_FLDMASK (0x10)
+#define HWIO_CPU_PWR_MGMT_STS_SMPEN_FLDSHFT (4)
+#define HWIO_CPU_PWR_MGMT_STS_L2FLUSHDONE_FLDMASK (0x8)
+#define HWIO_CPU_PWR_MGMT_STS_L2FLUSHDONE_FLDSHFT (3)
+#define HWIO_CPU_PWR_MGMT_STS_STANDBYWFE_FLDMASK (0x4)
+#define HWIO_CPU_PWR_MGMT_STS_STANDBYWFE_FLDSHFT (2)
+#define HWIO_CPU_PWR_MGMT_STS_STANDBYWFI_FLDMASK (0x2)
+#define HWIO_CPU_PWR_MGMT_STS_STANDBYWFI_FLDSHFT (1)
+#define HWIO_CPU_PWR_MGMT_STS_EVENTO_FLDMASK (0x1)
+#define HWIO_CPU_PWR_MGMT_STS_EVENTO_FLDSHFT (0)
+
+#define HWIO_CPU_DBG_CFG_REGOFF 0x14
+#define HWIO_CPU_DBG_CFG_ADDR(bAddr, regX) (bAddr + HWIO_CPU_DBG_CFG_REGOFF)
+#define HWIO_CPU_DBG_CFG_RSVD0_FLDMASK (0xfffffffc)
+#define HWIO_CPU_DBG_CFG_RSVD0_FLDSHFT (2)
+#define HWIO_CPU_DBG_CFG_NIDEN_FLDMASK (0x2)
+#define HWIO_CPU_DBG_CFG_NIDEN_FLDSHFT (1)
+#define HWIO_CPU_DBG_CFG_DBGEN_FLDMASK (0x1)
+#define HWIO_CPU_DBG_CFG_DBGEN_FLDSHFT (0)
+
+#define HWIO_CPU_STS_REGOFF 0x18
+#define HWIO_CPU_STS_ADDR(bAddr, regX) (bAddr + HWIO_CPU_STS_REGOFF)
+#define HWIO_CPU_STS_STATUS_FLDMASK (0xffffffff)
+#define HWIO_CPU_STS_STATUS_FLDSHFT (0)
+
+#define HWIO_CPU_SECURE_REGOFF 0x1C
+#define HWIO_CPU_SECURE_ADDR(bAddr, regX) (bAddr + HWIO_CPU_SECURE_REGOFF)
+#define HWIO_CPU_SECURE_SECURE_LOCK_FLDMASK (0x80000000)
+#define HWIO_CPU_SECURE_SECURE_LOCK_FLDSHFT (31)
+#define HWIO_CPU_SECURE_RSVD0_FLDMASK (0x7ffffff8)
+#define HWIO_CPU_SECURE_RSVD0_FLDSHFT (3)
+#define HWIO_CPU_SECURE_CP15SDISABLE_FLDMASK (0x4)
+#define HWIO_CPU_SECURE_CP15SDISABLE_FLDSHFT (2)
+#define HWIO_CPU_SECURE_SPNIDEN_FLDMASK (0x2)
+#define HWIO_CPU_SECURE_SPNIDEN_FLDSHFT (1)
+#define HWIO_CPU_SECURE_SPIDEN_FLDMASK (0x1)
+#define HWIO_CPU_SECURE_SPIDEN_FLDSHFT (0)
+
+#define HWIO_CPU_DBG_BUS_REGOFF 0x20
+#define HWIO_CPU_DBG_BUS_ADDR(bAddr, regX) (bAddr + HWIO_CPU_DBG_BUS_REGOFF)
+#define HWIO_CPU_DBG_BUS_RSVD0_FLDMASK (0xfffffffc)
+#define HWIO_CPU_DBG_BUS_RSVD0_FLDSHFT (2)
+#define HWIO_CPU_DBG_BUS_DBG_MUX_SEL_FLDMASK (0x3)
+#define HWIO_CPU_DBG_BUS_DBG_MUX_SEL_FLDSHFT (0)
+
+#endif /* __MNH_HWIO_CPU_ */
diff --git a/drivers/misc/mnh/mnh-hwio-scu.h b/drivers/misc/mnh/mnh-hwio-scu.h
index 965c450..38dff31 100644
--- a/drivers/misc/mnh/mnh-hwio-scu.h
+++ b/drivers/misc/mnh/mnh-hwio-scu.h
@@ -91,6 +91,8 @@
#define HWIO_SCU_GPS_GPS_FLDMASK (0xffffffff)
#define HWIO_SCU_GPS_GPS_FLDSHFT (0)
+#define MNH_BOOT_STAT (HWIO_SCU_GPS_ADDR(HWIO_SCU_BASE_ADDR, 0))
+
/* General Purpose Scratchpad */
/*
* Allocation:
diff --git a/drivers/misc/mnh/mnh-pcie.c b/drivers/misc/mnh/mnh-pcie.c
index d213336..8dc1b31 100644
--- a/drivers/misc/mnh/mnh-pcie.c
+++ b/drivers/misc/mnh/mnh-pcie.c
@@ -2013,10 +2013,14 @@
dev_dbg(&pdev->dev, "MNH PCIe driver is removed\n");
}
-int mnh_pci_suspend(void)
+int mnh_pci_suspend(struct pci_dev *pdev)
{
- struct pci_dev *pdev = mnh_dev->pdev;
- struct device *dev = &mnh_dev->pdev->dev;
+ struct device *dev;
+
+ if (!pdev || !pci_get_drvdata(pdev))
+ return 0;
+
+ dev = &pdev->dev;
dev_dbg(dev, "%s: enter\n", __func__);
@@ -2042,12 +2046,16 @@
}
EXPORT_SYMBOL_GPL(mnh_pci_suspend);
-int mnh_pci_resume(void)
+int mnh_pci_resume(struct pci_dev *pdev)
{
- struct pci_dev *pdev = mnh_dev->pdev;
- struct device *dev = &mnh_dev->pdev->dev;
+ struct device *dev;
int ret = 0;
+ if (!pdev || !pci_get_drvdata(pdev))
+ return -ENODEV;
+
+ dev = &pdev->dev;
+
dev_dbg(dev, "%s: enter\n", __func__);
mnh_dev->powered = true;
diff --git a/drivers/misc/mnh/mnh-pcie.h b/drivers/misc/mnh/mnh-pcie.h
index e361557..c23bbf3 100644
--- a/drivers/misc/mnh/mnh-pcie.h
+++ b/drivers/misc/mnh/mnh-pcie.h
@@ -474,6 +474,6 @@
void mnh_unmap_mem(
dma_addr_t dma_addr, size_t size, enum dma_data_direction direction);
-int mnh_pci_suspend(void);
-int mnh_pci_resume(void);
+int mnh_pci_suspend(struct pci_dev *pdev);
+int mnh_pci_resume(struct pci_dev *pdev);
#endif /* __MNH_PCIE_HOST */
diff --git a/drivers/misc/mnh/mnh-pwr.c b/drivers/misc/mnh/mnh-pwr.c
index cf9b761..4185429 100644
--- a/drivers/misc/mnh/mnh-pwr.c
+++ b/drivers/misc/mnh/mnh-pwr.c
@@ -264,7 +264,7 @@
* Due to pcie failure, suspend the driver state only after
* updating link status.
*/
- ret = mnh_pci_suspend();
+ ret = mnh_pci_suspend(pcidev);
if (ret)
dev_warn(mnh_pwr->dev,
"%s: mnh_pci_suspend failed (%d)\n",
@@ -273,7 +273,7 @@
mnh_pwr->pcie_failure = false;
} else {
/* suspend the driver state */
- ret = mnh_pci_suspend();
+ ret = mnh_pci_suspend(pcidev);
if (ret)
dev_warn(mnh_pwr->dev,
"%s: mnh_pci_suspend failed (%d)\n",
@@ -363,7 +363,7 @@
pci_restore_state(pcidev);
/* resume the driver state */
- ret = mnh_pci_resume();
+ ret = mnh_pci_resume(pcidev);
if (ret) {
dev_err(mnh_pwr->dev, "%s: mnh_pci_resume failed (%d)\n",
__func__, ret);
diff --git a/drivers/misc/mnh/mnh-sm.c b/drivers/misc/mnh/mnh-sm.c
index 962c64f..965d735 100644
--- a/drivers/misc/mnh/mnh-sm.c
+++ b/drivers/misc/mnh/mnh-sm.c
@@ -191,9 +191,6 @@
/* state of the ddr channel */
enum mnh_ddr_status ddr_status;
- /* mnh-ddr data */
- struct mnh_ddr_data mnh_ddr_data;
-
/* pin used for ddr pad isolation */
struct gpio_desc *ddr_pad_iso_n_pin;
@@ -1383,9 +1380,8 @@
return -EINVAL;
mnh_pwr_set_state(MNH_PWR_S0);
- mnh_ddr_po_init(&mnh_sm_dev->mnh_ddr_data,
- mnh_sm_dev->ddr_pad_iso_n_pin);
- mnh_ddr_mbist(&mnh_sm_dev->mnh_ddr_data, val);
+ mnh_ddr_po_init(mnh_sm_dev->dev, mnh_sm_dev->ddr_pad_iso_n_pin);
+ mnh_ddr_mbist(dev, val);
mnh_pwr_set_state(MNH_PWR_S4);
return count;
@@ -1495,8 +1491,7 @@
int ret;
/* Initialize DDR */
- ret = mnh_ddr_po_init(&mnh_sm_dev->mnh_ddr_data,
- mnh_sm_dev->ddr_pad_iso_n_pin);
+ ret = mnh_ddr_po_init(mnh_sm_dev->dev, mnh_sm_dev->ddr_pad_iso_n_pin);
if (ret) {
dev_err(mnh_sm_dev->dev, "%s: ddr training failed (%d)\n",
__func__, ret);
@@ -1509,9 +1504,16 @@
static int mnh_sm_resume_ddr(void)
{
+ int ret;
+
/* deassert pad isolation, take ddr out of self-refresh mode */
- mnh_ddr_resume(&mnh_sm_dev->mnh_ddr_data,
- mnh_sm_dev->ddr_pad_iso_n_pin);
+ ret = mnh_ddr_resume(mnh_sm_dev->dev);
+ if (ret) {
+ dev_err(mnh_sm_dev->dev, "%s: error resuming dram (%d)\n",
+ __func__, ret);
+ return ret;
+ }
+
mnh_sm_dev->ddr_status = MNH_DDR_ACTIVE;
return 0;
}
@@ -1519,8 +1521,7 @@
static int mnh_sm_suspend_ddr(void)
{
/* put ddr into self-refresh mode, assert pad isolation */
- mnh_ddr_suspend(&mnh_sm_dev->mnh_ddr_data,
- mnh_sm_dev->ddr_pad_iso_n_pin);
+ mnh_ddr_suspend(mnh_sm_dev->dev);
mnh_sm_dev->ddr_status = MNH_DDR_SELF_REFRESH;
return 0;
}
@@ -1663,16 +1664,23 @@
int err;
uint32_t val;
- err = mnh_config_read(MNH_BOOT_TRACE, sizeof(val), &val);
+ err = mnh_config_read(MNH_BOOT_STAT, sizeof(val), &val);
+ if (err) {
+ dev_err(dev,
+ "%s: failed reading MNH_BOOT_STAT (%d)\n",
+ __func__, err);
+ } else {
+ dev_info(dev, "MNH_BOOT_STAT = 0x%x\n", val);
+ }
+ err = mnh_config_read(MNH_BOOT_TRACE, sizeof(val), &val);
if (err) {
dev_err(dev,
"%s: failed reading MNH_BOOT_TRACE (%d)\n",
__func__, err);
- return;
+ } else {
+ dev_info(dev, "MNH_BOOT_TRACE = 0x%x\n", val);
}
-
- dev_info(dev, "%s: MNH_BOOT_TRACE = 0x%x\n", __func__, val);
}
static void mnh_sm_enable_ready_irq(bool enable)
@@ -2435,7 +2443,7 @@
}
/* initialize mnh-ddr driver */
- error = mnh_ddr_platform_init(pdev, &mnh_sm_dev->mnh_ddr_data);
+ error = mnh_ddr_platform_init(dev);
if (error) {
dev_err(dev, "failed to initialize mnh-ddr (%d)\n", error);
goto fail_probe_2;
diff --git a/drivers/phy/phy-qcom-ufs.c b/drivers/phy/phy-qcom-ufs.c
index 1e3e175..125be43 100644
--- a/drivers/phy/phy-qcom-ufs.c
+++ b/drivers/phy/phy-qcom-ufs.c
@@ -802,6 +802,25 @@
}
EXPORT_SYMBOL(ufs_qcom_phy_dump_regs);
+void ufs_qcom_phy_print_phy_state(struct phy *generic_phy)
+{
+ struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
+
+ dev_err(ufs_qcom_phy->dev, "phy->is_iface_clk_enabled = %x\n",
+ ufs_qcom_phy->is_iface_clk_enabled);
+ dev_err(ufs_qcom_phy->dev, "phy->is_ref_clk_enabled = %x\n",
+ ufs_qcom_phy->is_ref_clk_enabled);
+ dev_err(ufs_qcom_phy->dev, "phy->is_dev_ref_clk_enabled = %x\n",
+ ufs_qcom_phy->is_dev_ref_clk_enabled);
+ dev_err(ufs_qcom_phy->dev, "phy->is_powered_on = %x\n",
+ ufs_qcom_phy->is_powered_on);
+ dev_err(ufs_qcom_phy->dev, "phy->vdda_pll.enabled = %x\n",
+ ufs_qcom_phy->vdda_pll.enabled);
+ dev_err(ufs_qcom_phy->dev, "phy->vdda_phy.enabled = %x\n",
+ ufs_qcom_phy->vdda_phy.enabled);
+}
+EXPORT_SYMBOL(ufs_qcom_phy_print_phy_state);
+
void ufs_qcom_phy_dbg_register_dump(struct phy *generic_phy)
{
struct ufs_qcom_phy *ufs_qcom_phy = get_ufs_qcom_phy(generic_phy);
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa.c b/drivers/platform/msm/ipa/ipa_v3/ipa.c
index 49c04c4..7729025 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2017, 2019, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -330,11 +330,9 @@
static int ipa3_active_clients_panic_notifier(struct notifier_block *this,
unsigned long event, void *ptr)
{
- ipa3_active_clients_lock();
ipa3_active_clients_log_print_table(active_clients_table_buf,
IPA3_ACTIVE_CLIENTS_TABLE_BUF_SIZE);
IPAERR("%s", active_clients_table_buf);
- ipa3_active_clients_unlock();
return NOTIFY_DONE;
}
diff --git a/drivers/power/supply/qcom/qpnp-fg-gen3.c b/drivers/power/supply/qcom/qpnp-fg-gen3.c
index fb56968..3fc0845 100644
--- a/drivers/power/supply/qcom/qpnp-fg-gen3.c
+++ b/drivers/power/supply/qcom/qpnp-fg-gen3.c
@@ -2551,9 +2551,7 @@
chip->cyc_ctr.last_soc[i] = 0;
}
rc = fg_sram_write(chip, CYCLE_COUNT_WORD, CYCLE_COUNT_OFFSET,
- (u8 *)&chip->cyc_ctr.count,
- sizeof(chip->cyc_ctr.count) / sizeof(u8 *),
- FG_IMA_DEFAULT);
+ (u8 *)&chip->cyc_ctr.count, sizeof(chip->cyc_ctr.count), FG_IMA_DEFAULT);
if (rc < 0)
pr_err("failed to clear cycle counter rc=%d\n", rc);
diff --git a/drivers/power/supply/qcom/smb-lib.c b/drivers/power/supply/qcom/smb-lib.c
index eaf5e36..850260e 100644
--- a/drivers/power/supply/qcom/smb-lib.c
+++ b/drivers/power/supply/qcom/smb-lib.c
@@ -4737,6 +4737,7 @@
{
int rc = 0;
u8 stat;
+ bool debounce_done = false;
rc = smblib_set_prop_typec_power_role_locked(
chg, POWER_SUPPLY_TYPEC_PR_SINK);
@@ -4752,9 +4753,16 @@
smblib_err(chg, "Couldn't read Type-C status 4 rc=%d\n", rc);
return rc;
}
+ smblib_err(chg, "Type-C status 4 :%x\n", stat);
+ if ((stat & TYPEC_VBUS_STATUS_BIT) &&
+ !(stat & TYPEC_DEBOUNCE_DONE_STATUS_BIT))
+ goto done;
+
+ debounce_done = true;
*attached = stat & CC_ATTACHED_BIT ? true : false;
+done:
rc = smblib_set_prop_typec_power_role_locked(
chg, POWER_SUPPLY_TYPEC_PR_NONE);
if (rc < 0) {
@@ -4762,6 +4770,9 @@
return rc;
}
+ if (!debounce_done)
+ return -EAGAIN;
+
return 0;
}
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index 7d54725..8eae291 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -2730,6 +2730,14 @@
ufs_qcom_ice_print_regs(host);
}
+void ufs_qcom_print_phy_state(struct ufs_hba *hba)
+{
+ struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+ struct phy *phy = host->generic_phy;
+
+ ufs_qcom_phy_print_phy_state(phy);
+}
+
/**
* struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
*
diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h
index 12154b2..7df08db 100644
--- a/drivers/scsi/ufs/ufs-qcom.h
+++ b/drivers/scsi/ufs/ufs-qcom.h
@@ -412,4 +412,6 @@
return !!(host->caps & UFS_QCOM_CAP_SVS2);
}
+void ufs_qcom_print_phy_state(struct ufs_hba *hba);
+
#endif /* UFS_QCOM_H_ */
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index a92db98..d6d8ab7 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -104,6 +104,10 @@
static void ufshcd_update_error_stats(struct ufs_hba *hba, int type)
{
+ hba->h8_err = false;
+ if (type == UFS_ERR_HIBERN8_EXIT || type == UFS_ERR_HIBERN8_ENTER)
+ hba->h8_err = true;
+
ufsdbg_set_err_state(hba);
if (type < UFS_ERR_MAX)
hba->ufs_stats.err_stats[type]++;
@@ -273,7 +277,7 @@
UTP_TASK_REQ_COMPL |\
UFSHCD_ERROR_MASK)
/* UIC command timeout, unit: ms */
-#define UIC_CMD_TIMEOUT 500
+#define UIC_CMD_TIMEOUT 1500
/* NOP OUT retries waiting for NOP IN response */
#define NOP_OUT_RETRIES 10
@@ -286,7 +290,7 @@
#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
/* Task management command timeout */
-#define TM_CMD_TIMEOUT 100 /* msecs */
+#define TM_CMD_TIMEOUT 1500 /* msecs */
/* maximum number of retries for a general UIC command */
#define UFS_UIC_COMMAND_RETRIES 3
@@ -821,6 +825,14 @@
}
}
+void ufshcd_print_phy_state(struct ufs_hba *hba)
+{
+ if (!(hba->ufshcd_dbg_print & UFSHCD_DBG_PRINT_UIC_ERR_HIST_EN))
+ return;
+
+ ufs_qcom_print_phy_state(hba);
+}
+
static void ufshcd_print_uic_err_hist(struct ufs_hba *hba,
struct ufs_uic_err_reg_hist *err_hist, char *err_name)
{
@@ -5511,10 +5523,10 @@
"Reject UPIU not fully implemented\n");
break;
default:
- result = DID_ERROR << 16;
dev_err(hba->dev,
"Unexpected request response code = %x\n",
result);
+ result = DID_ERROR << 16;
break;
}
break;
@@ -6199,6 +6211,18 @@
hba = container_of(work, struct ufs_hba, eh_work);
+ if (hba->h8_err) {
+ dev_err(hba->dev, "%s: saved_err 0x%x saved_uic_err 0x%x",
+ __func__, hba->saved_err, hba->saved_uic_err);
+ ufshcd_print_host_regs(hba);
+ ufshcd_print_cmd_log(hba);
+ ufshcd_print_host_state(hba);
+ ufshcd_print_pwr_info(hba);
+ ufshcd_print_phy_state(hba);
+ hba->h8_err = false;
+ hba->silence_err_logs = true;
+ }
+
spin_lock_irqsave(hba->host->host_lock, flags);
ufsdbg_set_err_state(hba);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index ed9d6a1e..716293c 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -867,6 +867,7 @@
u32 saved_ce_err;
bool silence_err_logs;
bool force_host_reset;
+ bool h8_err;
/* Device management request data */
struct ufs_dev_cmd dev_cmd;
diff --git a/drivers/soc/qcom/glink_spi_xprt.c b/drivers/soc/qcom/glink_spi_xprt.c
index a2673ef..a691c82 100644
--- a/drivers/soc/qcom/glink_spi_xprt.c
+++ b/drivers/soc/qcom/glink_spi_xprt.c
@@ -492,7 +492,7 @@
- read_id;
if ((offset + size_to_read) > size) {
- pr_err("%s:wrong sz split_sz %u bufsz %u offset %u\n",
+ pr_err("%s:split_size %u buf size %u offset %u\n",
__func__, size_to_read, size, offset);
return -EINVAL;
}
@@ -549,7 +549,7 @@
- write_id;
if ((offset + size_to_write) > size) {
- pr_err("%s:wrong sz split_sz %u bufsz %u offset %u\n",
+ pr_err("%s:split_size %u buf size %u offset %u\n",
__func__, size_to_write, size, offset);
return -EINVAL;
}
diff --git a/drivers/staging/fw-api/fw/a_usb_defs.h b/drivers/staging/fw-api/fw/a_usb_defs.h
index 90a847f..2657d56 100644
--- a/drivers/staging/fw-api/fw/a_usb_defs.h
+++ b/drivers/staging/fw-api/fw/a_usb_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012, 2018 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -25,13 +25,7 @@
* to the Linux Foundation.
*/
-/*
- * Shared USB definitions
- *
- *
- *
- *
- */
+/* USB definitions shared between host and target */
#ifndef __A_USB_DEFS_H__
#define __A_USB_DEFS_H__
@@ -41,19 +35,32 @@
#endif
/* USB endpoint definitions */
+#ifdef PLATFORM_GENOA
+
+#define USB_EP_ADDR_APP_CTRL_IN 0x88
+#define USB_EP_ADDR_APP_DATA_IN 0x89
+#define USB_EP_ADDR_APP_QMI_IN 0x8A
+#define USB_EP_ADDR_APP_DIAG_IN 0x8B
+
+#define USB_EP_ADDR_APP_CTRL_OUT 0x08
+#define USB_EP_ADDR_APP_DATA_OUT 0x09
+#define USB_EP_ADDR_APP_QMI_OUT 0x0A
+#define USB_EP_ADDR_APP_DIAG_OUT 0x0B
+
+#else /* PLATFORM_GENOA */
#define USB_EP_ADDR_APP_CTRL_IN 0x81
#define USB_EP_ADDR_APP_DATA_IN 0x82
#define USB_EP_ADDR_APP_DATA2_IN 0x83
#define USB_EP_ADDR_APP_INT_IN 0x84
-
-
#define USB_EP_ADDR_APP_CTRL_OUT 0x01
#define USB_EP_ADDR_APP_DATA_LP_OUT 0x02
#define USB_EP_ADDR_APP_DATA_MP_OUT 0x03
#define USB_EP_ADDR_APP_DATA_HP_OUT 0x04
+#endif /* PLATFORM_GENOA */
+
#define USB_CONTROL_REQ_SEND_BMI_CMD 1
#define USB_CONTROL_REQ_RECV_BMI_RESP 2
#define USB_CONTROL_REQ_DIAG_CMD 3
diff --git a/drivers/staging/fw-api/fw/dbglog.h b/drivers/staging/fw-api/fw/dbglog.h
index 197866c..aa29c7a 100644
--- a/drivers/staging/fw-api/fw/dbglog.h
+++ b/drivers/staging/fw-api/fw/dbglog.h
@@ -81,6 +81,7 @@
/* Debug Log levels*/
typedef enum {
+ DBGLOG_ML = 0,
DBGLOG_VERBOSE = 0,
DBGLOG_INFO,
DBGLOG_INFO_LVL_1,
diff --git a/drivers/staging/fw-api/fw/dbglog_id.h b/drivers/staging/fw-api/fw/dbglog_id.h
index 18f6d83..50a4437 100644
--- a/drivers/staging/fw-api/fw/dbglog_id.h
+++ b/drivers/staging/fw-api/fw/dbglog_id.h
@@ -50,6 +50,324 @@
*/
#define DBGLOG_DBGID_SM_FRAMEWORK_PROXY_DBGLOG_MSG 1000
+/* RESMGR messageIDs for ML logging */
+typedef enum {
+ RESMGR_MSGID_DEFINITION_START = 0x0000,
+ RESMGR_CHMMGR_CHAINMASK_CHANGE_REQ_MSGID,
+ RESMGR_CHMMGR_PROCESS_CHM_CHANGE_REQ_MSGID,
+ RESMGR_CHMMGR_DB_UPDATE_MSGID,
+ RESMGR_CHMMGR_SEND_HW_MODE_PRE_NOTIF_MSGID,
+ RESMGR_OCM_SUSPEND_MSGID,
+ RESMGR_OCM_MIGRATE_MSGID,
+ RESGMR_OCM_RESUME_MSGID,
+ RESMGR_OCS_CHREQ_GRANT_MSGID,
+ RESMGR_OCS_CURR_CAT_WINDOW_MSGID,
+ RESMGR_OCS_CHREQ_RESTART_MSGID,
+ RESMGR_OCS_CHREQ_COMPLETE_MSGID,
+ RESMGR_OCS_WIN_CAT_DUR_MSGID,
+ RESMGR_OCS_PURGE_CHREQS_MSGID,
+ RESMGR_OCS_INVOKED_MSGID,
+ RESMGR_OCS_CHREQ_CREATE_MSGID,
+ RESMGR_OCS_CHREQ_DELETE_MSGID,
+ RESMGR_OCS_RECAL_QUOTAS_MSGID,
+ RESMGR_OCS_CHREQ_START_MSGID,
+ RESMGR_OCS_CHREQ_STOP_MSGID,
+ RESMGR_OCS_CHREQ_UPDATE_MSGID,
+ RESMGR_DBSMGR_SET_HW_MODE_MSGID,
+ RESMGR_DBSMGR_SET_CONNECTION_IN_PROGRESS_MSGID,
+ RESMGR_VCM_LINK_CREATE_MSGID,
+ RESMGR_VCM_LINK_DELETE_MSGID,
+ RESMGR_VC_INIT_VIR_CHAN_MSGID,
+ RESMGR_VC_ADD_LINK_MSGID,
+ RESMGR_VC_RMV_LINK_MSGID,
+ RESMGR_VC_REGISTER_LINK_MSGID,
+ RESMGR_VC_UNREGISTER_LINK_MSGID,
+ RESMGR_VC_ARBITRATE_ATTRIBUTES_MSGID,
+ RESMGR_DBSMGR_CHANGE_SCAN_STATE_MSGID,
+ RESMGR_DBSMGR_RECOMPUTE_SCAN_POLICY_MSGID,
+ RESMGR_DBSMGR_UPDATE_SCAN_POLICY_MSGID,
+ RESMGR_CHMMGR_INITIATE_VC_OPS_MSGID,
+ RESMGR_CHMMGR_INITIATE_WAL_OPS_MSGID,
+ RESMGR_EVENT_HANDLER_VDEV_MGR_MSGID,
+ RESMGR_EVENT_HANDLER_SCAN_POLICY_MSGID,
+ RESMGR_MSGID_DEFINITION_END = 0x7fff,
+} RESMGR_MSGID;
+
+/* VDEVMGR messageIDs for ML logging */
+typedef enum {
+ VDEV_MGR_MSGID_DEFINITION_START = 0x0000,
+ VDEV_MGR_RESMGR_CHMMGR_NOTIF_VDEV_UP_MSGID,
+ VDEV_MGR_FIRST_BMISS_DETECTED_MSGID,
+ VDEV_MGR_FINAL_BMISS_DETECTED_MSGID,
+ VDEV_MGR_MY_BEACON_RECEIVED_MSGID,
+ VDEV_MGR_VDEV_PAUSE_MSGID,
+ VDEV_MGR_VDEV_UNPAUSE_MSGID,
+ VDEV_MGR_VDEV_MIGRATE_MSGID,
+ VDEV_MGR_REGISTER_RESMGR_EVENT_MSGID,
+ VDEV_MGR_EVENT_HANDLER_VDEV_MSGID,
+ VDEV_MGR_EVENT_HANDLER_BEACON_MSGID,
+ VDEV_MGR_EVENT_HANDLER_MGMT_TXRX,
+ VDEV_MGR_EVENT_HANDLER_11D_SCAN_OFFLOAD_MSG_ID,
+ VDEV_MGR_EVENT_HANDLER_WOW_KEEPALIVE_MSGID,
+ VDEV_MGR_EVENT_HANDLER_EXTSCAN_MSGID,
+ VDEV_MGR_EVENT_HANDLER_SWBMISS_MSGID,
+ VDEV_MGR_EVENT_HANDLER_BEACON_DTIMSYNC_MSGID,
+ VDEV_MGR_EVENT_HANDLER_BEACON_TSFOOR_MSGID,
+ VDEV_MGR_THREAD_COMM_BE_FLOW_CTRL_MSGID,
+ VDEV_MGR_THREAD_COMM_SYNC_RT_DATA_OFFLOAD_MSGID,
+ VDEV_MGR_THREAD_COMM_BE_VDEV_STATE_CHANGE_MSGID,
+ VDEV_MGR_THREAD_COMM_VDEV_STATE_CHANGE_CONF_MSGID,
+ VDEV_MGR_MSGID_DEFINITION_END = 0x7fff,
+} VDEV_MGR_MSGID;
+
+/* SCAN messageIDs for ML logging */
+typedef enum {
+ SCAN_MSGID_DEFINITION_START = 0x0000,
+ SCAN_SCH_START_MSGID,
+ SCAN_EVENT_STARTED_MSGID,
+ SCAN_EVENT_FOREIGN_CHANNEL_MSGID,
+ SCAN_EVENT_FOREIGN_CHANNEL_EXIT_MSGID,
+ SCAN_EVENT_BSS_CHANNEL_MSGID,
+ SCAN_EVENT_PREEMPTED_MSGID,
+ SCAN_EVENT_RESTARTED_MSGID,
+ SCAN_EVENT_COMPLETED_MSGID,
+ SCAN_EVENT_DEQUEUED_MSGID,
+ SCAN_EVENT_SUSPENDED_MSGID,
+ SCAN_SCH_CANCEL_MSGID,
+ SCAN_SCH_SUSPEND_MSGID,
+ SCAN_MGR_EVENT_ASYNC_COMPLETE_MSGID,
+ SCAN_MGR_EVENT_COMPLETED_MSGID,
+ SCAN_MGR_EVENT_PREEMPTED_MSGID,
+ SCAN_MGR_EVENT_SUSPENDED_MSGID,
+ SCAN_POLICY_EVENT_MSGID,
+ SCAN_MGR_RESUME_EVENT_MSGID,
+ SCAN_MGR_SCAN_START_MSGID,
+ SCAN_MGR_CANCEL_MSGID,
+ SCAN_MGR_BCN_RECV_MSGID,
+ SCAN_MGR_CHECK_BAND_CHANNELS_MSGID,
+ SCAN_MGR_SCAN_POLICY_RECOMPUTE_MSGID,
+ SCAN_MGR_CLIENT_SCAN_POLICY_MSGID,
+ SCAN_ENG_START_MSGID,
+ SCAN_ENG_CANCEL_MSGID,
+ SCAN_SET_CHAN_LIST_MSGID,
+ SCAN_SEND_PROBE_REQ_RET_VDEV_MSGID,
+ SCAN_SEND_PROBE_REQ_RET_PASSIVE_MSGID,
+ SCAN_SEND_PROBE_REQ_2G_RET_MSGID,
+ SCAN_SEND_PROBE_REQ_5G_RET_MSGID,
+ SCAN_ADPATIVE_DWELL_ENABLED_MSGID,
+ SCAN_ADAPTIVE_DWELL_CH_ACTIVITY_START_MSGID,
+ SCAN_ADAPTIVE_DWELL_CH_ACTIVITY_END_MSGID,
+ SCAN_ADAPTIVE_DWELL_CH_CONGESTION_CHECK_MSGID,
+ SCAN_ADAPTIVE_DWELL_ACTIVE_STARTED_MSGID,
+ SCAN_ADAPTIVE_DWELL_ALL_PROBE_SENT_MSGID,
+ SCAN_ADAPTIVE_DWELL_PASSIVE_STARTED_MSGID,
+ SCAN_ADAPTIVE_DWELL_SWITCH_ACTIVE_MSGID,
+ SCAN_REGISTER_OFFLDMGR_CH_PREDICTION_MSGID,
+ SCAN_DEREGISTER_OFFLDMGR_CH_PREDICTION_MSGID,
+ SCAN_REGISTER_OFFLDMGR_ADAPTIVE_BCNPRB_MSGID,
+ SCAN_DEREGISTER_OFFLDMGR_ADAPTIVE_BCNPRB_MSGID,
+ SCAN_EVENT_HANDLER_MGMT_TXRX_MSGID,
+ SCAN_EVENT_HANDLER_NLO_MSGID,
+ SCAN_EVENT_HANDLER_SCAN_AUTOCHAN_MSGID,
+ SCAN_EVENT_HANDLER_VDEVMGR_MSGID,
+ SCAN_EVENT_HANDLER_OFFLOAD_BEACON_MSGID,
+ SCAN_EVENT_HANDLER_STA_TWT_MSGID,
+ SCAN_EVENT_HANDLER_BATCH_SCAN_MSGID,
+ SCAN_MSGID_DEFINITION_END = 0x7fff,
+} SCAN_MSGID;
+
+/* MGMT_TXRX messageIDs for ML logging */
+typedef enum {
+ MGMT_TXRX_MSGID_DEFINITION_START = 0x0000,
+ MGMT_TXRX_WAL_LOCAL_FRAME_SEND_MSGID,
+ MGMT_TXRX_WAL_FRAME_SEND_MSGID,
+ MGMT_TXRX_FORWARD_TO_HOST_MSGID,
+ DATA_TXRX_WAL_LOCAL_FRAME_SEND_MSGID,
+ MGMT_TXRX_MSGID_DEFINITION_END = 0x7fff,
+} MGMT_TXRX_MSGID;
+
+/* OFFLOAD messageIDs for ML logging */
+typedef enum {
+ OFFLOAD_MSGID_DEFINITION_START = 0x0000,
+ OFFLOAD_MGMT_RX_FRAME_ALLOW_MSGID,
+ OFFLOAD_MGMT_RX_FRAME_DROP_MSGID,
+ OFFLOAD_PROTO_DATA_RX_FRAME_STATUS_MSGID,
+ OFFLOAD_PROTO_DATA_RX_FRAME_TYPE_MSGID,
+ OFFLOAD_SCAN_CH_PREDICTION_MSGID,
+ OFFLOAD_SCAN_ADAPTIVE_BCNPRB_MSGID,
+ OFFLOAD_VDEV_OWN_BEACON_MSGID,
+ OFFLOAD_VDEV_BEACON_FILTER_MSGID,
+ OFFLOAD_VDEV_CONNECTING_MSGID,
+ OFFLOAD_11D_SCAN_MSGID,
+ OFFLOAD_BATCH_SCAN_MSGID,
+ OFFLOAD_OBSS_SCAN_MSGID,
+ OFFLOAD_ARP_RECV_MSGID,
+ OFFLOAD_ARP_DROP_MSGID,
+ OFFLOAD_ARP_REPLY_SUCCESS_MSGID,
+ OFFLOAD_ARP_REPLY_FAIL_MSGID,
+ OFFLOAD_NS_RECV_MSGID,
+ OFFLOAD_NS_DROP_MSGID,
+ OFFLOAD_NS_REPLY_SUCCESS_MSGID,
+ OFFLOAD_NS_REPLY_FAIL_MSGID,
+ OFFLOAD_GTK_PROESS_REKEY_MSGID,
+ OFFLOAD_GTK_REPLY_REKEY_MSGID,
+ OFFLOAD_GTK_PROESS_REKEY_FAIL_MSGID,
+ OFFLOAD_SUPPL_EAP_RECV_MSGID,
+ OFFLOAD_SUPPL_EAP_1X_MSGID,
+ OFFLOAD_MSGID_DEFINITION_END = 0x7fff,
+} OFFLOAD_MSGID;
+
+/* STA_PWRSAVE messageIDs for ML logging */
+typedef enum {
+ STA_PWRSAVE_MSGID_DEFINITION_START = 0x0000,
+ STA_PWRSAVE_ARBITER_REQUEST_MSGID,
+ STA_PWRSAVE_MSGID_DEFINITION_END = 0x7fff,
+} STA_PWRSAVE_MSGID;
+
+/* COEX messageIDs for ML logging */
+typedef enum {
+ COEX_MSGID_DEFINITION_START = 0x0000,
+ COEX_ASM_ANTENNA_REQUEST_MSGID,
+ COEX_ASM_ANTENNA_RELEASE_MSGID,
+ COEX_EVENT_HANDLER_RESMGR_MSGID,
+ COEX_EVENT_HANDLER_SCAN_ANT_MSGID,
+ COEX_EVENT_HANDLER_VDEV_ANT_OP_MSGID,
+ COEX_MSGID_DEFINITION_END = 0x7fff,
+} COEX_MSGID;
+
+/* STA_SMPS messageIDs for ML logging */
+typedef enum {
+ STA_SMPS_MSGID_DEFINITION_START = 0x0000,
+ STA_SMPS_VC_CFG_NOTIFY_MSGID,
+ STA_SMPS_MSGID_EDFINITION_END = 0x7fff,
+} STA_SMPS_MSGID;
+
+/* WAL messageIDs for ML logging */
+typedef enum {
+ WAL_MSGID_DEFINITION_START = 0x0000,
+ WAL_PDEV_CHANNEL_CHANGE_MSGID,
+ WAL_PDEV_HALPHY_RUN_DPD_CAL_MSGID,
+ WAL_TX_MGMT_COMP_MSGID,
+ WAL_TX_MGMT_ENQUEUE_MSGID,
+ WAL_RX_SUSPEND_START_MSGID,
+ WAL_RX_SUSPEND_SUCCESS_MSGID,
+ WAL_RX_RESUME_START_MSGID,
+ WAL_SOC_SWITCH_MODE_MSGID,
+ WAL_CONNECTION_PAUSE_BLOCK_ENABLE_MSGID,
+ WAL_CONNECTION_PAUSE_BLOCK_DISABLE_MSGID,
+ WAL_VDEV_PAUSE_ENABLE_MSGID,
+ WAL_VDEV_PAUSE_DISABLE_MSGID,
+ WAL_VDEV_PAUSE_RESET_MSGID,
+ WAL_PDEV_PAUSE_ENABLE_MSGID,
+ WAL_PDEV_PAUSE_DISABLE_MSGID,
+ WAL_PEER_SEND_N_REQ_MSGID,
+ WAL_PEER_PS_PRE_REQ_MSGID,
+ WAL_CONNECTION_PAUSE_ATTACH_TID_MSGID,
+ WAL_PDEV_PAUSE_NOTIFY_VDEV_CREATE_MSGID,
+ WAL_CONNECTION_PAUSE_PEER_CREATE_MSGID,
+ WAL_CONNECTION_PAUSE_TIDQ_HWQ_EMPTY_MSGID,
+ WAL_TX_SEND_ABORT_TX_MSGID,
+ WAL_TX_SEND_RESUME_TX_MSGID,
+ WAL_TX_FLUSH_TID_MSGID,
+ WAL_TX_FLUSH_PEER_MSGID,
+ WAL_TX_FLUSH_VDEV_MSGID,
+ WAL_VDEV_UP_MSGID,
+ WAL_VDEV_START_MSGID,
+ WAL_VDEV_DOWN_MSGID,
+ WAL_VDEV_STOP_MSGID,
+ WAL_VDEV_MIGRATE_MSGID,
+ WAL_PEER_CONSECUTIVE_FAILURE_MSGID,
+ WAL_PEER_CONSECUTIVE_FAILURE_RESET_MSGID,
+ WAL_PEER_STA_KICKOUT_MSGID,
+ SM_DISPATCH_EVENT_MSGID,
+ SM_STATE_TRANSITION_MSGID,
+ WAL_THREAD_COMM_TX_PAUSE_HWQ_EMPTY_MSGID,
+ WAL_THREAD_COMM_PEER_TX_PAUSE_REQ_MSGID,
+ WAL_THREAD_COMM_PEER_TX_UNPAUSE_REQ_MSGID,
+ WAL_THREAD_COMM_VDEV_TX_PAUSE_REQ_MSGID,
+ WAL_THREAD_COMM_PDEV_TX_PAUSE_REQ_MSGID,
+ WAL_THREAD_COMM_VDEV_TX_UNPAUSE_REQ_MSGID,
+ WAL_THREAD_COMM_PDEV_TX_UNPAUSE_REQ_MSGID,
+ WAL_THREAD_COMM_VDEV_TX_PAUSE_RESET_IND_MSGID,
+ WAL_THREAD_COMM_PEER_TX_BLOCK_REQ_MSGID,
+ WAL_THREAD_COMM_PEER_TX_UNBLOCK_REQ_MSGID,
+ WAL_THREAD_COMM_PEER_SEND_N_REQ_MSGID,
+ WAL_THREAD_COMM_PEER_PS_PRE_REQ_MSGID,
+ WAL_THREAD_COMM_TX_PAUSE_TID_CREATE_MSGID,
+ WAL_THREAD_COMM_TX_PAUSE_VDEV_CREATE_MSGID,
+ WAL_THREAD_COMM_TX_PAUSE_POST_RESPONSE_MSGID,
+ WAL_THREAD_COMM_PDEV_EVENT_HANDLER_MSGID,
+ WAL_THREAD_COMM_VDEV_EVENT_HANDLER_MSGID,
+ WAL_THREAD_COMM_PEER_EVENT_HANDLER_MSGID,
+ WAL_THREAD_COMM_POWER_MSGID,
+ WAL_THREAD_COMM_RT_POWER_BEACON_TIMEOUT_MSGID,
+ WAL_THREAD_COMM_RT_POWER_SUSPEND_FAIL_RESET_MSGID,
+ WAL_THREAD_COMM_RT_DATA_NULL_DEAUTH_MSGID,
+ WAL_THREAD_COMM_LOCAL_SEND_WITH_RATE_MSGID,
+ WAL_THREAD_COMM_LOCAL_SEND_COMPLETION_MSGID,
+ WAL_THREAD_COMM_TX_FLUSH_ENTITY_TID_MSGID,
+ WAL_THREAD_COMM_TX_FLUSH_ENTITY_PEER_MSGID,
+ WAL_THREAD_COMM_TX_FLUSH_ENTITY_VDEV_MSGID,
+ WAL_THREAD_COMM_TX_FLUSH_COMPLETE_MSGID,
+ WAL_THREAD_COMM_TAC_TID_LIST_OP_MSGID,
+ WAL_THREAD_COMM_TAC_TX_SCHED_MSGID,
+ WAL_THREAD_COMM_BE_RX_ATTACH_MSGID,
+ WAL_THREAD_COMM_TT_CONTROL_MSGID,
+ WAL_THREAD_COMM_RT_EXEC_DEV_RESET_MSGID,
+ WAL_THREAD_COMM_VDEV_MIGRATION_SYNC_MSGID,
+ WAL_THREAD_COMM_BE_SOC_SUSPEND_NOTIFY_MSGID,
+ WAL_THREAD_COMM_RT_SOC_SUSPEND_CONF_MSGID,
+ WAL_THREAD_COMM_TX_ABORT_MSGID,
+ WAL_THREAD_COMM_TX_RESUME_MSGID,
+ WAL_THREAD_COMM_RT_WPM_EXIT_HW_DTIM_AWAKE_MSGID,
+ WAL_THREAD_COMM_BE_RX_PROC_MSGID,
+ WAL_THREAD_COMM_BE_PEER_SET_PARAM_MSGID,
+ WAL_THREAD_COMM_PEER_SEND_MSG_MSGID,
+ WAL_THREAD_COMM_TID_DEL_MSGID,
+ WAL_TX_PAUSE_REQ_HANDLER_MSGID,
+ WAL_TX_PAUSE_RSP_HANDLER_MSGID,
+ WAL_SW_DTIM_POWER_MSG_HANDLER_MSGID,
+ WAL_PEER_KEY_SET_MSGID,
+ WAL_PEER_WAPI_EAPOL_TX_SEND_COMPLETE_MSGID,
+ WAL_PEER_PTK_M4_SENT_MSGID,
+ WAL_PEER_ALLOW_DATA_MSGID,
+ WAL_EVENT_HANDLER_VDEV_PAUSE_MSGID,
+ WAL_EVENT_HANDLER_STA_SWTIM_MSGID,
+ WAL_EVENT_HANDLER_VDEV_RECONFIG_MSGID,
+ WAL_MSGID_DEFINITION_END = 0x7fff,
+} WAL_MSGID;
+
+/* WPM messageIDs for ML logging */
+typedef enum {
+ WPM_MSGID_DEFINITION_START = 0x0000,
+ WPM_ARBITER_REQUEST_MSGID,
+ WPM_MSGID_DEFINITION_END = 0x7fff,
+} WPM_MSGID;
+
+/* MLME messageIDs for ML logging */
+typedef enum {
+ MLME_MSGID_DEFINITION_START = 0x0000,
+ MLME_THREAD_COMM_BE_HTT_SVC_VDEV_CHANGE_MSGID,
+ MLME_THREAD_COMM_INSTALL_KEY_MSGID,
+ MLME_THREAD_COMM_STORE_KEY_MSGID,
+ MLME_THREAD_COMM_UPDATE_STATUS_MSGID,
+ MLME_THREAD_COMM_CMD_PROXY_MSGID,
+ MLME_MSGID_DEFINITION_END = 0x7fff,
+} MLME_MSGID;
+
+typedef enum {
+ SUPPL_MSGID_DEFINITION_START = 0x0000,
+ SUPPL_THREAD_COMM_INIT_AUTH_MSGID,
+ SUPPL_THREAD_COMM_STATUS_CHANGE_EVT_MSGID,
+ SUPPL_MSGID_DEFINITION_END = 0x7fff,
+} SUPPL_MSGID;
+
+typedef enum {
+ AP_PWRSAVE_MSGID_DEFINITION_START = 0x0000,
+ AP_PWRSAVE_EVENT_HANDLER_SLEEP_STA_UPDATE_MSGID,
+ AP_PWRSAVE_MSGID_DEFINITION_END = 0x7fff,
+} AP_PWRSAVE_MSGID;
+
/* INF debug identifier definitions */
#define INF_DBGID_DEFINITION_START 0
@@ -1757,6 +2075,12 @@
#define WLAN_MODULE_QBOOST_DBGID_WLAN_PEER_NOT_FOUND 1
#define WLAN_MODULE_QBOOST_DEFINITION_END 2
+/* HPCS DBGID */
+#define HPCS_PULSE_START 0
+#define HPCS_PULSE_LF_TIMER 1
+#define HPCS_PULSE_HF_TIMER 2
+#define HPCS_PULSE_POWER_SAVE 3
+
#ifdef __cplusplus
}
#endif
diff --git a/drivers/staging/fw-api/fw/htc.h b/drivers/staging/fw-api/fw/htc.h
index 92b3b68..348c719 100644
--- a/drivers/staging/fw-api/fw/htc.h
+++ b/drivers/staging/fw-api/fw/htc.h
@@ -120,6 +120,11 @@
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
#define HTC_FLAGS_SEQ_CHECK (1 << 2) /* seq check on rx side */
#define HTC_FLAGS_CRC_CHECK (1 << 3) /* CRC check on rx side */
+/* HTC_FLAGS_PADDING_CHECK
+ * Set by the sender to inform the receiver that the HTC packet begins
+ * with continuation (block) alignment padding from the prior HTC packet.
+ */
+#define HTC_FLAGS_PADDING_CHECK (1 << 4)
/* receive direction */
#define HTC_FLAGS_RECV_1MORE_BLOCK (1 << 0) /* bit 0 bundle trailer present */
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
diff --git a/drivers/staging/fw-api/fw/htt.h b/drivers/staging/fw-api/fw/htt.h
index e56ca9d..2508b93 100644
--- a/drivers/staging/fw-api/fw/htt.h
+++ b/drivers/staging/fw-api/fw/htt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -165,9 +165,35 @@
* HTT_T2H_MSG_TYPE_PKTLOG
* 3.49 Add HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND def
* 3.50 Add learning_frame flag to htt_tx_msdu_desc_ext2_t
+ * 3.51 Add SW peer ID and TID num to HTT TX WBM COMPLETION
+ * 3.52 Add HTT_T2H FLOW_POOL_RESIZE msg def
+ * 3.53 Update HTT_T2H FLOW_POOL_RESIZE msg def
+ * 3.54 Define mcast and mcast_valid flags within htt_tx_wbm_transmit_status
+ * 3.55 Add initiator / responder flags to RX_DELBA indication
+ * 3.56 Fix HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE bit-mask defs
+ * 3.57 Add support for in-band data within HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND
+ * 3.58 Add optional MSDU ack RSSI array to end of HTT_T2H TX_COMPL_IND msg
+ * 3.59 Add HTT_RXDMA_HOST_BUF_RING2 def
+ * 3.60 Add HTT_T2H_MSG_TYPE_PEER_STATS_IND def
+ * 3.61 Add rx offset fields to HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG msg
+ * 3.62 Add antenna mask to reserved space in htt_rx_ppdu_desc_t
+ * 3.63 Add HTT_HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND def
+ * 3.64 Add struct htt_tx_compl_ind_append_tx_tsf64 and add tx_tsf64
+ * array to the end of HTT_T2H TX_COMPL_IND msg
+ * 3.65 Add fields in htt_tx_msdu_desc_ext2_t to allow the host to provide
+ * a "cookie" to identify a MSDU, and to specify to not apply aggregation
+ * for a MSDU.
+ * 3.66 Add HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND msg.
+ * Add PKT_CAPTURE_MODE flag within HTT_T2H TX_I_ORD_PADDR_IND msg.
+ * 3.67 Add drop threshold field to HTT_H2T RX_RING_SELECTION_CFG msg.
+ * 3.68 Add ipa_drop threshold fields to HTT_H2T_MSG_TYPE_SRING_SETUP
+ * 3.69 Add htt_ul_ofdma_user_info_v0 defs
+ * 3.70 Add AST1-AST3 fields to HTT_T2H PEER_MAP_V2 msg
+ * 3.71 Add rx offload engine / flow search engine htt setup message defs for
+ * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG, HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG
*/
#define HTT_CURRENT_VERSION_MAJOR 3
-#define HTT_CURRENT_VERSION_MINOR 50
+#define HTT_CURRENT_VERSION_MINOR 71
#define HTT_NUM_TX_FRAG_DESC 1024
@@ -506,6 +532,8 @@
HTT_H2T_MSG_TYPE_RFS_CONFIG = 0xf,
HTT_H2T_MSG_TYPE_EXT_STATS_REQ = 0x10,
HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11,
+ HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12,
+ HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13,
/* keep this last */
HTT_H2T_NUM_MSGS
@@ -1645,18 +1673,34 @@
/* DWORD 4: tx expiry time (TSF) MSBs */
A_UINT32 expire_tsf_hi;
- /* DWORD 5: reserved
- * This structure can be expanded further up to 60 bytes
- * by adding further DWORDs as needed.
- */
+ /* DWORD 5: flags to control routing / processing of the MSDU */
A_UINT32
/* learning_frame
* When this flag is set, this frame will be dropped by FW
* rather than being enqueued to the Transmit Queue Manager (TQM) HW.
*/
- learning_frame : 1,
- rsvd0 : 31;
+ learning_frame : 1,
+ /* send_as_standalone
+ * This will indicate if the msdu needs to be sent as a singleton PPDU,
+ * i.e. with no A-MSDU or A-MPDU aggregation.
+ * The scope is extended to other use-cases.
+ */
+ send_as_standalone : 1,
+ /* is_host_opaque_valid
+ * Host should set this bit to 1 if the host_opaque_cookie is populated
+ * with valid information.
+ */
+ is_host_opaque_valid : 1,
+ rsvd0 : 29;
+ /* DWORD 6 : Host opaque cookie for special frames */
+ A_UINT32 host_opaque_cookie : 16, /* see is_host_opaque_valid */
+ rsvd1 : 16;
+
+ /*
+ * This structure can be expanded further up to 40 bytes
+ * by adding further DWORDs as needed.
+ */
} POSTPACK;
/* DWORD 0 */
@@ -1724,6 +1768,15 @@
/* DWORD 5 */
#define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_M 0x00000001
#define HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S 0
+#define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M 0x00000002
+#define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S 1
+#define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M 0x00000004
+#define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S 2
+
+/* DWORD 6 */
+#define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M 0x0000FFFF
+#define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S 0
+
/* DWORD 0 */
#define HTT_TX_MSDU_EXT2_DESC_FLAG_VALID_PWR_GET(_var) \
@@ -1995,6 +2048,36 @@
((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_LEARNING_FRAME_S)); \
} while (0)
+#define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_GET(_var) \
+ (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_M) >> \
+ HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S)
+
+#define HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE, _val); \
+ ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_SEND_AS_STANDALONE_S)); \
+ } while (0)
+
+#define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_GET(_var) \
+ (((_var) & HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_M) >> \
+ HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S)
+#define HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID, _val); \
+ ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_FLAG_HOST_OPAQUE_VALID_S)); \
+ } while (0)
+
+/* DWORD 6 */
+#define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_GET(_var) \
+ (((_var) & HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_M) >> \
+ HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S)
+#define HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE, _val); \
+ ((_var) |= ((_val) << HTT_TX_MSDU_EXT2_DESC_HOST_OPAQUE_COOKIE_S)); \
+ } while (0)
+
+
typedef enum {
HTT_TCL_METADATA_TYPE_PEER_BASED = 0,
HTT_TCL_METADATA_TYPE_VDEV_BASED = 1,
@@ -2331,7 +2414,18 @@
* Units: dB w.r.t noise floor
*/
A_UINT32
- reserved0: 32;
+ sw_peer_id: 16,
+ tid_num: 5,
+ valid: 1, /* If this "valid" flag is set, the sw_peer_id
+ * and tid_num fields contain valid data.
+ * If this "valid" flag is not set, the
+ * sw_peer_id and tid_num fields must be ignored.
+ */
+ mcast: 1,
+ mcast_valid: 1, /* If this "mcast_valid" is set, the mcast field
+ * contains valid data.
+ */
+ reserved0: 8;
A_UINT32
reserved1: 32;
} POSTPACK;
@@ -2342,6 +2436,18 @@
#define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_M 0xff000000
#define HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S 24
+/* DWORD 5 */
+#define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M 0x0000ffff
+#define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S 0
+#define HTT_TX_WBM_COMPLETION_V2_TID_NUM_M 0x001f0000
+#define HTT_TX_WBM_COMPLETION_V2_TID_NUM_S 16
+#define HTT_TX_WBM_COMPLETION_V2_VALID_M 0x00200000
+#define HTT_TX_WBM_COMPLETION_V2_VALID_S 21
+#define HTT_TX_WBM_COMPLETION_V2_MCAST_M 0x00400000
+#define HTT_TX_WBM_COMPLETION_V2_MCAST_S 22
+#define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M 0x00800000
+#define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S 23
+
/* DWORD 4 */
#define HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_GET(_var) \
(((_var) & HTT_TX_WBM_COMPLETION_V2_SCH_CMD_ID_M) >> \
@@ -2363,6 +2469,57 @@
((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_ACK_FRAME_RSSI_S)); \
} while (0)
+/* DWORD 5 */
+#define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_M) >> \
+ HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_SW_PEER_ID_S)); \
+ } while (0)
+
+#define HTT_TX_WBM_COMPLETION_V2_TID_NUM_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V2_TID_NUM_M) >> \
+ HTT_TX_WBM_COMPLETION_V2_TID_NUM_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_TID_NUM_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_TID_NUM, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_TID_NUM_S)); \
+ } while (0)
+
+#define HTT_TX_WBM_COMPLETION_V2_VALID_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V2_VALID_M) >> \
+ HTT_TX_WBM_COMPLETION_V2_VALID_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_VALID, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_VALID_S)); \
+ } while (0)
+
+#define HTT_TX_WBM_COMPLETION_V2_MCAST_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_M) >> \
+ HTT_TX_WBM_COMPLETION_V2_MCAST_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_MCAST_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_S)); \
+ } while (0)
+
+#define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_GET(_var) \
+ (((_var) & HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_M) >> \
+ HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)
+
+#define HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_WBM_COMPLETION_V2_MCAST_VALID, _val); \
+ ((_var) |= ((_val) << HTT_TX_WBM_COMPLETION_V2_MCAST_VALID_S)); \
+ } while (0)
+
/**
* @brief HTT TX WBM reinject status from firmware to host
* @details
@@ -4149,9 +4306,9 @@
* setup message
*
* The message would appear as follows:
- * |31 24|23 20|19|18 16|15|14 8|7 0|
- * |--------------- +-----------------+----------------+------------------|
- * | ring_type | ring_id | pdev_id | msg_type |
+ * |31 24|23 21|20|19|18 16|15|14 8|7 0|
+ * |--------------- +-----------------+-----------------+-----------------|
+ * | ring_type | ring_id | pdev_id | msg_type |
* |----------------------------------------------------------------------|
* | ring_base_addr_lo |
* |----------------------------------------------------------------------|
@@ -4175,12 +4332,15 @@
* |----------------------------------------------------------------------|
* | intr_timer_th |IM| intr_batch_counter_th |
* |----------------------------------------------------------------------|
- * | reserved |RR|PTCF| intr_low_threshold |
+ * | reserved |ID|RR| PTCF| intr_low_threshold |
+ * |----------------------------------------------------------------------|
+ * | reserved |IPA drop thres hi|IPA drop thres lo|
* |----------------------------------------------------------------------|
* Where
* IM = sw_intr_mode
* RR = response_required
* PTCF = prefetch_timer_cfg
+ * IP = IPA drop flag
*
* The message is interpreted as follows:
* dword0 - b'0:7 - msg_type: This will be set to
@@ -4263,7 +4423,12 @@
* Others: Reserverd
* b'19 - response_required:
* Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response
- * b'20:31 - reserved: reserved for future use
+ * b'20 - ipa_drop_flag:
+ Indicates that host will config ipa drop threshold percentage
+ * b'21:31 - reserved: reserved for future use
+ * dword13 - b'0:7 - ipa drop low threshold percentage:
+ * b'8:15 - ipa drop high threshold percentage:
+ * b'16:31 - Reserved
*/
PREPACK struct htt_sring_setup_t {
A_UINT32 msg_type: 8,
@@ -4288,7 +4453,11 @@
A_UINT32 intr_low_threshold: 16,
prefetch_timer_cfg: 3,
response_required: 1,
- reserved1: 12;
+ ipa_drop_flag: 1,
+ reserved1: 11;
+ A_UINT32 ipa_drop_low_threshold: 8,
+ ipa_drop_high_threshold: 8,
+ reserved: 16;
} POSTPACK;
enum htt_srng_ring_type {
@@ -4307,6 +4476,7 @@
HTT_HOST1_TO_FW_RXBUF_RING, /* (mobile only) used by host to provide remote RX buffers */
HTT_HOST2_TO_FW_RXBUF_RING, /* (mobile only) second ring used by host to provide remote RX buffers */
HTT_RXDMA_NON_MONITOR_DEST_RING, /* Per MDPU indication to host for non-monitor RxDMA traffic upload */
+ HTT_RXDMA_HOST_BUF_RING2, /* Second ring used by FW to feed removed buffers and update removed packets */
/* Add Other SRING which can't be directly configured by host software above this line */
};
@@ -4643,9 +4813,9 @@
*
* The message would appear as follows:
*
- * |31 26|25|24|23 16|15 8|7 0|
- * |-----------------+----------------+----------------+---------------|
- * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type |
+ * |31 28|27|26|25|24|23 16|15 |9 8|7 0|
+ * |-----+--+--+--+--+----------------+------------+---+---------------|
+ * |rsvd1|DT|OV|PS|SS| ring_id | pdev_id | msg_type |
* |-------------------------------------------------------------------|
* | rsvd2 | ring_buffer_size |
* |-------------------------------------------------------------------|
@@ -4659,9 +4829,21 @@
* |-------------------------------------------------------------------|
* | tlv_filter_in_flags |
* |-------------------------------------------------------------------|
+ * | rx_header_offset | rx_packet_offset |
+ * |-------------------------------------------------------------------|
+ * | rx_mpdu_start_offset | rx_mpdu_end_offset |
+ * |-------------------------------------------------------------------|
+ * | rx_msdu_start_offset | rx_msdu_end_offset |
+ * |-------------------------------------------------------------------|
+ * | rsvd3 | rx_attention_offset |
+ * |-------------------------------------------------------------------|
+ * | rsvd4 | rx_drop_threshold |
+ * |-------------------------------------------------------------------|
* Where:
* PS = pkt_swap
* SS = status_swap
+ * OV = rx_offsets_valid
+ * DT = drop_thresh_valid
* The message is interpreted as follows:
* dword0 - b'0:7 - msg_type: This will be set to
* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG
@@ -4670,9 +4852,17 @@
* 1/2/3 mac id (for rings at LMAC level)
* b'16:23 - ring_id : Identify the ring to configure.
* More details can be got from enum htt_srng_ring_id
- * b'24 - status_swap: 1 is to swap status TLV
- * b'25 - pkt_swap: 1 is to swap packet TLV
- * b'26:31 - rsvd1: reserved for future use
+ * b'24 - status_swap (SS): 1 is to swap status TLV - refer to
+ * BUF_RING_CFG_0 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * b'25 - pkt_swap (PS): 1 is to swap packet TLV - refer to
+ * BUF_RING_CFG_0 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * b'26 - rx_offset_valid (OV): flag to indicate rx offsets
+ * configuration fields are valid
+ * b'27 - drop_thresh_valid (DT): flag to indicate if the
+ * rx_drop_threshold field is valid
+ * b'28:31 - rsvd1: reserved for future use
* dword1 - b'0:16 - ring_buffer_size: size of bufferes referenced by rx ring,
* in byte units.
* Valid only for HW_TO_SW_RING and SW_TO_HW_RING
@@ -4701,14 +4891,56 @@
* dword6 - b'0:31 - tlv_filter_in_flags:
* Filter in Attention/MPDU/PPDU/Header/User tlvs
* Refer to CFG_TLV_FILTER_IN_FLAG defs
+ * dword7 - b'0:15 - rx_packet_offset: rx_packet_offset in byte units
+ * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ * A value of 0 will be considered as ignore this config.
+ * Refer to BUF_RING_CFG_1 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * - b'16:31 - rx_header_offset: rx_header_offset in byte units
+ * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ * A value of 0 will be considered as ignore this config.
+ * Refer to BUF_RING_CFG_1 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * dword8 - b'0:15 - rx_mpdu_end_offset: rx_mpdu_end_offset in byte units
+ * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ * A value of 0 will be considered as ignore this config.
+ * Refer to BUF_RING_CFG_2 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * - b'16:31 - rx_mpdu_start_offset: rx_mpdu_start_offset in byte units
+ * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ * A value of 0 will be considered as ignore this config.
+ * Refer to BUF_RING_CFG_2 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * dword9 - b'0:15 - rx_msdu_end_offset: rx_msdu_end_offset in byte units
+ * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ * A value of 0 will be considered as ignore this config.
+ * Refer to BUF_RING_CFG_3 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * - b'16:31 - rx_msdu_start_offset: rx_msdu_start_offset in byte units
+ * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ * A value of 0 will be considered as ignore this config.
+ * Refer to BUF_RING_CFG_3 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * dword10- b'0:15 - rx_attention_offset: rx_attention_offset in byte units
+ * Valid only for HW_TO_SW_RING and SW_TO_HW_RING
+ * A value of 0 will be considered as ignore this config.
+ * Refer to BUF_RING_CFG_4 defs within HW .h files,
+ * e.g. wmac_top_reg_seq_hwioreg.h
+ * - b'16:31 - rsvd3 for future use
+ * dword11- b'9:0 - rx_drop_threshold: Threshold configured in monitor mode
+ * to source rings. Consumer drops packets if the available
+ * words in the ring falls below the configured threshold
+ * value.
*/
PREPACK struct htt_rx_ring_selection_cfg_t {
- A_UINT32 msg_type: 8,
- pdev_id: 8,
- ring_id: 8,
- status_swap: 1,
- pkt_swap: 1,
- rsvd1: 6;
+ A_UINT32 msg_type: 8,
+ pdev_id: 8,
+ ring_id: 8,
+ status_swap: 1,
+ pkt_swap: 1,
+ rx_offsets_valid: 1,
+ drop_thresh_valid: 1,
+ rsvd1: 4;
A_UINT32 ring_buffer_size: 16,
rsvd2: 16;
A_UINT32 packet_type_enable_flags_0;
@@ -4716,6 +4948,16 @@
A_UINT32 packet_type_enable_flags_2;
A_UINT32 packet_type_enable_flags_3;
A_UINT32 tlv_filter_in_flags;
+ A_UINT32 rx_packet_offset: 16,
+ rx_header_offset: 16;
+ A_UINT32 rx_mpdu_end_offset: 16,
+ rx_mpdu_start_offset: 16;
+ A_UINT32 rx_msdu_end_offset: 16,
+ rx_msdu_start_offset: 16;
+ A_UINT32 rx_attn_offset: 16,
+ rsvd3: 16;
+ A_UINT32 rx_drop_threshold: 10,
+ rsvd4: 22;
} POSTPACK;
#define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t))
@@ -4764,6 +5006,28 @@
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_PKT_TLV_SWAP_S)); \
} while (0)
+#define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M 0x04000000
+#define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S 26
+#define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_OFFSETS_VALID_S)); \
+ } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M 0x08000000
+#define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S 27
+#define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_M) >> \
+ HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S)
+#define HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_DROP_THRESHOLD_VALID_S)); \
+ } while (0)
+
#define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_M 0x0000ffff
#define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_S 0
#define HTT_RX_RING_SELECTION_CFG_RING_BUFFER_SIZE_GET(_var) \
@@ -4830,6 +5094,94 @@
((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_TLV_FILTER_IN_FLAG_S)); \
} while (0)
+#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M 0x0000ffff
+#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S 0
+#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET_S)); \
+ } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M 0xffff0000
+#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S 16
+#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET_S)); \
+ } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M 0x0000ffff
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S 0
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET_S)); \
+ } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M 0xffff0000
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S 16
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET_S)); \
+ } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M 0x0000ffff
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S 0
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET_S)); \
+ } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M 0xffff0000
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S 16
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET_S)); \
+ } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M 0x0000ffff
+#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S 0
+#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET_S)); \
+ } while (0)
+
+#define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M 0x000003ff
+#define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S 0
+#define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_GET(_var) \
+ (((_var) & HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_M) >> \
+ HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S)
+#define HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD, _val); \
+ ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S)); \
+ } while (0)
+
/*
* Subtype based MGMT frames enable bits.
* FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other
@@ -4915,23 +5267,23 @@
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_S 23
/* Beacon */
-#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000001
+#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000000
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_S 24
-#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000001
+#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000000
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_S 25
-#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x00000001
+#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x04000000
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_S 26
/* ATIM */
-#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x00000001
+#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x08000000
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_S 27
-#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x00000001
+#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x10000000
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_S 28
-#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x00000001
+#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x20000000
#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_S 29
/* Disassociation */
@@ -5478,6 +5830,466 @@
((_var) |= ((_val) << HTT_H2T_PPDU_STATS_CFG_TLV_BITMASK_S)); \
} while (0)
+/**
+ * @brief Host-->target HTT RX FSE setup message
+ * @details
+ * Through this message, the host will provide details of the flow tables
+ * in host DDR along with hash keys.
+ * This message can be sent per SOC or per PDEV, which is differentiated
+ * by pdev id values.
+ * The host will allocate flow search table and sends table size,
+ * physical DMA address of flow table, and hash keys to firmware to
+ * program into the RXOLE FSE HW block.
+ *
+ * The following field definitions describe the format of the RX FSE setup
+ * message sent from the host to target
+ *
+ * Header fields:
+ * dword0 - b'7:0 - msg_type: This will be set to
+ * HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG
+ * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
+ * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that
+ * pdev's LMAC ring.
+ * b'31:16 - reserved : Reserved for future use
+ * dword1 - b'19:0 - number of records: This field indicates the number of
+ * entries in the flow table. For example: 8k number of
+ * records is equivalent to
+ * 8 * 1024 * sizeof(RX_FLOW_SEARCH_ENTRY_STRUCT)
+ * b'27:20 - max search: This field specifies the skid length to FSE
+ * parser HW module whenever match is not found at the
+ * exact index pointed by hash.
+ * b'29:28 - ip_da_sa: This indicates which IPV4-IPV6 RFC to be used.
+ * Refer htt_ip_da_sa_prefix below for more details.
+ * b'31:30 - reserved: Reserved for future use
+ * dword2 - b'31:0 - base address lo: Lower 4 bytes base address of flow
+ * table allocated by host in DDR
+ * dword3 - b'31:0 - base address hi: Higher 4 bytes of base address of flow
+ * table allocated by host in DDR
+ * dword4:13 - b'31:0 - Toeplitz: 315 bits of Toeplitz keys for flow table
+ * entry hashing
+ *
+ *
+ * |31 30|29 28|27|26|25 20|19 16|15 8|7 0|
+ * |---------------------------------------------------------------|
+ * | reserved | pdev_id | MSG_TYPE |
+ * |---------------------------------------------------------------|
+ * |resvd|IPDSA| max_search | Number of records |
+ * |---------------------------------------------------------------|
+ * | base address lo |
+ * |---------------------------------------------------------------|
+ * | base address high |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 31_0 |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 63_32 |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 95_64 |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 127_96 |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 159_128 |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 191_160 |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 223_192 |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 255_224 |
+ * |---------------------------------------------------------------|
+ * | toeplitz key 287_256 |
+ * |---------------------------------------------------------------|
+ * | reserved | toeplitz key 314_288(26:0 bits) |
+ * |---------------------------------------------------------------|
+ * where:
+ * IPDSA = ip_da_sa
+ */
+
+/**
+ * @brief: htt_ip_da_sa_prefix
+ * 0x0 -> Prefix is 0x20010db8_00000000_00000000
+ * IPv6 addresses beginning with 0x20010db8 are reserved for
+ * documentation per RFC3849
+ * 0x1 -> Prefix is 0x00000000_00000000_0000ffff RFC4291 IPv4-mapped IPv6
+ * 0x2 -> Prefix is 0x0 RFC4291 IPv4-compatible IPv6
+ * 0x3 -> Prefix is 0x0064ff9b_00000000_00000000 RFC6052 well-known prefix
+ */
+
+enum htt_ip_da_sa_prefix {
+ HTT_RX_IPV6_20010db8,
+ HTT_RX_IPV4_MAPPED_IPV6,
+ HTT_RX_IPV4_COMPATIBLE_IPV6,
+ HTT_RX_IPV6_64FF9B,
+};
+
+PREPACK struct htt_h2t_msg_rx_fse_setup_t {
+ A_UINT32 msg_type:8, /* HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG */
+ pdev_id:8,
+ reserved0:16;
+ A_UINT32 num_records:20,
+ max_search:8,
+ ip_da_sa:2, /* htt_ip_da_sa_prefix enumeration */
+ reserved1:2;
+ A_UINT32 base_addr_lo;
+ A_UINT32 base_addr_hi;
+ A_UINT32 toeplitz31_0;
+ A_UINT32 toeplitz63_32;
+ A_UINT32 toeplitz95_64;
+ A_UINT32 toeplitz127_96;
+ A_UINT32 toeplitz159_128;
+ A_UINT32 toeplitz191_160;
+ A_UINT32 toeplitz223_192;
+ A_UINT32 toeplitz255_224;
+ A_UINT32 toeplitz287_256;
+ A_UINT32 toeplitz314_288:27,
+ reserved2:5;
+} POSTPACK;
+
+#define HTT_RX_FSE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_fse_setup_t))
+#define HTT_RX_FSE_OPERATION_SZ (sizeof(struct htt_h2t_msg_rx_fse_operation_t))
+
+#define HTT_RX_FSE_SETUP_HASH_314_288_M 0x07ffffff
+#define HTT_RX_FSE_SETUP_HASH_314_288_S 0
+
+/* DWORD 0: Pdev ID */
+#define HTT_RX_FSE_SETUP_PDEV_ID_M 0x0000ff00
+#define HTT_RX_FSE_SETUP_PDEV_ID_S 8
+#define HTT_RX_FSE_SETUP_PDEV_ID_GET(_var) \
+ (((_var) & HTT_RX_FSE_SETUP_PDEV_ID_M) >> \
+ HTT_RX_FSE_SETUP_PDEV_ID_S)
+#define HTT_RX_FSE_SETUP_PDEV_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_PDEV_ID, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_PDEV_ID_S)); \
+ } while (0)
+
+/* DWORD 1:num of records */
+#define HTT_RX_FSE_SETUP_NUM_REC_M 0x000fffff
+#define HTT_RX_FSE_SETUP_NUM_REC_S 0
+#define HTT_RX_FSE_SETUP_NUM_REC_GET(_var) \
+ (((_var) & HTT_RX_FSE_SETUP_NUM_REC_M) >> \
+ HTT_RX_FSE_SETUP_NUM_REC_S)
+#define HTT_RX_FSE_SETUP_NUM_REC_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_NUM_REC, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_NUM_REC_S)); \
+ } while (0)
+
+/* DWORD 1:max_search */
+#define HTT_RX_FSE_SETUP_MAX_SEARCH_M 0x0ff00000
+#define HTT_RX_FSE_SETUP_MAX_SEARCH_S 20
+#define HTT_RX_FSE_SETUP_MAX_SEARCH_GET(_var) \
+ (((_var) & HTT_RX_FSE_SETUP_MAX_SEARCH_M) >> \
+ HTT_RX_FSE_SETUP_MAX_SEARCH_S)
+#define HTT_RX_FSE_SETUP_MAX_SEARCH_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_MAX_SEARCH, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_MAX_SEARCH_S)); \
+ } while (0)
+
+/* DWORD 1:ip_da_sa prefix */
+#define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M 0x30000000
+#define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S 28
+#define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_GET(_var) \
+ (((_var) & HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_M) >> \
+ HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)
+#define HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_IP_DA_SA_PREFIX_S)); \
+ } while (0)
+
+/* DWORD 2: Base Address LO */
+#define HTT_RX_FSE_SETUP_BASE_ADDR_LO_M 0xffffffff
+#define HTT_RX_FSE_SETUP_BASE_ADDR_LO_S 0
+#define HTT_RX_FSE_SETUP_BASE_ADDR_LO_GET(_var) \
+ (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_LO_M) >> \
+ HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)
+#define HTT_RX_FSE_SETUP_BASE_ADDR_LO_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_LO, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_LO_S)); \
+ } while (0)
+
+/* DWORD 3: Base Address High */
+#define HTT_RX_FSE_SETUP_BASE_ADDR_HI_M 0xffffffff
+#define HTT_RX_FSE_SETUP_BASE_ADDR_HI_S 0
+#define HTT_RX_FSE_SETUP_BASE_ADDR_HI_GET(_var) \
+ (((_var) & HTT_RX_FSE_SETUP_BASE_ADDR_HI_M) >> \
+ HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)
+#define HTT_RX_FSE_SETUP_BASE_ADDR_HI_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_BASE_ADDR_HI, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_BASE_ADDR_HI_S)); \
+ } while (0)
+
+/* DWORD 4-12: Hash Value */
+#define HTT_RX_FSE_SETUP_HASH_VALUE_M 0xffffffff
+#define HTT_RX_FSE_SETUP_HASH_VALUE_S 0
+#define HTT_RX_FSE_SETUP_HASH_VALUE_GET(_var) \
+ (((_var) & HTT_RX_FSE_SETUP_HASH_VALUE_M) >> \
+ HTT_RX_FSE_SETUP_HASH_VALUE_S)
+#define HTT_RX_FSE_SETUP_HASH_VALUE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_VALUE, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_VALUE_S)); \
+ } while (0)
+
+/* DWORD 13: Hash Value 314:288 bits */
+#define HTT_RX_FSE_SETUP_HASH_314_288_GET(_var) \
+ (((_var) & HTT_RX_FSE_SETUP_HASH_314_288_M) >> \
+ HTT_RX_FSE_SETUP_HASH_314_288_S)
+#define HTT_RX_FSE_SETUP_HASH_314_288_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SETUP_HASH_314_288, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_SETUP_HASH_314_288_S)); \
+ } while (0)
+
+/**
+ * @brief Host-->target HTT RX FSE operation message
+ * @details
+ * The host will send this Flow Search Engine (FSE) operation message for
+ * every flow add/delete operation.
+ * The FSE operation includes FSE full cache invalidation or individual entry
+ * invalidation.
+ * This message can be sent per SOC or per PDEV which is differentiated
+ * by pdev id values.
+ *
+ * |31 16|15 8|7 1|0|
+ * |-------------------------------------------------------------|
+ * | reserved | pdev_id | MSG_TYPE |
+ * |-------------------------------------------------------------|
+ * | reserved | operation |I|
+ * |-------------------------------------------------------------|
+ * | ip_src_addr_31_0 |
+ * |-------------------------------------------------------------|
+ * | ip_src_addr_63_32 |
+ * |-------------------------------------------------------------|
+ * | ip_src_addr_95_64 |
+ * |-------------------------------------------------------------|
+ * | ip_src_addr_127_96 |
+ * |-------------------------------------------------------------|
+ * | ip_dst_addr_31_0 |
+ * |-------------------------------------------------------------|
+ * | ip_dst_addr_63_32 |
+ * |-------------------------------------------------------------|
+ * | ip_dst_addr_95_64 |
+ * |-------------------------------------------------------------|
+ * | ip_dst_addr_127_96 |
+ * |-------------------------------------------------------------|
+ * | l4_dst_port | l4_src_port |
+ * | (32-bit SPI incase of IPsec) |
+ * |-------------------------------------------------------------|
+ * | reserved | l4_proto |
+ * |-------------------------------------------------------------|
+ *
+ * where I is 1-bit ipsec_valid.
+ *
+ * The following field definitions describe the format of the RX FSE operation
+ * message sent from the host to target for every add/delete flow entry to flow
+ * table.
+ *
+ * Header fields:
+ * dword0 - b'7:0 - msg_type: This will be set to
+ * HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG
+ * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc
+ * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the
+ * specified pdev's LMAC ring.
+ * b'31:16 - reserved : Reserved for future use
+ * dword1 - b'0 - ipsec_valid: This indicates protocol IP or IPsec
+ * (Internet Protocol Security).
+ * IPsec describes the framework for providing security at
+ * IP layer. IPsec is defined for both versions of IP:
+ * IPV4 and IPV6.
+ * Please refer to htt_rx_flow_proto enumeration below for
+ * more info.
+ * ipsec_valid = 1 for IPSEC packets
+ * ipsec_valid = 0 for IP Packets
+ * b'7:1 - operation: This indicates types of FSE operation.
+ * Refer to htt_rx_fse_operation enumeration:
+ * 0 - No Cache Invalidation required
+ * 1 - Cache invalidate only one entry given by IP
+ * src/dest address at DWORD[2:9]
+ * 2 - Complete FSE Cache Invalidation
+ * 3 - FSE Disable
+ * 4 - FSE Enable
+ * b'31:8 - reserved: Reserved for future use
+ * dword2:9-b'31:0 - IP src/dest: IPV4/IPV6 source and destination address
+ * for per flow addition/deletion
+ * For IPV4 src/dest addresses, the first A_UINT32 is used
+ * and the subsequent 3 A_UINT32 will be padding bytes.
+ * For IPV6 src/dest Addresses, all A_UINT32 are used.
+ * dword10 -b'31:0 - L4 src port (15:0): 16-bit Source Port numbers range
+ * from 0 to 65535 but only 0 to 1023 are designated as
+ * well-known ports. Refer to [RFC1700] for more details.
+ * This field is valid only if
+ * (valid_ip_proto(l4_proto) && (ipsec_valid == 0))
+ * - L4 dest port (31:16): 16-bit Destination Port numbers
+ * range from 0 to 65535 but only 0 to 1023 are designated
+ * as well-known ports. Refer to [RFC1700] for more details.
+ * This field is valid only if
+ * (valid_ip_proto(l4_proto) && (ipsec_valid == 0))
+ * - SPI (31:0): Security Parameters Index is an
+ * identification tag added to the header while using IPsec
+ * for tunneling the IP traffici.
+ * Valid only if IPSec_valid bit (in DWORD1) is set to 1.
+ * dword11 -b'7:0 - l4_proto: This carries L4 protocol numbers, which are
+ * Assigned Internet Protocol Numbers.
+ * l4_proto numbers for standard protocol like UDP/TCP
+ * protocol at l4 layer, e.g. l4_proto = 6 for TCP,
+ * l4_proto = 17 for UDP etc.
+ * b'31:8 - reserved: Reserved for future use.
+ *
+ */
+
+PREPACK struct htt_h2t_msg_rx_fse_operation_t {
+ A_UINT32 msg_type:8,
+ pdev_id:8,
+ reserved0:16;
+ A_UINT32 ipsec_valid:1,
+ operation:7,
+ reserved1:24;
+ A_UINT32 ip_src_addr_31_0;
+ A_UINT32 ip_src_addr_63_32;
+ A_UINT32 ip_src_addr_95_64;
+ A_UINT32 ip_src_addr_127_96;
+ A_UINT32 ip_dest_addr_31_0;
+ A_UINT32 ip_dest_addr_63_32;
+ A_UINT32 ip_dest_addr_95_64;
+ A_UINT32 ip_dest_addr_127_96;
+ union {
+ A_UINT32 spi;
+ struct {
+ A_UINT32 l4_src_port:16,
+ l4_dest_port:16;
+ } ip;
+ } u;
+ A_UINT32 l4_proto:8,
+ reserved:24;
+} POSTPACK;
+
+/**
+ * Enumeration for IP Protocol or IPSEC Protocol
+ * IPsec describes the framework for providing security at IP layer.
+ * IPsec is defined for both versions of IP: IPV4 and IPV6.
+ */
+enum htt_rx_flow_proto {
+ HTT_RX_FLOW_IP_PROTO,
+ HTT_RX_FLOW_IPSEC_PROTO,
+};
+
+/**
+ * Enumeration for FSE Cache Invalidation
+ * 0 - No Cache Invalidation required
+ * 1 - Cache invalidate only one entry given by IP src/dest address at DWORD2:9
+ * 2 - Complete FSE Cache Invalidation
+ * 3 - FSE Disable
+ * 4 - FSE Enable
+ */
+enum htt_rx_fse_operation {
+ HTT_RX_FSE_CACHE_INVALIDATE_NONE,
+ HTT_RX_FSE_CACHE_INVALIDATE_ENTRY,
+ HTT_RX_FSE_CACHE_INVALIDATE_FULL,
+ HTT_RX_FSE_DISABLE,
+ HTT_RX_FSE_ENABLE,
+};
+
+/* DWORD 0: Pdev ID */
+#define HTT_RX_FSE_OPERATION_PDEV_ID_M 0x0000ff00
+#define HTT_RX_FSE_OPERATION_PDEV_ID_S 8
+#define HTT_RX_FSE_OPERATION_PDEV_ID_GET(_var) \
+ (((_var) & HTT_RX_FSE_OPERATION_PDEV_ID_M) >> \
+ HTT_RX_FSE_OPERATION_PDEV_ID_S)
+#define HTT_RX_FSE_OPERATION_PDEV_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_PDEV_ID, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_PDEV_ID_S)); \
+ } while (0)
+
+/* DWORD 1:IP PROTO or IPSEC */
+#define HTT_RX_FSE_IPSEC_VALID_M 0x00000001
+#define HTT_RX_FSE_IPSEC_VALID_S 0
+
+#define HTT_RX_FSE_IPSEC_VALID_SET(word, ipsec_valid) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_IPSEC_VALID, ipsec_valid); \
+ (word) |= ((ipsec_valid) << HTT_RX_FSE_IPSEC_VALID_S); \
+ } while (0)
+#define HTT_RX_FSE_IPSEC_VALID_GET(word) \
+ (((word) & HTT_RX_FSE_IPSEC_VALID_M) >> HTT_RX_FSE_IPSEC_VALID_S)
+
+/* DWORD 1:FSE Operation */
+#define HTT_RX_FSE_OPERATION_M 0x000000fe
+#define HTT_RX_FSE_OPERATION_S 1
+
+#define HTT_RX_FSE_OPERATION_SET(word, op_val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION, op_val); \
+ (word) |= ((op_val) << HTT_RX_FSE_OPERATION_S); \
+ } while (0)
+#define HTT_RX_FSE_OPERATION_GET(word) \
+ (((word) & HTT_RX_FSE_OPERATION_M) >> HTT_RX_FSE_OPERATION_S)
+
+/* DWORD 2-9:IP Address */
+#define HTT_RX_FSE_OPERATION_IP_ADDR_M 0xffffffff
+#define HTT_RX_FSE_OPERATION_IP_ADDR_S 0
+#define HTT_RX_FSE_OPERATION_IP_ADDR_GET(_var) \
+ (((_var) & HTT_RX_FSE_OPERATION_IP_ADDR_M) >> \
+ HTT_RX_FSE_OPERATION_IP_ADDR_S)
+#define HTT_RX_FSE_OPERATION_IP_ADDR_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_IP_ADDR, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_IP_ADDR_S)); \
+ } while (0)
+
+/* DWORD 10:Source Port Number */
+#define HTT_RX_FSE_SOURCEPORT_M 0x0000ffff
+#define HTT_RX_FSE_SOURCEPORT_S 0
+
+#define HTT_RX_FSE_SOURCEPORT_SET(word, sport) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_SOURCEPORT, sport); \
+ (word) |= ((sport) << HTT_RX_FSE_SOURCEPORT_S); \
+ } while (0)
+#define HTT_RX_FSE_SOURCEPORT_GET(word) \
+ (((word) & HTT_RX_FSE_SOURCEPORT_M) >> HTT_RX_FSE_SOURCEPORT_S)
+
+
+/* DWORD 11:Destination Port Number */
+#define HTT_RX_FSE_DESTPORT_M 0xffff0000
+#define HTT_RX_FSE_DESTPORT_S 16
+
+#define HTT_RX_FSE_DESTPORT_SET(word, dport) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_DESTPORT, dport); \
+ (word) |= ((dport) << HTT_RX_FSE_DESTPORT_S); \
+ } while (0)
+#define HTT_RX_FSE_DESTPORT_GET(word) \
+ (((word) & HTT_RX_FSE_DESTPORT_M) >> HTT_RX_FSE_DESTPORT_S)
+
+/* DWORD 10-11:SPI (In case of IPSEC) */
+#define HTT_RX_FSE_OPERATION_SPI_M 0xffffffff
+#define HTT_RX_FSE_OPERATION_SPI_S 0
+#define HTT_RX_FSE_OPERATION_SPI_GET(_var) \
+ (((_var) & HTT_RX_FSE_OPERATION_SPI_ADDR_M) >> \
+ HTT_RX_FSE_OPERATION_SPI_ADDR_S)
+#define HTT_RX_FSE_OPERATION_SPI_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_OPERATION_SPI, _val); \
+ ((_var) |= ((_val) << HTT_RX_FSE_OPERATION_SPI_S)); \
+ } while (0)
+
+/* DWORD 12:L4 PROTO */
+#define HTT_RX_FSE_L4_PROTO_M 0x000000ff
+#define HTT_RX_FSE_L4_PROTO_S 0
+
+#define HTT_RX_FSE_L4_PROTO_SET(word, proto_val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_FSE_L4_PROTO, proto_val); \
+ (word) |= ((proto_val) << HTT_RX_FSE_L4_PROTO_S); \
+ } while (0)
+#define HTT_RX_FSE_L4_PROTO_GET(word) \
+ (((word) & HTT_RX_FSE_L4_PROTO_M) >> HTT_RX_FSE_L4_PROTO_S)
+
+
/*=== target -> host messages ===============================================*/
@@ -5517,6 +6329,15 @@
HTT_T2H_MSG_TYPE_PEER_MAP_V2 = 0x1e,
HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 = 0x1f,
HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND = 0x20,
+ HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE = 0x21,
+ HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND = 0x22,
+ HTT_T2H_MSG_TYPE_PEER_STATS_IND = 0x23,
+ HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24,
+ /* TX_OFFLOAD_DELIVER_IND:
+ * Forward the target's locally-generated packets to the host,
+ * to provide to the monitor mode interface.
+ */
+ HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND = 0x25,
HTT_T2H_MSG_TYPE_TEST,
/* keep this last */
@@ -5662,7 +6483,22 @@
A_UINT32 /* word 1 */
vap_id: 8,
- reserved_1: 8,
+ /* NOTE:
+ * This reserved_1 field is not truly reserved - certain targets use
+ * this field internally to store debug information, and do not zero
+ * out the contents of the field before uploading the message to the
+ * host. Thus, any host-target communication supported by this field
+ * is limited to using values that are never used by the debug
+ * information stored by certain targets in the reserved_1 field.
+ * In particular, the targets in question don't use the value 0x3
+ * within bits 7:6 of this field (i.e. bits 15:14 of the A_UINT32),
+ * so this previously-unused value within these bits is available to
+ * use as the host / target PKT_CAPTURE_MODE flag.
+ */
+ reserved_1: 8, /* reserved_1a: 6, pkt_capture_mode: 2, */
+ /* if pkt_capture_mode == 0x3, host should
+ * send rx frames to monitor mode interface
+ */
msdu_cnt: 16;
};
@@ -5713,6 +6549,8 @@
#define HTT_RX_IN_ORD_PADDR_IND_PEER_ID_S 16
#define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M 0x000000ff
#define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S 0
+#define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M 0x0000c000
+#define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S 14
#define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_M 0xffff0000
#define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_S 16
/* for systems using 64-bit format for bus addresses */
@@ -5755,6 +6593,24 @@
#define HTT_RX_IN_ORD_PADDR_IND_VAP_ID_GET(word) \
(((word) & HTT_RX_IN_ORD_PADDR_IND_VAP_ID_M) >> HTT_RX_IN_ORD_PADDR_IND_VAP_ID_S)
+/*
+ * If the PKT_CAPTURE_MODE flags value is MONITOR (0x3), the host should
+ * deliver the rx frames to the monitor mode interface.
+ * The HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET macro
+ * sets the PKT_CAPTURE_MODE flags value to MONITOR, and the
+ * HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET macro
+ * checks whether the PKT_CAPTURE_MODE flags value is MONITOR.
+ */
+#define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR 0x3
+#define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR_SET(word) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE, HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR); \
+ (word) |= (value) << HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S; \
+ } while (0)
+#define HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET(word) \
+ ((((word) & HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_M) >> HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_S) == \
+ HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_MONITOR)
+
#define HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT_SET(word, value) \
do { \
HTT_CHECK_SET_VAL(HTT_RX_IN_ORD_PADDR_IND_MSDU_CNT, value); \
@@ -5935,9 +6791,17 @@
preamble_type: 8;
#define HTT_RX_IND_PPDU_OFFSET_WORD_VHT_SIG_A2 8
+ #define HTT_RX_IND_PPDU_OFFSET_WORD_SA_ANT_MATRIX 8
A_UINT32 /* word 8 */
vht_sig_a2: 24,
- reserved0: 8;
+ /* sa_ant_matrix
+ * For cases where a single rx chain has options to be connected to
+ * different rx antennas, show which rx antennas were in use during
+ * receipt of a given PPDU.
+ * This sa_ant_matrix provides a bitmask of the antennas used while
+ * receiving this frame.
+ */
+ sa_ant_matrix: 8;
} POSTPACK;
#define HTT_RX_PPDU_DESC_BYTES (sizeof(struct htt_rx_ppdu_desc_t))
@@ -6429,6 +7293,8 @@
#define HTT_RX_IND_PREAMBLE_TYPE_S 24
#define HTT_RX_IND_SERVICE_M 0xff000000
#define HTT_RX_IND_SERVICE_S 24
+#define HTT_RX_IND_SA_ANT_MATRIX_M 0xff000000
+#define HTT_RX_IND_SA_ANT_MATRIX_S 24
/* rx MSDU descriptor fields */
#define HTT_RX_IND_FW_RX_DESC_BYTES_M 0xffff
@@ -6673,6 +7539,14 @@
(((word) & HTT_RX_IND_SERVICE_M) >> \
HTT_RX_IND_SERVICE_S)
+#define HTT_RX_IND_SA_ANT_MATRIX_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_IND_SA_ANT_MATRIX, value); \
+ (word) |= (value) << HTT_RX_IND_SA_ANT_MATRIX_S; \
+ } while (0)
+#define HTT_RX_IND_SA_ANT_MATRIX_GET(word) \
+ (((word) & HTT_RX_IND_SA_ANT_MATRIX_M) >> \
+ HTT_RX_IND_SA_ANT_MATRIX_S)
#define HTT_RX_IND_MPDU_COUNT_SET(word, value) \
do { \
@@ -6693,7 +7567,7 @@
#define HTT_RX_IND_HL_BYTES \
(HTT_RX_IND_HDR_BYTES + \
- 4 /* single FW rx MSDU descriptor, plus padding */ + \
+ 4 /* single FW rx MSDU descriptor */ + \
4 /* single MPDU range information element */)
#define HTT_RX_IND_HL_SIZE32 (HTT_RX_IND_HL_BYTES >> 2)
@@ -6713,7 +7587,9 @@
/*
* HTT_RX_IND_HL_RX_DESC_BASE_OFFSET
* Currently, we use a resv field in hl_htt_rx_ind_base to store some
- * HL host needed info. The field is just after the msdu fw rx desc.
+ * HL host needed info; refer to fw_rx_desc_base in wal_rx_desc.h.
+ * The field is just after the MSDU FW rx desc, and 1 byte ahead of
+ * htt_rx_ind_hl_rx_desc_t.
*/
#define HTT_RX_IND_HL_RX_DESC_BASE_OFFSET (HTT_RX_IND_FW_RX_DESC_BYTE_OFFSET + 1)
struct htt_rx_ind_hl_rx_desc_t {
@@ -6730,6 +7606,7 @@
udp: 1,
reserved: 1;
} flags;
+ /* NOTE: no reserved space - don't append any new fields here */
};
#define HTT_RX_IND_HL_RX_DESC_VER_OFFSET \
@@ -6866,6 +7743,319 @@
#define HTT_CHAN_INFO_PHY_MODE_GET(word) \
(((word) & HTT_CHAN_INFO_PHY_MODE_M) >> HTT_CHAN_INFO_PHY_MODE_S)
+/*
+ * HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND
+ * @brief target -> host message definition for FW offloaded pkts
+ *
+ * @details
+ * The following field definitions describe the format of the firmware
+ * offload deliver message sent from the target to the host.
+ *
+ * definition for struct htt_tx_offload_deliver_ind_hdr_t
+ *
+ * |31 20|19 16|15 13|12 8|7 5|4|3|2 0|
+ * |----------------------------+--------+-----+---------------+-----+-+-+----|
+ * | reserved_1 | msg type |
+ * |--------------------------------------------------------------------------|
+ * | phy_timestamp_l32 |
+ * |--------------------------------------------------------------------------|
+ * | WORD2 (see below) |
+ * |--------------------------------------------------------------------------|
+ * | seqno | framectrl |
+ * |--------------------------------------------------------------------------|
+ * | reserved_3 | vdev_id | tid_num|
+ * |--------------------------------------------------------------------------|
+ * | reserved_4 | tx_mpdu_bytes |F|STAT|
+ * |--------------------------------------------------------------------------|
+ *
+ * where:
+ * STAT = status
+ * F = format (802.3 vs. 802.11)
+ *
+ * definition for word 2
+ *
+ * |31 26|25| 24 |23 | 22 |21 19|18 17|16 9|8 6|5 2|1 0|
+ * |--------+--+----+---+----+-----+-----+---------------------+----+-----+---|
+ * |reserv_2|BF|LDPC|SGI|STBC| BW | NSS | RSSI |RATE| MCS |PR |
+ * |--------------------------------------------------------------------------|
+ *
+ * where:
+ * PR = preamble
+ * BF = beamformed
+ */
+
+PREPACK struct htt_tx_offload_deliver_ind_hdr_t
+{
+ A_UINT32 /* word 0 */
+ msg_type:8, /* [ 7: 0] */
+ reserved_1:24; /* [31: 8] */
+ A_UINT32 phy_timestamp_l32; /* word 1 [31:0] */
+ A_UINT32 /* word 2 */
+ /* preamble:
+ * 0-OFDM,
+ * 1-CCk,
+ * 2-HT,
+ * 3-VHT
+ */
+ preamble: 2, /* [1:0] */
+ /* mcs:
+ * In case of HT preamble interpret
+ * MCS along with NSS.
+ * Valid values for HT are 0 to 7.
+ * HT mcs 0 with NSS 2 is mcs 8.
+ * Valid values for VHT are 0 to 9.
+ */
+ mcs: 4, /* [5:2] */
+ /* rate:
+ * This is applicable only for
+ * CCK and OFDM preamble type
+ * rate 0: OFDM 48 Mbps,
+ * 1: OFDM 24 Mbps,
+ * 2: OFDM 12 Mbps
+ * 3: OFDM 6 Mbps
+ * 4: OFDM 54 Mbps
+ * 5: OFDM 36 Mbps
+ * 6: OFDM 18 Mbps
+ * 7: OFDM 9 Mbps
+ * rate 0: CCK 11 Mbps Long
+ * 1: CCK 5.5 Mbps Long
+ * 2: CCK 2 Mbps Long
+ * 3: CCK 1 Mbps Long
+ * 4: CCK 11 Mbps Short
+ * 5: CCK 5.5 Mbps Short
+ * 6: CCK 2 Mbps Short
+ */
+ rate : 3, /* [ 8: 6] */
+ rssi : 8, /* [16: 9] units=dBm */
+ nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */
+ bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */
+ stbc : 1, /* [22] */
+ sgi : 1, /* [23] */
+ ldpc : 1, /* [24] */
+ beamformed: 1, /* [25] */
+ reserved_2: 6; /* [31:26] */
+ A_UINT32 /* word 3 */
+ framectrl:16, /* [15: 0] */
+ seqno:16; /* [31:16] */
+ A_UINT32 /* word 4 */
+ tid_num:5, /* [ 4: 0] actual TID number */
+ vdev_id:8, /* [12: 5] */
+ reserved_3:19; /* [31:13] */
+ A_UINT32 /* word 5 */
+ /* status:
+ * 0: tx_ok
+ * 1: retry
+ * 2: drop
+ * 3: filtered
+ * 4: abort
+ * 5: tid delete
+ * 6: sw abort
+ * 7: dropped by peer migration
+ */
+ status:3, /* [2:0] */
+ format:1, /* [3] 0: 802.3 format, 1: 802.11 format */
+ tx_mpdu_bytes:16, /* [19:4] */
+ reserved_4:12; /* [31:20] */
+} POSTPACK;
+
+/* FW offload deliver ind message header fields */
+
+/* DWORD one */
+#define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M 0xffffffff
+#define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S 0
+
+/* DWORD two */
+#define HTT_FW_OFFLOAD_IND_PREAMBLE_M 0x00000003
+#define HTT_FW_OFFLOAD_IND_PREAMBLE_S 0
+#define HTT_FW_OFFLOAD_IND_MCS_M 0x0000003c
+#define HTT_FW_OFFLOAD_IND_MCS_S 2
+#define HTT_FW_OFFLOAD_IND_RATE_M 0x000001c0
+#define HTT_FW_OFFLOAD_IND_RATE_S 6
+#define HTT_FW_OFFLOAD_IND_RSSI_M 0x0001fe00
+#define HTT_FW_OFFLOAD_IND_RSSI_S 9
+#define HTT_FW_OFFLOAD_IND_NSS_M 0x00060000
+#define HTT_FW_OFFLOAD_IND_NSS_S 17
+#define HTT_FW_OFFLOAD_IND_BW_M 0x00380000
+#define HTT_FW_OFFLOAD_IND_BW_S 19
+#define HTT_FW_OFFLOAD_IND_STBC_M 0x00400000
+#define HTT_FW_OFFLOAD_IND_STBC_S 22
+#define HTT_FW_OFFLOAD_IND_SGI_M 0x00800000
+#define HTT_FW_OFFLOAD_IND_SGI_S 23
+#define HTT_FW_OFFLOAD_IND_LDPC_M 0x01000000
+#define HTT_FW_OFFLOAD_IND_LDPC_S 24
+#define HTT_FW_OFFLOAD_IND_BEAMFORMED_M 0x02000000
+#define HTT_FW_OFFLOAD_IND_BEAMFORMED_S 25
+
+/* DWORD three*/
+#define HTT_FW_OFFLOAD_IND_FRAMECTRL_M 0x0000ffff
+#define HTT_FW_OFFLOAD_IND_FRAMECTRL_S 0
+#define HTT_FW_OFFLOAD_IND_SEQNO_M 0xffff0000
+#define HTT_FW_OFFLOAD_IND_SEQNO_S 16
+
+ /* DWORD four */
+#define HTT_FW_OFFLOAD_IND_TID_NUM_M 0x0000001f
+#define HTT_FW_OFFLOAD_IND_TID_NUM_S 0
+#define HTT_FW_OFFLOAD_IND_VDEV_ID_M 0x00001fe0
+#define HTT_FW_OFFLOAD_IND_VDEV_ID_S 5
+
+/* DWORD five */
+#define HTT_FW_OFFLOAD_IND_STATUS_M 0x00000007
+#define HTT_FW_OFFLOAD_IND_STATUS_S 0
+#define HTT_FW_OFFLOAD_IND_FORMAT_M 0x00000008
+#define HTT_FW_OFFLOAD_IND_FORMAT_S 3
+#define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M 0x000ffff0
+#define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S 4
+
+#define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_M) >> HTT_FW_OFFLOAD_IND_PHY_TIMESTAMP_L32_S)
+
+#define HTT_FW_OFFLOAD_IND_PREAMBLE_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_PREAMBLE, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_PREAMBLE_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_PREAMBLE_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_PREAMBLE_M) >> HTT_FW_OFFLOAD_IND_PREAMBLE_S)
+
+#define HTT_FW_OFFLOAD_IND_MCS_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_MCS, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_MCS_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_MCS_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_MCS_M) >> HTT_FW_OFFLOAD_IND_MCS_S)
+
+#define HTT_FW_OFFLOAD_IND_RATE_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RATE, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_RATE_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_RATE_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_RATE_M) >> HTT_FW_OFFLOAD_IND_RATE_S)
+
+#define HTT_FW_OFFLOAD_IND_RSSI_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_RSSI, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_RSSI_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_RSSI_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_RSSI_M) >> HTT_FW_OFFLOAD_IND_RSSI_S)
+
+
+#define HTT_FW_OFFLOAD_IND_NSS_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_NSS, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_NSS_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_NSS_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_NSS_M) >> HTT_FW_OFFLOAD_IND_NSS_S)
+
+#define HTT_FW_OFFLOAD_IND_BW_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BW, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_BW_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_BW_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_BW_M) >> HTT_FW_OFFLOAD_IND_BW_S)
+
+
+#define HTT_FW_OFFLOAD_IND_STBC_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STBC, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_STBC_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_STBC_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_STBC_M) >> HTT_FW_OFFLOAD_IND_STBC_S)
+
+
+#define HTT_FW_OFFLOAD_IND_SGI_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SGI, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_SGI_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_SGI_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_SGI_M) >> HTT_FW_OFFLOAD_IND_SGI_S)
+
+#define HTT_FW_OFFLOAD_IND_LDPC_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_LDPC, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_LDPC_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_LDPC_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_LDPC_M) >> HTT_FW_OFFLOAD_IND_LDPC_S)
+
+#define HTT_FW_OFFLOAD_IND_BEAMFORMED_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_BEAMFORMED, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_BEAMFORMED_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_BEAMFORMED_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_BEAMFORMED_M) >> HTT_FW_OFFLOAD_IND_BEAMFORMED_S)
+
+#define HTT_FW_OFFLOAD_IND_FRAMECTRL_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FRAMECTRL, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_FRAMECTRL_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_FRAMECTRL_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_FRAMECTRL_M) >> HTT_FW_OFFLOAD_IND_FRAMECTRL_S)
+
+
+#define HTT_FW_OFFLOAD_IND_SEQNO_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_SEQNO, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_SEQNO_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_SEQNO_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_SEQNO_M) >> HTT_FW_OFFLOAD_IND_SEQNO_S)
+
+#define HTT_FW_OFFLOAD_IND_TID_NUM_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TID_NUM, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_TID_NUM_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_TID_NUM_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_TID_NUM_M) >> HTT_FW_OFFLOAD_IND_TID_NUM_S)
+
+#define HTT_FW_OFFLOAD_IND_VDEV_ID_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_VDEV_ID, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_VDEV_ID_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_VDEV_ID_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_VDEV_ID_M) >> HTT_FW_OFFLOAD_IND_VDEV_ID_S)
+
+#define HTT_FW_OFFLOAD_IND_STATUS_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_STATUS, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_STATUS_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_STATUS_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_STATUS_M) >> HTT_FW_OFFLOAD_IND_STATUS_M)
+
+
+#define HTT_FW_OFFLOAD_IND_FORMAT_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_FORMAT, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_FORMAT_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_FORMAT_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_FORMAT_M) >> HTT_FW_OFFLOAD_IND_FORMAT_S)
+
+
+#define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES, value); \
+ (word) |= (value) << HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S; \
+ } while (0)
+#define HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_GET(word) \
+ (((word) & HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_M) >> HTT_FW_OFFLOAD_IND_TX_MPDU_BYTES_S)
+
/*
* @brief target -> host rx reorder flush message definition
@@ -7247,7 +8437,8 @@
* to identify which peer the frame needs to be forwarded to (i.e. the
* peer assocated with the Destination MAC Address within the packet),
* and particularly which vdev needs to transmit the frame (for cases
- * of inter-vdev rx --> tx forwarding).
+ * of inter-vdev rx --> tx forwarding). The HW peer id here is the same
+ * meaning as AST_INDEX_0.
* This DA-based peer ID that is provided for certain rx frames
* (the rx frames that need to be re-transmitted as tx frames)
* is the ID that the HW uses for referring to the peer in question,
@@ -7260,7 +8451,7 @@
* |-----------------------------------------------------------------------|
* | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
* |-----------------------------------------------------------------------|
- * | HW peer ID | MAC addr 5 | MAC addr 4 |
+ * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 |
* |-----------------------------------------------------------------------|
*
*
@@ -7390,26 +8581,34 @@
* is the ID that the HW uses for referring to the peer in question,
* rather than the peer ID that the SW+FW use to refer to the peer.
*
+ * The HW peer id here is the same meaning as AST_INDEX_0.
+ * Some chips support up to 4 AST indices per peer: AST_INDEX_0, AST_INDEX_1,
+ * AST_INDEX_2, and AST_INDEX_3. AST 0 is always valid; for AST 1 through
+ * AST 3, check the AST_VALID_MASK(3) to see if the corresponding extension
+ * AST is valid.
*
- * |31 24|23 16|15 8|7 0|
+ * |31 28|27 24|23 20|19 17|16|15 8|7 0|
* |-----------------------------------------------------------------------|
* | SW peer ID | VDEV ID | msg type |
* |-----------------------------------------------------------------------|
* | MAC addr 3 | MAC addr 2 | MAC addr 1 | MAC addr 0 |
* |-----------------------------------------------------------------------|
- * | HW peer ID | MAC addr 5 | MAC addr 4 |
+ * | HW peer ID / AST index 0 | MAC addr 5 | MAC addr 4 |
* |-----------------------------------------------------------------------|
- * | Reserved_17_31 | Next Hop | AST Hash Value |
+ * | Reserved_20_31 |ASTVM|NH| AST Hash Value |
* |-----------------------------------------------------------------------|
- * | Reserved_0 |
+ * | ASTFM3 | ASTFM2 | ASTFM1 | ASTFM0 | AST index 1 |
* |-----------------------------------------------------------------------|
- * | Reserved_1 |
+ * |TID valid low pri| TID valid hi pri| AST index 2 |
+ * |-----------------------------------------------------------------------|
+ * | Reserved_1 | AST index 3 |
* |-----------------------------------------------------------------------|
* | Reserved_2 |
* |-----------------------------------------------------------------------|
- * | Reserved_3 |
- * |-----------------------------------------------------------------------|
- *
+ * Where:
+ * NH = Next Hop
+ * ASTVM = AST valid mask
+ * ASTFM = AST flow mask
*
* The following field definitions describe the format of the rx peer map v2
* messages sent from the target to the host.
@@ -7433,7 +8632,7 @@
* Bits 15:0
* Purpose: Identifies which peer node the peer ID is for.
* Value: upper 2 bytes of peer node's MAC address
- * - HW_PEER_ID
+ * - HW_PEER_ID / AST_INDEX_0
* Bits 31:16
* Purpose: Identifies the HW peer ID corresponding to the peer MAC
* address, so for rx frames marked for rx --> tx forwarding, the
@@ -7448,6 +8647,36 @@
* Bit 16
* Purpose: Bit indicates that a next_hop AST entry is used for WDS
* (Wireless Distribution System).
+ * - AST_VALID_MASK
+ * Bits 19:17
+ * Purpose: Indicate if the AST 1 through AST 3 are valid
+ * - AST_INDEX_1
+ * Bits 15:0
+ * Purpose: indicate the second AST index for this peer
+ * - AST_0_FLOW_MASK
+ * Bits 19:16
+ * Purpose: identify the which flow the AST 0 entry corresponds to.
+ * - AST_1_FLOW_MASK
+ * Bits 23:20
+ * Purpose: identify the which flow the AST 1 entry corresponds to.
+ * - AST_2_FLOW_MASK
+ * Bits 27:24
+ * Purpose: identify the which flow the AST 2 entry corresponds to.
+ * - AST_3_FLOW_MASK
+ * Bits 31:28
+ * Purpose: identify the which flow the AST 3 entry corresponds to.
+ * - AST_INDEX_2
+ * Bits 15:0
+ * Purpose: indicate the third AST index for this peer
+ * - TID_VALID_HI_PRI
+ * Bits 23:16
+ * Purpose: identify if this peer's TIDs 0-7 support HI priority flow
+ * - TID_VALID_LOW_PRI
+ * Bits 31:24
+ * Purpose: identify if this peer's TIDs 0-7 support Low priority flow
+ * - AST_INDEX_3
+ * Bits 15:0
+ * Purpose: indicate the fourth AST index for this peer
*/
#define HTT_RX_PEER_MAP_V2_VDEV_ID_M 0xff00
#define HTT_RX_PEER_MAP_V2_VDEV_ID_S 8
@@ -7463,6 +8692,29 @@
#define HTT_RX_PEER_MAP_V2_AST_HASH_VALUE_S 0
#define HTT_RX_PEER_MAP_V2_NEXT_HOP_M 0x00010000
#define HTT_RX_PEER_MAP_V2_NEXT_HOP_S 16
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M 0x000e0000
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S 17
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_M 0xffff
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_S 0
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M 0x000f0000
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S 16
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M 0x00f00000
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S 20
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M 0x0f000000
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S 24
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M 0xf0000000
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S 28
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_M 0xffff
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_S 0
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M 0x00ff0000
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S 16
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M 0xff000000
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S 24
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_M 0xffff
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_S 0
#define HTT_RX_PEER_MAP_V2_VDEV_ID_SET(word, value) \
do { \
@@ -7504,10 +8756,97 @@
#define HTT_RX_PEER_MAP_V2_NEXT_HOP_GET(word) \
(((word) & HTT_RX_PEER_MAP_V2_NEXT_HOP_M) >> HTT_RX_PEER_MAP_V2_NEXT_HOP_S)
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_VALID_MASK, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_AST_VALID_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_VALID_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_1, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_1_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_1_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_1_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_0_FLOW_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_1_FLOW_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_2_FLOW_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_M) >> HTT_RX_PEER_MAP_V2_AST_3_FLOW_MASK_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_2, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_2_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_2_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_2_S)
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_S)
+
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_M) >> HTT_RX_PEER_MAP_V2_TID_VALID_LOW_PRI_S)
+
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PEER_MAP_V2_AST_INDEX_3, value); \
+ (word) |= (value) << HTT_RX_PEER_MAP_V2_AST_INDEX_3_S; \
+ } while (0)
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_GET(word) \
+ (((word) & HTT_RX_PEER_MAP_V2_AST_INDEX_3_M) >> HTT_RX_PEER_MAP_V2_AST_INDEX_3_S)
+
+
#define HTT_RX_PEER_MAP_V2_MAC_ADDR_OFFSET 4 /* bytes */
#define HTT_RX_PEER_MAP_V2_HW_PEER_ID_OFFSET 8 /* bytes */
#define HTT_RX_PEER_MAP_V2_AST_HASH_INDEX_OFFSET 12 /* bytes */
#define HTT_RX_PEER_MAP_V2_NEXT_HOP_OFFSET 12 /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_VALID_MASK_OFFSET 12 /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_1_OFFSET 16 /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_X_FLOW_MASK_OFFSET 16 /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_2_OFFSET 20 /* bytes */
+#define HTT_RX_PEER_MAP_V2_TID_VALID_LO_PRI_OFFSET 20 /* bytes */
+#define HTT_RX_PEER_MAP_V2_TID_VALID_HI_PRI_OFFSET 20 /* bytes */
+#define HTT_RX_PEER_MAP_V2_AST_INDEX_3_OFFSET 24 /* bytes */
#define HTT_RX_PEER_MAP_V2_BYTES 32
@@ -7730,9 +9069,9 @@
* The following diagram shows the format of the rx DELBA message sent
* from the target to the host:
*
- * |31 20|19 16|15 8|7 0|
+ * |31 20|19 16|15 10|9 8|7 0|
* |---------------------------------------------------------------------|
- * | peer ID | TID | reserved | msg type |
+ * | peer ID | TID | reserved | IR| msg type |
* |---------------------------------------------------------------------|
*
* The following field definitions describe the format of the rx ADDBA
@@ -7741,6 +9080,15 @@
* Bits 7:0
* Purpose: identifies this as an rx ADDBA or DELBA message
* Value: ADDBA -> 0x5, DELBA -> 0x6
+ * - IR (initiator / recipient)
+ * Bits 9:8 (DELBA only)
+ * Purpose: specify whether the DELBA handshake was initiated by the
+ * local STA/AP, or by the peer STA/AP
+ * Value:
+ * 0 - unspecified
+ * 1 - initiator (a.k.a. originator)
+ * 2 - recipient (a.k.a. responder)
+ * 3 - unused / reserved
* - WIN_SIZE
* Bits 15:8 (ADDBA only)
* Purpose: Specifies the length of the block ack window (max = 64).
@@ -7793,6 +9141,8 @@
#define HTT_RX_ADDBA_BYTES 4
+#define HTT_RX_DELBA_INITIATOR_M 0x00000300
+#define HTT_RX_DELBA_INITIATOR_S 8
#define HTT_RX_DELBA_TID_M HTT_RX_ADDBA_TID_M
#define HTT_RX_DELBA_TID_S HTT_RX_ADDBA_TID_S
#define HTT_RX_DELBA_PEER_ID_M HTT_RX_ADDBA_PEER_ID_M
@@ -7803,6 +9153,14 @@
#define HTT_RX_DELBA_PEER_ID_SET HTT_RX_ADDBA_PEER_ID_SET
#define HTT_RX_DELBA_PEER_ID_GET HTT_RX_ADDBA_PEER_ID_GET
+#define HTT_RX_DELBA_INITIATOR_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_DELBA_INITIATOR, value); \
+ (word) |= (value) << HTT_RX_DELBA_INITIATOR_S; \
+ } while (0)
+#define HTT_RX_DELBA_INITIATOR_GET(word) \
+ (((word) & HTT_RX_DELBA_INITIATOR_M) >> HTT_RX_DELBA_INITIATOR_S)
+
#define HTT_RX_DELBA_BYTES 4
/**
@@ -7965,22 +9323,43 @@
* The following diagram shows the format of the TX completion indication sent
* from the target to the host
*
- * |31 27|26|25|24|23 16| 15 |14 11|10 8|7 0|
- * |------------------------------------------------------------|
- * header: | rsvd |TP|A1|A0| num | t_i| tid |status| msg_type |
- * |------------------------------------------------------------|
- * payload: | MSDU1 ID | MSDU0 ID |
- * |------------------------------------------------------------|
- * : MSDU3 ID : MSDU2 ID :
- * |------------------------------------------------------------|
- * | struct htt_tx_compl_ind_append_retries |
- * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
- * | struct htt_tx_compl_ind_append_tx_tstamp |
- * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
+ * |31 30|29|28|27|26|25|24|23 16| 15 |14 11|10 8|7 0|
+ * |-------------------------------------------------------------------|
+ * header: |rsvd |A4|A3|A2|TP|A1|A0| num | t_i| tid |status| msg_type |
+ * |-------------------------------------------------------------------|
+ * payload:| MSDU1 ID | MSDU0 ID |
+ * |-------------------------------------------------------------------|
+ * : MSDU3 ID | MSDU2 ID :
+ * |-------------------------------------------------------------------|
+ * | struct htt_tx_compl_ind_append_retries |
+ * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
+ * | struct htt_tx_compl_ind_append_tx_tstamp |
+ * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
+ * | MSDU1 ACK RSSI | MSDU0 ACK RSSI |
+ * |-------------------------------------------------------------------|
+ * : MSDU3 ACK RSSI | MSDU2 ACK RSSI :
+ * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
+ * | MSDU0 tx_tsf64_low |
+ * |-------------------------------------------------------------------|
+ * | MSDU0 tx_tsf64_high |
+ * |-------------------------------------------------------------------|
+ * | MSDU1 tx_tsf64_low |
+ * |-------------------------------------------------------------------|
+ * | MSDU1 tx_tsf64_high |
+ * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
+ * | phy_timestamp |
+ * |-------------------------------------------------------------------|
+ * | rate specs (see below) |
+ * |-------------------------------------------------------------------|
+ * | seqctrl | framectrl |
+ * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
* Where:
* A0 = append (a.k.a. append0)
* A1 = append1
* TP = MSDU tx power presence
+ * A2 = append2
+ * A3 = append3
+ * A4 = append4
*
* The following field definitions describe the format of the TX completion
* indication sent from the target to the host
@@ -8034,6 +9413,41 @@
* which MSDU ID.
* Value: 0 indicates MSDU tx power reports are not appended,
* 1 indicates MSDU tx power reports are appended
+ * - append2
+ * Bits 27:27
+ * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in
+ * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report
+ * matches the order of the MSDU IDs. Although the ACK RSSI is the
+ * same for all MSDUs witin a single PPDU, the RSSI is duplicated
+ * for each MSDU, for convenience.
+ * The ACK RSSI values are valid when status is COMPLETE_OK (and
+ * this append2 bit is set).
+ * The ACK RSSI values are SNR in dB, i.e. are the RSSI in units of
+ * dB above the noise floor.
+ * Value: 0 indicates MSDU ACK RSSI values are not appended,
+ * 1 indicates MSDU ACK RSSI values are appended.
+ * - append3
+ * Bits 28:28
+ * Purpose: Append the struct htt_tx_compl_ind_append_tx_tsf64 which
+ * contains the tx tsf info based on wlan global TSF for
+ * each TX msdu id in payload.
+ * The order of the tx tsf matches the order of the MSDU IDs.
+ * The struct htt_tx_compl_ind_append_tx_tsf64 contains two 32-bits
+ * values to indicate the the lower 32 bits and higher 32 bits of
+ * the tx tsf.
+ * The tx_tsf64 here represents the time MSDU was acked and the
+ * tx_tsf64 has microseconds units.
+ * Value: 0 indicates no appending; 1 indicates appending
+ * - append4
+ * Bits 29:29
+ * Purpose: Indicate whether data frame control fields and fields required
+ * for radio tap header are appended for each MSDU in TX_COMP_IND
+ * message. The order of the this message matches the order of
+ * the MSDU IDs.
+ * Value: 0 indicates frame control fields and fields required for
+ * radio tap header values are not appended,
+ * 1 indicates frame control fields and fields required for
+ * radio tap header values are appended.
* Payload fields:
* - hmsdu_id
* Bits 15:0
@@ -8041,6 +9455,58 @@
* Value: 0 to "size of host MSDU descriptor pool - 1"
*/
+PREPACK struct htt_tx_data_hdr_information {
+ A_UINT32 phy_timestamp_l32; /* word 0 [31:0] */
+ A_UINT32 /* word 1 */
+ /* preamble:
+ * 0-OFDM,
+ * 1-CCk,
+ * 2-HT,
+ * 3-VHT
+ */
+ preamble: 2, /* [1:0] */
+ /* mcs:
+ * In case of HT preamble interpret
+ * MCS along with NSS.
+ * Valid values for HT are 0 to 7.
+ * HT mcs 0 with NSS 2 is mcs 8.
+ * Valid values for VHT are 0 to 9.
+ */
+ mcs: 4, /* [5:2] */
+ /* rate:
+ * This is applicable only for
+ * CCK and OFDM preamble type
+ * rate 0: OFDM 48 Mbps,
+ * 1: OFDM 24 Mbps,
+ * 2: OFDM 12 Mbps
+ * 3: OFDM 6 Mbps
+ * 4: OFDM 54 Mbps
+ * 5: OFDM 36 Mbps
+ * 6: OFDM 18 Mbps
+ * 7: OFDM 9 Mbps
+ * rate 0: CCK 11 Mbps Long
+ * 1: CCK 5.5 Mbps Long
+ * 2: CCK 2 Mbps Long
+ * 3: CCK 1 Mbps Long
+ * 4: CCK 11 Mbps Short
+ * 5: CCK 5.5 Mbps Short
+ * 6: CCK 2 Mbps Short
+ */
+ rate : 3, /* [ 8: 6] */
+ rssi : 8, /* [16: 9] units=dBm */
+ nss : 2, /* [18:17] if nss 1 means 1ss and 2 means 2ss */
+ bw : 3, /* [21:19] (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) */
+ stbc : 1, /* [22] */
+ sgi : 1, /* [23] */
+ ldpc : 1, /* [24] */
+ beamformed: 1, /* [25] */
+ reserved_1: 6; /* [31:26] */
+ A_UINT32 /* word 2 */
+ framectrl:16, /* [15: 0] */
+ seqno:16; /* [31:16] */
+} POSTPACK;
+
+
#define HTT_TX_COMPL_IND_STATUS_S 8
#define HTT_TX_COMPL_IND_STATUS_M 0x00000700
#define HTT_TX_COMPL_IND_TID_S 11
@@ -8055,6 +9521,12 @@
#define HTT_TX_COMPL_IND_APPEND1_M 0x02000000
#define HTT_TX_COMPL_IND_TX_POWER_S 26
#define HTT_TX_COMPL_IND_TX_POWER_M 0x04000000
+#define HTT_TX_COMPL_IND_APPEND2_S 27
+#define HTT_TX_COMPL_IND_APPEND2_M 0x08000000
+#define HTT_TX_COMPL_IND_APPEND3_S 28
+#define HTT_TX_COMPL_IND_APPEND3_M 0x10000000
+#define HTT_TX_COMPL_IND_APPEND4_S 29
+#define HTT_TX_COMPL_IND_APPEND4_M 0x20000000
#define HTT_TX_COMPL_IND_STATUS_SET(_info, _val) \
do { \
@@ -8106,6 +9578,28 @@
} while (0)
#define HTT_TX_COMPL_IND_TX_POWER_GET(_info) \
(((_info) & HTT_TX_COMPL_IND_TX_POWER_M) >> HTT_TX_COMPL_IND_TX_POWER_S)
+#define HTT_TX_COMPL_IND_APPEND2_SET(_info, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND2, _val); \
+ ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND2_S)); \
+ } while (0)
+#define HTT_TX_COMPL_IND_APPEND2_GET(_info) \
+ (((_info) & HTT_TX_COMPL_IND_APPEND2_M) >> HTT_TX_COMPL_IND_APPEND2_S)
+#define HTT_TX_COMPL_IND_APPEND3_SET(_info, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND3, _val); \
+ ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND3_S)); \
+ } while (0)
+#define HTT_TX_COMPL_IND_APPEND3_GET(_info) \
+ (((_info) & HTT_TX_COMPL_IND_APPEND3_M) >> HTT_TX_COMPL_IND_APPEND3_S)
+#define HTT_TX_COMPL_IND_APPEND4_SET(_info, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_COMPL_IND_APPEND4, _val); \
+ ((_info) |= ((_val) << HTT_TX_COMPL_IND_APPEND4_S)); \
+ } while (0)
+#define HTT_TX_COMPL_IND_APPEND4_GET(_info) \
+ (((_info) & HTT_TX_COMPL_IND_APPEND4_M) >> HTT_TX_COMPL_IND_APPEND4_S)
+
#define HTT_TX_COMPL_INV_TX_POWER 0xffff
#define HTT_TX_COMPL_CTXT_SZ sizeof(A_UINT16)
@@ -8164,6 +9658,155 @@
A_UINT32 timestamp[1/*or more*/];
} POSTPACK;
+PREPACK struct htt_tx_compl_ind_append_tx_tsf64 {
+ A_UINT32 tx_tsf64_low;
+ A_UINT32 tx_tsf64_high;
+} POSTPACK;
+
+/* htt_tx_data_hdr_information payload extension fields: */
+
+/* DWORD zero */
+#define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M 0xffffffff
+#define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S 0
+
+/* DWORD one */
+#define HTT_FW_TX_DATA_HDR_PREAMBLE_M 0x00000003
+#define HTT_FW_TX_DATA_HDR_PREAMBLE_S 0
+#define HTT_FW_TX_DATA_HDR_MCS_M 0x0000003c
+#define HTT_FW_TX_DATA_HDR_MCS_S 2
+#define HTT_FW_TX_DATA_HDR_RATE_M 0x000001c0
+#define HTT_FW_TX_DATA_HDR_RATE_S 6
+#define HTT_FW_TX_DATA_HDR_RSSI_M 0x0001fe00
+#define HTT_FW_TX_DATA_HDR_RSSI_S 9
+#define HTT_FW_TX_DATA_HDR_NSS_M 0x00060000
+#define HTT_FW_TX_DATA_HDR_NSS_S 17
+#define HTT_FW_TX_DATA_HDR_BW_M 0x00380000
+#define HTT_FW_TX_DATA_HDR_BW_S 19
+#define HTT_FW_TX_DATA_HDR_STBC_M 0x00400000
+#define HTT_FW_TX_DATA_HDR_STBC_S 22
+#define HTT_FW_TX_DATA_HDR_SGI_M 0x00800000
+#define HTT_FW_TX_DATA_HDR_SGI_S 23
+#define HTT_FW_TX_DATA_HDR_LDPC_M 0x01000000
+#define HTT_FW_TX_DATA_HDR_LDPC_S 24
+#define HTT_FW_TX_DATA_HDR_BEAMFORMED_M 0x02000000
+#define HTT_FW_TX_DATA_HDR_BEAMFORMED_S 25
+
+/* DWORD two */
+#define HTT_FW_TX_DATA_HDR_FRAMECTRL_M 0x0000ffff
+#define HTT_FW_TX_DATA_HDR_FRAMECTRL_S 0
+#define HTT_FW_TX_DATA_HDR_SEQNO_M 0xffff0000
+#define HTT_FW_TX_DATA_HDR_SEQNO_S 16
+
+
+#define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_M) >> HTT_FW_TX_DATA_HDR_PHY_TIMESTAMP_L32_S)
+
+#define HTT_FW_TX_DATA_HDR_PREAMBLE_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_PREAMBLE, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_PREAMBLE_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_PREAMBLE_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_PREAMBLE_M) >> HTT_FW_TX_DATA_HDR_PREAMBLE_S)
+
+#define HTT_FW_TX_DATA_HDR_MCS_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_MCS, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_MCS_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_MCS_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_MCS_M) >> HTT_FW_TX_DATA_HDR_MCS_S)
+
+#define HTT_FW_TX_DATA_HDR_RATE_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RATE, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_RATE_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_RATE_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_RATE_M) >> HTT_FW_TX_DATA_HDR_RATE_S)
+
+#define HTT_FW_TX_DATA_HDR_RSSI_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_RSSI, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_RSSI_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_RSSI_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_RSSI_M) >> HTT_FW_TX_DATA_HDR_RSSI_S)
+
+
+#define HTT_FW_TX_DATA_HDR_NSS_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_NSS, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_NSS_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_NSS_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_NSS_M) >> HTT_FW_TX_DATA_HDR_NSS_S)
+
+#define HTT_FW_TX_DATA_HDR_BW_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BW, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_BW_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_BW_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_BW_M) >> HTT_FW_TX_DATA_HDR_BW_S)
+
+
+#define HTT_FW_TX_DATA_HDR_STBC_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_STBC, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_STBC_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_STBC_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_STBC_M) >> HTT_FW_TX_DATA_HDR_STBC_S)
+
+
+#define HTT_FW_TX_DATA_HDR_SGI_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SGI, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_SGI_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_SGI_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_SGI_M) >> HTT_FW_TX_DATA_HDR_SGI_S)
+
+#define HTT_FW_TX_DATA_HDR_LDPC_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_LDPC, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_LDPC_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_LDPC_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_LDPC_M) >> HTT_FW_TX_DATA_HDR_LDPC_S)
+
+#define HTT_FW_TX_DATA_HDR_BEAMFORMED_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_BEAMFORMED, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_BEAMFORMED_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_BEAMFORMED_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_BEAMFORMED_M) >> HTT_FW_TX_DATA_HDR_BEAMFORMED_S)
+
+#define HTT_FW_TX_DATA_HDR_FRAMECTRL_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_FRAMECTRL, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_FRAMECTRL_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_FRAMECTRL_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_FRAMECTRL_M) >> HTT_FW_TX_DATA_HDR_FRAMECTRL_S)
+
+
+#define HTT_FW_TX_DATA_HDR_SEQNO_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FW_TX_DATA_HDR_SEQNO, value); \
+ (word) |= (value) << HTT_FW_TX_DATA_HDR_SEQNO_S; \
+ } while (0)
+#define HTT_FW_TX_DATA_HDR_SEQNO_GET(word) \
+ (((word) & HTT_FW_TX_DATA_HDR_SEQNO_M) >> HTT_FW_TX_DATA_HDR_SEQNO_S)
+
+
/**
* @brief target -> host rate-control update indication message
*
@@ -10198,6 +11841,27 @@
(((word) & HTT_T2H_PPDU_STATS_PPDU_ID_M) >> \
HTT_T2H_PPDU_STATS_PPDU_ID_S)
+/* htt_t2h_ppdu_stats_ind_hdr_t
+ * This struct contains the fields within the header of the
+ * HTT_T2H_PPDU_STATS_IND message, preceding the type-specific
+ * stats info.
+ * This struct assumes little-endian layout, and thus is only
+ * suitable for use within processors known to be little-endian
+ * (such as the target).
+ * In contrast, the above macros provide endian-portable methods
+ * to get and set the bitfields within this PPDU_STATS_IND header.
+ */
+typedef struct {
+ A_UINT32 msg_type: 8, /* bits 7:0 */
+ mac_id: 2, /* bits 9:8 */
+ pdev_id: 2, /* bits 11:10 */
+ reserved1: 4, /* bits 15:12 */
+ payload_size: 16; /* bits 31:16 */
+ A_UINT32 ppdu_id;
+ A_UINT32 timestamp_us;
+ A_UINT32 reserved2;
+} htt_t2h_ppdu_stats_ind_hdr_t;
+
/**
* @brief target -> host extended statistics upload
*
@@ -10427,5 +12091,1105 @@
(((word) & HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_M) >> \
HTT_T2H_MONITOR_MAC_HEADER_NUM_MPDU_S)
+/**
+ * @brief HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE Message
+ *
+ * @details
+ * HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE message is sent by the target when
+ * the flow pool associated with the specified ID is resized
+ *
+ * The message would appear as follows:
+ *
+ * |31 16|15 8|7 0|
+ * |---------------------------------+----------------+----------------|
+ * | reserved0 | Msg type |
+ * |-------------------------------------------------------------------|
+ * | flow pool new size | flow pool ID |
+ * |-------------------------------------------------------------------|
+ *
+ * The message is interpreted as follows:
+ * b'0:7 - msg_type: This will be set to
+ * HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE
+ *
+ * b'0:15 - flow pool ID: Existing flow pool ID
+ *
+ * b'16:31 - flow pool new size: new pool size for exisiting flow pool ID
+ *
+ */
+
+PREPACK struct htt_flow_pool_resize_t {
+ A_UINT32 msg_type:8,
+ reserved0:24;
+ A_UINT32 flow_pool_id:16,
+ flow_pool_new_size:16;
+} POSTPACK;
+
+#define HTT_FLOW_POOL_RESIZE_SZ (sizeof(struct htt_flow_pool_resize_t))
+
+#define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M 0x0000ffff
+#define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S 0
+
+#define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M 0xffff0000
+#define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S 16
+
+
+#define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_GET(_var) \
+ (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_M) >> \
+ HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S)
+
+#define HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID, _val); \
+ ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_ID_S)); \
+ } while (0)
+
+
+#define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_GET(_var) \
+ (((_var) & HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_M) >> \
+ HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S)
+
+#define HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE, _val); \
+ ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S)); \
+ } while (0)
+
+/**
+ * @brief host -> target channel change message
+ *
+ * @details
+ * the meesage is generated by FW every time FW changes channel. This will be used by host mainly
+ * to associate RX frames to correct channel they were received on.
+ * The following field definitions describe the format of the HTT target
+ * to host channel change message.
+ * |31 16|15 8|7 5|4 0|
+ * |------------------------------------------------------------|
+ * | reserved | MSG_TYPE |
+ * |------------------------------------------------------------|
+ * | CHAN_MHZ |
+ * |------------------------------------------------------------|
+ * | BAND_CENTER_FREQ1 |
+ * |------------------------------------------------------------|
+ * | BAND_CENTER_FREQ2 |
+ * |------------------------------------------------------------|
+ * | CHAN_PHY_MODE |
+ * |------------------------------------------------------------|
+ * Header fields:
+ * - MSG_TYPE
+ * Bits 7:0
+ * Value: 0xf
+ * - CHAN_MHZ
+ * Bits 31:0
+ * Purpose: frequency of the primary 20mhz channel.
+ * - BAND_CENTER_FREQ1
+ * Bits 31:0
+ * Purpose: centre frequency of the full channel.
+ * - BAND_CENTER_FREQ2
+ * Bits 31:0
+ * Purpose: centre frequency2 of the channel. is only valid for 11acvht 80plus80.
+ * - CHAN_PHY_MODE
+ * Bits 31:0
+ * Purpose: phy mode of the channel.
+*/
+
+PREPACK struct htt_chan_change_msg {
+ A_UINT32 chan_mhz; /* frequency in mhz */
+
+ A_UINT32 band_center_freq1; /* Center frequency 1 in MHz*/
+
+ A_UINT32 band_center_freq2; /* Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/
+
+ A_UINT32 chan_mode; /* WLAN_PHY_MODE of the channel defined in wlan_defs.h */
+} POSTPACK;
+
+#define HTT_CFR_CAPTURE_MAGIC_PATTERN 0xCCCCCCCC
+#define HTT_CFR_CAPTURE_READ_INDEX_OFFSET 0 /* bytes */
+#define HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES 4
+#define HTT_CFR_CAPTURE_WRITE_INDEX_OFFSET /* bytes */ \
+ (HTT_CFR_CAPTURE_READ_INDEX_OFFSET + HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES)
+#define HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES 4
+#define HTT_CFR_CAPTURE_SIZEOF_MAGIC_PATTERN_BYTES 4
+/*
+ * The read and write indices point to the data within the host buffer.
+ * Because the first 4 bytes of the host buffer is used for the read index and
+ * the next 4 bytes for the write index, the data itself starts at offset 8.
+ * The read index and write index are the byte offsets from the base of the
+ * meta-data buffer, and thus have a minimum value of 8 rather than 0.
+ * Refer the ASCII text picture below.
+ */
+#define HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX \
+ (HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES + \
+ HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES)
+
+/*
+ ***************************************************************************
+ *
+ * Layout when CFR capture message type is 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1'
+ *
+ ***************************************************************************
+ *
+ * The memory allocated by WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID is used
+ * in the below format. The HTT message 'htt_cfr_dump_compl_ind' is sent by
+ * FW to Host whenever a CFR capture (CFR data1 or CFR data2 etc.,) is
+ * written into the Host memory region mentioned below.
+ *
+ * Read index is updated by the Host. At any point of time, the read index will
+ * indicate the index that will next be read by the Host. The read index is
+ * in units of bytes offset from the base of the meta-data buffer.
+ *
+ * Write index is updated by the FW. At any point of time, the write index will
+ * indicate from where the FW can start writing any new data. The write index is
+ * in units of bytes offset from the base of the meta-data buffer.
+ *
+ * If the Host is not fast enough in reading the CFR data, any new capture data
+ * would be dropped if there is no space left to write the new captures.
+ *
+ * The last 4 bytes of the memory region will have the magic pattern
+ * HTT_CFR_CAPTURE_MAGIC_PATTERN. This can be used to ensure that the FW does
+ * not overrun the host buffer.
+ *
+ * ,--------------------. read and write indices store the
+ * | | byte offset from the base of the
+ * | ,--------+--------. meta-data buffer to the next
+ * | | | | location within the data buffer
+ * | | v v that will be read / written
+ * ************************************************************************
+ * * Read * Write * * Magic *
+ * * index * index * CFR data1 ...... CFR data N * pattern *
+ * * (4 bytes) * (4 bytes) * * (4 bytes)*
+ * ************************************************************************
+ * |<---------- data buffer ---------->|
+ *
+ * |<----------------- meta-data buffer allocated in Host ----------------|
+ *
+ * Note:
+ * - Considering the 4 bytes needed to store the Read index (R) and the
+ * Write index (W), the initial value is as follows:
+ * R = W = HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX
+ * - Buffer empty condition:
+ * R = W
+ *
+ * Regarding CFR data format:
+ * --------------------------
+ *
+ * Each CFR tone is stored in HW as 16-bits with the following format:
+ * {bits[15:12], bits[11:6], bits[5:0]} =
+ * {unsigned exponent (4 bits),
+ * signed mantissa_real (6 bits),
+ * signed mantissa_imag (6 bits)}
+ *
+ * CFR_real = mantissa_real * 2^(exponent-5)
+ * CFR_imag = mantissa_imag * 2^(exponent-5)
+ *
+ *
+ * The CFR data is written to the 16-bit unsigned output array (buff) in
+ * ascending tone order. For example, the Legacy20 CFR is output as follows:
+ *
+ * buff[0]: [CFR_exp[-26], CFR_mant_real[-26], CFR_mant_imag[-26]]
+ * buff[1]: [CFR_exp[-25], CFR_mant_real[-25], CFR_mant_imag[-25]]
+ * .
+ * .
+ * .
+ * buff[N-2]: [CFR_exp[25], CFR_mant_real[25], CFR_mant_imag[25]]
+ * buff[N-1]: [CFR_exp[26], CFR_mant_real[26], CFR_mant_imag[26]]
+ */
+
+/* Bandwidth of peer CFR captures */
+typedef enum {
+ HTT_PEER_CFR_CAPTURE_BW_20MHZ = 0,
+ HTT_PEER_CFR_CAPTURE_BW_40MHZ = 1,
+ HTT_PEER_CFR_CAPTURE_BW_80MHZ = 2,
+ HTT_PEER_CFR_CAPTURE_BW_160MHZ = 3,
+ HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4,
+ HTT_PEER_CFR_CAPTURE_BW_MAX,
+} HTT_PEER_CFR_CAPTURE_BW;
+
+/* Mode of the peer CFR captures. The type of RX frame for which the CFR
+ * was captured
+ */
+typedef enum {
+ HTT_PEER_CFR_CAPTURE_MODE_LEGACY = 0,
+ HTT_PEER_CFR_CAPTURE_MODE_DUP_LEGACY = 1,
+ HTT_PEER_CFR_CAPTURE_MODE_HT = 2,
+ HTT_PEER_CFR_CAPTURE_MODE_VHT = 3,
+ HTT_PEER_CFR_CAPTURE_MODE_MAX,
+} HTT_PEER_CFR_CAPTURE_MODE;
+
+typedef enum {
+ /* This message type is currently used for the below purpose:
+ *
+ * - capture_method = WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME in the
+ * wmi_peer_cfr_capture_cmd.
+ * If payload_present bit is set to 0 then the associated memory region
+ * gets allocated through WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID.
+ * If payload_present bit is set to 1 then CFR dump is part of the HTT
+ * message; the CFR dump will be present at the end of the message,
+ * after the chan_phy_mode.
+ */
+ HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 = 0x1,
+
+ /* Always keep this last */
+ HTT_PEER_CFR_CAPTURE_MSG_TYPE_MAX,
+} HTT_PEER_CFR_CAPTURE_MSG_TYPE;
+
+/**
+ * @brief target -> host CFR dump completion indication message definition
+ * htt_cfr_dump_compl_ind when the version is HTT_PEER_CFR_CAPTURE_MSG_TYPE_1.
+ *
+ * @details
+ * The following diagram shows the format of the Channel Frequency Response
+ * (CFR) dump completion indication. This inidcation is sent to the Host when
+ * the channel capture of a peer is copied by Firmware into the Host memory
+ *
+ * **************************************************************************
+ *
+ * Message format when the CFR capture message type is
+ * 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1'
+ *
+ * **************************************************************************
+ *
+ * |31 16|15 |8|7 0|
+ * |----------------------------------------------------------------|
+ * header: | reserved |P| msg_type |
+ * word 0 | | | |
+ * |----------------------------------------------------------------|
+ * payload: | cfr_capture_msg_type |
+ * word 1 | |
+ * |----------------------------------------------------------------|
+ * | vdev_id | captype | chbw | sts | mode | capbw |S| req_id |
+ * word 2 | | | | | | | | |
+ * |----------------------------------------------------------------|
+ * | mac_addr31to0 |
+ * word 3 | |
+ * |----------------------------------------------------------------|
+ * | unused / reserved | mac_addr47to32 |
+ * word 4 | | |
+ * |----------------------------------------------------------------|
+ * | index |
+ * word 5 | |
+ * |----------------------------------------------------------------|
+ * | length |
+ * word 6 | |
+ * |----------------------------------------------------------------|
+ * | timestamp |
+ * word 7 | |
+ * |----------------------------------------------------------------|
+ * | counter |
+ * word 8 | |
+ * |----------------------------------------------------------------|
+ * | chan_mhz |
+ * word 9 | |
+ * |----------------------------------------------------------------|
+ * | band_center_freq1 |
+ * word 10 | |
+ * |----------------------------------------------------------------|
+ * | band_center_freq2 |
+ * word 11 | |
+ * |----------------------------------------------------------------|
+ * | chan_phy_mode |
+ * word 12 | |
+ * |----------------------------------------------------------------|
+ * where,
+ * P - payload present bit (payload_present explained below)
+ * req_id - memory request id (mem_req_id explained below)
+ * S - status field (status explained below)
+ * capbw - capture bandwidth (capture_bw explained below)
+ * mode - mode of capture (mode explained below)
+ * sts - space time streams (sts_count explained below)
+ * chbw - channel bandwidth (channel_bw explained below)
+ * captype - capture type (cap_type explained below)
+ *
+ * The following field definitions describe the format of the CFR dump
+ * completion indication sent from the target to the host
+ *
+ * Header fields:
+ *
+ * Word 0
+ * - msg_type
+ * Bits 7:0
+ * Purpose: Identifies this as CFR TX completion indication
+ * Value: HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND
+ * - payload_present
+ * Bit 8
+ * Purpose: Identifies how CFR data is sent to host
+ * Value: 0 - If CFR Payload is written to host memory
+ * 1 - If CFR Payload is sent as part of HTT message
+ * (This is the requirement for SDIO/USB where it is
+ * not possible to write CFR data to host memory)
+ * - reserved
+ * Bits 31:9
+ * Purpose: Reserved
+ * Value: 0
+ *
+ * Payload fields:
+ *
+ * Word 1
+ * - cfr_capture_msg_type
+ * Bits 31:0
+ * Purpose: Contains the type of the message HTT_PEER_CFR_CAPTURE_MSG_TYPE
+ * to specify the format used for the remainder of the message
+ * Value: HTT_PEER_CFR_CAPTURE_MSG_TYPE_1
+ * (currently only MSG_TYPE_1 is defined)
+ *
+ * Word 2
+ * - mem_req_id
+ * Bits 6:0
+ * Purpose: Contain the mem request id of the region where the CFR capture
+ * has been stored - of type WMI_HOST_MEM_REQ_ID
+ * Value: WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID (if payload_present is 1,
+ this value is invalid)
+ * - status
+ * Bit 7
+ * Purpose: Boolean value carrying the status of the CFR capture of the peer
+ * Value: 1 (True) - Successful; 0 (False) - Not successful
+ * - capture_bw
+ * Bits 10:8
+ * Purpose: Carry the bandwidth of the CFR capture
+ * Value: Bandwidth of the CFR capture of type HTT_PEER_CFR_CAPTURE_BW
+ * - mode
+ * Bits 13:11
+ * Purpose: Carry the mode of the rx frame for which the CFR was captured
+ * Value: Mode of the CFR capture of type HTT_PEER_CFR_CAPTURE_MODE
+ * - sts_count
+ * Bits 16:14
+ * Purpose: Carry the number of space time streams
+ * Value: Number of space time streams
+ * - channel_bw
+ * Bits 19:17
+ * Purpose: Carry the bandwidth of the channel of the vdev performing the
+ * measurement
+ * Value: Bandwidth of the channel (of type HTT_PEER_CFR_CAPTURE_BW)
+ * - cap_type
+ * Bits 23:20
+ * Purpose: Carry the type of the capture
+ * Value: Capture type (of type WMI_PEER_CFR_CAPTURE_METHOD)
+ * - vdev_id
+ * Bits 31:24
+ * Purpose: Carry the virtual device id
+ * Value: vdev ID
+ *
+ * Word 3
+ * - mac_addr31to0
+ * Bits 31:0
+ * Purpose: Contain the bits 31:0 of the peer MAC address
+ * Value: Bits 31:0 of the peer MAC address
+ *
+ * Word 4
+ * - mac_addr47to32
+ * Bits 15:0
+ * Purpose: Contain the bits 47:32 of the peer MAC address
+ * Value: Bits 47:32 of the peer MAC address
+ *
+ * Word 5
+ * - index
+ * Bits 31:0
+ * Purpose: Contain the index at which this CFR dump was written in the Host
+ * allocated memory. This index is the number of bytes from the base address.
+ * Value: Index position
+ *
+ * Word 6
+ * - length
+ * Bits 31:0
+ * Purpose: Carry the length of the CFR capture of the peer, in bytes
+ * Value: Length of the CFR capture of the peer
+ *
+ * Word 7
+ * - timestamp
+ * Bits 31:0
+ * Purpose: Carry the time at which the CFR was captured in the hardware. The
+ * clock used for this timestamp is private to the target and not visible to
+ * the host i.e., Host can interpret only the relative timestamp deltas from
+ * one message to the next, but can't interpret the absolute timestamp from a
+ * single message.
+ * Value: Timestamp in microseconds
+ *
+ * Word 8
+ * - counter
+ * Bits 31:0
+ * Purpose: Carry the count of the current CFR capture from FW. This is
+ * helpful to identify any drops in FW in any scenario (e.g., lack of space
+ * in host memory)
+ * Value: Count of the current CFR capture
+ *
+ * Word 9
+ * - chan_mhz
+ * Bits 31:0
+ * Purpose: Carry the primary 20 MHz channel frequency in MHz of the VDEV
+ * Value: Primary 20 channel frequency
+ *
+ * Word 10
+ * - band_center_freq1
+ * Bits 31:0
+ * Purpose: Carry the center frequency 1 in MHz of the VDEV
+ * Value: Center frequency 1 in MHz
+ *
+ * Word 11
+ * - band_center_freq2
+ * Bits 31:0
+ * Purpose: Carry the center frequency 2 in MHz. valid only for 11acvht of
+ * the VDEV
+ * 80plus80 mode
+ * Value: Center frequency 2 in MHz
+ *
+ * Word 12
+ * - chan_phy_mode
+ * Bits 31:0
+ * Purpose: Carry the phy mode of the channel, of the VDEV
+ * Value: WLAN_PHY_MODE of the channel defined in wlan_defs.h
+ */
+PREPACK struct htt_cfr_dump_ind_type_1 {
+ A_UINT32 mem_req_id:7,
+ status:1,
+ capture_bw:3,
+ mode:3,
+ sts_count:3,
+ channel_bw:3,
+ cap_type:4,
+ vdev_id:8;
+ htt_mac_addr addr;
+ A_UINT32 index;
+ A_UINT32 length;
+ A_UINT32 timestamp;
+ A_UINT32 counter;
+ struct htt_chan_change_msg chan;
+} POSTPACK;
+
+PREPACK struct htt_cfr_dump_compl_ind {
+ A_UINT32 msg_type; /* HTT_PEER_CFR_CAPTURE_MSG_TYPE */
+ union {
+ /* Message format when msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 */
+ struct htt_cfr_dump_ind_type_1 htt_cfr_dump_compl_ind_type_1;
+ /* If there is a need to change the memory layout and its associated
+ * HTT indication format, a new CFR capture message type can be
+ * introduced and added into this union.
+ */
+ };
+} POSTPACK;
+
+/*
+ * Get / set macros for the bit fields within WORD-1 of htt_cfr_dump_compl_ind,
+ * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1
+ */
+#define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M 0x00000100
+#define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S 8
+
+#define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S; \
+ } while(0)
+#define HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_M) >> \
+ HTT_T2H_CFR_DUMP_PAYLOAD_PRESENT_ID_S)
+
+/*
+ * Get / set macros for the bit fields within WORD-2 of htt_cfr_dump_compl_ind,
+ * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1
+ */
+#define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M 0X0000007F
+#define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S 0
+#define HTT_T2H_CFR_DUMP_TYPE1_STATUS_M 0X00000080
+#define HTT_T2H_CFR_DUMP_TYPE1_STATUS_S 7
+#define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M 0X00000700
+#define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S 8
+#define HTT_T2H_CFR_DUMP_TYPE1_MODE_M 0X00003800
+#define HTT_T2H_CFR_DUMP_TYPE1_MODE_S 11
+#define HTT_T2H_CFR_DUMP_TYPE1_STS_M 0X0001C000
+#define HTT_T2H_CFR_DUMP_TYPE1_STS_S 14
+#define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M 0X000E0000
+#define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S 17
+#define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M 0X00F00000
+#define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S 20
+#define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M 0XFF000000
+#define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S 24
+
+#define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S; \
+ } while (0)
+#define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M) >> \
+ HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S)
+
+#define HTT_T2H_CFR_DUMP_TYPE1_STATUS_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STATUS, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STATUS_S; \
+ } while (0)
+#define HTT_T2H_CFR_DUMP_TYPE1_STATUS_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_TYPE1_STATUS_M) >> \
+ HTT_T2H_CFR_DUMP_TYPE1_STATUS_S)
+
+#define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_BW, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S; \
+ } while (0)
+#define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M) >> \
+ HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S)
+
+#define HTT_T2H_CFR_DUMP_TYPE1_MODE_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MODE, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MODE_S; \
+ } while (0)
+#define HTT_T2H_CFR_DUMP_TYPE1_MODE_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_TYPE1_MODE_M) >> \
+ HTT_T2H_CFR_DUMP_TYPE1_MODE_S)
+
+#define HTT_T2H_CFR_DUMP_TYPE1_STS_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STS, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STS_S; \
+ } while (0)
+#define HTT_T2H_CFR_DUMP_TYPE1_STS_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_TYPE1_STS_M) >> \
+ HTT_T2H_CFR_DUMP_TYPE1_STS_S)
+
+#define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S; \
+ } while (0)
+#define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M) >> \
+ HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S)
+
+#define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S; \
+ } while (0)
+#define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M) >> \
+ HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S)
+
+#define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID, value); \
+ (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S; \
+ } while (0)
+#define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_GET(word) \
+ (((word) & HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M) >> \
+ HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S)
+
+
+/**
+ * @brief target -> host peer (PPDU) stats message
+ * HTT_T2H_MSG_TYPE_PEER_STATS_IND
+ * @details
+ * This message is generated by FW when FW is sending stats to host
+ * about one or more PPDUs that the FW has transmitted to one or more peers.
+ * This message is sent autonomously by the target rather than upon request
+ * by the host.
+ * The following field definitions describe the format of the HTT target
+ * to host peer stats indication message.
+ *
+ * The HTT_T2H PPDU_STATS_IND message has a header followed by one
+ * or more PPDU stats records.
+ * Each PPDU stats record uses a htt_tx_ppdu_stats_info TLV.
+ * If the details of N PPDUS are sent in one PEER_STATS_IND message,
+ * then the message would start with the
+ * header, followed by N htt_tx_ppdu_stats_info structures, as depicted
+ * below.
+ *
+ * |31 16|15|14|13 11|10 9|8|7 0|
+ * |-------------------------------------------------------------|
+ * | reserved |MSG_TYPE |
+ * |-------------------------------------------------------------|
+ * rec 0 | TLV header |
+ * rec 0 |-------------------------------------------------------------|
+ * rec 0 | ppdu successful bytes |
+ * rec 0 |-------------------------------------------------------------|
+ * rec 0 | ppdu retry bytes |
+ * rec 0 |-------------------------------------------------------------|
+ * rec 0 | ppdu failed bytes |
+ * rec 0 |-------------------------------------------------------------|
+ * rec 0 | peer id | S|SG| BW | BA |A|rate code|
+ * rec 0 |-------------------------------------------------------------|
+ * rec 0 | retried MSDUs | successful MSDUs |
+ * rec 0 |-------------------------------------------------------------|
+ * rec 0 | TX duration | failed MSDUs |
+ * rec 0 |-------------------------------------------------------------|
+ * ...
+ * |-------------------------------------------------------------|
+ * rec N | TLV header |
+ * rec N |-------------------------------------------------------------|
+ * rec N | ppdu successful bytes |
+ * rec N |-------------------------------------------------------------|
+ * rec N | ppdu retry bytes |
+ * rec N |-------------------------------------------------------------|
+ * rec N | ppdu failed bytes |
+ * rec N |-------------------------------------------------------------|
+ * rec N | peer id | S|SG| BW | BA |A|rate code|
+ * rec N |-------------------------------------------------------------|
+ * rec N | retried MSDUs | successful MSDUs |
+ * rec N |-------------------------------------------------------------|
+ * rec N | TX duration | failed MSDUs |
+ * rec N |-------------------------------------------------------------|
+ *
+ * where:
+ * A = is A-MPDU flag
+ * BA = block-ack failure flags
+ * BW = bandwidth spec
+ * SG = SGI enabled spec
+ * S = skipped rate ctrl
+ * One htt_tx_ppdu_stats_info instance will have stats for one PPDU
+ *
+ * Header
+ * ------
+ * dword0 - b'0:7 - msg_type : HTT_T2H_MSG_TYPE_PEER_STATS_IND
+ * dword0 - b'8:31 - reserved : Reserved for future use
+ *
+ * payload include below peer_stats information
+ * --------------------------------------------
+ * @TLV : HTT_PPDU_STATS_INFO_TLV
+ * @tx_success_bytes : total successful bytes in the PPDU.
+ * @tx_retry_bytes : total retried bytes in the PPDU.
+ * @tx_failed_bytes : total failed bytes in the PPDU.
+ * @tx_ratecode : rate code used for the PPDU.
+ * @is_ampdu : Indicates PPDU is AMPDU or not.
+ * @ba_ack_failed : BA/ACK failed for this PPDU
+ * b00 -> BA received
+ * b01 -> BA failed once
+ * b10 -> BA failed twice, when HW retry is enabled.
+ * @bw : BW
+ * b00 -> 20 MHz
+ * b01 -> 40 MHz
+ * b10 -> 80 MHz
+ * b11 -> 160 MHz (or 80+80)
+ * @sg : SGI enabled
+ * @s : skipped ratectrl
+ * @peer_id : peer id
+ * @tx_success_msdus : successful MSDUs
+ * @tx_retry_msdus : retried MSDUs
+ * @tx_failed_msdus : MSDUs dropped in FW after max retry
+ * @tx_duration : Tx duration for the PPDU (microsecond units)
+ */
+
+
+/**
+ * @brief HTT_T2H_MSG_TYPE_BKPRESSURE_EVENTID Message
+ *
+ * @details
+ * HTT_T2H_MSG_TYPE_BKPRESSURE_EVENTID message is sent by the target when
+ * continuous backpressure is seen in the LMAC/ UMAC rings software rings.
+ * This message will only be sent if the backpressure condition has existed
+ * continuously for an initial period (100 ms).
+ * Repeat messages with updated information will be sent after each
+ * subsequent period (100 ms) as long as the backpressure remains unabated.
+ * This message indicates the ring id along with current head and tail index
+ * locations (i.e. write and read indices).
+ * The backpressure time indicates the time in ms for which continous
+ * backpressure has been observed in the ring.
+ *
+ * The message format is as follows:
+ *
+ * |31 24|23 16|15 8|7 0|
+ * |----------------+----------------+----------------+----------------|
+ * | ring_id | ring_type | pdev_id | msg_type |
+ * |-------------------------------------------------------------------|
+ * | tail_idx | head_idx |
+ * |-------------------------------------------------------------------|
+ * | backpressure_time_ms |
+ * |-------------------------------------------------------------------|
+ *
+ * The message is interpreted as follows:
+ * dword0 - b'0:7 - msg_type: This will be set to
+ * HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND
+ * b'8:15 - pdev_id: 0 indicates msg is for UMAC ring.
+ * 1, 2, 3 indicates pdev_id 0,1,2 and
+ the msg is for LMAC ring.
+ * b'16:23 - ring_type: Refer to enum htt_backpressure_ring_type.
+ * b'24:31 - ring_id: Refer enum htt_backpressure_umac_ring_id/
+ * htt_backpressure_lmac_ring_id. This represents
+ * the ring id for which continous backpressure is seen
+ *
+ * dword1 - b'0:15 - head_idx: This indicates the current head index of
+ * the ring indicated by the ring_id
+ *
+ * dword1 - b'16:31 - tail_idx: This indicates the current tail index of
+ * the ring indicated by the ring id
+ *
+ * dword2 - b'0:31 - backpressure_time_ms: Indicates how long continous
+ * backpressure has been seen in the ring
+ * indicated by the ring_id.
+ * Units = milliseconds
+ */
+#define HTT_T2H_RX_BKPRESSURE_PDEV_ID_M 0x0000ff00
+#define HTT_T2H_RX_BKPRESSURE_PDEV_ID_S 8
+#define HTT_T2H_RX_BKPRESSURE_RING_TYPE_M 0x00ff0000
+#define HTT_T2H_RX_BKPRESSURE_RING_TYPE_S 16
+#define HTT_T2H_RX_BKPRESSURE_RINGID_M 0xff000000
+#define HTT_T2H_RX_BKPRESSURE_RINGID_S 24
+#define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M 0x0000ffff
+#define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S 0
+#define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M 0xffff0000
+#define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S 16
+#define HTT_T2H_RX_BKPRESSURE_TIME_MS_M 0xffffffff
+#define HTT_T2H_RX_BKPRESSURE_TIME_MS_S 0
+
+#define HTT_T2H_RX_BKPRESSURE_PDEV_ID_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_PDEV_ID, value); \
+ (word) |= (value) << HTT_T2H_RX_BKPRESSURE_PDEV_ID_S; \
+ } while (0)
+#define HTT_T2H_RX_BKPRESSURE_PDEV_ID_GET(word) \
+ (((word) & HTT_T2H_RX_BKPRESSURE_PDEV_ID_M) >> \
+ HTT_T2H_RX_BKPRESSURE_PDEV_ID_S)
+
+#define HTT_T2H_RX_BKPRESSURE_RING_TYPE_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RING_TYPE, value); \
+ (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RING_TYPE_S; \
+ } while (0)
+#define HTT_T2H_RX_BKPRESSURE_RING_TYPE_GET(word) \
+ (((word) & HTT_T2H_RX_BKPRESSURE_RING_TYPE_M) >> \
+ HTT_T2H_RX_BKPRESSURE_RING_TYPE_S)
+
+#define HTT_T2H_RX_BKPRESSURE_RINGID_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_RINGID, value); \
+ (word) |= (value) << HTT_T2H_RX_BKPRESSURE_RINGID_S; \
+ } while (0)
+#define HTT_T2H_RX_BKPRESSURE_RINGID_GET(word) \
+ (((word) & HTT_T2H_RX_BKPRESSURE_RINGID_M) >> \
+ HTT_T2H_RX_BKPRESSURE_RINGID_S)
+
+#define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_HEAD_IDX, value); \
+ (word) |= (value) << HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S; \
+ } while (0)
+#define HTT_T2H_RX_BKPRESSURE_HEAD_IDX_GET(word) \
+ (((word) & HTT_T2H_RX_BKPRESSURE_HEAD_IDX_M) >> \
+ HTT_T2H_RX_BKPRESSURE_HEAD_IDX_S)
+
+#define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TAIL_IDX, value); \
+ (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S; \
+ } while (0)
+#define HTT_T2H_RX_BKPRESSURE_TAIL_IDX_GET(word) \
+ (((word) & HTT_T2H_RX_BKPRESSURE_TAIL_IDX_M) >> \
+ HTT_T2H_RX_BKPRESSURE_TAIL_IDX_S)
+
+#define HTT_T2H_RX_BKPRESSURE_TIME_MS_SET(word, value) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_T2H_RX_BKPRESSURE_TIME_MS, value); \
+ (word) |= (value) << HTT_T2H_RX_BKPRESSURE_TIME_MS_S; \
+ } while (0)
+#define HTT_T2H_RX_BKPRESSURE_TIME_MS_GET(word) \
+ (((word) & HTT_T2H_RX_BKPRESSURE_TIME_MS_M) >> \
+ HTT_T2H_RX_BKPRESSURE_TIME_MS_S)
+
+enum htt_backpressure_ring_type {
+ HTT_SW_RING_TYPE_UMAC,
+ HTT_SW_RING_TYPE_LMAC,
+ HTT_SW_RING_TYPE_MAX,
+};
+
+/* Ring id for which the message is sent to host */
+enum htt_backpressure_umac_ringid {
+ HTT_SW_RING_IDX_REO_REO2SW1_RING,
+ HTT_SW_RING_IDX_REO_REO2SW2_RING,
+ HTT_SW_RING_IDX_REO_REO2SW3_RING,
+ HTT_SW_RING_IDX_REO_REO2SW4_RING,
+ HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING,
+ HTT_SW_RING_IDX_REO_REO2TCL_RING,
+ HTT_SW_RING_IDX_REO_REO2FW_RING,
+ HTT_SW_RING_IDX_REO_REO_RELEASE_RING,
+ HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING,
+ HTT_SW_RING_IDX_TCL_TCL2TQM_RING,
+ HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING,
+ HTT_SW_RING_IDX_WBM_REO_RELEASE_RING,
+ HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING,
+ HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING,
+ HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING,
+ HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING,
+ HTT_SW_RING_IDX_REO_REO_CMD_RING,
+ HTT_SW_RING_IDX_REO_REO_STATUS_RING,
+ HTT_SW_UMAC_RING_IDX_MAX,
+};
+
+enum htt_backpressure_lmac_ringid {
+ HTT_SW_RING_IDX_FW2RXDMA_BUF_RING,
+ HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING,
+ HTT_SW_RING_IDX_FW2RXDMA_LINK_RING,
+ HTT_SW_RING_IDX_SW2RXDMA_BUF_RING,
+ HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING,
+ HTT_SW_RING_IDX_RXDMA2FW_RING,
+ HTT_SW_RING_IDX_RXDMA2SW_RING,
+ HTT_SW_RING_IDX_RXDMA2RELEASE_RING,
+ HTT_SW_RING_IDX_RXDMA2REO_RING,
+ HTT_SW_RING_IDX_MONITOR_STATUS_RING,
+ HTT_SW_RING_IDX_MONITOR_BUF_RING,
+ HTT_SW_RING_IDX_MONITOR_DESC_RING,
+ HTT_SW_RING_IDX_MONITOR_DEST_RING,
+ HTT_SW_LMAC_RING_IDX_MAX,
+};
+
+PREPACK struct htt_t2h_msg_bkpressure_event_ind_t {
+ A_UINT32 msg_type: 8, /* HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND */
+ pdev_id: 8,
+ ring_type: 8, /* htt_backpressure_ring_type */
+ /*
+ * ring_id holds an enum value from either
+ * htt_backpressure_umac_ringid or
+ * htt_backpressure_lmac_ringid, based on
+ * the ring_type setting.
+ */
+ ring_id: 8;
+ A_UINT16 head_idx;
+ A_UINT16 tail_idx;
+ A_UINT32 backpressure_time_ms; /* Time in milliseconds for which backpressure is seen continuously */
+} POSTPACK;
+
+
+/*
+ * Defines two 32 bit words that can be used by the target to indicate a per
+ * user RU allocation and rate information.
+ *
+ * This information is currently provided in the "sw_response_reference_ptr"
+ * (word 0) and "sw_response_reference_ptr_ext" (word 1) fields of the
+ * "rx_ppdu_end_user_stats" TLV.
+ *
+ * VALID:
+ * The consumer of these words must explicitly check the valid bit,
+ * and only attempt interpretation of any of the remaining fields if
+ * the valid bit is set to 1.
+ *
+ * VERSION:
+ * The consumer of these words must also explicitly check the version bit,
+ * and only use the V0 definition if the VERSION field is set to 0.
+ *
+ * Version 1 is currently undefined, with the exception of the VALID and
+ * VERSION fields.
+ *
+ * Version 0:
+ *
+ * The fields below are duplicated per BW.
+ *
+ * The consumer must determine which BW field to use, based on the UL OFDMA
+ * PPDU BW indicated by HW.
+ *
+ * RU_START: RU26 start index for the user.
+ * Note that this is always using the RU26 index, regardless
+ * of the actual RU assigned to the user
+ * (i.e. the second RU52 is RU_START 2, RU_SIZE
+ * HTT_UL_OFDMA_V0_RU_SIZE_RU_52)
+ *
+ * For example, 20MHz (the value in the top row is RU_START)
+ *
+ * RU Size 0 (26): |0|1|2|3|4|5|6|7|8|
+ * RU Size 1 (52): | | | | | |
+ * RU Size 2 (106): | | | |
+ * RU Size 3 (242): | |
+ *
+ * RU_SIZE: Indicates the RU size, as defined by enum
+ * htt_ul_ofdma_user_info_ru_size.
+ *
+ * LDPC: LDPC enabled (if 0, BCC is used)
+ *
+ * DCM: DCM enabled
+ *
+ * |31 | 30|29 23|22 19|18 16|15 9| 8 | 7 |6 3|2 0|
+ * |---------------------------------+--------------------------------|
+ * |Ver|Valid| FW internal |
+ * |---------------------------------+--------------------------------|
+ * | reserved |Trig Type|RU SIZE| RU START |DCM|LDPC|MCS |NSS|
+ * |---------------------------------+--------------------------------|
+ */
+
+enum htt_ul_ofdma_user_info_ru_size {
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_26,
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_52,
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_106,
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_242,
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_484,
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_996,
+ HTT_UL_OFDMA_V0_RU_SIZE_RU_996x2
+};
+
+/* htt_up_ofdma_user_info_v0 provides an abstract view of the info */
+struct htt_ul_ofdma_user_info_v0 {
+ A_UINT32 word0;
+ A_UINT32 word1;
+};
+
+/* htt_up_ofdma_user_info_v0_bitmap shows what bitfields are within the info */
+PREPACK struct htt_ul_ofdma_user_info_v0_bitmap {
+ union {
+ A_UINT32 word0;
+ struct {
+ A_UINT32 w0_fw_rsvd:30;
+ A_UINT32 w0_valid:1;
+ A_UINT32 w0_version:1;
+ };
+ };
+ union {
+ A_UINT32 word1;
+ struct {
+ A_UINT32 w1_nss:3;
+ A_UINT32 w1_mcs:4;
+ A_UINT32 w1_ldpc:1;
+ A_UINT32 w1_dcm:1;
+ A_UINT32 w1_ru_start:7;
+ A_UINT32 w1_ru_size:3;
+ A_UINT32 w1_trig_type:4;
+ A_UINT32 w1_unused:9;
+ };
+ };
+} POSTPACK;
+
+enum HTT_UL_OFDMA_TRIG_TYPE {
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BASIC = 0,
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BFRP,
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_BAR,
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_MU_RTS_CTS,
+ HTT_UL_OFDMA_USER_INFO_V0_TRIG_TYPE_BSR,
+};
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_SZ (sizeof(struct htt_ul_ofdma_user_info_v0))
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M 0x0000ffff
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S 0
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M 0x40000000
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S 30
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M 0x80000000
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S 31
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M 0x00000007
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S 0
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M 0x00000078
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S 3
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M 0x00000080
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S 7
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M 0x00000100
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S 8
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M 0x0000fe00
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S 9
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M 0x00070000
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S 16
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M 0x00780000
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S 19
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_M 0xff800000
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RESERVED1_S 23
+
+/*--- word 0 ---*/
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_FW_INTERNAL_S)); \
+ } while (0)
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VALID, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VALID_S)); \
+ } while (0)
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W0_VER_M) >> HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W0_VER_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W0_VER, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W0_VER_S)); \
+ } while (0)
+
+
+/*--- word 1 ---*/
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_NSS, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_NSS_S)); \
+ } while (0)
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_MCS, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_MCS_S)); \
+ } while (0)
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_LDPC_S)); \
+ } while (0)
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_DCM, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_DCM_S)); \
+ } while (0)
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_START_S)); \
+ } while (0)
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE_S)); \
+ } while (0)
+
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_GET(word) \
+ (((word) & HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_M) >> HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_S)
+
+#define HTT_UL_OFDMA_USER_INFO_V0_W1_TRIG_TYP_SET(word, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP, _val); \
+ ((word) |= ((_val) << HTT_UL_OFDMA_USER_INFO_V0_W1_RU_TRIG_TYP_S)); \
+ } while (0)
+
#endif
diff --git a/drivers/staging/fw-api/fw/htt_ppdu_stats.h b/drivers/staging/fw-api/fw/htt_ppdu_stats.h
index 7499827..9cc2677 100644
--- a/drivers/staging/fw-api/fw/htt_ppdu_stats.h
+++ b/drivers/staging/fw-api/fw/htt_ppdu_stats.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -114,6 +114,19 @@
((_var) |= ((_val) << HTT_PPDU_STATS_ARRAY_ITEM_TLV_SGI_S)); \
} while (0)
+#define HTT_PPDU_STATS_ARRAY_ITEM_TLV_SR_M 0x00008000
+#define HTT_PPDU_STATS_ARRAY_ITEM_TLV_SR_S 15
+
+#define HTT_PPDU_STATS_ARRAY_ITEM_TLV_SR_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_ARRAY_ITEM_TLV_SR_M) >> \
+ HTT_PPDU_STATS_ARRAY_ITEM_TLV_SR_S)
+
+#define HTT_PPDU_STATS_ARRAY_ITEM_TLV_SR_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_ARRAY_ITEM_TLV_SR, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_ARRAY_ITEM_TLV_SR_S)); \
+ } while (0)
+
#define HTT_PPDU_STATS_ARRAY_ITEM_TLV_PEERID_M 0xffff0000
#define HTT_PPDU_STATS_ARRAY_ITEM_TLV_PEERID_S 16
@@ -193,13 +206,42 @@
3: 160 MHz or 80+80 MHz */
bw: 3,
sgi: 1,
- reserved0: 1,
+ skipped_rate_ctrl: 1,
peer_id: 16;
A_UINT32 tx_success_msdus: 16,
tx_retry_msdus: 16;
A_UINT32 tx_failed_msdus: 16,
/* united in us */
tx_duration: 16;
+ /*
+ * 1 in bit 0 of valid_bitmap represents that bitmap itself is valid.
+ * If the bitmap is valid (i.e. bit 0 is set), then check the other bits
+ * of bitmap to know which fields within htt_tx_ppdu_stats_info are valid.
+ * If bit 1 is set, tx_success_bytes is valid
+ * If bit 2 is set, tx_retry_bytes is valid
+ * ...
+ * If bit 14 is set, tx_duration is valid
+ * If bit 15 is set, all of ack_rssi_chain are valid,
+ * for each validation of chain, need to check value in field
+ * If bit 16 is set, tx_timestamp is valid
+ * If bit 16 is set, sa_ant_matrix is valid
+ * If bit 17 is set, tid is valid
+ */
+ A_UINT32 valid_bitmap;
+ A_UINT32 ext_valid_bitmap; /* reserved for future extension valid bitmap */
+ /* ack rssi for each chain */
+ A_UINT32 ack_rssi_chain0: 8, /* Units: dB w.r.t noise floor, RSSI of Ack of all active chains. Value of 0x80 indicates invalid.*/
+ ack_rssi_chain1: 8, /* same as above */
+ ack_rssi_chain2: 8, /* same as above */
+ ack_rssi_chain3: 8; /* same as above */
+ A_UINT32 ack_rssi_chain4: 8, /* same as above */
+ ack_rssi_chain5: 8, /* same as above */
+ ack_rssi_chain6: 8, /* same as above */
+ ack_rssi_chain7: 8; /* same as above */
+ A_UINT32 tx_timestamp; /* HW assigned timestamp with microsecond unit */
+ A_UINT32 sa_ant_matrix: 8, /* This sa_ant_matrix provides a bitmask of the antennas used while frame transmit */
+ tid: 8,
+ reserved_1: 16;
} POSTPACK;
typedef struct {
@@ -211,15 +253,37 @@
* tx_ppdu_stats_info is variable length, with length =
* number_of_ppdu_stats * sizeof (struct htt_tx_ppdu_stats_info)
*/
- A_UINT32 tx_ppdu_stats_info[1/*number_of_ppdu_stats*/];
+ struct htt_tx_ppdu_stats_info tx_ppdu_stats_info[1/*number_of_ppdu_stats*/];
} htt_ppdu_stats_usr_common_array_tlv_v;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
+ union {
+ /* DEPRECATED (target_type)
+ * The target_type field is not actually present in the HTT messages
+ * produced by the FW. However, it cannot be removed (yet), due to
+ * FW code that refers to this field.
+ * As a workaround, this target_type field is being moved into a
+ * union with the "hw" field that actually is present in the message.
+ * This makes the message definitions become consistent with the
+ * actual message contents, while not breaking the compilation of
+ * code that refers to the target_type field.
+ * Overlaying the memory for "target_type" and "hw" does not cause
+ * problems, because the FW code that refers to target_type first
+ * writes a value into the target_type field, then writes data into
+ * the hw field.
+ * Once all FW references to the target_type field have been removed,
+ * the target_type field def and the encapsulating anonymous union
+ * will be removed from this htt_ppdu_stats_sch_cmd_tlv_v struct def.
+ */
+ A_UINT32 target_type;
- /* Refer bmi_msg.h */
- A_UINT32 target_type;
- A_UINT32 hw[1]; /* Variable length, refer to struct scheduler_cmd_status */
+ /*
+ * The hw portion of this struct contains a scheduler_command_status
+ * struct, whose definition is different for different target HW types.
+ */
+ A_UINT32 hw[1];
+ };
} htt_ppdu_stats_sch_cmd_tlv_v;
#define HTT_PPDU_STATS_COMMON_TLV_SCH_CMDID_M 0x0000ffff
@@ -296,8 +360,11 @@
HTT_STATS_FTYPE_SGEN_MU_RTS,
HTT_STATS_FTYPE_SGEN_MU_BSR,
HTT_STATS_FTYPE_SGEN_UL_BSR,
+ HTT_STATS_FTYPE_SGEN_UL_BSR_TRIGGER = HTT_STATS_FTYPE_SGEN_UL_BSR, /*alias*/
HTT_STATS_FTYPE_TIDQ_DATA_SU,
HTT_STATS_FTYPE_TIDQ_DATA_MU,
+ HTT_STATS_FTYPE_SGEN_UL_BSR_RESP,
+ HTT_STATS_FTYPE_SGEN_QOS_NULL,
HTT_STATS_FTYPE_MAX,
};
typedef enum HTT_STATS_FTYPE HTT_STATS_FTYPE;
@@ -342,6 +409,33 @@
};
typedef enum HTT_PPDU_STATS_BW HTT_PPDU_STATS_BW;
+enum HTT_PPDU_STATS_SEQ_TYPE {
+ HTT_SEQTYPE_UNSPECIFIED = 0,
+ HTT_SEQTYPE_SU = 1,
+ HTT_SEQTYPE_AC_MU_MIMO = 2,
+ HTT_SEQTYPE_AX_MU_MIMO = 3,
+ HTT_SEQTYPE_MU_OFDMA = 4,
+ HTT_SEQTYPE_UL_TRIG = 5,
+ HTT_SEQTYPE_BURST_BCN = 6,
+ HTT_SEQTYPE_UL_BSR_RESP = 7,
+ HTT_SEQTYPE_UL_BSR_TRIG = 8,
+ HTT_SEQTYPE_UL_RESP = 9,
+};
+typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE;
+
+#define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_M 0x00ff0000
+#define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_S 16
+
+#define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_M) >> \
+ HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_S)
+
+#define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_S)); \
+ } while (0)
+
#define HTT_PPDU_STATS_COMMON_TLV_BW_M 0x000f0000
#define HTT_PPDU_STATS_COMMON_TLV_BW_S 16
@@ -400,15 +494,18 @@
/* BIT [ 7 : 0] :- frame_type - HTT_STATS_FTYPE
* BIT [ 15: 8] :- queue_type - HTT_TX_QUEUE_TYPE
* BIT [ 19: 16] :- bw - HTT_PPDU_STATS_BW
- * BIT [ 31: 20] :- reserved
+ * BIT [ 27: 20] :- ppdu_seq_type - HTT_PPDU_STATS_SEQ_TYPE
+ * BIT [ 31: 28] :- reserved
*/
union {
A_UINT32 bw__queue_type__frame_type;
+ A_UINT32 ppdu_seq_type__bw__queue_type__frame_type;
struct {
A_UINT32 frame_type: 8,
queue_type: 8,
bw: 4,
- reserved0: 12;
+ ppdu_seq_type: 8,
+ reserved0: 4;
};
};
A_UINT32 chain_mask;
@@ -426,6 +523,42 @@
chan_mhz: 16;
};
};
+
+ /*
+ * The cca_delta_time_us reports the time the tx PPDU in question
+ * was waiting in the HW tx queue for the clear channel assessment
+ * to indicate that the transmission could start.
+ * If this CCA delta time is zero or small, this indicates that the
+ * air interface was unused prior to the transmission, and thus it's
+ * improbable that there was a collision with some other transceiver's
+ * transmission.
+ * In contrast, a large CCA delta time means that this transceiver had
+ * to wait a long time for the air interface to be available; it's
+ * possible that other transceivers were also waiting for the air
+ * interface to become available, and if the other waiting transceiver's
+ * CW backoff aligned with this one, to have a transmit collision.
+ */
+ A_UINT32 cca_delta_time_us;
+
+ /*
+ * The rxfrm_delta_time_us reports the time the tx PPDU in question
+ * was waiting in the HW tx queue while there was an ongoing rx,
+ * either because the rx was already ongoing at the time the tx PPDU
+ * was enqueued, or because the rx (i.e. the peer's tx) won the air
+ * interface contention over the local vdev's tx.
+ */
+ A_UINT32 rxfrm_delta_time_us;
+
+ /*
+ * The txfrm_delta_time_us reports the time from when the tx PPDU
+ * in question was enqueued into the HW tx queue until the time the
+ * tx completion interrupt for the PPDU occurred.
+ * Thus, the txfrm_delta_time_us incorporates any time the tx PPDU
+ * had to wait for the air interface to become available, the PPDU
+ * duration, the block ack reception, and the tx completion interrupt
+ * latency.
+ */
+ A_UINT32 txfrm_delta_time_us;
} htt_ppdu_stats_common_tlv;
#define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff
@@ -506,6 +639,18 @@
((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_BW_S)); \
} while (0)
+#define HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA_M 0x00004000
+#define HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA_S 14
+
+#define HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA_M) >> \
+ HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA_S)
+
+#define HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA_S)); \
+ } while (0)
#define HTT_PPDU_STATS_USER_COMMON_TLV_FRAME_CTRL_M 0x0000ffff
#define HTT_PPDU_STATS_USER_COMMON_TLV_FRAME_CTRL_S 0
@@ -552,7 +697,8 @@
/* BIT [ 0 : 0] :- mcast
* BIT [ 9 : 1] :- mpdus_tried
* BIT [ 13: 10] :- bw - HTT_PPDU_STATS_BW
- * BIT [ 31: 14] :- rsvd
+ * BIT [ 14: 14] : - delayed_ba
+ * BIT [ 31: 15] :- rsvd
*/
union {
A_UINT32 bw__mpdus_tried__mcast;
@@ -560,7 +706,8 @@
A_UINT32 mcast: 1,
mpdus_tried: 9,
bw: 4,
- reserved0: 18;
+ delayed_ba: 1,
+ reserved0: 17;
};
};
@@ -575,6 +722,36 @@
};
};
+ /*
+ * Data fields containing the physical address info of a MSDU buffer
+ * as well as the owner and a SW cookie info that can be used by the host
+ * to look up the virtual address of the MSDU buffer.
+ * These fields are only valid if is_buffer_addr_info_valid is set to 1.
+ */
+ A_UINT32 buffer_paddr_31_0 : 32;
+ A_UINT32 buffer_paddr_39_32 : 8,
+ return_buffer_manager : 3,
+ sw_buffer_cookie : 21;
+
+ /*
+ * host_opaque_cookie : Host can send upto 2 bytes of opaque
+ * cookie in TCL_DATA_CMD and FW will replay this back in
+ * HTT PPDU stats. Valid only if sent to FW through
+ * exception mechanism.
+ *
+ * is_standalone : This msdu was sent as a single MSDU/MPDU
+ * PPDU as indicated by host via TCL_DATA_CMD using
+ * the send_as_standalone bit.
+ *
+ * is_buffer_addr_info_valid : This will be set whenever a MSDU is sent as
+ * a singleton (single-MSDU PPDU) for FW use-cases or as indicated by host
+ * via send_as_standalone in TCL_DATA_CMD.
+ */
+ A_UINT32 host_opaque_cookie: 16,
+ is_host_opaque_valid: 1,
+ is_standalone: 1,
+ is_buffer_addr_info_valid: 1,
+ reserved1: 13;
} htt_ppdu_stats_user_common_tlv;
#define HTT_PPDU_STATS_USER_RATE_TLV_TID_NUM_M 0x000000ff
@@ -672,6 +849,104 @@
((_var) |= ((_val) << HTT_PPDU_STATS_USER_RATE_TLV_RESP_TYPE_VALID_S)); \
} while (0)
+
+#define HTT_PPDU_STATS_BUF_ADDR_39_32_M 0x000000ff
+#define HTT_PPDU_STATS_BUF_ADDR_39_32_S 0
+
+#define HTT_PPDU_STATS_BUF_ADDR_39_32__GET(_var) \
+ (((_var) & HTT_PPDU_STATS_BUF_ADDR_39_32_M) >> \
+ HTT_PPDU_STATS_BUF_ADDR_39_32_S)
+
+#define HTT_PPDU_STATS_BUF_ADDR_39_32_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_BUF_ADDR_39_32, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_BUF_ADDR_39_32_S)); \
+ } while (0)
+
+
+#define HTT_PPDU_STATS_RETURN_BUF_MANAGER_M 0x00000700
+#define HTT_PPDU_STATS_RETURN_BUF_MANAGER_S 8
+
+#define HTT_PPDU_STATS_RETURN_BUF_MANAGER_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_RETURN_BUF_MANAGER_M) >> \
+ HTT_PPDU_STATS_RETURN_BUF_MANAGER_S)
+
+#define HTT_PPDU_STATS_RETURN_BUF_MANAGER_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_RETURN_BUF_MANAGER, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_RETURN_BUF_MANAGER_S)); \
+ } while (0)
+
+
+#define HTT_PPDU_STATS_SW_BUFFER_COOKIE_M 0xfffff800
+#define HTT_PPDU_STATS_SW_BUFFER_COOKIE_S 11
+
+#define HTT_PPDU_STATS_SW_BUFFER_COOKIE_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_SW_BUFFER_COOKIE_M) >> \
+ HTT_PPDU_STATS_SW_BUFFER_COOKIE_S)
+
+#define HTT_PPDU_STATS_SW_BUFFER_COOKIE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_SW_BUFFER_COOKIE, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_SW_BUFFER_COOKIE_S)); \
+ } while (0)
+
+
+#define HTT_PPDU_STATS_HOST_OPAQUE_COOKIE_M 0x0000FFFF
+#define HTT_PPDU_STATS_HOST_OPAQUE_COOKIE_S 0
+
+#define HTT_PPDU_STATS_HOST_OPAQUE_COOKIE_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_HOST_OPAQUE_COOKIE_M) >> \
+ HTT_PPDU_STATS_HOST_OPAQUE_COOKIE_S)
+
+#define HTT_PPDU_STAT_HOST_OPAQUE_COOKIE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_HOST_OPAQUE_COOKIE, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_HOST_OPAQUE_COOKIE_S)); \
+ } while (0)
+
+
+#define HTT_PPDU_STATS_IS_OPAQUE_VALID_M 0x00010000
+#define HTT_PPDU_STATS_IS_OPAQUE_VALID_S 16
+
+#define HTT_PPDU_STATS_IS_OPAQUE_VALID_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_IS_OPAQUE_VALID_M) >> \
+ HTT_PPDU_STATS_IS_OPAQUE_VALID_S)
+
+#define HTT_PPDU_STATS_IS_OPAQUE_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_IS_OPAQUE_VALID, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_IS_OPAQUE_VALID_S)); \
+ } while (0)
+
+
+#define HTT_PPDU_STATS_IS_STANDALONE_M 0x00020000
+#define HTT_PPDU_STATS_IS_STANDALONE_S 17
+
+#define HTT_PPDU_STATS_IS_STANDALONE_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_IS_STANDALONE_M) >> \
+ HTT_PPDU_STATS_IS_OPAQUE_VALID_S)
+
+#define HTT_PPDU_STATS_IS_STANDALONE_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_IS_STANDALONE, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_IS_STANDALONE_S)); \
+ } while (0)
+
+
+#define HTT_PPDU_STATS_IS_BUFF_INFO_VALID_M 0x000400000
+#define HTT_PPDU_STATS_IS_BUFF_INFO_VALID_S 18
+
+#define HTT_PPDU_STATS_IS_BUFF_INFO_VALID_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_IS_BUFF_INFO_VALID_M) >> \
+ HTT_PPDU_STATS_IS_BUFF_INFO_VALID_S)
+
+#define HTT_PPDU_STATS_IS_BUFF_INFO_VALID_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_IS_BUFF_INFO_VALID, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_IS_BUFF_INFO_VALID_S)); \
+ } while (0)
+
enum HTT_PPDU_STATS_PPDU_TYPE {
HTT_PPDU_STATS_PPDU_TYPE_SU,
HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO,
@@ -958,23 +1233,27 @@
* BIT [ 27: 24] :- gi - HTT_PPDU_STATS_GI
* BIT [ 28: 28] :- dcm
* BIT [ 29: 29] :- ldpc
- * BIT [ 31: 30] :- reserved4
+ * BIT [ 30: 30] :- valid_skipped_rate_ctrl
+ * This flag indicates whether the skipped_rate_ctrl
+ * flag should be ignored, or if it holds valid data.
+ * BIT [ 31: 31] :- skipped_rate_ctrl
*/
union {
A_UINT32 rate_info;
struct {
- A_UINT32 ltf_size: 2,
- stbc: 1,
- he_re: 1,
- txbf: 4,
- bw: 4,
- nss: 4,
- mcs: 4,
- preamble: 4,
- gi: 4,
- dcm: 1,
- ldpc: 1,
- reserved4: 2;
+ A_UINT32 ltf_size: 2,
+ stbc: 1,
+ he_re: 1,
+ txbf: 4,
+ bw: 4,
+ nss: 4,
+ mcs: 4,
+ preamble: 4,
+ gi: 4,
+ dcm: 1,
+ ldpc: 1,
+ valid_skipped_rate_ctrl: 1,
+ skipped_rate_ctrl: 1;
};
};
@@ -1009,8 +1288,32 @@
resp_ppdu_type: 2;
};
};
+
+ /* Note: This is for tracking a UL OFDMA packet */
+ union {
+ A_UINT32 trig_cookie_info;
+ struct {
+ A_UINT32 trig_cookie: 16,
+ trig_cookie_rsvd: 15,
+ trig_cookie_valid: 1;
+ };
+ };
} htt_ppdu_stats_user_rate_tlv;
+#define HTT_PPDU_STATS_USR_RATE_COOKIE_M 0x0000ffff
+#define HTT_PPDU_STATS_USR_RATE_COOKIE_S 0
+
+#define HTT_PPDU_STATS_USR_RATE_VALID_M 0x80000000
+#define HTT_PPDU_STATS_USR_RATE_VALID_S 31
+
+#define HTT_PPDU_STATS_USR_RATE_COOKIE_GET(_val) \
+ (((_val) & HTT_PPDU_STATS_USR_RATE_COOKIE_M) >> \
+ HTT_PPDU_STATS_USR_RATE_COOKIE_S)
+
+#define HTT_PPDU_STATS_USR_RATE_VALID_GET(_val) \
+ (((_val) & HTT_PPDU_STATS_USR_RATE_VALID_M) >> \
+ HTT_PPDU_STATS_USR_RATE_VALID_S)
+
#define HTT_PPDU_STATS_ENQ_MPDU_BITMAP_TLV_TID_NUM_M 0x000000ff
#define HTT_PPDU_STATS_ENQ_MPDU_BITMAP_TLV_TID_NUM_S 0
@@ -1477,7 +1780,7 @@
((_var) |= ((_val) << HTT_PPDU_STATS_FLUSH_TLV_NUM_MPDU_S)); \
} while (0)
-#define HTT_PPDU_STATS_FLUSH_TLV_NUM_MSDU_M 0x01fe0000
+#define HTT_PPDU_STATS_FLUSH_TLV_NUM_MSDU_M 0x7ffe0000
#define HTT_PPDU_STATS_FLUSH_TLV_NUM_MSDU_S 17
#define HTT_PPDU_STATS_FLUSH_TLV_NUM_MSDU_GET(_var) \
@@ -1576,17 +1879,44 @@
};
} htt_ppdu_stats_flush_tlv;
+#define HTT_PPDU_STATS_TX_MGMTCTRL_TLV_FRAME_LENGTH_M 0x0000ffff
+#define HTT_PPDU_STATS_TX_MGMTCTRL_TLV_FRAME_LENGTH_S 0
+
+#define HTT_PPDU_STATS_TX_MGMTCTRL_TLV_FRAME_LENGTH_GET(_var) \
+ (((_var) & HTT_PPDU_STATS_TX_MGMTCTRL_TLV_FRAME_LENGTH_M) >> \
+ HTT_PPDU_STATS_TX_MGMTCTRL_TLV_FRAME_LENGTH_S)
+
+#define HTT_PPDU_STATS_TX_MGMTCTRL_TLV_FRAME_LENGTH_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_PPDU_STATS_TX_MGMTCTRL_TLV_FRAME_LENGTH, _val); \
+ ((_var) |= ((_val) << HTT_PPDU_STATS_TX_MGMTCTRL_TLV_FRAME_LENGTH_S)); \
+ } while (0)
+
typedef struct {
htt_tlv_hdr_t tlv_hdr;
+ /*
+ * BIT [ 15 : 0] :- frame_length
+ * BIT [ 31 : 16] :- reserved1
+ */
+ union {
+ A_UINT32 rsvd__frame_length;
+ struct {
+ A_UINT32 frame_length: 16,
+ reserved1: 16; /* set to 0x0 */
+ };
+ };
+
/* Future purpose */
- A_UINT32 reserved1; /* set to 0x0 */
A_UINT32 reserved2; /* set to 0x0 */
A_UINT32 reserved3; /* set to 0x0 */
/* mgmt/ctrl frame payload
- * The size of payload (in bytes) can be derived from the length in
- * tlv parametes, minus the 12 bytes of the above fields.
+ * The size of the actual mgmt payload (in bytes) can be obtained from
+ * the frame_length field.
+ * The size of entire payload including the padding for alignment
+ * (in bytes) can be derived from the length in tlv parametes,
+ * minus the 12 bytes of the above fields.
*/
A_UINT32 payload[1];
} htt_ppdu_stats_tx_mgmtctrl_payload_tlv;
diff --git a/drivers/staging/fw-api/fw/htt_stats.h b/drivers/staging/fw-api/fw/htt_stats.h
index 0bbd13c..7266729 100644
--- a/drivers/staging/fw-api/fw/htt_stats.h
+++ b/drivers/staging/fw-api/fw/htt_stats.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -35,7 +35,6 @@
* Max supported stats :- 256.
*/
enum htt_dbg_ext_stats_type {
-
/* HTT_DBG_EXT_STATS_RESET
* PARAM:
* - config_param0 : start_offset (stats type)
@@ -45,7 +44,7 @@
* RESP MSG:
* - No response sent.
*/
- HTT_DBG_EXT_STATS_RESET = 0,
+ HTT_DBG_EXT_STATS_RESET = 0,
/* HTT_DBG_EXT_STATS_PDEV_TX
* PARAMS:
@@ -53,7 +52,7 @@
* RESP MSG:
* - htt_tx_pdev_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_TX = 1,
+ HTT_DBG_EXT_STATS_PDEV_TX = 1,
/* HTT_DBG_EXT_STATS_PDEV_RX
* PARAMS:
@@ -61,7 +60,7 @@
* RESP MSG:
* - htt_rx_pdev_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_RX = 2,
+ HTT_DBG_EXT_STATS_PDEV_RX = 2,
/* HTT_DBG_EXT_STATS_PDEV_TX_HWQ
* PARAMS:
@@ -69,7 +68,7 @@
* RESP MSG:
* - htt_tx_hwq_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_TX_HWQ = 3,
+ HTT_DBG_EXT_STATS_PDEV_TX_HWQ = 3,
/* HTT_DBG_EXT_STATS_PDEV_TX_SCHED
* PARAMS:
@@ -77,7 +76,7 @@
* RESP MSG:
* - htt_stats_tx_sched_t
*/
- HTT_DBG_EXT_STATS_PDEV_TX_SCHED = 4,
+ HTT_DBG_EXT_STATS_PDEV_TX_SCHED = 4,
/* HTT_DBG_EXT_STATS_PDEV_ERROR
* PARAMS:
@@ -85,7 +84,7 @@
* RESP MSG:
* - htt_hw_err_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_ERROR = 5,
+ HTT_DBG_EXT_STATS_PDEV_ERROR = 5,
/* HTT_DBG_EXT_STATS_PDEV_TQM
* PARAMS:
@@ -93,7 +92,7 @@
* RESP MSG:
* - htt_tx_tqm_pdev_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_TQM = 6,
+ HTT_DBG_EXT_STATS_PDEV_TQM = 6,
/* HTT_DBG_EXT_STATS_TQM_CMDQ
* PARAMS:
@@ -103,7 +102,7 @@
* RESP MSG:
* - htt_tx_tqm_cmdq_stats_t
*/
- HTT_DBG_EXT_STATS_TQM_CMDQ = 7,
+ HTT_DBG_EXT_STATS_TQM_CMDQ = 7,
/* HTT_DBG_EXT_STATS_TX_DE_INFO
* PARAMS:
@@ -111,7 +110,7 @@
* RESP MSG:
* - htt_tx_de_stats_t
*/
- HTT_DBG_EXT_STATS_TX_DE_INFO = 8,
+ HTT_DBG_EXT_STATS_TX_DE_INFO = 8,
/* HTT_DBG_EXT_STATS_PDEV_TX_RATE
* PARAMS:
@@ -119,7 +118,7 @@
* RESP MSG:
* - htt_tx_pdev_rate_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_TX_RATE = 9,
+ HTT_DBG_EXT_STATS_PDEV_TX_RATE = 9,
/* HTT_DBG_EXT_STATS_PDEV_RX_RATE
* PARAMS:
@@ -127,7 +126,7 @@
* RESP MSG:
* - htt_rx_pdev_rate_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_RX_RATE = 10,
+ HTT_DBG_EXT_STATS_PDEV_RX_RATE = 10,
/* HTT_DBG_EXT_STATS_PEER_INFO
* PARAMS:
@@ -146,11 +145,19 @@
* 6 bit htt_msdu_flow_stats_tlv
* - config_param2: [Bit31 : Bit0] mac_addr31to0
* - config_param3: [Bit15 : Bit0] mac_addr47to32
- * [Bit31 : Bit16] reserved
+ * [Bit 16] If this bit is set, reset per peer stats
+ * of corresponding tlv indicated by config
+ * param 1.
+ * HTT_DBG_EXT_PEER_STATS_RESET_GET will be
+ * used to get this bit position.
+ * WMI_SERVICE_PER_PEER_HTT_STATS_RESET
+ * indicates that FW supports per peer HTT
+ * stats reset.
+ * [Bit31 : Bit17] reserved
* RESP MSG:
* - htt_peer_stats_t
*/
- HTT_DBG_EXT_STATS_PEER_INFO = 11,
+ HTT_DBG_EXT_STATS_PEER_INFO = 11,
/* HTT_DBG_EXT_STATS_TX_SELFGEN_INFO
* PARAMS:
@@ -158,7 +165,7 @@
* RESP MSG:
* - htt_tx_pdev_selfgen_stats_t
*/
- HTT_DBG_EXT_STATS_TX_SELFGEN_INFO = 12,
+ HTT_DBG_EXT_STATS_TX_SELFGEN_INFO = 12,
/* HTT_DBG_EXT_STATS_TX_MU_HWQ
* PARAMS:
@@ -166,7 +173,7 @@
* RESP MSG:
* - htt_tx_hwq_mu_mimo_stats_t
*/
- HTT_DBG_EXT_STATS_TX_MU_HWQ = 13,
+ HTT_DBG_EXT_STATS_TX_MU_HWQ = 13,
/* HTT_DBG_EXT_STATS_RING_IF_INFO
* PARAMS:
@@ -176,7 +183,7 @@
* RESP MSG:
* - htt_ring_if_stats_t
*/
- HTT_DBG_EXT_STATS_RING_IF_INFO = 14,
+ HTT_DBG_EXT_STATS_RING_IF_INFO = 14,
/* HTT_DBG_EXT_STATS_SRNG_INFO
* PARAMS:
@@ -187,7 +194,7 @@
* RESP MSG:
* - htt_sring_stats_t
*/
- HTT_DBG_EXT_STATS_SRNG_INFO = 15,
+ HTT_DBG_EXT_STATS_SRNG_INFO = 15,
/* HTT_DBG_EXT_STATS_SFM_INFO
* PARAMS:
@@ -195,7 +202,7 @@
* RESP MSG:
* - htt_sfm_stats_t
*/
- HTT_DBG_EXT_STATS_SFM_INFO = 16,
+ HTT_DBG_EXT_STATS_SFM_INFO = 16,
/* HTT_DBG_EXT_STATS_PDEV_TX_MU
* PARAMS:
@@ -203,7 +210,7 @@
* RESP MSG:
* - htt_tx_pdev_mu_mimo_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_TX_MU = 17,
+ HTT_DBG_EXT_STATS_PDEV_TX_MU = 17,
/* HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST
* PARAMS:
@@ -214,18 +221,19 @@
* RESP MSG:
* - htt_active_peer_details_list_t
*/
- HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST = 18,
+ HTT_DBG_EXT_STATS_ACTIVE_PEERS_LIST = 18,
/* HTT_DBG_EXT_STATS_PDEV_CCA_STATS
* PARAMS:
* - config_param0:
- * [Bit0] - 1 sec interval histogram
+ * [Bit0] - Clear bit0 to read 1sec,100ms & cumulative CCA stats.
+ * Set bit0 to 1 to read 1sec interval histogram.
* [Bit1] - 100ms interval histogram
* [Bit3] - Cumulative CCA stats
* RESP MSG:
* - htt_pdev_cca_stats_t
*/
- HTT_DBG_EXT_STATS_PDEV_CCA_STATS = 19,
+ HTT_DBG_EXT_STATS_PDEV_CCA_STATS = 19,
/* HTT_DBG_EXT_STATS_TWT_SESSIONS
* PARAMS:
@@ -234,7 +242,7 @@
* RESP MSG:
* - htt_pdev_twt_sessions_stats_t
*/
- HTT_DBG_EXT_STATS_TWT_SESSIONS = 20,
+ HTT_DBG_EXT_STATS_TWT_SESSIONS = 20,
/* HTT_DBG_EXT_STATS_REO_CNTS
* PARAMS:
@@ -243,175 +251,260 @@
* RESP MSG:
* - htt_soc_reo_resource_stats_t
*/
- HTT_DBG_EXT_STATS_REO_RESOURCE_STATS = 21,
+ HTT_DBG_EXT_STATS_REO_RESOURCE_STATS = 21,
+
+ /* HTT_DBG_EXT_STATS_TX_SOUNDING_INFO
+ * PARAMS:
+ * - config_param0:
+ * [Bit0] vdev_id_set:1
+ * set to 1 if vdev_id is set and vdev stats are requested.
+ * set to 0 if pdev_stats sounding stats are requested.
+ * [Bit8 : Bit1] vdev_id:8
+ * note:0xFF to get all active vdevs based on pdev_mask.
+ * [Bit31 : Bit9] rsvd:22
+ *
+ * RESP MSG:
+ * - htt_tx_sounding_stats_t
+ */
+ HTT_DBG_EXT_STATS_TX_SOUNDING_INFO = 22,
+
+ /* HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS
+ * PARAMS:
+ * - config_param0:
+ * No params
+ * RESP MSG:
+ * - htt_pdev_obss_pd_stats_t
+ */
+ HTT_DBG_EXT_STATS_PDEV_OBSS_PD_STATS = 23,
+
+ /* HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS
+ * PARAMS:
+ * - config_param0:
+ * No params
+ * RESP MSG:
+ * - htt_stats_ring_backpressure_stats_t
+ */
+ HTT_DBG_EXT_STATS_RING_BACKPRESSURE_STATS = 24,
+
+ /* HTT_DBG_EXT_STATS_LATENCY_PROF_STATS
+ * PARAMS:
+ *
+ * RESP MSG:
+ * - htt_soc_latency_prof_t
+ */
+ HTT_DBG_EXT_STATS_LATENCY_PROF_STATS = 25,
+
/* keep this last */
- HTT_DBG_NUM_EXT_STATS = 256,
+ HTT_DBG_NUM_EXT_STATS = 256,
};
+/*
+ * Macros to get/set the bit field in config param[3] that indicates to
+ * clear corresponding per peer stats specified by config param 1
+ */
+#define HTT_DBG_EXT_PEER_STATS_RESET_M 0x00010000
+#define HTT_DBG_EXT_PEER_STATS_RESET_S 16
+
+#define HTT_DBG_EXT_PEER_STATS_RESET_GET(_var) \
+ (((_var) & HTT_DBG_EXT_PEER_STATS_RESET_M) >> \
+ HTT_DBG_EXT_PEER_STATS_RESET_S)
+
+#define HTT_DBG_EXT_PEER_STATS_RESET_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_DBG_EXT_PEER_STATS_RESET, _val); \
+ ((_var) |= ((_val) << HTT_DBG_EXT_PEER_STATS_RESET_S)); \
+ } while (0)
+
typedef enum {
- HTT_STATS_TX_PDEV_CMN_TAG = 0, /* htt_tx_pdev_stats_cmn_tlv */
- HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, /* htt_tx_pdev_stats_urrn_tlv_v */
- HTT_STATS_TX_PDEV_SIFS_TAG = 2, /* htt_tx_pdev_stats_sifs_tlv_v */
- HTT_STATS_TX_PDEV_FLUSH_TAG = 3, /* htt_tx_pdev_stats_flush_tlv_v */
- HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, /* htt_tx_pdev_stats_phy_err_tlv_v */
- HTT_STATS_STRING_TAG = 5, /* htt_stats_string_tlv */
- HTT_STATS_TX_HWQ_CMN_TAG = 6, /* htt_tx_hwq_stats_cmn_tlv */
- HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, /* htt_tx_hwq_difs_latency_stats_tlv_v */
- HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, /* htt_tx_hwq_cmd_result_stats_tlv_v */
- HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, /* htt_tx_hwq_cmd_stall_stats_tlv_v */
- HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, /* htt_tx_hwq_fes_result_stats_tlv_v */
- HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, /* htt_tx_tqm_gen_mpdu_stats_tlv_v */
- HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, /* htt_tx_tqm_list_mpdu_stats_tlv_v */
- HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, /* htt_tx_tqm_list_mpdu_cnt_tlv_v */
- HTT_STATS_TX_TQM_CMN_TAG = 14, /* htt_tx_tqm_cmn_stats_tlv */
- HTT_STATS_TX_TQM_PDEV_TAG = 15, /* htt_tx_tqm_pdev_stats_tlv_v */
- HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, /* htt_tx_tqm_cmdq_status_tlv */
- HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, /* htt_tx_de_eapol_packets_stats_tlv */
- HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, /* htt_tx_de_classify_failed_stats_tlv */
- HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, /* htt_tx_de_classify_stats_tlv */
- HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, /* htt_tx_de_classify_status_stats_tlv */
- HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, /* htt_tx_de_enqueue_packets_stats_tlv */
- HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, /* htt_tx_de_enqueue_discard_stats_tlv */
- HTT_STATS_TX_DE_CMN_TAG = 23, /* htt_tx_de_cmn_stats_tlv */
- HTT_STATS_RING_IF_TAG = 24, /* htt_ring_if_stats_tlv */
- HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, /* htt_tx_pdev_mu_mimo_sch_stats_tlv */
- HTT_STATS_SFM_CMN_TAG = 26, /* htt_sfm_cmn_tlv */
- HTT_STATS_SRING_STATS_TAG = 27, /* htt_sring_stats_tlv */
- HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, /* htt_rx_pdev_fw_stats_tlv */
- HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, /* htt_rx_pdev_fw_ring_mpdu_err_tlv_v */
- HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, /* htt_rx_pdev_fw_mpdu_drop_tlv_v */
- HTT_STATS_RX_SOC_FW_STATS_TAG = 31, /* htt_rx_soc_fw_stats_tlv */
- HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, /* htt_rx_soc_fw_refill_ring_empty_tlv_v */
- HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, /* htt_rx_soc_fw_refill_ring_num_refill_tlv_v */
- HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, /* htt_tx_pdev_rate_stats_tlv */
- HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, /* htt_rx_pdev_rate_stats_tlv */
- HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, /* htt_tx_pdev_stats_sched_per_txq_tlv */
- HTT_STATS_TX_SCHED_CMN_TAG = 37, /* htt_stats_tx_sched_cmn_tlv */
- HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, /* htt_tx_pdev_mu_mimo_mpdu_stats_tlv */
- HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, /* htt_sched_txq_cmd_posted_tlv_v */
- HTT_STATS_RING_IF_CMN_TAG = 40, /* htt_ring_if_cmn_tlv */
- HTT_STATS_SFM_CLIENT_USER_TAG = 41, /* htt_sfm_client_user_tlv_v */
- HTT_STATS_SFM_CLIENT_TAG = 42, /* htt_sfm_client_tlv */
- HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, /* htt_tx_tqm_error_stats_tlv */
- HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, /* htt_sched_txq_cmd_reaped_tlv_v */
- HTT_STATS_SRING_CMN_TAG = 45, /* htt_sring_cmn_tlv */
- HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, /* htt_tx_selfgen_ac_err_stats_tlv */
- HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, /* htt_tx_selfgen_cmn_stats_tlv */
- HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, /* htt_tx_selfgen_ac_stats_tlv */
- HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, /* htt_tx_selfgen_ax_stats_tlv */
- HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, /* htt_tx_selfgen_ax_err_stats_tlv */
- HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, /* htt_tx_hwq_mu_mimo_sch_stats_tlv */
- HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, /* htt_tx_hwq_mu_mimo_mpdu_stats_tlv */
- HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, /* htt_tx_hwq_mu_mimo_cmn_stats_tlv */
- HTT_STATS_HW_INTR_MISC_TAG = 54, /* htt_hw_stats_intr_misc_tlv */
- HTT_STATS_HW_WD_TIMEOUT_TAG = 55, /* htt_hw_stats_wd_timeout_tlv */
- HTT_STATS_HW_PDEV_ERRS_TAG = 56, /* htt_hw_stats_pdev_errs_tlv */
- HTT_STATS_COUNTER_NAME_TAG = 57, /* htt_counter_tlv */
- HTT_STATS_TX_TID_DETAILS_TAG = 58, /* htt_tx_tid_stats_tlv */
- HTT_STATS_RX_TID_DETAILS_TAG = 59, /* htt_rx_tid_stats_tlv */
- HTT_STATS_PEER_STATS_CMN_TAG = 60, /* htt_peer_stats_cmn_tlv */
- HTT_STATS_PEER_DETAILS_TAG = 61, /* htt_peer_details_tlv */
- HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, /* htt_tx_peer_rate_stats_tlv */
- HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, /* htt_rx_peer_rate_stats_tlv */
- HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, /* htt_msdu_flow_stats_tlv */
- HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, /* htt_tx_de_compl_stats_tlv */
- HTT_STATS_WHAL_TX_TAG = 66, /* htt_hw_stats_whal_tx_tlv */
- HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, /* htt_tx_pdev_stats_sifs_hist_tlv_v */
- HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, /* htt_rx_pdev_fw_stats_phy_err_tlv */
- HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, /* htt_tx_tid_stats_v1_tlv */
- HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, /* htt_pdev_cca_stats_hist_tlv (for 1 sec interval stats) */
- HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, /* htt_pdev_cca_stats_hist_tlv (for 100 msec interval stats) */
- HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, /* htt_pdev_stats_cca_stats_tlv */
- HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, /* htt_pdev_stats_cca_counters_tlv */
- HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, /* htt_tx_pdev_mpdu_stats_tlv */
- HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, /* htt_pdev_stats_twt_sessions_tlv */
- HTT_STATS_PDEV_TWT_SESSION_TAG = 76, /* htt_pdev_stats_twt_session_tlv */
- HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, /* htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v */
- HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, /* htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v */
- HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, /* htt_rx_reo_debug_stats_tlv_v */
+ HTT_STATS_TX_PDEV_CMN_TAG = 0, /* htt_tx_pdev_stats_cmn_tlv */
+ HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, /* htt_tx_pdev_stats_urrn_tlv_v */
+ HTT_STATS_TX_PDEV_SIFS_TAG = 2, /* htt_tx_pdev_stats_sifs_tlv_v */
+ HTT_STATS_TX_PDEV_FLUSH_TAG = 3, /* htt_tx_pdev_stats_flush_tlv_v */
+ HTT_STATS_TX_PDEV_PHY_ERR_TAG = 4, /* htt_tx_pdev_stats_phy_err_tlv_v */
+ HTT_STATS_STRING_TAG = 5, /* htt_stats_string_tlv */
+ HTT_STATS_TX_HWQ_CMN_TAG = 6, /* htt_tx_hwq_stats_cmn_tlv */
+ HTT_STATS_TX_HWQ_DIFS_LATENCY_TAG = 7, /* htt_tx_hwq_difs_latency_stats_tlv_v */
+ HTT_STATS_TX_HWQ_CMD_RESULT_TAG = 8, /* htt_tx_hwq_cmd_result_stats_tlv_v */
+ HTT_STATS_TX_HWQ_CMD_STALL_TAG = 9, /* htt_tx_hwq_cmd_stall_stats_tlv_v */
+ HTT_STATS_TX_HWQ_FES_STATUS_TAG = 10, /* htt_tx_hwq_fes_result_stats_tlv_v */
+ HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, /* htt_tx_tqm_gen_mpdu_stats_tlv_v */
+ HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, /* htt_tx_tqm_list_mpdu_stats_tlv_v */
+ HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, /* htt_tx_tqm_list_mpdu_cnt_tlv_v */
+ HTT_STATS_TX_TQM_CMN_TAG = 14, /* htt_tx_tqm_cmn_stats_tlv */
+ HTT_STATS_TX_TQM_PDEV_TAG = 15, /* htt_tx_tqm_pdev_stats_tlv_v */
+ HTT_STATS_TX_TQM_CMDQ_STATUS_TAG = 16, /* htt_tx_tqm_cmdq_status_tlv */
+ HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, /* htt_tx_de_eapol_packets_stats_tlv */
+ HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, /* htt_tx_de_classify_failed_stats_tlv */
+ HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, /* htt_tx_de_classify_stats_tlv */
+ HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, /* htt_tx_de_classify_status_stats_tlv */
+ HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, /* htt_tx_de_enqueue_packets_stats_tlv */
+ HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, /* htt_tx_de_enqueue_discard_stats_tlv */
+ HTT_STATS_TX_DE_CMN_TAG = 23, /* htt_tx_de_cmn_stats_tlv */
+ HTT_STATS_RING_IF_TAG = 24, /* htt_ring_if_stats_tlv */
+ HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, /* htt_tx_pdev_mu_mimo_sch_stats_tlv */
+ HTT_STATS_SFM_CMN_TAG = 26, /* htt_sfm_cmn_tlv */
+ HTT_STATS_SRING_STATS_TAG = 27, /* htt_sring_stats_tlv */
+ HTT_STATS_RX_PDEV_FW_STATS_TAG = 28, /* htt_rx_pdev_fw_stats_tlv */
+ HTT_STATS_RX_PDEV_FW_RING_MPDU_ERR_TAG = 29, /* htt_rx_pdev_fw_ring_mpdu_err_tlv_v */
+ HTT_STATS_RX_PDEV_FW_MPDU_DROP_TAG = 30, /* htt_rx_pdev_fw_mpdu_drop_tlv_v */
+ HTT_STATS_RX_SOC_FW_STATS_TAG = 31, /* htt_rx_soc_fw_stats_tlv */
+ HTT_STATS_RX_SOC_FW_REFILL_RING_EMPTY_TAG = 32, /* htt_rx_soc_fw_refill_ring_empty_tlv_v */
+ HTT_STATS_RX_SOC_FW_REFILL_RING_NUM_REFILL_TAG = 33, /* htt_rx_soc_fw_refill_ring_num_refill_tlv_v */
+ HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, /* htt_tx_pdev_rate_stats_tlv */
+ HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, /* htt_rx_pdev_rate_stats_tlv */
+ HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, /* htt_tx_pdev_stats_sched_per_txq_tlv */
+ HTT_STATS_TX_SCHED_CMN_TAG = 37, /* htt_stats_tx_sched_cmn_tlv */
+ HTT_STATS_TX_PDEV_MUMIMO_MPDU_STATS_TAG = 38, /* htt_tx_pdev_mu_mimo_mpdu_stats_tlv */
+ HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, /* htt_sched_txq_cmd_posted_tlv_v */
+ HTT_STATS_RING_IF_CMN_TAG = 40, /* htt_ring_if_cmn_tlv */
+ HTT_STATS_SFM_CLIENT_USER_TAG = 41, /* htt_sfm_client_user_tlv_v */
+ HTT_STATS_SFM_CLIENT_TAG = 42, /* htt_sfm_client_tlv */
+ HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, /* htt_tx_tqm_error_stats_tlv */
+ HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, /* htt_sched_txq_cmd_reaped_tlv_v */
+ HTT_STATS_SRING_CMN_TAG = 45, /* htt_sring_cmn_tlv */
+ HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, /* htt_tx_selfgen_ac_err_stats_tlv */
+ HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, /* htt_tx_selfgen_cmn_stats_tlv */
+ HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, /* htt_tx_selfgen_ac_stats_tlv */
+ HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, /* htt_tx_selfgen_ax_stats_tlv */
+ HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, /* htt_tx_selfgen_ax_err_stats_tlv */
+ HTT_STATS_TX_HWQ_MUMIMO_SCH_STATS_TAG = 51, /* htt_tx_hwq_mu_mimo_sch_stats_tlv */
+ HTT_STATS_TX_HWQ_MUMIMO_MPDU_STATS_TAG = 52, /* htt_tx_hwq_mu_mimo_mpdu_stats_tlv */
+ HTT_STATS_TX_HWQ_MUMIMO_CMN_STATS_TAG = 53, /* htt_tx_hwq_mu_mimo_cmn_stats_tlv */
+ HTT_STATS_HW_INTR_MISC_TAG = 54, /* htt_hw_stats_intr_misc_tlv */
+ HTT_STATS_HW_WD_TIMEOUT_TAG = 55, /* htt_hw_stats_wd_timeout_tlv */
+ HTT_STATS_HW_PDEV_ERRS_TAG = 56, /* htt_hw_stats_pdev_errs_tlv */
+ HTT_STATS_COUNTER_NAME_TAG = 57, /* htt_counter_tlv */
+ HTT_STATS_TX_TID_DETAILS_TAG = 58, /* htt_tx_tid_stats_tlv */
+ HTT_STATS_RX_TID_DETAILS_TAG = 59, /* htt_rx_tid_stats_tlv */
+ HTT_STATS_PEER_STATS_CMN_TAG = 60, /* htt_peer_stats_cmn_tlv */
+ HTT_STATS_PEER_DETAILS_TAG = 61, /* htt_peer_details_tlv */
+ HTT_STATS_PEER_TX_RATE_STATS_TAG = 62, /* htt_tx_peer_rate_stats_tlv */
+ HTT_STATS_PEER_RX_RATE_STATS_TAG = 63, /* htt_rx_peer_rate_stats_tlv */
+ HTT_STATS_PEER_MSDU_FLOWQ_TAG = 64, /* htt_msdu_flow_stats_tlv */
+ HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, /* htt_tx_de_compl_stats_tlv */
+ HTT_STATS_WHAL_TX_TAG = 66, /* htt_hw_stats_whal_tx_tlv */
+ HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, /* htt_tx_pdev_stats_sifs_hist_tlv_v */
+ HTT_STATS_RX_PDEV_FW_STATS_PHY_ERR_TAG = 68, /* htt_rx_pdev_fw_stats_phy_err_tlv */
+ HTT_STATS_TX_TID_DETAILS_V1_TAG = 69, /* htt_tx_tid_stats_v1_tlv */
+ HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, /* htt_pdev_cca_stats_hist_tlv (for 1 sec interval stats) */
+ HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, /* htt_pdev_cca_stats_hist_tlv (for 100 msec interval stats) */
+ HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, /* htt_pdev_stats_cca_stats_tlv */
+ HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, /* htt_pdev_stats_cca_counters_tlv */
+ HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, /* htt_tx_pdev_mpdu_stats_tlv */
+ HTT_STATS_PDEV_TWT_SESSIONS_TAG = 75, /* htt_pdev_stats_twt_sessions_tlv */
+ HTT_STATS_PDEV_TWT_SESSION_TAG = 76, /* htt_pdev_stats_twt_session_tlv */
+ HTT_STATS_RX_REFILL_RXDMA_ERR_TAG = 77, /* htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v */
+ HTT_STATS_RX_REFILL_REO_ERR_TAG = 78, /* htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v */
+ HTT_STATS_RX_REO_RESOURCE_STATS_TAG = 79, /* htt_rx_reo_debug_stats_tlv_v */
+ HTT_STATS_TX_SOUNDING_STATS_TAG = 80, /* htt_tx_sounding_stats_tlv */
+ HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG = 81, /* htt_tx_pdev_stats_tx_ppdu_stats_tlv_v */
+ HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG = 82, /* htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v */
+ HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG = 83, /* htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v */
+ HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG = 84, /* htt_tx_hwq_txop_used_cnt_hist_tlv_v */
+ HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG = 85, /* htt_tx_de_fw2wbm_ring_full_hist_tlv */
+ HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, /* htt_sched_txq_sched_order_su_tlv */
+ HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, /* htt_sched_txq_sched_eligibility_tlv */
+ HTT_STATS_PDEV_OBSS_PD_TAG = 88, /* htt_pdev_obss_pd_stats_tlv */
+ HTT_STATS_HW_WAR_TAG = 89, /* htt_hw_war_stats_tlv */
+ HTT_STATS_RING_BACKPRESSURE_STATS_TAG = 90, /* htt_ring_backpressure_stats_tlv */
+ HTT_STATS_LATENCY_PROF_STATS_TAG = 91, /* htt_latency_prof_stats_tlv */
+ HTT_STATS_LATENCY_CTX_TAG = 92, /* htt_latency_prof_ctx_tlv */
+ HTT_STATS_LATENCY_CNT_TAG = 93, /* htt_latency_prof_cnt_tlv */
HTT_STATS_MAX_TAG,
} htt_tlv_tag_t;
-
-#define HTT_STATS_TLV_TAG_M 0x00000fff
-#define HTT_STATS_TLV_TAG_S 0
-#define HTT_STATS_TLV_LENGTH_M 0x00fff000
-#define HTT_STATS_TLV_LENGTH_S 12
+#define HTT_STATS_TLV_TAG_M 0x00000fff
+#define HTT_STATS_TLV_TAG_S 0
+#define HTT_STATS_TLV_LENGTH_M 0x00fff000
+#define HTT_STATS_TLV_LENGTH_S 12
#define HTT_STATS_TLV_TAG_GET(_var) \
(((_var) & HTT_STATS_TLV_TAG_M) >> \
- HTT_STATS_TLV_TAG_S)
+ HTT_STATS_TLV_TAG_S)
#define HTT_STATS_TLV_TAG_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_STATS_TLV_TAG, _val); \
- ((_var) |= ((_val) << HTT_STATS_TLV_TAG_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_STATS_TLV_TAG, _val); \
+ ((_var) |= ((_val) << HTT_STATS_TLV_TAG_S)); \
+ } while (0)
#define HTT_STATS_TLV_LENGTH_GET(_var) \
(((_var) & HTT_STATS_TLV_LENGTH_M) >> \
- HTT_STATS_TLV_LENGTH_S)
+ HTT_STATS_TLV_LENGTH_S)
#define HTT_STATS_TLV_LENGTH_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_STATS_TLV_LENGTH, _val); \
- ((_var) |= ((_val) << HTT_STATS_TLV_LENGTH_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_STATS_TLV_LENGTH, _val); \
+ ((_var) |= ((_val) << HTT_STATS_TLV_LENGTH_S)); \
+ } while (0)
typedef struct {
- /* BIT [11 : 0] :- tag
- * BIT [23 : 12] :- length
- * BIT [31 : 24] :- reserved
- */
- A_UINT32 tag__length;
+ union {
+ /* BIT [11 : 0] :- tag
+ * BIT [23 : 12] :- length
+ * BIT [31 : 24] :- reserved
+ */
+ A_UINT32 tag__length;
+ /*
+ * The following struct is not endian-portable.
+ * It is suitable for use within the target, which is known to be
+ * little-endian.
+ * The host should use the above endian-portable macros to access
+ * the tag and length bitfields in an endian-neutral manner.
+ */
+ struct {
+ A_UINT32 tag : 12, /* BIT [11 : 0] */
+ length : 12, /* BIT [23 : 12] */
+ reserved : 8; /* BIT [31 : 24] */
+ };
+ };
} htt_tlv_hdr_t;
-#define HTT_STATS_MAX_STRING_SZ32 4
-#define HTT_STATS_MACID_INVALID 0xff
-#define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10
-#define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13
-#define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5
-#define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10
+#define HTT_STATS_MAX_STRING_SZ32 4
+#define HTT_STATS_MACID_INVALID 0xff
+#define HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS 10
+#define HTT_TX_HWQ_MAX_CMD_RESULT_STATS 13
+#define HTT_TX_HWQ_MAX_CMD_STALL_STATS 5
+#define HTT_TX_HWQ_MAX_FES_RESULT_STATS 10
typedef enum {
- HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,
+ HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0,
HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1,
- HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2,
- HTT_TX_PDEV_MAX_URRN_STATS = 3,
+ HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2,
+ HTT_TX_PDEV_MAX_URRN_STATS = 3,
} htt_tx_pdev_underrun_enum;
-#define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 71
-#define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9
-#define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10
-#define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18
-#define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4
+#define HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 71
+#define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9
+#define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10
+#define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18
+#define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4
+#define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20
-#define HTT_RX_STATS_REFILL_MAX_RING 4
-#define HTT_RX_STATS_RXDMA_MAX_ERR 16
-#define HTT_RX_STATS_FW_DROP_REASON_MAX 16
+#define HTT_RX_STATS_REFILL_MAX_RING 4
+#define HTT_RX_STATS_RXDMA_MAX_ERR 16
+#define HTT_RX_STATS_FW_DROP_REASON_MAX 16
/* Bytes stored in little endian order */
/* Length should be multiple of DWORD */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 data[1]; /* Can be variable length */
+ A_UINT32 data[1]; /* Can be variable length */
} htt_stats_string_tlv;
-
-#define HTT_TX_PDEV_STATS_CMN_MAC_ID_M 0x000000ff
-#define HTT_TX_PDEV_STATS_CMN_MAC_ID_S 0
+#define HTT_TX_PDEV_STATS_CMN_MAC_ID_M 0x000000ff
+#define HTT_TX_PDEV_STATS_CMN_MAC_ID_S 0
#define HTT_TX_PDEV_STATS_CMN_MAC_ID_GET(_var) \
(((_var) & HTT_TX_PDEV_STATS_CMN_MAC_ID_M) >> \
- HTT_TX_PDEV_STATS_CMN_MAC_ID_S)
+ HTT_TX_PDEV_STATS_CMN_MAC_ID_S)
#define HTT_TX_PDEV_STATS_CMN_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_CMN_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_PDEV_STATS_CMN_MAC_ID_S)); \
- } while (0)
-
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_CMN_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_PDEV_STATS_CMN_MAC_ID_S)); \
+ } while (0)
/* == TX PDEV STATS == */
typedef struct {
@@ -447,7 +540,7 @@
A_UINT32 illgl_rate_phy_err;
/* wal pdev continous xretry */
A_UINT32 cont_xretry;
- /* wal pdev continous xretry */
+ /* wal pdev tx timeout */
A_UINT32 tx_timeout;
/* wal pdev resets */
A_UINT32 pdev_resets;
@@ -519,43 +612,101 @@
* (acked, no ack, flush, TTL, etc)
*/
A_UINT32 local_data_freed;
+
+ /* Num MPDUs tried by SW */
+ A_UINT32 mpdu_tried;
+ /* Num of waiting seq posted in isr completion handler */
+ A_UINT32 isr_wait_seq_posted;
+
+ A_UINT32 tx_active_dur_us_low;
+ A_UINT32 tx_active_dur_us_high;
+ /* Number of MPDUs dropped after max retries */
+ A_UINT32 remove_mpdus_max_retries;
+ /* Num HTT cookies dispatched */
+ A_UINT32 comp_delivered;
+ /* successful ppdu transmissions */
+ A_UINT32 ppdu_ok;
+ /* Scheduler self triggers */
+ A_UINT32 self_triggers;
+ /* FES duration of last tx data PPDU in us (sch_eval_end - ppdu_start) */
+ A_UINT32 tx_time_dur_data;
+ /* Num of times sequence terminated due to ppdu duration < burst limit */
+ A_UINT32 seq_qdepth_repost_stop;
+ /* Num of times MU sequence terminated due to MSDUs reaching threshold */
+ A_UINT32 mu_seq_min_msdu_repost_stop;
+ /* Num of times SU sequence terminated due to MSDUs reaching threshold */
+ A_UINT32 seq_min_msdu_repost_stop;
+ /* Num of times sequence terminated due to no TXOP available */
+ A_UINT32 seq_txop_repost_stop;
+ /* Num of times the next sequence got cancelled */
+ A_UINT32 next_seq_cancel;
+ /* Num of times fes offset was misaligned */
+ A_UINT32 fes_offsets_err_cnt;
} htt_tx_pdev_stats_cmn_tlv;
#define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 urrn_stats[1]; /* HTT_TX_PDEV_MAX_URRN_STATS */
+ A_UINT32 urrn_stats[1]; /* HTT_TX_PDEV_MAX_URRN_STATS */
} htt_tx_pdev_stats_urrn_tlv_v;
#define HTT_TX_PDEV_STATS_FLUSH_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */
+ A_UINT32 flush_errs[1]; /* HTT_TX_PDEV_MAX_FLUSH_REASON_STATS */
} htt_tx_pdev_stats_flush_tlv_v;
#define HTT_TX_PDEV_STATS_SIFS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 sifs_status[1]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */
+ A_UINT32 sifs_status[1]; /* HTT_TX_PDEV_MAX_SIFS_BURST_STATS */
} htt_tx_pdev_stats_sifs_tlv_v;
#define HTT_TX_PDEV_STATS_PHY_ERR_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 phy_errs[1]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */
+ A_UINT32 phy_errs[1]; /* HTT_TX_PDEV_MAX_PHY_ERR_STATS */
} htt_tx_pdev_stats_phy_err_tlv_v;
#define HTT_TX_PDEV_STATS_SIFS_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 sifs_hist_status[1]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */
+ A_UINT32 sifs_hist_status[1]; /* HTT_TX_PDEV_SIFS_BURST_HIST_STATS */
} htt_tx_pdev_stats_sifs_hist_tlv_v;
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 num_data_ppdus_legacy_su;
+ A_UINT32 num_data_ppdus_ac_su;
+ A_UINT32 num_data_ppdus_ax_su;
+ A_UINT32 num_data_ppdus_ac_su_txbf;
+ A_UINT32 num_data_ppdus_ax_su_txbf;
+} htt_tx_pdev_stats_tx_ppdu_stats_tlv_v;
+
+#define HTT_TX_PDEV_STATS_TRIED_MPDU_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
+/* NOTE: Variable length TLV, use length spec to infer array size .
+ *
+ * Tried_mpdu_cnt_hist is the histogram of MPDUs tries per HWQ.
+ * The tries here is the count of the MPDUS within a PPDU that the
+ * HW had attempted to transmit on air, for the HWSCH Schedule
+ * command submitted by FW.It is not the retry attempts.
+ * The histogram bins are 0-29, 30-59, 60-89 and so on. The are
+ * 10 bins in this histogram. They are defined in FW using the
+ * following macros
+ * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9
+ * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30
+ *
+ */
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 hist_bin_size;
+ A_UINT32 tried_mpdu_cnt_hist[1]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */
+} htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v;
/* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_TX
* TLV_TAGS:
@@ -565,18 +716,22 @@
* - HTT_STATS_TX_PDEV_FLUSH_TAG
* - HTT_STATS_TX_PDEV_PHY_ERR_TAG
* - HTT_STATS_TX_PDEV_SIFS_HIST_TAG
+ * - HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG
+ * - HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG
*/
/* NOTE:
* This structure is for documentation, and cannot be safely used directly.
* Instead, use the constituent TLV structures to fill/parse.
*/
typedef struct _htt_tx_pdev_stats {
- htt_tx_pdev_stats_cmn_tlv cmn_tlv;
- htt_tx_pdev_stats_urrn_tlv_v underrun_tlv;
- htt_tx_pdev_stats_sifs_tlv_v sifs_tlv;
- htt_tx_pdev_stats_flush_tlv_v flush_tlv;
- htt_tx_pdev_stats_phy_err_tlv_v phy_err_tlv;
- htt_tx_pdev_stats_sifs_hist_tlv_v sifs_hist_tlv;
+ htt_tx_pdev_stats_cmn_tlv cmn_tlv;
+ htt_tx_pdev_stats_urrn_tlv_v underrun_tlv;
+ htt_tx_pdev_stats_sifs_tlv_v sifs_tlv;
+ htt_tx_pdev_stats_flush_tlv_v flush_tlv;
+ htt_tx_pdev_stats_phy_err_tlv_v phy_err_tlv;
+ htt_tx_pdev_stats_sifs_hist_tlv_v sifs_hist_tlv;
+ htt_tx_pdev_stats_tx_ppdu_stats_tlv_v tx_su_tlv;
+ htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v tried_mpdu_cnt_hist_tlv;
} htt_tx_pdev_stats_t;
/* == SOC ERROR STATS == */
@@ -586,7 +741,7 @@
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Stored as little endian */
- A_UINT8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN];
+ A_UINT8 hw_intr_name[HTT_STATS_MAX_HW_INTR_NAME_LEN];
A_UINT32 mask;
A_UINT32 count;
} htt_hw_stats_intr_misc_tlv;
@@ -595,24 +750,22 @@
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Stored as little endian */
- A_UINT8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN];
+ A_UINT8 hw_module_name[HTT_STATS_MAX_HW_MODULE_NAME_LEN];
A_UINT32 count;
} htt_hw_stats_wd_timeout_tlv;
-
-#define HTT_HW_STATS_PDEV_ERRS_MAC_ID_M 0x000000ff
-#define HTT_HW_STATS_PDEV_ERRS_MAC_ID_S 0
+#define HTT_HW_STATS_PDEV_ERRS_MAC_ID_M 0x000000ff
+#define HTT_HW_STATS_PDEV_ERRS_MAC_ID_S 0
#define HTT_HW_STATS_PDEV_ERRS_MAC_ID_GET(_var) \
(((_var) & HTT_HW_STATS_PDEV_ERRS_MAC_ID_M) >> \
- HTT_HW_STATS_PDEV_ERRS_MAC_ID_S)
+ HTT_HW_STATS_PDEV_ERRS_MAC_ID_S)
#define HTT_HW_STATS_PDEV_ERRS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_HW_STATS_PDEV_ERRS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_HW_STATS_PDEV_ERRS_MAC_ID_S)); \
- } while (0)
-
+ do { \
+ HTT_CHECK_SET_VAL(HTT_HW_STATS_PDEV_ERRS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_HW_STATS_PDEV_ERRS_MAC_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -620,17 +773,45 @@
/* BIT [ 7 : 0] :- mac_id
* BIT [31 : 8] :- reserved
*/
- A_UINT32 mac_id__word;
- A_UINT32 tx_abort;
- A_UINT32 tx_abort_fail_count;
- A_UINT32 rx_abort;
- A_UINT32 rx_abort_fail_count;
- A_UINT32 warm_reset;
- A_UINT32 cold_reset;
- A_UINT32 tx_flush;
- A_UINT32 tx_glb_reset;
- A_UINT32 tx_txq_reset;
- A_UINT32 rx_timeout_reset;
+ A_UINT32 mac_id__word;
+ A_UINT32 tx_abort;
+ A_UINT32 tx_abort_fail_count;
+ A_UINT32 rx_abort;
+ A_UINT32 rx_abort_fail_count;
+ A_UINT32 warm_reset;
+ A_UINT32 cold_reset;
+ A_UINT32 tx_flush;
+ A_UINT32 tx_glb_reset;
+ A_UINT32 tx_txq_reset;
+ A_UINT32 rx_timeout_reset;
+ A_UINT32 mac_cold_reset_restore_cal;
+ A_UINT32 mac_cold_reset;
+ A_UINT32 mac_warm_reset;
+ A_UINT32 mac_only_reset;
+ A_UINT32 phy_warm_reset;
+ A_UINT32 phy_warm_reset_ucode_trig;
+ A_UINT32 mac_warm_reset_restore_cal;
+ A_UINT32 mac_sfm_reset;
+ A_UINT32 phy_warm_reset_m3_ssr;
+ A_UINT32 phy_warm_reset_reason_phy_m3;
+ A_UINT32 phy_warm_reset_reason_tx_hw_stuck;
+ A_UINT32 phy_warm_reset_reason_num_cca_rx_frame_stuck;
+ A_UINT32 phy_warm_reset_reason_wal_rx_recovery_rst_rx_busy;
+ A_UINT32 phy_warm_reset_reason_wal_rx_recovery_rst_mac_hang;
+ A_UINT32 phy_warm_reset_reason_mac_reset_converted_phy_reset;
+
+ A_UINT32 wal_rx_recovery_rst_mac_hang_count;
+ A_UINT32 wal_rx_recovery_rst_known_sig_count;
+ A_UINT32 wal_rx_recovery_rst_no_rx_count;
+ A_UINT32 wal_rx_recovery_rst_no_rx_consecutive_count;
+ A_UINT32 wal_rx_recovery_rst_rx_busy_count;
+ A_UINT32 wal_rx_recovery_rst_phy_mac_hang_count;
+ A_UINT32 rx_flush_cnt; /* Num rx flush issued */
+ A_UINT32 phy_warm_reset_reason_tx_lifetime_expiry_cca_stuck;
+ A_UINT32 phy_warm_reset_reason_tx_consecutive_flush9_war;
+ A_UINT32 phy_warm_reset_reason_tx_hwsch_reset_war;
+ A_UINT32 phy_warm_reset_reason_hwsch_wdog_or_cca_wdog_war;
+ A_UINT32 fw_rx_rings_reset;
} htt_hw_stats_pdev_errs_tlv;
typedef struct {
@@ -653,65 +834,92 @@
A_UINT32 sch_rx_sifs_resp_trigger;
} htt_hw_stats_whal_tx_tlv;
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ /* BIT [ 7 : 0] :- mac_id
+ * BIT [31 : 8] :- reserved
+ */
+ union {
+ struct {
+ A_UINT32 mac_id: 8,
+ reserved: 24;
+ };
+ A_UINT32 mac_id__word;
+ };
+
+ /*
+ * hw_wars is a variable-length array, with each element counting
+ * the number of occurrences of the corresponding type of HW WAR.
+ * That is, hw_wars[0] indicates how many times HW WAR 0 occurred,
+ * hw_wars[1] indicates how many times HW WAR 1 occurred, etc.
+ * The target has an internal HW WAR mapping that it uses to keep
+ * track of which HW WAR is WAR 0, which HW WAR is WAR 1, etc.
+ */
+ A_UINT32 hw_wars[1/*or more*/];
+} htt_hw_war_stats_tlv;
+
/* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_ERROR
* TLV_TAGS:
* - HTT_STATS_HW_PDEV_ERRS_TAG
* - HTT_STATS_HW_INTR_MISC_TAG (multiple)
* - HTT_STATS_HW_WD_TIMEOUT_TAG (multiple)
* - HTT_STATS_WHAL_TX_TAG
+ * - HTT_STATS_HW_WAR_TAG
*/
/* NOTE:
* This structure is for documentation, and cannot be safely used directly.
* Instead, use the constituent TLV structures to fill/parse.
*/
typedef struct _htt_pdev_err_stats {
- htt_hw_stats_pdev_errs_tlv pdev_errs;
- htt_hw_stats_intr_misc_tlv misc_stats[1];
+ htt_hw_stats_pdev_errs_tlv pdev_errs;
+ htt_hw_stats_intr_misc_tlv misc_stats[1];
htt_hw_stats_wd_timeout_tlv wd_timeout[1];
- htt_hw_stats_whal_tx_tlv whal_tx_stats;
+ htt_hw_stats_whal_tx_tlv whal_tx_stats;
+ htt_hw_war_stats_tlv hw_war;
} htt_hw_err_stats_t;
/* ============ PEER STATS ============ */
-#define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M 0x0000ffff
-#define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S 0
-#define HTT_MSDU_FLOW_STATS_TID_NUM_M 0x000f0000
-#define HTT_MSDU_FLOW_STATS_TID_NUM_S 16
-#define HTT_MSDU_FLOW_STATS_DROP_M 0x00100000
-#define HTT_MSDU_FLOW_STATS_DROP_S 20
+#define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M 0x0000ffff
+#define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S 0
+#define HTT_MSDU_FLOW_STATS_TID_NUM_M 0x000f0000
+#define HTT_MSDU_FLOW_STATS_TID_NUM_S 16
+#define HTT_MSDU_FLOW_STATS_DROP_M 0x00100000
+#define HTT_MSDU_FLOW_STATS_DROP_S 20
#define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_GET(_var) \
(((_var) & HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_M) >> \
- HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S)
+ HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S)
#define HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_TX_FLOW_NUM, _val); \
- ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_TX_FLOW_NUM, _val); \
+ ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_TX_FLOW_NUM_S)); \
+ } while (0)
#define HTT_MSDU_FLOW_STATS_TID_NUM_GET(_var) \
(((_var) & HTT_MSDU_FLOW_STATS_TID_NUM_M) >> \
- HTT_MSDU_FLOW_STATS_TID_NUM_S)
+ HTT_MSDU_FLOW_STATS_TID_NUM_S)
#define HTT_MSDU_FLOW_STATS_TID_NUM_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_TID_NUM, _val); \
- ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_TID_NUM_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_TID_NUM, _val); \
+ ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_TID_NUM_S)); \
+ } while (0)
#define HTT_MSDU_FLOW_STATS_DROP_GET(_var) \
(((_var) & HTT_MSDU_FLOW_STATS_DROP_M) >> \
- HTT_MSDU_FLOW_STATS_DROP_S)
+ HTT_MSDU_FLOW_STATS_DROP_S)
#define HTT_MSDU_FLOW_STATS_DROP_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_DROP, _val); \
- ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_DROP_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_MSDU_FLOW_STATS_DROP, _val); \
+ ((_var) |= ((_val) << HTT_MSDU_FLOW_STATS_DROP_S)); \
+ } while (0)
typedef struct _htt_msdu_flow_stats_tlv {
htt_tlv_hdr_t tlv_hdr;
+
A_UINT32 last_update_timestamp;
A_UINT32 last_add_timestamp;
A_UINT32 last_remove_timestamp;
@@ -736,65 +944,63 @@
#define MAX_HTT_TID_NAME 8
/* DWORD sw_peer_id__tid_num */
-#define HTT_TX_TID_STATS_SW_PEER_ID_M 0x0000ffff
-#define HTT_TX_TID_STATS_SW_PEER_ID_S 0
-#define HTT_TX_TID_STATS_TID_NUM_M 0xffff0000
-#define HTT_TX_TID_STATS_TID_NUM_S 16
+#define HTT_TX_TID_STATS_SW_PEER_ID_M 0x0000ffff
+#define HTT_TX_TID_STATS_SW_PEER_ID_S 0
+#define HTT_TX_TID_STATS_TID_NUM_M 0xffff0000
+#define HTT_TX_TID_STATS_TID_NUM_S 16
#define HTT_TX_TID_STATS_SW_PEER_ID_GET(_var) \
(((_var) & HTT_TX_TID_STATS_SW_PEER_ID_M) >> \
- HTT_TX_TID_STATS_SW_PEER_ID_S)
+ HTT_TX_TID_STATS_SW_PEER_ID_S)
#define HTT_TX_TID_STATS_SW_PEER_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_SW_PEER_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_TID_STATS_SW_PEER_ID_S)); \
- } while (0)
-
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_SW_PEER_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_TID_STATS_SW_PEER_ID_S)); \
+ } while (0)
#define HTT_TX_TID_STATS_TID_NUM_GET(_var) \
(((_var) & HTT_TX_TID_STATS_TID_NUM_M) >> \
- HTT_TX_TID_STATS_TID_NUM_S)
+ HTT_TX_TID_STATS_TID_NUM_S)
#define HTT_TX_TID_STATS_TID_NUM_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_TID_NUM, _val); \
- ((_var) |= ((_val) << HTT_TX_TID_STATS_TID_NUM_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_TID_NUM, _val); \
+ ((_var) |= ((_val) << HTT_TX_TID_STATS_TID_NUM_S)); \
+ } while (0)
/* DWORD num_sched_pending__num_ppdu_in_hwq */
-#define HTT_TX_TID_STATS_NUM_SCHED_PENDING_M 0x000000ff
-#define HTT_TX_TID_STATS_NUM_SCHED_PENDING_S 0
-#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M 0x0000ff00
-#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S 8
+#define HTT_TX_TID_STATS_NUM_SCHED_PENDING_M 0x000000ff
+#define HTT_TX_TID_STATS_NUM_SCHED_PENDING_S 0
+#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M 0x0000ff00
+#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S 8
#define HTT_TX_TID_STATS_NUM_SCHED_PENDING_GET(_var) \
(((_var) & HTT_TX_TID_STATS_NUM_SCHED_PENDING_M) >> \
- HTT_TX_TID_STATS_NUM_SCHED_PENDING_S)
+ HTT_TX_TID_STATS_NUM_SCHED_PENDING_S)
#define HTT_TX_TID_STATS_NUM_SCHED_PENDING_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_SCHED_PENDING, _val); \
- ((_var) |= ((_val) << HTT_TX_TID_STATS_NUM_SCHED_PENDING_S)); \
- } while (0)
-
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_SCHED_PENDING, _val); \
+ ((_var) |= ((_val) << HTT_TX_TID_STATS_NUM_SCHED_PENDING_S)); \
+ } while (0)
#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_GET(_var) \
(((_var) & HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_M) >> \
- HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S)
+ HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S)
#define HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ, _val); \
- ((_var) |= ((_val) << HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S)); \
- } while (0)
-
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ, _val); \
+ ((_var) |= ((_val) << HTT_TX_TID_STATS_NUM_PPDU_IN_HWQ_S)); \
+ } while (0)
/* Tidq stats */
typedef struct _htt_tx_tid_stats_tlv {
htt_tlv_hdr_t tlv_hdr;
+
/* Stored as little endian */
- A_UINT8 tid_name[MAX_HTT_TID_NAME];
+ A_UINT8 tid_name[MAX_HTT_TID_NAME];
/* BIT [15 : 0] :- sw_peer_id
* BIT [31 : 16] :- tid_num
*/
@@ -826,7 +1032,7 @@
typedef struct _htt_tx_tid_stats_v1_tlv {
htt_tlv_hdr_t tlv_hdr;
/* Stored as little endian */
- A_UINT8 tid_name[MAX_HTT_TID_NAME];
+ A_UINT8 tid_name[MAX_HTT_TID_NAME];
/* BIT [15 : 0] :- sw_peer_id
* BIT [31 : 16] :- tid_num
*/
@@ -859,34 +1065,34 @@
A_UINT32 sendn_frms_allowed;
} htt_tx_tid_stats_v1_tlv;
-#define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff
-#define HTT_RX_TID_STATS_SW_PEER_ID_S 0
-#define HTT_RX_TID_STATS_TID_NUM_M 0xffff0000
-#define HTT_RX_TID_STATS_TID_NUM_S 16
+#define HTT_RX_TID_STATS_SW_PEER_ID_M 0x0000ffff
+#define HTT_RX_TID_STATS_SW_PEER_ID_S 0
+#define HTT_RX_TID_STATS_TID_NUM_M 0xffff0000
+#define HTT_RX_TID_STATS_TID_NUM_S 16
#define HTT_RX_TID_STATS_SW_PEER_ID_GET(_var) \
(((_var) & HTT_RX_TID_STATS_SW_PEER_ID_M) >> \
- HTT_RX_TID_STATS_SW_PEER_ID_S)
+ HTT_RX_TID_STATS_SW_PEER_ID_S)
#define HTT_RX_TID_STATS_SW_PEER_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_SW_PEER_ID, _val); \
- ((_var) |= ((_val) << HTT_RX_TID_STATS_SW_PEER_ID_S)); \
- } while (0)
-
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_SW_PEER_ID, _val); \
+ ((_var) |= ((_val) << HTT_RX_TID_STATS_SW_PEER_ID_S)); \
+ } while (0)
#define HTT_RX_TID_STATS_TID_NUM_GET(_var) \
(((_var) & HTT_RX_TID_STATS_TID_NUM_M) >> \
- HTT_RX_TID_STATS_TID_NUM_S)
+ HTT_RX_TID_STATS_TID_NUM_S)
#define HTT_RX_TID_STATS_TID_NUM_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_TID_NUM, _val); \
- ((_var) |= ((_val) << HTT_RX_TID_STATS_TID_NUM_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_TID_STATS_TID_NUM, _val); \
+ ((_var) |= ((_val) << HTT_RX_TID_STATS_TID_NUM_S)); \
+ } while (0)
typedef struct _htt_rx_tid_stats_tlv {
htt_tlv_hdr_t tlv_hdr;
+
/* BIT [15 : 0] : sw_peer_id
* BIT [31 : 16] : tid_num
*/
@@ -894,7 +1100,7 @@
/* Stored as little endian */
A_UINT8 tid_name[MAX_HTT_TID_NAME];
/* dup_in_reorder not collected per tid for now,
- as there is no wal_peer back ptr in data rx peer. */
+ as there is no wal_peer back ptr in data rx peer. */
A_UINT32 dup_in_reorder;
A_UINT32 dup_past_outside_window;
A_UINT32 dup_past_within_window;
@@ -908,11 +1114,10 @@
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Stored as little endian */
- A_UINT8 counter_name[HTT_MAX_COUNTER_NAME];
- A_UINT32 count;
+ A_UINT8 counter_name[HTT_MAX_COUNTER_NAME];
+ A_UINT32 count;
} htt_counter_tlv;
-
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Number of rx ppdu. */
@@ -943,6 +1148,15 @@
/* Total ppdu transmitted bytes for peer: includes MAC header overhead */
A_UINT32 ppdu_transmitted_bytes_low;
A_UINT32 ppdu_transmitted_bytes_high;
+ A_UINT32 peer_ttl_removed_count;
+ /* inactive_time
+ * Running duration of the time since last tx/rx activity by this peer,
+ * units = seconds.
+ * If the peer is currently active, this inactive_time will be 0x0.
+ */
+ A_UINT32 inactive_time;
+ /* Number of MPDUs dropped after max retries */
+ A_UINT32 remove_mpdus_max_retries;
} htt_peer_stats_cmn_tlv;
typedef struct {
@@ -954,10 +1168,10 @@
* BIT [15 : 8] :- pdev_id
* BIT [31 : 16] :- ast_indx
*/
- A_UINT32 vdev_pdev_ast_idx;
+ A_UINT32 vdev_pdev_ast_idx;
htt_mac_addr mac_addr;
- A_UINT32 peer_flags;
- A_UINT32 qpeer_flags;
+ A_UINT32 peer_flags;
+ A_UINT32 qpeer_flags;
} htt_peer_details_tlv;
typedef enum {
@@ -972,12 +1186,25 @@
HTT_STATS_PREAM_COUNT,
} HTT_STATS_PREAM_TYPE;
-#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12
-#define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4
-#define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5
-#define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4
-#define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8
-#define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
+#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12
+#define HTT_TX_PEER_STATS_NUM_GI_COUNTERS 4
+#define HTT_TX_PEER_STATS_NUM_DCM_COUNTERS 5
+ /* HTT_TX_PEER_STATS_NUM_BW_COUNTERS:
+ * bw index 0: rssi_pri20_chain0
+ * bw index 1: rssi_ext20_chain0
+ * bw index 2: rssi_ext40_low20_chain0
+ * bw index 3: rssi_ext40_high20_chain0
+ */
+#define HTT_TX_PEER_STATS_NUM_BW_COUNTERS 4
+/* HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS:
+ * bw index 4 (bw ext index 0): rssi_ext80_low20_chain0
+ * bw index 5 (bw ext index 1): rssi_ext80_low_high20_chain0
+ * bw index 6 (bw ext index 2): rssi_ext80_high_low20_chain0
+ * bw index 7 (bw ext index 3): rssi_ext80_high20_chain0
+ */
+#define HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS 4
+#define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8
+#define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
typedef struct _htt_tx_peer_rate_stats_tlv {
htt_tlv_hdr_t tlv_hdr;
@@ -993,7 +1220,7 @@
A_UINT32 tx_su_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
A_UINT32 tx_mu_mcs[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
A_UINT32 tx_nss[HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS]; /* element 0,1, ...7 -> NSS 1,2, ...8 */
- A_UINT32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
+ A_UINT32 tx_bw[HTT_TX_PEER_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
A_UINT32 tx_stbc[HTT_TX_PEER_STATS_NUM_MCS_COUNTERS];
A_UINT32 tx_pream[HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES];
@@ -1002,19 +1229,18 @@
/* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */
A_UINT32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS];
-
} htt_tx_peer_rate_stats_tlv;
-#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12
-#define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4
-#define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5
-#define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4
-#define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8
-#define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
+#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12
+#define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4
+#define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5
+#define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4
+#define HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS 8
+#define HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
typedef struct _htt_rx_peer_rate_stats_tlv {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 nsts;
+ A_UINT32 nsts;
/* Number of rx ldpc packets */
A_UINT32 rx_ldpc;
@@ -1030,11 +1256,33 @@
A_UINT32 rx_stbc[HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
A_UINT32 rx_bw[HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
A_UINT32 rx_pream[HTT_RX_PEER_STATS_NUM_PREAMBLE_TYPES];
- A_UINT8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; /* units = dB above noise floor */
+ A_UINT8 rssi_chain[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS]; /* units = dB above noise floor */
/* Counters to track number of rx packets in each GI in each mcs (0-11) */
A_UINT32 rx_gi[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_MCS_COUNTERS];
+ A_UINT32 rx_ulofdma_non_data_ppdu; /* ppdu level */
+ A_UINT32 rx_ulofdma_data_ppdu; /* ppdu level */
+ A_UINT32 rx_ulofdma_mpdu_ok; /* mpdu level */
+ A_UINT32 rx_ulofdma_mpdu_fail; /* mpdu level */
+ A_INT8 rx_ul_fd_rssi[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS]; /* dBm unit */
+ /* per_chain_rssi_pkt_type:
+ * This field shows what type of rx frame the per-chain RSSI was computed
+ * on, by recording the frame type and sub-type as bit-fields within this
+ * field:
+ * BIT [3 : 0] :- IEEE80211_FC0_TYPE
+ * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE
+ * BIT [31 : 8] :- Reserved
+ */
+ A_UINT32 per_chain_rssi_pkt_type;
+ A_INT8 rx_per_chain_rssi_in_dbm[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_COUNTERS];
+
+ A_UINT32 rx_ulmumimo_non_data_ppdu; /* ppdu level */
+ A_UINT32 rx_ulmumimo_data_ppdu; /* ppdu level */
+ A_UINT32 rx_ulmumimo_mpdu_ok; /* mpdu level */
+ A_UINT32 rx_ulmumimo_mpdu_fail; /* mpdu level */
+
+ A_UINT8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; /* units = dB above noise floor */
} htt_rx_peer_rate_stats_tlv;
typedef enum {
@@ -1044,55 +1292,54 @@
} htt_peer_stats_req_mode_t;
typedef enum {
- HTT_PEER_STATS_CMN_TLV = 0,
- HTT_PEER_DETAILS_TLV = 1,
- HTT_TX_PEER_RATE_STATS_TLV = 2,
- HTT_RX_PEER_RATE_STATS_TLV = 3,
- HTT_TX_TID_STATS_TLV = 4,
- HTT_RX_TID_STATS_TLV = 5,
- HTT_MSDU_FLOW_STATS_TLV = 6,
+ HTT_PEER_STATS_CMN_TLV = 0,
+ HTT_PEER_DETAILS_TLV = 1,
+ HTT_TX_PEER_RATE_STATS_TLV = 2,
+ HTT_RX_PEER_RATE_STATS_TLV = 3,
+ HTT_TX_TID_STATS_TLV = 4,
+ HTT_RX_TID_STATS_TLV = 5,
+ HTT_MSDU_FLOW_STATS_TLV = 6,
- HTT_PEER_STATS_MAX_TLV = 31,
+ HTT_PEER_STATS_MAX_TLV = 31,
} htt_peer_stats_tlv_enum;
/* config_param0 */
-#define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_M 0x00000001
-#define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S 0
+#define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_M 0x00000001
+#define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S 0
-#define HTT_DBG_EXT_STATS_PEER_REQ_MODE_M 0x0000FFFE
-#define HTT_DBG_EXT_STATS_PEER_REQ_MODE_S 1
+#define HTT_DBG_EXT_STATS_PEER_REQ_MODE_M 0x0000FFFE
+#define HTT_DBG_EXT_STATS_PEER_REQ_MODE_S 1
-#define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_M 0xFFFF0000
-#define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S 16
+#define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_M 0xFFFF0000
+#define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S 16
-#define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET( _var, _val)\
- do { \
- HTT_CHECK_SET_VAL(HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR, _val); \
- ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S)); \
- } while (0)
+#define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_SET(_var, _val) \
+ do { \
+ HTT_CHECK_SET_VAL(HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR, _val); \
+ ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S)); \
+ } while (0)
#define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_GET(_var) \
(((_var) & HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_M) >> \
- HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S)
-
+ HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S)
#define HTT_DBG_EXT_STATS_PEER_REQ_MODE_GET(_var) \
(((_var) & HTT_DBG_EXT_STATS_PEER_REQ_MODE_M) >> \
- HTT_DBG_EXT_STATS_PEER_REQ_MODE_S)
+ HTT_DBG_EXT_STATS_PEER_REQ_MODE_S)
#define HTT_DBG_EXT_STATS_PEER_REQ_MODE_SET(_var, _val) \
- do { \
- ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_REQ_MODE_S)); \
- } while (0)
+ do { \
+ ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_REQ_MODE_S)); \
+ } while (0)
#define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_GET(_var) \
(((_var) & HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_M) >> \
- HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S)
+ HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S)
#define HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_SET(_var, _val) \
- do { \
- ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S)); \
- } while (0)
+ do { \
+ ((_var) |= ((_val) << HTT_DBG_EXT_STATS_PEER_INFO_SW_PEER_ID_S)); \
+ } while (0)
/* STATS_TYPE : HTT_DBG_EXT_STATS_PEER_INFO
* TLV_TAGS:
@@ -1111,14 +1358,15 @@
*/
typedef struct _htt_peer_stats {
htt_peer_stats_cmn_tlv cmn_tlv;
+
htt_peer_details_tlv peer_details;
/* from g_rate_info_stats */
htt_tx_peer_rate_stats_tlv tx_rate;
htt_rx_peer_rate_stats_tlv rx_rate;
- htt_tx_tid_stats_tlv tx_tid_stats[1];
- htt_rx_tid_stats_tlv rx_tid_stats[1];
- htt_msdu_flow_stats_tlv msdu_flowq[1];
- htt_tx_tid_stats_v1_tlv tx_tid_stats_v1[1];
+ htt_tx_tid_stats_tlv tx_tid_stats[1];
+ htt_rx_tid_stats_tlv rx_tid_stats[1];
+ htt_msdu_flow_stats_tlv msdu_flowq[1];
+ htt_tx_tid_stats_v1_tlv tx_tid_stats_v1[1];
} htt_peer_stats_t;
/* =========== ACTIVE PEER LIST ========== */
@@ -1135,56 +1383,56 @@
htt_peer_details_tlv peer_details[1];
} htt_active_peer_details_list_t;
-
/* =========== MUMIMO HWQ stats =========== */
/* MU MIMO stats per hwQ */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 mu_mimo_sch_posted;
- A_UINT32 mu_mimo_sch_failed;
- A_UINT32 mu_mimo_ppdu_posted;
+ A_UINT32 mu_mimo_sch_posted;
+ A_UINT32 mu_mimo_sch_failed;
+ A_UINT32 mu_mimo_ppdu_posted;
} htt_tx_hwq_mu_mimo_sch_stats_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 mu_mimo_mpdus_queued_usr; /* Number of mpdus queued per user */
- A_UINT32 mu_mimo_mpdus_tried_usr; /* Number of mpdus actually transmitted by TxPCU per user */
- A_UINT32 mu_mimo_mpdus_failed_usr; /* Number of mpdus failed per user */
- A_UINT32 mu_mimo_mpdus_requeued_usr; /* Number of mpdus requeued per user */
- A_UINT32 mu_mimo_err_no_ba_usr; /* Number of times BA is not received for a user in MU PPDU */
- A_UINT32 mu_mimo_mpdu_underrun_usr;
- A_UINT32 mu_mimo_ampdu_underrun_usr;
+ A_UINT32 mu_mimo_mpdus_queued_usr; /* Number of mpdus queued per user */
+ A_UINT32 mu_mimo_mpdus_tried_usr; /* Number of mpdus actually transmitted by TxPCU per user */
+ A_UINT32 mu_mimo_mpdus_failed_usr; /* Number of mpdus failed per user */
+ A_UINT32 mu_mimo_mpdus_requeued_usr; /* Number of mpdus requeued per user */
+ A_UINT32 mu_mimo_err_no_ba_usr; /* Number of times BA is not received for a user in MU PPDU */
+ A_UINT32 mu_mimo_mpdu_underrun_usr;
+ A_UINT32 mu_mimo_ampdu_underrun_usr;
} htt_tx_hwq_mu_mimo_mpdu_stats_tlv;
-#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_M 0x000000ff
-#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S 0
+#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_M 0x000000ff
+#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S 0
-#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_M 0x0000ff00
-#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S 8
+#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_M 0x0000ff00
+#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S 8
#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_GET(_var) \
(((_var) & HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_M) >> \
- HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S)
+ HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S)
#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_HWQ_MU_MIMO_CMN_STATS_MAC_ID_S)); \
+ } while (0)
#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_GET(_var) \
(((_var) & HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_M) >> \
- HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S)
+ HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S)
#define HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_HWQ_MU_MIMO_CMN_STATS_HWQ_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
+
/* BIT [ 7 : 0] :- mac_id
* BIT [15 : 8] :- hwq_id
* BIT [31 : 16] :- reserved
@@ -1198,41 +1446,42 @@
*/
typedef struct {
struct _hwq_mu_mimo_stats {
- htt_tx_hwq_mu_mimo_cmn_stats_tlv cmn_tlv;
- htt_tx_hwq_mu_mimo_sch_stats_tlv mu_mimo_sch_stats_tlv[1]; /* WAL_TX_STATS_MAX_GROUP_SIZE */
+ htt_tx_hwq_mu_mimo_cmn_stats_tlv cmn_tlv;
+ htt_tx_hwq_mu_mimo_sch_stats_tlv mu_mimo_sch_stats_tlv[1]; /* WAL_TX_STATS_MAX_GROUP_SIZE */
htt_tx_hwq_mu_mimo_mpdu_stats_tlv mu_mimo_mpdu_stats_tlv[1]; /* WAL_TX_STATS_TX_MAX_NUM_USERS */
} hwq[1];
} htt_tx_hwq_mu_mimo_stats_t;
/* == TX HWQ STATS == */
-#define HTT_TX_HWQ_STATS_CMN_MAC_ID_M 0x000000ff
-#define HTT_TX_HWQ_STATS_CMN_MAC_ID_S 0
+#define HTT_TX_HWQ_STATS_CMN_MAC_ID_M 0x000000ff
+#define HTT_TX_HWQ_STATS_CMN_MAC_ID_S 0
-#define HTT_TX_HWQ_STATS_CMN_HWQ_ID_M 0x0000ff00
-#define HTT_TX_HWQ_STATS_CMN_HWQ_ID_S 8
+#define HTT_TX_HWQ_STATS_CMN_HWQ_ID_M 0x0000ff00
+#define HTT_TX_HWQ_STATS_CMN_HWQ_ID_S 8
#define HTT_TX_HWQ_STATS_CMN_MAC_ID_GET(_var) \
(((_var) & HTT_TX_HWQ_STATS_CMN_MAC_ID_M) >> \
- HTT_TX_HWQ_STATS_CMN_MAC_ID_S)
+ HTT_TX_HWQ_STATS_CMN_MAC_ID_S)
#define HTT_TX_HWQ_STATS_CMN_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_HWQ_STATS_CMN_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_HWQ_STATS_CMN_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_HWQ_STATS_CMN_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_HWQ_STATS_CMN_MAC_ID_S)); \
+ } while (0)
#define HTT_TX_HWQ_STATS_CMN_HWQ_ID_GET(_var) \
(((_var) & HTT_TX_HWQ_STATS_CMN_HWQ_ID_M) >> \
- HTT_TX_HWQ_STATS_CMN_HWQ_ID_S)
+ HTT_TX_HWQ_STATS_CMN_HWQ_ID_S)
#define HTT_TX_HWQ_STATS_CMN_HWQ_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_HWQ_STATS_CMN_HWQ_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_HWQ_STATS_CMN_HWQ_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_HWQ_STATS_CMN_HWQ_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_HWQ_STATS_CMN_HWQ_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
+
/* BIT [ 7 : 0] :- mac_id
* BIT [15 : 8] :- hwq_id
* BIT [31 : 16] :- reserved
@@ -1240,37 +1489,39 @@
A_UINT32 mac_id__hwq_id__word;
/* PPDU level stats */
- A_UINT32 xretry; /* Number of times ack is failed for the PPDU scheduled on this txQ */
- A_UINT32 underrun_cnt; /* Number of times sched cmd status reported mpdu underrun */
- A_UINT32 flush_cnt; /* Number of times sched cmd is flushed */
- A_UINT32 filt_cnt; /* Number of times sched cmd is filtered */
- A_UINT32 null_mpdu_bmap; /* Number of times HWSCH uploaded null mpdu bitmap */
- A_UINT32 user_ack_failure; /* Number of time user ack or ba tlv is not seen on FES ring where it is expected to be */
- A_UINT32 ack_tlv_proc; /* Number of times TQM processed ack tlv received from HWSCH */
- A_UINT32 sched_id_proc; /* Cache latest processed scheduler ID received from ack ba tlv */
- A_UINT32 null_mpdu_tx_count; /* Number of times TxPCU reported mpdus transmitted for a user is zero */
- A_UINT32 mpdu_bmap_not_recvd; /* Number of times SW did not see any mpdu info bitmap tlv on FES status ring */
+ A_UINT32 xretry; /* Number of times ack is failed for the PPDU scheduled on this txQ */
+ A_UINT32 underrun_cnt; /* Number of times sched cmd status reported mpdu underrun */
+ A_UINT32 flush_cnt; /* Number of times sched cmd is flushed */
+ A_UINT32 filt_cnt; /* Number of times sched cmd is filtered */
+ A_UINT32 null_mpdu_bmap; /* Number of times HWSCH uploaded null mpdu bitmap */
+ A_UINT32 user_ack_failure; /* Number of time user ack or ba tlv is not seen on FES ring where it is expected to be */
+ A_UINT32 ack_tlv_proc; /* Number of times TQM processed ack tlv received from HWSCH */
+ A_UINT32 sched_id_proc; /* Cache latest processed scheduler ID received from ack ba tlv */
+ A_UINT32 null_mpdu_tx_count; /* Number of times TxPCU reported mpdus transmitted for a user is zero */
+ A_UINT32 mpdu_bmap_not_recvd; /* Number of times SW did not see any mpdu info bitmap tlv on FES status ring */
/* Selfgen stats per hwQ */
- A_UINT32 num_bar; /* Number of SU/MU BAR frames posted to hwQ */
- A_UINT32 rts; /* Number of RTS frames posted to hwQ */
- A_UINT32 cts2self; /* Number of cts2self frames posted to hwQ */
- A_UINT32 qos_null; /* Number of qos null frames posted to hwQ */
+ A_UINT32 num_bar; /* Number of SU/MU BAR frames posted to hwQ */
+ A_UINT32 rts; /* Number of RTS frames posted to hwQ */
+ A_UINT32 cts2self; /* Number of cts2self frames posted to hwQ */
+ A_UINT32 qos_null; /* Number of qos null frames posted to hwQ */
/* MPDU level stats */
- A_UINT32 mpdu_tried_cnt; /* mpdus tried Tx by HWSCH/TQM */
- A_UINT32 mpdu_queued_cnt; /* mpdus queued to HWSCH */
- A_UINT32 mpdu_ack_fail_cnt; /* mpdus tried but ack was not received */
- A_UINT32 mpdu_filt_cnt; /* This will include sched cmd flush and time based discard */
- A_UINT32 false_mpdu_ack_count; /* Number of MPDUs for which ACK was sucessful but no Tx happened */
+ A_UINT32 mpdu_tried_cnt; /* mpdus tried Tx by HWSCH/TQM */
+ A_UINT32 mpdu_queued_cnt; /* mpdus queued to HWSCH */
+ A_UINT32 mpdu_ack_fail_cnt; /* mpdus tried but ack was not received */
+ A_UINT32 mpdu_filt_cnt; /* This will include sched cmd flush and time based discard */
+ A_UINT32 false_mpdu_ack_count; /* Number of MPDUs for which ACK was sucessful but no Tx happened */
+
+ A_UINT32 txq_timeout; /* Number of times txq timeout happened */
} htt_tx_hwq_stats_cmn_tlv;
-#define HTT_TX_HWQ_DIFS_LATENCY_STATS_TLV_SZ(_num_elems) ( sizeof(A_UINT32) + /* hist_intvl */ \
+#define HTT_TX_HWQ_DIFS_LATENCY_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) + /* hist_intvl */ \
(sizeof(A_UINT32) * (_num_elems)))
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 hist_intvl;
+ A_UINT32 hist_intvl;
/* histogram of ppdu post to hwsch - > cmd status received */
A_UINT32 difs_latency_hist[1]; /* HTT_TX_HWQ_MAX_DIFS_LATENCY_BINS */
} htt_tx_hwq_difs_latency_stats_tlv_v;
@@ -1302,6 +1553,45 @@
A_UINT32 fes_result[1]; /* HTT_TX_HWQ_MAX_FES_RESULT_STATS */
} htt_tx_hwq_fes_result_stats_tlv_v;
+#define HTT_TX_HWQ_TRIED_MPDU_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
+/* NOTE: Variable length TLV, use length spec to infer array size
+ *
+ * The hwq_tried_mpdu_cnt_hist is a histogram of MPDUs tries per HWQ.
+ * The tries here is the count of the MPDUS within a PPDU that the HW
+ * had attempted to transmit on air, for the HWSCH Schedule command
+ * submitted by FW in this HWQ .It is not the retry attempts. The
+ * histogram bins are 0-29, 30-59, 60-89 and so on. The are 10 bins
+ * in this histogram.
+ * they are defined in FW using the following macros
+ * #define WAL_MAX_TRIED_MPDU_CNT_HISTOGRAM 9
+ * #define WAL_TRIED_MPDU_CNT_HISTOGRAM_INTERVAL 30
+ *
+ * */
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 hist_bin_size;
+ /* Histogram of number of mpdus on tried mpdu */
+ A_UINT32 tried_mpdu_cnt_hist[1]; /* HTT_TX_HWQ_TRIED_MPDU_CNT_HIST */
+} htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v;
+
+#define HTT_TX_HWQ_TXOP_USED_CNT_HIST_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
+/* NOTE: Variable length TLV, use length spec to infer array size
+ *
+ * The txop_used_cnt_hist is the histogram of txop per burst. After
+ * completing the burst, we identify the txop used in the burst and
+ * incr the corresponding bin.
+ * Each bin represents 1ms & we have 10 bins in this histogram.
+ * they are deined in FW using the following macros
+ * #define WAL_MAX_TXOP_USED_CNT_HISTOGRAM 10
+ * #define WAL_TXOP_USED_HISTOGRAM_INTERVAL 1000 ( 1 ms )
+ *
+ * */
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ /* Histogram of txop used cnt */
+ A_UINT32 txop_used_cnt_hist[1]; /* HTT_TX_HWQ_TXOP_USED_CNT_HIST */
+} htt_tx_hwq_txop_used_cnt_hist_tlv_v;
+
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_HWQ
* TLV_TAGS:
* - HTT_STATS_STRING_TAG
@@ -1310,34 +1600,43 @@
* - HTT_STATS_TX_HWQ_CMD_RESULT_TAG
* - HTT_STATS_TX_HWQ_CMD_STALL_TAG
* - HTT_STATS_TX_HWQ_FES_STATUS_TAG
+ * - HTT_STATS_TX_HWQ_TRIED_MPDU_CNT_HIST_TAG
+ * - HTT_STATS_TX_HWQ_TXOP_USED_CNT_HIST_TAG
*/
/* NOTE:
* This structure is for documentation, and cannot be safely used directly.
* Instead, use the constituent TLV structures to fill/parse.
+ * General HWQ stats Mechanism:
+ * Once the host request for the stats, FW fill all the HWQ TAGS in a buffer
+ * for all the HWQ requested. & the FW send the buffer to host. In the
+ * buffer the HWQ ID is filled in mac_id__hwq_id, thus identifying each
+ * HWQ distinctly.
*/
typedef struct _htt_tx_hwq_stats {
- htt_stats_string_tlv hwq_str_tlv;
- htt_tx_hwq_stats_cmn_tlv cmn_tlv;
- htt_tx_hwq_difs_latency_stats_tlv_v difs_tlv;
- htt_tx_hwq_cmd_result_stats_tlv_v cmd_result_tlv;
- htt_tx_hwq_cmd_stall_stats_tlv_v cmd_stall_tlv;
- htt_tx_hwq_fes_result_stats_tlv_v fes_stats_tlv;
+ htt_stats_string_tlv hwq_str_tlv;
+ htt_tx_hwq_stats_cmn_tlv cmn_tlv;
+ htt_tx_hwq_difs_latency_stats_tlv_v difs_tlv;
+ htt_tx_hwq_cmd_result_stats_tlv_v cmd_result_tlv;
+ htt_tx_hwq_cmd_stall_stats_tlv_v cmd_stall_tlv;
+ htt_tx_hwq_fes_result_stats_tlv_v fes_stats_tlv;
+ htt_tx_hwq_tried_mpdu_cnt_hist_tlv_v tried_mpdu_tlv;
+ htt_tx_hwq_txop_used_cnt_hist_tlv_v txop_used_tlv;
} htt_tx_hwq_stats_t;
/* == TX SELFGEN STATS == */
-#define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_M 0x000000ff
-#define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S 0
+#define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_M 0x000000ff
+#define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S 0
#define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_GET(_var) \
(((_var) & HTT_TX_SELFGEN_CMN_STATS_MAC_ID_M) >> \
- HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S)
+ HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S)
#define HTT_TX_SELFGEN_CMN_STATS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_SELFGEN_CMN_STATS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_SELFGEN_CMN_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -1389,6 +1688,7 @@
A_UINT32 ax_bsr_trigger;
A_UINT32 ax_mu_bar_trigger;
A_UINT32 ax_mu_rts_trigger;
+ A_UINT32 ax_ulmumimo_trigger;
} htt_tx_selfgen_ax_stats_tlv;
typedef struct {
@@ -1421,6 +1721,7 @@
A_UINT32 ax_bsr_trigger_err;
A_UINT32 ax_mu_bar_trigger_err;
A_UINT32 ax_mu_rts_trigger_err;
+ A_UINT32 ax_ulmumimo_trigger_err;
} htt_tx_selfgen_ax_err_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SELFGEN_INFO
@@ -1451,7 +1752,7 @@
#define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4
#define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8
-#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74
+#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -1469,6 +1770,10 @@
A_UINT32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS];
A_UINT32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS];
A_UINT32 ax_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
+ A_UINT32 ax_ul_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
+ A_UINT32 ax_ul_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
+ A_UINT32 ax_ul_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
+ A_UINT32 ax_ul_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS];
} htt_tx_pdev_mu_mimo_sch_stats_tlv;
typedef struct {
@@ -1503,8 +1808,8 @@
A_UINT32 ax_ofdma_ampdu_underrun_usr;
} htt_tx_pdev_mu_mimo_mpdu_stats_tlv;
-#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 /* SCHED_TX_MODE_MU_MIMO_AC */
-#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 /* SCHED_TX_MODE_MU_MIMO_AX */
+#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC 1 /* SCHED_TX_MODE_MU_MIMO_AC */
+#define HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX 2 /* SCHED_TX_MODE_MU_MIMO_AX */
#define HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX 3 /* SCHED_TX_MODE_MU_OFDMA_AX */
typedef struct {
@@ -1559,31 +1864,77 @@
A_UINT32 sched_cmd_reaped[1]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */
} htt_sched_txq_cmd_reaped_tlv_v;
-#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M 0x000000ff
-#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S 0
+#define HTT_SCHED_TXQ_SCHED_ORDER_SU_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
-#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_M 0x0000ff00
-#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S 8
+/* NOTE: Variable length TLV, use length spec to infer array size */
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ /*
+ * sched_order_su contains the peer IDs of peers chosen in the last
+ * NUM_SCHED_ORDER_LOG scheduler instances.
+ * The array is circular; it's unspecified which array element corresponds
+ * to the most recent scheduler invocation, and which corresponds to
+ * the (NUM_SCHED_ORDER_LOG-1) most recent scheduler invocation.
+ */
+ A_UINT32 sched_order_su[1]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */
+} htt_sched_txq_sched_order_su_tlv_v;
+
+typedef enum {
+ HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, /* Skip the tid when WAL_TID_DISABLE_TX_SCHED_MASK is true */
+ HTT_SCHED_TID_SKIP_NOTIFY_MPDU, /* Skip the tid's 2nd sched_cmd when 1st cmd is ongoing */
+ HTT_SCHED_TID_SKIP_MPDU_STATE_INVALID, /* Skip the tid when MPDU state is invalid */
+ HTT_SCHED_TID_SKIP_SCHED_DISABLED, /* Skip the tid when scheduling is disabled for that tid */
+ HTT_SCHED_TID_SKIP_TQM_BYPASS_CMD_PENDING, /* Skip the TQM bypass tid when it has pending sched_cmd */
+ HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, /* Skip tid from 2nd SU schedule when any of the following flag is set
+ WAL_TX_TID(SEND_BAR | TQM_MPDU_STATE_VALID | SEND_QOS_NULL | TQM_NOTIFY_MPDU | SENDN_PENDING) */
+ HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, /* Skip the tid when command slot is not available */
+ HTT_SCHED_TID_SKIP_NO_ENQ, /* Skip the tid when num_frames is zero with g_disable_remove_tid as true */
+ HTT_SCHED_TID_SKIP_LOW_ENQ, /* Skip the tid when enqueue is low */
+ HTT_SCHED_TID_SKIP_PAUSED, /* Skipping the paused tid(sendn-frames) */
+ HTT_SCHED_TID_SKIP_UL, /* UL tid skip */
+ HTT_SCHED_TID_REMOVE_PAUSED, /* Removing the paused tid when number of sendn frames is zero */
+ HTT_SCHED_TID_REMOVE_NO_ENQ, /* Remove tid with zero queue depth */
+ HTT_SCHED_TID_REMOVE_UL, /* UL tid remove */
+ HTT_SCHED_TID_QUERY, /* Moving to next user and adding tid in prepend list when qstats update is pending */
+ HTT_SCHED_TID_SU_ONLY, /* Tid is eligible and TX_SCHED_SU_ONLY is true */
+ HTT_SCHED_TID_ELIGIBLE, /* Tid is eligible for scheduling */
+ HTT_SCHED_INELIGIBILITY_MAX,
+} htt_sched_txq_sched_ineligibility_tlv_enum;
+
+#define HTT_SCHED_TXQ_SCHED_INELIGIBILITY_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
+
+/* NOTE: Variable length TLV, use length spec to infer array size */
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ /* sched_ineligibility counts the number of occurrences of different reasons for tid ineligibility during eligibility checks per txq in scheduling */
+ A_UINT32 sched_ineligibility[1]; /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */
+} htt_sched_txq_sched_ineligibility_tlv_v;
+
+#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M 0x000000ff
+#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S 0
+
+#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_M 0x0000ff00
+#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S 8
#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_GET(_var) \
(((_var) & HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M) >> \
- HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S)
+ HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S)
#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S)); \
+ } while (0)
#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_GET(_var) \
(((_var) & HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_M) >> \
- HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S)
+ HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S)
#define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_PDEV_STATS_SCHED_PER_TXQ_TXQUEUE_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -1631,23 +1982,36 @@
A_UINT32 num_tqm_sched_algo_trigger;
/* Num of schedules for notify frame */
A_UINT32 notify_sched;
+ /* Duration based sendn termination */
+ A_UINT32 dur_based_sendn_term;
+ /* scheduled via NOTIFY2 */
+ A_UINT32 su_notify2_sched;
+ /* schedule if queued packets are greater than avg MSDUs in PPDU */
+ A_UINT32 su_optimal_queued_msdus_sched;
+ /* schedule due to timeout */
+ A_UINT32 su_delay_timeout_sched;
+ /* delay if txtime is less than 500us */
+ A_UINT32 su_min_txtime_sched_delay;
+ /* scheduled via no delay */
+ A_UINT32 su_no_delay;
} htt_tx_pdev_stats_sched_per_txq_tlv;
-#define HTT_STATS_TX_SCHED_CMN_MAC_ID_M 0x000000ff
-#define HTT_STATS_TX_SCHED_CMN_MAC_ID_S 0
+#define HTT_STATS_TX_SCHED_CMN_MAC_ID_M 0x000000ff
+#define HTT_STATS_TX_SCHED_CMN_MAC_ID_S 0
#define HTT_STATS_TX_SCHED_CMN_MAC_ID_GET(_var) \
(((_var) & HTT_STATS_TX_SCHED_CMN_MAC_ID_M) >> \
- HTT_STATS_TX_SCHED_CMN_MAC_ID_S)
+ HTT_STATS_TX_SCHED_CMN_MAC_ID_S)
#define HTT_STATS_TX_SCHED_CMN_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_STATS_TX_SCHED_CMN_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_STATS_TX_SCHED_CMN_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_STATS_TX_SCHED_CMN_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_STATS_TX_SCHED_CMN_MAC_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
+
/* BIT [ 7 : 0] :- mac_id
* BIT [31 : 8] :- reserved
*/
@@ -1662,6 +2026,8 @@
* - HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG
* - HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG
* - HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG
+ * - HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG
+ * - HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG
*/
/* NOTE:
* This structure is for documentation, and cannot be safely used directly.
@@ -1670,17 +2036,18 @@
typedef struct {
htt_stats_tx_sched_cmn_tlv cmn_tlv;
struct _txq_tx_sched_stats {
- htt_tx_pdev_stats_sched_per_txq_tlv txq_tlv;
- htt_sched_txq_cmd_posted_tlv_v cmd_posted_tlv;
- htt_sched_txq_cmd_reaped_tlv_v cmd_reaped_tlv;
+ htt_tx_pdev_stats_sched_per_txq_tlv txq_tlv;
+ htt_sched_txq_cmd_posted_tlv_v cmd_posted_tlv;
+ htt_sched_txq_cmd_reaped_tlv_v cmd_reaped_tlv;
+ htt_sched_txq_sched_order_su_tlv_v sched_order_su_tlv;
+ htt_sched_txq_sched_ineligibility_tlv_v sched_ineligibility_tlv;
} txq[1];
} htt_stats_tx_sched_t;
-
/* == TQM STATS == */
-#define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16
-#define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16
+#define HTT_TX_TQM_MAX_GEN_MPDU_END_REASON 16
+#define HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16
#define HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16
#define HTT_TX_TQM_GEN_MPDU_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
@@ -1688,7 +2055,7 @@
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 gen_mpdu_end_reason[1]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */
+ A_UINT32 gen_mpdu_end_reason[1]; /* HTT_TX_TQM_MAX_GEN_MPDU_END_REASON */
} htt_tx_tqm_gen_mpdu_stats_tlv_v;
#define HTT_TX_TQM_LIST_MPDU_STATS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
@@ -1696,7 +2063,7 @@
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 list_mpdu_end_reason[1]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */
+ A_UINT32 list_mpdu_end_reason[1]; /* HTT_TX_TQM_MAX_LIST_MPDU_END_REASON */
} htt_tx_tqm_list_mpdu_stats_tlv_v;
#define HTT_TX_TQM_LIST_MPDU_CNT_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
@@ -1704,52 +2071,68 @@
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 list_mpdu_cnt_hist[1]; /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */
+ A_UINT32 list_mpdu_cnt_hist[1]; /* HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS */
} htt_tx_tqm_list_mpdu_cnt_tlv_v;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 msdu_count;
- A_UINT32 mpdu_count;
- A_UINT32 remove_msdu;
- A_UINT32 remove_mpdu;
- A_UINT32 remove_msdu_ttl;
- A_UINT32 send_bar;
- A_UINT32 bar_sync;
- A_UINT32 notify_mpdu;
- A_UINT32 sync_cmd;
- A_UINT32 write_cmd;
- A_UINT32 hwsch_trigger;
- A_UINT32 ack_tlv_proc;
- A_UINT32 gen_mpdu_cmd;
- A_UINT32 gen_list_cmd;
- A_UINT32 remove_mpdu_cmd;
- A_UINT32 remove_mpdu_tried_cmd;
- A_UINT32 mpdu_queue_stats_cmd;
- A_UINT32 mpdu_head_info_cmd;
- A_UINT32 msdu_flow_stats_cmd;
- A_UINT32 remove_msdu_cmd;
- A_UINT32 remove_msdu_ttl_cmd;
- A_UINT32 flush_cache_cmd;
- A_UINT32 update_mpduq_cmd;
- A_UINT32 enqueue;
- A_UINT32 enqueue_notify;
- A_UINT32 notify_mpdu_at_head;
- A_UINT32 notify_mpdu_state_valid;
+ A_UINT32 msdu_count;
+ A_UINT32 mpdu_count;
+ A_UINT32 remove_msdu;
+ A_UINT32 remove_mpdu;
+ A_UINT32 remove_msdu_ttl;
+ A_UINT32 send_bar;
+ A_UINT32 bar_sync;
+ A_UINT32 notify_mpdu;
+ A_UINT32 sync_cmd;
+ A_UINT32 write_cmd;
+ A_UINT32 hwsch_trigger;
+ A_UINT32 ack_tlv_proc;
+ A_UINT32 gen_mpdu_cmd;
+ A_UINT32 gen_list_cmd;
+ A_UINT32 remove_mpdu_cmd;
+ A_UINT32 remove_mpdu_tried_cmd;
+ A_UINT32 mpdu_queue_stats_cmd;
+ A_UINT32 mpdu_head_info_cmd;
+ A_UINT32 msdu_flow_stats_cmd;
+ A_UINT32 remove_msdu_cmd;
+ A_UINT32 remove_msdu_ttl_cmd;
+ A_UINT32 flush_cache_cmd;
+ A_UINT32 update_mpduq_cmd;
+ A_UINT32 enqueue;
+ A_UINT32 enqueue_notify;
+ A_UINT32 notify_mpdu_at_head;
+ A_UINT32 notify_mpdu_state_valid;
+/*
+ * On receiving TQM_FLOW_NOT_EMPTY_STATUS from TQM, (on MSDUs being enqueued
+ * the flow is non empty), if the number of MSDUs is greater than the threshold,
+ * notify is incremented. UDP_THRESH counters are for UDP MSDUs, and NONUDP are
+ * for non-UDP MSDUs.
+ * MSDUQ_SWNOTIFY_UDP_THRESH1 threshold - sched_udp_notify1 is incremented
+ * MSDUQ_SWNOTIFY_UDP_THRESH2 threshold - sched_udp_notify2 is incremented
+ * MSDUQ_SWNOTIFY_NONUDP_THRESH1 threshold - sched_nonudp_notify1 is incremented
+ * MSDUQ_SWNOTIFY_NONUDP_THRESH2 threshold - sched_nonudp_notify2 is incremented
+ *
+ * Notify signifies that we trigger the scheduler.
+ */
+ A_UINT32 sched_udp_notify1;
+ A_UINT32 sched_udp_notify2;
+ A_UINT32 sched_nonudp_notify1;
+ A_UINT32 sched_nonudp_notify2;
} htt_tx_tqm_pdev_stats_tlv_v;
-#define HTT_TX_TQM_CMN_STATS_MAC_ID_M 0x000000ff
-#define HTT_TX_TQM_CMN_STATS_MAC_ID_S 0
+#define HTT_TX_TQM_CMN_STATS_MAC_ID_M 0x000000ff
+#define HTT_TX_TQM_CMN_STATS_MAC_ID_S 0
#define HTT_TX_TQM_CMN_STATS_MAC_ID_GET(_var) \
(((_var) & HTT_TX_TQM_CMN_STATS_MAC_ID_M) >> \
- HTT_TX_TQM_CMN_STATS_MAC_ID_S)
+ HTT_TX_TQM_CMN_STATS_MAC_ID_S)
#define HTT_TX_TQM_CMN_STATS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_TQM_CMN_STATS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_TQM_CMN_STATS_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMN_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_TQM_CMN_STATS_MAC_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -1767,6 +2150,8 @@
A_UINT32 q_not_empty;
A_UINT32 drop_notification;
A_UINT32 desc_threshold;
+ A_UINT32 hwsch_tqm_invalid_status;
+ A_UINT32 missed_tqm_gen_mpdus;
} htt_tx_tqm_cmn_stats_tlv;
typedef struct {
@@ -1791,40 +2176,40 @@
* Instead, use the constituent TLV structures to fill/parse.
*/
typedef struct {
- htt_tx_tqm_cmn_stats_tlv cmn_tlv;
- htt_tx_tqm_error_stats_tlv err_tlv;
- htt_tx_tqm_gen_mpdu_stats_tlv_v gen_mpdu_stats_tlv;
+ htt_tx_tqm_cmn_stats_tlv cmn_tlv;
+ htt_tx_tqm_error_stats_tlv err_tlv;
+ htt_tx_tqm_gen_mpdu_stats_tlv_v gen_mpdu_stats_tlv;
htt_tx_tqm_list_mpdu_stats_tlv_v list_mpdu_stats_tlv;
- htt_tx_tqm_list_mpdu_cnt_tlv_v list_mpdu_cnt_tlv;
- htt_tx_tqm_pdev_stats_tlv_v tqm_pdev_stats_tlv;
+ htt_tx_tqm_list_mpdu_cnt_tlv_v list_mpdu_cnt_tlv;
+ htt_tx_tqm_pdev_stats_tlv_v tqm_pdev_stats_tlv;
} htt_tx_tqm_pdev_stats_t;
/* == TQM CMDQ stats == */
-#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M 0x000000ff
-#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S 0
+#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M 0x000000ff
+#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S 0
-#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M 0x0000ff00
-#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S 8
+#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M 0x0000ff00
+#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S 8
#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_GET(_var) \
(((_var) & HTT_TX_TQM_CMDQ_STATUS_MAC_ID_M) >> \
- HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S)
+ HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S)
#define HTT_TX_TQM_CMDQ_STATUS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_TQM_CMDQ_STATUS_MAC_ID_S)); \
+ } while (0)
#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_GET(_var) \
(((_var) & HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_M) >> \
- HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S)
+ HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S)
#define HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_TQM_CMDQ_STATUS_CMDQ_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -1858,7 +2243,7 @@
*/
typedef struct {
struct _cmdq_stats {
- htt_stats_string_tlv cmdq_str_tlv;
+ htt_stats_string_tlv cmdq_str_tlv;
htt_tx_tqm_cmdq_status_tlv status_tlv;
} q[1];
} htt_tx_tqm_cmdq_stats_t;
@@ -1868,129 +2253,172 @@
/* Structures for tx de stats */
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 m1_packets;
- A_UINT32 m2_packets;
- A_UINT32 m3_packets;
- A_UINT32 m4_packets;
- A_UINT32 g1_packets;
- A_UINT32 g2_packets;
+ A_UINT32 m1_packets;
+ A_UINT32 m2_packets;
+ A_UINT32 m3_packets;
+ A_UINT32 m4_packets;
+ A_UINT32 g1_packets;
+ A_UINT32 g2_packets;
+ A_UINT32 rc4_packets;
+ A_UINT32 eap_packets;
+ A_UINT32 eapol_start_packets;
+ A_UINT32 eapol_logoff_packets;
+ A_UINT32 eapol_encap_asf_packets;
} htt_tx_de_eapol_packets_stats_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 ap_bss_peer_not_found;
- A_UINT32 ap_bcast_mcast_no_peer;
- A_UINT32 sta_delete_in_progress;
- A_UINT32 ibss_no_bss_peer;
- A_UINT32 invaild_vdev_type;
- A_UINT32 invalid_ast_peer_entry;
- A_UINT32 peer_entry_invalid;
- A_UINT32 ethertype_not_ip;
- A_UINT32 eapol_lookup_failed;
- A_UINT32 qpeer_not_allow_data;
- A_UINT32 fse_tid_override;
+ A_UINT32 ap_bss_peer_not_found;
+ A_UINT32 ap_bcast_mcast_no_peer;
+ A_UINT32 sta_delete_in_progress;
+ A_UINT32 ibss_no_bss_peer;
+ A_UINT32 invaild_vdev_type;
+ A_UINT32 invalid_ast_peer_entry;
+ A_UINT32 peer_entry_invalid;
+ A_UINT32 ethertype_not_ip;
+ A_UINT32 eapol_lookup_failed;
+ A_UINT32 qpeer_not_allow_data;
+ A_UINT32 fse_tid_override;
+ A_UINT32 ipv6_jumbogram_zero_length;
+ A_UINT32 qos_to_non_qos_in_prog;
+ A_UINT32 ap_bcast_mcast_eapol;
+ A_UINT32 unicast_on_ap_bss_peer;
+ A_UINT32 ap_vdev_invalid;
+ A_UINT32 incomplete_llc;
+ A_UINT32 eapol_duplicate_m3;
+ A_UINT32 eapol_duplicate_m4;
} htt_tx_de_classify_failed_stats_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 arp_packets;
- A_UINT32 igmp_packets;
- A_UINT32 dhcp_packets;
- A_UINT32 host_inspected;
- A_UINT32 htt_included;
- A_UINT32 htt_valid_mcs;
- A_UINT32 htt_valid_nss;
- A_UINT32 htt_valid_preamble_type;
- A_UINT32 htt_valid_chainmask;
- A_UINT32 htt_valid_guard_interval;
- A_UINT32 htt_valid_retries;
- A_UINT32 htt_valid_bw_info;
- A_UINT32 htt_valid_power;
- A_UINT32 htt_valid_key_flags;
- A_UINT32 htt_valid_no_encryption;
- A_UINT32 fse_entry_count;
- A_UINT32 fse_priority_be;
- A_UINT32 fse_priority_high;
- A_UINT32 fse_priority_low;
- A_UINT32 fse_traffic_ptrn_be;
- A_UINT32 fse_traffic_ptrn_over_sub;
- A_UINT32 fse_traffic_ptrn_bursty;
- A_UINT32 fse_traffic_ptrn_interactive;
- A_UINT32 fse_traffic_ptrn_periodic;
- A_UINT32 fse_hwqueue_alloc;
- A_UINT32 fse_hwqueue_created;
- A_UINT32 fse_hwqueue_send_to_host;
- A_UINT32 mcast_entry;
- A_UINT32 bcast_entry;
+ A_UINT32 arp_packets;
+ A_UINT32 igmp_packets;
+ A_UINT32 dhcp_packets;
+ A_UINT32 host_inspected;
+ A_UINT32 htt_included;
+ A_UINT32 htt_valid_mcs;
+ A_UINT32 htt_valid_nss;
+ A_UINT32 htt_valid_preamble_type;
+ A_UINT32 htt_valid_chainmask;
+ A_UINT32 htt_valid_guard_interval;
+ A_UINT32 htt_valid_retries;
+ A_UINT32 htt_valid_bw_info;
+ A_UINT32 htt_valid_power;
+ A_UINT32 htt_valid_key_flags;
+ A_UINT32 htt_valid_no_encryption;
+ A_UINT32 fse_entry_count;
+ A_UINT32 fse_priority_be;
+ A_UINT32 fse_priority_high;
+ A_UINT32 fse_priority_low;
+ A_UINT32 fse_traffic_ptrn_be;
+ A_UINT32 fse_traffic_ptrn_over_sub;
+ A_UINT32 fse_traffic_ptrn_bursty;
+ A_UINT32 fse_traffic_ptrn_interactive;
+ A_UINT32 fse_traffic_ptrn_periodic;
+ A_UINT32 fse_hwqueue_alloc;
+ A_UINT32 fse_hwqueue_created;
+ A_UINT32 fse_hwqueue_send_to_host;
+ A_UINT32 mcast_entry;
+ A_UINT32 bcast_entry;
+ A_UINT32 htt_update_peer_cache;
+ A_UINT32 htt_learning_frame;
+ A_UINT32 fse_invalid_peer;
+ /*
+ * mec_notify is HTT TX WBM multicast echo check notification
+ * from firmware to host. FW sends SA addresses to host for all
+ * multicast/broadcast packets received on STA side.
+ */
+ A_UINT32 mec_notify;
} htt_tx_de_classify_stats_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 eok;
- A_UINT32 classify_done;
- A_UINT32 lookup_failed;
- A_UINT32 send_host_dhcp;
- A_UINT32 send_host_mcast;
- A_UINT32 send_host_unknown_dest;
- A_UINT32 send_host;
- A_UINT32 status_invalid;
+ A_UINT32 eok;
+ A_UINT32 classify_done;
+ A_UINT32 lookup_failed;
+ A_UINT32 send_host_dhcp;
+ A_UINT32 send_host_mcast;
+ A_UINT32 send_host_unknown_dest;
+ A_UINT32 send_host;
+ A_UINT32 status_invalid;
} htt_tx_de_classify_status_stats_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 enqueued_pkts;
- A_UINT32 to_tqm;
- A_UINT32 to_tqm_bypass;
+ A_UINT32 enqueued_pkts;
+ A_UINT32 to_tqm;
+ A_UINT32 to_tqm_bypass;
} htt_tx_de_enqueue_packets_stats_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 discarded_pkts;
- A_UINT32 local_frames;
- A_UINT32 is_ext_msdu;
+ A_UINT32 discarded_pkts;
+ A_UINT32 local_frames;
+ A_UINT32 is_ext_msdu;
} htt_tx_de_enqueue_discard_stats_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
- A_UINT32 tcl_dummy_frame;
- A_UINT32 tqm_dummy_frame;
- A_UINT32 tqm_notify_frame;
- A_UINT32 fw2wbm_enq;
- A_UINT32 tqm_bypass_frame;
+ A_UINT32 tcl_dummy_frame;
+ A_UINT32 tqm_dummy_frame;
+ A_UINT32 tqm_notify_frame;
+ A_UINT32 fw2wbm_enq;
+ A_UINT32 tqm_bypass_frame;
} htt_tx_de_compl_stats_tlv;
-#define HTT_TX_DE_CMN_STATS_MAC_ID_M 0x000000ff
-#define HTT_TX_DE_CMN_STATS_MAC_ID_S 0
+#define HTT_TX_DE_CMN_STATS_MAC_ID_M 0x000000ff
+#define HTT_TX_DE_CMN_STATS_MAC_ID_S 0
#define HTT_TX_DE_CMN_STATS_MAC_ID_GET(_var) \
(((_var) & HTT_TX_DE_CMN_STATS_MAC_ID_M) >> \
- HTT_TX_DE_CMN_STATS_MAC_ID_S)
+ HTT_TX_DE_CMN_STATS_MAC_ID_S)
#define HTT_TX_DE_CMN_STATS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_DE_CMN_STATS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_DE_CMN_STATS_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_DE_CMN_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_DE_CMN_STATS_MAC_ID_S)); \
+ } while (0)
+
+/*
+ * The htt_tx_de_fw2wbm_ring_full_hist_tlv is a histogram of time we waited
+ * for the fw2wbm ring buffer. we are requesting a buffer in FW2WBM release
+ * ring,which may fail, due to non availability of buffer. Hence we sleep for
+ * 200us & again request for it. This is a histogram of time we wait, with
+ * bin of 200ms & there are 10 bin (2 seconds max)
+ * They are defined by the following macros in FW
+ * #define ENTRIES_PER_BIN_COUNT 1000 // per bin 1000 * 200us = 200ms
+ * #define RING_FULL_BIN_ENTRIES (WAL_TX_DE_FW2WBM_ALLOC_TIMEOUT_COUNT /
+ * ENTRIES_PER_BIN_COUNT)
+ */
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+
+ A_UINT32 fw2wbm_ring_full_hist[1];
+} htt_tx_de_fw2wbm_ring_full_hist_tlv;
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* BIT [ 7 : 0] :- mac_id
* BIT [31 : 8] :- reserved
*/
- A_UINT32 mac_id__word;
+ A_UINT32 mac_id__word;
/* Global Stats */
- A_UINT32 tcl2fw_entry_count;
- A_UINT32 not_to_fw;
- A_UINT32 invalid_pdev_vdev_peer;
- A_UINT32 tcl_res_invalid_addrx;
- A_UINT32 wbm2fw_entry_count;
- A_UINT32 invalid_pdev;
+ A_UINT32 tcl2fw_entry_count;
+ A_UINT32 not_to_fw;
+ A_UINT32 invalid_pdev_vdev_peer;
+ A_UINT32 tcl_res_invalid_addrx;
+ A_UINT32 wbm2fw_entry_count;
+ A_UINT32 invalid_pdev;
+ A_UINT32 tcl_res_addrx_timeout;
+ A_UINT32 invalid_vdev;
+ A_UINT32 invalid_tcl_exp_frame_desc;
} htt_tx_de_cmn_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_TX_DE_INFO
* TLV_TAGS:
* - HTT_STATS_TX_DE_CMN_TAG
+ * - HTT_STATS_TX_DE_FW2WBM_RING_FULL_HIST_TAG
* - HTT_STATS_TX_DE_EAPOL_PACKETS_TAG
* - HTT_STATS_TX_DE_CLASSIFY_STATS_TAG
* - HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG
@@ -2005,6 +2433,7 @@
*/
typedef struct {
htt_tx_de_cmn_stats_tlv cmn_tlv;
+ htt_tx_de_fw2wbm_ring_full_hist_tlv fw2wbm_hist_tlv;
htt_tx_de_eapol_packets_stats_tlv eapol_stats_tlv;
htt_tx_de_classify_stats_tlv classify_stats_tlv;
htt_tx_de_classify_failed_stats_tlv classify_failed_tlv;
@@ -2016,119 +2445,119 @@
/* == RING-IF STATS == */
/* DWORD num_elems__prefetch_tail_idx */
-#define HTT_RING_IF_STATS_NUM_ELEMS_M 0x0000ffff
-#define HTT_RING_IF_STATS_NUM_ELEMS_S 0
+#define HTT_RING_IF_STATS_NUM_ELEMS_M 0x0000ffff
+#define HTT_RING_IF_STATS_NUM_ELEMS_S 0
-#define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_M 0xffff0000
-#define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S 16
+#define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_M 0xffff0000
+#define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S 16
#define HTT_RING_IF_STATS_NUM_ELEMS_GET(_var) \
(((_var) & HTT_RING_IF_STATS_NUM_ELEMS_M) >> \
- HTT_RING_IF_STATS_NUM_ELEMS_S)
+ HTT_RING_IF_STATS_NUM_ELEMS_S)
#define HTT_RING_IF_STATS_NUM_ELEMS_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_NUM_ELEMS, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_STATS_NUM_ELEMS_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_NUM_ELEMS, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_STATS_NUM_ELEMS_S)); \
+ } while (0)
#define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_GET(_var) \
(((_var) & HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_M) >> \
- HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S)
+ HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S)
#define HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_PREFETCH_TAIL_IDX, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_PREFETCH_TAIL_IDX, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_STATS_PREFETCH_TAIL_IDX_S)); \
+ } while (0)
/* DWORD head_idx__tail_idx */
-#define HTT_RING_IF_STATS_HEAD_IDX_M 0x0000ffff
-#define HTT_RING_IF_STATS_HEAD_IDX_S 0
+#define HTT_RING_IF_STATS_HEAD_IDX_M 0x0000ffff
+#define HTT_RING_IF_STATS_HEAD_IDX_S 0
-#define HTT_RING_IF_STATS_TAIL_IDX_M 0xffff0000
-#define HTT_RING_IF_STATS_TAIL_IDX_S 16
+#define HTT_RING_IF_STATS_TAIL_IDX_M 0xffff0000
+#define HTT_RING_IF_STATS_TAIL_IDX_S 16
#define HTT_RING_IF_STATS_HEAD_IDX_GET(_var) \
(((_var) & HTT_RING_IF_STATS_HEAD_IDX_M) >> \
- HTT_RING_IF_STATS_HEAD_IDX_S)
+ HTT_RING_IF_STATS_HEAD_IDX_S)
#define HTT_RING_IF_STATS_HEAD_IDX_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_HEAD_IDX, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_STATS_HEAD_IDX_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_HEAD_IDX, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_STATS_HEAD_IDX_S)); \
+ } while (0)
#define HTT_RING_IF_STATS_TAIL_IDX_GET(_var) \
(((_var) & HTT_RING_IF_STATS_TAIL_IDX_M) >> \
- HTT_RING_IF_STATS_TAIL_IDX_S)
+ HTT_RING_IF_STATS_TAIL_IDX_S)
#define HTT_RING_IF_STATS_TAIL_IDX_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_TAIL_IDX, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_STATS_TAIL_IDX_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_TAIL_IDX, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_STATS_TAIL_IDX_S)); \
+ } while (0)
/* DWORD shadow_head_idx__shadow_tail_idx */
-#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_M 0x0000ffff
-#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S 0
+#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_M 0x0000ffff
+#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S 0
-#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_M 0xffff0000
-#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S 16
+#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_M 0xffff0000
+#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S 16
#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_GET(_var) \
(((_var) & HTT_RING_IF_STATS_SHADOW_HEAD_IDX_M) >> \
- HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S)
+ HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S)
#define HTT_RING_IF_STATS_SHADOW_HEAD_IDX_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_SHADOW_HEAD_IDX, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_SHADOW_HEAD_IDX, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_STATS_SHADOW_HEAD_IDX_S)); \
+ } while (0)
#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_GET(_var) \
(((_var) & HTT_RING_IF_STATS_SHADOW_TAIL_IDX_M) >> \
- HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S)
+ HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S)
#define HTT_RING_IF_STATS_SHADOW_TAIL_IDX_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_SHADOW_TAIL_IDX, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_SHADOW_TAIL_IDX, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_STATS_SHADOW_TAIL_IDX_S)); \
+ } while (0)
/* DWORD lwm_thresh__hwm_thresh */
-#define HTT_RING_IF_STATS_LWM_THRESHOLD_M 0x0000ffff
-#define HTT_RING_IF_STATS_LWM_THRESHOLD_S 0
+#define HTT_RING_IF_STATS_LWM_THRESHOLD_M 0x0000ffff
+#define HTT_RING_IF_STATS_LWM_THRESHOLD_S 0
-#define HTT_RING_IF_STATS_HWM_THRESHOLD_M 0xffff0000
-#define HTT_RING_IF_STATS_HWM_THRESHOLD_S 16
+#define HTT_RING_IF_STATS_HWM_THRESHOLD_M 0xffff0000
+#define HTT_RING_IF_STATS_HWM_THRESHOLD_S 16
#define HTT_RING_IF_STATS_LWM_THRESHOLD_GET(_var) \
(((_var) & HTT_RING_IF_STATS_LWM_THRESHOLD_M) >> \
- HTT_RING_IF_STATS_LWM_THRESHOLD_S)
+ HTT_RING_IF_STATS_LWM_THRESHOLD_S)
#define HTT_RING_IF_STATS_LWM_THRESHOLD_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_LWM_THRESHOLD, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_STATS_LWM_THRESHOLD_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_LWM_THRESHOLD, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_STATS_LWM_THRESHOLD_S)); \
+ } while (0)
#define HTT_RING_IF_STATS_HWM_THRESHOLD_GET(_var) \
(((_var) & HTT_RING_IF_STATS_HWM_THRESHOLD_M) >> \
- HTT_RING_IF_STATS_HWM_THRESHOLD_S)
+ HTT_RING_IF_STATS_HWM_THRESHOLD_S)
#define HTT_RING_IF_STATS_HWM_THRESHOLD_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_HWM_THRESHOLD, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_STATS_HWM_THRESHOLD_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_STATS_HWM_THRESHOLD, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_STATS_HWM_THRESHOLD_S)); \
+ } while (0)
-
-#define HTT_STATS_LOW_WM_BINS 5
-#define HTT_STATS_HIGH_WM_BINS 5
+#define HTT_STATS_LOW_WM_BINS 5
+#define HTT_STATS_HIGH_WM_BINS 5
typedef struct {
A_UINT32 base_addr; /* DWORD aligned base memory address of the ring */
+
A_UINT32 elem_size; /* size of each ring element */
/* BIT [15 : 0] :- num_elems
@@ -2152,25 +2581,25 @@
A_UINT32 underrun_hit_count;
A_UINT32 prod_blockwait_count;
A_UINT32 cons_blockwait_count;
- A_UINT32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; /* FIX THIS: explain what each array element is for */
+ A_UINT32 low_wm_hit_count[HTT_STATS_LOW_WM_BINS]; /* FIX THIS: explain what each array element is for */
A_UINT32 high_wm_hit_count[HTT_STATS_HIGH_WM_BINS]; /* FIX THIS: explain what each array element is for */
} htt_ring_if_stats_tlv;
-#define HTT_RING_IF_CMN_MAC_ID_M 0x000000ff
-#define HTT_RING_IF_CMN_MAC_ID_S 0
+#define HTT_RING_IF_CMN_MAC_ID_M 0x000000ff
+#define HTT_RING_IF_CMN_MAC_ID_S 0
#define HTT_RING_IF_CMN_MAC_ID_GET(_var) \
(((_var) & HTT_RING_IF_CMN_MAC_ID_M) >> \
- HTT_RING_IF_CMN_MAC_ID_S)
+ HTT_RING_IF_CMN_MAC_ID_S)
#define HTT_RING_IF_CMN_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RING_IF_CMN_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_RING_IF_CMN_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RING_IF_CMN_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_RING_IF_CMN_MAC_ID_S)); \
+ } while (0)
typedef struct {
- htt_tlv_hdr_t tlv_hdr;
+ htt_tlv_hdr_t tlv_hdr;
/* BIT [ 7 : 0] :- mac_id
* BIT [31 : 8] :- reserved
@@ -2193,7 +2622,7 @@
htt_ring_if_cmn_tlv cmn_tlv;
/* Variable based on the Number of records. */
struct _ring_if {
- htt_stats_string_tlv ring_str_tlv;
+ htt_stats_string_tlv ring_str_tlv;
htt_ring_if_stats_tlv ring_tlv;
} r[1];
} htt_ring_if_stats_t;
@@ -2204,13 +2633,13 @@
/* NOTE: Variable length TLV, use length spec to infer array size */
typedef struct {
- htt_tlv_hdr_t tlv_hdr;
+ htt_tlv_hdr_t tlv_hdr;
/* Number of DWORDS used per user and per client */
A_UINT32 dwords_used_by_user_n[1];
} htt_sfm_client_user_tlv_v;
typedef struct {
- htt_tlv_hdr_t tlv_hdr;
+ htt_tlv_hdr_t tlv_hdr;
/* Client ID */
A_UINT32 client_id;
/* Minimum number of buffers */
@@ -2227,21 +2656,21 @@
A_UINT32 num_users;
} htt_sfm_client_tlv;
-#define HTT_SFM_CMN_MAC_ID_M 0x000000ff
-#define HTT_SFM_CMN_MAC_ID_S 0
+#define HTT_SFM_CMN_MAC_ID_M 0x000000ff
+#define HTT_SFM_CMN_MAC_ID_S 0
#define HTT_SFM_CMN_MAC_ID_GET(_var) \
(((_var) & HTT_SFM_CMN_MAC_ID_M) >> \
- HTT_SFM_CMN_MAC_ID_S)
+ HTT_SFM_CMN_MAC_ID_S)
#define HTT_SFM_CMN_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SFM_CMN_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_SFM_CMN_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SFM_CMN_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_SFM_CMN_MAC_ID_S)); \
+ } while (0)
typedef struct {
- htt_tlv_hdr_t tlv_hdr;
+ htt_tlv_hdr_t tlv_hdr;
/* BIT [ 7 : 0] :- mac_id
* BIT [31 : 8] :- reserved
@@ -2254,7 +2683,7 @@
/* DEALLOCATE_BUFFERS, refer to register SFM_R0_DEALLOCATE_BUFFERS */
A_UINT32 deallocate_bufs;
/* Number of Records */
- A_UINT32 num_records;
+ A_UINT32 num_records;
} htt_sfm_cmn_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_RING_IF_INFO
@@ -2272,177 +2701,176 @@
htt_sfm_cmn_tlv cmn_tlv;
/* Variable based on the Number of records. */
struct _sfm_client {
- htt_stats_string_tlv client_str_tlv;
- htt_sfm_client_tlv client_tlv;
+ htt_stats_string_tlv client_str_tlv;
+ htt_sfm_client_tlv client_tlv;
htt_sfm_client_user_tlv_v user_tlv;
} r[1];
} htt_sfm_stats_t;
/* == SRNG STATS == */
/* DWORD mac_id__ring_id__arena__ep */
-#define HTT_SRING_STATS_MAC_ID_M 0x000000ff
-#define HTT_SRING_STATS_MAC_ID_S 0
+#define HTT_SRING_STATS_MAC_ID_M 0x000000ff
+#define HTT_SRING_STATS_MAC_ID_S 0
-#define HTT_SRING_STATS_RING_ID_M 0x0000ff00
-#define HTT_SRING_STATS_RING_ID_S 8
+#define HTT_SRING_STATS_RING_ID_M 0x0000ff00
+#define HTT_SRING_STATS_RING_ID_S 8
-#define HTT_SRING_STATS_ARENA_M 0x00ff0000
-#define HTT_SRING_STATS_ARENA_S 16
+#define HTT_SRING_STATS_ARENA_M 0x00ff0000
+#define HTT_SRING_STATS_ARENA_S 16
-#define HTT_SRING_STATS_EP_TYPE_M 0x01000000
-#define HTT_SRING_STATS_EP_TYPE_S 24
+#define HTT_SRING_STATS_EP_TYPE_M 0x01000000
+#define HTT_SRING_STATS_EP_TYPE_S 24
#define HTT_SRING_STATS_MAC_ID_GET(_var) \
(((_var) & HTT_SRING_STATS_MAC_ID_M) >> \
- HTT_SRING_STATS_MAC_ID_S)
+ HTT_SRING_STATS_MAC_ID_S)
#define HTT_SRING_STATS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_MAC_ID_S)); \
+ } while (0)
#define HTT_SRING_STATS_RING_ID_GET(_var) \
(((_var) & HTT_SRING_STATS_RING_ID_M) >> \
- HTT_SRING_STATS_RING_ID_S)
+ HTT_SRING_STATS_RING_ID_S)
#define HTT_SRING_STATS_RING_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_RING_ID, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_RING_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_RING_ID, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_RING_ID_S)); \
+ } while (0)
#define HTT_SRING_STATS_ARENA_GET(_var) \
(((_var) & HTT_SRING_STATS_ARENA_M) >> \
- HTT_SRING_STATS_ARENA_S)
+ HTT_SRING_STATS_ARENA_S)
#define HTT_SRING_STATS_ARENA_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_ARENA, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_ARENA_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_ARENA, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_ARENA_S)); \
+ } while (0)
#define HTT_SRING_STATS_EP_TYPE_GET(_var) \
(((_var) & HTT_SRING_STATS_EP_TYPE_M) >> \
- HTT_SRING_STATS_EP_TYPE_S)
+ HTT_SRING_STATS_EP_TYPE_S)
#define HTT_SRING_STATS_EP_TYPE_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_EP_TYPE, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_EP_TYPE_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_EP_TYPE, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_EP_TYPE_S)); \
+ } while (0)
/* DWORD num_avail_words__num_valid_words */
-#define HTT_SRING_STATS_NUM_AVAIL_WORDS_M 0x0000ffff
-#define HTT_SRING_STATS_NUM_AVAIL_WORDS_S 0
+#define HTT_SRING_STATS_NUM_AVAIL_WORDS_M 0x0000ffff
+#define HTT_SRING_STATS_NUM_AVAIL_WORDS_S 0
-#define HTT_SRING_STATS_NUM_VALID_WORDS_M 0xffff0000
-#define HTT_SRING_STATS_NUM_VALID_WORDS_S 16
+#define HTT_SRING_STATS_NUM_VALID_WORDS_M 0xffff0000
+#define HTT_SRING_STATS_NUM_VALID_WORDS_S 16
#define HTT_SRING_STATS_NUM_AVAIL_WORDS_GET(_var) \
(((_var) & HTT_SRING_STATS_NUM_AVAIL_WORDS_M) >> \
- HTT_SRING_STATS_NUM_AVAIL_WORDS_S)
+ HTT_SRING_STATS_NUM_AVAIL_WORDS_S)
#define HTT_SRING_STATS_NUM_AVAIL_WORDS_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_AVAIL_WORDS, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_NUM_AVAIL_WORDS_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_AVAIL_WORDS, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_NUM_AVAIL_WORDS_S)); \
+ } while (0)
#define HTT_SRING_STATS_NUM_VALID_WORDS_GET(_var) \
(((_var) & HTT_SRING_STATS_NUM_VALID_WORDS_M) >> \
- HTT_SRING_STATS_NUM_VALID_WORDS_S)
+ HTT_SRING_STATS_NUM_VALID_WORDS_S)
#define HTT_SRING_STATS_NUM_VALID_WORDS_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_VALID_WORDS, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_NUM_VALID_WORDS_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_NUM_VALID_WORDS, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_NUM_VALID_WORDS_S)); \
+ } while (0)
/* DWORD head_ptr__tail_ptr */
-#define HTT_SRING_STATS_HEAD_PTR_M 0x0000ffff
-#define HTT_SRING_STATS_HEAD_PTR_S 0
+#define HTT_SRING_STATS_HEAD_PTR_M 0x0000ffff
+#define HTT_SRING_STATS_HEAD_PTR_S 0
-#define HTT_SRING_STATS_TAIL_PTR_M 0xffff0000
-#define HTT_SRING_STATS_TAIL_PTR_S 16
+#define HTT_SRING_STATS_TAIL_PTR_M 0xffff0000
+#define HTT_SRING_STATS_TAIL_PTR_S 16
#define HTT_SRING_STATS_HEAD_PTR_GET(_var) \
(((_var) & HTT_SRING_STATS_HEAD_PTR_M) >> \
- HTT_SRING_STATS_HEAD_PTR_S)
+ HTT_SRING_STATS_HEAD_PTR_S)
#define HTT_SRING_STATS_HEAD_PTR_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_HEAD_PTR, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_HEAD_PTR_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_HEAD_PTR, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_HEAD_PTR_S)); \
+ } while (0)
#define HTT_SRING_STATS_TAIL_PTR_GET(_var) \
(((_var) & HTT_SRING_STATS_TAIL_PTR_M) >> \
- HTT_SRING_STATS_TAIL_PTR_S)
+ HTT_SRING_STATS_TAIL_PTR_S)
#define HTT_SRING_STATS_TAIL_PTR_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_TAIL_PTR, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_TAIL_PTR_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_TAIL_PTR, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_TAIL_PTR_S)); \
+ } while (0)
/* DWORD consumer_empty__producer_full */
-#define HTT_SRING_STATS_CONSUMER_EMPTY_M 0x0000ffff
-#define HTT_SRING_STATS_CONSUMER_EMPTY_S 0
+#define HTT_SRING_STATS_CONSUMER_EMPTY_M 0x0000ffff
+#define HTT_SRING_STATS_CONSUMER_EMPTY_S 0
-#define HTT_SRING_STATS_PRODUCER_FULL_M 0xffff0000
-#define HTT_SRING_STATS_PRODUCER_FULL_S 16
+#define HTT_SRING_STATS_PRODUCER_FULL_M 0xffff0000
+#define HTT_SRING_STATS_PRODUCER_FULL_S 16
#define HTT_SRING_STATS_CONSUMER_EMPTY_GET(_var) \
(((_var) & HTT_SRING_STATS_CONSUMER_EMPTY_M) >> \
- HTT_SRING_STATS_CONSUMER_EMPTY_S)
+ HTT_SRING_STATS_CONSUMER_EMPTY_S)
#define HTT_SRING_STATS_CONSUMER_EMPTY_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_CONSUMER_EMPTY, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_CONSUMER_EMPTY_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_CONSUMER_EMPTY, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_CONSUMER_EMPTY_S)); \
+ } while (0)
#define HTT_SRING_STATS_PRODUCER_FULL_GET(_var) \
(((_var) & HTT_SRING_STATS_PRODUCER_FULL_M) >> \
- HTT_SRING_STATS_PRODUCER_FULL_S)
+ HTT_SRING_STATS_PRODUCER_FULL_S)
#define HTT_SRING_STATS_PRODUCER_FULL_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_PRODUCER_FULL, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_PRODUCER_FULL_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_PRODUCER_FULL, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_PRODUCER_FULL_S)); \
+ } while (0)
/* DWORD prefetch_count__internal_tail_ptr */
-#define HTT_SRING_STATS_PREFETCH_COUNT_M 0x0000ffff
-#define HTT_SRING_STATS_PREFETCH_COUNT_S 0
+#define HTT_SRING_STATS_PREFETCH_COUNT_M 0x0000ffff
+#define HTT_SRING_STATS_PREFETCH_COUNT_S 0
-#define HTT_SRING_STATS_INTERNAL_TP_M 0xffff0000
-#define HTT_SRING_STATS_INTERNAL_TP_S 16
+#define HTT_SRING_STATS_INTERNAL_TP_M 0xffff0000
+#define HTT_SRING_STATS_INTERNAL_TP_S 16
#define HTT_SRING_STATS_PREFETCH_COUNT_GET(_var) \
(((_var) & HTT_SRING_STATS_PREFETCH_COUNT_M) >> \
- HTT_SRING_STATS_PREFETCH_COUNT_S)
+ HTT_SRING_STATS_PREFETCH_COUNT_S)
#define HTT_SRING_STATS_PREFETCH_COUNT_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_PREFETCH_COUNT, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_PREFETCH_COUNT_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_PREFETCH_COUNT, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_PREFETCH_COUNT_S)); \
+ } while (0)
#define HTT_SRING_STATS_INTERNAL_TP_GET(_var) \
(((_var) & HTT_SRING_STATS_INTERNAL_TP_M) >> \
- HTT_SRING_STATS_INTERNAL_TP_S)
+ HTT_SRING_STATS_INTERNAL_TP_S)
#define HTT_SRING_STATS_INTERNAL_TP_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_SRING_STATS_INTERNAL_TP, _val); \
- ((_var) |= ((_val) << HTT_SRING_STATS_INTERNAL_TP_S)); \
- } while (0)
-
+ do { \
+ HTT_CHECK_SET_VAL(HTT_SRING_STATS_INTERNAL_TP, _val); \
+ ((_var) |= ((_val) << HTT_SRING_STATS_INTERNAL_TP_S)); \
+ } while (0)
typedef struct {
- htt_tlv_hdr_t tlv_hdr;
+ htt_tlv_hdr_t tlv_hdr;
/* BIT [ 7 : 0] :- mac_id
* BIT [15 : 8] :- ring_id
@@ -2482,8 +2910,8 @@
} htt_sring_stats_tlv;
typedef struct {
- htt_tlv_hdr_t tlv_hdr;
- A_UINT32 num_records;
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 num_records;
} htt_sring_cmn_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_SRNG_INFO
@@ -2501,35 +2929,38 @@
/* Variable based on the Number of records. */
struct _sring_stats {
htt_stats_string_tlv sring_str_tlv;
- htt_sring_stats_tlv sring_stats_tlv;
+ htt_sring_stats_tlv sring_stats_tlv;
} r[1];
} htt_sring_stats_t;
-
/* == PDEV TX RATE CTRL STATS == */
-#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12
-#define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4
-#define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5
-#define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
-#define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
-#define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
-#define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
-#define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
-#define HTT_TX_PDEV_STATS_NUM_LTF 4
+#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12
+#define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4
+#define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5
+#define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4
+#define HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
+#define HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
+#define HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
+#define HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
+#define HTT_TX_PDEV_STATS_NUM_LTF 4
+#define HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6
+#define HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \
+ (HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \
+ HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS)
-#define HTT_TX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff
-#define HTT_TX_PDEV_RATE_STATS_MAC_ID_S 0
+#define HTT_TX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff
+#define HTT_TX_PDEV_RATE_STATS_MAC_ID_S 0
#define HTT_TX_PDEV_RATE_STATS_MAC_ID_GET(_var) \
(((_var) & HTT_TX_PDEV_RATE_STATS_MAC_ID_M) >> \
- HTT_TX_PDEV_RATE_STATS_MAC_ID_S)
+ HTT_TX_PDEV_RATE_STATS_MAC_ID_S)
#define HTT_TX_PDEV_RATE_STATS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TX_PDEV_RATE_STATS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TX_PDEV_RATE_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_TX_PDEV_RATE_STATS_MAC_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -2552,7 +2983,7 @@
A_UINT32 tx_mu_mcs[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
A_UINT32 tx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; /* element 0,1, ...7 -> NSS 1,2, ...8 */
- A_UINT32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
+ A_UINT32 tx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
A_UINT32 tx_stbc[HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
A_UINT32 tx_pream[HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES];
@@ -2605,6 +3036,8 @@
A_UINT32 ac_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
A_UINT32 ax_mu_mimo_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
A_UINT32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS];
+ A_UINT32 trigger_type_11ax[HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES];
+ A_UINT32 tx_11ax_su_ext;
} htt_tx_pdev_rate_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE
@@ -2619,32 +3052,37 @@
htt_tx_pdev_rate_stats_tlv rate_tlv;
} htt_tx_pdev_rate_stats_t;
-
/* == PDEV RX RATE CTRL STATS == */
-#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12
-#define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4
-#define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5
-#define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4
-#define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
-#define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
+#define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4
+#define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8
+#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12
+#define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4
+#define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5
+#define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4
+#define HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8
+#define HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT
+#define HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8
+#define HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8
+#define HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS 16
+#define HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6
-#define HTT_RX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff
-#define HTT_RX_PDEV_RATE_STATS_MAC_ID_S 0
+#define HTT_RX_PDEV_RATE_STATS_MAC_ID_M 0x000000ff
+#define HTT_RX_PDEV_RATE_STATS_MAC_ID_S 0
#define HTT_RX_PDEV_RATE_STATS_MAC_ID_GET(_var) \
(((_var) & HTT_RX_PDEV_RATE_STATS_MAC_ID_M) >> \
- HTT_RX_PDEV_RATE_STATS_MAC_ID_S)
+ HTT_RX_PDEV_RATE_STATS_MAC_ID_S)
#define HTT_RX_PDEV_RATE_STATS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RX_PDEV_RATE_STATS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_RX_PDEV_RATE_STATS_MAC_ID_S)); \
- } while (0)
-
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PDEV_RATE_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_RX_PDEV_RATE_STATS_MAC_ID_S)); \
+ } while (0)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
+
/* BIT [ 7 : 0] :- mac_id
* BIT [31 : 8] :- reserved
*/
@@ -2665,12 +3103,72 @@
A_UINT32 rx_stbc[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
A_UINT32 rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; /* element 0: 20 MHz, 1: 40 MHz, 2: 80 MHz, 3: 160 and 80+80 MHz */
A_UINT32 rx_pream[HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES];
- A_UINT8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; /* units = dB above noise floor */
+ A_UINT8 rssi_chain[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; /* units = dB above noise floor */
/* Counters to track number of rx packets in each GI in each mcs (0-11) */
A_UINT32 rx_gi[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
-} htt_rx_pdev_rate_stats_tlv;
+ A_INT32 rssi_in_dbm; /* rx Signal Strength value in dBm unit */
+ A_UINT32 rx_11ax_su_ext;
+ A_UINT32 rx_11ac_mumimo;
+ A_UINT32 rx_11ax_mumimo;
+ A_UINT32 rx_11ax_ofdma;
+ A_UINT32 txbf;
+ A_UINT32 rx_legacy_cck_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS];
+ A_UINT32 rx_legacy_ofdm_rate[HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS];
+ A_UINT32 rx_active_dur_us_low;
+ A_UINT32 rx_active_dur_us_high;
+
+ A_UINT32 rx_11ax_ul_ofdma;
+
+ A_UINT32 ul_ofdma_rx_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
+ A_UINT32 ul_ofdma_rx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
+ A_UINT32 ul_ofdma_rx_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS];
+ A_UINT32 ul_ofdma_rx_bw[HTT_TX_PDEV_STATS_NUM_BW_COUNTERS];
+ A_UINT32 ul_ofdma_rx_stbc;
+ A_UINT32 ul_ofdma_rx_ldpc;
+
+ /* record the stats for each user index */
+ A_UINT32 rx_ulofdma_non_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */
+ A_UINT32 rx_ulofdma_data_ppdu[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* ppdu level */
+ A_UINT32 rx_ulofdma_mpdu_ok[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */
+ A_UINT32 rx_ulofdma_mpdu_fail[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* mpdu level */
+
+ A_UINT32 nss_count;
+ A_UINT32 pilot_count;
+ /* RxEVM stats in dB */
+ A_INT32 rx_pilot_evm_dB[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_PER_NSS];
+ /* rx_pilot_evm_dB_mean:
+ * EVM mean across pilots, computed as
+ * mean(10*log10(rx_pilot_evm_linear)) = mean(rx_pilot_evm_dB)
+ */
+ A_INT32 rx_pilot_evm_dB_mean[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS];
+ A_INT8 rx_ul_fd_rssi[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; /* dBm units */
+ /* per_chain_rssi_pkt_type:
+ * This field shows what type of rx frame the per-chain RSSI was computed
+ * on, by recording the frame type and sub-type as bit-fields within this
+ * field:
+ * BIT [3 : 0] :- IEEE80211_FC0_TYPE
+ * BIT [7 : 4] :- IEEE80211_FC0_SUBTYPE
+ * BIT [31 : 8] :- Reserved
+ */
+ A_UINT32 per_chain_rssi_pkt_type;
+ A_INT8 rx_per_chain_rssi_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_COUNTERS];
+ A_UINT32 rx_su_ndpa;
+ A_UINT32 rx_11ax_su_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
+ A_UINT32 rx_mu_ndpa;
+ A_UINT32 rx_11ax_mu_txbf_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
+ A_UINT32 rx_br_poll;
+ A_UINT32 rx_11ax_dl_ofdma_mcs[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS];
+ A_UINT32 rx_11ax_dl_ofdma_ru[HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS];
+
+ A_UINT32 rx_ulmumimo_non_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; /* ppdu level */
+ A_UINT32 rx_ulmumimo_data_ppdu[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; /* ppdu level */
+ A_UINT32 rx_ulmumimo_mpdu_ok[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; /* mpdu level */
+ A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; /* mpdu level */
+ A_UINT32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
+ A_UINT32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER];
+} htt_rx_pdev_rate_stats_tlv;
/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE
* TLV_TAGS:
@@ -2684,7 +3182,6 @@
htt_rx_pdev_rate_stats_tlv rate_tlv;
} htt_rx_pdev_rate_stats_t;
-
/* == RX PDEV/SOC STATS == */
typedef struct {
@@ -2725,7 +3222,6 @@
A_UINT32 refill_ring_empty_cnt[1]; /* HTT_RX_STATS_REFILL_MAX_RING */
} htt_rx_soc_fw_refill_ring_empty_tlv_v;
-
#define HTT_RX_SOC_FW_REFILL_RING_EMPTY_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems))
/* NOTE: Variable length TLV, use length spec to infer array size */
@@ -2737,22 +3233,22 @@
/* RXDMA error code from WBM released packets */
typedef enum {
- HTT_RX_RXDMA_OVERFLOW_ERR = 0,
- HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1,
- HTT_RX_RXDMA_FCS_ERR = 2,
- HTT_RX_RXDMA_DECRYPT_ERR = 3,
- HTT_RX_RXDMA_TKIP_MIC_ERR = 4,
- HTT_RX_RXDMA_UNECRYPTED_ERR = 5,
- HTT_RX_RXDMA_MSDU_LEN_ERR = 6,
- HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7,
- HTT_RX_RXDMA_WIFI_PARSE_ERR = 8,
- HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9,
- HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10,
- HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11,
- HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12,
- HTT_RX_RXDMA_FLUSH_REQUEST = 13,
- HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14,
- HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15,
+ HTT_RX_RXDMA_OVERFLOW_ERR = 0,
+ HTT_RX_RXDMA_MPDU_LENGTH_ERR = 1,
+ HTT_RX_RXDMA_FCS_ERR = 2,
+ HTT_RX_RXDMA_DECRYPT_ERR = 3,
+ HTT_RX_RXDMA_TKIP_MIC_ERR = 4,
+ HTT_RX_RXDMA_UNECRYPTED_ERR = 5,
+ HTT_RX_RXDMA_MSDU_LEN_ERR = 6,
+ HTT_RX_RXDMA_MSDU_LIMIT_ERR = 7,
+ HTT_RX_RXDMA_WIFI_PARSE_ERR = 8,
+ HTT_RX_RXDMA_AMSDU_PARSE_ERR = 9,
+ HTT_RX_RXDMA_SA_TIMEOUT_ERR = 10,
+ HTT_RX_RXDMA_DA_TIMEOUT_ERR = 11,
+ HTT_RX_RXDMA_FLOW_TIMEOUT_ERR = 12,
+ HTT_RX_RXDMA_FLUSH_REQUEST = 13,
+ HTT_RX_RXDMA_ERR_CODE_RVSD0 = 14,
+ HTT_RX_RXDMA_ERR_CODE_RVSD1 = 15,
/*
* This MAX_ERR_CODE should not be used in any host/target messages,
@@ -2768,33 +3264,33 @@
htt_tlv_hdr_t tlv_hdr;
/* NOTE:
- * The mapping of RXDMA error types to rxdma_err array elements is HW dependent.
- * It is expected but not required that the target will provide a rxdma_err element
- * for each of the htt_rx_rxdma_error_code_enum values, up to but not including
- * MAX_ERR_CODE. The host should ignore any array elements whose
- * indices are >= the MAX_ERR_CODE value the host was compiled with.
- */
+ * The mapping of RXDMA error types to rxdma_err array elements is HW dependent.
+ * It is expected but not required that the target will provide a rxdma_err element
+ * for each of the htt_rx_rxdma_error_code_enum values, up to but not including
+ * MAX_ERR_CODE. The host should ignore any array elements whose
+ * indices are >= the MAX_ERR_CODE value the host was compiled with.
+ */
A_UINT32 rxdma_err[1]; /* HTT_RX_RXDMA_MAX_ERR_CODE */
} htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v;
/* REO error code from WBM released packets */
typedef enum {
- HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0,
- HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1,
- HTT_RX_AMPDU_IN_NON_BA = 2,
- HTT_RX_NON_BA_DUPLICATE = 3,
- HTT_RX_BA_DUPLICATE = 4,
- HTT_RX_REGULAR_FRAME_2K_JUMP = 5,
- HTT_RX_BAR_FRAME_2K_JUMP = 6,
- HTT_RX_REGULAR_FRAME_OOR = 7,
- HTT_RX_BAR_FRAME_OOR = 8,
- HTT_RX_BAR_FRAME_NO_BA_SESSION = 9,
- HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10,
- HTT_RX_PN_CHECK_FAILED = 11,
- HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12,
- HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13,
- HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14,
- HTT_RX_REO_ERR_CODE_RVSD = 15,
+ HTT_RX_REO_QUEUE_DESC_ADDR_ZERO = 0,
+ HTT_RX_REO_QUEUE_DESC_NOT_VALID = 1,
+ HTT_RX_AMPDU_IN_NON_BA = 2,
+ HTT_RX_NON_BA_DUPLICATE = 3,
+ HTT_RX_BA_DUPLICATE = 4,
+ HTT_RX_REGULAR_FRAME_2K_JUMP = 5,
+ HTT_RX_BAR_FRAME_2K_JUMP = 6,
+ HTT_RX_REGULAR_FRAME_OOR = 7,
+ HTT_RX_BAR_FRAME_OOR = 8,
+ HTT_RX_BAR_FRAME_NO_BA_SESSION = 9,
+ HTT_RX_BAR_FRAME_SN_EQUALS_SSN = 10,
+ HTT_RX_PN_CHECK_FAILED = 11,
+ HTT_RX_2K_ERROR_HANDLING_FLAG_SET = 12,
+ HTT_RX_PN_ERROR_HANDLING_FLAG_SET = 13,
+ HTT_RX_QUEUE_DESCRIPTOR_BLOCKED_SET = 14,
+ HTT_RX_REO_ERR_CODE_RVSD = 15,
/*
* This MAX_ERR_CODE should not be used in any host/target messages,
@@ -2810,12 +3306,12 @@
htt_tlv_hdr_t tlv_hdr;
/* NOTE:
- * The mapping of REO error types to reo_err array elements is HW dependent.
- * It is expected but not required that the target will provide a rxdma_err element
- * for each of the htt_rx_reo_error_code_enum values, up to but not including
- * MAX_ERR_CODE. The host should ignore any array elements whose
- * indices are >= the MAX_ERR_CODE value the host was compiled with.
- */
+ * The mapping of REO error types to reo_err array elements is HW dependent.
+ * It is expected but not required that the target will provide a rxdma_err element
+ * for each of the htt_rx_reo_error_code_enum values, up to but not including
+ * MAX_ERR_CODE. The host should ignore any array elements whose
+ * indices are >= the MAX_ERR_CODE value the host was compiled with.
+ */
A_UINT32 reo_err[1]; /* HTT_RX_REO_MAX_ERR_CODE */
} htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v;
@@ -2824,28 +3320,28 @@
* Instead, use the constituent TLV structures to fill/parse.
*/
typedef struct {
- htt_rx_soc_fw_stats_tlv fw_tlv;
- htt_rx_soc_fw_refill_ring_empty_tlv_v fw_refill_ring_empty_tlv;
- htt_rx_soc_fw_refill_ring_num_refill_tlv_v fw_refill_ring_num_refill_tlv;
+ htt_rx_soc_fw_stats_tlv fw_tlv;
+ htt_rx_soc_fw_refill_ring_empty_tlv_v fw_refill_ring_empty_tlv;
+ htt_rx_soc_fw_refill_ring_num_refill_tlv_v fw_refill_ring_num_refill_tlv;
htt_rx_soc_fw_refill_ring_num_rxdma_err_tlv_v fw_refill_ring_num_rxdma_err_tlv;
- htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v fw_refill_ring_num_reo_err_tlv;
+ htt_rx_soc_fw_refill_ring_num_reo_err_tlv_v fw_refill_ring_num_reo_err_tlv;
} htt_rx_soc_stats_t;
/* == RX PDEV STATS == */
-#define HTT_RX_PDEV_FW_STATS_MAC_ID_M 0x000000ff
-#define HTT_RX_PDEV_FW_STATS_MAC_ID_S 0
+#define HTT_RX_PDEV_FW_STATS_MAC_ID_M 0x000000ff
+#define HTT_RX_PDEV_FW_STATS_MAC_ID_S 0
#define HTT_RX_PDEV_FW_STATS_MAC_ID_GET(_var) \
(((_var) & HTT_RX_PDEV_FW_STATS_MAC_ID_M) >> \
- HTT_RX_PDEV_FW_STATS_MAC_ID_S)
+ HTT_RX_PDEV_FW_STATS_MAC_ID_S)
#define HTT_RX_PDEV_FW_STATS_MAC_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_RX_PDEV_FW_STATS_MAC_ID, _val); \
- ((_var) |= ((_val) << HTT_RX_PDEV_FW_STATS_MAC_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_RX_PDEV_FW_STATS_MAC_ID, _val); \
+ ((_var) |= ((_val) << HTT_RX_PDEV_FW_STATS_MAC_ID_S)); \
+ } while (0)
-#define HTT_STATS_SUBTYPE_MAX 16
+#define HTT_STATS_SUBTYPE_MAX 16
typedef struct {
htt_tlv_hdr_t tlv_hdr;
@@ -3044,34 +3540,34 @@
* Instead, use the constituent TLV structures to fill/parse.
*/
typedef struct {
- htt_rx_soc_stats_t soc_stats;
- htt_rx_pdev_fw_stats_tlv fw_stats_tlv;
+ htt_rx_soc_stats_t soc_stats;
+ htt_rx_pdev_fw_stats_tlv fw_stats_tlv;
htt_rx_pdev_fw_ring_mpdu_err_tlv_v fw_ring_mpdu_err_tlv;
- htt_rx_pdev_fw_mpdu_drop_tlv_v fw_ring_mpdu_drop;
- htt_rx_pdev_fw_stats_phy_err_tlv fw_stats_phy_err_tlv;
+ htt_rx_pdev_fw_mpdu_drop_tlv_v fw_ring_mpdu_drop;
+ htt_rx_pdev_fw_stats_phy_err_tlv fw_stats_phy_err_tlv;
} htt_rx_pdev_stats_t;
-#define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1)
-#define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2)
-#define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4)
-#define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8)
-#define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10)
-#define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20)
-#define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40)
-#define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80)
+#define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1)
+#define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2)
+#define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4)
+#define HTT_PDEV_CCA_STATS_MY_RX_FRAME_INFO_PRESENT (0x8)
+#define HTT_PDEV_CCA_STATS_USEC_CNT_INFO_PRESENT (0x10)
+#define HTT_PDEV_CCA_STATS_MED_RX_IDLE_INFO_PRESENT (0x20)
+#define HTT_PDEV_CCA_STATS_MED_TX_IDLE_GLOBAL_INFO_PRESENT (0x40)
+#define HTT_PDEV_CCA_STATS_CCA_OBBS_USEC_INFO_PRESENT (0x80)
typedef struct {
htt_tlv_hdr_t tlv_hdr;
/* Below values are obtained from the HW Cycles counter registers */
- A_UINT32 tx_frame_usec;
- A_UINT32 rx_frame_usec;
- A_UINT32 rx_clear_usec;
- A_UINT32 my_rx_frame_usec;
- A_UINT32 usec_cnt;
- A_UINT32 med_rx_idle_usec;
- A_UINT32 med_tx_idle_global_usec;
- A_UINT32 cca_obss_usec;
+ A_UINT32 tx_frame_usec;
+ A_UINT32 rx_frame_usec;
+ A_UINT32 rx_clear_usec;
+ A_UINT32 my_rx_frame_usec;
+ A_UINT32 usec_cnt;
+ A_UINT32 med_rx_idle_usec;
+ A_UINT32 med_tx_idle_global_usec;
+ A_UINT32 cca_obss_usec;
} htt_pdev_stats_cca_counters_tlv;
/* NOTE: THIS htt_pdev_cca_stats_hist_tlv STRUCTURE IS DEPRECATED,
@@ -3082,10 +3578,10 @@
htt_tlv_hdr_t tlv_hdr;
/* The channel number on which these stats were collected */
- A_UINT32 chan_num;
+ A_UINT32 chan_num;
/* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/
- A_UINT32 num_records;
+ A_UINT32 num_records;
/*
* Bit map of valid CCA counters
@@ -3100,7 +3596,7 @@
*
* See HTT_PDEV_CCA_STATS_xxx_INFO_PRESENT defs
*/
- A_UINT32 valid_cca_counters_bitmap;
+ A_UINT32 valid_cca_counters_bitmap;
/* Indicates the stats collection interval
* Valid Values:
@@ -3108,7 +3604,7 @@
* 1000 - For 1sec interval CCA histogram
* 0xFFFFFFFF - For Cumulative CCA Stats
*/
- A_UINT32 collection_interval;
+ A_UINT32 collection_interval;
/**
* This will be followed by an array which contains the CCA stats
@@ -3124,10 +3620,10 @@
htt_tlv_hdr_t tlv_hdr;
/* The channel number on which these stats were collected */
- A_UINT32 chan_num;
+ A_UINT32 chan_num;
/* num of CCA records (Num of htt_pdev_stats_cca_counters_tlv)*/
- A_UINT32 num_records;
+ A_UINT32 num_records;
/*
* Bit map of valid CCA counters
@@ -3142,7 +3638,7 @@
*
* See HTT_PDEV_CCA_STATS_xxx_INFO_PRESENT defs
*/
- A_UINT32 valid_cca_counters_bitmap;
+ A_UINT32 valid_cca_counters_bitmap;
/* Indicates the stats collection interval
* Valid Values:
@@ -3150,7 +3646,7 @@
* 1000 - For 1sec interval CCA histogram
* 0xFFFFFFFF - For Cumulative CCA Stats
*/
- A_UINT32 collection_interval;
+ A_UINT32 collection_interval;
/**
* This will be followed by an array which contains the CCA stats
@@ -3162,77 +3658,77 @@
*/
} htt_pdev_cca_stats_hist_v1_tlv;
-#define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000ffff
-#define HTT_TWT_SESSION_FLAG_FLOW_ID_S 0
+#define HTT_TWT_SESSION_FLAG_FLOW_ID_M 0x0000ffff
+#define HTT_TWT_SESSION_FLAG_FLOW_ID_S 0
-#define HTT_TWT_SESSION_FLAG_BCAST_TWT_M 0x00010000
-#define HTT_TWT_SESSION_FLAG_BCAST_TWT_S 16
+#define HTT_TWT_SESSION_FLAG_BCAST_TWT_M 0x00010000
+#define HTT_TWT_SESSION_FLAG_BCAST_TWT_S 16
-#define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_M 0x00020000
-#define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S 17
+#define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_M 0x00020000
+#define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S 17
-#define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_M 0x00040000
-#define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S 18
+#define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_M 0x00040000
+#define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S 18
#define HTT_TWT_SESSION_FLAG_FLOW_ID_GET(_var) \
- (((_var) & HTT_TWT_SESSION_FLAG_FLOW_ID_M) >> \
- HTT_TWT_SESSION_FLAG_FLOW_ID_S)
+ (((_var) & HTT_TWT_SESSION_FLAG_FLOW_ID_M) >> \
+ HTT_TWT_SESSION_FLAG_FLOW_ID_S)
#define HTT_TWT_SESSION_FLAG_FLOW_ID_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_FLOW_ID, _val); \
- ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_FLOW_ID_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_FLOW_ID, _val); \
+ ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_FLOW_ID_S)); \
+ } while (0)
#define HTT_TWT_SESSION_FLAG_BCAST_TWT_GET(_var) \
- (((_var) & HTT_TWT_SESSION_FLAG_BCAST_TWT_M) >> \
- HTT_TWT_SESSION_FLAG_BCAST_TWT_S)
+ (((_var) & HTT_TWT_SESSION_FLAG_BCAST_TWT_M) >> \
+ HTT_TWT_SESSION_FLAG_BCAST_TWT_S)
#define HTT_TWT_SESSION_FLAG_BCAST_TWT_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BCAST_TWT, _val); \
- ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BCAST_TWT_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_BCAST_TWT, _val); \
+ ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_BCAST_TWT_S)); \
+ } while (0)
#define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_GET(_var) \
- (((_var) & HTT_TWT_SESSION_FLAG_TRIGGER_TWT_M) >> \
- HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S)
+ (((_var) & HTT_TWT_SESSION_FLAG_TRIGGER_TWT_M) >> \
+ HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S)
#define HTT_TWT_SESSION_FLAG_TRIGGER_TWT_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_TRIGGER_TWT, _val); \
- ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_TRIGGER_TWT, _val); \
+ ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_TRIGGER_TWT_S)); \
+ } while (0)
#define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_GET(_var) \
- (((_var) & HTT_TWT_SESSION_FLAG_ANNOUN_TWT_M) >> \
- HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S)
+ (((_var) & HTT_TWT_SESSION_FLAG_ANNOUN_TWT_M) >> \
+ HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S)
#define HTT_TWT_SESSION_FLAG_ANNOUN_TWT_SET(_var, _val) \
- do { \
- HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_ANNOUN_TWT, _val); \
- ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S)); \
- } while (0)
+ do { \
+ HTT_CHECK_SET_VAL(HTT_TWT_SESSION_FLAG_ANNOUN_TWT, _val); \
+ ((_var) |= ((_val) << HTT_TWT_SESSION_FLAG_ANNOUN_TWT_S)); \
+ } while (0)
-#define TWT_DIALOG_ID_UNAVAILABLE 0xFFFFFFFF
+#define TWT_DIALOG_ID_UNAVAILABLE 0xFFFFFFFF
typedef struct {
- htt_tlv_hdr_t tlv_hdr;
+ htt_tlv_hdr_t tlv_hdr;
- A_UINT32 vdev_id;
- htt_mac_addr peer_mac;
- A_UINT32 flow_id_flags;
- A_UINT32 dialog_id; /* TWT_DIALOG_ID_UNAVAILABLE is used when TWT session is not initiated by host */
- A_UINT32 wake_dura_us;
- A_UINT32 wake_intvl_us;
- A_UINT32 sp_offset_us;
+ A_UINT32 vdev_id;
+ htt_mac_addr peer_mac;
+ A_UINT32 flow_id_flags;
+ A_UINT32 dialog_id; /* TWT_DIALOG_ID_UNAVAILABLE is used when TWT session is not initiated by host */
+ A_UINT32 wake_dura_us;
+ A_UINT32 wake_intvl_us;
+ A_UINT32 sp_offset_us;
} htt_pdev_stats_twt_session_tlv;
typedef struct {
- htt_tlv_hdr_t tlv_hdr;
+ htt_tlv_hdr_t tlv_hdr;
- A_UINT32 pdev_id;
- A_UINT32 num_sessions;
+ A_UINT32 pdev_id;
+ A_UINT32 num_sessions;
htt_pdev_stats_twt_session_tlv twt_session[1];
} htt_pdev_stats_twt_sessions_tlv;
@@ -3252,21 +3748,21 @@
typedef enum {
/* Global link descriptor queued in REO */
- HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0,
- HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1,
- HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2,
+ HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_0 = 0,
+ HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_1 = 1,
+ HTT_RX_REO_RESOURCE_GLOBAL_LINK_DESC_COUNT_2 = 2,
/*Number of queue descriptors of this aging group */
- HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3,
- HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4,
- HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5,
- HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6,
+ HTT_RX_REO_RESOURCE_BUFFERS_USED_AC0 = 3,
+ HTT_RX_REO_RESOURCE_BUFFERS_USED_AC1 = 4,
+ HTT_RX_REO_RESOURCE_BUFFERS_USED_AC2 = 5,
+ HTT_RX_REO_RESOURCE_BUFFERS_USED_AC3 = 6,
/* Total number of MSDUs buffered in AC */
- HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7,
- HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8,
- HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9,
- HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10,
+ HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC0 = 7,
+ HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC1 = 8,
+ HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC2 = 9,
+ HTT_RX_REO_RESOURCE_AGING_NUM_QUEUES_AC3 = 10,
- HTT_RX_REO_RESOURCE_STATS_MAX = 16
+ HTT_RX_REO_RESOURCE_STATS_MAX = 16
} htt_rx_reo_resource_sample_id_enum;
typedef struct {
@@ -3306,4 +3802,200 @@
htt_rx_reo_resource_stats_tlv_v reo_resource_stats;
} htt_soc_reo_resource_stats_t;
+/* == TX SOUNDING STATS == */
+
+/* config_param0 */
+
+#define HTT_DBG_EXT_STATS_SET_VDEV_MASK(_var) ((_var << 1) | 0x1)
+#define HTT_DBG_EXT_STATS_GET_VDEV_ID_FROM_VDEV_MASK(_var) ((_var >> 1) & 0xFF)
+#define HTT_DBG_EXT_STATS_IS_VDEV_ID_SET(_var) ((_var) & 0x1)
+
+typedef enum {
+ /* Implicit beamforming stats */
+ HTT_IMPLICIT_TXBF_STEER_STATS = 0,
+ /* Single user short inter frame sequence steer stats */
+ HTT_EXPLICIT_TXBF_SU_SIFS_STEER_STATS = 1,
+ /* Single user random back off steer stats */
+ HTT_EXPLICIT_TXBF_SU_RBO_STEER_STATS = 2,
+ /* Multi user short inter frame sequence steer stats */
+ HTT_EXPLICIT_TXBF_MU_SIFS_STEER_STATS = 3,
+ /* Multi user random back off steer stats */
+ HTT_EXPLICIT_TXBF_MU_RBO_STEER_STATS = 4,
+ /* For backward compatability new modes cannot be added */
+ HTT_TXBF_MAX_NUM_OF_MODES = 5
+} htt_txbf_sound_steer_modes;
+
+typedef enum {
+ HTT_TX_AC_SOUNDING_MODE = 0,
+ HTT_TX_AX_SOUNDING_MODE = 1,
+} htt_stats_sounding_tx_mode;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 tx_sounding_mode; /* HTT_TX_XX_SOUNDING_MODE */
+ /* Counts number of soundings for all steering modes in each bw */
+ A_UINT32 cbf_20[HTT_TXBF_MAX_NUM_OF_MODES];
+ A_UINT32 cbf_40[HTT_TXBF_MAX_NUM_OF_MODES];
+ A_UINT32 cbf_80[HTT_TXBF_MAX_NUM_OF_MODES];
+ A_UINT32 cbf_160[HTT_TXBF_MAX_NUM_OF_MODES];
+ /*
+ * The sounding array is a 2-D array stored as an 1-D array of
+ * A_UINT32. The stats for a particular user/bw combination is
+ * referenced with the following:
+ *
+ * sounding[(user* max_bw) + bw]
+ *
+ * ... where max_bw == 4 for 160mhz
+ */
+ A_UINT32 sounding[HTT_TX_NUM_OF_SOUNDING_STATS_WORDS];
+} htt_tx_sounding_stats_tlv;
+
+/* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SOUNDING_INFO
+ * TLV_TAGS:
+ * - HTT_STATS_TX_SOUNDING_STATS_TAG
+ */
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct {
+ htt_tx_sounding_stats_tlv sounding_tlv;
+} htt_tx_sounding_stats_t;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+
+ A_UINT32 num_obss_tx_ppdu_success;
+ A_UINT32 num_obss_tx_ppdu_failure;
+ /* num_sr_tx_transmissions:
+ * Counter of TX done by aborting other BSS RX with spatial reuse
+ * (for cases where rx RSSI from other BSS is below the packet-detection
+ * threshold for doing spatial reuse)
+ */
+ union {
+ A_UINT32 num_sr_tx_transmissions; /* CORRECTED - use this one */
+ A_UINT32 num_sr_tx_tranmissions; /* DEPRECATED - has typo in name */
+ };
+ /* num_sr_rx_ge_pd_rssi_thr
+ * counter of rx from other BSS for which RSSI was above the
+ * packet-detection threshold specified for enabling spatial reuse
+ */
+ A_UINT32 num_sr_rx_ge_pd_rssi_thr;
+} htt_pdev_obss_pd_stats_tlv;
+
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct {
+ htt_pdev_obss_pd_stats_tlv obss_pd_stat;
+} htt_pdev_obss_pd_stats_t;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 pdev_id;
+ A_UINT32 current_head_idx;
+ A_UINT32 current_tail_idx;
+ A_UINT32 num_htt_msgs_sent;
+ /*
+ * Time in milliseconds for which the ring has been in
+ * its current backpressure condition
+ */
+ A_UINT32 backpressure_time_ms;
+ /* backpressure_hist - histogram showing how many times different degrees
+ * of backpressure duration occurred:
+ * Index 0 indicates the number of times ring was
+ * continously in backpressure state for 100 - 200ms.
+ * Index 1 indicates the number of times ring was
+ * continously in backpressure state for 200 - 300ms.
+ * Index 2 indicates the number of times ring was
+ * continously in backpressure state for 300 - 400ms.
+ * Index 3 indicates the number of times ring was
+ * continously in backpressure state for 400 - 500ms.
+ * Index 4 indicates the number of times ring was
+ * continously in backpressure state beyond 500ms.
+ */
+ A_UINT32 backpressure_hist[5];
+} htt_ring_backpressure_stats_tlv;
+
+/* STATS_TYPE : HTT_STATS_RING_BACKPRESSURE_STATS_INFO
+ * TLV_TAGS:
+ * - HTT_STATS_RING_BACKPRESSURE_STATS_TAG
+ */
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct {
+ htt_sring_cmn_tlv cmn_tlv;
+ struct {
+ htt_stats_string_tlv sring_str_tlv;
+ htt_ring_backpressure_stats_tlv backpressure_stats_tlv;
+ } r[1]; /* variable-length array */
+} htt_ring_backpressure_stats_t;
+
+#define HTT_LATENCY_PROFILE_MAX_HIST 3
+#define HTT_STATS_MAX_PROF_STATS_NAME_LEN 32
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ /* print_header:
+ * This field suggests whether the host should print a header when
+ * displaying the TLV (because this is the first latency_prof_stats
+ * TLV within a series), or if only the TLV contents should be displayed
+ * without a header (because this is not the first TLV within the series).
+ */
+ A_UINT32 print_header;
+ A_UINT8 latency_prof_name[HTT_STATS_MAX_PROF_STATS_NAME_LEN];
+ A_UINT32 cnt; /* number of data values included in the tot sum */
+ A_UINT32 min; /* time in us */
+ A_UINT32 max; /* time in us */
+ A_UINT32 last;
+ A_UINT32 tot; /* time in us */
+ A_UINT32 avg; /* time in us */
+ /* hist_intvl:
+ * Histogram interval, i.e. the latency range covered by each
+ * bin of the histogram, in microsecond units.
+ * hist[0] counts how many latencies were between 0 to hist_intvl
+ * hist[1] counts how many latencies were between hist_intvl to 2*hist_intvl
+ * hist[2] counts how many latencies were more than 2*hist_intvl
+ */
+ A_UINT32 hist_intvl;
+ A_UINT32 hist[HTT_LATENCY_PROFILE_MAX_HIST];
+} htt_latency_prof_stats_tlv;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ /* duration:
+ * Time period over which counts were gathered, units = microseconds.
+ */
+ A_UINT32 duration;
+ A_UINT32 tx_msdu_cnt;
+ A_UINT32 tx_mpdu_cnt;
+ A_UINT32 tx_ppdu_cnt;
+ A_UINT32 rx_msdu_cnt;
+ A_UINT32 rx_mpdu_cnt;
+} htt_latency_prof_ctx_tlv;
+
+typedef struct {
+ htt_tlv_hdr_t tlv_hdr;
+ A_UINT32 prof_enable_cnt; /* count of enabled profiles */
+} htt_latency_prof_cnt_tlv;
+
+/* STATS_TYPE : HTT_DBG_EXT_STATS_LATENCY_PROF_STATS
+ * TLV_TAGS:
+ * HTT_STATS_LATENCY_PROF_STATS_TAG / htt_latency_prof_stats_tlv
+ * HTT_STATS_LATENCY_CTX_TAG / htt_latency_prof_ctx_tlv
+ * HTT_STATS_LATENCY_CNT_TAG / htt_latency_prof_cnt_tlv
+ */
+/* NOTE:
+ * This structure is for documentation, and cannot be safely used directly.
+ * Instead, use the constituent TLV structures to fill/parse.
+ */
+typedef struct {
+ htt_latency_prof_stats_tlv latency_prof_stat;
+ htt_latency_prof_ctx_tlv latency_ctx_stat;
+ htt_latency_prof_cnt_tlv latency_cnt_stat;
+} htt_soc_latency_stats_t;
+
+
#endif /* __HTT_STATS_H__ */
diff --git a/drivers/staging/fw-api/fw/targaddrs.h b/drivers/staging/fw-api/fw/targaddrs.h
index 98d4b20..774a3c9 100644
--- a/drivers/staging/fw-api/fw/targaddrs.h
+++ b/drivers/staging/fw-api/fw/targaddrs.h
@@ -370,6 +370,24 @@
#define HI_OPTION_BE_LATENCY_OPTIMIZE 0x100 /* This bit is to enable BE low latency for some customers. The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).*/
#define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */
+/*
+ * If both SDIO_CRASH_DUMP_ENHANCEMENT_HOST and SDIO_CRASH_DUMP_ENHANCEMENT_FW
+ * flags are set, then crashdump upload will be done using the BMI host/target
+ * communication channel.
+ */
+#define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST 0x400 /* HOST to support using BMI dump FW memory when hit assert */
+#define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_FW 0x800 /* FW to support using BMI dump FW memory when hit assert */
+
+/* USB_RESET_RESUME
+ * The host will set this flag, based on platform configuration specs.
+ * The target will check this flag at the time USB becomes suspended.
+ * If the flag is set, the target will invoke its reset / resume code.
+ * If the flag is not set, the target will do nothing, other than wait.
+ */
+#define HI_OPTION_USB_RESET_RESUME 0x1000
+#define USB_RESET_RESUME() \
+ (HOST_INTEREST->hi_option_flag2 & HI_OPTION_USB_RESET_RESUME)
+
#define GPIO_WAKEUP_ENABLED() \
(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
diff --git a/drivers/staging/fw-api/fw/wlan_defs.h b/drivers/staging/fw-api/fw/wlan_defs.h
index 4dd6292..9c878dc 100644
--- a/drivers/staging/fw-api/fw/wlan_defs.h
+++ b/drivers/staging/fw-api/fw/wlan_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2016, 2018-2019 The Linux Foundation. All rights reserved.*
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -115,6 +115,8 @@
#define HE_PET_8_USEC 1
#define HE_PET_16_USEC 2
+#define DEFAULT_OFDMA_RU26_COUNT 0
+
typedef enum {
MODE_11A = 0, /* 11a Mode */
MODE_11G = 1, /* 11b/g Mode */
@@ -170,11 +172,23 @@
#endif
} WLAN_PHY_MODE;
-#ifndef CONFIG_160MHZ_SUPPORT
+#if (!defined(CONFIG_160MHZ_SUPPORT)) && (!defined(SUPPORT_11AX))
A_COMPILE_TIME_ASSERT(
mode_unknown_value_consistency_Check,
MODE_UNKNOWN == MODE_UNKNOWN_NO_160MHZ_SUPPORT);
#else
+/*
+ * If SUPPORT_11AX is defined but CONFIG_160MHZ_SUPPORT is not defined,
+ * there will be a gap in the mode values, with 14 and 15 being unused.
+ * But MODE_UNKNOWN_NO_160MHZ_SUPPORT will have an invalid value, since
+ * mode values 16 through 23 will be used for 11AX modes.
+ * Thus, MODE_UNKNOWN would still be MODE_UNKNOWN_160MHZ_SUPPORT, for
+ * cases where 160 MHz is not supported by 11AX is supported.
+ * (Ideally, MODE_UNKNOWN_160MHZ_SUPPORT and NO_160MHZ_SUPPORT should be
+ * renamed to cover the 4 permutations of support or no support for
+ * 11AX and 160 MHZ, but that is impractical, due to backwards
+ * compatibility concerns.)
+ */
A_COMPILE_TIME_ASSERT(
mode_unknown_value_consistency_Check,
MODE_UNKNOWN == MODE_UNKNOWN_160MHZ_SUPPORT);
@@ -206,6 +220,7 @@
((mode) == MODE_11AC_VHT80))
#endif
+#if SUPPORT_11AX
#define IS_MODE_HE(mode) (((mode) == MODE_11AX_HE20) || \
((mode) == MODE_11AX_HE40) || \
((mode) == MODE_11AX_HE80) || \
@@ -214,6 +229,10 @@
((mode) == MODE_11AX_HE20_2G) || \
((mode) == MODE_11AX_HE40_2G) || \
((mode) == MODE_11AX_HE80_2G))
+#define IS_MODE_HE_2G(mode) (((mode) == MODE_11AX_HE20_2G) || \
+ ((mode) == MODE_11AX_HE40_2G) || \
+ ((mode) == MODE_11AX_HE80_2G))
+#endif /* SUPPORT_11AX */
#define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \
((mode) == MODE_11AC_VHT40_2G) || \
@@ -235,6 +254,40 @@
((mode) == MODE_11NG_HT40))
#define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY)
+#define IS_MODE_LEGACY(phymode) ((phymode == MODE_11A) || \
+ (phymode == MODE_11G) || \
+ (phymode == MODE_11B) || \
+ (phymode == MODE_11GONLY))
+
+#define IS_MODE_11N(phymode) ((phymode >= MODE_11NA_HT20) && \
+ (phymode <= MODE_11NG_HT40))
+#ifdef CONFIG_160MHZ_SUPPORT
+ #define IS_MODE_11AC(phymode) ((phymode >= MODE_11AC_VHT20) && \
+ (phymode <= MODE_11AC_VHT160))
+#else
+ #define IS_MODE_11AC(phymode) ((phymode >= MODE_11AC_VHT20) && \
+ (phymode <= MODE_11AC_VHT80_2G))
+#endif /* CONFIG_160MHZ_SUPPORT */
+
+#if SUPPORT_11AX
+ #define IS_MODE_80MHZ(phymode) ((phymode == MODE_11AC_VHT80_2G) || \
+ (phymode == MODE_11AC_VHT80) || \
+ (phymode == MODE_11AX_HE80) || \
+ (phymode == MODE_11AX_HE80_2G))
+ #define IS_MODE_40MHZ(phymode) ((phymode == MODE_11AC_VHT40_2G) || \
+ (phymode == MODE_11AC_VHT40) || \
+ (phymode == MODE_11NG_HT40) || \
+ (phymode == MODE_11NA_HT40) || \
+ (phymode == MODE_11AX_HE40) || \
+ (phymode == MODE_11AX_HE40_2G))
+#else
+ #define IS_MODE_80MHZ(phymode) ((phymode == MODE_11AC_VHT80_2G) || \
+ (phymode == MODE_11AC_VHT80))
+ #define IS_MODE_40MHZ(phymode) ((phymode == MODE_11AC_VHT40_2G) || \
+ (phymode == MODE_11AC_VHT40) || \
+ (phymode == MODE_11NG_HT40) || \
+ (phymode == MODE_11NA_HT40))
+#endif /* SUPPORT_11AX */
enum {
REGDMN_MODE_11A = 0x00000001, /* 11a channels */
@@ -318,12 +371,13 @@
* In host-based implementation of the rate-control feature, this struture is used to
* create the payload for HTT message/s from target to host.
*/
-
-#if (NUM_SPATIAL_STREAM > 3)
- #define A_RATEMASK A_UINT64
-#else
- #define A_RATEMASK A_UINT32
-#endif
+#ifndef CONFIG_MOVE_RC_STRUCT_TO_MACCORE
+ #if (NUM_SPATIAL_STREAM > 3)
+ #define A_RATEMASK A_UINT64
+ #else
+ #define A_RATEMASK A_UINT32
+ #endif
+#endif /* CONFIG_MOVE_RC_STRUCT_TO_MACCORE */
typedef A_UINT8 A_RATE;
typedef A_UINT8 A_RATECODE;
@@ -425,6 +479,7 @@
* because the host should have no references to these target-only data
* structures.
*/
+#ifndef CONFIG_MOVE_RC_STRUCT_TO_MACCORE
#if !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX)
#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B)
typedef struct{
@@ -494,6 +549,7 @@
A_UINT8 dd_profile;
} RC_TX_RATE_INFO;
#endif /* !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) */
+#endif /* CONFIG_MOVE_RC_STRUCT_TO_MACCORE */
#endif
/*
@@ -525,6 +581,13 @@
A_UINT32 ptr;
/** size of the chunk */
A_UINT32 size;
+ /** ptr_high
+ * most significant bits of physical address of the memory chunk
+ * Only applicable for addressing more than 32 bit.
+ * This will only be non-zero if the target has set
+ * WMI_SERVICE_SUPPORT_EXTEND_ADDRESS flag.
+ */
+ A_UINT32 ptr_high;
} wlan_host_memory_chunk;
#define NUM_UNITS_IS_NUM_VDEVS 0x1
@@ -597,7 +660,12 @@
* so that it is easy to handle the statistics in BE host.
*/
-struct wlan_dbg_tx_stats {
+/*
+ * wlan_dbg_tx_stats_v1, _v2:
+ * differing versions of the wlan_dbg_tx_stats struct used by different
+ * targets
+ */
+struct wlan_dbg_tx_stats_v1 {
/* Num HTT cookies queued to dispatch list */
A_INT32 comp_queued;
/* Num HTT cookies dispatched */
@@ -618,19 +686,12 @@
A_INT32 hw_reaped;
/* Num underruns */
A_INT32 underrun;
-#if defined(AR900B)
- /* HW Paused. */
- A_UINT32 hw_paused;
-#endif
/* Num PPDUs cleaned up in TX abort */
A_INT32 tx_abort;
/* Num MPDUs requed by SW */
A_INT32 mpdus_requed;
/* excessive retries */
A_UINT32 tx_ko;
-#if defined(AR900B)
- A_UINT32 tx_xretry;
-#endif
/* data hw rate code */
A_UINT32 data_rc;
/* Scheduler self triggers */
@@ -651,7 +712,58 @@
A_UINT32 phy_underrun;
/* MPDU is more than txop limit */
A_UINT32 txop_ovf;
-#if defined(AR900B)
+};
+
+struct wlan_dbg_tx_stats_v2 {
+ /* Num HTT cookies queued to dispatch list */
+ A_INT32 comp_queued;
+ /* Num HTT cookies dispatched */
+ A_INT32 comp_delivered;
+ /* Num MSDU queued to WAL */
+ A_INT32 msdu_enqued;
+ /* Num MPDU queue to WAL */
+ A_INT32 mpdu_enqued;
+ /* Num MSDUs dropped by WMM limit */
+ A_INT32 wmm_drop;
+ /* Num Local frames queued */
+ A_INT32 local_enqued;
+ /* Num Local frames done */
+ A_INT32 local_freed;
+ /* Num queued to HW */
+ A_INT32 hw_queued;
+ /* Num PPDU reaped from HW */
+ A_INT32 hw_reaped;
+ /* Num underruns */
+ A_INT32 underrun;
+ /* HW Paused. */
+ A_UINT32 hw_paused;
+ /* Num PPDUs cleaned up in TX abort */
+ A_INT32 tx_abort;
+ /* Num MPDUs requed by SW */
+ A_INT32 mpdus_requed;
+ /* excessive retries */
+ A_UINT32 tx_ko;
+ A_UINT32 tx_xretry;
+ /* data hw rate code */
+ A_UINT32 data_rc;
+ /* Scheduler self triggers */
+ A_UINT32 self_triggers;
+ /* frames dropped due to excessive sw retries */
+ A_UINT32 sw_retry_failure;
+ /* illegal rate phy errors */
+ A_UINT32 illgl_rate_phy_err;
+ /* wal pdev continous xretry */
+ A_UINT32 pdev_cont_xretry;
+ /* wal pdev continous xretry */
+ A_UINT32 pdev_tx_timeout;
+ /* wal pdev resets */
+ A_UINT32 pdev_resets;
+ /* frames dropped due to non-availability of stateless TIDs */
+ A_UINT32 stateless_tid_alloc_failure;
+ /* PhY/BB underrun */
+ A_UINT32 phy_underrun;
+ /* MPDU is more than txop limit */
+ A_UINT32 txop_ovf;
/* Number of Sequences posted */
A_UINT32 seq_posted;
/* Number of Sequences failed queueing */
@@ -672,10 +784,20 @@
A_INT32 mpdus_ack_failed;
/* Num MPDUs that was dropped du to expiry. */
A_INT32 mpdus_expired;
-#endif
};
-struct wlan_dbg_rx_stats {
+#if defined(AR900B)
+#define wlan_dbg_tx_stats wlan_dbg_tx_stats_v2
+#else
+#define wlan_dbg_tx_stats wlan_dbg_tx_stats_v1
+#endif
+
+/*
+ * wlan_dbg_rx_stats_v1, _v2:
+ * differing versions of the wlan_dbg_rx_stats struct used by different
+ * targets
+ */
+struct wlan_dbg_rx_stats_v1 {
/* Cnts any change in ring routing mid-ppdu */
A_INT32 mid_ppdu_route_change;
/* Total number of statuses processed */
@@ -699,12 +821,41 @@
A_INT32 phy_err_drop;
/* Number of mpdu errors - FCS, MIC, ENC etc. */
A_INT32 mpdu_errs;
-#if defined(AR900B)
- /* Number of rx overflow errors. */
- A_INT32 rx_ovfl_errs;
-#endif
};
+struct wlan_dbg_rx_stats_v2 {
+ /* Cnts any change in ring routing mid-ppdu */
+ A_INT32 mid_ppdu_route_change;
+ /* Total number of statuses processed */
+ A_INT32 status_rcvd;
+ /* Extra frags on rings 0-3 */
+ A_INT32 r0_frags;
+ A_INT32 r1_frags;
+ A_INT32 r2_frags;
+ A_INT32 r3_frags;
+ /* MSDUs / MPDUs delivered to HTT */
+ A_INT32 htt_msdus;
+ A_INT32 htt_mpdus;
+ /* MSDUs / MPDUs delivered to local stack */
+ A_INT32 loc_msdus;
+ A_INT32 loc_mpdus;
+ /* AMSDUs that have more MSDUs than the status ring size */
+ A_INT32 oversize_amsdu;
+ /* Number of PHY errors */
+ A_INT32 phy_errs;
+ /* Number of PHY errors drops */
+ A_INT32 phy_err_drop;
+ /* Number of mpdu errors - FCS, MIC, ENC etc. */
+ A_INT32 mpdu_errs;
+ /* Number of rx overflow errors. */
+ A_INT32 rx_ovfl_errs;
+};
+
+#if defined(AR900B)
+#define wlan_dbg_rx_stats wlan_dbg_rx_stats_v2
+#else
+#define wlan_dbg_rx_stats wlan_dbg_rx_stats_v1
+#endif
struct wlan_dbg_mem_stats {
A_UINT32 iram_free_size;
@@ -716,6 +867,28 @@
A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */
};
+/*
+ * wlan_dbg_rx_rate_info_v1a_t, _v1b_t:
+ * differing versions of the wlan_dbg_rx_rate_info struct used by different
+ * targets
+ */
+typedef struct {
+ A_UINT32 mcs[10];
+ A_UINT32 sgi[10];
+ A_UINT32 nss[4];
+ A_UINT32 nsts;
+ A_UINT32 stbc[10];
+ A_UINT32 bw[3];
+ A_UINT32 pream[6];
+ A_UINT32 ldpc;
+ A_UINT32 txbf;
+ A_UINT32 mgmt_rssi;
+ A_UINT32 data_rssi;
+ A_UINT32 rssi_chain0;
+ A_UINT32 rssi_chain1;
+ A_UINT32 rssi_chain2;
+} wlan_dbg_rx_rate_info_v1a_t;
+
typedef struct {
A_UINT32 mcs[10];
A_UINT32 sgi[10];
@@ -734,12 +907,15 @@
/*
* TEMPORARY: leave rssi_chain3 in place for AR900B builds until code using
* rssi_chain3 has been converted to use wlan_dbg_rx_rate_info_v2_t.
- * At that time, this rssi_chain3 field will be deleted.
*/
-#if defined(AR900B)
A_UINT32 rssi_chain3;
+} wlan_dbg_rx_rate_info_v1b_t;
+
+#if defined(AR900B)
+#define wlan_dbg_rx_rate_info_t wlan_dbg_rx_rate_info_v1b_t
+#else
+#define wlan_dbg_rx_rate_info_t wlan_dbg_rx_rate_info_v1a_t
#endif
-} wlan_dbg_rx_rate_info_t ;
typedef struct {
A_UINT32 mcs[10];
@@ -930,25 +1106,56 @@
wlan_dgb_sifs_resp_stats_t sifs_resp_info;
} wlan_dbg_wifi2_stats_t;
+/*
+ * wlan_dbg_rx_rate_info_v1a, _v1b:
+ * differing versions of the wlan_dbg_rx_rate_info struct used by different
+ * targets
+ */
typedef struct {
- wlan_dbg_rx_rate_info_t rx_phy_info;
+ wlan_dbg_rx_rate_info_v1a_t rx_phy_info;
wlan_dbg_tx_rate_info_t tx_rate_info;
-} wlan_dbg_rate_info_t;
+} wlan_dbg_rate_info_v1a_t;
+
+typedef struct {
+ wlan_dbg_rx_rate_info_v1b_t rx_phy_info;
+ wlan_dbg_tx_rate_info_t tx_rate_info;
+} wlan_dbg_rate_info_v1b_t;
+
+#if defined(AR900B)
+#define wlan_dbg_rate_info_t wlan_dbg_rate_info_v1b_t
+#else
+#define wlan_dbg_rate_info_t wlan_dbg_rate_info_v1a_t
+#endif
typedef struct {
wlan_dbg_rx_rate_info_v2_t rx_phy_info;
wlan_dbg_tx_rate_info_v2_t tx_rate_info;
} wlan_dbg_rate_info_v2_t;
-struct wlan_dbg_stats {
- struct wlan_dbg_tx_stats tx;
- struct wlan_dbg_rx_stats rx;
-#if defined(AR900B)
- struct wlan_dbg_mem_stats mem;
-#endif
+/*
+ * wlan_dbg_stats_v1, _v2:
+ * differing versions of the wlan_dbg_stats struct used by different
+ * targets
+ */
+struct wlan_dbg_stats_v1 {
+ struct wlan_dbg_tx_stats_v1 tx;
+ struct wlan_dbg_rx_stats_v1 rx;
struct wlan_dbg_peer_stats peer;
};
+struct wlan_dbg_stats_v2 {
+ struct wlan_dbg_tx_stats_v2 tx;
+ struct wlan_dbg_rx_stats_v2 rx;
+ struct wlan_dbg_mem_stats mem;
+ struct wlan_dbg_peer_stats peer;
+};
+
+#if defined(AR900B)
+#define wlan_dbg_stats wlan_dbg_stats_v2
+#else
+#define wlan_dbg_stats wlan_dbg_stats_v1
+#endif
+
#define DBG_STATS_MAX_HWQ_NUM 10
#define DBG_STATS_MAX_TID_NUM 20
#define DBG_STATS_MAX_CONG_NUM 16
diff --git a/drivers/staging/fw-api/fw/wlan_module_ids.h b/drivers/staging/fw-api/fw/wlan_module_ids.h
index 39b9d4d..1bb9d01 100644
--- a/drivers/staging/fw-api/fw/wlan_module_ids.h
+++ b/drivers/staging/fw-api/fw/wlan_module_ids.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -30,79 +30,93 @@
/* Wlan module ids , global across all the modules */
typedef enum {
- WLAN_MODULE_ID_MIN = 0,
- WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */
- WLAN_MODULE_WMI, /* 0x1 */
- WLAN_MODULE_STA_PWRSAVE, /* 0x2 */
- WLAN_MODULE_WHAL, /* 0x3 */
- WLAN_MODULE_COEX, /* 0x4 */
- WLAN_MODULE_ROAM, /* 0x5 */
- WLAN_MODULE_RESMGR_CHAN_MANAGER, /* 0x6 */
- WLAN_MODULE_RESMGR, /* 0x7 */
- WLAN_MODULE_VDEV_MGR, /* 0x8 */
- WLAN_MODULE_SCAN, /* 0x9 */
- WLAN_MODULE_RATECTRL, /* 0xa */
- WLAN_MODULE_AP_PWRSAVE, /* 0xb */
- WLAN_MODULE_BLOCKACK, /* 0xc */
- WLAN_MODULE_MGMT_TXRX, /* 0xd */
- WLAN_MODULE_DATA_TXRX, /* 0xe */
- WLAN_MODULE_HTT, /* 0xf */
- WLAN_MODULE_HOST, /* 0x10 */
- WLAN_MODULE_BEACON, /* 0x11 */
- WLAN_MODULE_OFFLOAD, /* 0x12 */
- WLAN_MODULE_WAL, /* 0x13 */
- WAL_MODULE_DE, /* 0x14 */
- WLAN_MODULE_PCIELP, /* 0x15 */
- WLAN_MODULE_RTT, /* 0x16 */
- WLAN_MODULE_RESOURCE, /* 0x17 */
- WLAN_MODULE_DCS, /* 0x18 */
- WLAN_MODULE_CACHEMGR, /* 0x19 */
- WLAN_MODULE_ANI, /* 0x1a */
- WLAN_MODULE_P2P, /* 0x1b */
- WLAN_MODULE_CSA, /* 0x1c */
- WLAN_MODULE_NLO, /* 0x1d */
- WLAN_MODULE_CHATTER, /* 0x1e */
- WLAN_MODULE_WOW, /* 0x1f */
- WLAN_MODULE_WAL_VDEV, /* 0x20 */
- WLAN_MODULE_WAL_PDEV, /* 0x21 */
- WLAN_MODULE_TEST, /* 0x22 */
- WLAN_MODULE_STA_SMPS, /* 0x23 */
- WLAN_MODULE_SWBMISS, /* 0x24 */
- WLAN_MODULE_WMMAC, /* 0x25 */
- WLAN_MODULE_TDLS, /* 0x26 */
- WLAN_MODULE_HB, /* 0x27 */
- WLAN_MODULE_TXBF, /* 0x28 */
- WLAN_MODULE_BATCH_SCAN, /* 0x29 */
- WLAN_MODULE_THERMAL_MGR, /* 0x2a */
- WLAN_MODULE_PHYERR_DFS, /* 0x2b */
- WLAN_MODULE_RMC, /* 0x2c */
- WLAN_MODULE_STATS, /* 0x2d */
- WLAN_MODULE_NAN, /* 0x2e */
- WLAN_MODULE_IBSS_PWRSAVE, /* 0x2f */
- WLAN_MODULE_HIF_UART, /* 0x30 */
- WLAN_MODULE_LPI, /* 0x31 */
- WLAN_MODULE_EXTSCAN, /* 0x32 */
- WLAN_MODULE_UNIT_TEST, /* 0x33 */
- WLAN_MODULE_MLME, /* 0x34 */
- WLAN_MODULE_SUPPL, /* 0x35 */
- WLAN_MODULE_ERE, /* 0x36 */
- WLAN_MODULE_OCB, /* 0x37 */
- WLAN_MODULE_RSSI_MONITOR, /* 0x38 */
- WLAN_MODULE_WPM, /* 0x39 */
- WLAN_MODULE_CSS, /* 0x3a */
- WLAN_MODULE_PPS, /* 0x3b */
- WLAN_MODULE_SCAN_CH_PREDICT, /* 0x3c */
- WLAN_MODULE_MAWC, /* 0x3d */
- WLAN_MODULE_CMC_QMIC, /* 0x3e */
- WLAN_MODULE_EGAP, /* 0x3f */
- WLAN_MODULE_NAN20, /* 0x40 */
- WLAN_MODULE_QBOOST, /* 0x41 */
- WLAN_MODULE_P2P_LISTEN_OFFLOAD, /* 0x42 */
- WLAN_MODULE_HALPHY, /* 0x43 */
- WAL_MODULE_ENQ, /* 0x44 */
+ WLAN_MODULE_ID_MIN = 0,
+ WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */
+ WLAN_MODULE_WMI, /* 0x1 */
+ WLAN_MODULE_STA_PWRSAVE, /* 0x2 */
+ WLAN_MODULE_WHAL, /* 0x3 */
+ WLAN_MODULE_COEX, /* 0x4 */
+ WLAN_MODULE_ROAM, /* 0x5 */
+ WLAN_MODULE_RESMGR_CHAN_MANAGER, /* 0x6 */
+ WLAN_MODULE_RESMGR, /* 0x7 */
+ WLAN_MODULE_VDEV_MGR, /* 0x8 */
+ WLAN_MODULE_SCAN, /* 0x9 */
+ WLAN_MODULE_RATECTRL, /* 0xa */
+ WLAN_MODULE_AP_PWRSAVE, /* 0xb */
+ WLAN_MODULE_BLOCKACK, /* 0xc */
+ WLAN_MODULE_MGMT_TXRX, /* 0xd */
+ WLAN_MODULE_DATA_TXRX, /* 0xe */
+ WLAN_MODULE_HTT, /* 0xf */
+ WLAN_MODULE_HOST, /* 0x10 */
+ WLAN_MODULE_BEACON, /* 0x11 */
+ WLAN_MODULE_OFFLOAD, /* 0x12 */
+ WLAN_MODULE_WAL, /* 0x13 */
+ WAL_MODULE_DE, /* 0x14 */
+ WLAN_MODULE_PCIELP, /* 0x15 */
+ WLAN_MODULE_RTT, /* 0x16 */
+ WLAN_MODULE_RESOURCE, /* 0x17 */
+ WLAN_MODULE_DCS, /* 0x18 */
+ WLAN_MODULE_CACHEMGR, /* 0x19 */
+ WLAN_MODULE_ANI, /* 0x1a */
+ WLAN_MODULE_P2P, /* 0x1b */
+ WLAN_MODULE_CSA, /* 0x1c */
+ WLAN_MODULE_NLO, /* 0x1d */
+ WLAN_MODULE_CHATTER, /* 0x1e */
+ WLAN_MODULE_WOW, /* 0x1f */
+ WLAN_MODULE_WAL_VDEV, /* 0x20 */
+ WLAN_MODULE_WAL_PDEV, /* 0x21 */
+ WLAN_MODULE_TEST, /* 0x22 */
+ WLAN_MODULE_STA_SMPS, /* 0x23 */
+ WLAN_MODULE_SWBMISS, /* 0x24 */
+ WLAN_MODULE_WMMAC, /* 0x25 */
+ WLAN_MODULE_TDLS, /* 0x26 */
+ WLAN_MODULE_HB, /* 0x27 */
+ WLAN_MODULE_TXBF, /* 0x28 */
+ WLAN_MODULE_BATCH_SCAN, /* 0x29 */
+ WLAN_MODULE_THERMAL_MGR, /* 0x2a */
+ WLAN_MODULE_PHYERR_DFS, /* 0x2b */
+ WLAN_MODULE_RMC, /* 0x2c */
+ WLAN_MODULE_STATS, /* 0x2d */
+ WLAN_MODULE_NAN, /* 0x2e */
+ WLAN_MODULE_IBSS_PWRSAVE, /* 0x2f */
+ WLAN_MODULE_HIF_UART, /* 0x30 */
+ WLAN_MODULE_LPI, /* 0x31 */
+ WLAN_MODULE_EXTSCAN, /* 0x32 */
+ WLAN_MODULE_UNIT_TEST, /* 0x33 */
+ WLAN_MODULE_MLME, /* 0x34 */
+ WLAN_MODULE_SUPPL, /* 0x35 */
+ WLAN_MODULE_ERE, /* 0x36 */
+ WLAN_MODULE_OCB, /* 0x37 */
+ WLAN_MODULE_RSSI_MONITOR, /* 0x38 */
+ WLAN_MODULE_WPM, /* 0x39 */
+ WLAN_MODULE_CSS, /* 0x3a */
+ WLAN_MODULE_PPS, /* 0x3b */
+ WLAN_MODULE_SCAN_CH_PREDICT, /* 0x3c */
+ WLAN_MODULE_MAWC, /* 0x3d */
+ WLAN_MODULE_CMC_QMIC, /* 0x3e */
+ WLAN_MODULE_EGAP, /* 0x3f */
+ WLAN_MODULE_NAN20, /* 0x40 */
+ WLAN_MODULE_QBOOST, /* 0x41 */
+ WLAN_MODULE_P2P_LISTEN_OFFLOAD, /* 0x42 */
+ WLAN_MODULE_HALPHY, /* 0x43 */
+ WAL_MODULE_ENQ, /* 0x44 */
+ WLAN_MODULE_GNSS, /* 0x45 */
+ WLAN_MODULE_WAL_MEM, /* 0x46 */
+ WLAN_MODULE_SCHED_ALGO, /* 0x47 */
+ WLAN_MODULE_TX, /* 0x48 */
+ WLAN_MODULE_RX, /* 0x49 */
+ WLAN_MODULE_WLM, /* 0x4a */
+ WLAN_MODULE_RU_ALLOCATOR, /* 0x4b */
+ WLAN_MODULE_11K_OFFLOAD, /* 0x4c */
+ WLAN_MODULE_STA_TWT, /* 0x4d */
+ WLAN_MODULE_AP_TWT, /* 0x4e */
+ WLAN_MODULE_UL_OFDMA, /* 0x4f */
+ WLAN_MODULE_HPCS_PULSE, /* 0x50 */
+ WLAN_MODULE_DTF, /* 0x51 */ /* Deterministic Test Framework */
+ WLAN_MODULE_QUIET_IE, /* 0x52 */
- WLAN_MODULE_ID_MAX,
- WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
+ WLAN_MODULE_ID_MAX,
+ WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
} WLAN_MODULE_ID;
diff --git a/drivers/staging/fw-api/fw/wmi_services.h b/drivers/staging/fw-api/fw/wmi_services.h
index 4cff188..354d886 100644
--- a/drivers/staging/fw-api/fw/wmi_services.h
+++ b/drivers/staging/fw-api/fw/wmi_services.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -250,7 +250,161 @@
WMI_SERVICE_GMAC_OFFLOAD_SUPPORT=154, /* Support for GMAC */
WMI_SERVICE_SPOOF_MAC_SUPPORT=155, /* support for SERVICE_SPOOF_MAC */
WMI_SERVICE_PEER_TID_CONFIGS_SUPPORT=156, /* Support TID specific configurations per peer (ack,aggr,retry,rate) */
+ WMI_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT=157, /* Support vdev software retries configuration per AC (non aggr retry/aggr retry) */
+ WMI_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT=158, /* Support dual beacon on same channel on single MAC */
+ WMI_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT=159, /* Support dual beacon on different channel on single MAC */
+ WMI_SERVICE_MOTION_DET=160, /* support for motion detection config */
+ WMI_SERVICE_INFRA_MBSSID=161, /* support infra multi-BSSID feature */
+ WMI_SERVICE_OBSS_SPATIAL_REUSE=162, /* support spatial reuse feature */
+ WMI_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT=163, /* Support different beacon intervals on different VDEVs */
+ WMI_SERVICE_NAN_DBS_SUPPORT=164, /* Support DBS for NAN discovery interface */
+ WMI_SERVICE_NDI_DBS_SUPPORT=165, /* Support DBS for NAN data interface */
+ WMI_SERVICE_NAN_SAP_SUPPORT=166, /* Support SAP Concurrency for NAN Discovery interface */
+ WMI_SERVICE_NDI_SAP_SUPPORT=167, /* Support SAP Concurrency for NAN Data interface */
+ WMI_SERVICE_CFR_CAPTURE_SUPPORT=168, /* Support to capture uncompressed Channel Frequency Response (CFR) */
+ WMI_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1=169, /* Message type HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 in HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND */
+ WMI_SERVICE_ESP_SUPPORT=170, /* Support for Estimated Service Params IE */
+ WMI_SERVICE_PEER_CHWIDTH_CHANGE = 171, /* Support for host to update/re-intersect the node capability */
+ WMI_SERVICE_WLAN_HPCS_PULSE=172, /* Support for High Precision Clock Synchronization feature */
+ WMI_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT=173, /* Support for configuring chainmask per VDEV */
+ WMI_SERVICE_TX_DATA_MGMT_ACK_RSSI=174, /* ACK RSSI indication to host for host TX data and mgmt frame */
+ WMI_SERVICE_NAN_DISABLE_SUPPORT=175, /* indicates firmware is dependent on host to disable NAN incase of concurrencies */
+ WMI_SERVICE_NAN_DISABLE_SUPPORT__prototype = WMI_SERVICE_NAN_DISABLE_SUPPORT, /* alias, to clarify that NAN_DISABLE_SUPPORT is for prototype testing purposes */
+ WMI_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN=176, /* indicates FW supports uniformly excluding the HTC header length from the HTT H2T message length */
+ WMI_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION=177, /* indicates FW supports FDD coex with unequal isolation between BT and each of the WLAN chains */
+ /* WMI_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT:
+ * Support HW+FW db2dbm conversion for RSSI fields in rx descriptors
+ * and host/target messages.
+ * If enabled, HW and FW will convert SNR to RSSI by adding noise floor
+ * and rssi_offset from BDF to RSSI values that formerly had units of
+ * dB w.r.t. noise floor to convert the units to dBm.
+ * MAC beacon RSSI average register return a signed value for RSSI,
+ * as well as hw descriptors.
+ *-------------------------------------------------------------------------
+ * The RSSI field of below WMI messages will be changed to dBm units:
+ * WMI_MGMT_RX_EVENTID:
+ * wmi_mgmt_rx_hdr.rssi_ctl;
+ * WMI_UPDATE_STATS_EVENTID:
+ * wmi_rssi_stats.rssi_avg_beacon;
+ * wmi_rssi_stats.rssi_avg_data;
+ * wmi_snr_info.bcn_snr;
+ * wmi_snr_info.dat_snr;
+ * wmi_vdev_stats.bcn_rssi_history; (NOT USED IN FW)
+ * wmi_peer_stats.peer_rssi;
+ * WMI_WOW_WAKEUP_HOST_EVENTID:
+ * wmi_rssi_breach_event_fixed_param.rssi;
+ * wmi_roam_event_fixed_param.rssi;
+ * WMI_PEER_STA_KICKOUT_EVENTID:
+ * wmi_peer_sta_kickout_event_fixed_param.rssi;
+ * WMI_PASSPOINT_MATCH_EVENTID:
+ * wmi_passpoint_event_hdr.rssi;(NOT USED IN FW)
+ * WMI_PEER_INFO_EVENTID:
+ * wmi_peer_info.rssi;
+ * WMI_ROAM_SYNCH_EVENTID:
+ * wmi_roam_synch_event_fixed_param.rssi;
+ * WMI_ROAM_SCAN_STATS_EVENTID:
+ * wmi_roam_scan_stats_event_fixed_param.rssi;
+ * wmi_pdev_div_rssi_antid_event_id:
+ * wmi_pdev_div_rssi_antid_event_fixed_param.chain_rssi;
+ * wmi_rssi_breach_event_id
+ * WMI_INST_RSSI_STATS_EVENTID:
+ * wmi_inst_rssi_stats_resp_fixed_param.iRSSI;
+ * RSSI thresholds configured by host
+ * WMI_ROAM_SCAN_RSSI_THRESHOLD
+ * roam_scan_rssi_thresh snr
+ * boost_threshold_5g snr
+ * penalty_threshold_5g snr
+ * good_rssi_threshold snr
+ * roam_bg_scan_bad_rssi_thresh snr
+ * roam_earlystop_thres_min snr
+ * roam_earlystop_thres_max snr
+ * WMI_ROAM_AP_PROFILE
+ * rssi_abs_thresh snr
+ * WMI_ROAM_CONFIGURE_MAWC_CMDID:
+ * best_ap_rssi_threshold Snr
+ * wmi_ap_profile.rssi_abs_thresh;
+ * WMI_ROAM_SCAN_RSSI_THRESHOLD:
+ * wmi_roam_scan_extended_threshold_param.boost_threshold_5g;
+ * wmi_roam_scan_extended_threshold_param.penalty_threshold_5g;
+ * wmi_roam_scan_extended_threshold_param.good_rssi_threshold;
+ * wmi_roam_scan_rssi_threshold_fixed_param.roam_scan_rssi_thresh;
+ * wmi_roam_bg_scan_roaming_param.roam_bg_scan_bad_rssi_thresh;
+ * WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID:
+ * wmi_vdev_spectral_configure_cmd_fixed_param.spectral_scan_rssi_rpt_mode;
+ * wmi_vdev_spectral_configure_cmd_fixed_param.spectral_scan_rssi_thr;
+ * WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID:
+ * wmi_rssi_breach_monitor_config_fixed_param.low_rssi_breach_threshold;
+ * wmi_rssi_breach_monitor_config_fixed_param.hi_rssi_breach_threshold;
+ * WMI_STA_SMPS_PARAM_CMDID:
+ * wmi_sta_smps_param.value of below cmd IDs:
+ * // RSSI threshold to enter Dynamic SMPS mode from inactive mode
+ * WMI_STA_SMPS_PARAM_UPPER_RSSI_THRESH = 0,
+ * // RSSI threshold to enter Stalled-D-SMPS mode from D-SMPS mode
+ * // or to enter D-SMPS mode from Stalled-D-SMPS mode
+ * WMI_STA_SMPS_PARAM_STALL_RSSI_THRESH = 1,
+ * // RSSI threshold to disable SMPS modes
+ * WMI_STA_SMPS_PARAM_LOWER_RSSI_THRESH = 2,
+ * // Upper threshold for beacon-RSSI. Used to reduce RX chainmask.
+ * WMI_STA_SMPS_PARAM_UPPER_BRSSI_THRESH = 3,
+ * // Lower threshold for beacon-RSSI. Used to increase RX chainmask
+ * WMI_STA_SMPS_PARAM_LOWER_BRSSI_THRESH = 4,
+ * // Enable/Disable DTIM 1chRx feature
+ * WMI_STA_SMPS_PARAM_DTIM_1CHRX_ENABLE = 5
+ * WMI_TDLS_SET_STATE_CMDID:
+ * wmi_tdls_set_state_cmd_fixed_param.rssi_teardown_threshold;
+ * wmi_tdls_set_state_cmd_fixed_param.rssi_delta;
+ *-------------------------------------------------------------------------
+ * The RSSI fields of below HTT data type will change to dBm units:
+ * PREPACK struct htt_tx_wbm_completion.ack_frame_rssi;
+ * PREPACK struct htt_tx_wbm_transmit_status.ack_frame_rssi;
+ * htt_ppdu_stats_user_cmpltn_common_tlv.ack_rssi;
+ */
+ WMI_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178,
+ WMI_SERVICE_SUPPORT_EXTEND_ADDRESS=179, /* indicates firmware supports host memory addresses larger than 32 bit */
+ WMI_SERVICE_BEACON_RECEPTION_STATS=180, /* Support per vdev beacon stats info */
+ WMI_SERVICE_FETCH_TX_PN=181,
+ WMI_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, /* support peer ids unmap response from host */
+ WMI_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, /* indicate FW support per peer TX AMPDU size */
+ WMI_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, /* Firmware supports bss-color switch count handling */
+ WMI_SERVICE_HTT_PEER_STATS_SUPPORT = 185, /* Supports the feature where FW sends peer stats autonomously to Host via the HTT_T2H PEER_STATS_IND message */
+ WMI_SERVICE_UL_RU26_ALLOWED = 186, /* indicates support for RU26 in UL OFDMA */
+ WMI_SERVICE_GET_MWS_COEX_STATE = 187, /* FW provides MWS Coex info */
+ WMI_SERVICE_GET_MWS_DPWB_STATE = 188, /* FW provides LTE-Coex Dynamic Power Back-off info */
+ WMI_SERVICE_GET_MWS_TDM_STATE = 189, /* FW provides LTE-Coex TDM info */
+ WMI_SERVICE_GET_MWS_IDRX_STATE = 190, /* FW provides LTE-Coex IDRx info */
+ WMI_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, /* FW provides LTE-Coex Antenna sharing info */
+ WMI_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, /* FW provides enhanced tx power control configuration dump */
+ WMI_SERVICE_WLM_STATS_REQUEST = 193, /* FW supports WLAN latency manager stats request */
+ WMI_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, /* Extended Peer Tid configuration support for QoS related settings */
+ WMI_SERVICE_WPA3_FT_SAE_SUPPORT = 195, /* FW roaming support for WPA3_FT_SAE */
+ WMI_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, /* FW roaming support for WPA3_FT_SUITE_B */
+ WMI_SERVICE_VOW_ENABLE=197, /* FW supports a set of features to optimize VoW performance */
+ WMI_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, /* support WMI_PEER_CFR_CAPTURE_EVENT msg */
+ WMI_SERVICE_BROADCAST_TWT = 199, /* support of Broadcast TWT (Target Wake Time) for STA/AP */
+ WMI_SERVICE_RAP_DETECTION_SUPPORT = 200, /* indicate FW supports rogue AP detection */
+ WMI_SERVICE_PS_TDCC = 201, /* FW support tx_duty_cycle_control powersave */
+ WMI_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, /* BTCOEX Three-way CoEx Config Legacy Feature support */
+ WMI_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, /* BTCOEX Three-way CoEx Config Override Feature support */
+ WMI_SERVICE_TX_PWR_PER_PEER = 204, /* target supports per-peer tx pwr spec via WMI_PEER_USE_FIXED_PWR */
+ WMI_SERVICE_STA_PLUS_STA_SUPPORT = 205, /* indicates target supports STA + STA concurrency */
+ WMI_SERVICE_WPA3_FT_FILS = 206,
+ WMI_SERVICE_ADAPTIVE_11R_ROAM = 207, /* Indicates FW supports adaptive 11r roaming */
+ WMI_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, /* FW provides RF scores for chans in the service ready extension msg */
+ WMI_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, /* FW sends WMI_IFACE_COMBINATION_IND_EVENT msg immediately after WMI_SERVICE_READY_EXT_EVENT msg */
+ WMI_SERVICE_TX_COMPL_TSF64 = 210, /* FW supports 64-bit tx TSF in HTT_T2H TX_COMPL_IND msg */
+ WMI_SERVICE_DSM_ROAM_FILTER = 211, /* FW supports data stall AP mitigation while roaming */
+ WMI_SERVICE_PACKET_CAPTURE_SUPPORT = 212, /* target supports packet capture Mode (SMART MU) */
+ WMI_SERVICE_PER_PEER_HTT_STATS_RESET = 213, /* FW supports HTT per peer stats reset facility */
+ WMI_SERVICE_DELETE_ALL_PEER_SUPPORT = 214, /* target supports cmd to delete all peers within a vdev */
+ WMI_SERVICE_DYNAMIC_HW_MODE_SWITCH_SUPPORT = 215, /* target supports Dynamic HW mode switch */
+ WMI_SERVICE_MSDU_FLOW_OVERRIDE_BY_HOST = 216, /* target supports flow override feature */
+ WMI_SERVICE_WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENT= 217, /* target will send WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENT */
+ WMI_SERVICE_RX_FSE_SUPPORT = 218, /* target supports flow search through RxOLE FSE hw block */
+ WMI_SERVICE_FREQINFO_IN_METADATA = 219, /* FW provides freq_info during spectral scan */
+ WMI_SERVICE_EXT2_MSG = 220, /* WMI_SERVICE_READY_EXT2 msg is sent by target */
+ WMI_SERVICE_WPA3_SAE_ROAM_SUPPORT = 221, /* Indicates FW supports WPA3 SAE roaming */
+ WMI_SERVICE_WPA3_OWE_ROAM_SUPPORT = 222, /* Indicates FW supports WPA3 OWE roaming */
/******* ADD NEW SERVICES HERE *******/
diff --git a/drivers/staging/fw-api/fw/wmi_tlv_defs.h b/drivers/staging/fw-api/fw/wmi_tlv_defs.h
index 1baafd7..e7e7681 100644
--- a/drivers/staging/fw-api/fw/wmi_tlv_defs.h
+++ b/drivers/staging/fw-api/fw/wmi_tlv_defs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2019 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -839,6 +839,8 @@
WMITLV_TAG_STRUC_wmi_roam_lca_disallow_config_tlv_param,
WMITLV_TAG_STRUC_wmi_vdev_limit_offchan_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_roam_rssi_rejection_oce_config_param,
+ WMITLV_TAG_STRUC_wmi_roam_rejection_list_config_param = /* alias */
+ WMITLV_TAG_STRUC_wmi_roam_rssi_rejection_oce_config_param,
WMITLV_TAG_STRUC_wmi_unit_test_event_fixed_param,
WMITLV_TAG_STRUC_wmi_roam_fils_offload_tlv_param,
WMITLV_TAG_STRUC_wmi_pdev_update_pmk_cache_cmd_fixed_param,
@@ -912,6 +914,94 @@
WMITLV_TAG_STRUC_wmi_request_roam_scan_stats_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_roam_scan_stats_event_fixed_param,
WMITLV_TAG_STRUC_wmi_peer_tid_configurations_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_set_custom_sw_retry_th_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_get_tpc_power_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_get_tpc_power_evt_fixed_param,
+ WMITLV_TAG_STRUC_wmi_dma_buf_release_spectral_meta_data,
+ WMITLV_TAG_STRUC_wmi_motion_det_config_params_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_motion_det_base_line_config_params_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_motion_det_start_stop_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_motion_det_base_line_start_stop_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_motion_det_event,
+ WMITLV_TAG_STRUC_wmi_motion_det_base_line_event,
+ WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param,
+ WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_esp_estimate_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_nan_host_config_param,
+ WMITLV_TAG_STRUC_wmi_spectral_bin_scaling_params,
+ WMITLV_TAG_STRUC_wmi_peer_cfr_capture_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_peer_chan_width_switch_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_chan_width_peer_list,
+ WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_he_tb_action_frm_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_peer_extd2_stats,
+ WMITLV_TAG_STRUC_wmi_hpcs_pulse_start_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_ctl_failsafe_check_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_chainmask_config_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_bcn_offload_quiet_config_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_nan_event_info,
+ WMITLV_TAG_STRUC_wmi_ndp_channel_info,
+ WMITLV_TAG_STRUC_wmi_ndp_cmd_param,
+ WMITLV_TAG_STRUC_wmi_ndp_event_param,
+ WMITLV_TAG_STRUC_wmi_pdev_pktlog_filter_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_pktlog_filter_info,
+ WMITLV_TAG_STRUC_wmi_quiet_offload_info,
+ WMITLV_TAG_STRUC_wmi_get_bcn_recv_stats_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_bcn_recv_stats_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_peer_tx_pn_request_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_peer_tx_pn_response_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_tlv_arrays_len_param,
+ WMITLV_TAG_STRUC_wmi_peer_unmap_response_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_csc_switch_count_status_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_roam_bss_load_config_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_roam_blacklist_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_csc_vdev_list,
+ WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_info_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_state_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_dpwb_state_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_tdm_state_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_idrx_state_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_antenna_sharing_state_fixed_param,
+ WMITLV_TAG_STRUC_wmi_request_wlm_stats_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_wlm_stats_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_key_material_ext,
+ WMITLV_TAG_STRUC_wmi_peer_cfr_capture_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_cold_boot_cal_data_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_set_rap_config_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_set_rap_config_on_sta_ps_tlv_param,
+ WMITLV_TAG_STRUC_wmi_pdev_rap_info_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_sta_tdcc_config_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_roam_deauth_config_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_roam_idle_config_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_idle_trigger_monitor_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_stats_interference,
+ WMITLV_TAG_STRUC_wmi_roam_score_delta_param,
+ WMITLV_TAG_STRUC_wmi_roam_cnd_min_rssi_param,
+ WMITLV_TAG_STRUC_wmi_chan_rf_characterization_info,
+ WMITLV_TAG_STRUC_wmi_wlanfw_iface_cmb_ind_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_wlanfw_iface_combination_param,
+ WMITLV_TAG_STRUC_wmi_wlanfw_iface_limit_param,
+ WMITLV_TAG_STRUC_wmi_pdev_dsm_filter_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_bssid_disallow_list_config_param,
+ WMITLV_TAG_STRUC_wmi_mgmt_hdr,
+ WMITLV_TAG_STRUC_wmi_muedca_params_config_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_twt_btwt_invite_sta_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_twt_btwt_remove_sta_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_twt_btwt_invite_sta_complete_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_twt_btwt_remove_sta_complete_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_delete_all_peer_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_vdev_delete_all_peer_resp_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_chan_rf_characterization_info_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_oem_data_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_roam_enable_disable_trigger_reason_fixed_param,
+ WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_roam_preauth_status_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_roam_preauth_start_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_set_elna_bypass_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_get_elna_bypass_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_get_elna_bypass_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_roam_pmkid_request_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_peer_cfr_capture_event_phase_fixed_param,
} WMITLV_TAG_ID;
/*
@@ -926,6 +1016,7 @@
OP(WMI_PEER_SET_PARAM_CMDID) \
OP(WMI_STA_POWERSAVE_MODE_CMDID) \
OP(WMI_STA_POWERSAVE_PARAM_CMDID) \
+ OP(WMI_STA_TDCC_CONFIG_CMDID) \
OP(WMI_STA_DTIM_PS_METHOD_CMDID) \
OP(WMI_PDEV_SET_REGDOMAIN_CMDID) \
OP(WMI_PEER_TID_ADDBA_CMDID) \
@@ -1283,6 +1374,41 @@
OP(WMI_TWT_RESUME_DIALOG_CMDID) \
OP(WMI_REQUEST_ROAM_SCAN_STATS_CMDID) \
OP(WMI_PEER_TID_CONFIGURATIONS_CMDID) \
+ OP(WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID) \
+ OP(WMI_GET_TPC_POWER_CMDID) \
+ OP(WMI_MOTION_DET_CONFIG_PARAM_CMDID) \
+ OP(WMI_MOTION_DET_BASE_LINE_CONFIG_PARAM_CMDID) \
+ OP(WMI_MOTION_DET_START_STOP_CMDID) \
+ OP(WMI_MOTION_DET_BASE_LINE_START_STOP_CMDID) \
+ OP(WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID) \
+ OP(WMI_PEER_CFR_CAPTURE_CMDID) \
+ OP(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID) \
+ OP(WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID) \
+ OP(WMI_PDEV_HE_TB_ACTION_FRM_CMDID) \
+ OP(WMI_HPCS_PULSE_START_CMDID) \
+ OP(WMI_VDEV_CHAINMASK_CONFIG_CMDID) \
+ OP(WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID) \
+ OP(WMI_NDP_CMDID) \
+ OP(WMI_PDEV_PKTLOG_FILTER_CMDID) \
+ OP(WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID) \
+ OP(WMI_PEER_TX_PN_REQUEST_CMDID) \
+ OP(WMI_PEER_UNMAP_RESPONSE_CMDID) \
+ OP(WMI_ROAM_BSS_LOAD_CONFIG_CMDID) \
+ OP(WMI_VDEV_GET_MWS_COEX_INFO_CMDID) \
+ OP(WMI_REQUEST_WLM_STATS_CMDID) \
+ OP(WMI_PDEV_SET_RAP_CONFIG_CMDID) \
+ OP(WMI_ROAM_DEAUTH_CONFIG_CMDID) \
+ OP(WMI_ROAM_IDLE_CONFIG_CMDID) \
+ OP(WMI_IDLE_TRIGGER_MONITOR_CMDID) \
+ OP(WMI_PDEV_DSM_FILTER_CMDID) \
+ OP(WMI_TWT_BTWT_INVITE_STA_CMDID) \
+ OP(WMI_TWT_BTWT_REMOVE_STA_CMDID) \
+ OP(WMI_VDEV_DELETE_ALL_PEER_CMDID) \
+ OP(WMI_OEM_DATA_CMDID) \
+ OP(WMI_ROAM_ENABLE_DISABLE_TRIGGER_REASON_CMDID) \
+ OP(WMI_ROAM_PREAUTH_STATUS_CMDID) \
+ OP(WMI_SET_ELNA_BYPASS_CMDID) \
+ OP(WMI_GET_ELNA_BYPASS_CMDID) \
/* add new CMD_LIST elements above this line */
@@ -1293,6 +1419,7 @@
#define WMITLV_ALL_EVT_LIST(OP) \
OP(WMI_SERVICE_READY_EVENTID) \
OP(WMI_SERVICE_READY_EXT_EVENTID) \
+ OP(WMI_SERVICE_READY_EXT2_EVENTID) \
OP(WMI_READY_EVENTID) \
OP(WMI_SCAN_EVENTID) \
OP(WMI_PDEV_TPC_CONFIG_EVENTID) \
@@ -1489,6 +1616,35 @@
OP(WMI_TWT_PAUSE_DIALOG_COMPLETE_EVENTID) \
OP(WMI_TWT_RESUME_DIALOG_COMPLETE_EVENTID) \
OP(WMI_ROAM_SCAN_STATS_EVENTID) \
+ OP(WMI_GET_TPC_POWER_EVENTID) \
+ OP(WMI_MOTION_DET_HOST_EVENTID) \
+ OP(WMI_MOTION_DET_BASE_LINE_HOST_EVENTID) \
+ OP(WMI_ESP_ESTIMATE_EVENTID) \
+ OP(WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID) \
+ OP(WMI_NDP_EVENTID) \
+ OP(WMI_VDEV_BCN_RECEPTION_STATS_EVENTID) \
+ OP(WMI_PEER_TX_PN_RESPONSE_EVENTID) \
+ OP(WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID) \
+ OP(WMI_ROAM_BLACKLIST_EVENTID) \
+ OP(WMI_VDEV_GET_MWS_COEX_STATE_EVENTID) \
+ OP(WMI_VDEV_GET_MWS_COEX_DPWB_STATE_EVENTID) \
+ OP(WMI_VDEV_GET_MWS_COEX_TDM_STATE_EVENTID) \
+ OP(WMI_VDEV_GET_MWS_COEX_IDRX_STATE_EVENTID) \
+ OP(WMI_VDEV_GET_MWS_COEX_ANTENNA_SHARING_STATE_EVENTID) \
+ OP(WMI_WLM_STATS_EVENTID) \
+ OP(WMI_PEER_CFR_CAPTURE_EVENTID) \
+ OP(WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID) \
+ OP(WMI_PDEV_RAP_INFO_EVENTID) \
+ OP(WMI_IFACE_COMBINATION_IND_EVENTID) \
+ OP(WMI_VDEV_MGMT_OFFLOAD_EVENTID) \
+ OP(WMI_MUEDCA_PARAMS_CONFIG_EVENTID) \
+ OP(WMI_TWT_BTWT_INVITE_STA_COMPLETE_EVENTID) \
+ OP(WMI_TWT_BTWT_REMOVE_STA_COMPLETE_EVENTID) \
+ OP(WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID) \
+ OP(WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID) \
+ OP(WMI_ROAM_PREAUTH_START_EVENTID) \
+ OP(WMI_GET_ELNA_BYPASS_EVENTID) \
+ OP(WMI_ROAM_PMKID_REQUEST_EVENTID) \
/* add new EVT_LIST elements above this line */
@@ -1516,7 +1672,20 @@
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_CMDID);
-/* Peer flush Cmd*/
+/* Delete all peer Cmd */
+#define WMITLV_TABLE_WMI_VDEV_DELETE_ALL_PEER_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_delete_all_peer_cmd_fixed_param, wmi_vdev_delete_all_peer_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_ALL_PEER_CMDID);
+
+/* Peer unmap response Cmd */
+#define WMITLV_TABLE_WMI_PEER_UNMAP_RESPONSE_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_unmap_response_cmd_fixed_param, wmi_peer_unmap_response_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, peer_ids, WMITLV_SIZE_VAR)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_UNMAP_RESPONSE_CMDID);
+
+/* Peer flush Cmd */
#define WMITLV_TABLE_WMI_PEER_FLUSH_TIDS_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_flush_tids_cmd_fixed_param, wmi_peer_flush_tids_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -1540,6 +1709,12 @@
WMITLV_CREATE_PARAM_STRUC(WMI_STA_POWERSAVE_PARAM_CMDID);
+/* STA TDCC Param Config Cmd */
+#define WMITLV_TABLE_WMI_STA_TDCC_CONFIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_tdcc_config_cmd_fixed_param, wmi_sta_tdcc_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_STA_TDCC_CONFIG_CMDID);
+
/* STA DTIM PS METHOD Cmd */
#define WMITLV_TABLE_WMI_STA_DTIM_PS_METHOD_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_sta_dtim_ps_method_cmd_fixed_param, wmi_sta_dtim_ps_method_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -2073,6 +2248,12 @@
WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_STATS_CMDID);
+/* PN Request Cmd */
+#define WMITLV_TABLE_WMI_PEER_TX_PN_REQUEST_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tx_pn_request_cmd_fixed_param, wmi_peer_tx_pn_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TX_PN_REQUEST_CMDID);
+
/* Request for memory dump stats Cmd */
#define WMITLV_TABLE_WMI_GET_FW_MEM_DUMP_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_fw_mem_dump_fixed_param, wmi_get_fw_mem_dump_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -2111,6 +2292,12 @@
WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_LINK_STATS_CMDID);
+/* Request wlm stats Cmd */
+#define WMITLV_TABLE_WMI_REQUEST_WLM_STATS_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_wlm_stats_cmd_fixed_param, wmi_request_wlm_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_WLM_STATS_CMDID);
+
/* Network list offload config Cmd */
#define WMITLV_TABLE_WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nlo_config_cmd_fixed_param, wmi_nlo_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -2389,6 +2576,17 @@
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_LIMIT_OFFCHAN_CMDID);
+/* vdev per-AC SW retry configuration cmd */
+#define WMITLV_TABLE_WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_custom_sw_retry_th_cmd_fixed_param, wmi_vdev_set_custom_sw_retry_th_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID);
+
+#define WMITLV_TABLE_WMI_VDEV_CHAINMASK_CONFIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_chainmask_config_cmd_fixed_param, wmi_vdev_chainmask_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_CHAINMASK_CONFIG_CMDID);
+
/* PDEV Set Base Mac Address Cmd */
#define WMITLV_TABLE_WMI_PDEV_SET_BASE_MACADDR_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_base_macaddr_cmd_fixed_param, wmi_pdev_set_base_macaddr_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -2411,7 +2609,9 @@
#define WMITLV_TABLE_WMI_ROAM_AP_PROFILE(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_ap_profile_fixed_param, wmi_roam_ap_profile_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ap_profile, wmi_ap_profile, ap_profile, WMITLV_SIZE_FIX) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_cnd_scoring_param, wmi_roam_cnd_scoring_param, roam_cnd_scoring_param, WMITLV_SIZE_FIX)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_cnd_scoring_param, wmi_roam_cnd_scoring_param, roam_cnd_scoring_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_score_delta_param, roam_score_delta_param_list, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_cnd_min_rssi_param, roam_cnd_min_rssi_param_list, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_AP_PROFILE);
@@ -2563,6 +2763,12 @@
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_QUIET_MODE_CMDID);
+/* vdev set offload quiet Cmd */
+#define WMITLV_TABLE_WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_offload_quiet_config_cmd_fixed_param, wmi_vdev_bcn_offload_quiet_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID);
+
/* Setting custom aggregation size using command */
#define WMITLV_TABLE_WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_custom_aggr_size_cmd_fixed_param, wmi_vdev_set_custom_aggr_size_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -2870,6 +3076,59 @@
WMITLV_CREATE_PARAM_STRUC(WMI_REQUEST_ROAM_SCAN_STATS_CMDID);
+/* BSS load parameters for roam trigger */
+#define WMITLV_TABLE_WMI_ROAM_BSS_LOAD_CONFIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_bss_load_config_cmd_fixed_param, wmi_roam_bss_load_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_BSS_LOAD_CONFIG_CMDID);
+
+/* Deauth roam trigger parameters */
+#define WMITLV_TABLE_WMI_ROAM_DEAUTH_CONFIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_deauth_config_cmd_fixed_param, wmi_roam_deauth_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_DEAUTH_CONFIG_CMDID);
+
+/* Idle roam trigger parameters */
+#define WMITLV_TABLE_WMI_ROAM_IDLE_CONFIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_idle_config_cmd_fixed_param, wmi_roam_idle_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_IDLE_CONFIG_CMDID);
+
+/* Roam Pre-Authentication completion status */
+#define WMITLV_TABLE_WMI_ROAM_PREAUTH_STATUS_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_preauth_status_cmd_fixed_param, wmi_roam_preauth_status_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, pmkid, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_PREAUTH_STATUS_CMDID);
+
+/** Roam PMKID request event */
+#define WMITLV_TABLE_WMI_ROAM_PMKID_REQUEST_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_pmkid_request_event_fixed_param, wmi_roam_pmkid_request_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_pmkid_request_tlv_param, pmkid_request, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_PMKID_REQUEST_EVENTID);
+
+/* Screen Status Command parameters */
+#define WMITLV_TABLE_WMI_IDLE_TRIGGER_MONITOR_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_idle_trigger_monitor_cmd_fixed_param, wmi_idle_trigger_monitor_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_IDLE_TRIGGER_MONITOR_CMDID);
+
+/* Enable or disable roaming trigger reason */
+#define WMITLV_TABLE_WMI_ROAM_ENABLE_DISABLE_TRIGGER_REASON_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_enable_disable_trigger_reason_fixed_param, wmi_roam_enable_disable_trigger_reason_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_ENABLE_DISABLE_TRIGGER_REASON_CMDID);
+
+/* DSM filter parameters */
+#define WMITLV_TABLE_WMI_PDEV_DSM_FILTER_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_dsm_filter_fixed_param, wmi_pdev_dsm_filter_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_bssid_disallow_list_config_param, bssid_disallow_list, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DSM_FILTER_CMDID);
+
+#define WMITLV_TABLE_WMI_ROAM_BLACKLIST_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_blacklist_event_fixed_param, wmi_roam_blacklist_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_blacklist_with_timeout_tlv_param, blacklist_with_timeout, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_BLACKLIST_EVENTID);
+
+/* Roam Pre-Authentication Start Event */
+#define WMITLV_TABLE_WMI_ROAM_PREAUTH_START_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_preauth_start_event_fixed_param, wmi_roam_preauth_start_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_PREAUTH_START_EVENTID);
+
#define WMITLV_TABLE_WMI_LPI_RESULT_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_lpi_result_event_fixed_param, wmi_lpi_result_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
@@ -2904,7 +3163,8 @@
/* NaN Request */
#define WMITLV_TABLE_WMI_NAN_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_cmd_param, wmi_nan_cmd_param, fixed_param, WMITLV_SIZE_FIX) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_host_config_param, host_config, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_NAN_CMDID);
/* NAN Data Get Capabilities Cmd */
@@ -2922,6 +3182,7 @@
* A_UINT8 ndp_pmk[];
* A_INT8 ndp_passphrase[];
* A_INT8 nan_servicename[];
+ * wmi_ndp_transport_ip_param ndp_transport_ip_param;
*/
#define WMITLV_TABLE_WMI_NDP_INITIATOR_REQ_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_initiator_req_fixed_param, wmi_ndp_initiator_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \
@@ -2930,7 +3191,8 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_pmk, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, ndp_passphrase, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, nan_servicename, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, nan_servicename, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param, wmi_ndp_transport_ip_param, ndp_transport_ip_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_INITIATOR_REQ_CMDID);
/** NAN Data Responder Request Cmd
@@ -2941,6 +3203,7 @@
* A_UINT8 ndp_pmk[];
* A_INT8 ndp_passphrase[];
* A_INT8 nan_servicename[];
+ * wmi_ndp_transport_ip_param ndp_transport_ip_param;
*/
#define WMITLV_TABLE_WMI_NDP_RESPONDER_REQ_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_responder_req_fixed_param, wmi_ndp_responder_req_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \
@@ -2948,7 +3211,8 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_pmk, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, ndp_passphrase, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, nan_servicename, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, nan_servicename, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param, wmi_ndp_transport_ip_param, ndp_transport_ip_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_RESPONDER_REQ_CMDID);
/** NAN Data End Request Cmd
@@ -2962,6 +3226,11 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_end_req_PROTOTYPE, ndp_end_req_list, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_END_REQ_CMDID);
+/* NDP Request */
+#define WMITLV_TABLE_WMI_NDP_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_cmd_param, wmi_ndp_cmd_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CMDID);
+
/* RCPI Info Request Cmd */
#define WMITLV_TABLE_WMI_REQUEST_RCPI_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_request_rcpi_cmd_fixed_param, wmi_request_rcpi_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -3002,7 +3271,8 @@
#define WMITLV_TABLE_WMI_OBSS_SCAN_ENABLE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_obss_scan_enable_cmd_fixed_param, wmi_obss_scan_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, channels, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_field, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ie_field, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, chan_freqs, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_OBSS_SCAN_ENABLE_CMDID);
/* 2.4Ghz HT40 OBSS scan disable */
@@ -3207,7 +3477,7 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, bssid_preferred_list, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, bssid_preferred_factor, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_lca_disallow_config_tlv_param, lca_disallow_param, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_rssi_rejection_oce_config_param, rssi_rejection_list, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_rejection_list_config_param, rssi_rejection_list, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_FILTER_CMDID);
/* TSF timestamp action cmd */
@@ -3521,6 +3791,16 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_chip_power_stats_cmd_fixed_param, wmi_pdev_get_chip_power_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_CHIP_POWER_STATS_CMDID);
+/* WLAN GET mws conflict */
+#define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_INFO_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_info_cmd_fixed_param, wmi_vdev_get_mws_coex_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_MWS_COEX_INFO_CMDID);
+
+/* WLAN GET beacon reception Stats*/
+#define WMITLV_TABLE_WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_bcn_recv_stats_fixed_param, wmi_vdev_get_bcn_recv_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID);
+
/* pdev set stats threshold cmd*/
#define WMITLV_TABLE_WMI_PDEV_SET_STATS_THRESHOLD_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_stats_threshold_cmd_fixed_param, wmi_pdev_set_stats_threshold_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -3636,6 +3916,23 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlm_config_cmd_fixed_param, wmi_wlm_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_WLM_CONFIG_CMDID);
+/* Motion detection cmd */
+#define WMITLV_TABLE_WMI_MOTION_DET_CONFIG_PARAM_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_motion_det_config_params_cmd_fixed_param, wmi_motion_det_config_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MOTION_DET_CONFIG_PARAM_CMDID);
+
+#define WMITLV_TABLE_WMI_MOTION_DET_BASE_LINE_CONFIG_PARAM_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_motion_det_base_line_config_params_cmd_fixed_param, wmi_motion_det_base_line_config_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MOTION_DET_BASE_LINE_CONFIG_PARAM_CMDID);
+
+#define WMITLV_TABLE_WMI_MOTION_DET_START_STOP_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_motion_det_start_stop_cmd_fixed_param, wmi_motion_det_start_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MOTION_DET_START_STOP_CMDID);
+
+#define WMITLV_TABLE_WMI_MOTION_DET_BASE_LINE_START_STOP_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_motion_det_base_line_start_stop_cmd_fixed_param, wmi_motion_det_base_line_start_stop_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MOTION_DET_BASE_LINE_START_STOP_CMDID);
+
/* Pdev Set AC TX Queue Optimized Cmd */
#define WMITLV_TABLE_WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_ac_tx_queue_optimized_cmd_fixed_param, wmi_pdev_set_ac_tx_queue_optimized_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -3658,6 +3955,12 @@
WMITLV_CREATE_PARAM_STRUC(WMI_RUNTIME_DPD_RECAL_CMDID);
+/** Get TX power Cmd */
+#define WMITLV_TABLE_WMI_GET_TPC_POWER_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_tpc_power_cmd_fixed_param, wmi_get_tpc_power_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_TPC_POWER_CMDID);
+
/* TWT enable cmd */
#define WMITLV_TABLE_WMI_TWT_ENABLE_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param, wmi_twt_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -3688,11 +3991,84 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_resume_dialog_cmd_fixed_param, wmi_twt_resume_dialog_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_TWT_RESUME_DIALOG_CMDID);
+/* B-TWT STA invitation cmd */
+#define WMITLV_TABLE_WMI_TWT_BTWT_INVITE_STA_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_btwt_invite_sta_cmd_fixed_param, wmi_twt_btwt_invite_sta_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_TWT_BTWT_INVITE_STA_CMDID);
+
+/* B-TWT STA removal cmd */
+#define WMITLV_TABLE_WMI_TWT_BTWT_REMOVE_STA_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_btwt_remove_sta_cmd_fixed_param, wmi_twt_btwt_remove_sta_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_TWT_BTWT_REMOVE_STA_CMDID);
+
/* Set peer tid configurations Cmd */
#define WMITLV_TABLE_WMI_PEER_TID_CONFIGURATIONS_CMDID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tid_configurations_cmd_fixed_param, wmi_peer_tid_configurations_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_CONFIGURATIONS_CMDID);
+/* OBSS_PD Spatial_Reuse cnmd */
+#define WMITLV_TABLE_WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_cmd_fixed_param, wmi_obss_spatial_reuse_set_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID);
+
+/* Peer CFR capture cmd */
+#define WMITLV_TABLE_WMI_PEER_CFR_CAPTURE_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_cfr_capture_cmd_fixed_param, wmi_peer_cfr_capture_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_cfr_capture_event_phase_fixed_param, wmi_peer_cfr_capture_event_phase_fixed_param, phase_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CFR_CAPTURE_CMDID);
+
+/* CHANNEL WIDTH SWITCH commands for peers. */
+#define WMITLV_TABLE_WMI_PEER_CHAN_WIDTH_SWITCH_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_chan_width_switch_cmd_fixed_param, wmi_peer_chan_width_switch_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_chan_width_peer_list, peer_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID);
+
+/* OBSS_PD Spatial_Reuse Set Default OBSS Thresholds */
+#define WMITLV_TABLE_WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID);
+
+/* HE TB Action frame enable/disable */
+#define WMITLV_TABLE_WMI_PDEV_HE_TB_ACTION_FRM_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_he_tb_action_frm_cmd_fixed_param, \
+ wmi_pdev_he_tb_action_frm_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_HE_TB_ACTION_FRM_CMDID);
+
+/* HPCS Pulse cmd */
+#define WMITLV_TABLE_WMI_HPCS_PULSE_START_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_hpcs_pulse_start_cmd_fixed_param, wmi_hpcs_pulse_start_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_HPCS_PULSE_START_CMDID);
+
+/* PDev Packet Log filter Cmd */
+#define WMITLV_TABLE_WMI_PDEV_PKTLOG_FILTER_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_pktlog_filter_cmd_fixed_param, wmi_pdev_pktlog_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_pktlog_filter_info, pdev_pktlog_filter_info, WMITLV_SIZE_VAR)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_PKTLOG_FILTER_CMDID);
+
+/* PDev Set Rogue AP Config cmd */
+#define WMITLV_TABLE_WMI_PDEV_SET_RAP_CONFIG_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_set_rap_config_fixed_param, wmi_pdev_set_rap_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_rap_config_on_sta_ps_tlv_param, rap_param, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RAP_CONFIG_CMDID);
+
+/* OEM Data config cmd */
+#define WMITLV_TABLE_WMI_OEM_DATA_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_oem_data_cmd_fixed_param, wmi_oem_data_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, oem_data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DATA_CMDID);
+
+/* Set ELNA BYPASS cmd */
+#define WMITLV_TABLE_WMI_SET_ELNA_BYPASS_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_set_elna_bypass_cmd_fixed_param, wmi_set_elna_bypass_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_SET_ELNA_BYPASS_CMDID);
+
+/* Get ELNA BYPASS cmd */
+#define WMITLV_TABLE_WMI_GET_ELNA_BYPASS_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_get_elna_bypass_cmd_fixed_param, wmi_get_elna_bypass_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_ELNA_BYPASS_CMDID);
+
/************************** TLV definitions of WMI events *******************************/
@@ -3722,9 +4098,30 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_MAC_PHY_CHAINMASK_CAPABILITY, mac_phy_chainmask_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_OEM_DMA_RING_CAPABILITIES, oem_dma_ring_caps, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_WMI_SAR_CAPABILITIES, WMI_SAR_CAPABILITIES, sar_caps, WMITLV_SIZE_FIX) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_DMA_RING_CAPABILITIES, dma_ring_caps, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_DMA_RING_CAPABILITIES, dma_ring_caps, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_spectral_bin_scaling_params, wmi_bin_scaling_params, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_CHAN_RF_CHARACTERIZATION_INFO, wmi_chan_rf_characterization_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT_EVENTID);
+/* SERVICE_READY_EXT2 event */
+#define WMITLV_TABLE_WMI_SERVICE_READY_EXT2_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param, wmi_service_ready_ext2_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_DMA_RING_CAPABILITIES, dma_ring_caps, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_spectral_bin_scaling_params, wmi_bin_scaling_params, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_SERVICE_READY_EXT2_EVENTID);
+
+#define WMITLV_TABLE_WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_chan_rf_characterization_info_event_fixed_param, wmi_chan_rf_characterization_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_CHAN_RF_CHARACTERIZATION_INFO, wmi_chan_rf_characterization_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID);
+
+/* iface combination indication event */
+#define WMITLV_TABLE_WMI_IFACE_COMBINATION_IND_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlanfw_iface_cmb_ind_event_fixed_param, wmi_wlanfw_iface_cmb_ind_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlanfw_iface_combination, combinations, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wlanfw_iface_limit, limits, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_IFACE_COMBINATION_IND_EVENTID);
+
/* Ready event */
#define WMITLV_TABLE_WMI_READY_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ready_event_fixed_param, wmi_ready_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -3796,14 +4193,16 @@
WMITLV_CREATE_PARAM_STRUC(WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID);
/* Update_whal_mib_stats Event */
-#define WMITLV_TABLE_WMI_UPDATE_WHAL_MIB_STATS_EVENTID(id,op,buf,len) \
+#define WMITLV_TABLE_WMI_UPDATE_WHAL_MIB_STATS_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_update_whal_mib_stats_event_fixed_param, wmi_update_whal_mib_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_WHAL_MIB_STATS_EVENTID);
/* PDEV TPC Config Event */
-#define WMITLV_TABLE_WMI_PDEV_TPC_CONFIG_EVENTID(id,op,buf,len) \
+#define WMITLV_TABLE_WMI_PDEV_TPC_CONFIG_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_tpc_config_event_fixed_param, wmi_pdev_tpc_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ratesArray, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ratesArray, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tlv_arrays_len_param, ctlPwrTbl_param, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ctlPwrTbl_buf, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_TPC_CONFIG_EVENTID);
/* PDEV DIV RSSI Antenna index Event */
@@ -3845,7 +4244,8 @@
/* Mgmt TX completion event */
#define WMITLV_TABLE_WMI_MGMT_TX_COMPLETION_EVENTID(id,op,buf,len) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_event_fixed_param, wmi_mgmt_tx_compl_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_event_fixed_param, wmi_mgmt_tx_compl_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_hdr, mgmt_hdr, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_COMPLETION_EVENTID);
/* offchan data TX completion event */
@@ -3858,7 +4258,9 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_tx_compl_bundle_event_fixed_param, wmi_mgmt_tx_compl_bundle_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, desc_ids, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, status, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ppdu_id, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ppdu_id, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ack_rssi, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_mgmt_hdr, mgmt_hdr, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID);
/* VDEV Start response Event */
@@ -3928,8 +4330,11 @@
WMITLV_CREATE_PARAM_STRUC(WMI_AGGR_STATE_TRIG_EVENTID);
/* Roam Event */
-#define WMITLV_TABLE_WMI_ROAM_EVENTID(id,op,buf,len) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_event_fixed_param, wmi_roam_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+#define WMITLV_TABLE_WMI_ROAM_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_event_fixed_param, wmi_roam_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, deauth_disassoc_frame, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_EVENTID);
/* Roam Synch Event */
@@ -3943,7 +4348,8 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, reassoc_req_frame, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_hw_mode_transition_event_fixed_param, hw_mode_transition_fixed_param, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_pdev_set_hw_mode_response_vdev_mac_entry, wmi_pdev_set_hw_mode_response_vdev_mac_mapping, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_fils_synch_tlv_param, roam_fils_synch_info, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_fils_synch_tlv_param, roam_fils_synch_info, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_key_material_ext, key_ext, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SYNCH_EVENTID);
/* Roam Synch frame Event */
@@ -3963,7 +4369,9 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_hb_ind_event_fixed_param, hb_indevt, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, WMI_GTK_OFFLOAD_STATUS_EVENT_fixed_param, wow_gtkigtk, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_oic_ping_handoff_event, wow_oic_ping_handoff, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dhcp_lease_renew_event, wow_dhcp_lease_renew, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dhcp_lease_renew_event, wow_dhcp_lease_renew, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_motion_det_event, md_indevt, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_motion_det_base_line_event, bl_indevt, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_WOW_WAKEUP_HOST_EVENTID);
#define WMITLV_TABLE_WMI_WOW_INITIAL_WAKEUP_EVENTID(id,op,buf,len) \
@@ -3991,6 +4399,16 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_keepalive_event_fixed_param, wmi_vdev_get_keepalive_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_KEEPALIVE_EVENTID);
+/** Get TX power Event */
+#define WMITLV_TABLE_WMI_GET_TPC_POWER_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_tpc_power_evt_fixed_param, wmi_get_tpc_power_evt_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_TPC_POWER_EVENTID);
+
+/** Get MU EDCA report param event */
+#define WMITLV_TABLE_WMI_MUEDCA_PARAMS_CONFIG_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_muedca_params_config_event_fixed_param, wmi_muedca_params_config_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MUEDCA_PARAMS_CONFIG_EVENTID);
+
/* GPIO Input Event */
#define WMITLV_TABLE_WMI_GPIO_INPUT_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_gpio_input_event_fixed_param, wmi_gpio_input_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -4106,10 +4524,21 @@
#define WMITLV_TABLE_WMI_HOST_SWBA_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param, wmi_host_swba_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tim_info, tim_info, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_info, p2p_noa_info, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_info, p2p_noa_info, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_quiet_offload_info, quiet_offload_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_HOST_SWBA_EVENTID);
+/* HOST SWBA Event v2 */
+#define WMITLV_TABLE_WMI_HOST_SWBA_V2_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param, wmi_host_swba_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tim_info_v2, tim_info, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_p2p_noa_info, p2p_noa_info, WMITLV_SIZE_VAR)
+
+WMITLV_CREATE_PARAM_STRUC(WMI_HOST_SWBA_V2_EVENTID);
+
+
/* HOST SWFDA Event requesting host to queue a FILS Discovery frame for transmission */
#define WMITLV_TABLE_WMI_HOST_SWFDA_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_swfda_event_fixed_param, wmi_host_swfda_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -4122,9 +4551,15 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_per_chain_rssi_stats, wmi_per_chain_rssi_stats, chain_stats, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rssi_stats, rssi_stats, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_congestion_stats, congestion_stats, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_congestion_stats, congestion_stats, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_extd2_stats, peer_extd2_stats, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_UPDATE_STATS_EVENTID);
+/* Update PN response Event */
+#define WMITLV_TABLE_WMI_PEER_TX_PN_RESPONSE_EVENTID(id,op,buf,len)\
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_tx_pn_response_event_fixed_param, wmi_peer_tx_pn_response_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TX_PN_RESPONSE_EVENTID);
+
/* For vdev based ht/vht info upload*/
#define WMITLV_TABLE_WMI_UPDATE_VDEV_RATE_STATS_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_rate_stats_event_fixed_param, wmi_vdev_rate_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -4175,6 +4610,12 @@
WMITLV_CREATE_PARAM_STRUC(WMI_RADIO_LINK_STATS_EVENTID);
+/* Update WLM stats event */
+#define WMITLV_TABLE_WMI_WLM_STATS_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlm_stats_event_fixed_param, wmi_wlm_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_WLM_STATS_EVENTID);
+
/* PDEV QVIT Event */
#define WMITLV_TABLE_WMI_PDEV_QVIT_EVENTID(id,op,buf,len)\
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
@@ -4316,9 +4757,10 @@
WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DMA_RING_CFG_RSP_EVENTID)
/* NAN Response/Indication Event */
-#define WMITLV_TABLE_WMI_NAN_EVENTID(id,op,buf,len) \
+#define WMITLV_TABLE_WMI_NAN_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_event_hdr, wmi_nan_event_hdr, fixed_param, WMITLV_SIZE_FIX) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_nan_event_info, event_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_NAN_EVENTID);
/* NAN discovery interface created event */
@@ -4380,12 +4822,14 @@
* structure. The TLV's are:
* A_UINT8 ndp_cfg[];
* A_UINT8 ndp_app_info[];
+ * wmi_ndp_transport_ip_param ndp_transport_ip_param;
*/
#define WMITLV_TABLE_WMI_NDP_INDICATION_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_indication_event_fixed_param, wmi_ndp_indication_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_scid, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_scid, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param, wmi_ndp_transport_ip_param, ndp_transport_ip_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_INDICATION_EVENTID);
/** NDP confirm event
@@ -4394,13 +4838,16 @@
* A_UINT8 ndp_cfg[];
* A_UINT8 ndp_app_info[];
* wmi_channel ndp_channel_list[];
+ * wmi_ndp_transport_ip_param ndp_transport_ip_param;
*/
#define WMITLV_TABLE_WMI_NDP_CONFIRM_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_confirm_event_fixed_param, wmi_ndp_confirm_event_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_cfg, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, ndp_app_info, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, ndp_channel_list, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, nss_list, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, nss_list, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param, wmi_ndp_transport_ip_param, ndp_transport_ip_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_channel_info, ndp_channel_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_NDP_CONFIRM_EVENTID);
/** NDP end indication event
@@ -4423,9 +4870,15 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndl_schedule_update_fixed_param, wmi_ndl_schedule_update_fixed_param_PROTOTYPE, fixed_param, WMITLV_SIZE_FIX) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, ndp_instance_list, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel, ndl_channel_list, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, nss_list, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, nss_list, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_ndp_channel_info, ndp_channel_info, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_NDL_SCHEDULE_UPDATE_EVENTID);
+/* NDP Event */
+#define WMITLV_TABLE_WMI_NDP_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ndp_event_param, wmi_ndp_event_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_NDP_EVENTID);
+
/* Update RCPI Info Event */
#define WMITLV_TABLE_WMI_UPDATE_RCPI_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_update_rcpi_event_fixed_param, wmi_update_rcpi_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -4471,6 +4924,11 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_delete_resp_event_fixed_param, wmi_peer_delete_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PEER_DELETE_RESP_EVENTID);
+/* delete all peer response Event */
+#define WMITLV_TABLE_WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_delete_all_peer_resp_event_fixed_param, wmi_vdev_delete_all_peer_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID);
+
/* peer assoc conf Event */
#define WMITLV_TABLE_WMI_PEER_ASSOC_CONF_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -4668,6 +5126,35 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, debug_registers, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CHIP_POWER_STATS_EVENTID);
+#define WMITLV_TABLE_WMI_VDEV_BCN_RECEPTION_STATS_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_recv_stats_event_fixed_param, wmi_vdev_bcn_recv_stats_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_BCN_RECEPTION_STATS_EVENTID);
+
+/* WLAN GET mws coex state */
+#define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_STATE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_state_fixed_param, wmi_vdev_get_mws_coex_state_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_MWS_COEX_STATE_EVENTID);
+
+/* WLAN GET Dynamic power back-off state */
+#define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_DPWB_STATE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_dpwb_state_fixed_param, wmi_vdev_get_mws_coex_dpwb_state_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_MWS_COEX_DPWB_STATE_EVENTID);
+
+/* WLAN GET TDM state */
+#define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_TDM_STATE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_tdm_state_fixed_param, wmi_vdev_get_mws_coex_tdm_state_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_MWS_COEX_TDM_STATE_EVENTID);
+
+/* WLAN GET Idrx state */
+#define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_IDRX_STATE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_idrx_state_fixed_param, wmi_vdev_get_mws_coex_idrx_state_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_MWS_COEX_IDRX_STATE_EVENTID);
+
+/* WLAN GET antenna sharing state */
+#define WMITLV_TABLE_WMI_VDEV_GET_MWS_COEX_ANTENNA_SHARING_STATE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_antenna_sharing_state_fixed_param, wmi_vdev_get_mws_coex_antenna_sharing_state_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_MWS_COEX_ANTENNA_SHARING_STATE_EVENTID);
+
#define WMITLV_TABLE_WMI_PDEV_ANI_OFDM_LEVEL_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_ani_ofdm_event_fixed_param, wmi_ani_ofdm_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_ANI_OFDM_LEVEL_EVENTID);
@@ -4751,6 +5238,7 @@
* array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_mcs_array_len + MCS index
* Contains a count of rx PPDUs for each MCS of each AC of each peer.
* wmi_stats_period stats_period[]; Array length is specified by stats_period_array_len
+ * wmi_stats_interference stats_interference[]; Array length is determied by dividing array level TLV header's length value by array-element TLV header's length value.
*
* For example, if there were 2 peers (X and Y) whose stats were being reported,
* the message and its TLV arrays would look like this:
@@ -4841,7 +5329,8 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_rx_stats, rx_stats, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rx_mpdu_aggr, WMITLV_SIZE_VAR) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rx_mcs, WMITLV_SIZE_VAR) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_stats_period, stats_period, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_stats_period, stats_period, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_stats_interference, stats_interference, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_REPORT_STATS_EVENTID);
#define WMITLV_TABLE_WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID(id, op, buf, len) \
@@ -4873,6 +5362,11 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID);
+#define WMITLV_TABLE_WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_csc_switch_count_status_event_fixed_param, wmi_pdev_csc_switch_count_status_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_csc_vdev_list, vdev_info, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID);
+
/* cal version response event */
#define WMITLV_TABLE_WMI_PDEV_CHECK_CAL_VERSION_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_check_cal_version_event_fixed_param, wmi_pdev_check_cal_version_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
@@ -4902,9 +5396,14 @@
/* dma buffer release event */
#define WMITLV_TABLE_WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_dma_buf_release_fixed_param, wmi_dma_buf_release_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
- WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR)
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_dma_buf_release_spectral_meta_data, meta_data, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID);
+/* ctl failsafe check event */
+#define WMITLV_TABLE_WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_ctl_failsafe_check_fixed_param, wmi_pdev_ctl_failsafe_check_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID);
/* UNIT-TEST Event */
#define WMITLV_TABLE_WMI_UNIT_TEST_EVENTID(id,op,buf,len) \
@@ -4943,6 +5442,16 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_resume_dialog_complete_event_fixed_param, wmi_twt_resume_dialog_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_TWT_RESUME_DIALOG_COMPLETE_EVENTID);
+/* inviting STA to B-TWT dialog complete Event */
+#define WMITLV_TABLE_WMI_TWT_BTWT_INVITE_STA_COMPLETE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_btwt_invite_sta_complete_event_fixed_param, wmi_twt_btwt_invite_sta_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_TWT_BTWT_INVITE_STA_COMPLETE_EVENTID);
+
+/* removing STA from B-TWT dialog complete Event */
+#define WMITLV_TABLE_WMI_TWT_BTWT_REMOVE_STA_COMPLETE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_twt_btwt_remove_sta_complete_event_fixed_param, wmi_twt_btwt_remove_sta_complete_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_TWT_BTWT_REMOVE_STA_COMPLETE_EVENTID);
+
/* Event to send roam scan stats */
#define WMITLV_TABLE_WMI_ROAM_SCAN_STATS_EVENTID(id,op,buf,len) \
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_stats_event_fixed_param, wmi_roam_scan_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
@@ -4961,6 +5470,45 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, rssi, WMITLV_SIZE_VAR)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SCAN_STATS_EVENTID);
+/* Motion detection events */
+#define WMITLV_TABLE_WMI_MOTION_DET_HOST_EVENTID(id,op,buf,len) \
+WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_motion_det_event, wmi_motion_det_event, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MOTION_DET_HOST_EVENTID);
+
+#define WMITLV_TABLE_WMI_MOTION_DET_BASE_LINE_HOST_EVENTID(id,op,buf,len) \
+WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_motion_det_base_line_event, wmi_motion_det_base_line_event, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_MOTION_DET_BASE_LINE_HOST_EVENTID);
+
+#define WMITLV_TABLE_WMI_ESP_ESTIMATE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_esp_estimate_event_fixed_param, wmi_esp_estimate_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_ESP_ESTIMATE_EVENTID);
+
+/* Peer CFR capture event */
+#define WMITLV_TABLE_WMI_PEER_CFR_CAPTURE_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_cfr_capture_event_fixed_param, wmi_peer_cfr_capture_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CFR_CAPTURE_EVENTID);
+
+#define WMITLV_TABLE_WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cold_boot_cal_data_fixed_param, wmi_cold_boot_cal_data_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID);
+
+/* rogue ap info event */
+#define WMITLV_TABLE_WMI_PDEV_RAP_INFO_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_rap_info_event_fixed_param, wmi_pdev_rap_info_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_RAP_INFO_EVENTID);
+
+/* Offload TX mgmt frames */
+#define WMITLV_TABLE_WMI_VDEV_MGMT_OFFLOAD_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_mgmt_hdr, wmi_mgmt_hdr, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, bufp, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_MGMT_OFFLOAD_EVENTID);
+
+/* get ELNA BYPASS status event */
+#define WMITLV_TABLE_WMI_GET_ELNA_BYPASS_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_elna_bypass_event_fixed_param, wmi_get_elna_bypass_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_GET_ELNA_BYPASS_EVENTID);
+
#ifdef __cplusplus
}
diff --git a/drivers/staging/fw-api/fw/wmi_unified.h b/drivers/staging/fw-api/fw/wmi_unified.h
index da7adcf..1186b59 100644
--- a/drivers/staging/fw-api/fw/wmi_unified.h
+++ b/drivers/staging/fw-api/fw/wmi_unified.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2010-2019 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -150,7 +150,7 @@
}
/** 2 word representation of MAC addr */
-typedef struct {
+typedef struct _wmi_mac_addr {
/** upper 4 bytes of MAC address */
A_UINT32 mac_addr31to0;
/** lower 2 bytes of MAC address */
@@ -178,6 +178,16 @@
} while (0)
/*
+ * The below function declarations are for implementations on some
+ * platforms of the above macros, but in function form, to save code
+ * memory by avoiding macro-inlining of a non-trivial amount of code.
+ * These function versions of the above macros may not be available
+ * on all host and target platforms.
+ */
+void wmi_mac_addr_to_char_array(wmi_mac_addr *pwmi_mac_addr, A_UINT8 *c_macaddr);
+void wmi_char_array_to_mac_addr(A_UINT8 *c_macaddr, wmi_mac_addr *pwmi_mac_addr);
+
+/*
* wmi command groups.
*/
typedef enum {
@@ -243,6 +253,10 @@
WMI_GRP_WLM, /* 0x3c WLAN Latency Manager */
WMI_GRP_11K_OFFLOAD, /* 0x3d */
WMI_GRP_TWT, /* 0x3e TWT (Target Wake Time) for STA and AP */
+ WMI_GRP_MOTION_DET, /* 0x3f */
+ WMI_GRP_SPATIAL_REUSE, /* 0x40 */
+ WMI_GRP_ESP, /* 0x41 Estimate Service Parameters (802.11mc) */
+ WMI_GRP_HPCS_PULSE, /* 0x42 */
} WMI_GRP_ID;
#define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1)
@@ -387,6 +401,14 @@
WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID,
/* set a generic direct DMA ring config */
WMI_PDEV_DMA_RING_CFG_REQ_CMDID,
+ /* enable/disable Action frame response as HE TB PPDU */
+ WMI_PDEV_HE_TB_ACTION_FRM_CMDID,
+ /** filter packet log based on MAC address */
+ WMI_PDEV_PKTLOG_FILTER_CMDID,
+ /** wmi command for setting rogue ap configuration */
+ WMI_PDEV_SET_RAP_CONFIG_CMDID,
+ /** Specify DSM filters along with disallow bssid filters */
+ WMI_PDEV_DSM_FILTER_CMDID,
/* VDEV (virtual device) specific commands */
/** vdev create */
@@ -450,6 +472,16 @@
WMI_VDEV_GET_TX_POWER_CMDID,
/* limit STA offchannel activity */
WMI_VDEV_LIMIT_OFFCHAN_CMDID,
+ /** To set custom software retries per-AC for vdev */
+ WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID,
+ /** To set chainmask configuration for vdev */
+ WMI_VDEV_CHAINMASK_CONFIG_CMDID,
+
+ WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID,
+ /* request LTE-Coex info */
+ WMI_VDEV_GET_MWS_COEX_INFO_CMDID,
+ /** delete all peer (excluding bss peer) */
+ WMI_VDEV_DELETE_ALL_PEER_CMDID,
/* peer specific commands */
@@ -522,6 +554,35 @@
*/
WMI_PEER_TID_CONFIGURATIONS_CMDID,
+ /** Peer configuration for Channel Frequency Response (CFR) capture
+ * of type wmi_peer_cfr_capture_cmd.
+ *
+ * On targets that do not use the direct DMA framework,
+ * completion of the CFR capture is communicated through
+ * HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND.
+ * Such targets will set WMI_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1
+ * in WMI Service Ready.
+ *
+ * On targets that use direct DMA, completion of CFR capture is
+ * communicated through WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID
+ * using module ID WMI_DMA_RING_CONFIG_MODULE_RTT.
+ * Such targets will set WMI_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1
+ * in WMI Service Ready and enumerate WMI_DMA_RING_CONFIG_MODULE_RTT
+ * in the dma_ring_caps entry of WMI_SERVICE_READY_EXT_EVENTID.
+ * Additional MAC metadata is provided in WMI_PEER_CFR_CAPTURE_EVENTID.
+ */
+ WMI_PEER_CFR_CAPTURE_CMDID,
+
+ /** WMI command related to AP channel width switching */
+ WMI_PEER_CHAN_WIDTH_SWITCH_CMDID,
+
+ /** WMI command to fetch current tx PN for the peer */
+ WMI_PEER_TX_PN_REQUEST_CMDID,
+
+ /** unmap response with peer ids */
+ WMI_PEER_UNMAP_RESPONSE_CMDID,
+
+
/* beacon/management specific commands */
/** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */
@@ -551,6 +612,8 @@
WMI_BCN_OFFLOAD_CTRL_CMDID,
/** Cmd to enable FW handling BSS color change notification from AP. */
WMI_BSS_COLOR_CHANGE_ENABLE_CMDID,
+ /** To configure Beacon offload quiet-ie params */
+ WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID,
/** commands to directly control ba negotiation directly from host. only used in test mode */
@@ -573,6 +636,8 @@
WMI_STA_POWERSAVE_PARAM_CMDID,
/** set station mimo powersave mode */
WMI_STA_MIMO_PS_MODE_CMDID,
+ /** config station TX cycle percentage in a beacon interval */
+ WMI_STA_TDCC_CONFIG_CMDID,
/** DFS-specific commands */
@@ -629,7 +694,22 @@
/** Enable or Disable Fast Initial Link Setup (FILS) feature */
WMI_ENABLE_FILS_CMDID,
/** Request for roam scan stats */
- WMI_REQUEST_ROAM_SCAN_STATS_CMDID,
+ WMI_REQUEST_ROAM_SCAN_STATS_CMDID,
+ /** Configure BSS load parameters for roam trigger */
+ WMI_ROAM_BSS_LOAD_CONFIG_CMDID,
+ /** Configure deauth roam trigger parameters */
+ WMI_ROAM_DEAUTH_CONFIG_CMDID,
+ /** Configure idle roam trigger parameters */
+ WMI_ROAM_IDLE_CONFIG_CMDID,
+ /**
+ * WMI_ROAM_DSM_FILTER_CMDID is deprecated and should be unused,
+ * but leave it reserved just to be safe.
+ */
+ DEPRECATED__WMI_ROAM_DSM_FILTER_CMDID,
+ /** Enable or disable roaming triggers */
+ WMI_ROAM_ENABLE_DISABLE_TRIGGER_REASON_CMDID,
+ /** Pre-Authentication completion status command */
+ WMI_ROAM_PREAUTH_STATUS_CMDID,
/** offload scan specific commands */
/** set offload scan AP profile */
@@ -785,6 +865,10 @@
/** One time request for radio channel stats */
WMI_REQUEST_RADIO_CHAN_STATS_CMDID,
+ /** request for WLM (wlan latency manager) stats */
+ WMI_REQUEST_WLM_STATS_CMDID,
+
+
/** ARP OFFLOAD REQUEST*/
WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ARP_NS_OFL),
@@ -899,6 +983,14 @@
WMI_THERM_THROT_SET_CONF_CMDID,
/* set runtime dpd recalibration params */
WMI_RUNTIME_DPD_RECAL_CMDID,
+ /* get TX power for input HALPHY parameters */
+ WMI_GET_TPC_POWER_CMDID,
+ /* Specify when to start monitoring for idle state */
+ WMI_IDLE_TRIGGER_MONITOR_CMDID,
+ /** set ELNA BYPASS status */
+ WMI_SET_ELNA_BYPASS_CMDID,
+ /** get ELNA BYPASS status */
+ WMI_GET_ELNA_BYPASS_CMDID,
/* Offload 11k related requests */
WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD),
@@ -990,12 +1082,17 @@
WMI_BATCH_SCAN_DISABLE_CMDID,
/*get batch scan result*/
WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID,
+
+
/* OEM related cmd */
WMI_OEM_REQ_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_OEM),
WMI_OEM_REQUEST_CMDID, /* UNUSED */
/* OEM related cmd used for Low Power ranging */
WMI_LPI_OEM_REQ_CMDID,
WMI_OEM_DMA_RING_CFG_REQ_CMDID,
+ /** Command to handle OEM's opaque data */
+ WMI_OEM_DATA_CMDID,
+
/** Nan Request */
WMI_NAN_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_NAN),
@@ -1114,6 +1211,7 @@
WMI_NDP_INITIATOR_REQ_CMDID,
WMI_NDP_RESPONDER_REQ_CMDID,
WMI_NDP_END_REQ_CMDID,
+ WMI_NDP_CMDID,
/** WMI commands related to HW data filtering **/
WMI_HW_DATA_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_HW_DATA_FILTER),
@@ -1128,6 +1226,21 @@
WMI_TWT_DEL_DIALOG_CMDID,
WMI_TWT_PAUSE_DIALOG_CMDID,
WMI_TWT_RESUME_DIALOG_CMDID,
+ WMI_TWT_BTWT_INVITE_STA_CMDID,
+ WMI_TWT_BTWT_REMOVE_STA_CMDID,
+
+ /** WMI commands related to motion detection **/
+ WMI_MOTION_DET_CONFIG_PARAM_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_MOTION_DET),
+ WMI_MOTION_DET_BASE_LINE_CONFIG_PARAM_CMDID,
+ WMI_MOTION_DET_START_STOP_CMDID,
+ WMI_MOTION_DET_BASE_LINE_START_STOP_CMDID,
+
+ /** WMI commands related to OBSS PD Spatial Reuse **/
+ WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_SPATIAL_REUSE),
+ WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID,
+
+ /** WMI commands related to High Precision Clock Synchronization feature **/
+ WMI_HPCS_PULSE_START_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_HPCS_PULSE),
} WMI_CMD_ID;
typedef enum {
@@ -1141,6 +1254,11 @@
*/
WMI_SERVICE_AVAILABLE_EVENTID,
+ /** Specify what numbers and kinds of interfaces (a.k.a. vdevs)
+ * the target supports
+ */
+ WMI_IFACE_COMBINATION_IND_EVENTID,
+
/** Scan specific events */
WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN),
@@ -1219,6 +1337,22 @@
WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID,
+ /** WMI Event to deliver CTL Failsafe application */
+ WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID,
+
+ /* Event to report the switch count in BSS color of one or more VDEVs */
+ WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID,
+
+ /* Event to send cold boot calibration data */
+ WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID,
+
+ /* Event to report a rogue ap info that is detected in fw */
+ WMI_PDEV_RAP_INFO_EVENTID,
+
+ WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID,
+
+ /** 2nd extension of SERVICE_READY msg with extra target capability info */
+ WMI_SERVICE_READY_EXT2_EVENTID,
/* VDEV specific events */
/** VDEV started event in response to VDEV_START request */
@@ -1253,6 +1387,30 @@
/** get tx power event in response to VDEV_GET_TX_POWER request */
WMI_VDEV_GET_TX_POWER_EVENTID,
+ WMI_VDEV_BCN_RECEPTION_STATS_EVENTID,
+
+ /* provide LTE-Coex state */
+ WMI_VDEV_GET_MWS_COEX_STATE_EVENTID,
+
+ /* provide LTE-Coex Dynamic Power Back-off info */
+ WMI_VDEV_GET_MWS_COEX_DPWB_STATE_EVENTID,
+
+ /* provide LTE-Coex TDM info */
+ WMI_VDEV_GET_MWS_COEX_TDM_STATE_EVENTID,
+
+ /* provide LTE-Coex IDRx info */
+ WMI_VDEV_GET_MWS_COEX_IDRX_STATE_EVENTID,
+
+ /* provide LTE-Coex antenna sharing info */
+ WMI_VDEV_GET_MWS_COEX_ANTENNA_SHARING_STATE_EVENTID,
+
+ /* Event to handle FW offloaded mgmt packets */
+ WMI_VDEV_MGMT_OFFLOAD_EVENTID,
+
+ /* FW response to Host for delete all peer cmdid */
+ WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID,
+
+
/* peer specific events */
/** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */
WMI_PEER_STA_KICKOUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PEER),
@@ -1313,6 +1471,10 @@
/** Peer operating mode change indication sent to host to update stats */
WMI_PEER_OPER_MODE_CHANGE_EVENTID,
+ /** report the current tx PN for the peer */
+ WMI_PEER_TX_PN_RESPONSE_EVENTID,
+
+ WMI_PEER_CFR_CAPTURE_EVENTID,
/* beacon/mgmt specific events */
/** RX management frame. the entire frame is carried along with the event. */
@@ -1345,6 +1507,10 @@
/** software FILS Discovery Frame alert event to Host, requesting host to Queue an FD frame for transmission */
WMI_HOST_SWFDA_EVENTID,
+ /** software beacon alert event to Host requesting host to Queue a beacon for transmission.
+ * Used only in host beacon mode. */
+ WMI_HOST_SWBA_V2_EVENTID,
+
/* ADDBA Related WMI Events*/
/** Indication the completion of the prior
WMI_PEER_TID_DELBA_CMDID(initiator) */
@@ -1369,7 +1535,13 @@
/** roam synch frame event */
WMI_ROAM_SYNCH_FRAME_EVENTID,
/** various roam scan stats */
- WMI_ROAM_SCAN_STATS_EVENTID,
+ WMI_ROAM_SCAN_STATS_EVENTID,
+ /** Blacklisted AP information event */
+ WMI_ROAM_BLACKLIST_EVENTID,
+ /** Roam Pre-Authentication start event */
+ WMI_ROAM_PREAUTH_START_EVENTID,
+ /** Roaming PMKID request event */
+ WMI_ROAM_PMKID_REQUEST_EVENTID,
/** P2P disc found */
WMI_P2P_DISC_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_P2P),
@@ -1447,6 +1619,11 @@
* and report radio channel stats to host */
WMI_RADIO_CHAN_STATS_EVENTID,
+ /** This event is used to respond to WMI_REQUEST_WLM_STATS_CMDID
+ * and report WLM (WLAN latency manager) stats info to host */
+ WMI_WLM_STATS_EVENTID,
+
+
/* NLO specific events */
/** NLO match event after the first match */
WMI_NLO_MATCH_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_NLO_OFL),
@@ -1561,6 +1738,15 @@
/** event to report result of host configure SAR2 */
WMI_SAR2_RESULT_EVENTID,
+ /** event to get TX power per input HALPHY parameters */
+ WMI_GET_TPC_POWER_EVENTID,
+
+ /** event to provide MU-EDCA Parameters (to update host's beacon config) */
+ WMI_MUEDCA_PARAMS_CONFIG_EVENTID,
+
+ /** event to get ELNA BYPASS status */
+ WMI_GET_ELNA_BYPASS_EVENTID,
+
/* GPIO Event */
WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO),
/** upload H_CV info WMI event
@@ -1667,6 +1853,8 @@
WMI_TWT_DEL_DIALOG_COMPLETE_EVENTID,
WMI_TWT_PAUSE_DIALOG_COMPLETE_EVENTID,
WMI_TWT_RESUME_DIALOG_COMPLETE_EVENTID,
+ WMI_TWT_BTWT_INVITE_STA_COMPLETE_EVENTID,
+ WMI_TWT_BTWT_REMOVE_STA_COMPLETE_EVENTID,
/** Events in Prototyping phase */
WMI_NDI_CAP_RSP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_PROTOTYPE),
@@ -1678,6 +1866,14 @@
WMI_NDP_END_INDICATION_EVENTID,
WMI_WLAN_COEX_BT_ACTIVITY_EVENTID,
WMI_NDL_SCHEDULE_UPDATE_EVENTID,
+ WMI_NDP_EVENTID,
+
+ /** WMI events related to motion detection */
+ WMI_MOTION_DET_HOST_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MOTION_DET),
+ WMI_MOTION_DET_BASE_LINE_HOST_EVENTID,
+
+ /** WMI events related to Estimation of Service Parameters (802.11mc) */
+ WMI_ESP_ESTIMATE_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_ESP),
} WMI_EVT_ID;
/* defines for OEM message sub-types */
@@ -1711,7 +1907,7 @@
A_UINT32 info;
/** contains min power, max power, reg power and reg class id. */
A_UINT32 reg_info_1;
- /** contains antennamax */
+ /** contains antennamax, max bandwidth */
A_UINT32 reg_info_2;
} wmi_channel;
@@ -1785,6 +1981,12 @@
} while (0)
#define WMI_GET_CHANNEL_MAX_TX_POWER(pwmi_channel) ((((pwmi_channel)->reg_info_2)>>8) & 0xff)
+/* max bw supported for each channel, enum wmi_channel_width as value */
+#define WMI_SET_CHANNEL_MAX_BANDWIDTH(pwmi_channel,val) do { \
+ (pwmi_channel)->reg_info_2 &= 0xff00ffff; \
+ (pwmi_channel)->reg_info_2 |= ((val & 0xff) << 16); \
+ } while (0)
+#define WMI_GET_CHANNEL_MAX_BANDWIDTH(pwmi_channel) ((((pwmi_channel)->reg_info_2) >> 16) & 0xff)
/** HT Capabilities*/
#define WMI_HT_CAP_ENABLED 0x0001 /* HT Enabled/ disabled */
@@ -1887,6 +2089,13 @@
/* Interested readers refer to Rx/Tx MCS Map definition as defined in
802.11ac
*/
+#define WMI_VHT_MAX_MCS_EXT_SS_GET(vht_mcs_map, index) WMI_GET_BITS(vht_mcs_map, 16 + index, 1)
+#define WMI_VHT_MAX_MCS_EXT_SS_SET(vht_mcs_map, index, value) WMI_SET_BITS(vht_mcs_map, 16 + index, 1, value)
+
+/* Notification bit for Ext MCS 10/11 support */
+#define WMI_VHT_MCS_NOTIFY_EXT_SS_GET(vht_mcs_map) WMI_GET_BITS(vht_mcs_map, 24, 1)
+#define WMI_VHT_MCS_NOTIFY_EXT_SS_SET(vht_mcs_map, value) WMI_SET_BITS(vht_mcs_map, 24, 1, value)
+
#define WMI_VHT_MAX_MCS_4_SS_MASK(r,ss) ((3 & (r)) << (((ss) - 1) << 1))
#define WMI_VHT_MAX_SUPP_RATE_MASK 0x1fff0000
#define WMI_VHT_MAX_SUPP_RATE_MASK_SHIFT 16
@@ -1898,6 +2107,37 @@
#define WMI_HE_FRAG_SUPPORT_MASK 0x00000018
#define WMI_HE_FRAG_SUPPORT_SHIFT 3
+#define WMI_HE_CAP_1X_LTF_400NS_GI_SUPPORT 0x00000001
+#define WMI_HE_CAP_2X_LTF_400NS_GI_SUPPORT 0x00000002
+#define WMI_HE_CAP_2X_LTF_160_80_80_SUPPORT 0x00000004
+#define WMI_HE_CAP_RX_DL_OFDMA_SUPPORT 0x00000018
+#define WMI_HE_CAP_RX_DL_MUMIMO_SUPPORT 0x00000030
+
+#define WMI_HE_CAP_1X_LTF_400NS_GI_SUPPORT_GET(he_cap_info_dword1) \
+ WMI_GET_BITS(he_cap_info_dword1, 0, 1)
+#define WMI_HE_CAP_1X_LTF_400NS_GI_SUPPORT_SET(he_cap_info_dword1, value) \
+ WMI_SET_BITS(he_cap_info_dword1, 0, 1, value)
+
+#define WMI_HE_CAP_2X_LTF_400NS_GI_SUPPORT_GET(he_cap_info_dword1) \
+ WMI_GET_BITS(he_cap_info_dword1, 1, 1)
+#define WMI_HE_CAP_2X_LTF_400NS_GI_SUPPORT_SET(he_cap_info_dword1, value) \
+ WMI_SET_BITS(he_cap_info_dword1, 1, 1, value)
+
+#define WMI_HE_CAP_2X_LTF_160_80_80_SUPPORT_GET(he_cap_info_dword1) \
+ WMI_GET_BITS(he_cap_info_dword1, 2, 1)
+#define WMI_HE_CAP_2X_LTF_160_80_80_SUPPORT_SET(he_cap_info_dword1, value) \
+ WMI_SET_BITS(he_cap_info_dword1, 2, 1, value)
+
+#define WMI_HE_CAP_RX_DL_OFDMA_SUPPORT_GET(he_cap_info_dword1) \
+ WMI_GET_BITS(he_cap_info_dword1, 3, 2)
+#define WMI_HE_CAP_RX_DL_OFDMA_SUPPORT_SET(he_cap_info_dword1, value) \
+ WMI_SET_BITS(he_cap_info_dword1, 3, 2, value)
+
+#define WMI_HE_CAP_RX_DL_MUMIMO_SUPPORT_GET(he_cap_info_dword1) \
+ WMI_GET_BITS(he_cap_info_dword1, 5, 2)
+#define WMI_HE_CAP_RX_DL_MUMIMO_SUPPORT_SET(he_cap_info_dword1, value) \
+ WMI_SET_BITS(he_cap_info_dword1, 5, 2, value)
+
/* Interested readers refer to Rx/Tx MCS Map definition as defined in 802.11ax
*/
#define WMI_HE_MAX_MCS_4_SS_MASK(r,ss) ((3 & (r)) << (((ss) - 1) << 1))
@@ -1910,6 +2150,20 @@
WMI_HE_FRAG_SUPPORT_LEVEL3, /* support for multiple fragments per MSDU within an A-MPDU */
};
+enum {
+ WMI_HE_RX_DL_OFDMA_SUPPORT_DEFAULT, /* Default */
+ WMI_HE_RX_DL_OFDMA_SUPPORT_DISABLE, /* RX DL OFDMA Support Disabled */
+ WMI_HE_RX_DL_OFDMA_SUPPORT_ENABLE, /* RX DL OFDMA Support Enabled */
+ WMI_HE_RX_DL_OFDMA_SUPPORT_INVALID, /* INVALID */
+};
+
+enum {
+ WMI_HE_RX_DL_MUMIMO_SUPPORT_DEFAULT, /* Default */
+ WMI_HE_RX_DL_MUMIMO_SUPPORT_DISABLE, /* RX DL MU-MIMO Support Disabled */
+ WMI_HE_RX_DL_MUMIMO_SUPPORT_ENABLE, /* RX DL MU-MIMO Support Enabled */
+ WMI_HE_RX_DL_MUMIMO_SUPPORT_INVALID, /* INVALID */
+};
+
/** NOTE: This defs cannot be changed in the future without breaking WMI compatibility */
#define WMI_MAX_NUM_SS MAX_HE_NSS
#define WMI_MAX_NUM_RU MAX_HE_RU
@@ -2122,6 +2376,34 @@
#define WMI_PDEV_ID_2ND 2 /* second pdev (pdev 1) */
#define WMI_PDEV_ID_3RD 3 /* third pdev (pdev 2) */
+/*
+ * Enum regarding which BDF elements are provided in which elements of the
+ * wmi_service_ready_event_fixed_param.hw_bd_info[] array
+ */
+typedef enum {
+ BDF_VERSION = 0,
+ REF_DESIGN_ID = 1,
+ CUSTOMER_ID = 2,
+ PROJECT_ID = 3,
+ BOARD_DATA_REV = 4,
+} wmi_hw_bd_info_e;
+
+/*
+ * Macros to get/set BDF details within the
+ * wmi_service_ready_event_fixed_param.hw_bd_info[] array
+ */
+#define WMI_GET_BDF_VERSION(hw_bd_info) ((hw_bd_info)[BDF_VERSION])
+#define WMI_GET_REF_DESIGN(hw_bd_info) ((hw_bd_info)[REF_DESIGN_ID])
+#define WMI_GET_CUSTOMER_ID(hw_bd_info) ((hw_bd_info)[CUSTOMER_ID])
+#define WMI_GET_PROJECT_ID(hw_bd_info) ((hw_bd_info)[PROJECT_ID])
+#define WMI_GET_BOARD_DATA_REV(hw_bd_info) ((hw_bd_info)[BOARD_DATA_REV])
+
+#define WMI_SET_BDF_VERSION(hw_bd_info, val) ((hw_bd_info)[BDF_VERSION] = (val))
+#define WMI_SET_REF_DESIGN(hw_bd_info, val) ((hw_bd_info)[REF_DESIGN_ID] = (val))
+#define WMI_SET_CUSTOMER_ID(hw_bd_info, val) ((hw_bd_info)[CUSTOMER_ID] = (val))
+#define WMI_SET_PROJECT_ID(hw_bd_info, val) ((hw_bd_info)[PROJECT_ID] = (val))
+#define WMI_SET_BOARD_DATA_REV(hw_bd_info, val) ((hw_bd_info)[BOARD_DATA_REV] = (val))
+
/**
* The following struct holds optional payload for
* wmi_service_ready_event_fixed_param,e.g., 11ac pass some of the
@@ -2265,8 +2547,37 @@
* is equal to or less than the target capability limit reported here.
*/
A_UINT32 max_nlo_ssids;
+ /* ref to section 8.4.2.48 Multiple BSSID element
+ * The Max BSSID Indicator field contains a value assigned to n,
+ * where 2^n is the maximum number of BSSIDs
+ */
+ A_UINT32 max_bssid_indicator;
+
+ /* 2nd DWORD of HE MAC Capabilities */
+ A_UINT32 he_cap_info_ext;
+
+ /*
+ * A variable-length TLV array of wmi_chan_rf_characterization_info will
+ * follow this fixed_param TLV, containing rx characterization info for
+ * primary channels.
+ * WMI_CHAN_RF_CHARACTERIZATION_INFO wmi_chan_rf_characterization_info[];
+ */
} wmi_service_ready_ext_event_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_service_ready_ext2_event_fixed_param.*/
+} wmi_service_ready_ext2_event_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_chan_rf_characterization_info_event_fixed_param */
+ /*
+ * A variable-length TLV array of wmi_chan_rf_characterization_info will
+ * follow this fixed_param TLV, containing rx characterization info for
+ * primary channels.
+ * WMI_CHAN_RF_CHARACTERIZATION_INFO wmi_chan_rf_characterization_info[];
+ */
+} wmi_chan_rf_characterization_info_event_fixed_param;
+
typedef enum {
WMI_FW_STA_RTT_INITR = 0x00000001,
WMI_FW_STA_RTT_RESPR = 0x00000002,
@@ -2385,6 +2696,14 @@
* Peer ID can be up to num_total_peers + num_extra_peers.
*/
A_UINT32 num_extra_peers;
+ /*
+ * max_ast_index - max AST index that Firmware can generate
+ * max_ast_index = (ast_table_size-1), ast_table_size is dynamically chosen
+ * based on num_peers configutation from Host. Hence Host needs to know the
+ * max_ast_index that Firmware can generate.
+ * A 0x0 value for max_ast_index means the target has not specified a limit.
+ */
+ A_UINT32 max_ast_index;
/*
* This fixed_param TLV is followed by these additional TLVs:
@@ -2704,6 +3023,120 @@
#define WMI_RSRC_CFG_FLAG_TCL_CCE_DISABLE_S 12
#define WMI_RSRC_CFG_FLAG_TCL_CCE_DISABLE_M 0x1000
+ #define WMI_RSRC_CFG_FLAG_TIM_V2_SUPPORT_ENABLE_S 13
+ #define WMI_RSRC_CFG_FLAG_TIM_V2_SUPPORT_ENABLE_M 0x2000
+
+ #define WMI_RSRC_CFG_FLAG_EAPOL_REKEY_MINRATE_SUPPORT_ENABLE_S 14
+ #define WMI_RSRC_CFG_FLAG_EAPOL_REKEY_MINRATE_SUPPORT_ENABLE_M 0x4000
+
+ #define WMI_RSRC_CFG_FLAG_EAPOL_AC_OVERRIDE_VALID_S 15
+ #define WMI_RSRC_CFG_FLAG_EAPOL_AC_OVERRIDE_VALID_M 0x8000
+
+ /*
+ * If the AC override valid bit is set then this field will specify the
+ * access category to use for EAPOL frames
+ * 0 - WMM_AC_BE
+ * 1 - WMM_AC_BK
+ * 2 - WMM_AC_VI
+ * 3 - WMM_AC_VO
+ */
+ #define WMI_RSRC_CFG_FLAG_EAPOL_AC_OVERRIDE_S 16
+ #define WMI_RSRC_CFG_FLAG_EAPOL_AC_OVERRIDE_M 0x30000
+
+ /*
+ * If TX_ACK_RSSI is set, then the target should populate the ack_rssi
+ * field within the WMI_MGMT_TX_COMPLETION_EVENT message, the ack_rssi
+ * TLV within the WMI_MGMT_TX_BUNDLE_COMPLETION_EVENT message, and the
+ * "MSDU ACK RSSI" array within the HTT_T2H TX_COMPL_IND message.
+ */
+ #define WMI_RSRC_CFG_FLAG_TX_ACK_RSSI_S 18
+ #define WMI_RSRC_CFG_FLAG_TX_ACK_RSSI_M 0x40000
+
+ /*
+ * If HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN is set, the host will not
+ * include the HTC header length in the payload length for all HTT_H2T
+ * messages.
+ * Otherwise, only when sending HTT_H2T_MSG_TYPE_TX_FRM message,
+ * payload length includes HTC header length. Other HTT_H2T messages'
+ * payload length does not include HTC header length.
+ * The host will only set this HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN flag
+ * if the target has set the WMI_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN
+ * flag to indicate its support for this option.
+ */
+ #define WMI_RSRC_CFG_FLAG_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN_S 19
+ #define WMI_RSRC_CFG_FLAG_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN_M 0x80000
+
+ #define WMI_RSRC_CFG_FLAG_PEER_UNMAP_RESPONSE_SUPPORT_S 20
+ #define WMI_RSRC_CFG_FLAG_PEER_UNMAP_RESPONSE_SUPPORT_M 0x100000
+
+ /*
+ * If this HTT_PEER_STATS is set, then the target should use the
+ * the HTT_T2H_MSG_TYPE_PEER_STATS_IND message to upload peer stats;
+ * else the target should avoid sending the PEER_STATS_IND message.
+ */
+ #define WMI_RSRC_CFG_FLAG_HTT_PEER_STATS_S 21
+ #define WMI_RSRC_CFG_FLAG_HTT_PEER_STATS_M 0x200000
+
+ /*
+ * If this BIT is set, then the target should use peer_tid_ext to analyze
+ * per peer per tid extended configurations
+ */
+ #define WMI_RSRC_CFG_FLAG_PEER_TID_EXT_S 22
+ #define WMI_RSRC_CFG_FLAG_PEER_TID_EXT_M 0x400000
+
+ /*
+ * If the VIDEO_OVER_WIFI_ENABLE flag is set, the target will use a
+ * series of algorithmic adjustments to optimize Video performance
+ * by reducing latency, reducing latency jitter, and minimizing
+ * dropped packets.
+ */
+ #define WMI_RSRC_CFG_FLAG_VIDEO_OVER_WIFI_ENABLE_S 23
+ #define WMI_RSRC_CFG_FLAG_VIDEO_OVER_WIFI_ENABLE_M 0x800000
+
+ /*
+ * If the THREE_WAY_COEX_CONFIG_LEGACY flag is set, the target will use
+ * the configuration parameters given by Host driver to WLAN FW and
+ * apply them along with the existing CoEx Weights Override logic to
+ * prioritize the WLAN-BT-Zigbee packets accordingly.
+ *
+ * The host shall only set the THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT
+ * RSRC_CFG flag if the target has set the WMI_SERVICE
+ * THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT flag.
+ *
+ * The logic to send GPM to BT-SOC with BT-ZB priorities remains the same.
+ */
+ #define WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT_S 24
+ #define WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT_M 0x1000000
+
+ /*
+ * If the THREE_WAY_COEX_CONFIG_OVERRIDE flag is set, the target will use
+ * the configuration parameters given by Host driver to WLAN FW and
+ * apply them by OVERRIDing the existing CoEx Weights Override logic to
+ * prioritize the WLAN-BT-Zigbee packets accordingly.
+ *
+ * The host shall only set the THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT
+ * RSRC_CFG flag if the target has set the WMI_SERVICE
+ * THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT flag.
+ *
+ * The logic to send GPM to BT-SOC with BT-ZB priorities remains the same.
+ */
+ #define WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT_S 25
+ #define WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT_M 0x2000000
+
+ /*
+ * If the TX_COMPLETION_TX_TSF64 flag is set, the target should
+ * populate the htt_tx_compl_ind_append_tx_tsf64 array within the
+ * HTT_T2H TX_COMPL_IND message.
+ */
+ #define WMI_RSRC_CFG_FLAG_TX_COMPLETION_TX_TSF64_ENABLE_S 26
+ #define WMI_RSRC_CFG_FLAG_TX_COMPLETION_TX_TSF64_ENABLE_M 0x4000000
+
+ /*
+ * If this BIT is set, then the target should support Packet capture(SMART MU FR)
+ */
+ #define WMI_RSRC_CFG_FLAG_PACKET_CAPTURE_SUPPORT_S 27
+ #define WMI_RSRC_CFG_FLAG_PACKET_CAPTURE_SUPPORT_M 0x8000000
+
A_UINT32 flag1;
/** @brief smart_ant_cap - Smart Antenna capabilities information
@@ -2824,8 +3257,92 @@
* 0 - fw chooses its default value: 'num_vdevs' of this structure.
*/
A_UINT32 num_max_sta_vdevs;
+
+ /* ref to section 8.4.2.48 Multiple BSSID element
+ * The Max BSSID Indicator field contains a value assigned to n,
+ * where 2^n is the maximum number of BSSIDs
+ */
+ A_UINT32 max_bssid_indicator;
+
+ /** @brief ul_resp_config - Configures the 11ax uplink ofdma feature on STA.
+ * I.e. sending uplink response to a trigger frame sent by AP.
+ * @details
+ * 0 - fw default behavior, based on chipset
+ * 1 - UL_RESP is disabled.
+ * 2 - UL_RESP is enabled.
+ * other - reserved.
+ */
+ A_UINT32 ul_resp_config;
+
+ /* msdu_flow_override_config0 - contains AST enable bitmask
+ * AST0 is unconditionally enabled, unless the MSDU flow override feature
+ * is entirely disabled.
+ * AST1 through AST3 are conditionally enabled, based on bits 0-2 in
+ * msdu_flow_override_config0.
+ * If all three bits are 0, no msdu flow override feature at all in FW.
+ *
+ * The WMI_MSDU_FLOW_AST_ENABLE_GET and WMI_MSDU_FLOW_AST_ENABLE_SET
+ * macros are used to read and write these bitfields.
+ */
+ A_UINT32 msdu_flow_override_config0;
+
+ /* msdu_flow_override_config1:
+ * Bits 3:0 - AST0_FLOW_MASK(4)
+ * Bits 7:4 - AST1_FLOW_MASK(4)
+ * Bits 11:8 - AST2_FLOW_MASK(4)
+ * Bits 15:12 - AST3_FLOW_MASK(4)
+ * Bits 23:16 - TID_VALID_HI_PRI (8)
+ * Bits 31:24 - TID_VALID_LOW_PRI (8)
+ *
+ * The macros
+ * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_GET
+ * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_SET
+ * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_GET
+ * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_SET
+ * WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_GET
+ * WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_SET
+ * are used to read and write these bitfields.
+ */
+ A_UINT32 msdu_flow_override_config1;
} wmi_resource_config;
+#define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \
+ (((ast_x) == 0) ? 1 : ((msdu_flow_config0) & (1 << ((ast_x) - 1))))
+#define WMI_MSDU_FLOW_AST_ENABLE_SET(msdu_flow_config0, ast_x, enable) \
+ do { \
+ if ((ast_x) == 0) break; \
+ if ((enable)) { \
+ (msdu_flow_config0) |= (1 << ((ast_x) - 1)); \
+ } else { \
+ (msdu_flow_config0) &= ~(1 << ((ast_x) - 1)); \
+ } \
+ } while(0)
+
+#define WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_GET(msdu_flow_config1, ast_x) \
+ (((msdu_flow_config1) & (0x0f << ((ast_x) * 4))) >> ((ast_x) * 4))
+#define WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_SET( \
+ msdu_flow_config1, ast_x, mask) \
+ do { \
+ (msdu_flow_config1) &= ~(0xF << ((ast_x) * 4)); \
+ (msdu_flow_config1) |= ((mask) << ((ast_x) * 4)); \
+ } while(0)
+
+#define WMI_MSDU_FLOW_TID_VALID_HI_MASKS_GET(msdu_flow_config1) \
+ (((msdu_flow_config1) & 0xff0000) >> 16)
+#define WMI_MSDU_FLOW_TID_VALID_HI_MASKS_SET(msdu_flow_config1, mask) \
+ do { \
+ (msdu_flow_config1) &= ~0xff0000; \
+ (msdu_flow_config1) |= ((mask) << 16); \
+ } while(0)
+
+#define WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_GET(msdu_flow_config1) \
+ ((msdu_flow_config1 & 0xff000000) >> 24)
+#define WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_SET(msdu_flow_config1, mask) \
+ do { \
+ (msdu_flow_config1) &= ~0xff000000; \
+ (msdu_flow_config1) |= ((mask) << 24); \
+ } while(0)
+
#define WMI_RSRC_CFG_FLAG_SET(word32, flag, value) \
do { \
(word32) &= ~WMI_RSRC_CFG_FLAG_ ## flag ## _M; \
@@ -2896,6 +3413,76 @@
#define WMI_RSRC_CFG_FLAG_TCL_CCE_DISABLE_GET(word32) \
WMI_RSRC_CFG_FLAG_GET((word32), TCL_CCE_DISABLE)
+#define WMI_RSRC_CFG_FLAG_TIM_V2_SUPPORT_ENABLE_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), TIM_V2_SUPPORT_ENABLE, (value))
+#define WMI_RSRC_CFG_FLAG_TIM_V2_SUPPORT_ENABLE_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), TIM_V2_SUPPORT_ENABLE)
+
+#define WMI_RSRC_CFG_FLAG_EAPOL_REKEY_MINRATE_SUPPORT_ENABLE_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), EAPOL_REKEY_MINRATE_SUPPORT_ENABLE, (value))
+#define WMI_RSRC_CFG_FLAG_EAPOL_REKEY_MINRATE_SUPPORT_ENABLE_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), EAPOL_REKEY_MINRATE_SUPPORT_ENABLE)
+
+#define WMI_RSRC_CFG_FLAG_EAPOL_AC_OVERRIDE_VALID_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), EAPOL_AC_OVERRIDE_VALID, (value))
+#define WMI_RSRC_CFG_FLAG_EAPOL_AC_OVERRIDE_VALID_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), EAPOL_AC_OVERRIDE_VALID)
+
+#define WMI_RSRC_CFG_FLAG_EAPOL_AC_OVERRIDE_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), EAPOL_AC_OVERRIDE, (value))
+#define WMI_RSRC_CFG_FLAG_EAPOL_AC_OVERRIDE_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), EAPOL_AC_OVERRIDE)
+
+#define WMI_RSRC_CFG_FLAG_TX_ACK_RSSI_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), TX_ACK_RSSI, (value))
+#define WMI_RSRC_CFG_FLAG_TX_ACK_RSSI_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), TX_ACK_RSSI)
+
+#define WMI_RSRC_CFG_FLAG_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN, (value))
+#define WMI_RSRC_CFG_FLAG_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN)
+
+#define WMI_RSRC_CFG_FLAG_PEER_UNMAP_RESPONSE_SUPPORT_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), PEER_UNMAP_RESPONSE_SUPPORT, (value))
+#define WMI_RSRC_CFG_FLAG_PEER_UNMAP_RESPONSE_SUPPORT_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), PEER_UNMAP_RESPONSE_SUPPORT)
+
+#define WMI_RSRC_CFG_FLAG_HTT_PEER_STATS_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), HTT_PEER_STATS, (value))
+#define WMI_RSRC_CFG_FLAG_HTT_PEER_STATS_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), HTT_PEER_STATS)
+
+#define WMI_RSRC_CFG_FLAG_PEER_TID_EXT_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), PEER_TID_EXT, (value))
+#define WMI_RSRC_CFG_FLAG_PEER_TID_EXT_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), PEER_TID_EXT)
+
+#define WMI_RSRC_CFG_FLAG_VIDEO_OVER_WIFI_ENABLE_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), VIDEO_OVER_WIFI_ENABLE, (value))
+#define WMI_RSRC_CFG_FLAG_VIDEO_OVER_WIFI_ENABLE_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), VIDEO_OVER_WIFI_ENABLE)
+
+#define WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT, (value))
+#define WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT)
+
+#define WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT, (value))
+#define WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), THREE_WAY_COEX_CONFIG_OVERRIDE_SUPPORT)
+
+#define WMI_RSRC_CFG_FLAG_TX_COMPLETION_TX_TSF64_ENABLE_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), TX_COMPLETION_TX_TSF64_ENABLE, (value))
+#define WMI_RSRC_CFG_FLAG_TX_COMPLETION_TX_TSF64_ENABLE_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), TX_COMPLETION_TX_TSF64_ENABLE)
+
+#define WMI_RSRC_CFG_FLAG_PACKET_CAPTURE_SUPPORT_SET(word32, value) \
+ WMI_RSRC_CFG_FLAG_SET((word32), PACKET_CAPTURE_SUPPORT, (value))
+#define WMI_RSRC_CFG_FLAG_PACKET_CAPTURE_SUPPORT_GET(word32) \
+ WMI_RSRC_CFG_FLAG_GET((word32), PACKET_CAPTURE_SUPPORT)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param */
@@ -2968,6 +3555,43 @@
*/
} wmi_tlv_buf_len_param;
+/**
+ * TLV used for specifying the demensions of a multi-dimensional array
+ * that has been stored in a flat buffer
+ */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tlv_arrays_len_param */
+ /**
+ * d1_len, d2_len, d3_len, and d4_len are the lengths of each dimension
+ * for a multi-dimensional array.
+ * If the length of outer dimension is not 1, the inner dimension
+ * shouldn't be 1.
+ * If the multi-dimensional array has less than 4 dimensions, the outer
+ * dimensions' lengths should be 1. For example, a buf[3][4] array
+ * would have d1_len = 4, d2_len = 3, d3_len = 1, d4_len = 1.
+ * The outermost dimension of the array can be inferred from the array
+ * length; thus, this struct supports up to 5-D arrays. For a 5-D array,
+ * the outermost (5th) dimension would be
+ * array length / (d1_len * d2_len * d3_len * d4_len)
+ *
+ * For security (to ensure no out-of-bounds memory access),
+ * the receiver shall validate that the product of all dimensions
+ * is equal to (or less than) the array length.
+ */
+ A_UINT32 d1_len; /* the length of 1st (innermost) dimension array */
+ A_UINT32 d2_len; /* the length of 2nd dimension array */
+ A_UINT32 d3_len; /* the length of 3rd dimension array */
+ A_UINT32 d4_len; /* the length of 4th dimension array */
+ /**
+ * Following this structure is the TLV multi-dimension array buffer:
+ * <type> buf[L1*L2*L3*L4];
+ * where, L1, L2, L3, and L4 are the values of
+ * d1_len, d2_len, d3_len and d4_len.
+ * To access the 4-D element a[i][j][k][l], the buf[] array would be
+ * indexed as buf[i*L3*L2*L1 + j*L2*L1 + k*L1 + l].
+ */
+} wmi_tlv_arrays_len_param;
+
typedef struct {
/** Len of the SSID */
A_UINT32 ssid_len;
@@ -3088,11 +3712,13 @@
A_UINT32 num_vendor_oui;
/** Scan control flags extended **/
A_UINT32 scan_ctrl_flags_ext;
+ /** dwell time in msec on active 2G channels, if it's not zero */
+ A_UINT32 dwell_time_active_2g;
/**
* TLV (tag length value) parameters follow the scan_cmd
* structure. The TLV's are:
- * A_UINT32 channel_list[num_chan];
+ * A_UINT32 channel_list[num_chan]; // in MHz
* wmi_ssid ssid_list[num_ssids];
* wmi_mac_addr bssid_list[num_bssid];
* A_UINT8 ie_data[ie_len];
@@ -3229,6 +3855,7 @@
#define MAX_NUM_CHAN_PER_WMI_CMD 58 /* each WMI cmd can hold 58 channel entries at most */
#define APPEND_TO_EXISTING_CHAN_LIST 1
+#define CHANNEL_MAX_BANDWIDTH_VALID 2
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_scan_chan_list_cmd_fixed_param */
@@ -3360,6 +3987,7 @@
WMI_SCAN_REASON_TIMEDOUT = 3,
WMI_SCAN_REASON_INTERNAL_FAILURE = 4, /* This reason indication failures when performaing scan */
WMI_SCAN_REASON_SUSPENDED = 5,
+ WMI_SCAN_REASON_DFS_VIOLATION = 6, /* Failure when tried to SCAN channel in NOL list */
WMI_SCAN_REASON_MAX,
};
@@ -3569,7 +4197,7 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_rx_hdr */
- /** channel on which this frame is received. */
+ /** channel on which this frame is received (channel number) */
A_UINT32 channel;
/** snr information used to cal rssi */
A_UINT32 snr;
@@ -3580,7 +4208,7 @@
/** length of the frame */
A_UINT32 buf_len;
/** rx status */
- A_UINT32 status;
+ A_UINT32 status; /* capture mode indication */
/** RSSI of PRI 20MHz for each chain. */
A_UINT32 rssi_ctl[ATH_MAX_ANTENNA];
/** information about the management frame e.g. can give a scan source for a scan result mgmt frame */
@@ -3612,6 +4240,9 @@
*/
A_UINT32 pdev_id;
+ /** freq in MHz of the channel on which this frame was received */
+ A_UINT32 chan_freq;
+
/* This TLV is followed by array of bytes:
* A_UINT8 bufp[]; <-- management frame buffer
*/
@@ -3620,6 +4251,83 @@
*/
} wmi_mgmt_rx_hdr;
+typedef enum {
+ PKT_CAPTURE_MODE_DISABLE = 0,
+ PKT_CAPTURE_MODE_MGMT_ONLY,
+ PKT_CAPTURE_MODE_DATA_ONLY,
+ PKT_CAPTURE_MODE_DATA_MGMT,
+} WMI_PKT_CAPTURE_MODE_CONFIG;
+
+/* This information sending to host during offloaded MGMT local TX and host TX */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mgmt_hdr */
+ /* channel frequency in MHz */
+ A_UINT32 chan_freq;
+ /** snr information used to cal rssi in dB */
+ A_UINT32 snr;
+ /** Rate kbps */
+ A_UINT32 rate_kbps;
+ /** phy mode WLAN_PHY_MODE */
+ A_UINT32 phy_mode;
+ /** length of the frame in bytes */
+ A_UINT32 buf_len;
+ /** status:
+ * 0x00: CRC ERR
+ * 0x08: DECRYPT ERR
+ * 0x10: MIC ERR
+ * 0x20: KEY CACHE MISS
+ */
+ A_UINT32 status;
+ /** flags:
+ * Information about the management frame e.g. can give a scan source
+ * for a scan result mgmt frame
+ * Refer to WMI_MGMT_RX_HDR_ definitions.
+ * ex: WMI_MGMT_RX_HDR_EXTSCAN,WMI_MGMT_RX_HDR_ENLO
+ */
+ A_UINT32 flags;
+ /** combined RSSI, i.e. the sum of the snr + noise floor (dBm units) */
+ A_INT32 rssi;
+ /** delta between local TSF (TSF timestamp when frame was RXd)
+ * and remote TSF (TSF timestamp in the IE for mgmt frame -
+ * beacon, proberesp for example). If remote TSF is not available,
+ * delta is set to 0.
+ * Although tsf_delta is stored as A_UINT32, it can be negative,
+ * and thus would need to be sign-extended if added to a value
+ * larger than 32 bits.
+ */
+ A_UINT32 tsf_delta;
+
+ /* The lower 32 bits of the TSF (tsf_l32) is copied by FW from
+ * TSF timestamp in the TX MAC descriptor provided by HW.
+ */
+ A_UINT32 tsf_l32;
+
+ /* The upper 32 bits of the TSF (tsf_u32) is copied by FW from
+ * TSF timestamp in the TX MAC descriptor provided by HW.
+ */
+ A_UINT32 tsf_u32;
+
+ /** pdev_id for identifying the MAC the tx mgmt frame transmitted.
+ * See macros starting with WMI_PDEV_ID_ for values.
+ */
+ A_UINT32 pdev_id;
+
+ A_UINT32 direction; /* tx:0,rx:1*/
+
+ /** tx_status:
+ * 0: xmit ok
+ * 1: excessive retries
+ * 2: blocked by tx filtering
+ * 4: fifo underrun
+ * 8: swabort
+ */
+ A_UINT32 tx_status;
+
+/* This TLV may be followed by array of bytes:
+ * A_UINT8 bufp[]; <-- management frame buffer
+ */
+} wmi_mgmt_hdr;
+
/*
* Instead of universally increasing the RX_HDR_HEADROOM size which may cause problems for older targets,
* this new ext_hdr can be used for extending the header and will be only applicable for new targets.
@@ -3841,6 +4549,9 @@
((int8_t) (WMI_F_MS((hdr)->rssi_chain##c, \
WMI_UNIFIED_RSSI_CHAN_##ch)))
+#define WMI_UNIFIED_CHAIN_RSSI_GET(tlv, chain_idx, band) \
+ ((A_INT8) WMI_F_MS((tlv)->chain_rssi[chain_idx], WMI_UNIFIED_RSSI_CHAN_ ## band))
+
typedef struct {
/** Phy error event header */
wmi_single_phyerr_rx_hdr hdr;
@@ -3935,6 +4646,9 @@
#define WMI_TX_SEND_PARAM_FRAME_TYPE_GET(tx_param_dword1) WMI_GET_BITS(tx_param_dword1, 20, 1)
#define WMI_TX_SEND_PARAM_FRAME_TYPE_SET(tx_param_dword1, value) WMI_SET_BITS(tx_param_dword1, 20, 1, value)
+#define WMI_TX_SEND_PARAM_CFR_CAPTURE_GET(tx_param_dword1) WMI_GET_BITS(tx_param_dword1, 21, 1)
+#define WMI_TX_SEND_PARAM_CFR_CAPTURE_SET(tx_param_dword1, value) WMI_SET_BITS(tx_param_dword1, 21, 1, value)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_send_params */
@@ -4035,7 +4749,7 @@
/* chain_mask - specify which chains to transmit from
* If not set, target will choose what chain_mask to use.
*/
- chain_mask: 8,
+ chain_mask: 8,
/* The bits in this mask correspond to the values as below
* bit 0 -> 5MHz
@@ -4047,7 +4761,7 @@
* bit 6 -> 80_80MHz
* If no bits are set, target can choose what BW to use.
*/
- bw_mask: 7,
+ bw_mask: 7,
/* preamble_type_mask -
* Specify which preamble types (CCK, OFDM, HT, VHT) the target
@@ -4060,15 +4774,19 @@
* bit 4: if set, HE
* If no bits are set, target can choose what preamble type to use.
*/
- preamble_type: 5,
+ preamble_type: 5,
/* Data:1 Mgmt:0
*/
- frame_type: 1,
+ frame_type: 1,
- reserved1_31_21: 11;
- };
- A_UINT32 tx_param_dword1;
+ /* Capture CFR when bit is set
+ */
+ cfr_capture: 1,
+
+ reserved1_31_22: 10;
+ };
+ A_UINT32 tx_param_dword1;
};
} wmi_tx_send_params;
@@ -4077,6 +4795,14 @@
A_UINT32 vdev_id;
A_UINT32 desc_id; /* echoed in tx_compl_event */
A_UINT32 chanfreq; /* MHz units */
+ /* WMI_MGMT_TX_SEND_CMDID is used for both pass by value and
+ * pass by reference WMI management frames.
+ *
+ * a) If the command is for pass by reference,
+ * paddr_lo and padd_hi will hold the address of remote/host buffer
+ * b) If the command is for pass by value,
+ * paddr_lo and paddr_hi will be NULL.
+ */
A_UINT32 paddr_lo;
A_UINT32 paddr_hi;
A_UINT32 frame_len;
@@ -4224,6 +4950,33 @@
A_UINT32 enabled; /* enable/disable */
} wmi_vdev_set_quiet_cmd_fixed_param;
+/*
+ * START_STOP flag value: 1 - Start, 0 - Stop
+ */
+#define WMI_OFFLOAD_QUIET_FLAG_START_STOP 0x00000001
+/*
+ * ONE_SHOT flag value: 1 - One shot, 0 - Repeat
+ * This flag is only relevant if the START_STOP flag == 1 (start).
+ */
+#define WMI_OFFLOAD_QUIET_FLAG_ONE_SHOT 0x00000002
+/*
+ * Enable/Disable sending Quiet IE info in SWBA event from the target
+ * 0 - Don't include Quiet IE in WMI SWBA Event
+ * 1 - Include Quiet IE in WMI SWBA Event
+ */
+#define WMI_OFFLOAD_QUIET_FLAG_INFO_IN_SWBA_START_STOP 0x00000004
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_bcn_offload_quiet_config_cmd_fixed_param */
+ A_UINT32 vdev_id; /* Virtual interface ID */
+ A_UINT32 period; /* period in TUs */
+ A_UINT32 duration; /* duration in TUs */
+ A_UINT32 next_start; /* offset in TUs from beacon */
+ A_UINT32 flags; /* STOP or START (and single vs. repeated) Quiet IE
+ * See WMI_OFFLOAD_QUIET_FLAG_xxx defs.
+ */
+} wmi_vdev_bcn_offload_quiet_config_cmd_fixed_param;
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_custom_aggr_size_cmd_fixed_param */
A_UINT32 vdev_id; /* vdev id indicating to which the vdev custom aggregation size will be applied. */
@@ -4301,6 +5054,57 @@
WMI_GET_BITS(param, WMI_VDEV_CUSTOM_TX_AC_EN_BITPOS, \
WMI_VDEV_CUSTOM_TX_AC_EN_NUM_BITS)
+typedef enum {
+ WMI_VDEV_CUSTOM_SW_RETRY_TYPE_NONAGGR = 0,
+ WMI_VDEV_CUSTOM_SW_RETRY_TYPE_AGGR = 1,
+ WMI_VDEV_CUSTOM_SW_RETRY_TYPE_MAX,
+} wmi_vdev_custom_sw_retry_type_t;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_custom_sw_retry_th_cmd_fixed_param */
+ A_UINT32 vdev_id; /* vdev id indicating to which the vdev custom software retries will be applied. */
+ A_UINT32 ac_type; /* access category (VI, VO, BE, BK) enum wmi_traffic_ac */
+ A_UINT32 sw_retry_type; /* 0 = non-aggr retry, 1 = aggr retry (wmi_vdev_custom_sw_retry_type_t enum) */
+ A_UINT32 sw_retry_th; /* max retry count per AC base on ac_type for the vdev mentioned in vdev id*/
+} wmi_vdev_set_custom_sw_retry_th_cmd_fixed_param;
+
+typedef struct {
+ /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_chainmask_config_cmd_fixed_param */
+ A_UINT32 tlv_header;
+ /* vdev id indicating to which the vdev, this chainmask configuration will be applied. */
+ A_UINT32 vdev_id;
+ /* number of chains to use for transmissions in 2.4 GHz band */
+ A_UINT32 num_tx_chains_2g;
+ /* number of chains to use for reception in 2.4 GHz band */
+ A_UINT32 num_rx_chains_2g;
+ /* nss to use for transmissions in 2.4 GHz band */
+ A_UINT32 tx_nss_2g;
+ /* nss to use for reception in 2.4 GHz band */
+ A_UINT32 rx_nss_2g;
+ /* number of chains to use for 11b transmissions. Valid only in 2.4 GHz */
+ A_UINT32 num_tx_chains_b;
+ /* number of chains to use for 11g transmissions. Valid only in 2.4 GHz */
+ A_UINT32 num_tx_chains_g;
+ /* number of chains to use for transmissions in 5 GHz band */
+ A_UINT32 num_tx_chains_5g;
+ /* number of chains to use for reception in 5 GHz band */
+ A_UINT32 num_rx_chains_5g;
+ /* nss to use for transmissions in 5 GHz band */
+ A_UINT32 tx_nss_5g;
+ /* nss to use for reception in 5 GHz band */
+ A_UINT32 rx_nss_5g;
+ /* number of chains to use for 11a transmissions. Valid only in 5 GHz */
+ A_UINT32 num_tx_chains_a;
+ /* If non-zero then use only one chain for TX when connection tx_nss is 1 in 2.4 GHz */
+ A_UINT32 disable_tx_mrc_2g;
+ /* If non-zero then use only one chain for RX when connection rx_nss is 1 in 2.4 GHz */
+ A_UINT32 disable_rx_mrc_2g;
+ /* If non-zero then use only one chain for TX when connection tx_nss is 1 in 5 GHz */
+ A_UINT32 disable_tx_mrc_5g;
+ /* If non-zero then use only one chain for RX when connection rx_nss is 1 in 5 GHz */
+ A_UINT32 disable_rx_mrc_5g;
+} wmi_vdev_chainmask_config_cmd_fixed_param;
+
/*
* Command to enable/disable Green AP Power Save.
* This helps conserve power during AP operation. When the AP has no
@@ -4403,6 +5207,8 @@
#define WMI_BEACON_CTRL_TX_DISABLE 0
#define WMI_BEACON_CTRL_TX_ENABLE 1
+#define WMI_BEACON_CTRL_SWBA_EVENT_DISABLE 2
+#define WMI_BEACON_CTRL_SWBA_EVENT_ENABLE 3
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bcn_offload_ctrl_cmd_fixed_param */
@@ -4498,6 +5304,27 @@
PKT_PWR_SAVE_FSM_ENABLE = 0x80000000,
} WMI_PDEV_PKT_PWR_SAVE_LEVEL;
+/** MACROs to get user setting for enabling/disabling Secondary Rate Feature set
+ * Bit-0 : Enable/Disable Control for "PPDU Secondary Retry Support"
+ * Bit-1 : Enable/Disable Control for "RTS Black/White-listing Support"
+ * Bit-2 : Enable/Disable Control for "Higher MCS retry restriction on XRETRY failures"
+ * Bit 3-5 : "Xretry threshold" to use
+ * Bit 6~31 : reserved for future use.
+ */
+#define WMI_PDEV_PARAM_SECONDARY_RATE_ENABLE_BIT_S 0
+#define WMI_PDEV_PARAM_SECONDARY_RATE_ENABLE_BIT 0x00000001
+#define WMI_PDEV_PARAM_RTS_BL_WL_ENABLE_BIT_S 1
+#define WMI_PDEV_PARAM_RTS_BL_WL_ENABLE_BIT 0x00000002
+#define WMI_PDEV_PARAM_HIGHER_MCS_XRETRY_RESTRICTION_S 2
+#define WMI_PDEV_PARAM_HIGHER_MCS_XRETRY_RESTRICTION 0x00000004
+#define WMI_PDEV_PARAM_XRETRY_THRESHOLD_S 3
+#define WMI_PDEV_PARAM_XRETRY_THRESHOLD 0x00000038
+
+#define WMI_PDEV_PARAM_IS_SECONDARY_RATE_ENABLED(word32) WMI_F_MS(word32, WMI_PDEV_PARAM_SECONDARY_RATE_ENABLE_BIT)
+#define WMI_PDEV_PARAM_IS_RTS_BL_WL_ENABLED(word32) WMI_F_MS(word32, WMI_PDEV_PARAM_RTS_BL_WL_ENABLE_BIT)
+#define WMI_PDEV_PARAM_IS_HIGHER_MCS_XRETRY_RESTRICTION_SET(word32) WMI_F_MS(word32, WMI_PDEV_PARAM_HIGHER_MCS_XRETRY_RESTRICTION)
+#define WMI_PDEV_PARAM_GET_XRETRY_THRESHOLD(word32) WMI_F_MS(word32, WMI_PDEV_PARAM_XRETRY_THRESHOLD)
+
typedef enum {
/** TX chain mask */
WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1,
@@ -4941,8 +5768,324 @@
* rate will be used instead.
*/
WMI_PDEV_PARAM_CCK_TX_ENABLE, /* 0x9e */
+ /*
+ * Set the user-specified antenna gain, but in 0.5 dB units.
+ * This is a finer-granularity version of WMI_PDEV_PARAM_ANTENNA_GAIN.
+ * E.g. to set a gain of 15.5 dB, a value of 31 could be provided as the
+ * value accompanying the PDEV_PARAM_ANTENNA_GAIN_HALF_DB parameter type.
+ */
+ WMI_PDEV_PARAM_ANTENNA_GAIN_HALF_DB, /* 0x9f */
+ /*
+ * Global Enable/Disable control for Secondary Retry Feature Set
+ *
+ * Bit-0 : Enable/Disable Control for "PPDU Secondary Retry Support"
+ * Bit-1 : Enable/Disable Control for "RTS Black/White-listing Support"
+ * Bit-2 : Enable/Disable Control for "Higher MCS retry restriction on XRETRY failures"
+ * Bit 3-5: "Xretry threshold" to use
+ */
+ WMI_PDEV_PARAM_SECONDARY_RETRY_ENABLE, /* 0xA0 */
+ /** Set global uplink triggered PPDU duration limit (usec). */
+ WMI_PDEV_PARAM_SET_UL_PPDU_DURATION, /* 0xA1 */
+ /** Set target buffer status report trigger interval (ms) */
+ WMI_PDEV_PARAM_SET_UL_BSR_TRIG_INTERVAL, /* 0xA2 */
+ /** Use simplified equal RU allocation for DL and UL OFDMA */
+ WMI_PDEV_PARAM_EQUAL_RU_ALLOCATION_ENABLE, /* 0xA3 */
+ /** Enable/disable MWS-COEX 4G (LTE) Quick FTDM.
+ * 0 - Don't allow quick FTDM Policy (Default)
+ * 1 - Allow quick FTDM policy.
+ */
+ WMI_PDEV_PARAM_MWSCOEX_4G_ALLOW_QUICK_FTDM, /* 0xA4 */
+ /** Set MWS-COEX 5G-NR power limit.
+ * 0: Don't apply user specific power limit,
+ * use internal power limit (Default)
+ * 1-2: invalid value (ignored)
+ * 3-21: apply the specified value as the external power limit, in dBm
+ * >21: invalid value (ignored)
+ */
+ WMI_PDEV_PARAM_MWSCOEX_SET_5GNR_PWR_LIMIT, /* 0xA5 */
+ /** Set max msdus available for cong ctrl in target */
+ WMI_PDEV_PARAM_SET_CONG_CTRL_MAX_MSDUS, /* 0xA6 */
+ /*
+ * Configures the Estimated Throughput Calculation indication (802.11mc) settings.
+ * The accompanying A_UINT32 parameter, in units of seconds, specifies how often FW needs to send the ESP estimation indication to the host.
+ * Value 0: Disable this feature
+ * Non zero Value: Periodicity (seconds)
+ */
+ WMI_PDEV_PARAM_ESP_INDICATION_PERIOD, /* 0xA7 */
+
+ /*
+ * Enable/Disable periodic peer CFR capture
+ * WMI_PEER_CFR_CAPTURE_ENABLE - Enable per peer periodic CFR capture
+ * WMI_PEER_CFR_CAPTURE_DISABLE - Disable per peer periodic CFR capture
+ */
+ WMI_PDEV_PARAM_PER_PEER_PERIODIC_CFR_ENABLE,
+
+ /*
+ * Set the base timer for the periodic CFR capture. By default this is 10ms.
+ * The period ('periodicity' param in wmi_peer_cfr_capture_cmd) of
+ * CFR measurment of other peers will be in multiples of this base timer.
+ * The unit is in milliseconds.
+ */
+ WMI_PDEV_PARAM_PERIODIC_CFR_BASE_TIMER,
+
+ /*
+ * Once the periodic capture is enabled using
+ * WMI_PDEV_PARAM_PER_PEER_PERIODIC_CFR_ENABLE, the timer starts running in
+ * the target. This parameter will ensure that the timer stops if there are
+ * no active peers in the capture list. Once the peers are added again to
+ * the capture list, the timer will not start again. The timer has to be
+ * started again using WMI_PDEV_PARAM_PER_PEER_PERIODIC_CFR_ENABLE.
+ * Value 1: Enable this feature
+ * Value 0: Disable this feature
+ */
+ WMI_PDEV_PARAM_ENABLE_OPTIMIZED_PERIODIC_CFR_TIMER,
+
+ /*
+ * Configures a portion of the Estimated Service Params indication
+ * (802.11mc) settings, which together specify estimated throughput.
+ * The accompanying A_UINT32 parameter is the ESP BA WINDOW size advertised
+ * Value 0: Disable this feature
+ * Non zero Value: ESP BA WINDOW size
+ */
+ WMI_PDEV_PARAM_ESP_BA_WINDOW,
+
+ /*
+ * Configures a portion of the Estimated Service Params indication
+ * (802.11mc) settings, which together specify estimated throughput.
+ * The accompanying A_UINT32 parameter is the air time fraction to be
+ * advertised in the ESP IE
+ * Value 0: Disable this feature
+ * Non zero Value: Air time fraction in percentage
+ */
+ WMI_PDEV_PARAM_ESP_AIRTIME_FRACTION,
+
+ /*
+ * Configures a portion of the Estimated Service Params indication
+ * (802.11mc) settings, which together specify estimated throughput.
+ * The accompanying A_UINT32 parameter specifies PPDU duration in units
+ * of milliseconds.
+ * Value 0: Disable this feature
+ * Non zero Value: PPDU duration in milliseconds
+ */
+ WMI_PDEV_PARAM_ESP_PPDU_DURATION,
+
+ /*
+ * Enable/Disable NOL(Non Occupancy list) in firmware
+ * 1- Use NOL in firmware
+ * 0- Don't use NOL in firmware
+ */
+ WMI_PDEV_PARAM_USE_NOL,
+
+ /*
+ * Allow / Not Allow RU26 in any user's RU allocation field in UL OFDMA
+ * trigger frames sent by AP
+ * 1 - Allow RU26
+ * 0 - Do not allow RU26
+ */
+ WMI_PDEV_PARAM_UL_RU26_ALLOWED,
+
+ /*
+ * Enable/Disable sub channel marking
+ * 1 - Enable sub channel marking
+ * 0 - Disable sub channel marking (default value)
+ */
+ WMI_PDEV_PARAM_SUB_CHANNEL_MARKING,
+
+ /*
+ * Enable/Disable/Set MGMT_TTL in milliseconds.
+ * non_zero - Enable, with the specified value
+ * 0 - Disable
+ */
+ WMI_PDEV_PARAM_SET_MGMT_TTL,
+
+ /*
+ * Enable/Disable/Set PROBE_RESP_TTL in milliseconds.
+ * non_zero - Enable, with the specified value
+ * 0 - Disable
+ */
+ WMI_PDEV_PARAM_SET_PROBE_RESP_TTL,
+
+ /*
+ * TBTT_CTRL_CFG
+ * BITS 0 - 2 (refer to WMI_TBTT_CTRL_CFG enum)
+ * 0 - DEFAULT -> HW_TBTT
+ * 1 - SW_TBTT -> HW_TBTT disabled,
+ * software would truncate BURST near TBTT
+ * 2 - IGNORE_TBTT
+ *
+ * BITS 3 - 31 Reserved, must be set to 0x0
+ */
+ WMI_PDEV_PARAM_SET_TBTT_CTRL,
+
+ /*
+ * BITS0 ~1 (refer to enum)
+ * 0 - default --> always update
+ * 1 - ignore to update
+ * 2 - update if larger than threshould
+ * 3 - update if less or equal than threshould
+ *
+ * BITS 2 ~ 31 Threshould
+ */
+ WMI_PDEV_PARAM_NAV_OVERRIDE_CONFIG,
+
+ /* Set global MU PPDU duration for DL (usec units) */
+ WMI_PDEV_PARAM_SET_MU_PPDU_DURATION,
+
+ /*
+ * Enable / disable test mode configuration.
+ * By default FW will always send triggers dynamically (mix of BSR/Basic).
+ * The below testmode are only used for certain tests.
+ * A value of 1 in a given bit enables corresponding test mode.
+ * bit | test mode
+ * ---------------
+ * 0 | FW only sends BSR triggers.
+ * 1 | FW only sends Basic triggers.
+ * 2 | If set, FW enables MU-RTS trigger.
+ * | If cleared, FW uses implementation-specific internal default setting.
+ * 3 | FW enables unicast embedded trigger in HE MU PPDU.
+ * 4-31| reserved.
+ */
+ WMI_PDEV_PARAM_SET_TEST_CMD_UL_TRIGGER_TYPE_ENABLE,
+
+ /*
+ * Configure test command to set LSIG len.
+ * Value 0: Dynamic LSIG based on STA's qdepth.
+ * Non zero Value: LSIG length to be configured
+ * as part of trigger frame.
+ * bit |
+ * ---------------
+ * 0 - 30 | Bits storing the host supplied <value>.
+ * 31 | If set: The legitimate value closest to the value specified in
+ * | in bits 30:0 is directly set in UL len in trigger frame.
+ * | The FW performs calculations to determine which legitimate
+ * | value is closest to the specified value, if the specified
+ * | value is not already legitimate.
+ * | If not set: The value in lower bits is the duration (in ms),
+ * | from which the UL len is derived.
+ * | Example: if host sets 2000 (2ms), then UL Len in trigger
+ * | will be derived to accomodate the given duration.
+ */
+ WMI_PDEV_PARAM_SET_TEST_CMD_UL_TRIGGER_LSIG_LEN,
+
+ /*
+ * Configure test cmd for fixed rate setting used for UL Trigger
+ * (only Basic/BSR triggers).
+ * The top nibble is used to select which format to use for encoding
+ * the rate specification: 0xVXXXXXXX, V must be 1 for the UL
+ * format.
+ * If V == 0b0001: format is: 0x1000RRRR.
+ * This will be output of WMI_ASSEMBLE_RATECODE_V1
+ *
+ */
+ WMI_PDEV_PARAM_SET_TEST_CMD_UL_TRIGGER_FIXED_RATE,
+
+ /*
+ * Configure test command to set the mac padding duration.
+ * 0 - FW set Mac Padding to 0us
+ * 1 - FW set Mac Padding to 8us
+ * 2 - FW set Mac Padding to 16us
+ */
+ WMI_PDEV_PARAM_SET_TEST_CMD_UL_MAC_PADDING,
+
+ /*
+ * Configure test command to set the fc duration in BSR trigger frame.
+ * value 0 - FW calulates the duration(default).
+ * Non zero Value: Duration to be configured.
+ */
+ WMI_PDEV_PARAM_SET_TEST_CMD_UL_BSR_FC_DURATION,
+
+ /* Parameter used for configuring TWT scheduling properties
+ * bit | config_mode
+ * -----------------
+ * 0 | Disables DL MU for TWT peers within TWT SP
+ * 1 | Disables UL MU for TWT peers within TWT SP
+ * 2 | Disables scheduling from WMM sched context for TWT peers
+ * 3 | If set, FW only sends Basic triggers in TWT SP.
+ * 4-31| reserved.
+ */
+ WMI_PDEV_PARAM_SET_TEST_CMD_TWT_SCHED_CONFIG,
+
+ /* Parameter used to configure OBSS Packet Detect threshold
+ * for Spatial Reuse feature.
+ * The accepted values are in between 0x00 and 0xFF, inclusive.
+ * The parameter value is programmed into the spatial reuse register,
+ * to specify how low the background signal strength from neighboring
+ * BSS cells must be, for this AP to employ spatial reuse.
+ *
+ * The value of the parameter is compared against the OBSS RSSI in dB.
+ * It is a 8-bit value whose
+ * range is -128 to 127 (after two's complement operation).
+ * For example, if the parameter value is 0xF5, the target will
+ * allow spatial reuse if the RSSI detected from other BSS
+ * is below -10 dB.
+ * Similarly, if the parameter value is 0x0A, the target will
+ * allow spatial reuse only if the RSSI detected from neighboring
+ * BSS cells is no more than 10 dB.
+ *
+ * bit | purpose
+ * -------------
+ * 0 - 7 | Param Value
+ * 8 - 30 | reserved
+ * 31 | Enable/Disable. If set to 0, ignore bits 0-7.
+ */
+ WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD,
+
+ /* Parameter used for enabling/disabling non wlan coex from boot */
+ WMI_PDEV_PARAM_ENABLE_NON_WLAN_COEX_FROM_BOOT,
+
+ /* Parameter used to configure OBSS Packet Detection per Access Category
+ * for Spatial Reuse feature.
+ * Based on the bits set, the corresponding Access Category Queues will have
+ * spatial reuse enabled / disabled.
+ * bit | AC
+ * -----------
+ * 0 | BK
+ * 1 | BE
+ * 2 | VI
+ * 3 | VO
+ * 4 - 31 | Reserved
+ */
+ WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC,
+
} WMI_PDEV_PARAM;
+#define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
+#define WMI_PDEV_ONLY_BSR_TRIG_ENABLE(trig_type) WMI_SET_BITS(trig_type, 0, 1, 1)
+#define WMI_PDEV_ONLY_BSR_TRIG_DISABLE(trig_type) WMI_SET_BITS(trig_type, 0, 1, 0)
+
+#define WMI_PDEV_ONLY_BASIC_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 1, 1)
+#define WMI_PDEV_ONLY_BASIC_TRIG_ENABLE(trig_type) WMI_SET_BITS(trig_type, 1, 1, 1)
+#define WMI_PDEV_ONLY_BASIC_TRIG_DISABLE(trig_type) WMI_SET_BITS(trig_type, 1, 1, 0)
+
+#define WMI_PDEV_MU_RTS_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 2, 1)
+#define WMI_PDEV_MU_RTS_ENABLE(trig_type) WMI_SET_BITS(trig_type, 2, 1, 1)
+#define WMI_PDEV_MU_RTS_DISABLE(trig_type) WMI_SET_BITS(trig_type, 2, 1, 0)
+
+#define WMI_PDEV_EMBEDDED_TRIGGER_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 3, 1)
+#define WMI_PDEV_EMBEDDED_TRIGGER_ENABLE(trig_type) WMI_SET_BITS(trig_type, 3, 1, 1)
+#define WMI_PDEV_EMBEDDED_TRIGGER_DISABLE(trig_type) WMI_SET_BITS(trig_type, 3, 1, 0)
+
+#define WMI_PDEV_TWT_SCHED_CFG_IS_DL_MU_IS_ENABLED(twt_sched_cfg) WMI_GET_BITS(twt_sched_cfg, 0, 1)
+#define WMI_PDEV_TWT_SCHED_CFG_DL_MU_ENABLE(twt_sched_cfg) WMI_SET_BITS(twt_sched_cfg, 0, 1, 1)
+#define WMI_PDEV_TWT_SCHED_CFG_DL_MU_DISABLE(twt_sched_cfg) WMI_SET_BITS(twt_sched_cfg, 0, 1, 0)
+
+#define WMI_PDEV_TWT_SCHED_CFG_IS_UL_MU_IS_ENABLED(twt_sched_cfg) WMI_GET_BITS(twt_sched_cfg, 1, 1)
+#define WMI_PDEV_TWT_SCHED_CFG_UL_MU_ENABLE(twt_sched_cfg) WMI_SET_BITS(twt_sched_cfg, 1, 1, 1)
+#define WMI_PDEV_TWT_SCHED_CFG_UL_MU_DISABLE(twt_sched_cfg) WMI_SET_BITS(twt_sched_cfg, 1, 1, 0)
+
+#define WMI_PDEV_TWT_SCHED_CFG_IS_WMM_IS_ENABLED(twt_sched_cfg) WMI_GET_BITS(twt_sched_cfg, 2, 1)
+#define WMI_PDEV_TWT_SCHED_CFG_WMM_ENABLE(twt_sched_cfg) WMI_SET_BITS(twt_sched_cfg, 2, 1, 1)
+#define WMI_PDEV_TWT_SCHED_CFG_WMM_DISABLE(twt_sched_cfg) WMI_SET_BITS(twt_sched_cfg, 2, 1, 0)
+
+#define WMI_PDEV_TWT_SCHED_CFG_IS_USE_ONLY_BASIC_TRIGGER_IS_ENABLED(twt_sched_cfg) WMI_GET_BITS(twt_sched_cfg, 3, 1)
+#define WMI_PDEV_TWT_SCHED_CFG_USE_ONLY_BASIC_TRIGGER_ENABLE(twt_sched_cfg) WMI_SET_BITS(twt_sched_cfg, 3, 1, 1)
+#define WMI_PDEV_TWT_SCHED_CFG_USE_ONLY_BASIC_TRIGGER_DISABLE(twt_sched_cfg) WMI_SET_BITS(twt_sched_cfg, 3, 1, 0)
+
+#define WMI_PDEV_LSIG_LEN_DURATION_ENABLE(lsig_len) WMI_SET_BITS(lsig_len, 0, 31, 1)
+#define WMI_PDEV_LSIG_LEN_DURATION_DISABLE(lsig_len) WMI_SET_BITS(lsig_len, 0, 31, 0)
+#define WMI_PDEV_LSIG_LEN_DURATION_GET(lsig_len) WMI_GET_BITS(lsig_len, 0, 30)
+#define WMI_PDEV_LSIG_LEN_DURATION_SET(lsig_len, value) WMI_SET_BITS(lsig_len, 0, 30, value)
+
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_param_cmd_fixed_param */
/** pdev_id for identifying the MAC
@@ -4955,6 +6098,28 @@
A_UINT32 param_value;
} wmi_pdev_set_param_cmd_fixed_param;
+/* param values for WMI_PDEV_PARAM_SET_TBTT_CTRL's TBTT_CTRL_CFG bit-field */
+typedef enum {
+ WMI_TBTT_CTRL_HW_TRUNCATE = 0,
+ WMI_TBTT_CTRL_SW_TRUNCATE,
+ WMI_TBTT_CTRL_IGNORE_TBTT,
+
+ WMI_TBTT_CTRL_MAX = 0x7,
+} WMI_TBTT_CTRL_CFG;
+
+/** MACRO to set / get TBTT_CTRL_CFG bit-field within
+ * WMI_PDEV_PARAM_SET_TBTT_CTRL:
+ * bits 0~2 : TBTT_CTRL_CFG
+ * bits 3~31: Reserved (set to 0x0)
+ */
+#define WMI_PDEV_PARAM_TBTT_CTRL_CFG_S 0
+#define WMI_PDEV_PARAM_TBTT_CTRL_CFG 0x00000007
+
+#define WMI_PDEV_PARAM_GET_TBTT_CTRL_CFG(word32) \
+ WMI_F_MS(word32, WMI_PDEV_PARAM_TBTT_CTRL_CFG)
+#define WMI_PDEV_PARAM_SET_TBTT_CTRL_CFG(word32, value) \
+ WMI_F_RMW(word32,value,WMI_PDEV_PARAM_TBTT_CTRL_CFG)
+
/** MACRO define to set / get 11b and 11ag mode TX chain number:
* bit 0~15 : 11b mode TX chain number.
* bit 16~31: 11ag mode TX chain number.
@@ -5018,6 +6183,35 @@
*/
} wmi_pdev_update_ctltable_request_fixed_param;
+#define WMI_ESP_ESTIMATE_GET_BE(airtime) WMI_GET_BITS(airtime, 0, 8)
+#define WMI_ESP_ESTIMATE_SET_BE(airtime, value) WMI_SET_BITS(airtime, 0, 8, value)
+
+#define WMI_ESP_ESTIMATE_GET_BK(airtime) WMI_GET_BITS(airtime, 8, 8)
+#define WMI_ESP_ESTIMATE_SET_BK(airtime, value) WMI_SET_BITS(airtime, 8, 8, value)
+
+#define WMI_ESP_ESTIMATE_GET_VI(airtime) WMI_GET_BITS(airtime, 16, 8)
+#define WMI_ESP_ESTIMATE_SET_VI(airtime, value) WMI_SET_BITS(airtime, 16, 8, value)
+
+#define WMI_ESP_ESTIMATE_GET_VO(airtime) WMI_GET_BITS(airtime, 24, 8)
+#define WMI_ESP_ESTIMATE_SET_VO(airtime, value) WMI_SET_BITS(airtime, 24, 8, value)
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_esp_estimate_event_fixed_param */
+ /** pdev_id for identifying the MAC
+ * See macros starting with WMI_PDEV_ID_ for values.
+ * In non-DBDC case host should set it to 0
+ */
+ A_UINT32 pdev_id;
+ /*
+ * Percentage of air time available for each AC
+ * BIT[0-7] : AC_BE
+ * BIT[8-15] : AC_BK
+ * BIT[16-23] : AC_VI
+ * BIT[24-31] : AC_VO
+ */
+ A_UINT32 ac_airtime_percentage;
+} wmi_esp_estimate_event_fixed_param;
+
#define WMI_FAST_DIVERSITY_BIT_OFFSET 0
#define WMI_SLOW_DIVERSITY_BIT_OFFSET 1
@@ -5135,6 +6329,13 @@
* A ppdu_id value of 0x0 is invalid, and should be ignored.
*/
A_UINT32 ppdu_id;
+ /* ack_rssi
+ * TX mgmt ack RSSI report to host.
+ * Only valid when status == COMPLETE_OK and the ACK_RSSI report is enabled
+ * ACK RSSI is reported as SNR dB, i.e. how many dB the RSSI is above
+ * the noise floor.
+ */
+ A_UINT32 ack_rssi;
} wmi_mgmt_tx_compl_event_fixed_param;
typedef struct {
@@ -5159,6 +6360,8 @@
* A_UINT32 desc_ids[num_reports]; <- from tx_send_cmd
* A_UINT32 status[num_reports]; <- WMI_MGMT_TX_COMP_STATUS_TYPE
* A_UINT32 ppdu_id[num_reports]; <- list of PPDU IDs
+ * A_UINT32 ack_rssi[num_reports]; <- list of ack RSSI
+ * RSSI units = dB w.r.t. noise floor
*/
} wmi_mgmt_tx_compl_bundle_event_fixed_param;
@@ -5167,9 +6370,14 @@
#define WMI_TPC_TX_NUM_CHAIN 4
typedef enum {
- WMI_TPC_CONFIG_EVENT_FLAG_TABLE_CDD = 0x1,
+ /* bits 0-7 for table flags */
+ WMI_TPC_CONFIG_EVENT_FLAG_TABLE_CDD = 0x1,
WMI_TPC_CONFIG_EVENT_FLAG_TABLE_STBC = 0x2,
WMI_TPC_CONFIG_EVENT_FLAG_TABLE_TXBF = 0x4,
+
+ /* bits 8-11 for interface version flags */
+ WMI_TPC_CONFIG_EVENT_FLAG_IF_MASK = 0x0F00,
+ WMI_TPC_CONFIG_EVENT_FLAG_IF_V1 = 0x0100,
} WMI_TPC_CONFIG_EVENT_FLAG;
typedef struct {
@@ -5194,8 +6402,21 @@
* See macros starting with WMI_PDEV_ID_ for values.
*/
A_UINT32 pdev_id;
-/* This TLV is followed by a byte array:
+/* This TLV is followed by further TLVs:
+ * 1. byte array:
* A_UINT8 ratesArray[];
+ * 2a. multi-dimensional array dimension spec:
+ * wmi_tlv_arrays_len_param ctlPwrTbl_param[0 or 1]
+ *
+ * 2b. ctl power table
+ * A_UINT8 ctlPwrTbl_buf[bf][modes][nss], i.e.
+ * A_UINT8 ctlPwrTbl_buf[d3_len * d2_len * d1_len]
+ * bf is [0 or 1] for [on or off].
+ * For 2G, modes is [0, 1, 2, or 3] for
+ * [cck, legacy, (v)ht20, or (v)ht40]
+ * For 5G, modes is [0, 1, 2, or 3] for
+ * [legacy, (v)ht20, (v)ht40, or vht80]
+ * nss is [0, 1, 2, or 3] for the number of streams 1~4.
*/
} wmi_pdev_tpc_config_event_fixed_param;
@@ -5210,6 +6431,8 @@
A_UINT32 ant_id[WMI_MAX_CHAINS];
/** mac address of diversity peer */
wmi_mac_addr macaddr;
+ /* EVM value for stream0 and stream1 20Mhz, dB units */
+ A_INT32 chain_evm[WMI_MAX_CHAINS];
} wmi_pdev_div_rssi_antid_event_fixed_param;
typedef struct {
@@ -5318,6 +6541,11 @@
WMI_PKTLOG_ENABLE_FORCE = 1, /* pktlog unconditionally enabled */
} WMI_PKTLOG_ENABLE;
+typedef enum {
+ WMI_PKTLOG_FILTER_IN = 0, /* capture only for the MAC addresses in pktlog_mac_addr_list*/
+ WMI_PKTLOG_FILTER_OUT = 1, /* capture for all MAC addresses except those in pktlog_mac_addr_list */
+} WMI_PKTLOG_FILTER_TYPE;
+
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_pktlog_enable_cmd_fixed_param */
/** pdev_id for identifying the MAC
@@ -5337,6 +6565,58 @@
} wmi_pdev_pktlog_disable_cmd_fixed_param;
typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_pdev_pktlog_filter_info */
+ A_UINT32 tlv_header;
+ /** mac addr of the peer to be filtered */
+ wmi_mac_addr peer_mac_address;
+} wmi_pdev_pktlog_filter_info;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_pktlog_filter_cmd_fixed_param */
+ /** pdev_id for identifying the MAC
+ * See macros starting with WMI_PDEV_ID_ for values.
+ */
+ A_UINT32 pdev_id;
+ /** 0 - disable filtering, 1 - enable filtering */
+ A_UINT32 enable;
+ A_UINT32 filter_type; /* WMI_PKTLOG_FILTER_TYPE */
+ A_UINT32 num_of_mac_addresses;
+ /* This TLV is followed by another TLV of array of structs
+ * wmi_pdev_pktlog_filter_info pdev_pktlog_filter_info[];
+ */
+} wmi_pdev_pktlog_filter_cmd_fixed_param;
+
+typedef enum {
+ WMI_ROGUE_AP_ON_STA_PS = 1, /* rogue ap on sta ps module */
+} WMI_ROGUE_AP_TYPE;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_rap_config_fixed_param */
+ /** pdev_id for identifying the MAC, the default value is WMI_PDEV_ID_SOC
+ * See macros starting with WMI_PDEV_ID_ for values.
+ */
+ A_UINT32 pdev_id;
+ /** rogue ap type, see WMI_ROGUE_AP_TYPE */
+ A_UINT32 type;
+ /** Enable detection of rogue ap in the ps module
+ *
+ * 0 -> disabled
+ * 1 -> enabled (default)
+ */
+ A_UINT32 sta_ps_detection_enabled;
+/* This TLV is followed by rap_param for each rogue ap:
+ * wmi_pdev_set_rap_config_on_sta_ps_tlv_param rap_param[];
+ */
+} wmi_pdev_set_rap_config_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_set_rap_config_on_sta_ps_tlv_param */
+ /** bssid of rogue ap */
+ wmi_mac_addr bssid;
+} wmi_pdev_set_rap_config_on_sta_ps_tlv_param;
+
+typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_mib_stats_enable_cmd_fixed_param */
/** pdev_id for identifying the MAC
* See macros starting with WMI_PDEV_ID_ for values.
@@ -5510,18 +6790,21 @@
} wmi_pdev_set_wmm_params_cmd_fixed_param;
typedef enum {
- WMI_REQUEST_PEER_STAT = 0x01,
- WMI_REQUEST_AP_STAT = 0x02,
- WMI_REQUEST_PDEV_STAT = 0x04,
- WMI_REQUEST_VDEV_STAT = 0x08,
- WMI_REQUEST_BCNFLT_STAT = 0x10,
- WMI_REQUEST_VDEV_RATE_STAT = 0x20,
- WMI_REQUEST_INST_STAT = 0x40,
- WMI_REQUEST_MIB_STAT = 0x80,
- WMI_REQUEST_RSSI_PER_CHAIN_STAT = 0x100,
- WMI_REQUEST_CONGESTION_STAT = 0x200,
- WMI_REQUEST_PEER_EXTD_STAT = 0x400,
- WMI_REQUEST_BCN_STAT = 0x800,
+ WMI_REQUEST_PEER_STAT = 0x0001,
+ WMI_REQUEST_AP_STAT = 0x0002,
+ WMI_REQUEST_PDEV_STAT = 0x0004,
+ WMI_REQUEST_VDEV_STAT = 0x0008,
+ WMI_REQUEST_BCNFLT_STAT = 0x0010,
+ WMI_REQUEST_VDEV_RATE_STAT = 0x0020,
+ WMI_REQUEST_INST_STAT = 0x0040,
+ WMI_REQUEST_MIB_STAT = 0x0080,
+ WMI_REQUEST_RSSI_PER_CHAIN_STAT = 0x0100,
+ WMI_REQUEST_CONGESTION_STAT = 0x0200,
+ WMI_REQUEST_PEER_EXTD_STAT = 0x0400,
+ WMI_REQUEST_BCN_STAT = 0x0800,
+ WMI_REQUEST_BCN_STAT_RESET = 0x1000,
+ WMI_REQUEST_PEER_EXTD2_STAT = 0x2000,
+ WMI_REQUEST_MIB_EXTD_STAT = 0x4000,
} wmi_stats_id;
/*
@@ -5718,6 +7001,7 @@
WMI_CHAN_WIDTH_80P80 = 4,
WMI_CHAN_WIDTH_5 = 5,
WMI_CHAN_WIDTH_10 = 6,
+ WMI_CHAN_WIDTH_165 = 7,
} wmi_channel_width;
/*Clear stats*/
@@ -5754,6 +7038,18 @@
wmi_mac_addr peer_macaddr;
} wmi_request_link_stats_cmd_fixed_param;
+#define WLM_STATS_REQ_LINK 0x00000001
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_request_wlm_stats_cmd_fixed_param */
+ /** unique id identifying the VDEV, generated by the caller */
+ A_UINT32 vdev_id;
+ /** WLM event request bitmask
+ * Used by host to customize the wlm stats report.
+ * Filled with a combination of WLM_STATS_xxx values.
+ */
+ A_UINT32 request_bitmask;
+} wmi_request_wlm_stats_cmd_fixed_param;
+
/* channel statistics */
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel_stats */
@@ -6077,6 +7373,36 @@
*/
} wmi_iface_link_stats_event_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_wlm_stats_event_fixed_param */
+ /** bitmask listing which WLM stats are provided.
+ * Copied from wlm_stats_cmd_fixed_param.
+ * (This field is provided for convenience rather than necessity, since
+ * the recipient can directly check which TLV arrays have non-zero length.)
+ */
+ A_UINT32 request_bitmask;
+ /** unique id identifying the VDEV, generated by the caller */
+ A_UINT32 vdev_id;
+ /**
+ * timestamp of event report, in microseconds units
+ * This timestamp is for debugging purposes only.
+ * It can be used to correlate this WLM stats event data with
+ * other WLM information uploaded through other means.
+ */
+ A_UINT32 timestamp;
+ /**
+ * Interval between two consecutive WLM stats query requests,
+ * in microseconds units.
+ * This interval is used for converting the scan_period and pwr_on_period
+ * values from within wmi_wlm_link_stats from percentage units to time
+ * units.
+ */
+ A_UINT32 req_interval;
+/*
+ * This TLV is followed by an A_UINT32 array TLV carrying an opaque payload.
+ */
+} wmi_wlm_stats_event_fixed_param;
+
/** Suspend option */
enum {
WMI_PDEV_SUSPEND, /* suspend */
@@ -6121,6 +7447,31 @@
} wmi_rx_aggr_failure_info;
typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_pn_request_cmd_fixed_param */
+ /** unique id identifying the VDEV, generated by the caller */
+ A_UINT32 vdev_id;
+ /** peer MAC address */
+ wmi_mac_addr peer_macaddr;
+ A_UINT32 key_type; /* use standard cipher types - see WMI_CIPHER_ defs */
+} wmi_peer_tx_pn_request_cmd_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tx_pn_response_event_fixed_param */
+ /** unique id identifying the VDEV, generated by the caller */
+ A_UINT32 vdev_id;
+ /** peer MAC address */
+ wmi_mac_addr peer_macaddr;
+ A_UINT32 key_type; /* use standard cipher types - see WMI_CIPHER_ defs */
+ /** Packet Number
+ * The PN is provided in little endian order, with bits 7:0 of the PN
+ * residing in pn[0].
+ * The key_type indirectly specifies the packet number length, and thus
+ * how many bytes within pn[] are filled with valid data.
+ */
+ A_UINT8 pn[16];
+} wmi_peer_tx_pn_response_event_fixed_param;
+
+typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_event_fixed_param */
wmi_stats_id stats_id;
/** number of pdev stats event structures (wmi_pdev_stats) 0 or 1 */
@@ -6137,6 +7488,18 @@
A_UINT32 pdev_id; /** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0. */
/** number of beacon stats event structures (wmi_bcn_stats) */
A_UINT32 num_bcn_stats;
+ /** number of extended peer stats event structures (wmi_peer_extd_stats) */
+ A_UINT32 num_peer_extd_stats;
+ /** number of extd2 peer stats event structures (wmi_peer_extd2_stats) */
+ A_UINT32 num_peer_extd2_stats;
+ /** last_event
+ * The most significant bit is set to 1 to indicate whether the last_event
+ * field contains valid data. The least significant bit is set to 1 to
+ * indicate this is the final WMI_STATS_EVENT in a series.
+ */
+ A_UINT32 last_event;
+ /** number of extended MIB stats event structures (wmi_mib_extd_stats) */
+ A_UINT32 num_mib_extd_stats;
/* This TLV is followed by another TLV of array of bytes
* A_UINT8 data[];
@@ -6153,6 +7516,11 @@
* the data[] array also contains num_peer_stats * size of wmi_peer_extd_stats
* following the information elements listed above.
*/
+/* If WMI_REQUEST_MIB_EXTD_STAT is set in stats_id,
+ * the data[] array also contains
+ * num_mib_extd_stats * size of(struct wmi_mib_extd_stats)
+ * following the information elements listed above.
+ */
} wmi_stats_event_fixed_param;
/* WLAN channel CCA stats bitmap */
@@ -6498,6 +7866,31 @@
TRIGGER_COND_ID_ONE_TIME_REQUEST = 0x3,
} wmi_report_stats_event_trigger_cond_id;
+typedef struct
+{
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_stats_interference */
+
+ /** For cases where a single rx chain has options to be connected to
+ * different rx antennas, show which rx antennas were in use during
+ * receipt of a given PPDU.
+ * This sa_ant_matrix provides a bitmask of the antennas used while
+ * receiving this frame.
+ */
+ A_UINT32 sa_ant_matrix;
+
+ /** Count how many times the hal_rxerr_phy is marked, in this time period.
+ * The counter value is reset each period. The host specifies the period
+ * via WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD.
+ */
+ A_UINT32 phyerr_count;
+
+ /** The timestamp at which the WMI event is reported.
+ * In targets that have a WBTIMER_1 timer, this timestamp is taken
+ * from WBTIMER_1.
+ */
+ A_UINT32 timestamp;
+} wmi_stats_interference;
+
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_report_stats_event_fixed_param */
/** Indicate what triggered this event, check wmi_report_stats_event_trigger_cond_id for details */
@@ -6578,6 +7971,7 @@
* A_UINT32 rx_mcs[][][]; Array length is (num_peer_ac_rx_stats * WLAN_MAX_AC) * rx_mcs_array_len,
* array index is (peer_index * WLAN_MAX_AC + ac_index) * rx_mcs_array_len + MCS index
* wmi_stats_period stats_period[]; Array length is specified by stats_period_array_len
+ * wmi_stats_interference stats_interference[]; Array length is determied by dividing array level TLV header's length value by array-element TLV header's length value.
**/
} wmi_report_stats_event_fixed_param;
@@ -6723,8 +8117,23 @@
/**
* PDEV statistics
- * @todo
- * add all PDEV stats here
+ *
+ * This struct incorporates the wlan_dbg_stats struct, which is
+ * conditionally defined, based on the AR900B flag.
+ * The below _v1 struct variant is the unconditional definition
+ * that matches what would be conditionally defined by builds that
+ * don't use the AR900B flag. The _v2 struct variant is the
+ * unconditional definition that matches what would be conditionally
+ * defined by builds that use the AR900B flag.
+ * The _v2 struct def can be used within host or target builds
+ * that don't use the AR900B flag, but needs to interoperate with a
+ * target or host build that does use the AR900B flag.
+ * Similarly, the _v1 struct def can be used by a host or target build
+ * that does use the AR900B flag, but needs to interoperate with a
+ * target or host build that doesn't use the AR900B flag.
+ *
+ * For backwards compatibility, wmi_pdev_stats is still (conditionally)
+ * defined, as an alias for either the _v1 or _v2 variant.
*/
typedef struct {
/** Channel noise floor */
@@ -6742,9 +8151,33 @@
/** Channel Tx Power */
A_UINT32 chan_tx_pwr;
/** WAL dbg stats */
- struct wlan_dbg_stats pdev_stats;
+ struct wlan_dbg_stats_v1 pdev_stats;
+} wmi_pdev_stats_v1;
-} wmi_pdev_stats;
+typedef struct {
+ /** Channel noise floor */
+ A_INT32 chan_nf;
+ /** TX frame count */
+ A_UINT32 tx_frame_count;
+ /** RX frame count */
+ A_UINT32 rx_frame_count;
+ /** rx clear count */
+ A_UINT32 rx_clear_count;
+ /** cycle count */
+ A_UINT32 cycle_count;
+ /** Phy error count */
+ A_UINT32 phy_err_count;
+ /** Channel Tx Power */
+ A_UINT32 chan_tx_pwr;
+ /** WAL dbg stats */
+ struct wlan_dbg_stats_v2 pdev_stats;
+} wmi_pdev_stats_v2;
+
+#if defined(AR900B)
+#define wmi_pdev_stats wmi_pdev_stats_v2
+#else
+#define wmi_pdev_stats wmi_pdev_stats_v1
+#endif
/**
* VDEV statistics
@@ -6806,7 +8239,7 @@
typedef struct {
/** peer MAC address */
wmi_mac_addr peer_macaddr;
- /* rx duration in microseconds*/
+ /* lower 32 bits of rx duration in microseconds */
A_UINT32 rx_duration;
/** Total TX bytes (including dot11 header) sent to peer */
A_UINT32 peer_tx_bytes;
@@ -6816,10 +8249,43 @@
A_UINT32 last_tx_rate_code;
/** TX power used by peer - units are 0.5 dBm */
A_INT32 last_tx_power;
- A_UINT32 reserved[4]; /** for future use - add new peer stats here */
+
+ /* Total number of received multicast & broadcast data frames corresponding to this peer */
+ A_UINT32 rx_mc_bc_cnt; /* 1 in the MSB of rx_mc_bc_cnt represents a valid data */
+ /* upper 32 bits of rx duration in microseconds */
+ A_UINT32 rx_duration_u32; /* 1 in the most significant bit indicates this field contains valid data */
+ A_UINT32 reserved[2]; /** for future use - add new peer stats here */
} wmi_peer_extd_stats;
typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_extd2_stats */
+ /** peer MAC address */
+ wmi_mac_addr peer_macaddr;
+ /*
+ * The following rx_bytes field (lower/upper pair) counts only the
+ * MSDU bytes (after 802.11 decap, if applicable), and thus doesn't
+ * count the 802.11 header, unlike the wmi_peer_extd_stats.peer_rx_bytes
+ * and wmi_peer_stats_info.rx_bytes fields.
+ */
+ /** Lower 32 bits of the rx_bytes (size of MSDUs) excluding dot11 header from this peer */
+ A_UINT32 rx_bytes_l32;
+ /** Upper 32 bits of the rx_bytes (size of MSDUs) excluding dot11 header from this peer */
+ A_UINT32 rx_bytes_u32;
+ /** Number of MPDUS received with FCS error from this peer */
+ A_UINT32 rx_fcs_err;
+ /** Number of MPDUs(both data and non data) received from this peer */
+ A_UINT32 rx_mpdus;
+ /** nss of last tx data to peer */
+ A_UINT32 last_tx_nss;
+ /** nss of last rx data from peer */
+ A_UINT32 last_rx_nss;
+ /** chain mask used for last tx data to peer */
+ A_UINT32 last_tx_chain_mask;
+ /** chain mask used for last rx data from peer */
+ A_UINT32 last_rx_chain_mask;
+} wmi_peer_extd2_stats;
+
+typedef struct {
/** Primary channel freq of the channel for which stats are sent */
A_UINT32 chan_mhz;
/** Time spent on the channel */
@@ -6832,6 +8298,9 @@
A_UINT32 rx_duration_us;
} wmi_chan_stats;
+/**
+ * MIB statistics. See 802.11 spec for the meaning of each field.
+ */
typedef struct {
A_UINT32 tx_mpdu_grp_frag_cnt; /*dot11TransmittedFragmentCount */
A_UINT32 tx_msdu_grp_frm_cnt; /*dot11GroupTransmittedFrameCount */
@@ -6884,6 +8353,20 @@
A_UINT32 reserved_4;
} wmi_mib_stats;
+/**
+ * MIB extension statistics.
+ */
+typedef struct {
+ A_UINT32 tx_msdu_multi_retry_cnt; /*dot11MultipleRetryCount*/
+ A_UINT32 tx_ack_fail_cnt; /*dot11ACKFailureCount*/
+ A_UINT32 tx_qos_msdu_multi_retry_up; /*dot11QosMultipleRetryCount*/
+ A_UINT32 tx_qos_ack_fail_cnt_up; /*dot11QosACKFailureCount*/
+ A_UINT32 rsna_cmac_icv_err_cnt; /*dot11RSNAStatsCMACICVErrors*/
+ A_UINT32 rsna_cmac_replay_err_cnt; /*dot11RSNAStatsCMACReplays*/
+ A_UINT32 rx_ampdu_deli_crc_err_cnt; /*dot11AMPDUDelimiterCRCErrorCount*/
+ A_UINT32 reserved[8]; /* Reserve more fields for future extension */
+} wmi_mib_extd_stats;
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_rssi_stats */
A_UINT32 vdev_id;
@@ -6911,6 +8394,11 @@
*/
} wmi_per_chain_rssi_stats;
+/* vdev control flags (per bits) */
+#define VDEV_FLAGS_NON_MBSSID_AP 0x00000001 /* legacy AP */
+#define VDEV_FLAGS_TRANSMIT_AP 0x00000002 /* indicate if this vdev is transmitting AP */
+#define VDEV_FLAGS_NON_TRANSMIT_AP 0x00000004 /* explicitly indicate this vdev is non-transmitting AP */
+
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_create_cmd_fixed_param */
/** unique id identifying the VDEV, generated by the caller */
@@ -6928,6 +8416,10 @@
* See macros starting with WMI_PDEV_ID_ for values.
*/
A_UINT32 pdev_id;
+ /** control flags for this vdev */
+ A_UINT32 flags;
+ /** vdevid of transmitted AP (mbssid case) */
+ A_UINT32 vdevid_trans;
/* This TLV is followed by another TLV of array of structures
* wmi_vdev_txrx_streams cfg_txrx_streams[];
*/
@@ -6972,6 +8464,8 @@
/* NAN Data Interface */
#define WMI_VDEV_TYPE_NDI 0x7
+#define WMI_VDEV_TYPE_MESH_POINT 0x8
+
/*
* Param values to be sent for WMI_VDEV_PARAM_SGI command
* which are used in 11ax systems
@@ -7005,6 +8499,11 @@
* added to AST table for traffic flow between mesh stations
*/
#define WMI_UNIFIED_VDEV_SUBTYPE_MESH_11S 0x6
+/* Subtype to indicate that the AP VAP is in smart monitor mode
+ * This is needed to differentiate in firmware betweem normal AP mode
+ * with smart monitor AP mode
+ */
+#define WMI_UNIFIED_VDEV_SUBTYPE_SMART_MON 0x7
/** values for vdev_start_request flags */
/** Indicates that AP VDEV uses hidden ssid. only valid for
@@ -7026,49 +8525,55 @@
#define WMI_UNIFIED_VDEV_START_LDPC_RX_ENABLED (1<<3)
/* BSS color 0-6 */
-#define WMI_HEOPS_COLOR_GET(he_ops) WMI_GET_BITS(he_ops, 0, 6)
-#define WMI_HEOPS_COLOR_SET(he_ops, value) WMI_SET_BITS(he_ops, 0, 6, value)
+#define WMI_HEOPS_COLOR_GET_D2(he_ops) WMI_GET_BITS(he_ops, 0, 6)
+#define WMI_HEOPS_COLOR_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 0, 6, value)
/* Default PE Duration subfield indicates the PE duration in units of 4 us */
-#define WMI_HEOPS_DEFPE_GET(he_ops) WMI_GET_BITS(he_ops, 6, 3)
-#define WMI_HEOPS_DEFPE_SET(he_ops, value) WMI_SET_BITS(he_ops, 6, 3, value)
+#define WMI_HEOPS_DEFPE_GET_D2(he_ops) WMI_GET_BITS(he_ops, 6, 3)
+#define WMI_HEOPS_DEFPE_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 6, 3, value)
/* TWT required */
-#define WMI_HEOPS_TWT_GET(he_ops) WMI_GET_BITS(he_ops, 9, 1)
-#define WMI_HEOPS_TWT_SET(he_ops, value) WMI_SET_BITS(he_ops, 9, 1, value)
+#define WMI_HEOPS_TWT_REQUIRED_GET_D2(he_ops) WMI_GET_BITS(he_ops, 9, 1)
+#define WMI_HEOPS_TWT_REQUIRED_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 9, 1, value)
+/* DEPRECATED, use WMI_HEOPS_TWT_REQUIRED_GET instead */
+#define WMI_HEOPS_TWT_GET_D2(he_ops) \
+ WMI_HEOPS_TWT_REQUIRED_GET_D2(he_ops)
+/* DEPRECATED, use WMI_HEOPS_TWT_REQUIRED_SET instead */
+#define WMI_HEOPS_TWT_SET_D2(he_ops, value) \
+ WMI_HEOPS_TWT_REQUIRED_SET_D2(he_ops, value)
/* RTS threshold in units of 32 us,0 - always use RTS 1023 - this is disabled */
-#define WMI_HEOPS_RTSTHLD_GET(he_ops) WMI_GET_BITS(he_ops, 10, 10)
-#define WMI_HEOPS_RTSTHLD_SET(he_ops, value) WMI_SET_BITS(he_ops, 10, 10, value)
+#define WMI_HEOPS_RTSTHLD_GET_D2(he_ops) WMI_GET_BITS(he_ops, 10, 10)
+#define WMI_HEOPS_RTSTHLD_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 10, 10, value)
/* Partial BSS Color field indicates whether BSS applies an AID assignment rule using partial BSS color bits */
-#define WMI_HEOPS_PARTBSSCOLOR_GET(he_ops) WMI_GET_BITS(he_ops, 20, 1)
-#define WMI_HEOPS_PARTBSSCOLOR_SET(he_ops, value) WMI_SET_BITS(he_ops, 20, 1, value)
+#define WMI_HEOPS_PARTBSSCOLOR_GET_D2(he_ops) WMI_GET_BITS(he_ops, 20, 1)
+#define WMI_HEOPS_PARTBSSCOLOR_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 20, 1, value)
/* MAX BSS supported by MultiBSS element */
-#define WMI_HEOPS_MAXBSSID_GET(he_ops) WMI_GET_BITS(he_ops, 21, 8)
-#define WMI_HEOPS_MAXBSSID_SET(he_ops, value) WMI_SET_BITS(he_ops, 21, 8, value)
+#define WMI_HEOPS_MAXBSSID_GET_D2(he_ops) WMI_GET_BITS(he_ops, 21, 8)
+#define WMI_HEOPS_MAXBSSID_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 21, 8, value)
/* Tx BSSID Indicator indicates whether HE AP corresponds to transmitted BSSID */
-#define WMI_HEOPS_TXBSSID_GET(he_ops) WMI_GET_BITS(he_ops, 29, 1)
-#define WMI_HEOPS_TXBSSID_SET(he_ops, value) WMI_SET_BITS(he_ops, 29, 1, value)
+#define WMI_HEOPS_TXBSSID_GET_D2(he_ops) WMI_GET_BITS(he_ops, 29, 1)
+#define WMI_HEOPS_TXBSSID_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 29, 1, value)
/* when set to 1 disables use of BSS color */
-#define WMI_HEOPS_BSSCOLORDISABLE_GET(he_ops) WMI_GET_BITS(he_ops, 30, 1)
-#define WMI_HEOPS_BSSCOLORDISABLE_SET(he_ops, value) WMI_SET_BITS(he_ops, 30, 1, value)
+#define WMI_HEOPS_BSSCOLORDISABLE_GET_D2(he_ops) WMI_GET_BITS(he_ops, 30, 1)
+#define WMI_HEOPS_BSSCOLORDISABLE_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 30, 1, value)
/**--- HEOPS_DUALBEACON: DO NOT USE - DEPRECATED ---*/
/* When set to 1 HE AP transmits beacons using two PHY formats,
* one in non-HE format and other in an HE_EXT_SU PHY format
*/
-#define WMI_HEOPS_DUALBEACON_GET(he_ops) (0)
-#define WMI_HEOPS_DUALBEACON_SET(he_ops, value) {;}
+#define WMI_HEOPS_DUALBEACON_GET_D2(he_ops) (0)
+#define WMI_HEOPS_DUALBEACON_SET_D2(he_ops, value) {;}
#define WMI_MAX_HECAP_PHY_SIZE (3)
/* Dual Band both 2.4 GHz and 5 GHz Supported */
-#define WMI_HECAP_PHY_DB_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 0, 1)
-#define WMI_HECAP_PHY_DB_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 0, 1, value)
+#define WMI_HECAP_PHY_DB_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 0, 1)
+#define WMI_HECAP_PHY_DB_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 0, 1, value)
/*
* B0: Indicates STA support 40 MHz channel width in 2.4 GHz
@@ -7082,8 +8587,8 @@
* MHz channel width in 5 GHz. Otherwise Reserved.
* B6: Reserved
*/
-#define WMI_HECAP_PHY_CBW_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 1, 7)
-#define WMI_HECAP_PHY_CBW_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 1, 7, value)
+#define WMI_HECAP_PHY_CBW_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 1, 7)
+#define WMI_HECAP_PHY_CBW_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 1, 7, value)
/*
* B0: Indicates STA supports reception of preamble puncturing in 80 MHz,
@@ -7098,59 +8603,59 @@
* or 80+80 MHz, where in the primary 80 MHz of the preamble, the
* primary 40 MHz is present
*/
-#define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 8, 4)
-#define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 8, 4, value)
+#define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 8, 4)
+#define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 8, 4, value)
/* Indicates transmitting STA is a Class A (1) or a Class B (0) device */
-#define WMI_HECAP_PHY_COD_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 12, 1)
-#define WMI_HECAP_PHY_COD_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 12, 1, value)
+#define WMI_HECAP_PHY_COD_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 12, 1)
+#define WMI_HECAP_PHY_COD_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 12, 1, value)
/* Indicates support of transmission and reception of LDPC encoded packets */
-#define WMI_HECAP_PHY_LDPC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 13, 1)
-#define WMI_HECAP_PHY_LDPC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 13, 1, value)
+#define WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 13, 1)
+#define WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 13, 1, value)
/* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LDPC instead */
-#define WMI_HECAP_PHY_TXLDPC_GET(he_cap_phy) WMI_HECAP_PHY_LDPC_GET(he_cap_phy)
-#define WMI_HECAP_PHY_TXLDPC_SET(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET(he_cap_phy, value)
+#define WMI_HECAP_PHY_TXLDPC_GET_D2(he_cap_phy) WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy)
+#define WMI_HECAP_PHY_TXLDPC_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value)
/* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LDPC instead */
-#define WMI_HECAP_PHY_RXLDPC_GET(he_cap_phy) WMI_HECAP_PHY_LDPC_GET(he_cap_phy)
-#define WMI_HECAP_PHY_RXLDPC_SET(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET(he_cap_phy, value)
+#define WMI_HECAP_PHY_RXLDPC_GET_D2(he_cap_phy) WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy)
+#define WMI_HECAP_PHY_RXLDPC_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value)
/*
* B0: Indicates support of reception of 1x LTF and 0.8us guard interval duration for HE SU PPDUs.
*/
-#define WMI_HECAP_PHY_LTFGIFORHE_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 14, 1)
-#define WMI_HECAP_PHY_LTFGIFORHE_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 14, 1, value)
+#define WMI_HECAP_PHY_LTFGIFORHE_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 14, 1)
+#define WMI_HECAP_PHY_LTFGIFORHE_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 14, 1, value)
/*
* When the Doppler Rx subfield is 1, indicates the maximum number of space-
* time streams supported for reception when midamble is used in the Data field.
*/
-#define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 15, 2)
-#define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 15, 2, value)
+#define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 15, 2)
+#define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 15, 2, value)
/*
* B0: For a transmitting STA acting as beamformee, it indicates support of
* NDP reception using 4x LTF and 3.2 us guard interval duration
*/
-#define WMI_HECAP_PHY_LTFGIFORNDP_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 17, 1)
-#define WMI_HECAP_PHY_LTFGIFORNDP_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 17, 1, value)
+#define WMI_HECAP_PHY_LTFGIFORNDP_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 17, 1)
+#define WMI_HECAP_PHY_LTFGIFORNDP_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 17, 1, value)
/* indicates support for the transmission of HE PPDUs using STBC with one spatial stream for <= 80MHz Tx*/
-#define WMI_HECAP_PHY_TXSTBC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 18, 1)
-#define WMI_HECAP_PHY_TXSTBC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 18, 1, value)
+#define WMI_HECAP_PHY_TXSTBC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 18, 1)
+#define WMI_HECAP_PHY_TXSTBC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 18, 1, value)
/* indicates support for the reception of HE PPDUs using STBC with one spatial stream for <= 80MHz Tx*/
-#define WMI_HECAP_PHY_RXSTBC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 19, 1)
-#define WMI_HECAP_PHY_RXSTBC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 19, 1, value)
+#define WMI_HECAP_PHY_RXSTBC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 19, 1)
+#define WMI_HECAP_PHY_RXSTBC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 19, 1, value)
/* indicates transmitting STA supports transmitting HE PPDUs with Doppler procedure */
-#define WMI_HECAP_PHY_TXDOPPLER_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 20, 1)
-#define WMI_HECAP_PHY_TXDOPPLER_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 20, 1, value)
+#define WMI_HECAP_PHY_TXDOPPLER_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 20, 1)
+#define WMI_HECAP_PHY_TXDOPPLER_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 20, 1, value)
/* indicates transmitting STA supports receiving HE PPDUs with Doppler procedure */
-#define WMI_HECAP_PHY_RXDOPPLER_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 21, 1)
-#define WMI_HECAP_PHY_RXDOPPLER_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 21, 1, value)
+#define WMI_HECAP_PHY_RXDOPPLER_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 21, 1)
+#define WMI_HECAP_PHY_RXDOPPLER_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 21, 1, value)
/*
* If the transmitting STA is an AP:
@@ -7160,8 +8665,8 @@
* indicates STA supports of transmission of full bandwidth UL MU-MIMO
* transmission.
*/
-#define WMI_HECAP_PHY_UL_MU_MIMO_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 22, 1)
-#define WMI_HECAP_PHY_UL_MU_MIMO_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 22, 1, value)
+#define WMI_HECAP_PHY_UL_MU_MIMO_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 22, 1)
+#define WMI_HECAP_PHY_UL_MU_MIMO_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 22, 1, value)
/*
* If the transmitting STA is an AP:
@@ -7171,8 +8676,8 @@
* indicates STA supports of transmission of UL MU-MIMO transmission on an
* RU in an HE MU PPDU where the RU does not span the entire PPDU bandwidth.
*/
-#define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 23, 1)
-#define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 23, 1, value)
+#define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 23, 1)
+#define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 23, 1, value)
/* Tx DCM
* B0:B1
@@ -7184,8 +8689,8 @@
* 0: 1 spatial stream
* 1: 2 spatial streams
*/
-#define WMI_HECAP_PHY_DCMTX_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 24, 3)
-#define WMI_HECAP_PHY_DCMTX_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 24, 3, value)
+#define WMI_HECAP_PHY_DCMTX_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 24, 3)
+#define WMI_HECAP_PHY_DCMTX_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 24, 3, value)
/* Rx DCM
* B0:B1
@@ -7197,36 +8702,36 @@
* 0: 1 spatial stream
* 1: 2 spatial streams
*/
-#define WMI_HECAP_PHY_DCMRX_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 27, 3)
-#define WMI_HECAP_PHY_DCMRX_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 27, 3, value)
+#define WMI_HECAP_PHY_DCMRX_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 27, 3)
+#define WMI_HECAP_PHY_DCMRX_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 27, 3, value)
/*
* Indicates that the STA supports the reception of an HE MU PPDU payload
* over full bandwidth and partial bandwidth (106-tone RU within 20 MHz).
*/
-#define WMI_HECAP_PHY_ULHEMU_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 30, 1)
-#define WMI_HECAP_PHY_ULHEMU_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 30, 1, value)
+#define WMI_HECAP_PHY_ULHEMU_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 30, 1)
+#define WMI_HECAP_PHY_ULHEMU_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 30, 1, value)
/* Indicates support for operation as an SU beamformer */
-#define WMI_HECAP_PHY_SUBFMR_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 31, 1)
-#define WMI_HECAP_PHY_SUBFMR_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 31, 1, value)
+#define WMI_HECAP_PHY_SUBFMR_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 31, 1)
+#define WMI_HECAP_PHY_SUBFMR_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 31, 1, value)
/* Indicates support for operation as an SU beamformee */
-#define WMI_HECAP_PHY_SUBFME_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 0, 1)
-#define WMI_HECAP_PHY_SUBFME_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 0, 1, value)
+#define WMI_HECAP_PHY_SUBFME_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 0, 1)
+#define WMI_HECAP_PHY_SUBFME_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 0, 1, value)
/* Indicates support for operation as an MU Beamformer */
-#define WMI_HECAP_PHY_MUBFMR_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 1, 1)
-#define WMI_HECAP_PHY_MUBFMR_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 1, 1, value)
+#define WMI_HECAP_PHY_MUBFMR_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 1, 1)
+#define WMI_HECAP_PHY_MUBFMR_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 1, 1, value)
/*
* Num STS -1 for <= 80MHz (min val 3)
* The maximum number of space-time streams minus 1 that the STA can
* receive in an HE NDP
*/
-#define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 2, 3)
-#define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 2, 3, value)
+#define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 2, 3)
+#define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 2, 3, value)
/*
@@ -7234,8 +8739,8 @@
* The maximum number of space-time streams minus 1 that the STA can
* receive in an HE NDP
*/
-#define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3)
-#define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value)
+#define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3)
+#define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value)
/*
* Number Of Sounding Dimensions For <= 80 MHz
@@ -7243,8 +8748,8 @@
* TXVECTOR parameter NUM_STS minus 1.
* Otherwise, reserved.
*/
-#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3)
-#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value)
+#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3)
+#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value)
/*
* Number Of Sounding Dimensions For > 80 MHz
@@ -7252,40 +8757,40 @@
* TXVECTOR parameter NUM_STS minus 1.
* Otherwise, reserved.
*/
-#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 11, 3)
-#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 11, 3, value)
+#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 11, 3)
+#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 11, 3, value)
/*
* Indicates if the HE beamformee is capable of feedback with tone
* grouping of 16 in the HE Compressed Beamforming Report field for
* a SU-type feedback.
*/
-#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 14, 1)
-#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 14, 1, value)
+#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 14, 1)
+#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 14, 1, value)
/*
* Indicates if the HE beamformee is capable of feedback with tone
* grouping of 16 in the HE Compressed Beamforming Report field for
* a MU-type feedback.
*/
-#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 15, 1)
-#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 15, 1, value)
+#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 15, 1)
+#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 15, 1, value)
/*
* Indicates if HE beamformee is capable of feedback with codebook
* size {4, 2} in the HECompressed Beamforming Report field for
* a SU-type feedback.
*/
-#define WMI_HECAP_PHY_CODBK42SU_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 16, 1)
-#define WMI_HECAP_PHY_CODBK42SU_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 16, 1, value)
+#define WMI_HECAP_PHY_CODBK42SU_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 16, 1)
+#define WMI_HECAP_PHY_CODBK42SU_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 16, 1, value)
/*
* Indicates if HE beamformee is capable of feedback with codebook
* size {7, 5} in the HE Compressed Beamforming Report field for
* a MU-type feedback.
*/
-#define WMI_HECAP_PHY_CODBK75MU_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 17, 1)
-#define WMI_HECAP_PHY_CODBK75MU_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 17, 1, value)
+#define WMI_HECAP_PHY_CODBK75MU_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 17, 1)
+#define WMI_HECAP_PHY_CODBK75MU_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 17, 1, value)
/*
* Beamforming Feedback With Trigger Frame
@@ -7298,73 +8803,73 @@
* B1: indicates support of transmission of MU-Type partial(1) bandwidth feedback
* B2: indicates support of transmission of CQI-Onlypartial (1)and full bandwidth feedback
*/
-#define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 18, 3)
-#define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 18, 3, value)
+#define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 18, 3)
+#define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 18, 3, value)
/* Indicates the support of transmission and reception of an HE extended range SU PPDU payload transmitted
* over the right 106-tone RU or partial BW ER
*/
-#define WMI_HECAP_PHY_HEERSU_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 21, 1)
-#define WMI_HECAP_PHY_HEERSU_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 21, 1, value)
+#define WMI_HECAP_PHY_HEERSU_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 21, 1)
+#define WMI_HECAP_PHY_HEERSU_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 21, 1, value)
/* Indicates that the non-AP STA supports reception of a DL MU-MIMO transmission on an RU in an HE MU PPDU
* where the RU does not span the entire PPDU bandwidth.
*/
-#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 22, 1)
-#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 22, 1, value)
+#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 22, 1)
+#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 22, 1, value)
/* Indicates whether or not the PPE Threshold field is present */
-#define WMI_HECAP_PHY_PETHRESPRESENT_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 23, 1)
-#define WMI_HECAP_PHY_PETHRESPRESENT_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 23, 1, value)
+#define WMI_HECAP_PHY_PETHRESPRESENT_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 23, 1)
+#define WMI_HECAP_PHY_PETHRESPRESENT_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 23, 1, value)
/* Indicates that the STA supports SRP-based SR operation */
-#define WMI_HECAP_PHY_SRPSPRESENT_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 24, 1)
-#define WMI_HECAP_PHY_SRPPRESENT_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 24, 1, value)
+#define WMI_HECAP_PHY_SRPSPRESENT_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 24, 1)
+#define WMI_HECAP_PHY_SRPPRESENT_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 24, 1, value)
/* Indicates that the STA supports a power boost factor ar for the r-th RU in the range [0.5, 2] */
-#define WMI_HECAP_PHY_PWRBOOSTAR_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 25, 1)
-#define WMI_HECAP_PHY_PWRBOOSTAR_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 25, 1, value)
+#define WMI_HECAP_PHY_PWRBOOSTAR_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 25, 1)
+#define WMI_HECAP_PHY_PWRBOOSTAR_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 25, 1, value)
/* Indicates support for the reception of 4x LTF and 0.8us guard interval duration for HE SU PPDUs. */
-#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 26, 1)
-#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 26, 1, value)
+#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 26, 1)
+#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 26, 1, value)
/* For a transmitting STA acting as a beamformee, it indicates the maximum Nc for beamforming sounding
* feedback supported If SU beamformee capable, then set to the maximum Nc for beamforming sounding feedback
* minus 1. Otherwise, reserved.
*/
-#define WMI_HECAP_PHY_MAXNC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 27, 3)
-#define WMI_HECAP_PHY_MAXNC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 27, 3, value)
+#define WMI_HECAP_PHY_MAXNC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 27, 3)
+#define WMI_HECAP_PHY_MAXNC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 27, 3, value)
/* Indicates support for the transmission of an HE PPDU that has a bandwidth greater than 80 MHz and is using
* STBC with one spatial stream
*/
-#define WMI_HECAP_PHY_STBCTXGT80_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 30, 1)
-#define WMI_HECAP_PHY_STBCTXGT80_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 30, 1, value)
+#define WMI_HECAP_PHY_STBCTXGT80_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 30, 1)
+#define WMI_HECAP_PHY_STBCTXGT80_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 30, 1, value)
/* Indicates support for the reception of an HE PPDU that has a bandwidth greater than 80 MHz and is using
* STBC with one spatial stream
*/
-#define WMI_HECAP_PHY_STBCRXGT80_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 31, 1)
-#define WMI_HECAP_PHY_STBCRXGT80_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 31, 1, value)
+#define WMI_HECAP_PHY_STBCRXGT80_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 31, 1)
+#define WMI_HECAP_PHY_STBCRXGT80_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 31, 1, value)
/* Indicates support for the reception of an HE ER SU PPDU with 4x LTF and 0.8 us guard interval duration */
-#define WMI_HECAP_PHY_ERSU4X800NSECGI_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 0, 1)
-#define WMI_HECAP_PHY_ERSU4X800NSECGI_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 0, 1, value)
+#define WMI_HECAP_PHY_ERSU4X800NSECGI_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 0, 1)
+#define WMI_HECAP_PHY_ERSU4X800NSECGI_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 0, 1, value)
/*
* Indicates support of 26-, 52-, and 106-tone mapping for a 20 MHz operating non-AP HE STA that is the
* receiver of a 40 MHz HE MU PPDU in 2.4 GHz band, or the transmitter of a 40 MHz HE TB PPDU in 2.4GHz band.
*/
-#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 1, 1)
-#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 1, 1, value)
+#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 1, 1)
+#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 1, 1, value)
/*
* Indicates support of 26-, 52-, and 106-tone mapping for a 20 MHz operating non-AP HE STA that is the
* receiver of a 80+80 MHz or a 160 MHz HE MU PPDU, or the transmitter of a 80+80 MHz or 160 MHz HE TB PPDU.
*/
-#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 2, 1)
-#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 2, 1, value)
+#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 2, 1)
+#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 2, 1, value)
/*
* Indicates supports of 160 MHz OFDMA for a non-AP HE STA that sets bit B1 of Channel Width Set to 1, and
@@ -7372,32 +8877,32 @@
* bit is applicable while receiving a 80+80 MHz or a 160 MHz HE MU PPDU, or transmitting a 80+80 MHz or a
* 160 MHz HE TB PPDU.
*/
-#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 3, 1)
-#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 3, 1, value)
+#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 3, 1)
+#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 3, 1, value)
/* Indicates support for the reception of an HE ER SU PPDU with 1x LTF and 0.8 us guard interval duration */
-#define WMI_HECAP_PHY_ERSU1X800NSECGI_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 4, 1)
-#define WMI_HECAP_PHY_ERSU1X800NSECGI_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 4, 1, value)
+#define WMI_HECAP_PHY_ERSU1X800NSECGI_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 4, 1)
+#define WMI_HECAP_PHY_ERSU1X800NSECGI_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 4, 1, value)
/*
* When the Doppler Rx subfield is 1, indicates support for receiving midambles with 2x HE-LTF, 1x HE-LTF
* in HE SU PPDU if the HE SU PPDU With 1x HE-LTF And 0.8 s GI subfield is set to 1, and 1x HE-LTF in
* HE ER SU PPDU if the HE ER SU PPDU With 1x HELTF And 0.8 s GI subfield is set to 1.
*/
-#define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 5, 1)
-#define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 5, 1, value)
+#define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 5, 1)
+#define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 5, 1, value)
/*HTC + HE Support Set to 1 if STA supports reception of HE Variant HT control Field*/
-#define WMI_HECAP_MAC_HECTRL_GET(he_cap) WMI_GET_BITS(he_cap, 0, 1)
-#define WMI_HECAP_MAC_HECTRL_SET(he_cap, value) WMI_SET_BITS(he_cap, 0, 1, value)
+#define WMI_HECAP_MAC_HECTRL_GET_D2(he_cap) WMI_GET_BITS(he_cap, 0, 1)
+#define WMI_HECAP_MAC_HECTRL_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 0, 1, value)
/* set to 1 to for TWT Requestor support*/
-#define WMI_HECAP_MAC_TWTREQ_GET(he_cap) WMI_GET_BITS(he_cap, 1, 1)
-#define WMI_HECAP_MAC_TWTREQ_SET(he_cap, value) WMI_SET_BITS(he_cap, 1, 1, value)
+#define WMI_HECAP_MAC_TWTREQ_GET_D2(he_cap) WMI_GET_BITS(he_cap, 1, 1)
+#define WMI_HECAP_MAC_TWTREQ_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 1, 1, value)
/* set to 1 to for TWT Responder support*/
-#define WMI_HECAP_MAC_TWTRSP_GET(he_cap) WMI_GET_BITS(he_cap, 2, 1)
-#define WMI_HECAP_MAC_TWTRSP_SET(he_cap, value) WMI_SET_BITS(he_cap, 2, 1, value)
+#define WMI_HECAP_MAC_TWTRSP_GET_D2(he_cap) WMI_GET_BITS(he_cap, 2, 1)
+#define WMI_HECAP_MAC_TWTRSP_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 2, 1, value)
/* Level of frag support
Set to 0 for no support for dynamic fragmentation.
@@ -7408,78 +8913,78 @@
dynamic fragments for each MSDU within an AMPDU or multi-TID AMPDU and up to one dynamic fragment
for each MMPDU in a multi-TID A-MPDU that is not a Single MPDU
*/
-#define WMI_HECAP_MAC_HEFRAG_GET(he_cap) WMI_GET_BITS(he_cap, 3, 2)
-#define WMI_HECAP_MAC_HEFRAG_SET(he_cap, value) WMI_SET_BITS(he_cap, 3, 2, value)
+#define WMI_HECAP_MAC_HEFRAG_GET_D2(he_cap) WMI_GET_BITS(he_cap, 3, 2)
+#define WMI_HECAP_MAC_HEFRAG_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 3, 2, value)
/* The maximum number of fragmented MSDUs, Nmax,defined by this field is Nmax = 2 Maximum Number Of FMPDUs*/
-#define WMI_HECAP_MAC_MAXFRAGMSDU_GET(he_cap) WMI_GET_BITS(he_cap, 5, 3)
-#define WMI_HECAP_MAC_MAXFRAGMSDU_SET(he_cap, value) WMI_SET_BITS(he_cap, 5, 3, value)
+#define WMI_HECAP_MAC_MAXFRAGMSDU_GET_D2(he_cap) WMI_GET_BITS(he_cap, 5, 3)
+#define WMI_HECAP_MAC_MAXFRAGMSDU_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 5, 3, value)
/* 0 = no restriction on the minimum payload , 1 = 128 octets min, 2 = 256 octets min, 3 = 512 octets min */
-#define WMI_HECAP_MAC_MINFRAGSZ_GET(he_cap) WMI_GET_BITS(he_cap, 8, 2)
-#define WMI_HECAP_MAC_MINFRAGSZ_SET(he_cap, value) WMI_SET_BITS(he_cap, 8, 2, value)
+#define WMI_HECAP_MAC_MINFRAGSZ_GET_D2(he_cap) WMI_GET_BITS(he_cap, 8, 2)
+#define WMI_HECAP_MAC_MINFRAGSZ_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 8, 2, value)
/*0 = no additional processing time, 1 = 8us,2 = 16us */
-#define WMI_HECAP_MAC_TRIGPADDUR_GET(he_cap) WMI_GET_BITS(he_cap, 10, 2)
-#define WMI_HECAP_MAC_TRIGPADDUR_SET(he_cap, value) WMI_SET_BITS(he_cap, 10, 2, value)
+#define WMI_HECAP_MAC_TRIGPADDUR_GET_D2(he_cap) WMI_GET_BITS(he_cap, 10, 2)
+#define WMI_HECAP_MAC_TRIGPADDUR_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 10, 2, value)
/*number of TIDs minus 1 of QoS Data frames that HE STA can aggregate in multi-TID AMPDU*/
-#define WMI_HECAP_MAC_MTID_GET(he_cap) WMI_GET_BITS(he_cap, 12, 3)
-#define WMI_HECAP_MAC_MTID_SET(he_cap, value) WMI_SET_BITS(he_cap, 12, 3, value)
+#define WMI_HECAP_MAC_MTID_GET_D2(he_cap) WMI_GET_BITS(he_cap, 12, 3)
+#define WMI_HECAP_MAC_MTID_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 12, 3, value)
/*
* Indicates support by a STA to receive an ack-enabled A-MPDU in which an A-MSDU is carried in
* a QoS Data frame for which no block ack agreement exists.
*/
-#define WMI_HECAP_MAC_AMSDUINAMPDU_GET(he_cap) WMI_GET_BITS(he_cap, 15, 1)
-#define WMI_HECAP_MAC_AMSDUINAMPDU_SET(he_cap, value) WMI_SET_BITS(he_cap, 15, 1, value)
+#define WMI_HECAP_MAC_AMSDUINAMPDU_GET_D2(he_cap) WMI_GET_BITS(he_cap, 15, 1)
+#define WMI_HECAP_MAC_AMSDUINAMPDU_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 15, 1, value)
/*--- HECAP_MAC_HELKAD: DO NOT USE - DEPRECATED ---*/
/*0=No Feedback,2=Unsolicited,3=Both*/
-#define WMI_HECAP_MAC_HELKAD_GET(he_cap) (0)
-#define WMI_HECAP_MAC_HELKAD_SET(he_cap, value) {;}
+#define WMI_HECAP_MAC_HELKAD_GET_D2(he_cap) (0)
+#define WMI_HECAP_MAC_HELKAD_SET_D2(he_cap, value) {;}
/* bit 16 reserved. */
/*Set to 1 for reception of AllAck support*/
-#define WMI_HECAP_MAC_AACK_GET(he_cap) WMI_GET_BITS(he_cap, 17, 1)
-#define WMI_HECAP_MAC_AACK_SET(he_cap, value) WMI_SET_BITS(he_cap, 17, 1, value)
+#define WMI_HECAP_MAC_AACK_GET_D2(he_cap) WMI_GET_BITS(he_cap, 17, 1)
+#define WMI_HECAP_MAC_AACK_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 17, 1, value)
/*Set to 1 if the STA supports reception of the UL MU Response Scheduling A-Control field*/
-#define WMI_HECAP_MAC_ULMURSP_GET(he_cap) WMI_GET_BITS(he_cap, 18, 1)
-#define WMI_HECAP_MAC_ULMURSP_SET(he_cap, value) WMI_SET_BITS(he_cap, 18, 1, value)
+#define WMI_HECAP_MAC_ULMURSP_GET_D2(he_cap) WMI_GET_BITS(he_cap, 18, 1)
+#define WMI_HECAP_MAC_ULMURSP_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 18, 1, value)
/*Set to 1 if the STA supports the BSR A-Control field functionality.*/
-#define WMI_HECAP_MAC_BSR_GET(he_cap) WMI_GET_BITS(he_cap, 19, 1)
-#define WMI_HECAP_MAC_BSR_SET(he_cap, value) WMI_SET_BITS(he_cap, 19, 1, value)
+#define WMI_HECAP_MAC_BSR_GET_D2(he_cap) WMI_GET_BITS(he_cap, 19, 1)
+#define WMI_HECAP_MAC_BSR_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 19, 1, value)
/*Set to 1 when the STA supports broadcast TWT functionality.*/
-#define WMI_HECAP_MAC_BCSTTWT_GET(he_cap) WMI_GET_BITS(he_cap, 20, 1)
-#define WMI_HECAP_MAC_BCSTTWT_SET(he_cap, value) WMI_SET_BITS(he_cap, 20, 1, value)
+#define WMI_HECAP_MAC_BCSTTWT_GET_D2(he_cap) WMI_GET_BITS(he_cap, 20, 1)
+#define WMI_HECAP_MAC_BCSTTWT_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 20, 1, value)
/*Set to 1 if STA supports rx of Multi-STA BA that has 32-bit Block Ack Bitmap*/
-#define WMI_HECAP_MAC_32BITBA_GET(he_cap) WMI_GET_BITS(he_cap, 21, 1)
-#define WMI_HECAP_MAC_32BITBA_SET(he_cap, value) WMI_SET_BITS(he_cap, 21, 1, value)
+#define WMI_HECAP_MAC_32BITBA_GET_D2(he_cap) WMI_GET_BITS(he_cap, 21, 1)
+#define WMI_HECAP_MAC_32BITBA_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 21, 1, value)
/*Set to 1 if the STA supports MU cascading operation*/
-#define WMI_HECAP_MAC_MUCASCADE_GET(he_cap) WMI_GET_BITS(he_cap, 22, 1)
-#define WMI_HECAP_MAC_MUCASCADE_SET(he_cap, value) WMI_SET_BITS(he_cap, 22, 1, value)
+#define WMI_HECAP_MAC_MUCASCADE_GET_D2(he_cap) WMI_GET_BITS(he_cap, 22, 1)
+#define WMI_HECAP_MAC_MUCASCADE_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 22, 1, value)
/*Set to 1 when the STA supports reception of this multi-TID A-MPDU format*/
-#define WMI_HECAP_MAC_ACKMTIDAMPDU_GET(he_cap) WMI_GET_BITS(he_cap, 23, 1)
-#define WMI_HECAP_MAC_ACKMTIDAMPDU_SET(he_cap, value) WMI_SET_BITS(he_cap, 23, 1, value)
+#define WMI_HECAP_MAC_ACKMTIDAMPDU_GET_D2(he_cap) WMI_GET_BITS(he_cap, 23, 1)
+#define WMI_HECAP_MAC_ACKMTIDAMPDU_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 23, 1, value)
/*Set to 1 when the STA supports its reception*/
-#define WMI_HECAP_MAC_GROUPMSTABA_GET(he_cap) WMI_GET_BITS(he_cap, 24, 1)
-#define WMI_HECAP_MAC_GROUPMSTABA_SET(he_cap, value) WMI_SET_BITS(he_cap, 24, 1, value)
+#define WMI_HECAP_MAC_GROUPMSTABA_GET_D2(he_cap) WMI_GET_BITS(he_cap, 24, 1)
+#define WMI_HECAP_MAC_GROUPMSTABA_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 24, 1, value)
/*Set to 1 if the STA supports reception of the OMI A-Control field*/
-#define WMI_HECAP_MAC_OMI_GET(he_cap) WMI_GET_BITS(he_cap, 25, 1)
-#define WMI_HECAP_MAC_OMI_SET(he_cap, value) WMI_SET_BITS(he_cap, 25, 1, value)
+#define WMI_HECAP_MAC_OMI_GET_D2(he_cap) WMI_GET_BITS(he_cap, 25, 1)
+#define WMI_HECAP_MAC_OMI_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 25, 1, value)
/*1 if OFDMA Random Access Supported*/
-#define WMI_HECAP_MAC_OFDMARA_GET(he_cap) WMI_GET_BITS(he_cap, 26, 1)
-#define WMI_HECAP_MAC_OFDMARA_SET(he_cap, value) WMI_SET_BITS(he_cap, 26, 1, value)
+#define WMI_HECAP_MAC_OFDMARA_GET_D2(he_cap) WMI_GET_BITS(he_cap, 26, 1)
+#define WMI_HECAP_MAC_OFDMARA_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 26, 1, value)
/* Maximum AMPDU Length Exponent.
* If the HE STA includes a VHT Capabilities element, the Maximum A-MPDU Length Exponent subfield in
@@ -7487,131 +8992,148 @@
* Capabilities element indicate the maximum length of A-MPDU that the STA can Receive where EOF
* padding is not included in this limit.
*/
-#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET(he_cap) WMI_GET_BITS(he_cap, 27, 2)
-#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET(he_cap, value) WMI_SET_BITS(he_cap, 27, 2, value)
+#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET_D2(he_cap) WMI_GET_BITS(he_cap, 27, 2)
+#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 27, 2, value)
/*A-MSDU Fragmentation Support*/
-#define WMI_HECAP_MAC_AMSDUFRAG_GET(he_cap) WMI_GET_BITS(he_cap, 29, 1)
-#define WMI_HECAP_MAC_AMSDUFRAG_SET(he_cap, value) WMI_SET_BITS(he_cap, 29, 1, value)
+#define WMI_HECAP_MAC_AMSDUFRAG_GET_D2(he_cap) WMI_GET_BITS(he_cap, 29, 1)
+#define WMI_HECAP_MAC_AMSDUFRAG_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 29, 1, value)
/*Flexible TWT Schedule Support*/
-#define WMI_HECAP_MAC_FLEXTWT_GET(he_cap) WMI_GET_BITS(he_cap, 30, 1)
-#define WMI_HECAP_MAC_FLEXTWT_SET(he_cap, value) WMI_SET_BITS(he_cap, 30, 1, value)
+#define WMI_HECAP_MAC_FLEXTWT_GET_D2(he_cap) WMI_GET_BITS(he_cap, 30, 1)
+#define WMI_HECAP_MAC_FLEXTWT_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 30, 1, value)
/*Rx Control Frame to MultiBSS*/
-#define WMI_HECAP_MAC_MBSS_GET(he_cap) WMI_GET_BITS(he_cap, 31, 1)
-#define WMI_HECAP_MAC_MBSS_SET(he_cap, value) WMI_SET_BITS(he_cap, 31, 1, value)
+#define WMI_HECAP_MAC_MBSS_GET_D2(he_cap) WMI_GET_BITS(he_cap, 31, 1)
+#define WMI_HECAP_MAC_MBSS_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 31, 1, value)
/* BSRP A-MPDU Aggregation
* maintaining compatability since we dont support this now so not wasting memory
*/
-#define WMI_HECAP_MAC_BSRPAMPDU_GET(he_cap) (0)
-#define WMI_HECAP_MAC_BSRPAMPDU_SET(he_cap, value) {;}
+#define WMI_HECAP_MAC_BSRPAMPDU_GET_D2(he_cap) (0)
+#define WMI_HECAP_MAC_BSRPAMPDU_SET_D2(he_cap, value) {;}
/* Quiet Time Period (QTP) operation
* maintaining compatability since we dont support this now so not wasting memory
*/
-#define WMI_HECAP_MAC_QTP_GET(he_cap) (0)
-#define WMI_HECAP_MAC_QTP_SET(he_cap, value) {;}
+#define WMI_HECAP_MAC_QTP_GET_D2(he_cap) (0)
+#define WMI_HECAP_MAC_QTP_SET_D2(he_cap, value) {;}
/* support by an AP for receiving an (A-)MPDU that contains a BQR in the
* A-Control subfield and support by a non-AP STA for generating an (A-)MPDU
* that contains a BQR in the A-Control subfield
* maintaining compatability since we dont support this now so not wasting memory
*/
-#define WMI_HECAP_MAC_ABQR_GET(he_cap) (0)
-#define WMI_HECAP_MAC_ABQR_SET(he_cap, value) {;}
+#define WMI_HECAP_MAC_ABQR_GET_D2(he_cap) (0)
+#define WMI_HECAP_MAC_ABQR_SET_D2(he_cap, value) {;}
/*Indicates support by the STA for the role of SR Responder.*/
-#define WMI_HECAP_MAC_SRRESP_GET(he_cap) (0)
-#define WMI_HECAP_MAC_SRRESP_SET(he_cap, value) {;}
+#define WMI_HECAP_MAC_SRRESP_GET_D2(he_cap) (0)
+#define WMI_HECAP_MAC_SRRESP_SET_D2(he_cap, value) {;}
/* Indicates support for an AP to encode OPS information to TIM element of the FILS Discovery
* frames or TIM frames as described in AP operation for opportunistic power save.
* Indicates support for a non-AP STA to receive the opportunistic power save encoded TIM elements
*/
-#define WMI_HECAP_MAC_OPS_GET(he_cap) (0)
-#define WMI_HECAP_MAC_OPS_SET(he_cap, value) {;}
+#define WMI_HECAP_MAC_OPS_GET_D2(he_cap) (0)
+#define WMI_HECAP_MAC_OPS_SET_D2(he_cap, value) {;}
/* Indicates support for a non-AP STA to follow the NDP feedback report procedure and respond to
* the NDP Feedback Report Poll Trigger frame.
*/
-#define WMI_HECAP_MAC_NDPFDBKRPT_GET(he_cap) (0)
-#define WMI_HECAP_MAC_NDPFDBKRPT_SET(he_cap, value) {;}
+#define WMI_HECAP_MAC_NDPFDBKRPT_GET_D2(he_cap) (0)
+#define WMI_HECAP_MAC_NDPFDBKRPT_SET_D2(he_cap, value) {;}
/* BELOW MACROS ARE DEPRECATED Also we are not defining bits for capabilities
* beyond bit 31 we donot support as it adds additional dword to our struct which may be later
* removed by standard
*/
-#define WMI_HECAP_MAC_MBAHECTRL_GET(he_cap) (0) /* DO NOT USE - DEPRECATED*/
-#define WMI_HECAP_MAC_MBAHECTRL_SET(he_cap, value) {;} /* DO NOT USE - DEPRECATED*/
+#define WMI_HECAP_MAC_MBAHECTRL_GET_D2(he_cap) (0) /* DO NOT USE - DEPRECATED*/
+#define WMI_HECAP_MAC_MBAHECTRL_SET_D2(he_cap, value) {;} /* DO NOT USE - DEPRECATED*/
-#define WMI_HECAP_MAC_MURTS_GET(he_cap) (0) /* DO NOT USE - DEPRECATED*/
-#define WMI_HECAP_MAC_MURTS_SET(he_cap, value) {;} /* DO NOT USE - DEPRECATED*/
+#define WMI_HECAP_MAC_MURTS_GET_D2(he_cap) (0) /* DO NOT USE - DEPRECATED*/
+#define WMI_HECAP_MAC_MURTS_SET_D2(he_cap, value) {;} /* DO NOT USE - DEPRECATED*/
/*Deprecate use WMI_HECAP_PHY_PREAMBLEPUNCRX instead*/
-#define WMI_HECAP_PHY_CBMODE_GET(he_cap_phy) WMI_HECAP_PHY_CBMODE_GET(he_cap_phy)
-#define WMI_HECAP_PHY_CBMODE_SET(he_cap_phy, value) WMI_HECAP_PHY_CBMODE_SET(he_cap_phy, value)
+#define WMI_HECAP_PHY_CBMODE_GET_D2(he_cap_phy) WMI_HECAP_PHY_CBMODE_GET_D2(he_cap_phy)
+#define WMI_HECAP_PHY_CBMODE_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_CBMODE_SET_D2(he_cap_phy, value)
/* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LTFGIFORHE_GET instead */
-#define WMI_HECAP_PHY_OLTF_GET(he_cap_phy) WMI_HECAP_PHY_LTFGIFORHE_GET(he_cap_phy)
-#define WMI_HECAP_PHY_OLTF_SET(he_cap_phy, value) WMI_HECAP_PHY_LTFGIFORHE_SET(he_cap_phy, value)
+#define WMI_HECAP_PHY_OLTF_GET_D2(he_cap_phy) WMI_HECAP_PHY_LTFGIFORHE_GET_D2(he_cap_phy)
+#define WMI_HECAP_PHY_OLTF_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LTFGIFORHE_SET_D2(he_cap_phy, value)
/*DEPRECATED - USE WMI_HECAP_PHY_BFMENLTSGT80MHZ*/
-#define WMI_HECAP_PHY_SUBFMESTS_GET(he_cap_phy) WMI_HECAP_PHY_BFMESTSLT80MHZ_GET(he_cap_phy)
-#define WMI_HECAP_PHY_SUBFMESTS_SET(he_cap_phy, value) WMI_HECAP_PHY_BFMESTSLT80MHZ_SET(he_cap_phy, value)
+#define WMI_HECAP_PHY_SUBFMESTS_GET_D2(he_cap_phy) WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D2(he_cap_phy)
+#define WMI_HECAP_PHY_SUBFMESTS_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D2(he_cap_phy, value)
/*DEPRECATED - use WMI_HECAP_PHY_PETHRESPRESENT**/
-#define WMI_HECAP_PHY_PADDING_GET(he_cap_phy) WMI_HECAP_PHY_PETHRESPRESENT_GET(he_cap_phy)
-#define WMI_HECAP_PHY_PADDING_SET(he_cap_phy, value) WMI_HECAP_PHY_PETHRESPRESENT_SET(he_cap_phy, value)
+#define WMI_HECAP_PHY_PADDING_GET_D2(he_cap_phy) WMI_HECAP_PHY_PETHRESPRESENT_GET_D2(he_cap_phy)
+#define WMI_HECAP_PHY_PADDING_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_PETHRESPRESENT_SET_D2(he_cap_phy, value)
/**DO NOT USE - DEPRECATED*/
-#define WMI_HECAP_PHY_DLOFMAMUMIMO_GET(he_cap_phy) (0)
-#define WMI_HECAP_PHY_DLOFDMAMUMIO_SET(he_cap_phy, value) {;}
+#define WMI_HECAP_PHY_DLOFMAMUMIMO_GET_D2(he_cap_phy) (0)
+#define WMI_HECAP_PHY_DLOFDMAMUMIO_SET_D2(he_cap_phy, value) {;}
/*DO NOT USE - DEPRECATED**/
-#define WMI_HECAP_PHY_32GI_GET(he_cap_phy) (0)
-#define WMI_HECAP_PHY_32GI_SET(he_cap_phy, value) {;}
+#define WMI_HECAP_PHY_32GI_GET_D2(he_cap_phy) (0)
+#define WMI_HECAP_PHY_32GI_SET_D2(he_cap_phy, value) {;}
/*DO NOT USE - DEPRECATED**/
-#define WMI_HECAP_PHY_NOSUNDIMENS_GET(he_cap_phy) (0)
-#define WMI_HECAP_PHY_NOSUNDIMENS_SET(he_cap_phy, value) {;}
+#define WMI_HECAP_PHY_NOSUNDIMENS_GET_D2(he_cap_phy) (0)
+#define WMI_HECAP_PHY_NOSUNDIMENS_SET_D2(he_cap_phy, value) {;}
/*DO NOT USE - DEPRECATED**/
-#define WMI_HECAP_PHY_40MHZNSS_GET(he_cap_phy)(0)
-#define WMI_HECAP_PHY_40MHZNSS_SET(he_cap_phy, value) {;}
+#define WMI_HECAP_PHY_40MHZNSS_GET_D2(he_cap_phy)(0)
+#define WMI_HECAP_PHY_40MHZNSS_SET_D2(he_cap_phy, value) {;}
/* START TEMPORARY WORKAROUND -
* Leave legacy names as aliases for new names, until all references to the
* legacy names have been removed.
*/
-#define WMI_HECAP_PHY_ULOFDMA_GET WMI_HECAP_PHY_ULMUMIMOOFDMA_GET
-#define WMI_HECAP_PHY_ULOFDMA_SET WMI_HECAP_PHY_ULMUMIMOOFDMA_SET
+#define WMI_HECAP_PHY_ULOFDMA_GET_D2 WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D2
+#define WMI_HECAP_PHY_ULOFDMA_SET_D2 WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D2
/* END TEMPORARY WORKAROUND */
/* DEPRECATED - use WMI_HECAP_PHY_DCMRX or WMI_HECAP_PHY_DCMTX */
-#define WMI_HECAP_PHY_DCM_GET(he_cap_phy) WMI_HECAP_PHY_DCMRX_GET(he_cap_phy)
-#define WMI_HECAP_PHY_DCM_SET(he_cap_phy, value) WMI_HECAP_PHY_DCMRX_SET(he_cap_phy, value)
+#define WMI_HECAP_PHY_DCM_GET_D2(he_cap_phy) WMI_HECAP_PHY_DCMRX_GET_D2(he_cap_phy)
+#define WMI_HECAP_PHY_DCM_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_DCMRX_SET_D2(he_cap_phy, value)
/*
* The maximum value for NSTS-1<=80MHz,(min val 3)total that can be sent
* to the STA in a DL MU-MIMO transmission on full or partial bandwidth
*/
-#define WMI_HECAP_PHY_NSTSLT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3)
-#define WMI_HECAP_PHY_NSTSLT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value)
+#define WMI_HECAP_PHY_NSTSLT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3)
+#define WMI_HECAP_PHY_NSTSLT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value)
/*
* The maximum value for NSTS-1 > 80MHz (min val 3) total that can be sent
* to the STA in a DL MU-MIMO transmission on full or partial bandwidth
*/
-#define WMI_HECAP_PHY_NSTSGT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3)
-#define WMI_HECAP_PHY_NSTSGT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value)
+#define WMI_HECAP_PHY_NSTSGT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3)
+#define WMI_HECAP_PHY_NSTSGT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value)
+/*
+ * Indicates the spatial multiplexing power save mode after receiving a
+ * Trigger frame that is in operation immediately after (re)association.
+ */
+#define WMI_HECAP_MAC_DYNSMPWRSAVE_GET_D2(he_cap2) (0)
+#define WMI_HECAP_MAC_DYNSMPWRSAVE_SET_D2(he_cap2, value) {;}
+
+/* Indicates support for Punctured Sounding */
+#define WMI_HECAP_MAC_PUNCSOUNDING_GET_D2(he_cap2) (0)
+#define WMI_HECAP_MAC_PUNCSOUNDING_SET_D2(he_cap2, value) {;}
+
+/*
+ * Indicates support for receiving a Trigger frame in an HT PPDU and
+ * receiving a Trigger frame in a VHT PPDU
+ */
+#define WMI_HECAP_MAC_HTVHTTRIGRX_GET_D2(he_cap2) (0)
+#define WMI_HECAP_MAC_HTVHTTRIGRX_SET_D2(he_cap2, value) {;}
#define WMI_GET_HW_RATECODE_PREAM_V1(_rcode) (((_rcode) >> 8) & 0x7)
#define WMI_GET_HW_RATECODE_NSS_V1(_rcode) (((_rcode) >> 5) & 0x7)
@@ -8336,6 +9858,187 @@
*/
WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_INITIATOR_RANDOM_MAC, /* 0x81 */
+ /**
+ * For each AC, configure how many tx retries to send without RTS
+ * before enabling RTS
+ * bits 0:7 :BE
+ * bits 8:15 :BK
+ * bits 16:23 :VI
+ * bits 24:31 :VO
+ * A value of 0 in specific AC means default configuration for that AC.
+ */
+ WMI_VDEV_PARAM_TX_RETRIES_BEFORE_RTS_PER_AC, /* 0x82 */
+
+ /**
+ * Parameter to enable/disable AMSDU aggregation size auto-selection logic.
+ * We have logic where AMSDU aggregation size is dynamically decided
+ * based on MCS. That logic is enabled by default.
+ * For certain tests, we need a method to disable this optimization,
+ * and base AMSDU size only on the peer's capability rather than our logic.
+ * A value of 0 means disable internal optimization,
+ * 1 means enable internal optimzation.
+ */
+ WMI_VDEV_PARAM_AMSDU_AGGREGATION_SIZE_OPTIMIZATION, /* 0x83 */
+
+ /**
+ * In RAW mode, FW will not know whether the encryption is enabled
+ * on this vdev or not.
+ * Because of this, FW will not program the right info into the
+ * RawNwifi TLV resulting in the connection failure in RAW mode.
+ * So to program the right info, FW should know whether the security
+ * is enabled on this VDEV.
+ * Host will send this VDEV param command (With Value = 1) in case of
+ * RAW secure mode.
+ */
+ WMI_VDEV_PARAM_RAW_IS_ENCRYPTED, /* 0x84 */
+
+ /**
+ * Dynamically enable/disable green tx (GTX) on supported rates.
+ * Host will set this param to 1 for enabling GTX & 0 for disabling it.
+ * Note: If GTX was already running (since the global GTX control
+ * resides with default BDF setting) & host wants to disable GTX,
+ * the VDEV does not exercise any more TPC changes on the GTX supported
+ * rates & goes to a default GTX SM where all PPDU's sent on default TPC.
+ * Whenever, host wants to reenable GTX, the enable command resumes the
+ * GTX functionality & TPC convergence to lower power levels can be
+ * attained as long as PER on GTX supported rates is within the pre-defined
+ * PER margin configured through the BDF.
+ */
+ WMI_VDEV_PARAM_GTX_ENABLE, /* 0x85 */
+
+ /*
+ * Enable/Disable multicast buffer.
+ * A FLAG to enable & disable buffering of multicast frames at AP
+ * when stations are in Power Save mode.
+ * Once AP disables buffering of multicast frame,
+ * clients which goes into Power save mode will not receive these frames.
+ * by default MCAST buffering will be enabled.
+ * (CABQ = Content After Beacon Queue = multicast queue)
+ * Host will send this VDEV param command,
+ * With Value = 1 means fw will disable the MCAST buffering
+ * With Value = 0 means fw will enable the MCAST buffering.
+ */
+ WMI_VDEV_PARAM_DISABLE_CABQ, /* 0x86 */
+
+ /**
+ * For SU and MU sounding
+ * switch between su ac/ax sounding and mu ac/ax sounding
+ * switch between triggered/ non-triggered on ax sounding enabled.
+ * each bit toggles the corresponding modes by enabling/disabling
+ *
+ * Bit 1 doesn't carry any operation for now and may change later,
+ * so reserved.
+ *
+ *-----------------------
+ * bit(0) | mode
+ *-----------------------
+ * 0 | AC
+ * 1 | AX
+ *-----------------------
+ *
+ * bit(1) | Reserved
+ *
+ *-----------------------
+ * bit(2) | mode
+ *-----------------------
+ * 0 | SU
+ * 1 | MU
+ *-----------------------
+ * bit(3) | mode
+ *-----------------------
+ * 0 | non -triggered
+ * 1 | triggered
+ */
+ WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE, /* 0x87 */
+
+ /** Fixed rate setting used in UL Trigger
+ * The top nibble is used to select which format to use for encoding
+ * the rate specification: 0xVXXXXXXX, V must be 1 for the UL
+ * format.
+ * If V == 0b0001: format is: 0x1000RRRR.
+ * This will be output of WMI_ASSEMBLE_RATECODE_V1
+ *
+ * This parameter controls the UL OFDMA and UL MU-MIMO vdev fixed rate.
+ */
+ WMI_VDEV_PARAM_UL_FIXED_RATE, /* 0x88 */
+
+ /**
+ * Uplink MU-MIMO & OFDMA GI configuration used in UL Trigger
+ * 11AX: GI =
+ * WMI_GI_400_NS, WMI_GI_800_NS, WMI_GI_1600_NS, or WMI_GI_3200_NS
+ * 11N: SGI=WMI_GI_400_NS
+ */
+ WMI_VDEV_PARAM_UL_GI, /* 0x89 */
+
+ /** Enable/Disable LDPC in UL Trigger */
+ WMI_VDEV_PARAM_UL_LDPC, /* 0x8A */
+
+ /** Max NSS allowed in UL Trigger */
+ WMI_VDEV_PARAM_UL_NSS, /* 0x8B */
+
+ /** Enable/Disable STBC in UL Trigger */
+ WMI_VDEV_PARAM_UL_STBC, /* 0x8C */
+
+ /** specify the HE LTF setting that should be used for fixed rate
+ * uplink transmissions.
+ *
+ * Expects values of WMI_HE_LTF_DEFAULT, WMI_HE_LTF_1X, WMI_HE_LTF_2X,
+ * or WMI_HE_LTF_4X.
+ */
+ WMI_VDEV_PARAM_UL_HE_LTF, /* 0x8D */
+
+ /** Uplink OFDMA PPDU bandwidth (0: 20MHz, 1: 40MHz, 2: 80Mhz, 3: 160MHz)*/
+ WMI_VDEV_PARAM_UL_PPDU_BW, /* 0x8E */
+
+ /** Enable/Disable FW handling MU EDCA change from AP (1: En, 0:Dis) */
+ WMI_VDEV_PARAM_MU_EDCA_FW_UPDATE_EN, /* 0x8F */
+
+ /** Update dot11ObssNbruToleranceTime in fw. Param value: seconds */
+ WMI_VDEV_PARAM_UPDATE_OBSS_RU_TOLERANCE_TIME, /* 0x90 */
+
+ /** Parameter used when MTU size is sent by the host
+ * In particular, this configuration message is used for cases where the
+ * encapsulation header results in a larger max frame size than the
+ * typical 802.3 + SNAP/LLC frame.
+ */
+ WMI_VDEV_PARAM_MAX_MTU_SIZE, /* 0x91 */
+
+ /** Send every nth beacon to host
+ * if value of n is 0, it means this Nth beacon upload is disabled
+ */
+ WMI_VDEV_PARAM_NTH_BEACON_TO_HOST, /* 0x92 */
+
+ /**
+ * To capture the MGMT OR DATA OR BOTH packets.
+ * Refer to enum WMI_PKT_CAPTURE_MODE_CONFIG for specifications of
+ * which parameter value enables which kind of packet captures.
+ */
+ WMI_VDEV_PARAM_PACKET_CAPTURE_MODE, /* 0x93 */
+
+ /**
+ * To configure duration of how many seconds without tx unicast traffic is
+ * considered stale for mcast rate adaptation
+ */
+ WMI_VDEV_PARAM_MCAST_RC_STALE_PERIOD, /* 0x94 */
+
+ /*
+ * Bits 3:0 - AST0_FLOW_MASK(4)
+ * Bits 7:4 - AST1_FLOW_MASK(4)
+ * Bits 11:8 - AST2_FLOW_MASK(4)
+ * Bits 15:12 - AST3_FLOW_MASK(4)
+ * Bits 23:16 - TID_VALID_HI_PRI(8)
+ * Bits 31:24 - TID_VALID_LOW_PRI(8)
+ *
+ * The below macros can be used to set/get the relevent fields.
+ * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_GET(msdu_flow_config1, ast_x)
+ * WMI_MSDU_FLOW_ASTX_MSDU_FLOW_MASKS_SET(msdu_flow_config1, ast_x, mask)
+ * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_GET(msdu_flow_config1)
+ * WMI_MSDU_FLOW_TID_VALID_HI_MASKS_SET(msdu_flow_config1, mask)
+ * WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_GET(msdu_flow_config1)
+ * WMI_MSDU_FLOW_TID_VALID_LOW_MASKS_SET(msdu_flow_config1, mask)
+ */
+ WMI_VDEV_PARAM_MSDU_FLOW_OVERRIDE_CONFIG, /* 0x95 */
+
/*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE ===
* The below vdev param types are used for prototyping, and are
@@ -8396,6 +10099,10 @@
#define WMI_VDEV_HE_ULMUMIMO_ENABLE(hemu_mode) WMI_SET_BITS(hemu_mode, 6, 1, 1)
#define WMI_VDEV_HE_ULMUMIMO_DISABLE(hemu_mode) WMI_SET_BITS(hemu_mode, 6, 1, 0)
+#define WMI_VDEV_HE_AX_SOUNDING_IS_ENABLED(mode) WMI_GET_BITS(mode, 0, 1)
+#define WMI_VDEV_HE_MU_SOUNDING_IS_ENABLED(mode) WMI_GET_BITS(mode, 2, 1)
+#define WMI_VDEV_HE_AX_TRIG_SOUNDING_IS_ENABLED(mode) WMI_GET_BITS(mode, 3, 1)
+
/* vdev capabilities bit mask */
#define WMI_VDEV_BEACON_SUPPORT 0x1
#define WMI_VDEV_WDS_LRN_ENABLED 0x2
@@ -8555,6 +10262,12 @@
#define WMI_ROAM_FW_OFFLOAD_ENABLE_FLAG 0x1
/* Enable Roaming module in FW to do scan based on Final BMISS */
#define WMI_ROAM_BMISS_FINAL_SCAN_ENABLE_FLAG 0x2
+/**
+ * To enable/disable EAPOL_4WAY_HANDSHAKE process while roaming.
+ * param value = 0 --> Enable EAPOL 4way handshake
+ * param value = 1 --> Skip EAPOL 4way handshake
+ */
+#define WMI_VDEV_PARAM_SKIP_ROAM_EAPOL_4WAY_HANDSHAKE 0x4
/** slot time long */
#define WMI_VDEV_SLOT_TIME_LONG 0x1
@@ -8624,6 +10337,9 @@
#define WMI_VDEV_START_RESPONSE_STATUS_SUCCESS 0x0 /** VDEV succesfully started */
#define WMI_VDEV_START_RESPONSE_INVALID_VDEVID 0x1 /** requested VDEV not found */
#define WMI_VDEV_START_RESPONSE_NOT_SUPPORTED 0x2 /** unsupported VDEV combination */
+#define WMI_VDEV_START_RESPONSE_DFS_VIOLATION 0x3 /** DFS_VIOLATION since channel in the NOL is selected */
+#define WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN 0x4 /** Invalid regulatory domain in VDEV start */
+#define WMI_VDEV_START_RESPONSE_INVALID_BAND 0x5 /** Band unsupported by current hw mode in VDEV start */
/** Beacon processing related command and event structures */
typedef struct {
@@ -8700,6 +10416,20 @@
* is 0, 1, 4 and 5, set the bitmap to (0X80000033)
*/
A_UINT32 csa_event_bitmap;
+ /** offset (in octets/bytes) of MBSSID IE in beacon frame */
+ A_UINT32 mbssid_ie_offset;
+ /** offset (in octets/bytes) of ESP IE in beacon frame */
+ A_UINT32 esp_ie_offset;
+ /** CSC IE color switch count offset from the beginning of data[]
+ * Value 0 indicates CSC IE is not present in beacon template.
+ */
+ A_UINT32 csc_switch_count_offset; /* units = bytes */
+ /** Specify when to send the CSC switch count status from FW to host.
+ * See WMI_CSC_EVENT_BMAP* below for more information.
+ * E.g. if CSA switch count event is needed to be sent when the switch count
+ * is 0, 1, 4 and 5, set the bitmap to (0X80000033)
+ */
+ A_UINT32 csc_event_bitmap;
/*
* The TLVs follows:
@@ -8713,6 +10443,11 @@
Same can also be achieved by setting bitmap to 0X80000001 */
#define WMI_CSA_EVENT_BMAP_ALL 0XFFFFFFFF /* Send CSA switch count event for every update to switch count */
+#define WMI_CSC_EVENT_BMAP_VALID_MASK 0X80000000 /* Follow bitmap for sending the CSC switch count event */
+#define WMI_CSC_EVENT_BMAP_SWITCH_COUNT_ZERO 0 /* Send only when the switch count becomes zero, added for backward compatibility
+ Same can also be achieved by setting bitmap to 0X80000001 */
+#define WMI_CSC_EVENT_BMAP_ALL 0XFFFFFFFF /* Send CSC switch count event for every update to switch count */
+
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_prb_tmpl_cmd_fixed_param */
/** unique id identifying the VDEV, generated by the caller */
@@ -8754,6 +10489,14 @@
A_UINT32 sta_ps_mode;
} wmi_sta_powersave_mode_cmd_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_sta_tdcc_config_cmd_fixed_param */
+ /** Set a max tx period: percentage of one beacon interval. range: 0 - 100 */
+ A_UINT32 tx_cycle_percentage;
+ /** Enable/disable TX Duty Cycle Control powersave */
+ A_UINT32 enabled;
+} wmi_sta_tdcc_config_cmd_fixed_param;
+
enum wmi_csa_offload_en {
WMI_CSA_OFFLOAD_DISABLE = 0,
WMI_CSA_OFFLOAD_ENABLE = 1,
@@ -9174,6 +10917,21 @@
} wmi_tim_info;
typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tim_info */
+ /** TIM Partial Virtual Bitmap */
+ A_UINT32 tim_mcast;
+ A_UINT32 tim_changed;
+ A_UINT32 tim_num_ps_pending;
+ /** Use the vdev_id only if vdev_id_valid is set */
+ A_UINT32 vdev_id_valid;
+ /** unique id identifying the VDEV */
+ A_UINT32 vdev_id;
+ /** TIM bitmap len (in bytes) */
+ A_UINT32 tim_len;
+ /* followed by WMITLV_TAG_ARRAY_BYTE holding the TIM bitmap */
+} wmi_tim_info_v2;
+
+typedef struct {
/** Flag to enable quiet period IE support */
A_UINT32 is_enabled;
/** Quiet start */
@@ -9206,6 +10964,15 @@
A_UINT32 vdev_id;
} wmi_p2p_noa_info;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_quiet_offload_info */
+ A_UINT32 vdev_id; /* unique id identifying the VDEV */
+ A_UINT8 tbttcount; /* quiet start */
+ A_UINT8 period; /* beacon intervals between quiets */
+ A_UINT16 duration; /* TUs of each quiet */
+ A_UINT16 offset; /* TUs of from TBTT of quiet start */
+} wmi_quiet_offload_info;
+
#define WMI_UNIFIED_NOA_ATTR_MODIFIED 0x1
#define WMI_UNIFIED_NOA_ATTR_MODIFIED_S 0
@@ -9276,6 +11043,7 @@
/* This TLV is followed by tim_info and p2p_noa_info for each vdev:
* wmi_tim_info tim_info[];
* wmi_p2p_noa_info p2p_noa_info[];
+ * wmi_quiet_offload_info quiet_offload_info[0/1];
*
*/
} wmi_host_swba_event_fixed_param;
@@ -9371,6 +11139,7 @@
WMI_PEER_TYPE_TDLS = 2, /* Peer is a TDLS Peer */
WMI_PEER_TYPE_OCB = 3, /* Peer is a OCB Peer */
WMI_PEER_TYPE_NAN_DATA = 4, /* Peer is NAN DATA */
+ WMI_PEER_TYPE_TRANS_BSS = 5, /* For creating BSS peer when connecting with non-transmit AP */
WMI_PEER_TYPE_HOST_MAX = 127, /* Host <-> Target Peer type is assigned up to 127 */
/* Reserved from 128 - 255 for target internal use.*/
WMI_PEER_TYPE_ROAMOFFLOAD_TEMP = 128, /* Temporarily created during offload roam */
@@ -9395,6 +11164,22 @@
} wmi_peer_delete_cmd_fixed_param;
typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_delete_all_peer_cmd_fixed_param */
+ /** unique id identifying the VDEV, generated by the caller */
+ A_UINT32 vdev_id;
+} wmi_vdev_delete_all_peer_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_unmap_response_cmd_fixed_param */
+ A_UINT32 tlv_header;
+ /*
+ * Following this struct is the TLV:
+ * A_UINT32 peer_ids[]; <-- variable-length array of peer_ids
+ * that have been unmapped by the host
+ */
+} wmi_peer_unmap_response_cmd_fixed_param;
+
+typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_set_rx_blocksize_cmd_fixed_param */
/** unique id identifying the VDEV, generated by the caller */
A_UINT32 vdev_id;
@@ -9658,6 +11443,25 @@
* (value 1 is enabled, value 0 is disabled)
* bits 1:5 are for ring 32 (i.e. ring id value
* selected from 0 to 31 values)
+ * bit 8 for peer based ring selection enabled or not
+ * (value 1 is enabled, value 0 is disabled
+ * bits 9-15 are valid when bit 8 is set to 1)
+ * bit 9 is for ring selection enabled for filter-pass
+ * unicast or not (value 1 is enabled, value 0 is disabled)
+ * bit 10 is for ring selection enabled for filter-pass
+ * mcast or not (value 1 is enabled, value 0 is disabled)
+ * bit 11 is for ring selection enabled for filter-pass
+ * BAR or not (value 1 is enabled, value 0 is disabled)
+ * bit 12-13 is for source ring selection value
+ * (value 0 for wbm2rxdma buf ring,
+ * value 1 for fw2rxdma buf ring,
+ * value 2 for sw2rxdma buf ring,
+ * value 3 for no buf ring)
+ * bit 14-15 is for destination ring selection value
+ * (value 0 for wbm release ring,
+ * value 1 for rxdma2fw ring,
+ * value 2 for rxdma2sw ring,
+ * value 3 for rxdma2reo ring)
*/
#define WMI_PEER_SET_DEFAULT_ROUTING 0x13
/* peer NSS for VHT160 - Extended NSS support */
@@ -9674,6 +11478,35 @@
#define WMI_PEER_PARAM_OFDMA_ENABLE 0x19
/* Per peer 11ax/11ac MU enable or disable */
#define WMI_PEER_PARAM_MU_ENABLE 0x1a
+/** Set peer fixed rate used in UL Trigger
+ * The top nibble is used to select which format to use for encoding
+ * the rate specification: 0xVXXXXXXX, V must be 1 for this parameter.
+ * If V == 0b0001: format is: 0x1000RRRR.
+ * This will be output of WMI_ASSEMBLE_RATECODE_V1
+ *
+ * This parameter controls the UL OFDMA and UL MU-MIMO peer fixed rate.
+ */
+#define WMI_PEER_PARAM_UL_FIXED_RATE 0x1b
+/** send specific OMI to peer via QoS-null frame
+ * param_value = follow 11ax spec definition
+ * bit0:VHT(1), bit1:HE(1), bit2-31:A-Control
+ */
+#define WMI_PEER_PARAM_XMIT_OMI 0x1c
+#define WMI_PEER_RARAM_XMIT_OMI WMI_PEER_PARAM_XMIT_OMI /* alias due to prior typo */
+
+/* Disable burst and assist */
+#define WMI_PEER_PARAM_DISABLE_AGGRESSIVE_TX 0x1d
+/* Enable 11r FT Roaming */
+#define WMI_PEER_PARAM_ENABLE_FT 0x1e
+/* update peer flag for ptk 4 way handshake */
+#define WMI_PEER_PARAM_NEED_PTK_4_WAY 0x1f
+/* update peer flag for gtk 2 way handshake */
+#define WMI_PEER_PARAM_NEED_GTK_2_WAY 0x20
+/* update peer flag for M4 sent */
+#define WMI_PEER_PARAM_M4_SENT 0x21
+
+/* Per peer MISC stats enable or disable */
+#define WMI_PEER_PARAM_MISC_STATS_ENABLE 0x22
/** mimo ps values for the parameter WMI_PEER_MIMO_PS_STATE */
#define WMI_PEER_MIMO_PS_NONE 0x0
@@ -9789,11 +11622,15 @@
A_UINT32 rx_max_rate; /* Max Rx data rate */
A_UINT32 rx_mcs_set; /* Negotiated RX VHT rates */
A_UINT32 tx_max_rate; /* Max Tx data rate */
+ /*
+ * bit [15:0] indicates MCS 0 to 9
+ * bit [23:16] indicates MCS 10 & 11
+ * bit [24] indicates whether MCS 10 & 11 is notified in bit [23:16]
+ */
A_UINT32 tx_mcs_set; /* Negotiated TX VHT rates */
A_UINT32 tx_max_mcs_nss; /* b0-b3: max mcs idx; b4-b7: max nss */
} wmi_vht_rate_set;
-
/* NOTE: It would bea good idea to represent the Tx MCS
* info in one word and Rx in another word. This is split
* into multiple words for convenience
@@ -9838,6 +11675,9 @@
#define WMI_PEER_DYN_MIMOPS 0x00020000 /* Dynamic MIMO PS Enabled */
#define WMI_PEER_STATIC_MIMOPS 0x00040000 /* Static MIMO PS enabled */
#define WMI_PEER_SPATIAL_MUX 0x00200000 /* SM Enabled */
+#define WMI_PEER_TWT_REQ 0x00400000 /* TWT Requester Support bit in Extended Capabilities element */
+#define WMI_PEER_TWT_RESP 0x00800000 /* TWT Responder Support bit in Extended Capabilities element */
+#define WMI_PEER_MULTI_BSSID 0x01000000 /* Multiple BSSID Support bit in Extended Capabilities element */
#define WMI_PEER_VHT 0x02000000 /* VHT Enabled */
#define WMI_PEER_80MHZ 0x04000000 /* 80MHz enabld */
#define WMI_PEER_PMF 0x08000000 /* Robust Management Frame Protection enabled */
@@ -9935,6 +11775,22 @@
A_UINT32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE];
A_UINT32 peer_he_mcs; /* Indicates number of HE MCS TLV present */
+ /* 2nd DWORD of 11ax MAC Capabilities */
+ A_UINT32 peer_he_cap_info_ext;
+
+ /*
+ * bit 0 : Indicated support for RX 1xLTF + 0.4us
+ * bit 1 : Indicates support for RX 2xLTF + 0.4us
+ * bit 2 : Indicates support for 2xLTF in 160/80+80 MHz HE PPDU
+ * bit[4:3] : Indicates support for DL OFDMA
+ * Refer to enum WMI_HE_RX_DL_OFDMA_SUPPORT_x
+ * bit[6:5] : Indicates support for DL MU-MIMO
+ * Refer to enum WMI_HE_RX_DL_MUMIMO_SUPPORT_x
+ * bit[31:7] : Reserved
+ * Refer to WMI_HE_CAP_xx_LTF_xxx_SUPPORT_GET/SET macros
+ */
+ A_UINT32 peer_he_cap_info_internal;
+
/* Following this struct are the TLV's:
* A_UINT8 peer_legacy_rates[];
* A_UINT8 peer_ht_rates[];
@@ -9957,8 +11813,11 @@
A_UINT32 vdev_id;
} wmi_peer_add_wds_entry_cmd_fixed_param;
-#define WMI_CHAN_InFO_START_RESP 0
-#define WMI_CHAN_InFO_END_RESP 1
+#define WMI_CHAN_INFO_START_RESP 0
+#define WMI_CHAN_INFO_END_RESP 1
+/* deprecated but maintained as aliases: old names containing typo */
+#define WMI_CHAN_InFO_START_RESP WMI_CHAN_INFO_START_RESP
+#define WMI_CHAN_InFO_END_RESP WMI_CHAN_INFO_END_RESP
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_remove_wds_entry_cmd_fixed_param */
@@ -10197,6 +12056,19 @@
A_UINT32 roam_scan_mode;
A_UINT32 vdev_id;
A_UINT32 flags; /* see WMI_ROAM_SCAN_MODE_FLAG defs */
+ /*
+ * Minimum duration allowed between two consecutive roam scans.
+ * Roam scan is not allowed, if duration between two consecutive
+ * roam scans is less than this time.
+ */
+ A_UINT32 min_delay_btw_scans; /* In msec */
+ /*
+ * Bitmask (with enum WMI_ROAM_TRIGGER_REASON_ID identifying the bit
+ * positions) showing for which roam_trigger_reasons the
+ * min_delay_btw_scans constraint should be applied.
+ * 0x0 means there is no time restrictions between successive roam scans.
+ */
+ A_UINT32 min_delay_roam_trigger_reason_bitmask;
} wmi_roam_scan_mode_fixed_param;
#define WMI_ROAM_SCAN_MODE_NONE 0x0
@@ -10257,16 +12129,25 @@
* BIT 1-2 : Action on non matching candidate with cache. Used WMI_ROAM_BTM_OFLD_NON_MATCHING_CND_XXX
* BIT 3-5 : Roaming handoff decisions. Use WMI_ROAM_BTM_OFLD_CNDS_MATCH_XXX
* BIT 6 : Enable/Disable solicited BTM
- * BIT 7-31 : Reserved
+ * BIT 7 : Roam BTM candidates based on the roam score instead of BTM preferred value
+ * BIT 8 : BTM query preference over 11k neighbor report request
+ * BIT 9-31 : Reserved
*/
-#define WMI_ROAM_BTM_SET_ENABLE(flags, val) WMI_SET_BITS(flags, 0, 1, val)
-#define WMI_ROAM_BTM_GET_ENABLE(flags) WMI_GET_BITS(flags, 0, 1)
-#define WMI_ROAM_BTM_SET_NON_MATCHING_CND_ACTION(flags, val) WMI_SET_BITS(flags, 1, 2, val)
-#define WMI_ROAM_BTM_GET_NON_MATCHING_CND_ACTION(flags) WMI_GET_BITS(flags, 1, 2)
-#define WMI_ROAM_BTM_SET_CNDS_MATCH_CONDITION(flags, val) WMI_SET_BITS(flags, 3, 3, val)
-#define WMI_ROAM_BTM_GET_CNDS_MATCH_CONDITION(flags) WMI_GET_BITS(flags, 3, 3)
-#define WMI_ROAM_BTM_SET_SOLICITED_BTM_ENABLE(flags, val) WMI_SET_BITS(flags, 6, 1, val)
-#define WMI_ROAM_BTM_GET_SOLICITED_BTM_ENABLE(flags) WMI_GET_BITS(flags, 6, 1)
+#define WMI_ROAM_BTM_SET_ENABLE(flags, val) WMI_SET_BITS(flags, 0, 1, val)
+#define WMI_ROAM_BTM_GET_ENABLE(flags) WMI_GET_BITS(flags, 0, 1)
+#define WMI_ROAM_BTM_SET_NON_MATCHING_CND_ACTION(flags, val) WMI_SET_BITS(flags, 1, 2, val)
+#define WMI_ROAM_BTM_GET_NON_MATCHING_CND_ACTION(flags) WMI_GET_BITS(flags, 1, 2)
+#define WMI_ROAM_BTM_SET_CNDS_MATCH_CONDITION(flags, val) WMI_SET_BITS(flags, 3, 3, val)
+#define WMI_ROAM_BTM_GET_CNDS_MATCH_CONDITION(flags) WMI_GET_BITS(flags, 3, 3)
+#define WMI_ROAM_BTM_SET_SOLICITED_BTM_ENABLE(flags, val) WMI_SET_BITS(flags, 6, 1, val)
+#define WMI_ROAM_BTM_GET_SOLICITED_BTM_ENABLE(flags) WMI_GET_BITS(flags, 6, 1)
+#define WMI_ROAM_BTM_SET_CNDS_SELECT_BASED_ON_SCORE(flags, val) WMI_SET_BITS(flags, 7, 1, val)
+#define WMI_ROAM_BTM_GET_CNDS_SELECT_BASED_ON_SCORE(flags) WMI_GET_BITS(flags, 7, 1)
+#define WMI_ROAM_BTM_SET_BTM_QUERY_PREFERENCE_OVER_11K(flags, val) WMI_SET_BITS(flags, 8, 1, val)
+#define WMI_ROAM_BTM_GET_BTM_QUERY_PREFERENCE_OVER_11K(flags) WMI_GET_BITS(flags, 8, 1)
+#define WMI_ROAM_BTM_SET_BTM_QUERY_WITH_CANDIDATE_LIST(flags, val) WMI_SET_BITS(flags, 9, 1, val)
+#define WMI_ROAM_BTM_GET_BTM_QUERY_WITH_CANDIDATE_LIST(flags) WMI_GET_BITS(flags, 9, 1)
+
/** WMI_ROAM_BTM_SET_NON_MATCHING_CNDS_ACTION definition: When BTM candidate is not matched with cache by WMI_ROAM_BTM_SET_CNDS_MATCH_CONDITION, determine what to do */
#define WMI_ROAM_BTM_NON_MATCHING_CNDS_SCAN_CONSUME 0 /** Invoke roam scan and consume within firmware. Applicable only when ROAM_SCAN_MODE is enabled. If ROAM_SCAN_MODE is disabled, firmware won't scan and forward it to host */
@@ -10303,6 +12184,26 @@
* Default value: 300 will be set if invalid value is given
*/
A_UINT32 stick_time_seconds;
+ /* Disassoc time threshold in milliseconds
+ * This time threshold allows the target to judge whether the STA
+ * should can move to another AP immediately, or if the STA has time
+ * to calculate roaming candidates.
+ * If the disassoc_timer_threshold value is 0x0, the field should be
+ * disregarded.
+ */
+ A_UINT32 disassoc_timer_threshold;
+ /*
+ * Bitmask (with enum WMI_ROAM_TRIGGER_REASON_ID identifying the bit
+ * positions) showing for which roam_trigger_reasons the
+ * btm query needs to be sent.
+ * If roam trigger reasons are unspecified, btm_bitmap will be 0x0.
+ */
+ A_UINT32 btm_bitmap;
+ /*
+ * Consider AP as roam candidate only if AP score is better than
+ * btm_candidate_min_score for BTM roam trigger
+ */
+ A_UINT32 btm_candidate_min_score;
} wmi_btm_config_fixed_param;
#define WMI_ROAM_5G_BOOST_PENALIZE_ALGO_FIXED 0x0
@@ -10332,9 +12233,17 @@
/** unique id identifying the VDEV, generated by the caller */
A_UINT32 vdev_id;
/** roam scan period value */
- A_UINT32 roam_scan_period;
+ A_UINT32 roam_scan_period; /* units = milliseconds */
/** Aging for Roam scans */
A_UINT32 roam_scan_age;
+ /** Inactivity monitoring time to consider device is in inactive state with data count is less than roam_inactive_count */
+ A_UINT32 inactivity_time_period; /* units = milliseconds */
+ /** Maximum allowed data packets count during inactivity_time_period */
+ A_UINT32 roam_inactive_count;
+ /** New roam scan period after device is in inactivity state */
+ A_UINT32 roam_scan_period_after_inactivity; /* units = milliseconds */
+ /** roam full scan period value */
+ A_UINT32 roam_full_scan_period; /* units = milliseconds */
} wmi_roam_scan_period_fixed_param;
/**
@@ -10372,7 +12281,7 @@
/**
* TLV (tag length value) parameters follow the wmi_roam_chan_list
* structure. The TLV's are:
- * A_UINT32 channel_list[];
+ * A_UINT32 channel_list[]; // in MHz
**/
} wmi_roam_chan_list_fixed_param;
@@ -10401,6 +12310,12 @@
WMI_AUTH_RSNA_FILS_SHA384,
WMI_AUTH_RSNA_SUITE_B_8021X_SHA256,
WMI_AUTH_RSNA_SUITE_B_8021X_SHA384,
+ WMI_AUTH_FT_RSNA_SAE,
+ WMI_AUTH_FT_RSNA_SUITE_B_8021X_SHA384,
+ WMI_AUTH_FT_RSNA_FILS_SHA256,
+ WMI_AUTH_FT_RSNA_FILS_SHA384,
+ WMI_AUTH_WPA3_SAE,
+ WMI_AUTH_WPA3_OWE,
};
typedef enum {
@@ -10633,6 +12548,8 @@
nss_scoring :- NSS scoring percentage information.
esp_qbss_scoring :- ESP/QBSS scoring percentage information
oce_wan_scoring : OCE WAN metrics percentage information
+ roam_score_delta_pcnt :- consider scanned AP as roam eligible candidate only if scanned AP score is at least roam_score_delta % better than connected AP score
+ roam_score_delta_mask :- roam trigger bitmap for which roam_score_delta needs to apply. The WMI_ROAM_TRIGGER_REASON_ID enum values identify which bit within the mask is used for which roam trigger cause.
*/
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_cnd_scoring_param */
@@ -10654,8 +12571,35 @@
wmi_roam_cnd_nss_scoring nss_scoring;
wmi_roam_cnd_esp_qbss_scoring esp_qbss_scoring;
wmi_roam_cnd_oce_wan_scoring oce_wan_scoring;
+ A_UINT32 roam_score_delta_pcnt;
+ A_UINT32 roam_score_delta_mask;
} wmi_roam_cnd_scoring_param;
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_score_delta_param */
+ /* Roam trigger reason ID from WMI_ROAM_TRIGGER_REASON_ID */
+ A_UINT32 roam_trigger_reason;
+ /* Roam score delta in %.
+ * Consider AP as roam candidate only if AP score is at least
+ * roam_score_delta % better than connected AP score.
+ * Ex: roam_score_delta = 20, and connected AP score is 4000,
+ * then consider candidate AP only if its score is at least
+ * 4800 (= 4000 * 120%)
+ */
+ A_UINT32 roam_score_delta;
+} wmi_roam_score_delta_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_cnd_min_rssi_param */
+ /* Roam trigger reason ID from WMI_ROAM_TRIGGER_REASON_ID */
+ A_UINT32 roam_trigger_reason;
+ /*
+ * Consider AP as roam candidate only if AP rssi is better than
+ * candidate_min_rssi
+ */
+ A_UINT32 candidate_min_rssi; /* units = dbm */
+} wmi_roam_cnd_min_rssi_param;
+
/** To match an open AP, the rs_authmode should be set to WMI_AUTH_NONE
* and WMI_AP_PROFILE_FLAG_CRYPTO should be clear.
* To match a WEP enabled AP, the rs_authmode should be set to WMI_AUTH_NONE
@@ -10842,6 +12786,8 @@
* Following this structure is the TLV:
* wmi_ap_profile ap_profile; <-- AP profile info
* wmi_roam_cnd_scoring_param roam_cnd_scoring_param
+ * wmi_roam_score_delta_param roam_score_delta_param_list[]
+ * wmi_roam_cnd_min_rssi_param roam_cnd_min_rssi_param_list[]
*/
} wmi_roam_ap_profile_fixed_param;
@@ -10905,6 +12851,10 @@
A_UINT32 qos_caps;
A_UINT32 wmm_caps;
A_UINT32 mcsset[ROAM_OFFLOAD_NUM_MCS_SET>>2]; /* since this 4 byte aligned, we don't declare it as tlv array */
+ A_UINT32 handoff_delay_for_rx; /* In msec. Delay Hand-Off by this duration to receive pending Rx frames from current BSS */
+ A_UINT32 max_mlme_sw_retries; /* maximum number of software retries for preauth and reassoc req */
+ A_UINT32 no_ack_timeout; /* In msec. duration to wait before another SW retry made if no ack seen for previous frame */
+ A_UINT32 roam_candidate_validity_time; /* In msec. validity duration of each entry in roam cache. If the value is 0x0, this field should be disregarded. */
} wmi_roam_offload_tlv_param;
@@ -10956,6 +12906,9 @@
A_UINT32 r0kh_id_len;
A_UINT32 psk_msk[ROAM_OFFLOAD_PSK_MSK_BYTES>>2]; /* psk/msk offload. As this 4 byte aligned, we don't declare it as tlv array */
A_UINT32 psk_msk_len; /**length of psk_msk*/
+ A_UINT32 psk_msk_ext_len; /**length of psk_msk_ext*/
+ A_UINT32 psk_msk_ext[ROAM_OFFLOAD_PSK_MSK_BYTES>>2];
+ A_UINT32 adaptive_11r; /* FW needs to perform adaptive 11r roaming */
} wmi_roam_11r_offload_tlv_param;
/* This TLV will be filled only in case of ESE */
@@ -10965,6 +12918,42 @@
A_UINT32 btk[ROAM_OFFLOAD_BTK_BYTES>>2]; /* BTK offload. As this 4 byte aligned, we don't declare it as tlv array */
} wmi_roam_ese_offload_tlv_param;
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_blacklist_with_timeout_tlv_param */
+ A_UINT32 tlv_header;
+ /** Blaclisted AP mac address */
+ wmi_mac_addr bssid;
+ /** How much time in milliseconds to keep AP in blacklist */
+ A_UINT32 timeout;
+} wmi_roam_blacklist_with_timeout_tlv_param;
+
+/** WMI_ROAM_BLACKLIST_EVENT: generated whenever STA needs to move AP to blacklist for a particluar time
+ * Ex: AP which sends BTM request with disassoc imminent is set should be
+ * moved to blacklist until disassociation timer expires
+ */
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_blacklist_event_fixed_param */
+ A_UINT32 vdev_id;
+ /* This TLV is followed by further TLVs:
+ * wmi_roam_blacklist_with_timeout_tlv_param blacklist_with_timeout[]
+ */
+} wmi_roam_blacklist_event_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header;
+ /** candidate AP mac address */
+ wmi_mac_addr bssid;
+} wmi_roam_pmkid_request_tlv_param;
+
+/** WMI_ROAM_PMKID_REQUEST_EVENT: generated whenever FW needs the PMKID while roaming **/
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_pmkid_request_event_fixed_param */
+ A_UINT32 vdev_id;
+ /* This TLV is followed by further TLVs:
+ * wmi_roam_pmkid_request_tlv_param pmkid_request[]
+ */
+} wmi_roam_pmkid_request_event_fixed_param;
+
/** WMI_ROAM_EVENT: roam event triggering the host roam logic.
* generated when ever a better AP is found in the recent roam scan (or)
* when beacon miss is detected (or) when a DEAUTH/DISASSOC is received
@@ -10980,6 +12969,14 @@
A_UINT32 rssi;
/** roam notification */
A_UINT32 notif;
+ /** roam notification param
+ * Refer to WMI_ROAM_NOTIF_ defs to interpret the notif_params value.
+ */
+ A_UINT32 notif_params;
+ /** roam notification param1
+ * Refer to WMI_ROAM_NOTIF_ defs to interpret the notif_params1 value.
+ */
+ A_UINT32 notif_params1;
} wmi_roam_event_fixed_param;
@@ -10987,7 +12984,6 @@
#define WMI_ROAM_REASON_INVALID 0x0 /** invalid reason. Do not interpret reason field */
#define WMI_ROAM_REASON_BETTER_AP 0x1 /** found a better AP */
#define WMI_ROAM_REASON_BMISS 0x2 /** beacon miss detected */
-#define WMI_ROAM_REASON_DEAUTH 0x2 /** deauth/disassoc received */
#define WMI_ROAM_REASON_LOW_RSSI 0x3 /** connected AP's low rssi condition detected */
#define WMI_ROAM_REASON_SUITABLE_AP 0x4 /** found another AP that matches
SSID and Security profile in
@@ -11004,6 +13000,7 @@
#define WMI_ROAM_REASON_INVOKE_ROAM_FAIL 0x6
#define WMI_ROAM_REASON_RSO_STATUS 0x7
#define WMI_ROAM_REASON_BTM 0x8 /** Roaming because of BTM request received */
+#define WMI_ROAM_REASON_DEAUTH 0x9 /** deauth/disassoc received */
/* reserved up through 0xF */
/* subnet status: bits 4-5 */
@@ -11051,6 +13048,9 @@
#define WMI_ROAM_NOTIF_SCAN_MODE_FAIL 0x5 /** indicate that roaming scan mode is failed due to internal roaming state */
#define WMI_ROAM_NOTIF_DISCONNECT 0x6 /** indicate that roaming not allowed due BTM req */
#define WMI_ROAM_NOTIF_SUBNET_CHANGED 0x7 /** indicate that subnet has changed */
+#define WMI_ROAM_NOTIF_SCAN_START 0x8 /** indicate roam scan start, notif_params to be sent as WMI_ROAM_TRIGGER_REASON_ID */
+#define WMI_ROAM_NOTIF_DEAUTH_RECV 0x9 /** indicate deauth received, notif_params to be sent as reason code, notif_params1 to be sent as frame length */
+#define WMI_ROAM_NOTIF_DISASSOC_RECV 0xa /** indicate disassoc received, notif_params to be sent as reason code, notif_params1 to be sent as frame length */
/**whenever RIC request information change, host driver should pass all ric related information to firmware (now only support tsepc)
* Once, 11r roaming happens, firmware can generate RIC request in reassoc request based on these informations
@@ -11111,6 +13111,7 @@
#define WMI_ROAM_INVOKE_SCAN_MODE_CACHE_LIST 1 /* scan cached channel list */
#define WMI_ROAM_INVOKE_SCAN_MODE_FULL_CH 2 /* scan full channel */
#define WMI_ROAM_INVOKE_SCAN_MODE_SKIP 3 /* no scan is performed. use beacon/probe resp given by the host */
+#define WMI_ROAM_INVOKE_SCAN_MODE_CACHE_MAP 4 /* scan cached channel map */
#define WMI_ROAM_INVOKE_AP_SEL_FIXED_BSSID 0 /* roam to given BSSID only */
#define WMI_ROAM_INVOKE_AP_SEL_ANY_BSSID 1 /* roam to any BSSID */
@@ -11141,7 +13142,7 @@
/**
* TLV (tag length value) parameters follows roam_invoke_req
* The TLV's are:
- * A_UINT32 channel_list[];
+ * A_UINT32 channel_list[]; // in MHz
* wmi_mac_addr bssid_list[];
* wmi_tlv_buf_len_param bcn_prb_buf_list[];
* A_UINT8 bcn_prb_frm[];
@@ -11169,7 +13170,7 @@
#define WMI_ROAM_LCA_DISALLOW_SOURCE_FORCED 0x100
typedef struct {
- /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_rssi_rejection_oce_config_param */
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_rejection_list_config_param */
A_UINT32 tlv_header;
/** BSSID of AP, who reject (re-)assoc due to low RSSI */
wmi_mac_addr bssid;
@@ -11177,7 +13178,8 @@
A_UINT32 remaining_disallow_duration;
/** AP will be allowed for candidate, when AP RSSI better than expected RSSI units in dBm */
A_INT32 requested_rssi;
-} wmi_roam_rssi_rejection_oce_config_param;
+} wmi_roam_rejection_list_config_param;
+typedef wmi_roam_rejection_list_config_param wmi_roam_rssi_rejection_oce_config_param; /* retain old struct name as an alias for the new name */
typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_filter_list_fixed_param */
@@ -11196,7 +13198,7 @@
* wmi_mac_addr bssid_preferred_list[];
* A_UINT32 bssid_preferred_factor[];
* wmi_roam_lca_disallow_config_tlv_param lca_disallow_param[0/1] (opt)
- * wmi_roam_rssi_rejection_oce_config_param rssi_rejection_list[]
+ * wmi_roam_rejection_list_config_param rssi_rejection_list[]
*/
} wmi_roam_filter_fixed_param;
@@ -11274,6 +13276,23 @@
**/
} wmi_roam_subnet_change_config_fixed_param;
+/**
+ * WMI_ROAM_ENABLE_DISABLE_TRIGGER_REASON:
+ * Enable or disable roaming triggers in FW.
+ */
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_enable_disable_trigger_reason_fixed_param */
+ /** unique id identifying the VDEV, generated by the caller */
+ A_UINT32 vdev_id;
+ /**
+ * Bitmask (with enum WMI_ROAM_TRIGGER_REASON_ID identifying the bit
+ * positions) showing for which roam_trigger_reasons are enabled by
+ * bit value equal 0x1, and which roam_trigger_reasons are disabled by
+ * bit value equal 0x0.
+ */
+ A_UINT32 trigger_reason_bitmask;
+} wmi_roam_enable_disable_trigger_reason_fixed_param;
+
/** WMI_PROFILE_MATCH_EVENT: offload scan
* generated when ever atleast one of the matching profiles is found
* in recent NLO scan. no data is carried with the event.
@@ -11379,13 +13398,13 @@
A_UINT32 disc_type;
/* p2p find perodic */
A_UINT32 perodic;
- /* p2p find listen channel */
+ /* p2p find listen channel in MHz */
A_UINT32 listen_channel;
/* p2p find full channel number */
A_UINT32 num_scan_chans;
/**
* TLV (tag length value) paramerters follow the pattern structure.
- * TLV contain channel list
+ * TLV contain channel list in MHz
*/
} wmi_p2p_disc_offload_config_cmd;
@@ -11659,6 +13678,7 @@
WOW_11D_SCAN_EVENT,
WOW_SAP_OBSS_DETECTION_EVENT,
WOW_BSS_COLOR_COLLISION_DETECT_EVENT,
+ WOW_TKIP_MIC_ERR_FRAME_RECVD_EVENT,
} WOW_WAKE_EVENT_TYPE;
typedef enum wake_reason_e {
@@ -11717,7 +13737,15 @@
WOW_REASON_WLAN_DHCP_RENEW,
WOW_REASON_SAP_OBSS_DETECTION,
WOW_REASON_BSS_COLOR_COLLISION_DETECT,
+ WOW_REASON_TKIP_MIC_ERR_FRAME_RECVD_DETECT,
+ WOW_REASON_WLAN_MD, /* motion detected */
+ WOW_REASON_WLAN_BL, /* baselining done */
+ WOW_REASON_NTH_BCN_OFLD, /* nth beacon forward to host */
+ WOW_REASON_PKT_CAPTURE_MODE_WAKE,
+ WOW_REASON_PAGE_FAULT, /* Host wake up due to page fault */
+ /* add new WOW_REASON_ defs before this line */
+ WOW_REASON_MAX,
WOW_REASON_DEBUG_TEST = 0xFF,
} WOW_WAKE_REASON_TYPE;
@@ -11951,6 +13979,12 @@
A_UINT32 interval_low; /* interval for keeping low voltage, unit: ms */
A_UINT32 interval_high; /* interval for keeping high voltage, unit: ms */
A_UINT32 repeat_cnt; /* repeat times for pulse (0xffffffff means forever) */
+ A_UINT32 init_state; /* Sense of the GPIO pin used for host wakeups.
+ * If init_state is 0, a low --> high transition
+ * causes a host wakeup interrupt.
+ * If init_state is 1, a high --> low transition
+ * causes a host wakeup interrrupt.
+ */
} WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD_fixed_param;
#define MAX_SUPPORTED_ACTION_CATEGORY 256
@@ -12166,6 +14200,7 @@
#define WMI_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
#define WMI_RXERR_MIC 0x10 /* Michael MIC decrypt error */
#define WMI_RXERR_KEY_CACHE_MISS 0x20 /* No/incorrect key matter in h/w */
+#define WMI_RX_OFFLOAD_MON_MODE 0x40 /* Offload dropped mgmt pkt's for only in capture mode*/
typedef enum {
PKT_PWR_SAVE_PAID_MATCH = 0x00000001,
@@ -12637,7 +14672,7 @@
A_UINT32 num_cnlo_band_pref;
/* The TLVs will follow.
* nlo_configured_parameters nlo_list[];
- * A_UINT32 channel_list[num_of_channels];
+ * A_UINT32 channel_list[num_of_channels]; // in MHz
* nlo_channel_prediction_cfg ch_prediction_cfg;
* enlo_candidate_score_params candidate_score_params;
* wmi_vendor_oui vendor_oui[num_vendor_oui];
@@ -13035,6 +15070,17 @@
WMI_VENDOR_OUI_ACTION_CONNECTION_1X1 = 0, /* Connect in 1X1 only */
WMI_VENDOR_OUI_ACTION_ITO_EXTENSION = 1, /* Extend the Immediate Time-Out (ITO) if data is not received from AP after beacon with TIM bit set */
WMI_VENDOR_OUI_ACTION_CCKM_1X1 = 2, /* TX (only) CCKM rates with 1 chain only */
+ WMI_VENDOR_OUI_ACTION_ALT_ITO = 3, /* inactivity time-out */
+ WMI_VENDOR_OUI_ACTION_SWITCH_TO_11N_MODE = 4, /* Switch from 11ac to 11n mode to avoid IOT issues with ONM frame */
+ /* WMI_VENDOR_OUI_ACTION_CONNECTION_1X1_NUM_TX_RX_CHAINS_1
+ * Connect in 1x1 only and Use only one chain for both Tx and Rx
+ * to avoid IOT issues due to change in number of Tx and Rx chains
+ */
+ WMI_VENDOR_OUI_ACTION_CONNECTION_1X1_NUM_TX_RX_CHAINS_1 = 5,
+
+ /* Disable burst and assist, and restrict A-MPDU size to 32 */
+ WMI_VENDOR_OUI_ACTION_DISABLE_AGGRESSIVE_TX = 6,
+
/* Add any action before this line */
WMI_VENDOR_OUI_ACTION_MAX_ACTION_ID
} wmi_vendor_oui_action_id;
@@ -13141,6 +15187,10 @@
A_UINT32 off_duration; /* uint in mill seconds, channel off duraiton for path loss frame sending */
wmi_mac_addr dest_mac; /* multicast DA, for path loss frame */
A_UINT32 num_chans;
+/*
+ * This fixed_param TLV is followed by other TLVs:
+ * A_UINT32 channel_list[num_chans]; // in MHz
+ */
} wmi_vdev_plmreq_start_cmd_fixed_param;
typedef struct {
@@ -13655,8 +15705,15 @@
A_UINT32 tdls_puapsd_rx_frame_threshold;
/**Duration (in ms) over which to check whether TDLS link needs to be torn down */
A_UINT32 teardown_notification_ms;
- /**STA kickout threshold for TDLS peer */
+ /** STA kickout threshold for TDLS peer */
A_UINT32 tdls_peer_kickout_threshold;
+ /* TDLS discovery WAKE timeout in ms.
+ * DUT will wake until this timeout to receive TDLS discovery response
+ * from peer.
+ * If tdls_discovery_wake_timeout is 0x0, the DUT will choose autonomously
+ * what wake timeout value to use.
+ */
+ A_UINT32 tdls_discovery_wake_timeout;
} wmi_tdls_set_state_cmd_fixed_param;
/* WMI_TDLS_PEER_UPDATE_CMDID */
@@ -13703,6 +15760,8 @@
A_UINT32 pref_offchan_num;
/* Preferred off channel bandwidth as configured by user */
A_UINT32 pref_offchan_bw;
+ /* Preferred off channel frequency in MHz as configured by user */
+ A_UINT32 pref_offchan_freq;
/** Followed by the variable length TLV peer_chan_list:
* wmi_channel peer_chan_list[].
@@ -13840,14 +15899,16 @@
A_UINT32 offchan_mode;
/** peer MAC address */
wmi_mac_addr peer_macaddr;
- /* Is peer initiator or responder of TDLS setup request */
+ /* Is peer initiator or responder of TDLS setup request */
A_UINT32 is_peer_responder;
/* off channel number*/
A_UINT32 offchan_num;
/* off channel bandwidth bitmap, e.g. WMI_OFFCHAN_20MHZ */
A_UINT32 offchan_bw_bitmap;
- /* operating class for offchan */
- A_UINT32 offchan_oper_class;
+ /* operating class for offchan */
+ A_UINT32 offchan_oper_class;
+ /* off channel frequency in MHz */
+ A_UINT32 offchan_freq;
} wmi_tdls_set_offchan_mode_cmd_fixed_param;
@@ -14308,10 +16369,11 @@
A_UINT32 tlv_header;
wmi_mac_addr bssid; /* BSSID */
wmi_ssid ssid; /* SSID */
- A_UINT32 ch; /* Channel */
+ A_UINT32 ch; /* Channel number */
A_UINT32 rssi; /* RSSI or Level */
/* Timestamp when Network was found. Used to calculate age based on timestamp in GET_RSP msg header */
A_UINT32 timestamp;
+ A_UINT32 ch_freq; /* Channel frequency in MHz */
} wmi_batch_scan_result_network_info;
typedef struct
@@ -14429,7 +16491,7 @@
/**
* TLV (tag length value) parameters follow the scan_cmd
* structure. The TLV's are:
- * A_UINT32 channel_list[];
+ * A_UINT32 channel_list[]; // in MHz
* wmi_ssid ssid_list[];
* wmi_mac_addr bssid_list[];
* A_UINT8 ie_data[];
@@ -14802,6 +16864,16 @@
WMI_PEER_TID_CONFIG_RATE_CONTROL_AUTO,
/** Fixed rate control */
WMI_PEER_TID_CONFIG_RATE_CONTROL_FIXED_RATE,
+ /** Set the Default lowest rate (6Mbps in 5GHZ and 1Mbps in 2GHZ) */
+ WMI_PEER_TID_CONFIG_RATE_CONTROL_DEFAULT_LOWEST_RATE,
+ /**
+ * Set the highest rate cap allowed for this TID.
+ * Rate cap is specified in rate code format,
+ * i.e. NSS and MCS combined as shown below:
+ * b'5-b'4 indicate the NSS (0 - 1x1, 1 - 2x2, 2 - 3x3, 3 - 4x4)
+ * b'3-b'0 indicate the MCS
+ */
+ WMI_PEER_TID_CONFIG_RATE_UPPER_CAP,
} WMI_PEER_TID_CONFIG_RATE_CONTROL;
/**
@@ -14816,6 +16888,15 @@
WMI_PEER_TID_SW_RETRY_NO_RETRY = 0xFFFFFFFF,
} WMI_PEER_TID_CONFIG_SW_RETRY_THRESHOLD;
+/*
+ * values for tid_config_supported_bitmap field,
+ * in wmi_peer_tid_configurations_cmd structure.
+ */
+typedef enum {
+ /* Used to indicate that disable_rts_cts field is valid */
+ WMI_PEER_TID_DISABLE_RTS_CTS_VALID = 0x00000001,
+} WMI_PEER_TID_EXT_CONFIG_VALID_BITMAP;
+
/**
* Command format for the TID configuration
*/
@@ -14859,8 +16940,81 @@
* tx rate to use during each retransmission.
*/
A_UINT32 sw_retry_threshold;
+
+ /*--- Start of extended structure ---*/
+ /* Bitmap to indicate which fields in the extended structure are valid.
+ * Bitmap values correspond to enum WMI_PEER_TID_EXT_CONFIG_VALID_BITMAP
+ */
+ A_UINT32 tid_config_supported_bitmap;
+
+ /* Knob to enable/disable RTS/CTS per TID */
+ A_UINT32 disable_rts_cts;
} wmi_peer_tid_configurations_cmd_fixed_param;
+/* The below enable/disable macros are used for both per peer CFR capture
+ * control (as in wmi_peer_cfr_capture_cmd) and control of the entire periodic
+ * CFR capture feature (as in WMI_PDEV_PARAM_PER_PEER_PERIODIC_CFR_ENABLE)
+ */
+#define WMI_PEER_CFR_CAPTURE_ENABLE 1
+#define WMI_PEER_CFR_CAPTURE_DISABLE 0
+
+#define WMI_PEER_CFR_ONE_SHOT_REQUEST 0
+#define WMI_PEER_CFR_PERIODICITY_MIN 10 /* 10ms */
+#define WMI_PEER_CFR_PERIODICITY_MAX 10*60*1000 /* 10 minutes */
+
+/* Bandwidth of peer CFR captures */
+typedef enum {
+ WMI_PEER_CFR_CAPTURE_BW_20MHZ = 0,
+ WMI_PEER_CFR_CAPTURE_BW_40MHZ = 1,
+ WMI_PEER_CFR_CAPTURE_BW_80MHZ = 2,
+ WMI_PEER_CFR_CAPTURE_BW_160MHZ = 3,
+ WMI_PEER_CFR_CAPTURE_BW_80_80MHZ = 4,
+ WMI_PEER_CFR_CAPTURE_BW_MAX,
+} WMI_PEER_CFR_CAPTURE_BW;
+
+/* Peer CFR capture method */
+typedef enum {
+ /* Send null frame on the requested bw and capture CFR on ACK */
+ WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME = 0,
+ WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME_WITH_PHASE = 1,
+ WMI_PEER_CFR_CAPTURE_METHOD_PROBE_RESP = 2,
+ /* New methods to be added here */
+ WMI_PEER_CFR_CAPTURE_METHOD_MAX,
+} WMI_PEER_CFR_CAPTURE_METHOD;
+
+/*
+ * Peer command structure to configure the CFR capture
+ */
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_peer_cfr_capture_cmd_fixed_param
+ */
+ A_UINT32 tlv_header;
+
+ /* WMI_PEER_CFR_CAPTURE_ENABLE: Enable CFR capture for the peer
+ * WMI_PEER_CFR_CAPTURE_DISABLE: Disable CFR capture for the peer
+ */
+ A_UINT32 request;
+ /* Peer MAC address. In AP mode, this is the address of the connected peer
+ * for which CFR capture is needed. In case of STA mode, this is the address
+ * of the AP to which the STA is connected
+ */
+ wmi_mac_addr mac_addr;
+ /* vdev id */
+ A_UINT32 vdev_id;
+ /* Periodicity of measurement in ms.
+ * WMI_PEER_CFR_ONE_SHOT_REQUEST: One-shot request i.e., Only one CFR
+ * capture for the request and no periodic CFR captures.
+ * The min value is WMI_PEER_CFR_PERIODICITY_MIN
+ * The max value is WMI_PEER_CFR_PERIODICITY_MAX
+ */
+ A_UINT32 periodicity;
+ /* BW of measurement - of type WMI_PEER_CFR_CAPTURE_BW */
+ A_UINT32 bandwidth;
+ /* Method used to capture CFR - of type WMI_PEER_CFR_CAPTURE_METHOD */
+ A_UINT32 capture_method;
+} wmi_peer_cfr_capture_cmd_fixed_param;
+
typedef enum {
WMI_PEER_IND_SMPS = 0x0, /* spatial multiplexing power save */
WMI_PEER_IND_OMN, /* operating mode notification */
@@ -15024,6 +17178,10 @@
wmi_mac_addr next_hop_mac_addr;
} wmi_mhf_offload_routing_table_entry;
+enum {
+ WMI_DFS_RADAR_PULSE_FLAG_MASK_PSIDX_DIFF_VALID = 0x00000001,
+};
+
typedef struct {
/** tlv tag and len, tag equals
* WMITLV_TAG_STRUC_wmi_dfs_radar_event */
@@ -15085,6 +17243,16 @@
/** Max pulse chirp velocity variance in delta bins */
A_INT32 pulse_delta_diff;
+ /** the difference in the FFT peak index between short FFT and the first long FFT
+ * psidx_diff = (first_long_fft_psidx - 4*first_short_fft_psidx),
+ */
+ A_INT32 psidx_diff;
+
+ /** pulse_flags: see WMI_DFS_RADAR_PULSE_FLAG_MASK enum values
+ * 0x0001 - set if psidx_diff is valid
+ */
+ A_UINT32 pulse_flags;
+
} wmi_dfs_radar_event_fixed_param;
enum {
@@ -15445,6 +17613,27 @@
} wmi_oem_dma_buf_release_entry;
typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_oem_data_cmd_fixed_param */
+ A_UINT32 tlv_header;
+ /** Unique id identifying the VDEV */
+ A_UINT32 vdev_id;
+ /** Actual length in byte of data[]. */
+ A_UINT32 data_len;
+/** This structure is used to send OEM DATA binary blobs from
+ * application/service to firmware where Host driver is pass through.
+ * The OEM-specific commands from OEM-specific userspace applications
+ * are passed to OEM-specific feature handlers in firmware as OEM DATA
+ * binary blobs. The format of the data is per agreement between FW and
+ * userspace applications, with the binary blob beginning with a header
+ * that identifies to the FW the nature of the remaining data within the
+ * blob.
+ *
+ * Following this structure is the TLV:
+ * A_UINT8 data[]; <-- actual length in byte given by field data_len.
+ */
+} wmi_oem_data_cmd_fixed_param;
+
+typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_cmd_param */
A_UINT32 data_len; /** length in byte of data[]. */
/* This structure is used to send REQ binary blobs
@@ -15455,6 +17644,14 @@
} wmi_nan_cmd_param;
typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_host_config_param */
+ A_UINT32 nan_2g_disc_disable:1; /** This bit when set to 1 indicate NAN 2G discovery should be disabled */
+ A_UINT32 nan_5g_disc_disable:1; /** This bit when set to 1 indicate NAN 5G discovery should be disabled */
+ A_UINT32 reserved:30;
+} wmi_nan_host_config_param_PROTOTYPE;
+#define wmi_nan_host_config_param wmi_nan_host_config_param_PROTOTYPE
+
+typedef struct {
A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_event_hdr */
A_UINT32 data_len; /** length in byte of data[]. */
/* This structure is used to send REQ binary blobs
@@ -15464,6 +17661,15 @@
*/
} wmi_nan_event_hdr;
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_event_info */
+ A_UINT32 mac_id; /* MAC ID associated with NAN primary discovery channel; Valid only for NAN enable resp message identified by NAN_MSG_ID_ENABLE_RSP */
+ A_UINT32 status:1; /** This bit when set to 0 indicates status is successful; Valid only for NAN enable resp message identified by NAN_MSG_ID_ENABLE_RSP */
+ A_UINT32 reserved:31;
+} wmi_nan_event_info_PROTOTYPE;
+
+#define wmi_nan_event_info wmi_nan_event_info_PROTOTYPE
+
/**
* Event to indicate NAN discovery interface created
*/
@@ -15552,8 +17758,46 @@
WMI_NDP_FORCE_CHANNEL_SETUP = 2/* NDP must start on the provided channel */
} wmi_ndp_channel_cfg_PROTOTYPE;
+/*
+ * The WMI_NDP_IPV6_INTF_ADDR_LEN macro cannot be changed without breaking
+ * WMI compatibility.
+ */
+#define WMI_NDP_IPV6_INTF_ADDR_LEN 16
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_transport_ip_param */
+ /* Presence of ipv6_intf_addr */
+ A_UINT32 ipv6_addr_present;
+ /* Presence of transport Port */
+ A_UINT32 trans_port_present;
+ /* Presence of transport Protocol */
+ A_UINT32 trans_proto_present;
+ /* ipv6 Interface address */
+ A_UINT8 ipv6_intf_addr[WMI_NDP_IPV6_INTF_ADDR_LEN];
+ /* Transport Port */
+ A_UINT32 transport_port;
+ /* Transport Protocol */
+ A_UINT32 transport_protocol;
+} wmi_ndp_transport_ip_param;
+
#define wmi_ndp_channel_cfg wmi_ndp_channel_cfg_PROTOTYPE
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_channel_info */
+ A_UINT32 mac_id; /* mac_id associated with ndp channel at same index */
+} wmi_ndp_channel_info_PROTOTYPE;
+
+#define wmi_ndp_channel_info wmi_ndp_channel_info_PROTOTYPE
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_event_param */
+ A_UINT32 vdev_id; /* NDI VDEV ID */
+ A_UINT32 ndp_termination_in_progress:1; /** This bit when set to 1 indicates to termination of all NDPs associated with NDI vdev ID is started */
+ A_UINT32 reserved:31;
+} wmi_ndp_event_param_PROTOTYPE;
+
+#define wmi_ndp_event_param wmi_ndp_event_param_PROTOTYPE
+
/**
* NDP Initiator requesting a data session
*/
@@ -15591,6 +17835,7 @@
* A_UINT8 ndp_pmk[];
* A_INT8 ndp_passphrase[];
* A_INT8 nan_servicename[];
+ * wmi_ndp_transport_ip_param ndp_transport_ip_param;
*/
} wmi_ndp_initiator_req_fixed_param_PROTOTYPE;
@@ -15634,6 +17879,7 @@
* A_UINT8 ndp_pmk[];
* A_INT8 ndp_passphrase[];
* A_INT8 nan_servicename[];
+ * wmi_ndp_transport_ip_param ndp_transport_ip_param;
*/
} wmi_ndp_responder_req_fixed_param_PROTOTYPE;
@@ -15673,6 +17919,15 @@
#define wmi_ndp_end_req wmi_ndp_end_req_PROTOTYPE
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_ndp_cmd_param */
+ A_UINT32 vdev_id; /* NDI VDEV ID */
+ A_UINT32 ndp_disable:1; /** This bit when set to 1 indicates to terminate all NDPs associated with NDI vdev ID */
+ A_UINT32 reserved:31;
+} wmi_ndp_cmd_param_PROTOTYPE;
+
+#define wmi_ndp_cmd_param wmi_ndp_cmd_param_PROTOTYPE
+
/**
* NDP End request
*/
@@ -15769,6 +18024,7 @@
} wmi_ndp_responder_rsp_event_fixed_param_PROTOTYPE;
#define wmi_ndp_responder_rsp_event_fixed_param wmi_ndp_responder_rsp_event_fixed_param_PROTOTYPE
+
/**
* Active ndp instance id
*/
@@ -15883,6 +18139,7 @@
* A_UINT8 ndp_cfg[];
* A_UINT8 ndp_app_info[];
* A_UINT8 nan_scid[];
+ * wmi_ndp_transport_ip_param ndp_transport_ip_param;
*/
} wmi_ndp_indication_event_fixed_param_PROTOTYPE;
@@ -15924,6 +18181,7 @@
* wmi_channel ndp_channel_list[];
* A_UINT32 nss_list[]; // Nss indexing should match with channel indexing,
* // since Nss is associated with the channel
+ * wmi_ndp_transport_ip_param ndp_transport_ip_param;
*/
} wmi_ndp_confirm_event_fixed_param_PROTOTYPE;
@@ -16101,6 +18359,7 @@
WMI_SAR_FEATURE_NO_CHANGE,
WMI_SAR_FEATURE_ON_USER_DEFINED,
WMI_SAR_FEATURE_ON_SAR_V2_0,
+ WMI_SAR_FEATURE_ON_SAR_V3,
};
typedef struct {
@@ -16241,6 +18500,8 @@
(2) data/mgmt frame is received from roamed AP, which needs to return to host
*/
+#define GTK_OFFLOAD_KCK_EXTENDED_BYTES 32
+
typedef struct {
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material */
A_UINT32 tlv_header;
@@ -16251,6 +18512,16 @@
} wmi_key_material;
typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_key_material_ext */
+ A_UINT32 tlv_header;
+ /*
+ * key_buffer contains kck,kck2,kek,kek2,replay counter, in order
+ * The split between kck vs. kek should be known to host based on akmp.
+ */
+ A_UINT8 key_buffer[GTK_OFFLOAD_KEK_EXTENDED_BYTES+GTK_OFFLOAD_KCK_EXTENDED_BYTES+GTK_REPLAY_COUNTER_BYTES];
+} wmi_key_material_ext;
+
+typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_synch_event_fixed_param */
/** Unique id identifying the VDEV on which roaming is done by firmware */
A_UINT32 vdev_id;
@@ -16285,7 +18556,7 @@
* A_UINT32 status; subnet changed status not being used currently.
* will pass the information using roam_status.
* A_UINT8 reassoc_req_frame[]; length identified by reassoc_req_len
- *
+ * wmi_key_material_ext key_ext
**/
} wmi_roam_synch_event_fixed_param;
@@ -16383,6 +18654,20 @@
} wmi_peer_delete_resp_event_fixed_param;
typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_delete_all_peer_resp_event_fixed_param */
+ /** unique id identifying the VDEV, generated by the caller */
+ A_UINT32 vdev_id;
+ /* Status of peer delete all command */
+ /*
+ * Values for Status:
+ * 0 - OK; command successful
+ * 1 - EINVAL; Requested invalid vdev_id
+ * 2 - EFAILED; Delete all peer failed
+ */
+ A_UINT32 status;
+} wmi_vdev_delete_all_peer_resp_event_fixed_param;
+
+typedef struct {
/* TLV tag and len; tag equals WMITLV_TAG_STRUC_ wmi_peer_state_event_fixed_param */
A_UINT32 tlv_header;
A_UINT32 vdev_id; /* vdev ID */
@@ -16446,10 +18731,17 @@
/** following two parameters used by FW to fill IEs when sending 20/40 coexistence action frame to AP */
A_UINT32 forty_mhz_intolerant; /** STA 40M bandwidth intolerant capability */
A_UINT32 current_operating_class; /** STA current operating class */
- /** length of 2.4GHz channel list to scan at, channel list in tlv->channels[] */
+ /** length of 2.4GHz channel list to scan at, channel number list in tlv->channels[] */
A_UINT32 channel_len;
/** length of optional ie data to append to probe reqest when active scan, ie data in tlv->ie_field[] */
A_UINT32 ie_len;
+
+/**
+ * TLV (tag length value) parameters following the fixed param structure
+ * A_UINT8 channels[channel_len]; // channel numbers
+ * A_UINT8 ie_field[ie_len];
+ * A_UINT32 chan_freqs[channel_len] // in MHz
+ */
} wmi_obss_scan_enable_cmd_fixed_param;
typedef struct {
@@ -16565,7 +18857,7 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */
- /** channel number */
+ /** channel in MHz */
A_UINT32 channel;
/** dwell time in msec - use defaults if 0 */
@@ -16751,13 +19043,13 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */
- /**bssid */
+ /** bssid */
wmi_mac_addr bssid;
- /**channel number */
+ /** channel in MHz */
A_UINT32 channel;
- /**upper RSSI limit */
+ /** upper RSSI limit */
A_UINT32 upper_rssi_limit;
- /**lower RSSI limit */
+ /** lower RSSI limit */
A_UINT32 lower_rssi_limit;
} wmi_extscan_wlan_change_bssid_param;
@@ -16796,11 +19088,11 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */
- /**bssid */
+ /** bssid */
wmi_mac_addr bssid;
- /**RSSI min threshold for reporting */
+ /** RSSI min threshold for reporting */
A_UINT32 min_rssi;
- /**Deprecated entry - channel number */
+ /** Deprecated entry - channel in MHz */
A_UINT32 channel;
/** RSSI max threshold for reporting */
A_UINT32 max_rssi;
@@ -17029,25 +19321,25 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_ARRAY_STRUC */
- /**bssid */
+ /** bssid */
wmi_mac_addr bssid;
- /**ssid */
+ /** ssid */
wmi_ssid ssid;
- /**channel number */
+ /** channel in MHz */
A_UINT32 channel;
- /* capabilities */
+ /** capabilities */
A_UINT32 capabilities;
- /* beacon interval in TUs */
+ /** beacon interval in TUs */
A_UINT32 beacon_interval;
- /**time stamp in milliseconds - time last seen */
+ /** time stamp in milliseconds - time last seen */
A_UINT32 tstamp;
- /**flags - _tExtScanEntryFlags */
+ /** flags - _tExtScanEntryFlags */
A_UINT32 flags;
- /**RTT in ns */
+ /** RTT in ns */
A_UINT32 rtt;
- /**rtt standard deviation */
+ /** rtt standard deviation */
A_UINT32 rtt_sd;
- /* rssi information */
+ /** rssi information */
A_UINT32 number_rssi_samples;
/** IE length */
A_UINT32 ie_length; /* length of IE data */
@@ -18554,6 +20846,22 @@
A_UINT32 qtimer_low;
/* high 32 bits of qtimer */
A_UINT32 qtimer_high;
+ /*
+ * tsf_id: TSF ID for the current vdev
+ * This field should be ignored unless the tsf_id_valid flag is set.
+ */
+ A_UINT32 tsf_id;
+ A_UINT32 tsf_id_valid;
+ /*
+ * mac_id: MAC identifier
+ * This field should be ignored unless the mac_id_valid flag is set.
+ */
+ A_UINT32 mac_id;
+ A_UINT32 mac_id_valid;
+ /* low 32 bits of wlan global tsf */
+ A_UINT32 wlan_global_tsf_low;
+ /* high 32 bits of wlan global tsf */
+ A_UINT32 wlan_global_tsf_high;
} wmi_vdev_tsf_report_event_fixed_param;
/* ie_id values:
@@ -18959,6 +21267,11 @@
A_UINT32 queue_ptr_hi; /* upper 32 bits of queue desc adddress */
A_UINT32 queue_no; /* 16-bit number assigned by host for queue,
stored in bits 15:0 of queue_no field */
+ A_UINT32 ba_window_size_valid; /* Is ba_window_size valid?
+ * 0 = Invalid, 1 = Valid */
+ A_UINT32 ba_window_size; /* Valid values: 0 to 256
+ * Host sends the message when BA session is
+ * established or terminated for the TID. */
} wmi_peer_reorder_queue_setup_cmd_fixed_param;
/**
@@ -19440,6 +21753,12 @@
* byte 40
*/
A_UINT32 toeplitz_hash_ipv6_40;
+
+ /**
+ * @brief pdev_id - identifies the MAC
+ * See macros starting with WMI_PDEV_ID_ for values.
+ */
+ A_UINT32 pdev_id;
} wmi_lro_info_cmd_fixed_param;
typedef struct {
@@ -20088,6 +22407,31 @@
} wmi_pdev_get_chip_power_stats_cmd_fixed_param;
typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_bcn_recv_stats_cmd_fixed_param */
+ /** VDEV identifier */
+ A_UINT32 vdev_id;
+} wmi_vdev_get_bcn_recv_stats_cmd_fixed_param;
+
+/*
+ * wmi mws-coex command IDs
+ */
+typedef enum {
+ WMI_MWS_COEX_STATE = 0x01,
+ WMI_MWS_COEX_DPWB_STATE,
+ WMI_MWS_COEX_TDM_STATE,
+ WMI_MWS_COEX_IDRX_STATE,
+ WMI_MWS_COEX_ANTENNA_SHARING_STATE,
+} wmi_mws_coex_cmd_id;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_state_cmd_fixed_param */
+ /** VDEV identifier */
+ A_UINT32 vdev_id;
+ /** Command ID (type: wmi_mws_coex_cmd_id) */
+ A_UINT32 cmd_id;
+} wmi_vdev_get_mws_coex_info_cmd_fixed_param;
+
+typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_tpc_event_fixed_param */
/** pdev_id for identifying the MAC
* See macros starting with WMI_PDEV_ID_ for values.
@@ -20179,6 +22523,317 @@
*/
} wmi_pdev_chip_power_stats_event_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_bcn_recv_stats_fixed_param */
+ A_UINT32 vdev_id;
+ /* total_bcn_cnt
+ * total beacon count (tbtt instances)
+ * After this value reaches 255 it saturates and stays at 255.
+ * This field is used to determine which of the 256 bits in the
+ * bmiss_bitmap field are valid.
+ */
+ A_UINT32 total_bcn_cnt;
+ /* total_bmiss_cnt
+ * Total beacon miss count in last 255 beacons, max value is 255.
+ * This value is the number of bits set within bmiss_bitmap.
+ */
+ A_UINT32 total_bmiss_cnt;
+ /* bmiss_bitmap
+ * This bitmap indicates the status of the last 255 beacons.
+ * If a bit is set, that means the corresponding beacon was missed.
+ * Bit 0 of bmiss_bitmap[0] represents the most recent beacon.
+ * The total_bcn_cnt field indicates how many bits within bmiss_bitmap
+ * are valid.
+ */
+ A_UINT32 bmiss_bitmap[8];
+} wmi_vdev_bcn_recv_stats_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_state_fixed_param */
+ A_UINT32 vdev_id;
+
+ /* LTE-WLAN coexistence scheme bitmap
+ * Indicates the final schemes applied for the currrent Coex scenario.
+ * Bit 0 - TDM policy
+ * Bit 1 - Forced TDM policy
+ * Bit 2 - Dynamic Power Back-off policy
+ * Bit 3 - Channel Avoidance policy
+ * Bit 4 - Static Power Back-off policy
+ */
+ A_UINT32 coex_scheme_bitmap;
+
+ /* Active conflict count
+ * Indicates the number of Active conflicts for the current WLAN and LTE frequency combinations.
+ */
+ A_UINT32 active_conflict_count;
+
+ /* Potential conflict count
+ * Indicates the number of Potential conflicts for the current WLAN and LTE frequency combinations.
+ */
+ A_UINT32 potential_conflict_count;
+
+ /* Bitmap of the group-0 WLAN channels to be avoided during LTE-WLAN coex operation.
+ * Indicates the WLAN channels to be avoided in b/w WLAN CH-1 and WLAN CH-14.
+ */
+ A_UINT32 chavd_group0_bitmap;
+
+ /* Bitmap of the group-1 WLAN channels to be avoided during LTE-WLAN coex operation.
+ * Indicates the WLAN channels to be avoided in b/w WLAN CH-36 and WLAN CH-64.
+ */
+ A_UINT32 chavd_group1_bitmap;
+
+ /* Bitmap of the group-2 WLAN channels to be avoided during LTE-WLAN coex operation.
+ * Indicates the WLAN channels to be avoided in b/w WLAN CH-100 and WLAN CH-140.
+ */
+ A_UINT32 chavd_group2_bitmap;
+
+ /* Bitmap of the group-3 WLAN channels to be avoided during LTE-WLAN coex operation.
+ * Indicates the WLAN channels to be avoided in b/w WLAN CH-149 and WLAN CH-165.
+ */
+ A_UINT32 chavd_group3_bitmap;
+} wmi_vdev_get_mws_coex_state_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_dpwb_state_fixed_param */
+ A_UINT32 vdev_id;
+
+ /* Current state of the Dynamic Power Back-off state machine
+ * MWSCOEX_PWB_UNINIT_STATE = 0, PWB state machine is in un-intialized state.
+ * MWSCOEX_PWB_WLAN_ON_SINR_START_STATE = 1, SINR measurement starts when WLAN is on
+ * MWSCOEX_PWB_WLAN_ON_WAIT_RESP_STATE = 2, Waiting for SINR response when WLAN is on
+ * MWSCOEX_PWB_WLAN_OFF_AWAIT_STATE = 3, WLAN off state for buffer between SINR on/off measurement.
+ * MWSCOEX_PWB_WLAN_OFF_SINR_START_STATE = 4, SINR measurement starts when WLAN is off
+ * MWSCOEX_PWB_WLAN_OFF_WAIT_RESP_STATE = 5, Waiting for SINR response when WLAN is off
+ * MWSCOEX_PWB_WLAN_OFF_SINR_STOP_STATE = 6, SINR measurement stops when WLAN is off
+ * MWSCOEX_PWB_FORCED_TDM_STATE = 7, Entered Forced TDM state.
+ * MWSCOEX_PWB_HALTED_STATE = 8, Power back-off algorithm halted.
+ * MWSCOEX_PWB_WLAN_ALWAYS_ON_SINR_START_STATE = 9, SINR measurement starts in WLAN always on state.
+ * MWSCOEX_PWB_WLAN_ALWAYS_ON_SINR_STOP_STATE = 10, SINR measurement stops in WLAN always on state.
+ */
+ A_UINT32 current_dpwb_state;
+
+ /* P(N+1) value in dBm i.e. Tx power to be applied in the next Dynamic Power Back-off cycle,
+ * where P(N) is the power applied during current cycle.
+ * ranges from 3dBm to 21 dBM
+ */
+ A_INT32 pnp1_value;
+
+ /* Indicates the duty cycle of current LTE frame.
+ * Duty cycle: Number of UL slots with uplink data and allocated RBs.
+ */
+ A_UINT32 lte_dutycycle;
+
+ /* LTE SINR value in dB, when WLAN is ON. */
+ A_INT32 sinr_wlan_on;
+
+ /* LTE SINR value in dB, when WLAN is OFF. */
+ A_INT32 sinr_wlan_off;
+
+ /* LTE blocks with error for the current bler report.
+ * Number of LTE blocks with error for a given number (block_count) of LTE blocks.
+ */
+ A_UINT32 bler_count;
+
+ /* Number of LTE blocks considered for bler count report.
+ * Bler repot will be generated after the reception of every "block_count" number of blocks.
+ */
+ A_UINT32 block_count;
+
+ /* WLAN RSSI level
+ * WLAN RSSI is devided in to 3 levels i.e. Good/Moderate/Low (configurable inside f/w)
+ * 0-Good, 1-Moderate, 2-Low
+ */
+ A_UINT32 wlan_rssi_level;
+
+ /* WLAN RSSI value in dBm considered in Dynamic Power back-off algorithm
+ * Dynamic power back-off algorithm considers either Rx data frame RSSI/Beacon RSSI based on some constraints.
+ */
+ A_INT32 wlan_rssi;
+
+ /* Indicates whether any TDM policy triggered from Dynamic power back-off policy.
+ * 1 - TDM triggered.
+ * 0 - TDM not triggered.
+ */
+ A_UINT32 is_tdm_running;
+} wmi_vdev_get_mws_coex_dpwb_state_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_tdm_state_fixed_param */
+ A_UINT32 vdev_id;
+ /* Time Division Multiplexing (TDM) LTE-Coex Policy type.
+ * There are totally 4 types of TDM policies(1-SINR TDM, 2-RSSI TDM, 3-LOW RX RATE TDM, 4-STICKY TDM)
+ * Bit 0 - SINR TDM policy.
+ * Bit 1 - RSSI TDM policy.
+ * Bit 2 - Low Rx rate TDM policy
+ * Bit 3 - Sticky TDM policy
+ */
+ A_UINT32 tdm_policy_bitmap;
+
+ /* TDM LTE/WLAN sub-frame bitmap
+ * Indicates the bitmap of LTE/WLAN sub-frames.
+ * value 0: WLAN slot.
+ * value 1: LTE slot.
+ */
+ A_UINT32 tdm_sf_bitmap;
+} wmi_vdev_get_mws_coex_tdm_state_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_idrx_state_fixed_param */
+ A_UINT32 vdev_id;
+
+ /* SUB0 LTE-coex tech.
+ *------------------------
+ * TECH TECH_ID
+ *------------------------
+ * LTE 0
+ * TDSCDMA 1
+ * GSM1 2
+ * ONEX 3
+ * HDR 4
+ * WCDMA 5
+ * GSM2 6
+ * GSM3 7
+ * WCDMA2 8
+ * LTE2 9
+ * Indicates the type of WWAN technology used as SUB0 i.e. SIM slot 1
+ */
+ A_UINT32 sub0_techid;
+
+ /* SUB0 mitigation policy.
+ * Indicates the mitigation policy used to coexist with WLAN.
+ * 1 - Tx blanking
+ * 2 - Static power back-off
+ */
+ A_UINT32 sub0_policy;
+
+ /* Set if SUB0 is in link critical state.
+ * Link critical will be set, if continuous page miss happens or RSSI is below -100 dBm at LTE side.
+ */
+ A_UINT32 sub0_is_link_critical;
+
+ /* LTE SUB0 imposed static power applied to WLAN due to LTE-WLAN coex.
+ * Value of static power applied during LTE page cycle ranges from 3-21 dBm.
+ */
+ A_INT32 sub0_static_power;
+
+ /* LTE SUB0 RSSI value in dBm */
+ A_INT32 sub0_rssi;
+
+ /* SUB1 LTE-coex tech.
+ *------------------------
+ * TECH TECH_ID
+ *------------------------
+ * LTE 0
+ * TDSCDMA 1
+ * GSM1 2
+ * ONEX 3
+ * HDR 4
+ * WCDMA 5
+ * GSM2 6
+ * GSM3 7
+ * WCDMA2 8
+ * LTE2 9
+ * Indicates the type of WWAN technology used as SUB1 i.e. SIM slot 2
+ */
+ A_UINT32 sub1_techid;
+
+ /* SUB1 mitigation policy.
+ * Indicates the mitigation policy used to coexist with WLAN.
+ * 1 - Tx blanking
+ * 2 - Static power back-off
+ */
+ A_UINT32 sub1_policy;
+
+ /* Set if SUB1 is in link critical state.
+ * Link critical will be set, if continuous page miss happens or RSSI is below -100 dBm at LTE side.
+ */
+ A_UINT32 sub1_is_link_critical;
+
+ /* LTE SUB1 imposed static power applied to WLAN due to LTE-WLAN coex.
+ * Value of static power applied during LTE page cycle ranges from 3-21 dBm.
+ */
+ A_INT32 sub1_static_power;
+
+ /* LTE SUB1 RSSI value in dBm */
+ A_INT32 sub1_rssi;
+} wmi_vdev_get_mws_coex_idrx_state_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_mws_coex_antenna_sharing_state_fixed_param */
+ A_UINT32 vdev_id;
+
+ /* BDF values of Coex flags.
+ * coexflag 0x1 = MWS Coex enabled
+ * coexflag 0x3 = MWS Coex enabled + Antenna sharing enabled for WLAN operating in 2.4GHz band.
+ */
+ A_UINT32 coex_flags;
+
+ /* BDF values of Coex Antenna sharing config
+ * coex_config 0x0 = no Antenna sharing
+ * coexconfig 0x1 = switched based Antenna sharing
+ * coexconfig 0x2 = splitter based Antenna sharing
+ */
+ A_UINT32 coex_config;
+
+ /* Tx Chain mask value
+ * Bit 0: Tx chain-0
+ * Bit 1: Tx Chain-1
+ * value: 0x1 - Operating in 1X1
+ * value: 0x3 - Operating in 2X2
+ */
+ A_UINT32 tx_chain_mask;
+
+ /* Rx Chain mask value
+ * Bit 0: Rx chain-0
+ * Bit 1: Rx Chain-1
+ * value: 0x1 - Operating in 1X1
+ * value: 0x3 - Operating in 2X2
+ */
+ A_UINT32 rx_chain_mask;
+
+ /* Currently active Rx Spatial streams
+ * Bit 0: Rx Spatial Stream-0
+ * Bit 1: Rx Spatial Stream-1
+ */
+ A_UINT32 rx_nss;
+
+ /* Forced MRC policy type
+ * BTC_FORCED (0x01)
+ * RSSI_FORCED (0x02)
+ * MODEM_ACQ_FORCED (0x04)
+ */
+ A_UINT32 force_mrc;
+
+ /* RSSI value considered for MRC
+ * 1: Data RSSI
+ * 2: Beacon RSSI
+ */
+ A_UINT32 rssi_type;
+
+ /* RSSI value measured at Chain-0 in dBm */
+ A_INT32 chain0_rssi;
+
+ /* RSSI value measured at Chain-1 in dBm */
+ A_INT32 chain1_rssi;
+
+ /* RSSI value of two chains combined in dBm */
+ A_INT32 combined_rssi;
+
+ /* Absolute imbalance between two Rx chains in dB */
+ A_UINT32 imbalance;
+
+ /* RSSI threshold defined for the above imbalance value in dBm.
+ * Based on the degree of imbalance between the rx chains, different
+ * RSSI thresholds are used to determine whether MRC (Maximum-Ratio
+ * Combining) use of multiple rx chains is suitable.
+ * This field shows the RSSI threshold below which MRC is used.
+ */
+ A_INT32 mrc_threshold;
+
+ /* Antenna grant duration to WLAN, in milliseconds */
+ A_UINT32 grant_duration;
+} wmi_vdev_get_mws_coex_antenna_sharing_state_fixed_param;
+
typedef enum wmi_chip_power_save_failure_reason_code_type {
WMI_PROTOCOL_POWER_SAVE_FAILURE_REASON,
WMI_HW_POWER_SAVE_FAILURE_REASON,
@@ -20254,6 +22909,101 @@
arg2-arg5: BT information parameters */
WMI_COEX_CONFIG_SINK_WLAN_TDM = 21, /* config interval (ms units) (arg1 BT, arg2 WLAN) for A2DP SINK + WLAN */
WMI_COEX_CONFIG_COEX_ENABLE_MCC_TDM = 22, /* config disable/enable COEX TDM for MCC */
+ WMI_COEX_CONFIG_LOWRSSI_A2DPOPP_TDM = 23, /* config interval (ms units) (arg1 BT, arg2 WLAN) for STA + A2dp + OPP + LOWRSSI */
+ WMI_COEX_CONFIG_BTC_MODE = 24, /* config BTC mode, arg1 mode: 0 TDD/1 FDD/2 Hybrid*/
+ WMI_COEX_CONFIG_ANTENNA_ISOLATION = 25, /* config isolation between BT and WLAN chains
+ * The arguments are interpreted differently
+ * depending on whether the target suppports
+ * WMI_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION
+ * If (not COEX_SUPPORT_UNEQUAL_ISOLATION) or arg2 == 0:
+ * arg1 => isolation between BT and WLAN chains,
+ * dB units,
+ * same isolation for all chains
+ * Else:
+ * arg1 bits 7:0 - chain 0 isolation, in dB
+ * arg1 bits 15:8 - chain 1 isolation, in dB
+ * arg1 bits 23:16 - chain 2 isolation, in dB
+ * arg1 bits 31:24 - chain 3 isolation, in dB
+ * arg2 - 0 => Equal isolation b/w BT and each WLAN chain (default)
+ * 1 => Different isolation b/w BT and each WLAN chain
+ */
+ WMI_COEX_CONFIG_BT_LOW_RSSI_THRESHOLD = 26,/*config BT low rssi threshold (dbm units)*/
+ WMI_COEX_CONFIG_BT_INTERFERENCE_LEVEL = 27,/*config bt interference level (dbm units)
+ arg1 low - lower limit
+ arg2 low - upper limit
+ arg3 medium - lower limit
+ arg4 medium - upper limit
+ arg5 high - lower limit
+ arg6 high - upper limit */
+ WMI_COEX_CONFIG_WLAN_OVER_ZBLOW = 28, /* config to boost WiFi traffic over 15.4 Low prio traffic */
+ WMI_COEX_CONFIG_WLAN_MGMT_OVER_BT_A2DP = 29, /* config to raise WLAN priority higher than BT in coex scenario of SAP + BT or 15.4 */
+ WMI_COEX_CONFIG_WLAN_CONN_OVER_LE = 30, /* config to elevate Wifi priority over BLE during WLAN association */
+ WMI_COEX_CONFIG_LE_OVER_WLAN_TRAFFIC = 31, /* config to elevate BLE traffic over WiFi traffic */
+ WMI_COEX_CONFIG_THREE_WAY_COEX_RESET = 32, /* config to reset the weights to default */
+ /* WMI_COEX_CONFIG_THREE_WAY_DELAY_PARA
+ * config to T_PRIO T_DELAY parameter for each case
+ * arg1 - wlan/bt state
+ * 0: beacon tx
+ * 1: wlan connecting
+ * 2: wlan in dhcp
+ * 3: a2dp critical
+ * 4: eSCO
+ * arg2 - t_prio for low priority traffic (microsecond units)
+ * arg3 - t_delay for low priority traffic (microsecond units)
+ * arg4 - t_prio for high priority traffic (microsecond units)
+ * arg5 - t_delay for high priority traffic (microsecond units)
+ */
+ WMI_COEX_CONFIG_THREE_WAY_DELAY_PARA = 33,
+ /* WMI_COEX_CONFIG_THREE_WAY_COEX_START
+ * config to set coex parameters from WLAN host to adjust priorities
+ * among wlan/bt/zb
+ * arg1 - priority level 1, the serialized coex scenorio ID will be put here
+ * arg2 - priority level 2, same parameters rules as arg1
+ * arg3 - priority level 3, same parameters rules as arg1
+ * arg4 - priority level 4, same parameters rules as arg1
+ */
+ WMI_COEX_CONFIG_THREE_WAY_COEX_START = 34,
+ /* WMI_COEX_CONFIG_MPTA_HELPER_ENABLE
+ * config to enable(1)/disable(0) mpta-helper function
+ */
+ WMI_COEX_CONFIG_MPTA_HELPER_ENABLE = 35,
+ /* WMI_COEX_CONFIG_MPTA_HELPER_ZIGBEE_STATE
+ * config zigbee state
+ * arg1: zigbee state
+ * (idle form-network wait-join join-network network-up HMI)
+ */
+ WMI_COEX_CONFIG_MPTA_HELPER_ZIGBEE_STATE = 36,
+ /* WMI_COEX_CONFIG_MPTA_HELPER_INT_OCS_PARAMS
+ * config ocs wlan/nonwlan params after MPTA interrupt fired
+ * arg1: wlan duration (ms units) in Shape-OCS
+ * arg2: nonwlan duration (ms units) in Shape-OCS
+ */
+ WMI_COEX_CONFIG_MPTA_HELPER_INT_OCS_PARAMS = 37,
+ /* WMI_COEX_CONFIG_MPTA_HELPER_MON_OCS_PARAMS
+ * config ocs wlan/nonwlan params during monitor period after
+ * interrupt period finished
+ * arg1: wlan duration (ms units) in Shape-OCS
+ * arg2: nonwlan duration (ms units) in Shape-OCS
+ */
+ WMI_COEX_CONFIG_MPTA_HELPER_MON_OCS_PARAMS = 38,
+ /* WMI_COEX_CONFIG_MPTA_HELPER_INT_MON_DURATION
+ * config ocs duration in interrupt period and monitor period
+ * arg1: duration (ms units) in interrupt period
+ * arg2: duration (ms units) in monitor period
+ */
+ WMI_COEX_CONFIG_MPTA_HELPER_INT_MON_DURATION = 39,
+ /* WMI_COEX_CONFIG_MPTA_HELPER_ZIGBEE_CHANNEL
+ * config zigbee channel 11 - 26
+ */
+ WMI_COEX_CONFIG_MPTA_HELPER_ZIGBEE_CHANNEL = 40,
+ /* WMI_COEX_CONFIG_MPTA_HELPER_WLAN_MUTE_DURATION
+ * config msw mute duration (ms units) after MPTA interrupt fired
+ */
+ WMI_COEX_CONFIG_MPTA_HELPER_WLAN_MUTE_DURATION = 41,
+ /* WMI_COEX_CONFIG_BT_SCO_ALLOW_WLAN_2G_SCAN
+ * allow WLAN scan on 2.4G channel when BT SCO connectivity is alive
+ */
+ WMI_COEX_CONFIG_BT_SCO_ALLOW_WLAN_2G_SCAN = 42,
} WMI_COEX_CONFIG_TYPE;
typedef struct {
@@ -20556,7 +23306,19 @@
* - 0 indicates support for VHT-MCS 0-7 for n spatial streams
* - 1 indicates support for VHT-MCS 0-8 for n spatial streams
* - 2 indicates support for VHT-MCS 0-9 for n spatial streams
- * - 3 indicates that n spatial streams is not supported */
+ * - 3 indicates that n spatial streams is not supported
+ * - bit [15:0] Each NSS takes 2 bit.
+ * - bit [23:16] Indicates support for VHT-MCS 10 and 11 for
+ * n spatial streams
+ * - bit 16 - for NSS 1
+ * - bit 17 - for NSS 2
+ * - .
+ * - .
+ * - bit 23 - for NSS 8
+ * - bit 24 - indicate whether the VHT-MCS 10-11 specs in bits 23:16
+ * are valid
+ * Refer to the WMI_VHT_MAX_MCS_EXT_SS_GET/SET macros.
+ */
A_UINT32 vht_supp_mcs_2G;
/*HE capability info field of 802.11ax, WMI_HE_CAP defines */
A_UINT32 he_cap_info_2G;
@@ -20584,11 +23346,23 @@
/* VHT capability info field of 802.11ac, WMI_VHT_CAP defines */
A_UINT32 vht_cap_info_5G;
/* VHT Supported MCS Set field Rx/Tx same
- * The max VHT-MCS for n SS subfield (where n = 1,...,8) is encoded as follows
- * - 0 indicates support for VHT-MCS 0-7 for n spatial streams
- * - 1 indicates support for VHT-MCS 0-8 for n spatial streams
- * - 2 indicates support for VHT-MCS 0-9 for n spatial streams
- * - 3 indicates that n spatial streams is not supported */
+ * The max VHT-MCS for n SS subfield (where n = 1,...,8) is encoded as follows
+ * - 0 indicates support for VHT-MCS 0-7 for n spatial streams
+ * - 1 indicates support for VHT-MCS 0-8 for n spatial streams
+ * - 2 indicates support for VHT-MCS 0-9 for n spatial streams
+ * - 3 indicates that n spatial streams is not supported
+ * - bit [15:0] Each NSS takes 2 bit.
+ * - bit [23:16] Indicates support for VHT-MCS 10 and 11 for
+ * n spatial streams
+ * - bit 16 - for NSS 1
+ * - bit 17 - for NSS 2
+ * - .
+ * - .
+ * - bit 23 - for NSS 8
+ * - bit 24 - indicate whether the VHT-MCS 10-11 specs in bits 23:16
+ * are valid
+ * Refer to the WMI_VHT_MAX_MCS_EXT_SS_GET/SET macros.
+ */
A_UINT32 vht_supp_mcs_5G;
/*HE capability info field of 802.11ax, WMI_HE_CAP defines */
A_UINT32 he_cap_info_5G;
@@ -20622,6 +23396,23 @@
A_UINT32 chainmask_table_id;
/* PDEV ID to LMAC ID mapping */
A_UINT32 lmac_id;
+ /* 2nd DWORD of HE capability info field of 802.11ax, support Draft 3+ */
+ A_UINT32 he_cap_info_2G_ext;
+ A_UINT32 he_cap_info_5G_ext;
+ /*
+ * bit 0 : Indicated support for RX 1xLTF + 0.4us
+ * bit 1 : Indicates support for RX 2xLTF + 0.4us
+ * bit 2 : Indicates support for 2xLTF in 160/80+80 MHz HE PPDU
+ * bit[31:3] : Reserved
+ * Refer to WMI_HE_CAP_xx_LTF_xxx_SUPPORT_GET/SET macros
+ */
+ A_UINT32 he_cap_info_internal;
+
+ A_UINT32 wireless_modes; /* REGDMN MODE, see REGDMN_MODE_ enum */
+ A_UINT32 low_2ghz_chan_freq; /* units = MHz */
+ A_UINT32 high_2ghz_chan_freq; /* units = MHz */
+ A_UINT32 low_5ghz_chan_freq; /* units = MHz */
+ A_UINT32 high_5ghz_chan_freq; /* units = MHz */
} WMI_MAC_PHY_CAPABILITIES;
typedef struct {
@@ -20751,10 +23542,10 @@
A_UINT32 regcap2;
/* REGDMN MODE, see REGDMN_MODE_ enum */
A_UINT32 wireless_modes;
- A_UINT32 low_2ghz_chan;
- A_UINT32 high_2ghz_chan;
- A_UINT32 low_5ghz_chan;
- A_UINT32 high_5ghz_chan;
+ A_UINT32 low_2ghz_chan; /* freq in MHz */
+ A_UINT32 high_2ghz_chan; /* freq in MHz */
+ A_UINT32 low_5ghz_chan; /* freq in MHz */
+ A_UINT32 high_5ghz_chan; /* freq in MHz */
} WMI_HAL_REG_CAPABILITIES_EXT;
typedef struct {
@@ -21012,6 +23803,8 @@
WMI_RETURN_STRING(WMI_PEER_CREATE_CMDID);
/** delete a peer */
WMI_RETURN_STRING(WMI_PEER_DELETE_CMDID);
+ /** delete all peer (excluding bss peer) */
+ WMI_RETURN_STRING(WMI_VDEV_DELETE_ALL_PEER_CMDID);
/** flush specific tid queues of a peer */
WMI_RETURN_STRING(WMI_PEER_FLUSH_TIDS_CMDID);
/** set a parameter of a peer */
@@ -21029,6 +23822,8 @@
WMI_RETURN_STRING(WMI_PEER_MCAST_GROUP_CMDID);
/* request peer info from FW to get PEER_INFO_EVENTID */
WMI_RETURN_STRING(WMI_PEER_INFO_REQ_CMDID);
+ /* unmap response for a peer */
+ WMI_RETURN_STRING(WMI_PEER_UNMAP_RESPONSE_CMDID);
/* beacon/management specific commands */
@@ -21542,6 +24337,40 @@
WMI_RETURN_STRING(WMI_TWT_RESUME_DIALOG_CMDID);
WMI_RETURN_STRING(WMI_REQUEST_ROAM_SCAN_STATS_CMDID);
WMI_RETURN_STRING(WMI_PEER_TID_CONFIGURATIONS_CMDID);
+ WMI_RETURN_STRING(WMI_VDEV_SET_CUSTOM_SW_RETRY_TH_CMDID);
+ WMI_RETURN_STRING(WMI_GET_TPC_POWER_CMDID);
+ WMI_RETURN_STRING(WMI_MOTION_DET_CONFIG_PARAM_CMDID);
+ WMI_RETURN_STRING(WMI_MOTION_DET_BASE_LINE_CONFIG_PARAM_CMDID);
+ WMI_RETURN_STRING(WMI_MOTION_DET_START_STOP_CMDID);
+ WMI_RETURN_STRING(WMI_MOTION_DET_BASE_LINE_START_STOP_CMDID);
+ WMI_RETURN_STRING(WMI_SAR_LIMITS_CMDID);
+ WMI_RETURN_STRING(WMI_SAR_GET_LIMITS_CMDID);
+ WMI_RETURN_STRING(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID);
+ WMI_RETURN_STRING(WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID);
+ WMI_RETURN_STRING(WMI_PDEV_HE_TB_ACTION_FRM_CMDID);
+ WMI_RETURN_STRING(WMI_HPCS_PULSE_START_CMDID);
+ WMI_RETURN_STRING(WMI_VDEV_CHAINMASK_CONFIG_CMDID);
+ WMI_RETURN_STRING(WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID);
+ WMI_RETURN_STRING(WMI_NDP_CMDID);
+ WMI_RETURN_STRING(WMI_PDEV_PKTLOG_FILTER_CMDID);
+ WMI_RETURN_STRING(WMI_SET_CURRENT_COUNTRY_CMDID);
+ WMI_RETURN_STRING(WMI_VDEV_GET_BCN_RECEPTION_STATS_CMDID);
+ WMI_RETURN_STRING(WMI_PEER_TX_PN_REQUEST_CMDID);
+ WMI_RETURN_STRING(WMI_ROAM_BSS_LOAD_CONFIG_CMDID);
+ WMI_RETURN_STRING(WMI_VDEV_GET_MWS_COEX_INFO_CMDID);
+ WMI_RETURN_STRING(WMI_REQUEST_WLM_STATS_CMDID);
+ WMI_RETURN_STRING(WMI_PDEV_SET_RAP_CONFIG_CMDID);
+ WMI_RETURN_STRING(WMI_STA_TDCC_CONFIG_CMDID);
+ WMI_RETURN_STRING(WMI_ROAM_DEAUTH_CONFIG_CMDID);
+ WMI_RETURN_STRING(WMI_ROAM_IDLE_CONFIG_CMDID);
+ WMI_RETURN_STRING(WMI_IDLE_TRIGGER_MONITOR_CMDID);
+ WMI_RETURN_STRING(WMI_PDEV_DSM_FILTER_CMDID);
+ WMI_RETURN_STRING(WMI_TWT_BTWT_INVITE_STA_CMDID);
+ WMI_RETURN_STRING(WMI_TWT_BTWT_REMOVE_STA_CMDID);
+ WMI_RETURN_STRING(WMI_OEM_DATA_CMDID);
+ WMI_RETURN_STRING(WMI_ROAM_PREAUTH_STATUS_CMDID);
+ WMI_RETURN_STRING(WMI_SET_ELNA_BYPASS_CMDID);
+ WMI_RETURN_STRING(WMI_GET_ELNA_BYPASS_CMDID);
}
return "Invalid WMI cmd";
@@ -21841,6 +24670,28 @@
*/
} wmi_pdev_csa_switch_count_status_event_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_csc_vdev_list */
+ A_UINT32 vdev_id;
+ A_UINT32 current_switch_count; /** CSC switch count value in the last transmitted beacon */
+} wmi_csc_vdev_list;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_csc_switch_count_status_event_fixed_param */
+ A_UINT32 tlv_header;
+ /** pdev_id for identifying the MAC
+ * See macros starting with WMI_PDEV_ID_ for values.
+ * In non-DBDC case host should set it to 0
+ */
+ A_UINT32 pdev_id;
+ /** CSC switch count value in the last transmitted beacon */
+ A_UINT32 current_switch_count;
+
+ /* The TLVs follows this structure:
+ * struct wmi_csc_vdev_list vdev_info[]; // IDs of vdevs and their current switch countdown values
+ */
+} wmi_pdev_csc_switch_count_status_event_fixed_param;
+
/* Operation types for packet routing command */
typedef enum {
WMI_PDEV_ADD_PKT_ROUTING,
@@ -21855,8 +24706,28 @@
WMI_PDEV_ROUTING_TYPE_MLD_IPV6,
WMI_PDEV_ROUTING_TYPE_DHCP_IPV4,
WMI_PDEV_ROUTING_TYPE_DHCP_IPV6,
+ WMI_PDEV_ROUTING_TYPE_DNS_TCP_IPV4,
+ WMI_PDEV_ROUTING_TYPE_DNS_TCP_IPV6,
+ WMI_PDEV_ROUTING_TYPE_DNS_UDP_IPV4,
+ WMI_PDEV_ROUTING_TYPE_DNS_UDP_IPV6,
+ WMI_PDEV_ROUTING_TYPE_ICMP_IPV4,
+ WMI_PDEV_ROUTING_TYPE_ICMP_IPV6,
+ WMI_PDEV_ROUTING_TYPE_TCP_IPV4,
+ WMI_PDEV_ROUTING_TYPE_TCP_IPV6,
+ WMI_PDEV_ROUTING_TYPE_UDP_IPV4,
+ WMI_PDEV_ROUTING_TYPE_UDP_IPV6,
+ WMI_PDEV_ROUTING_TYPE_IPV4,
+ WMI_PDEV_ROUTING_TYPE_IPV6,
+ WMI_PDEV_ROUTING_TYPE_EAP,
} wmi_pdev_pkt_routing_type;
+typedef enum {
+ WMI_PDEV_WIFIRXCCE_USE_CCE_E = 0,
+ WMI_PDEV_WIFIRXCCE_USE_ASPT_E = 1,
+ WMI_PDEV_WIFIRXCCE_USE_FT_E = 2,
+ WMI_PDEV_WIFIRXCCE_USE_CCE2_E = 3,
+} wmi_pdev_dest_ring_handler_type;
+
/* This command shall be sent only when no VDEV is up. If the command is sent after any VDEV is up, target will ignore the command */
typedef struct {
/** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_update_pkt_routing_cmd_fixed_param */
@@ -21875,6 +24746,11 @@
* CCE copies this back in RX_MSDU_END_TLV.
*/
A_UINT32 meta_data;
+ /**
+ * Indicates the dest ring handler type: CCE, APST, FT, CCE2
+ * Refer to wmi_pdev_dest_ring_handler_type / WMI_PDEV_WIFIRXCCE_USE_xxx
+ */
+ A_UINT32 dest_ring_handler;
} wmi_pdev_update_pkt_routing_cmd_fixed_param;
typedef enum {
@@ -21999,11 +24875,11 @@
/*
* Lay out of flags in wmi_wlm_config_cmd_fixed_param
*
-* |31 17|16 14| 13 | 12 | 11 | 10 |9 8|7 6|5 4|3 2| 1 | 0 |
-* +------+-----+----+----+------+------+------+------+------+------+-----+-----+
-* | RSVD | NSS |EDCA| TRY| SSLP | CSLP | RSVD | Roam | RSVD | DWLT | DFS | SUP |
-* +----------------------+-------------+-------------+-------------------------+
-* | WAL | PS | Roam | Scan |
+* |31 19| 18 | 17|16 14| 13 | 12| 11 | 10 | 9 | 8 |7 6|5 4|3 2| 1 | 0 |
+* +-----+-----+---+-----+----+---+----+----+-----+----+----+----+----+---+---+
+* | RSVD|SRATE|RTS| NSS |EDCA|TRY|SSLP|CSLP|DBMPS|RSVD|Roam|RSVD|DWLT|DFS|SUP|
+* +------------------------------+---------------+---------+-----------------+
+* | WAL | PS | Roam | Scan |
*
* Flag values:
* TRY: (1) enable short limit for retrying unacked tx, where the limit is
@@ -22014,6 +24890,10 @@
* NSS: (0) no Nss limits, other than those negotiatied during association
* (1) during 2-chain operation, tx only a single spatial stream
* (2) - (7) reserved / invalid
+* RTS: (0) default protection
+* (1) always enable RTS/CTS protection
+* SRATE: (0) default secondary rate policy
+* (1) disable secondary rate
*/
/* bit 0-3 of flags is used for scan operation */
/* bit 0: WLM_FLAGS_SCAN_SUPPRESS, suppress all scan and other bits would be ignored if bit is set */
@@ -22025,7 +24905,7 @@
#define WLM_FLAGS_SCAN_SKIP_DFS 1 /* skip dfs channel operation */
/* bit 2-3: define policy of dwell time/duration of each foreign channel
- (b2 b3)
+ (b3 b2)
(0 0 ): Default dwell time
(0 1 ): WLM_FLAGS_STICK_SCAN_DWELL_TIME : Stick to original active/passive dwell time, but split
foreign channel dwell times into fitting into min (dl_latency, ul_latency). Note it can increase
@@ -22043,7 +24923,7 @@
/* bit 6-7 of flags is used for roaming operation */
/* bit 6-7: define roaming policy:
- (b6 b7)
+ (b7 b6)
(0 0 ): WLM_FLAGS_ROAM_ALLOW: Default behavior, allow roaming in all scenarios
(0 1 ): WLM_FLAGS_ROAM_SUPPRESS: Disallow all roaming
(1 0 ): WLM_FLAGS_ALLOW_FINAL_BMISS_ROAM: Allow final bmiss roaming only
@@ -22053,9 +24933,13 @@
#define WLM_FLAGS_ROAM_SUPPRESS 1
#define WLM_FLAGS_ALLOW_FINAL_BMISS_ROAM 2
-/* bit 8-9: reserved for roaming */
+/* bit 8: reserved for roaming */
-/* bit 10-11 of flags is used for powersave operation */
+/* bit 9-11 of flags is used for powersave operation */
+/* bit 9: WLM_FLAGS_PS_DISABLE_BMPS, disable BMPS if bit is set */
+
+#define WLM_FLAGS_PS_DISABLE_BMPS 1 /* disable BMPS */
+
/* bit 10: WLM_FLAGS_PS_DISABLE_CSS_COLLAPSE, disable css power collapse if bit is set */
#define WLM_FLAGS_PS_DISABLE_CSS_COLLAPSE 1 /* disable css power collapse */
@@ -22075,6 +24959,7 @@
#define WLM_FLAGS_SCAN_SET_DWELL_TIME_POLICY(flag, val) WMI_SET_BITS(flag, 2, 2, val)
#define WLM_FLAGS_ROAM_GET_POLICY(flag) WMI_GET_BITS(flag, 6, 2)
#define WLM_FLAGS_ROAM_SET_POLICY(flag, val) WMI_SET_BITS(flag, 6, 2, val)
+#define WLM_FLAGS_PS_IS_BMPS_DISABLED(flag) WMI_GET_BITS(flag, 9, 1)
#define WLM_FLAGS_PS_IS_CSS_CLPS_DISABLED(flag) WMI_GET_BITS(flag, 10, 1)
#define WLM_FLAGS_PS_SET_CSS_CLPS_DISABLE(flag, val) WMI_SET_BITS(flag, 10, 1, val)
#define WLM_FLAGS_PS_IS_SYS_SLP_DISABLED(flag) WMI_GET_BITS(flag, 11, 1)
@@ -22085,6 +24970,10 @@
#define WLM_FLAGS_WAL_ADJUST_EDCA_SET(flag, val) WMI_SET_BITS(flag, 13, 1, val)
#define WLM_FLAGS_WAL_1NSS_ENABLED(flag) (WMI_GET_BITS(flag, 14, 3) & 0x1)
#define WLM_FLAGS_WAL_NSS_SET(flag, val) WMI_SET_BITS(flag, 14, 3, val)
+#define WLM_FLAGS_WAL_ALWAYS_RTS_PROTECTION(flag) WMI_GET_BITS(flag, 17, 1)
+#define WLM_FLAGS_WAL_RTS_PROTECTION_SET(flag, val) WMI_SET_BITS(flag, 17, 1, val)
+#define WLM_FLAGS_WAL_DISABLE_SECONDARY_RATE(flag) WMI_GET_BITS(flag, 18, 1)
+#define WLM_FLAGS_WAL_SECONDARY_RATE_SET(flag, val) WMI_SET_BITS(flag, 18, 1, val)
typedef struct {
/** TLV tag and len; tag equals
@@ -22112,16 +25001,25 @@
A_UINT32 flags;
} wmi_wlm_config_cmd_fixed_param;
+/* Broadcast TWT enable/disable */
+#define TWT_EN_DIS_FLAGS_GET_BTWT(flag) WMI_GET_BITS(flag, 0, 1)
+#define TWT_EN_DIS_FLAGS_SET_BTWT(flag, val) WMI_SET_BITS(flag, 0, 1, val)
+
+/* legacy MBSSID enable/disable */
+#define TWT_EN_DIS_FLAGS_GET_L_MBSSID(flag) WMI_GET_BITS(flag, 1, 1)
+#define TWT_EN_DIS_FLAGS_SET_L_MBSSID(flag, val) WMI_SET_BITS(flag, 1, 1, val)
+
+/* 11ax MBSSID enable/disable */
+#define TWT_EN_DIS_FLAGS_GET_AX_MBSSID(flag) WMI_GET_BITS(flag, 2, 1)
+#define TWT_EN_DIS_FLAGS_SET_AX_MBSSID(flag, val) WMI_SET_BITS(flag, 2, 1, val)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_enable_cmd_fixed_param */
/** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0
- * The host should never set this pdev_id to WMI_PDEV_ID_SOC,
- * because the configuration parameters herein will be different
- * for each MAC instance.
*/
A_UINT32 pdev_id;
A_UINT32 sta_cong_timer_ms; /* STA TWT congestion timer TO value in terms of ms */
- A_UINT32 mbss_support; /* Flag indicating if AP TWT feature supported in MBSS mode or not */
+ A_UINT32 mbss_support; /* Reserved */
A_UINT32 default_slot_size; /* This is the default value for the TWT slot setup by AP (units = microseconds) */
A_UINT32 congestion_thresh_setup; /* Minimum congestion required to start setting up TWT sessions */
/*
@@ -22147,7 +25045,8 @@
*/
A_UINT32 mode_check_interval; /* Interval between two successive check to decide the mode of TWT */
A_UINT32 add_sta_slot_interval; /* Interval between decisions making to create TWT slots for STAs */
- A_UINT32 remove_sta_slot_interval; /* Inrerval between decisions making to remove TWT slot of STAs */
+ A_UINT32 remove_sta_slot_interval; /* Interval between decisions making to remove TWT slot of STAs */
+ A_UINT32 flags; /* enable/disable flags, refer to MACROs TWT_EN_DIS_FLAGS_* (TWT_EN_DIS_FLAGS_GET_BTWT etc.) */
} wmi_twt_enable_cmd_fixed_param;
/* status code of enabling TWT */
@@ -22169,7 +25068,8 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_disable_cmd_fixed_param */
/** pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values. In non-DBDC case host should set it to 0 */
- A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC */
+ A_UINT32 pdev_id; /* host should never set it to WMI_PDEV_ID_SOC */
+ A_UINT32 flags; /* enable/disable flags, refer to MACROs TWT_EN_DIS_FLAGS_* (TWT_EN_DIS_FLAGS_GET_BTWT etc.) */
} wmi_twt_disable_cmd_fixed_param;
typedef struct {
@@ -22209,29 +25109,42 @@
#define TWT_FLAGS_GET_PROTECTION(flag) WMI_GET_BITS(flag, 11, 1)
#define TWT_FLAGS_SET_PROTECTION(flag, val) WMI_SET_BITS(flag, 11, 1, val)
+/* B-TWT ID 0: 0 means non-0 B-TWT ID or I-TWT, 1 means B-TWT ID 0 */
+#define TWT_FLAGS_GET_BTWT_ID0(flag) WMI_GET_BITS(flag, 12, 1)
+#define TWT_FLAGS_SET_BTWT_ID0(flag, val) WMI_SET_BITS(flag, 12, 1, val)
+
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_add_dialog_cmd_fixed_param */
A_UINT32 vdev_id; /* VDEV identifier */
- wmi_mac_addr peer_macaddr; /* peer MAC address when vdev is AP VDEV */
- /* diaglog_id (TWT dialog ID)
- * This dialog ID must be unique within its vdev.
- */
- A_UINT32 dialog_id;
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
+ A_UINT32 dialog_id; /* TWT dialog_id (< 0xFF) is per peer, I-TWT & B-TWT use different diaglog ID */
/* 1. wake_intvl_mantis must be <= 0xFFFF
* 2. wake_intvl_us must be divided evenly by wake_intvl_mantis,
* i.e., wake_intvl_us % wake_intvl_mantis == 0
- * 2. the quotient of wake_intvl_us/wake_intvl_mantis must be 2 to N-th(0<=N<=31) power,
- i.e., wake_intvl_us/wake_intvl_mantis == 2^N, 0<=N<=31
+ * 3. the quotient of wake_intvl_us/wake_intvl_mantis must be 2 to N-th(0<=N<=31) power,
+ * i.e., wake_intvl_us/wake_intvl_mantis == 2^N, 0<=N<=31
*/
A_UINT32 wake_intvl_us; /* TWT Wake Interval in units of us */
A_UINT32 wake_intvl_mantis; /* TWT Wake Interval Mantissa */
/* wake_dura_us must be divided evenly by 256, i.e., wake_dura_us % 256 == 0 */
- A_UINT32 wake_dura_us; /* TWT Wake Duration in units of us, must be <= 0xFFFF */
+ A_UINT32 wake_dura_us; /* TWT Wake Duration in units of us, must be <= 65280 (0xFF00) */
A_UINT32 sp_offset_us; /* this long time after TWT setup the 1st SP will start */
A_UINT32 flags; /* TWT flags, refer to MACROs TWT_FLAGS_*(TWT_FLAGS_GET_CMD etc) */
+
+ /* Broadcast TWT(B-TWT) Persistence, when used in Add/update Dialog,
+ * indicates for how long(in units of TBTTs) current B-TWT session
+ * parameters will not be changed.
+ * Refer to 11ax spec session "9.4.2.199 TWT element" for more info.
+ */
+ A_UINT32 b_twt_persistence;
+
+ /* Broadcast TWT(B-TWT) Recommendation, refer to section
+ * "9.4.2.199 TWT element" of latest 11ax draft
+ */
+ A_UINT32 b_twt_recommendation;
} wmi_twt_add_dialog_cmd_fixed_param;
/* status code of adding TWT dialog */
@@ -22251,6 +25164,7 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_add_dialog_complete_event_fixed_param */
A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
A_UINT32 dialog_id; /* TWT dialog ID */
A_UINT32 status; /* refer to WMI_ADD_TWT_STATUS_T */
} wmi_twt_add_dialog_complete_event_fixed_param;
@@ -22258,7 +25172,14 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_del_dialog_cmd_fixed_param */
A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
A_UINT32 dialog_id; /* TWT dialog ID */
+ /* Broadcast TWT(B-TWT) Persistence, when used in Del Dialog,
+ * indicates for how long(in units of TBTTs) current B-TWT session
+ * parameters will be present.
+ * Refer to 11ax spec session "9.4.2.199 TWT element" for more info.
+ */
+ A_UINT32 b_twt_persistence;
} wmi_twt_del_dialog_cmd_fixed_param;
/* status code of deleting TWT dialog */
@@ -22275,6 +25196,7 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_del_dialog_complete_event_fixed_param */
A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
A_UINT32 dialog_id; /* TWT dialog ID */
A_UINT32 status; /* refer to WMI_DEL_TWT_STATUS_T */
} wmi_twt_del_dialog_complete_event_fixed_param;
@@ -22282,6 +25204,7 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_pause_dialog_cmd_fixed_param */
A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
A_UINT32 dialog_id; /* TWT dialog ID */
} wmi_twt_pause_dialog_cmd_fixed_param;
@@ -22299,6 +25222,7 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_pause_dialog_complete_event_fixed_param */
A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
A_UINT32 dialog_id; /* TWT dialog ID */
A_UINT32 status; /* refer to WMI_PAUSE_TWT_STATUS_T */
} wmi_twt_pause_dialog_complete_event_fixed_param;
@@ -22306,8 +25230,10 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_resume_dialog_cmd_fixed_param */
A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
A_UINT32 dialog_id; /* TWT dialog ID */
A_UINT32 sp_offset_us; /* this long time after TWT resumed the 1st SP will start */
+ A_UINT32 next_twt_size; /* Next TWT subfield Size, refer to IEEE 802.11ax sectin "9.4.1.60 TWT Information field" */
} wmi_twt_resume_dialog_cmd_fixed_param;
/* status code of resuming TWT dialog */
@@ -22325,12 +25251,68 @@
typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_resume_dialog_complete_event_fixed_param */
A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
A_UINT32 dialog_id; /* TWT dialog ID */
A_UINT32 status; /* refer to WMI_RESUME_TWT_STATUS_T */
} wmi_twt_resume_dialog_complete_event_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_twt_btwt_invite_sta_cmd_fixed_param */
+ A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
+ A_UINT32 dialog_id; /* TWT dialog ID */
+} wmi_twt_btwt_invite_sta_cmd_fixed_param;
+
+/* status code of inviting STA to B-TWT dialog */
+typedef enum _WMI_TWT_BTWT_INVITE_STA_STATUS_T {
+ WMI_TWT_BTWT_INVITE_STA_STATUS_OK, /* inviting STA to B-TWT successfully completed */
+ WMI_TWT_BTWT_INVITE_STA_STATUS_DIALOG_ID_NOT_EXIST, /* TWT dialog ID not exists */
+ WMI_TWT_BTWT_INVITE_STA_STATUS_INVALID_PARAM, /* invalid parameters */
+ WMI_TWT_BTWT_INVITE_STA_STATUS_DIALOG_ID_BUSY, /* FW is in the process of handling this dialog */
+ WMI_TWT_BTWT_INVITE_STA_STATUS_ALREADY_JOINED, /* peer STA already joined the session */
+ WMI_TWT_BTWT_INVITE_STA_STATUS_NO_RESOURCE, /* FW resource exhausted */
+ WMI_TWT_BTWT_INVITE_STA_STATUS_NO_ACK, /* peer STA did not ACK the request/response frame */
+ WMI_TWT_BTWT_INVITE_STA_STATUS_UNKNOWN_ERROR, /* failed with an unknown reason */
+} WMI_TWT_BTWT_INVITE_STA_STATUS_T;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_twt_btwt_invite_sta_complete_event_fixed_param */
+ A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
+ A_UINT32 dialog_id; /* TWT dialog ID */
+ A_UINT32 status; /* refer to WMI_TWT_BTWT_INVITE_STA_STATUS_T */
+} wmi_twt_btwt_invite_sta_complete_event_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_twt_btwt_remove_sta_cmd_fixed_param */
+ A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
+ A_UINT32 dialog_id; /* TWT dialog ID */
+} wmi_twt_btwt_remove_sta_cmd_fixed_param;
+
+/* status code of removing STA from B-TWT dialog */
+typedef enum _WMI_TWT_BTWT_REMOVE_STA_STATUS_T {
+ WMI_TWT_BTWT_REMOVE_STA_STATUS_OK, /* removing STA from B-TWT successfully completed */
+ WMI_TWT_BTWT_REMOVE_STA_STATUS_DIALOG_ID_NOT_EXIST, /* TWT dialog ID not exists */
+ WMI_TWT_BTWT_REMOVE_STA_STATUS_INVALID_PARAM, /* invalid parameters */
+ WMI_TWT_BTWT_REMOVE_STA_STATUS_DIALOG_ID_BUSY, /* FW is in the process of handling this dialog */
+ WMI_TWT_BTWT_REMOVE_STA_STATUS_NOT_JOINED, /* peer STA not joined yet */
+ WMI_TWT_BTWT_REMOVE_STA_STATUS_NO_RESOURCE, /* FW resource exhausted */
+ WMI_TWT_BTWT_REMOVE_STA_STATUS_NO_ACK, /* peer STA did not ACK the request/response frame */
+ WMI_TWT_BTWT_REMOVE_STA_STATUS_UNKNOWN_ERROR, /* failed with an unknown reason */
+} WMI_TWT_BTWT_REMOVE_STA_STATUS_T;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_twt_btwt_remove_sta_complete_event_fixed_param */
+ A_UINT32 vdev_id; /* VDEV identifier */
+ wmi_mac_addr peer_macaddr; /* peer MAC address */
+ A_UINT32 dialog_id; /* TWT dialog ID */
+ A_UINT32 status; /* refer to WMI_TWT_BTWT_REMOVE_STA_STATUS_T */
+} wmi_twt_btwt_remove_sta_complete_event_fixed_param;
+
typedef enum {
- WMI_DMA_RING_CONFIG_MODULE_SPECTRAL,
+ WMI_DMA_RING_CONFIG_MODULE_SPECTRAL,
+ WMI_DMA_RING_CONFIG_MODULE_RTT,
} WMI_DMA_RING_SUPPORTED_MODULE;
typedef struct {
@@ -22342,6 +25324,49 @@
A_UINT32 min_buf_align; /* minimum alignment in bytes of each buffer in the DMA ring */
} WMI_DMA_RING_CAPABILITIES;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUCT_ wmi_chan_rf_characterization_info */
+
+ /**
+ * [7:0] : channel metric - 0 = unusable, 1 = worst, 100 = best
+ * [11:8] : channel BW - This bit-field uses values compatible with
+ * enum definitions used internally within the target's
+ * halphy code. This bit field uses wmi_channel_width.
+ * [15:12]: Reserved
+ * [31:16]: Frequency - Center frequency of the channel for which
+ * the RF characterisation info applies (MHz)
+ */
+ A_UINT32 freq_info;
+} WMI_CHAN_RF_CHARACTERIZATION_INFO;
+
+#define WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_CHAN_METRIC 0x000000ff
+#define WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_CHAN_METRIC_S 0
+#define WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_BW 0x00000f00
+#define WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_BW_S 8
+#define WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_FREQ 0xffff0000
+#define WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_FREQ_S 16
+
+#define WMI_CHAN_RF_CHARACTERIZATION_CHAN_METRIC_SET(dword,val) \
+ WMI_F_RMW((dword)->freq_info,(val), \
+ WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_CHAN_METRIC)
+#define WMI_CHAN_RF_CHARACTERIZATION_CHAN_METRIC_GET(dword) \
+ WMI_F_MS((dword)->freq_info,WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_CHAN_METRIC)
+
+#define WMI_CHAN_RF_CHARACTERIZATION_BW_SET(dword, val) \
+ WMI_F_RMW((dword)->freq_info,(val), \
+ WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_BW)
+#define WMI_CHAN_RF_CHARACTERIZATION_BW_GET(dword) \
+ WMI_F_MS((dword)->freq_info,WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_BW)
+
+#define WMI_CHAN_RF_CHARACTERIZATION_FREQ_SET(dword, val) \
+ WMI_F_RMW((dword)->freq_info,(val), \
+ WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_FREQ)
+
+#define WMI_CHAN_RF_CHARACTERIZATION_FREQ_GET(dword) \
+ WMI_F_MS((dword)->freq_info,WMI_CHAN_RF_CHARACTERIZATION_FREQ_INFO_FREQ)
+
+
+
#define WMI_DMA_RING_PADDR_LO_S 0
#define WMI_DMA_RING_PADDR_LO 0xffffffff
@@ -22421,8 +25446,10 @@
A_UINT32 pdev_id; /** ID of pdev whose DMA ring produced the data */
A_UINT32 mod_id; /* see WMI_DMA_RING_SUPPORTED_MODULE */
A_UINT32 num_buf_release_entry;
+ A_UINT32 num_meta_data_entry;
/* This TLV is followed by another TLV of array of structs.
- * wmi_dma_buf_release_entry entries;
+ * wmi_dma_buf_release_entry entries[num_buf_release_entry];
+ * wmi_dma_buf_release_spectral_meta_data meta_datat[num_meta_data_entry];
*/
} wmi_dma_buf_release_fixed_param;
@@ -22433,13 +25460,72 @@
*/
A_UINT32 paddr_lo;
/**
- * Bits 15:0: address of data [47:32]
- * Bits 31:16: reserved
+ * Bits 11:0: address of data [43:32]
+ * Bits 31:12: host context data [19:0]
*/
A_UINT32 paddr_hi;
} wmi_dma_buf_release_entry;
typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_dma_buf_release_spectral_meta_data */
+ /**
+ * meta data information.
+ * Host uses the noise floor values as one of the major parameter
+ * to classify the spectral data.
+ * This information will not be provided by ucode unlike the fft reports
+ * which gets DMAed to DDR buffer.
+ * Hence sending the NF values in dBm units as meta data information.
+ */
+ A_INT32 noise_floor[WMI_MAX_CHAINS];
+ /**
+ * The time taken by target in micro seconds to complete the reset routine
+ * and re-initiate the spectral scan.
+ * If the delay is 0, the WAR to bookkeep the timestamp wont be exercised
+ * in HOST.
+ */
+ A_UINT32 reset_delay;
+ /**
+ * Current center freq1 (MHz units)
+ */
+ A_UINT32 freq1;
+ /**
+ * Current center freq2 (MHz units)
+ */
+ A_UINT32 freq2;
+ /**
+ * Channel Width (MHz units)
+ */
+ A_UINT32 ch_width;
+} wmi_dma_buf_release_spectral_meta_data;
+
+typedef enum {
+ NO_SCALING = 0, /* No bin scaling*/
+ /**
+ * scaled_bin_mag = bin_mag *
+ * sqrt(10^(max(legacy_max_gain - default_agc_max_gain + low_level_offset - RSSI_corr,
+ * (agc_total_gain_db < default_agc_max_gain) * high_level_offset)/10)) *
+ * 2^(DET{0,1,2}_SPECTRAL_SCAN_BIN_SCALE - legacy_spectral_scan_bin_scale)
+ */
+ AGC_GAIN_RSSI_CORR_BASED = 1,
+} WMI_SPECTRAL_SCALING_FORMULA_ID;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_spectral_bin_scaling_params */
+ A_UINT32 pdev_id; /* ID of pdev to which the scaling parameters are to be applied */
+ WMI_SPECTRAL_SCALING_FORMULA_ID formula_id; /* Represets the formula to be used */
+ A_UINT32 low_level_offset; /* low level offset for fine tuning the scaling factor based on RSSI and AGC gain */
+ A_UINT32 high_level_offset; /* high level offset for fine tuning the scaling factor based on RSSI and AGC gain */
+ A_UINT32 rssi_thr; /* RSSI threshold to be used to adjust the inband power of the given spectral report */
+ A_UINT32 default_agc_max_gain;/* DEFAULT AGC MAX GAIN used. Fetched from register RXTD_RADAR_SBS_CTRL_1_L bits20:13 */
+} wmi_spectral_bin_scaling_params;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_ctl_failsafe_event_params */
+ A_UINT32 pdev_id; /* ID of pdev to which ctl failsafe status is sent */
+ A_UINT32 ctl_FailsafeStatus; /* To indicate if Failsafe value is imposed on CTL. 0- Success, 1- Failsafe imposed */
+} wmi_pdev_ctl_failsafe_check_fixed_param;
+
+typedef struct {
A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_runtime_dpd_recal_cmd_fixed_param */
A_UINT32 enable; /* Enable/disable */
@@ -22475,6 +25561,9 @@
WMI_ROAM_TRIGGER_REASON_FORCED,
WMI_ROAM_TRIGGER_REASON_BTM,
WMI_ROAM_TRIGGER_REASON_UNIT_TEST,
+ WMI_ROAM_TRIGGER_REASON_BSS_LOAD,
+ WMI_ROAM_TRIGGER_REASON_DEAUTH,
+ WMI_ROAM_TRIGGER_REASON_IDLE,
WMI_ROAM_TRIGGER_REASON_MAX,
} WMI_ROAM_TRIGGER_REASON_ID;
@@ -22502,6 +25591,178 @@
A_UINT32 vdev_id;
} wmi_request_roam_scan_stats_cmd_fixed_param;
+/** BSS load configuration parameters for roam trigger */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_bss_load_cmd_fixed_param */
+ A_UINT32 vdev_id;
+ /** Minimum number of beacons to be consider for calculating average AP BSS load within time monitor_time_window */
+ A_UINT32 beacons_min_count;
+ /** Monitor time window in seconds */
+ A_UINT32 monitor_time_window;
+ /** BSS load threshold after which roam scan should trigger */
+ A_UINT32 bss_load_threshold;
+ /** rssi_2g_threshold
+ * If connected AP is in 2.4Ghz, then consider bss load roam triggered
+ * only if load % > bss_load_threshold && connected AP rssi is worse
+ * than rssi_2g_threshold.
+ */
+ A_INT32 rssi_2g_threshold; /* units = dbm */
+ /** rssi_5g_threshold
+ * If connected AP is in 5Ghz, then consider bss load roam triggered
+ * only if load % > bss_load_threshold && connected AP rssi is worse
+ * than rssi_5g_threshold.
+ */
+ A_INT32 rssi_5g_threshold; /* units = dbm */
+} wmi_roam_bss_load_config_cmd_fixed_param;
+
+/** Deauth roam trigger parameters */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_deauth_config_cmd_fixed_param */
+ A_UINT32 vdev_id;
+ /* 1-Enable, 0-Disable */
+ A_UINT32 enable;
+} wmi_roam_deauth_config_cmd_fixed_param;
+
+/** IDLE roam trigger parameters */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_idle_config_cmd_fixed_param */
+ A_UINT32 vdev_id;
+ /* 1-Enable, 0-Disable */
+ A_UINT32 enable;
+ /* Connected AP band. 0 - Any Band, 1 - 2.4Ghz Band, 2 - 5Ghz Band */
+ A_UINT32 band;
+ /* Trigger Idle roaming only if rssi change of connected AP is within rssi_delta during idle time */
+ A_UINT32 rssi_delta; /* units = dB */
+ /* Trigger idle roam only if connected RSSI is better than min_rssi */
+ A_INT32 min_rssi; /* units = dBm */
+ /* Inactive/Idle time duration
+ * After screen is OFF (or whatever condition is suitable in a given
+ * system as an indication that the system is likely idle)
+ * and if below conditions are met then idle roaming will be triggered.
+ * 1. Connected AP band is matching with band value configured
+ * 2. No TX/RX data for more than idle_time configured
+ * or TX/RX data packets count is less than data_packet_count
+ * during idle_time
+ * 3. Connected AP rssi change is not more than rssi_delta
+ * 4. Connected AP rssi is better than min_rssi.
+ * The purpose of this trigger for idle scan is to issue the scan
+ * even if (moreover, particularly if) the connection to the
+ * existing AP is still good, to keep the STA from getting locked
+ * onto the current good AP and thus missing out on an available
+ * even better AP. This min_rssi threshold can be used to adjust
+ * the connection quality level at which the STA considers doing an
+ * idle scan.
+ */
+ A_UINT32 idle_time; /* units = seconds */
+ /* Maximum allowed data packets count during idle time */
+ A_UINT32 data_packet_count;
+} wmi_roam_idle_config_cmd_fixed_param;
+
+/** trigger to start/stop monitoring if system is idle command parameters */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_idle_trigger_monitor_cmd_fixed_param */
+ /* idle_trigger_monitor values are from WMI_IDLE_TRIGGER_MONITOR_ID */
+ A_UINT32 idle_trigger_monitor;
+} wmi_idle_trigger_monitor_cmd_fixed_param;
+
+typedef enum {
+ WMI_IDLE_TRIGGER_MONITOR_NONE = 0, /* no-op */
+ /* IDLE_TRIGGER_MONITOR_ON
+ * The host's screen has turned off (or some other event indicating that
+ * the system is likely idle) -
+ * start monitoring to check if the system is idle.
+ */
+ WMI_IDLE_TRIGGER_MONITOR_ON,
+ /* IDLE_TRIGGER_MONITOR_OFF
+ * The host's screen has turned on (or some other event indicating that
+ * the system is not idle)
+ */
+ WMI_IDLE_TRIGGER_MONITOR_OFF,
+} WMI_SCREEN_STATUS_NOTIFY_ID;
+
+typedef struct {
+ /** TLV tag and len; tag equals wmi_pdev_dsm_filter_fixed_param */
+ A_UINT32 tlv_header;
+ /**
+ * TLV (tag length value) parameter's following pdev_dsm_filter_cmd are,
+ *
+ * wmi_pdev_bssid_disallow_list_config_param bssid_disallow_list[];
+ * i.e array containing all disallow AP filter lists including
+ * the new DSM lists (avoidlist / driver_blacklist) and existing
+ * lists (supplicant_blacklist / rssi_rejectlist etc.)
+ */
+} wmi_pdev_dsm_filter_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_bssid_disallow_list_config_param */
+ A_UINT32 tlv_header;
+ /** bssid type i.e whether bssid falls in avoid list or driver_blacklist etc.
+ see WMI_BSSID_DISALLOW_LIST_TYPE **/
+ A_UINT32 bssid_type;
+ /** mac address of disallow BSSID */
+ wmi_mac_addr bssid;
+ /** Disallow AP for certain duration, in units of milliseconds */
+ A_UINT32 remaining_disallow_duration;
+ /** AP will be allowed for candidate, when AP RSSI better than expected RSSI units in dBm */
+ A_INT32 expected_rssi;
+} wmi_pdev_bssid_disallow_list_config_param;
+
+typedef enum {
+ /* USER_SPACE_BLACK_LIST
+ * Black Listed AP's by host's user space
+ */
+ WMI_BSSID_DISALLOW_USER_SPACE_BLACK_LIST = 1,
+ /* DRIVER_BLACK_LIST
+ * Black Listed AP's by host driver
+ * used for data stall migitation
+ */
+ WMI_BSSID_DISALLOW_DRIVER_BLACK_LIST,
+ /* USER_SPACE_AVOID_LIST
+ * Avoid List AP's by host's user space
+ * used for data stall migitation
+ */
+ WMI_BSSID_DISALLOW_USER_SPACE_AVOID_LIST,
+ /* DRIVER_AVOID_LIST
+ * Avoid List AP's by host driver
+ * used for data stall migitation
+ */
+ WMI_BSSID_DISALLOW_DRIVER_AVOID_LIST,
+ /* RSSI_REJECT_LIST
+ * OCE AP's
+ */
+ WMI_BSSID_DISALLOW_RSSI_REJECT_LIST,
+} WMI_BSSID_DISALLOW_LIST_TYPE;
+
+/* WLAN_PDEV_MAX_NUM_BSSID_DISALLOW_LIST:
+ * Maximum number of BSSID disallow entries which host is allowed to send
+ * to firmware within the WMI_PDEV_DSM_FILTER_CMDID message.
+ */
+#define WLAN_PDEV_MAX_NUM_BSSID_DISALLOW_LIST 28
+
+/** Roam Pre-Authentication completion status */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_preauth_status_cmd_fixed_param */
+ A_UINT32 vdev_id;
+ /* preauth_status, 0 - Success, Non Zero - Failure
+ * Refer to IEEE Std 802.11-2016 Table 9-46 for meaning of status values.
+ */
+ A_UINT32 preauth_status;
+ /* AP BSSID for which pre-authentication is completed */
+ wmi_mac_addr candidate_ap_bssid;
+ /**
+ * PMKID computed after successful pre-authentication. This is valid only if preauth_status is success
+ * A_UINT8 pmkid[];
+ */
+} wmi_roam_preauth_status_cmd_fixed_param;
+
+/** Roam Pre-Authentication start event */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_preauth_start_event_fixed_param */
+ A_UINT32 vdev_id;
+ /* AP BSSID for which host needs to start pre-authentication */
+ wmi_mac_addr candidate_ap_bssid;
+} wmi_roam_preauth_start_event_fixed_param;
+
typedef struct {
/*
* The timestamp is in units of ticks of a 19.2MHz clock.
@@ -22559,6 +25820,1627 @@
*/
} wmi_roam_scan_stats_event_fixed_param;
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_txpower_query_cmd_fixed_param */
+ A_UINT32 request_id; /* unique request ID to distinguish the command / event set */
+
+ /* The mode value has the following meaning :
+ * 0 : 11a
+ * 1 : 11bg
+ * 2 : 11b
+ * 3 : 11g only
+ * 4 : 11a HT20
+ * 5 : 11g HT20
+ * 6 : 11a HT40
+ * 7 : 11g HT40
+ * 8 : 11a VHT20
+ * 9 : 11a VHT40
+ * 10 : 11a VHT80
+ * 11 : 11g VHT20
+ * 12 : 11g VHT40
+ * 13 : 11g VHT80
+ * 14 : unknown
+ */
+ A_UINT32 mode;
+ A_UINT32 rate; /* rate index */
+ A_UINT32 nss; /* number of spatial stream */
+ A_UINT32 beamforming; /* beamforming parameter 0:disabled, 1:enabled */
+ A_UINT32 chain_mask; /* mask for the antenna set to get power */
+ A_UINT32 chain_index; /* index for the antenna */
+} wmi_get_tpc_power_cmd_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_tpc_power_evt_fixed_param */
+ A_UINT32 request_id; /* request ID set by the command */
+ A_INT32 tx_power; /* TX power for the specified HALPHY parameters in half dBm unit */
+} wmi_get_tpc_power_evt_fixed_param;
+
+/* below structures are related to Motion Detection. */
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_motion_det_config_params_cmd_fixed_param */
+ A_UINT32 tlv_header; /** TLV Header */
+ A_UINT32 vdev_id; /** Vdev ID */
+ A_UINT32 time_t1; /** Time gap of successive bursts of
+ * measurement frames during coarse
+ * motion detection (in ms) */
+ A_UINT32 time_t2; /** Time gap of successive bursts of
+ * measurement frames during fine
+ * motion detection (in ms) */
+ A_UINT32 n1; /** number of measurement frames in one
+ * burst, for coarse detection */
+ A_UINT32 n2; /** number of measurement frames in one
+ * burst, for fine detection */
+ A_UINT32 time_t1_gap; /** gap between measurement frames in
+ * course detection (in ms) */
+ A_UINT32 time_t2_gap; /** gap between measurement frames in
+ * fine detection (in ms) */
+ A_UINT32 coarse_K; /** number of times motion detection has to
+ * be performed for coarse detection */
+ A_UINT32 fine_K; /** number of times motion detection has to
+ * be performed for fine detection */
+ A_UINT32 coarse_Q; /** number of times motion is expected
+ * to be detected for success case in
+ * coarse detection */
+ A_UINT32 fine_Q; /** number of times motion is expected
+ * to be detected for success case in
+ * fine detection */
+ A_UINT32 md_coarse_thr_high; /** higher threshold value (in percent)
+ * from host to FW, which will be used in
+ * coarse detection phase of motion detection.
+ * This is the threshold for the correlation
+ * of the old RF local-scattering environment
+ * with the current RF local-scattering
+ * environment. A value of 100(%) indicates
+ * that neither the transceiver nor any
+ * nearby objects have changed position. */
+ A_UINT32 md_fine_thr_high; /** higher threshold value (in percent)
+ * from host to FW, which will be used in
+ * fine detection phase of motion detection.
+ * This is the threshold for correlation
+ * between the old and current RF environments,
+ * as explained above. */
+ A_UINT32 md_coarse_thr_low; /** lower threshold value (in percent)
+ * for immediate detection of motion in
+ * coarse detection phase.
+ * This is the threshold for correlation
+ * between the old and current RF environments,
+ * as explained above. */
+ A_UINT32 md_fine_thr_low; /** lower threshold value (in percent)
+ * for immediate detection of motion in
+ * fine detection phase.
+ * This is the threshold for correlation
+ * between the old and current RF environments,
+ * as explained above. */
+} wmi_motion_det_config_params_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_motion_det_base_line_config_params_cmd_fixed_param */
+ A_UINT32 tlv_header; /** TLV Header */
+ A_UINT32 vdev_id; /** Vdev ID */
+ A_UINT32 bl_time_t; /** time T for baseline (in ms)
+ * Every bl_time_t, bl_n packets are sent */
+ A_UINT32 bl_packet_gap; /** gap between measurement frames for baseline
+ * (in ms) */
+ A_UINT32 bl_n; /** number of measurement frames to be sent
+ * during one baseline */
+ A_UINT32 bl_num_meas; /** number of times the baseline measurement
+ * to be done */
+} wmi_motion_det_base_line_config_params_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_motion_det_start_stop_cmd_fixed_param */
+ A_UINT32 tlv_header; /** TLV Header */
+ A_UINT32 vdev_id; /** Vdev ID */
+ A_UINT32 enable; /** start = 1, stop =0 */
+} wmi_motion_det_start_stop_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_motion_det_base_line_start_stop_cmd_fixed_param */
+ A_UINT32 tlv_header; /** TLV Header */
+ A_UINT32 vdev_id; /** Vdev ID */
+ A_UINT32 enable; /** start = 1, stop =0 */
+} wmi_motion_det_base_line_start_stop_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_motion_det_event */
+ A_UINT32 tlv_header; /** TLV Header */
+ A_UINT32 vdev_id; /** Vdev ID */
+ A_UINT32 status; /** status = 1 -> motion detected */
+} wmi_motion_det_event;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_motion_det_base_line_event */
+ A_UINT32 tlv_header; /** TLV Header */
+ A_UINT32 vdev_id; /** Vdev ID */
+ A_UINT32 bl_baseline_value; /** baseline correlation value calculated
+ * during baselining phase (in %) */
+ A_UINT32 bl_max_corr_reserved; /** max corr value obtained during baselining
+ * phase (in %); reserved for future */
+ A_UINT32 bl_min_corr_reserved; /** min corr value obtained during baselining
+ * phase (in %); reserved for future */
+} wmi_motion_det_base_line_event;
+
+/* Below structures are related to OBSS_PD_SPATIAL Reuse */
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_obss_set_cmd_fixed_param */
+ A_UINT32 tlv_header;
+ /** Enable/Disable Spatial Reuse */
+ A_UINT32 enable;
+ /*
+ * In the below fields, "OBSS level" refers to the power of the
+ * signals received from "Other BSS".
+ * Spatial reuse will only be permitted if the Other BSS's signal power
+ * is witin the min to max range specified by the below fields.
+ */
+ /** Minimum OBSS level to use */
+ A_INT32 obss_min; /* RSSI in dBm */
+ /** Maximum OBSS level to use */
+ A_INT32 obss_max; /* RSSI in dBm */
+ /** Vdev id*/
+ A_UINT32 vdev_id;
+} wmi_obss_spatial_reuse_set_cmd_fixed_param;
+
+/*
+ * Below structure is related to WMI CMD that configures the default
+ * mimimum (OBSS_MIN) and maximum (OBSS_MAX) Other BSS levels (RSSI in dbm)
+ * for VDEV of a give type (STA or AP). These thresholds are configured
+ * within the Host and passed down to the FW. FW will use these
+ * default OBSS_MIN and OBSS_MAX values during roaming if the assoc response
+ * from the AP does not include spatial reuse parameter set Info Element.
+ */
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param
+ */
+ A_UINT32 tlv_header;
+ /*
+ * In the below fields, "OBSS level" refers to the power of the
+ * signals received from "Other BSS".
+ * Spatial reuse will only be permitted if the Other BSS's signal power
+ * is witin the min to max range specified by the below fields.
+ */
+ /** Minimum OBSS level to use */
+ A_INT32 obss_min; /* RSSI in dBm */
+ /** Maximum OBSS level to use */
+ A_INT32 obss_max; /* RSSI in dBm */
+ /** Type of VDEV for which these threshold are applicable.
+ * vdev_type should be one of WMI_VDEV_TYPE_STA or WMI_VDEV_TYPE_AP
+ */
+ A_UINT32 vdev_type;
+} wmi_obss_spatial_reuse_set_def_obss_thresh_cmd_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUCT_wmi_chan_width_peer_list */
+ wmi_mac_addr peer_macaddr;
+ A_UINT32 chan_width; /* wmi_channel_width */
+} wmi_chan_width_peer_list;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_chan_width_switch_cmd_fixed_param */
+ A_UINT32 num_peers;
+ /*
+ * Following this structure is the TLV:
+ * struct wmi_chan_width_peer_list chan_width_peer_info[num_peers];
+ */
+} wmi_peer_chan_width_switch_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_he_tb_action_frm_cmd_fixed_param */
+ A_UINT32 tlv_header;
+ /* enable or disable HE TB Action frame */
+ A_UINT32 enable;
+ /* length of action frame body in bytes */
+ A_UINT32 data_len;
+/* This TLV is followed by another TLV of array of bytes
+ * A_UINT8 data[];
+ * This data array contains the action frame raw data
+ */
+} wmi_pdev_he_tb_action_frm_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_hpcs_pulse_start_cmd_fixed_param */
+ A_UINT32 tlv_header; /** TLV Header */
+ A_UINT32 vdev_id; /** Vdev ID */
+ A_UINT32 start; /** Start/Stop */
+ A_UINT32 sync_time; /** Lower 32-bit of the TSF at which the
+ * pulse should be synced. */
+ A_UINT32 pulse_interval; /** Periodicity of pulses in micro seconds */
+ A_UINT32 active_sync_period; /** Number of beacons to sync before generating
+ * pulse in units of beacon interval.
+ * Valid for clock slaves only. */
+ A_UINT32 gpio_pin; /** GPIO Pin number to be used */
+ A_UINT32 pulse_width; /** Duration of pulse in micro seconds */
+} wmi_hpcs_pulse_start_cmd_fixed_param;
+
+typedef struct {
+ /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_muedca_params_config_event_fixed_param */
+ A_UINT32 tlv_header; /** TLV Header */
+ A_UINT32 pdev_id;
+ /*
+ * The following per-AC arrays are indexed using the
+ * WMI_AC_xxx / wmi_traffic_ac enum values.
+ */
+ /* aifsn
+ * Arbitration inter frame spacing number (AIFSN)
+ * Values are integers used for back off computation.
+ */
+ A_UINT32 aifsn[WMI_AC_MAX];
+ /* ecwmin
+ * Exponent form of ContentionWindow min (ECWmin)
+ * Values are integers used for back off computation.
+ */
+ A_UINT32 ecwmin[WMI_AC_MAX];
+ /* ecwmax
+ * Exponent form of ContentionWindow max (ECWmax)
+ * Values are integers used for back off computation.
+ */
+ A_UINT32 ecwmax[WMI_AC_MAX];
+ /* muedca_expiration_time
+ * MU EDCA Expiration time refers to the length of time after the most
+ * recent UL trigger time. The MU EDCA Timer field indicates the time
+ * limit, in units of 8 TUs
+ */
+ A_UINT32 muedca_expiration_time[WMI_AC_MAX];
+ } wmi_muedca_params_config_event_fixed_param;
+
+/* Default PE Duration subfield indicates the PE duration in units of 4 us */
+#define WMI_HEOPS_DEFPE_GET_D3(he_ops) WMI_GET_BITS(he_ops, 0, 3)
+#define WMI_HEOPS_DEFPE_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 0, 3, value)
+
+/* TWT required */
+#define WMI_HEOPS_TWT_REQUIRED_GET_D3(he_ops) WMI_GET_BITS(he_ops, 3, 1)
+#define WMI_HEOPS_TWT_REQUIRED_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 3, 1, value)
+
+/* RTS threshold in units of 32 us,0 - always use RTS 1023 - this is disabled */
+#define WMI_HEOPS_RTSTHLD_GET_D3(he_ops) WMI_GET_BITS(he_ops, 4, 10)
+#define WMI_HEOPS_RTSTHLD_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 4, 10, value)
+
+/* VHT Operation Information Present */
+#define WMI_HEOPS_VHTOPSPRSNT_GET_D3(he_ops) WMI_GET_BITS(he_ops, 14, 1)
+#define WMI_HEOPS_VHTOPSPRSNT_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 14, 1, value)
+
+/* Co-Located BSS */
+#define WMI_HEOPS_COLOCBSS_GET_D3(he_ops) WMI_GET_BITS(he_ops, 15, 1)
+#define WMI_HEOPS_COLOCBSS_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 15, 1, value)
+
+/* ER SU Disable */
+#define WMI_HEOPS_ERSUDIS_GET_D3(he_ops) WMI_GET_BITS(he_ops, 16, 1)
+#define WMI_HEOPS_ERSUDIS_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 16, 1, value)
+
+/* bit17 - bit23 are reserved */
+
+/* BSS color */
+#define WMI_HEOPS_COLOR_GET_D3(he_ops) WMI_GET_BITS(he_ops, 24, 6)
+#define WMI_HEOPS_COLOR_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 24, 6, value)
+
+/* Partial BSS Color field indicates whether BSS applies an AID assignment rule using partial BSS color bits */
+#define WMI_HEOPS_PARTBSSCOLOR_GET_D3(he_ops) WMI_GET_BITS(he_ops, 30, 1)
+#define WMI_HEOPS_PARTBSSCOLOR_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 30, 1, value)
+
+/* when set to 1 disables use of BSS color */
+#define WMI_HEOPS_BSSCOLORDISABLE_GET_D3(he_ops) WMI_GET_BITS(he_ops, 31, 1)
+#define WMI_HEOPS_BSSCOLORDISABLE_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 31, 1, value)
+
+/* PHY Capabilities Information field */
+
+
+/* bit 0 reserved */
+
+/*
+ * B0: Indicates STA support 40 MHz channel width in 2.4 GHz
+ * B1: Indicates STA support 40 MHz and 80 MHz channel width in 5 GHz
+ * B2: Indicates STA supports 160 MHz channel width in 5 GHz
+ * B3: Indicates STA supports 160/80+80 MHz channel width in 5 GHz
+ * B4: If B1 is set to 0, then B5 indicates support of 242/106/52/26-tone
+ * RU mapping in 40 MHz channel width in 2.4 GHz. Otherwise Reserved.
+ * B5: If B2, B3, and B4 are set to 0, then B6 indicates support of
+ * 242-tone RU mapping in 40 MHz and 80
+ * MHz channel width in 5 GHz. Otherwise Reserved.
+ * B6: Reserved
+ */
+#define WMI_HECAP_PHY_CBW_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 1, 7)
+#define WMI_HECAP_PHY_CBW_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 1, 7, value)
+
+/*
+ * B0: Indicates STA supports reception of preamble puncturing in 80 MHz,
+ * where in the preamble only the secondary 20 MHz is punctured
+ * B1: Indicates STA supports reception of preamble puncturing in 80 MHz,
+ * where in the preamble only one of the two 20 MHz sub-channels in the
+ * secondary 40 MHz is punctured
+ * B2: Indicates STA supports reception of preamble puncturing in 160 MHz
+ * or 80+80 MHz, where in the primary 80 MHz of the preamble only the
+ * secondary 20 MHz is punctured
+ * B3: Indicates STA supports reception of preamble puncturing in 160 MHz
+ * or 80+80 MHz, where in the primary 80 MHz of the preamble, the
+ * primary 40 MHz is present
+ */
+#define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 8, 4)
+#define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 8, 4, value)
+
+/* Indicates transmitting STA is a Class A (1) or a Class B (0) device */
+#define WMI_HECAP_PHY_COD_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 12, 1)
+#define WMI_HECAP_PHY_COD_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 12, 1, value)
+
+/* Indicates support of transmission and reception of LDPC encoded packets */
+#define WMI_HECAP_PHY_LDPC_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 13, 1)
+#define WMI_HECAP_PHY_LDPC_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 13, 1, value)
+
+/*
+ * B0: Indicates support of reception of 1x LTF and 0.8us guard interval duration for HE SU PPDUs.
+ */
+#define WMI_HECAP_PHY_LTFGIFORHE_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 14, 1)
+#define WMI_HECAP_PHY_LTFGIFORHE_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 14, 1, value)
+
+/*
+ * If the Doppler Rx subfield is 1, indicates the maximum number of space-time streams supported for reception
+ * when a midamble is present in the Data field.
+ * If the Doppler Tx subfield is 1, indicates the maximum number of space-time streams supported for transmission
+ * when a midamble is present in the Data field.
+ * If both Doppler Rx and Doppler Tx subfields are 1, indicates the maximum number of space-time streams
+ * supported for transmission and reception when a midamble is present in the Data field.
+ */
+#define WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 15, 2)
+#define WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 15, 2, value)
+
+/*
+ * B0: For a transmitting STA acting as beamformee, it indicates support of
+ * NDP reception using 4x LTF and 3.2 us guard interval duration
+ */
+#define WMI_HECAP_PHY_LTFGIFORNDP_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 17, 1)
+#define WMI_HECAP_PHY_LTFGIFORNDP_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 17, 1, value)
+
+/*
+ * indicates support for the transmission of an HE TB PPDU that has a
+ * bandwidth less than or equal to 80 MHz and is using STBC and with
+ * one spatial stream
+ */
+#define WMI_HECAP_PHY_TXSTBC_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 18, 1)
+#define WMI_HECAP_PHY_TXSTBC_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 18, 1, value)
+
+/* indicates support for the reception of HE PPDUs using STBC with one spatial stream for <= 80MHz Tx */
+#define WMI_HECAP_PHY_RXSTBC_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 19, 1)
+#define WMI_HECAP_PHY_RXSTBC_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 19, 1, value)
+
+/* indicates transmitting STA supports transmitting HE PPDUs with Doppler procedure */
+#define WMI_HECAP_PHY_TXDOPPLER_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 20, 1)
+#define WMI_HECAP_PHY_TXDOPPLER_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 20, 1, value)
+
+/* indicates transmitting STA supports receiving HE PPDUs with Doppler procedure */
+#define WMI_HECAP_PHY_RXDOPPLER_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 21, 1)
+#define WMI_HECAP_PHY_RXDOPPLER_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 21, 1, value)
+
+/*
+ * If the transmitting STA is an AP:
+ * indicates STA supports of reception of full bandwidth UL MU-MIMO
+ * transmission.
+ * If the transmitting STA is a non-AP STA:
+ * indicates STA supports of transmission of full bandwidth UL MU-MIMO
+ * transmission.
+ */
+#define WMI_HECAP_PHY_UL_MU_MIMO_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 22, 1)
+#define WMI_HECAP_PHY_UL_MU_MIMO_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 22, 1, value)
+
+/*
+ * If the transmitting STA is an AP:
+ * indicates STA supports of reception of UL MUMIMO transmission on an
+ * RU in an HE MU PPDU where the RU does not span the entire PPDU bandwidth.
+ * If the transmitting STA is a non-AP STA:
+ * indicates STA supports of transmission of UL MU-MIMO transmission on an
+ * RU in an HE MU PPDU where the RU does not span the entire PPDU bandwidth.
+ */
+#define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 23, 1)
+#define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 23, 1, value)
+
+/* Tx DCM
+ * B0:B1
+ * 00: Does not support DCM
+ * 01: BPSK
+ * 10: QPSK
+ * 11: 16-QAM
+ * B2 signals maximum number of spatial streams with DCM
+ * 0: 1 spatial stream
+ * 1: 2 spatial streams
+ */
+#define WMI_HECAP_PHY_DCMTX_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 24, 3)
+#define WMI_HECAP_PHY_DCMTX_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 24, 3, value)
+
+/* Rx DCM
+ * B0:B1
+ * 00: Does not support DCM
+ * 01: BPSK
+ * 10: QPSK
+ * 11: 16-QAM
+ * B2 signals maximum number of spatial streams with DCM
+ * 0: 1 spatial stream
+ * 1: 2 spatial streams
+ */
+#define WMI_HECAP_PHY_DCMRX_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 27, 3)
+#define WMI_HECAP_PHY_DCMRX_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 27, 3, value)
+
+
+/*
+ * Indicates that the STA supports the reception of an HE MU PPDU payload
+ * over full bandwidth and partial bandwidth (106-tone RU within 20 MHz).
+ */
+#define WMI_HECAP_PHY_ULHEMU_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 30, 1)
+#define WMI_HECAP_PHY_ULHEMU_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 30, 1, value)
+
+/* Indicates support for operation as an SU beamformer */
+#define WMI_HECAP_PHY_SUBFMR_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 31, 1)
+#define WMI_HECAP_PHY_SUBFMR_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 31, 1, value)
+
+/* Indicates support for operation as an SU beamformee */
+#define WMI_HECAP_PHY_SUBFME_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 0, 1)
+#define WMI_HECAP_PHY_SUBFME_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 0, 1, value)
+
+/* Indicates support for operation as an MU Beamformer */
+#define WMI_HECAP_PHY_MUBFMR_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 1, 1)
+#define WMI_HECAP_PHY_MUBFMR_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 1, 1, value)
+
+/*
+ * Num STS -1 for <= 80MHz (min val 3)
+ * The maximum number of space-time streams minus 1 that the STA can
+ * receive in an HE NDP
+ */
+#define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 2, 3)
+#define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 2, 3, value)
+
+
+/*
+ * Num STS -1 for > 80MHz (min val 3)
+ * The maximum number of space-time streams minus 1 that the STA can
+ * receive in an HE NDP
+ */
+#define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3)
+#define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value)
+
+
+/*
+ * Number Of Sounding Dimensions For <= 80 MHz
+ * If SU beamformer capable, set to the maximum supported value of the
+ * TXVECTOR parameter NUM_STS minus 1.
+ * Otherwise, reserved.
+ */
+#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3)
+#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value)
+
+/*
+ * Number Of Sounding Dimensions For > 80 MHz
+ * If SU beamformer capable, set to the maximum supported value of the
+ * TXVECTOR parameter NUM_STS minus 1.
+ * Otherwise, reserved.
+ */
+#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 11, 3)
+#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 11, 3, value)
+
+/*
+ * Indicates if the HE beamformee is capable of feedback with tone
+ * grouping of 16 in the HE Compressed Beamforming Report field for
+ * a SU-type feedback.
+ */
+#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 14, 1)
+#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 14, 1, value)
+
+/*
+ * Indicates if the HE beamformee is capable of feedback with tone
+ * grouping of 16 in the HE Compressed Beamforming Report field for
+ * a MU-type feedback.
+ */
+#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 15, 1)
+#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 15, 1, value)
+
+/*
+ * Indicates if HE beamformee is capable of feedback with codebook
+ * size {4, 2} in the HECompressed Beamforming Report field for
+ * a SU-type feedback.
+ */
+#define WMI_HECAP_PHY_CODBK42SU_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 16, 1)
+#define WMI_HECAP_PHY_CODBK42SU_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 16, 1, value)
+
+/*
+ * Indicates if HE beamformee is capable of feedback with codebook
+ * size {7, 5} in the HE Compressed Beamforming Report field for
+ * a MU-type feedback.
+ */
+#define WMI_HECAP_PHY_CODBK75MU_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 17, 1)
+#define WMI_HECAP_PHY_CODBK75MU_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 17, 1, value)
+
+/*
+ * Beamforming Feedback With Trigger Frame
+ * If the transmitting STA is an AP STA:
+ * B0: indicates support of reception of SU-Type partial(1) and full bandwidth feedback(0)
+ * B1: indicates support of reception of MU-Type partial(1) bandwidth feedback
+ * B2: indicates support of reception of CQI-Only partial and full bandwidth feedback
+ * If the transmitting STA is a non-AP STA:
+ * B0: indicates support of transmission of SU-Type partial(1) and full bandwidth(0) feedback
+ * B1: indicates support of transmission of MU-Type partial(1) bandwidth feedback
+ * B2: indicates support of transmission of CQI-Onlypartial (1)and full bandwidth feedback
+ */
+#define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 18, 3)
+#define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 18, 3, value)
+
+/* Indicates the support of transmission and reception of an HE extended range SU PPDU payload transmitted
+ * over the right 106-tone RU or partial BW ER
+ */
+#define WMI_HECAP_PHY_HEERSU_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 21, 1)
+#define WMI_HECAP_PHY_HEERSU_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 21, 1, value)
+
+/* Indicates that the non-AP STA supports reception of a DL MU-MIMO transmission on an RU in an HE MU PPDU
+ * where the RU does not span the entire PPDU bandwidth.
+ */
+#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 22, 1)
+#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 22, 1, value)
+
+/* Indicates whether or not the PPE Threshold field is present */
+#define WMI_HECAP_PHY_PETHRESPRESENT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 23, 1)
+#define WMI_HECAP_PHY_PETHRESPRESENT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 23, 1, value)
+
+/* Indicates that the STA supports SRP-based SR operation */
+#define WMI_HECAP_PHY_SRPSPRESENT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 24, 1)
+#define WMI_HECAP_PHY_SRPPRESENT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 24, 1, value)
+
+/* Indicates that the STA supports a power boost factor ar for the r-th RU in the range [0.5, 2] */
+#define WMI_HECAP_PHY_PWRBOOSTAR_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 25, 1)
+#define WMI_HECAP_PHY_PWRBOOSTAR_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 25, 1, value)
+
+/* Indicates support for the reception of 4x LTF and 0.8us guard interval duration for HE SU PPDUs. */
+#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 26, 1)
+#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 26, 1, value)
+
+/* For a transmitting STA acting as a beamformee, it indicates the maximum Nc for beamforming sounding
+ * feedback supported If SU beamformee capable, then set to the maximum Nc for beamforming sounding feedback
+ * minus 1. Otherwise, reserved.
+ */
+#define WMI_HECAP_PHY_MAXNC_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 27, 3)
+#define WMI_HECAP_PHY_MAXNC_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 27, 3, value)
+
+/* Indicates support for the transmission of an HE PPDU that has a bandwidth greater than 80 MHz and is using
+ * STBC with one spatial stream
+ */
+#define WMI_HECAP_PHY_STBCTXGT80_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 30, 1)
+#define WMI_HECAP_PHY_STBCTXGT80_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 30, 1, value)
+
+/* Indicates support for the reception of an HE PPDU that has a bandwidth greater than 80 MHz and is using
+ * STBC with one spatial stream
+ */
+#define WMI_HECAP_PHY_STBCRXGT80_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 31, 1)
+#define WMI_HECAP_PHY_STBCRXGT80_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 31, 1, value)
+
+/* Indicates support for the reception of an HE ER SU PPDU with 4x LTF and 0.8 us guard interval duration */
+#define WMI_HECAP_PHY_ERSU4X800NSECGI_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 0, 1)
+#define WMI_HECAP_PHY_ERSU4X800NSECGI_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 0, 1, value)
+
+/*
+ * Indicates support of 26-, 52-, and 106-tone mapping for a 20 MHz operating non-AP HE STA that is the
+ * receiver of a 40 MHz HE MU PPDU in 2.4 GHz band, or the transmitter of a 40 MHz HE TB PPDU in 2.4GHz band.
+ */
+#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 1, 1)
+#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 1, 1, value)
+
+/*
+ * Indicates support of 26-, 52-, and 106-tone mapping for a 20 MHz operating non-AP HE STA that is the
+ * receiver of a 80+80 MHz or a 160 MHz HE MU PPDU, or the transmitter of a 80+80 MHz or 160 MHz HE TB PPDU.
+ */
+#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 2, 1)
+#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 2, 1, value)
+
+/*
+ * Indicates supports of 160 MHz OFDMA for a non-AP HE STA that sets bit B1 of Channel Width Set to 1, and
+ * sets B2 and B3 of Channel Width Set each to 0, when operating with 80 MHz channel width. The capability
+ * bit is applicable while receiving a 80+80 MHz or a 160 MHz HE MU PPDU, or transmitting a 80+80 MHz or a
+ * 160 MHz HE TB PPDU.
+ */
+#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 3, 1)
+#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 3, 1, value)
+
+/* Indicates support for the reception of an HE ER SU PPDU with 1x LTF and 0.8 us guard interval duration */
+#define WMI_HECAP_PHY_ERSU1X800NSECGI_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 4, 1)
+#define WMI_HECAP_PHY_ERSU1X800NSECGI_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 4, 1, value)
+
+/*
+ * If the Doppler Rx subfield is 1, indicates support for receiving midambles with 2x HE-LTF, 1x HE-LTF in
+ * HE SU PPDU if the HE SU PPDU With 1x HE-LTF And 0.8 s GI subfield is set to 1, and 1x HE-LTF in
+ * HE ER SU PPDU if the HE ER SU PPDU With 1x HELTF And 0.8 s GI subfield is set to 1.
+ *
+ * If the Doppler Tx subfield is 1, indicates support for transmitting midambles with 2x HE-LTF, 1x HE-LTF
+ * in HE TB PPDU when allowed.
+
+ * If both the Doppler Rx and Doppler Tx subfields are 1, indicates support for receiving midambles with 2x HELTF,
+ * 1x HE-LTF in HE SU PPDU if the HE SU PPDU With 1x HE-LTF And 0.8 s GI subfield is set to 1, and
+ * 1x HE-LTF in HE ER SU PPDU if the HE ER SU PPDU With 1x HE-LTF And 0.8 s GI subfield is set
+ * to 1; and also support for transmitting midambles with 2x HE-LTF, 1x HE-LTF in HE TB PPDU when allowed.
+ */
+#define WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 5, 1)
+#define WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 5, 1, value)
+
+/*
+ * If the DCM Max Constellation Tx subfield is greater than 0, then the DCM Max BW subfield indicates the
+ * maximum bandwidth of a PPDU that the STA might transmit with DCM applied.
+ *
+ * If the DCM Max Constellation Rx subfield is greater than 0, then the DCM Max BW subfield indicates the
+ * maximum bandwidth of a PPDU with DCM applied that the STA can receive.
+ *
+ * If both the DCM Max Constellation Tx subfield and DCM Max Constellation Rx subfield are 0, then this
+ * subfield is reserved.
+ *
+ * 0=20MHz, 1=40Mhz, 2=80Mhz, 3=160Mhz or 80+80Mhz
+ */
+#define WMI_HECAP_PHY_DCMMAXBW_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 6, 2)
+#define WMI_HECAP_PHY_DCMMAXBW_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 6, 2, value)
+
+/*
+ * For a non-AP STA, indicates support for receiving a DL HE MU PPDU where the number of OFDM symbols
+ * in the HE SIG-B field is greater than 16.
+ */
+#define WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 8, 1)
+#define WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 8, 1, value)
+
+/*
+ * For an AP, indicates support for the reception of full bandwidth non-triggered CQI-only feedback.
+ * For a non-AP STA, indicates support for the transmission of full bandwidth non-triggered CQI-only feedback.
+ */
+#define WMI_HECAP_PHY_NONTRIGCQIFEEDBK_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 9, 1)
+#define WMI_HECAP_PHY_NONTRIGCQIFEEDBK_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 9, 1, value)
+
+/*
+ * For a non-AP STA, indicates support for the transmission of 1024-QAM on a 26-, 52-, and 106-tone RU.
+ * Reserved for an AP.
+ */
+#define WMI_HECAP_PHY_TX1024QAM242RUSUPRT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 10, 1)
+#define WMI_HECAP_PHY_TX1024QAM242RUSUPRT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 10, 1, value)
+
+/*
+ * Indicates support for the reception of 1024-QAM on a 26-, 52-, and 106-tone RU.
+ */
+#define WMI_HECAP_PHY_RX1024QAM242RUSUPRT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 11, 1)
+#define WMI_HECAP_PHY_RX1024QAM242RUSUPRT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 11, 1, value)
+
+/*
+ * Indicates support for reception of an HE MU PPDU with an RU spanning the entire PPDU bandwidth and a
+ * compressed HE-SIG-B format.
+ */
+#define WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 12, 1)
+#define WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 12, 1, value)
+
+/*
+ * Indicates support for reception of an HE MU PPDU with a bandwidth less than or equal to 80 MHz, an RU
+ * spanning the entire PPDU bandwidth and a non-compressed HE-SIG-B format.
+ */
+#define WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 13, 1)
+#define WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 13, 1, value)
+
+/* HE MAC Capabilities Information field format */
+
+/* HTC + HE Support Set to 1 if STA supports reception of HE Variant HT control Field */
+#define WMI_HECAP_MAC_HECTRL_GET_D3(he_cap) WMI_GET_BITS(he_cap, 0, 1)
+#define WMI_HECAP_MAC_HECTRL_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 0, 1, value)
+
+/* set to 1 to for TWT Requestor support */
+#define WMI_HECAP_MAC_TWTREQ_GET_D3(he_cap) WMI_GET_BITS(he_cap, 1, 1)
+#define WMI_HECAP_MAC_TWTREQ_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 1, 1, value)
+
+/* set to 1 to for TWT Responder support */
+#define WMI_HECAP_MAC_TWTRSP_GET_D3(he_cap) WMI_GET_BITS(he_cap, 2, 1)
+#define WMI_HECAP_MAC_TWTRSP_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 2, 1, value)
+
+/* Level of frag support
+ Set to 0 for no support for dynamic fragmentation.
+ Set to 1 for support for dynamic fragments that are contained within a S-MPDU
+ Set to 2 for support for dynamic fragments that are contained within a Single MPDU and support for up to
+ one dynamic fragment for each MSDU and each MMPDU within an A-MPDU or multi-TID A-MPDU.
+ Set to 3 for support for dynamic fragments that are contained within a Single MPDU and support for multiple
+ dynamic fragments for each MSDU within an AMPDU or multi-TID AMPDU and up to one dynamic fragment
+ for each MMPDU in a multi-TID A-MPDU that is not a Single MPDU
+*/
+#define WMI_HECAP_MAC_HEFRAG_GET_D3(he_cap) WMI_GET_BITS(he_cap, 3, 2)
+#define WMI_HECAP_MAC_HEFRAG_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 3, 2, value)
+
+/* The maximum number of fragmented MSDUs, Nmax,defined by this field is Nmax = 2 Maximum Number Of FMPDUs */
+#define WMI_HECAP_MAC_MAXFRAGMSDU_GET_D3(he_cap) WMI_GET_BITS(he_cap, 5, 3)
+#define WMI_HECAP_MAC_MAXFRAGMSDU_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 5, 3, value)
+
+
+/* 0 = no restriction on the minimum payload , 1 = 128 octets min, 2 = 256 octets min, 3 = 512 octets min */
+#define WMI_HECAP_MAC_MINFRAGSZ_GET_D3(he_cap) WMI_GET_BITS(he_cap, 8, 2)
+#define WMI_HECAP_MAC_MINFRAGSZ_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 8, 2, value)
+
+/*0 = no additional processing time, 1 = 8us,2 = 16us */
+#define WMI_HECAP_MAC_TRIGPADDUR_GET_D3(he_cap) WMI_GET_BITS(he_cap, 10, 2)
+#define WMI_HECAP_MAC_TRIGPADDUR_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 10, 2, value)
+
+/* Indicates the number of TIDs of QoS Data frames that an HE STA can receive in a multi-TID AMPDU */
+#define WMI_HECAP_MAC_MTID_RX_GET_D3(he_cap) WMI_GET_BITS(he_cap, 12, 3)
+#define WMI_HECAP_MAC_MTID_RX_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 12, 3, value)
+
+/* Indicates support for link adaptation using the HLA Control subfield. */
+#define WMI_HECAP_MAC_HELINK_ADPT_GET_D3(he_cap) WMI_GET_BITS(he_cap, 15, 2)
+#define WMI_HECAP_MAC_HELINK_ADPT_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 15, 2, value)
+
+/* Set to 1 for reception of AllAck support */
+#define WMI_HECAP_MAC_AACK_GET_D3(he_cap) WMI_GET_BITS(he_cap, 17, 1)
+#define WMI_HECAP_MAC_AACK_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 17, 1, value)
+
+/* Set to 1 if the STA supports reception of the UL MU Response Scheduling A-Control field */
+#define WMI_HECAP_MAC_TRS_GET_D3(he_cap) WMI_GET_BITS(he_cap, 18, 1)
+#define WMI_HECAP_MAC_TRS_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 18, 1, value)
+
+/* Set to 1 if the STA supports the BSR A-Control field functionality.*/
+#define WMI_HECAP_MAC_BSR_GET_D3(he_cap) WMI_GET_BITS(he_cap, 19, 1)
+#define WMI_HECAP_MAC_BSR_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 19, 1, value)
+
+/* Set to 1 when the STA supports broadcast TWT functionality.*/
+#define WMI_HECAP_MAC_BCSTTWT_GET_D3(he_cap) WMI_GET_BITS(he_cap, 20, 1)
+#define WMI_HECAP_MAC_BCSTTWT_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 20, 1, value)
+
+/* Set to 1 if STA supports rx of Multi-STA BA that has 32-bit Block Ack Bitmap */
+#define WMI_HECAP_MAC_32BITBA_GET_D3(he_cap) WMI_GET_BITS(he_cap, 21, 1)
+#define WMI_HECAP_MAC_32BITBA_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 21, 1, value)
+
+/* Set to 1 if the STA supports MU cascading operation */
+#define WMI_HECAP_MAC_MUCASCADE_GET_D3(he_cap) WMI_GET_BITS(he_cap, 22, 1)
+#define WMI_HECAP_MAC_MUCASCADE_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 22, 1, value)
+
+/* Set to 1 when the STA supports reception of this multi-TID A-MPDU format */
+#define WMI_HECAP_MAC_ACKMTIDAMPDU_GET_D3(he_cap) WMI_GET_BITS(he_cap, 23, 1)
+#define WMI_HECAP_MAC_ACKMTIDAMPDU_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 23, 1, value)
+
+/* bit 24 - reserved */
+
+/* Set to 1 if the STA supports reception of the OMI A-Control field */
+#define WMI_HECAP_MAC_OMI_GET_D3(he_cap) WMI_GET_BITS(he_cap, 25, 1)
+#define WMI_HECAP_MAC_OMI_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 25, 1, value)
+
+/*1 if OFDMA Random Access Supported */
+#define WMI_HECAP_MAC_OFDMARA_GET_D3(he_cap) WMI_GET_BITS(he_cap, 26, 1)
+#define WMI_HECAP_MAC_OFDMARA_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 26, 1, value)
+
+/* Maximum AMPDU Length Exponent.
+ * If the HE STA includes a VHT Capabilities element, the Maximum A-MPDU Length Exponent subfield in
+ * HE Capabilities element combined with the Maximum A-MPDU Length Exponent subfield in VHT
+ * Capabilities element indicate the maximum length of A-MPDU that the STA can Receive where EOF
+ * padding is not included in this limit.
+*/
+#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET_D3(he_cap) WMI_GET_BITS(he_cap, 27, 2)
+#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 27, 2, value)
+
+
+/* A-MSDU Fragmentation Support */
+#define WMI_HECAP_MAC_AMSDUFRAG_GET_D3(he_cap) WMI_GET_BITS(he_cap, 29, 1)
+#define WMI_HECAP_MAC_AMSDUFRAG_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 29, 1, value)
+
+/* Flexible TWT Schedule Support */
+#define WMI_HECAP_MAC_FLEXTWT_GET_D3(he_cap) WMI_GET_BITS(he_cap, 30, 1)
+#define WMI_HECAP_MAC_FLEXTWT_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 30, 1, value)
+
+/* Rx Control Frame to MultiBSS */
+#define WMI_HECAP_MAC_MBSS_GET_D3(he_cap) WMI_GET_BITS(he_cap, 31, 1)
+#define WMI_HECAP_MAC_MBSS_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 31, 1, value)
+
+/* 2nd DWORD of HE MAC Capabilities */
+
+/* BSRP A-MPDU Aggregation
+ * maintaining compatability since we dont support this now so not wasting memory
+ */
+#define WMI_HECAP_MAC_BSRPAMPDU_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 0, 1)
+#define WMI_HECAP_MAC_BSRPAMPDU_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 0, 1, value)
+
+/* Quiet Time Period (QTP) operation
+ * maintaining compatability since we dont support this now so not wasting memory
+ */
+#define WMI_HECAP_MAC_QTP_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 1, 1)
+#define WMI_HECAP_MAC_QTP_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 1, 1, value)
+
+/* support by an AP for receiving an (A-)MPDU that contains a BQR in the
+ * A-Control subfield and support by a non-AP STA for generating an (A-)MPDU
+ * that contains a BQR in the A-Control subfield
+ * maintaining compatability since we dont support this now so not wasting memory
+ */
+#define WMI_HECAP_MAC_ABQR_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 2, 1)
+#define WMI_HECAP_MAC_ABQR_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 2, 1, value)
+
+/* Indicates support by the STA for the role of SRP Responder.*/
+#define WMI_HECAP_MAC_SRPRESP_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 3, 1)
+#define WMI_HECAP_MAC_SRPRESP_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 3, 1, value)
+
+/* Indicates support for a non-AP STA to follow the NDP feedback report procedure and respond to
+ * the NDP Feedback Report Poll Trigger frame.
+ */
+#define WMI_HECAP_MAC_NDPFDBKRPT_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 4, 1)
+#define WMI_HECAP_MAC_NDPFDBKRPT_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 4, 1, value)
+
+/* Indicates support for an AP to encode OPS information to TIM element of the FILS Discovery
+ * frames or TIM frames as described in AP operation for opportunistic power save.
+ * Indicates support for a non-AP STA to receive the opportunistic power save encoded TIM elements
+ */
+#define WMI_HECAP_MAC_OPS_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 5, 1)
+#define WMI_HECAP_MAC_OPS_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 5, 1, value)
+
+/* Indicates support by a STA to receive an ack-enabled A-MPDU in which an A-MSDU is carried in
+ * a QoS Data frame for which no block ack agreement exists.
+ */
+#define WMI_HECAP_MAC_AMSDUINAMPDU_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 6, 1)
+#define WMI_HECAP_MAC_AMSDUINAMPDU_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 6, 1, value)
+
+/* Indicates the number of TIDs of QoS Data frames that an HE STA can transmit in a multi-TID AMPDU */
+#define WMI_HECAP_MAC_MTID_TX_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 7, 3)
+#define WMI_HECAP_MAC_MTID_TX_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 7, 3, value)
+
+/* Indicates whether an HE STA supports an HE subchannel selective transmission operation */
+#define WMI_HECAP_MAC_SUBCHANSELTX_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 10, 1)
+#define WMI_HECAP_MAC_SUBCHANSELTX_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 10, 1, value)
+
+/* Indicates support by a STA to receive a TRS Control subfield or a Trigger frame with a User Info
+ * field addressed to the STA with the RU Allocation subfield of the TRS Control subfield or the User
+ * Info field indicating 2x996-tone.
+ */
+#define WMI_HECAP_MAC_UL2X996RU_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 11, 1)
+#define WMI_HECAP_MAC_UL2X996RU_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 11, 1, value)
+
+/* Indicates whether an AP supports interpretation of the UL MU Data Disable subfield of the OM Control subfield */
+#define WMI_HECAP_MAC_OMCULMUDDIS_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 12, 1)
+#define WMI_HECAP_MAC_OMCULMUDDIS_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 12, 1, value)
+
+/* Indicates the spatial multiplexing power save mode after receiving a
+ * Trigger frame that is in operation immediately after (re)association.
+ */
+#define WMI_HECAP_MAC_DYNSMPWRSAVE_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 13, 1)
+#define WMI_HECAP_MAC_DYNSMPWRSAVE_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 13, 1, value)
+
+/* Indicates support for Punctured Sounding */
+#define WMI_HECAP_MAC_PUNCSOUNDING_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 14, 1)
+#define WMI_HECAP_MAC_PUNCSOUNDING_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 14, 1, value)
+
+/* Indicates support for receiving a Trigger frame in an HT PPDU and
+ * receiving a Trigger frame in a VHT PPDU
+ */
+#define WMI_HECAP_MAC_HTVHTTRIGRX_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 15, 1)
+#define WMI_HECAP_MAC_HTVHTTRIGRX_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 15, 1, value)
+
+/*
+ * The following conditionally-defined macros can be used in systems
+ * which only support either 802.11ax draft 2 or 802.11ax draft 3,
+ * but not both, and which make this D2 vs. D3 selection at build time.
+ */
+#ifdef SUPPORT_11AX_D3
+ #define WMI_HEOPS_COLOR_GET WMI_HEOPS_COLOR_GET_D3
+ #define WMI_HEOPS_COLOR_SET WMI_HEOPS_COLOR_SET_D3
+ #define WMI_HEOPS_DEFPE_GET WMI_HEOPS_DEFPE_GET_D3
+ #define WMI_HEOPS_DEFPE_SET WMI_HEOPS_DEFPE_SET_D3
+ #define WMI_HEOPS_TWT_REQUIRED_GET WMI_HEOPS_TWT_REQUIRED_GET_D3
+ #define WMI_HEOPS_TWT_REQUIRED_SET WMI_HEOPS_TWT_REQUIRED_SET_D3
+ #define WMI_HEOPS_TWT_GET WMI_HEOPS_TWT_REQUIRED_GET_D3 /* DEPRECATED, use WMI_HEOPS_TWT_REQUIRED_GET */
+ #define WMI_HEOPS_TWT_SET WMI_HEOPS_TWT_REQUIRED_SET_D3 /* DEPRECATED, use WMI_HEOPS_TWT_REQUIRED_SET */
+ #define WMI_HEOPS_RTSTHLD_GET WMI_HEOPS_RTSTHLD_GET_D3
+ #define WMI_HEOPS_RTSTHLD_SET WMI_HEOPS_RTSTHLD_SET_D3
+ #define WMI_HEOPS_PARTBSSCOLOR_GET WMI_HEOPS_PARTBSSCOLOR_GET_D3
+ #define WMI_HEOPS_PARTBSSCOLOR_SET WMI_HEOPS_PARTBSSCOLOR_SET_D3
+ #define WMI_HEOPS_COLOCBSS_GET WMI_HEOPS_COLOCBSS_GET_D3
+ #define WMI_HEOPS_COLOCBSS_SET WMI_HEOPS_COLOCBSS_SET_D3
+ #define WMI_HEOPS_VHTOPSPRSNT_GET WMI_HEOPS_VHTOPSPRSNT_GET_D3
+ #define WMI_HEOPS_VHTOPSPRSNT_SET WMI_HEOPS_VHTOPSPRSNT_SET_D3
+ #define WMI_HEOPS_ERSUDIS_GET WMI_HEOPS_ERSUDIS_GET_D3
+ #define WMI_HEOPS_ERSUDIS_SET WMI_HEOPS_ERSUDIS_SET_D3
+ #define WMI_HEOPS_BSSCOLORDISABLE_GET WMI_HEOPS_BSSCOLORDISABLE_GET_D3
+ #define WMI_HEOPS_BSSCOLORDISABLE_SET WMI_HEOPS_BSSCOLORDISABLE_SET_D3
+ #define WMI_HEOPS_TXBSSID_GET(he_ops) (0) /* DEPRECATED - DO NOT USE */
+ #define WMI_HEOPS_TXBSSID_SET(he_ops, value) /* DEPRECATED - DO NOT USE */
+
+ #define WMI_HECAP_PHY_CBW_GET WMI_HECAP_PHY_CBW_GET_D3
+ #define WMI_HECAP_PHY_CBW_SET WMI_HECAP_PHY_CBW_SET_D3
+ #define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET WMI_HECAP_PHY_PREAMBLEPUNCRX_GET_D3
+ #define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET WMI_HECAP_PHY_PREAMBLEPUNCRX_SET_D3
+ #define WMI_HECAP_PHY_COD_GET WMI_HECAP_PHY_COD_GET_D3
+ #define WMI_HECAP_PHY_COD_SET WMI_HECAP_PHY_COD_SET_D3
+ #define WMI_HECAP_PHY_LDPC_GET WMI_HECAP_PHY_LDPC_GET_D3
+ #define WMI_HECAP_PHY_LDPC_SET WMI_HECAP_PHY_LDPC_SET_D3
+ #define WMI_HECAP_PHY_TXLDPC_GET WMI_HECAP_PHY_LDPC_GET /* Deprecated use WMI_HECAP_PHY_LDPC */
+ #define WMI_HECAP_PHY_TXLDPC_SET WMI_HECAP_PHY_LDPC_SET /* Deprecated use WMI_HECAP_PHY_LDPC */
+ #define WMI_HECAP_PHY_RXLDPC_GET WMI_HECAP_PHY_LDPC_GET /* Deprecated use WMI_HECAP_PHY_LDPC */
+ #define WMI_HECAP_PHY_RXLDPC_SET WMI_HECAP_PHY_LDPC_SET /* Deprecated use WMI_HECAP_PHY_LDPC */
+ #define WMI_HECAP_PHY_LTFGIFORHE_GET WMI_HECAP_PHY_LTFGIFORHE_GET_D3
+ #define WMI_HECAP_PHY_LTFGIFORHE_SET WMI_HECAP_PHY_LTFGIFORHE_SET_D3
+ #define WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET_D3
+ #define WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET_D3
+ #define WMI_HECAP_PHY_LTFGIFORNDP_GET WMI_HECAP_PHY_LTFGIFORNDP_GET_D3
+ #define WMI_HECAP_PHY_LTFGIFORNDP_SET WMI_HECAP_PHY_LTFGIFORNDP_SET_D3
+ #define WMI_HECAP_PHY_TXSTBC_GET WMI_HECAP_PHY_TXSTBC_GET_D3
+ #define WMI_HECAP_PHY_TXSTBC_SET WMI_HECAP_PHY_TXSTBC_SET_D3
+ #define WMI_HECAP_PHY_RXSTBC_GET WMI_HECAP_PHY_RXSTBC_GET_D3
+ #define WMI_HECAP_PHY_RXSTBC_SET WMI_HECAP_PHY_RXSTBC_SET_D3
+ #define WMI_HECAP_PHY_TXDOPPLER WMI_HECAP_PHY_TXDOPPLER_GET_D3
+ #define WMI_HECAP_PHY_TXDOPPLER_SET WMI_HECAP_PHY_TXDOPPLER_SET_D3
+ #define WMI_HECAP_PHY_RXDOPPLER_GET WMI_HECAP_PHY_RXDOPPLER_GET_D3
+ #define WMI_HECAP_PHY_RXDOPPLER_SET WMI_HECAP_PHY_RXDOPPLER_SET_D3
+ #define WMI_HECAP_PHY_UL_MU_MIMO_GET WMI_HECAP_PHY_UL_MU_MIMO_GET_D3
+ #define WMI_HECAP_PHY_UL_MU_MIMO_SET WMI_HECAP_PHY_UL_MU_MIMO_SET_D3
+ #define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D3
+ #define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D3
+ #define WMI_HECAP_PHY_DCMTX_GET WMI_HECAP_PHY_DCMTX_GET_D3
+ #define WMI_HECAP_PHY_DCMTX_SET WMI_HECAP_PHY_DCMTX_SET_D3
+ #define WMI_HECAP_PHY_DCMRX_GET WMI_HECAP_PHY_DCMRX_GET_D3
+ #define WMI_HECAP_PHY_DCMRX_SET WMI_HECAP_PHY_DCMRX_SET_D3
+ /* DEPRECATED - use WMI_HECAP_PHY_DCMRX or WMI_HECAP_PHY_DCMTX */
+ #define WMI_HECAP_PHY_DCM_GET WMI_HECAP_PHY_DCMRX_GET_D3
+ #define WMI_HECAP_PHY_DCM_SET WMI_HECAP_PHY_DCMRX_SET_D3
+ #define WMI_HECAP_PHY_ULHEMU_GET WMI_HECAP_PHY_ULHEMU_GET_D3
+ #define WMI_HECAP_PHY_ULHEMU_SET WMI_HECAP_PHY_ULHEMU_SET_D3
+ #define WMI_HECAP_PHY_SUBFMR_GET WMI_HECAP_PHY_SUBFMR_GET_D3
+ #define WMI_HECAP_PHY_SUBFMR_SET WMI_HECAP_PHY_SUBFMR_SET_D3
+ #define WMI_HECAP_PHY_SUBFME_GET WMI_HECAP_PHY_SUBFME_GET_D3
+ #define WMI_HECAP_PHY_SUBFME_SET WMI_HECAP_PHY_SUBFME_SET_D3
+ #define WMI_HECAP_PHY_MUBFMR_GET WMI_HECAP_PHY_MUBFMR_GET_D3
+ #define WMI_HECAP_PHY_MUBFMR_SET WMI_HECAP_PHY_MUBFMR_SET_D3
+ #define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D3
+ #define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D3
+ #define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D3
+ #define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D3
+ #define WMI_HECAP_PHY_NSTSLT80MHZ_GET WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D3
+ #define WMI_HECAP_PHY_NSTSLT80MHZ_SET WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D3
+ #define WMI_HECAP_PHY_NSTSGT80MHZ_GET WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D3
+ #define WMI_HECAP_PHY_NSTSGT80MHZ_SET WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D3
+ #define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET_D3
+ #define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET_D3
+ #define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET_D3
+ #define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET_D3
+ #define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET_D3
+ #define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET_D3
+ #define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET_D3
+ #define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET_D3
+ #define WMI_HECAP_PHY_CODBK42SU_GET WMI_HECAP_PHY_CODBK42SU_GET_D3
+ #define WMI_HECAP_PHY_CODBK42SU_SET WMI_HECAP_PHY_CODBK42SU_SET_D3
+ #define WMI_HECAP_PHY_CODBK75MU_GET WMI_HECAP_PHY_CODBK75MU_GET_D3
+ #define WMI_HECAP_PHY_CODBK75MU_SET WMI_HECAP_PHY_CODBK75MU_SET_D3
+ #define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET WMI_HECAP_PHY_BFFEEDBACKTRIG_GET_D3
+ #define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET WMI_HECAP_PHY_BFFEEDBACKTRIG_SET_D3
+ #define WMI_HECAP_PHY_HEERSU_GET WMI_HECAP_PHY_HEERSU_GET_D3
+ #define WMI_HECAP_PHY_HEERSU_SET WMI_HECAP_PHY_HEERSU_SET_D3
+ #define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET_D3
+ #define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET_D3
+ #define WMI_HECAP_PHY_PETHRESPRESENT_GET WMI_HECAP_PHY_PETHRESPRESENT_GET_D3
+ #define WMI_HECAP_PHY_PETHRESPRESENT_SET WMI_HECAP_PHY_PETHRESPRESENT_SET_D3
+ #define WMI_HECAP_PHY_SRPSPRESENT_GET WMI_HECAP_PHY_SRPSPRESENT_GET_D3
+ #define WMI_HECAP_PHY_SRPPRESENT_SET WMI_HECAP_PHY_SRPPRESENT_SET_D3
+ #define WMI_HECAP_PHY_PWRBOOSTAR_GET WMI_HECAP_PHY_PWRBOOSTAR_GET_D3
+ #define WMI_HECAP_PHY_PWRBOOSTAR_SET WMI_HECAP_PHY_PWRBOOSTAR_SET_D3
+ #define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET_D3
+ #define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET_D3
+ #define WMI_HECAP_PHY_MAXNC_GET WMI_HECAP_PHY_MAXNC_GET_D3
+ #define WMI_HECAP_PHY_MAXNC_SET WMI_HECAP_PHY_MAXNC_SET_D3
+ #define WMI_HECAP_PHY_STBCTXGT80_GET WMI_HECAP_PHY_STBCTXGT80_GET_D3
+ #define WMI_HECAP_PHY_STBCTXGT80_SET WMI_HECAP_PHY_STBCTXGT80_SET_D3
+ #define WMI_HECAP_PHY_STBCRXGT80_GET WMI_HECAP_PHY_STBCRXGT80_GET_D3
+ #define WMI_HECAP_PHY_STBCRXGT80_SET WMI_HECAP_PHY_STBCRXGT80_SET_D3
+ #define WMI_HECAP_PHY_ERSU4X800NSECGI_GET WMI_HECAP_PHY_ERSU4X800NSECGI_GET_D3
+ #define WMI_HECAP_PHY_ERSU4X800NSECGI_SET WMI_HECAP_PHY_ERSU4X800NSECGI_SET_D3
+ #define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET_D3
+ #define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET_D3
+ #define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET_D3
+ #define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET_D3
+ #define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET_D3
+ #define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET_D3
+ #define WMI_HECAP_PHY_ERSU1X800NSECGI_GET WMI_HECAP_PHY_ERSU1X800NSECGI_GET_D3
+ #define WMI_HECAP_PHY_ERSU1X800NSECGI_SET WMI_HECAP_PHY_ERSU1X800NSECGI_SET_D3
+ #define WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET_D3
+ #define WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET_D3
+ #define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET /* DEPRECATED */
+ #define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET /* DEPRECATED */
+ #define WMI_HECAP_PHY_DCMMAXBW_GET WMI_HECAP_PHY_DCMMAXBW_GET_D3
+ #define WMI_HECAP_PHY_DCMMAXBW_SET WMI_HECAP_PHY_DCMMAXBW_SET_D3
+ #define WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_GET WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_GET_D3
+ #define WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_SET WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_SET_D3
+ #define WMI_HECAP_PHY_NONTRIGCQIFEEDBK_GET WMI_HECAP_PHY_NONTRIGCQIFEEDBK_GET_D3
+ #define WMI_HECAP_PHY_NONTRIGCQIFEEDBK_SET WMI_HECAP_PHY_NONTRIGCQIFEEDBK_SET_D3
+ #define WMI_HECAP_PHY_TX1024QAM242RUSUPRT_GET WMI_HECAP_PHY_TX1024QAM242RUSUPRT_GET_D3
+ #define WMI_HECAP_PHY_TX1024QAM242RUSUPRT_SET WMI_HECAP_PHY_TX1024QAM242RUSUPRT_SET_D3
+ #define WMI_HECAP_PHY_RX1024QAM242RUSUPRT_GET WMI_HECAP_PHY_RX1024QAM242RUSUPRT_GET_D3
+ #define WMI_HECAP_PHY_RX1024QAM242RUSUPRT_SET WMI_HECAP_PHY_RX1024QAM242RUSUPRT_SET_D3
+ #define WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_GET WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_GET_D3
+ #define WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_SET WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_SET_D3
+ #define WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_GET WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_GET_D3
+ #define WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_SET WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_SET_D3
+ #define WMI_HECAP_PHY_DB_GET(he_phy_cap) (0) /* DEPRECATED - DO NOT USE */
+ #define WMI_HECAP_PHY_DB_SET(he_phy_cap, value) /* DEPRECATED - DO NOT USE */
+ #define WMI_HECAP_MAC_HECTRL_GET WMI_HECAP_MAC_HECTRL_GET_D3
+ #define WMI_HECAP_MAC_HECTRL_SET WMI_HECAP_MAC_HECTRL_SET_D3
+ #define WMI_HECAP_MAC_TWTREQ_GET WMI_HECAP_MAC_TWTREQ_GET_D3
+ #define WMI_HECAP_MAC_TWTREQ_SET WMI_HECAP_MAC_TWTREQ_SET_D3
+ #define WMI_HECAP_MAC_TWTRSP_GET WMI_HECAP_MAC_TWTRSP_GET_D3
+ #define WMI_HECAP_MAC_TWTRSP_SET WMI_HECAP_MAC_TWTRSP_SET_D3
+ #define WMI_HECAP_MAC_HEFRAG_GET WMI_HECAP_MAC_HEFRAG_GET_D3
+ #define WMI_HECAP_MAC_HEFRAG_SET WMI_HECAP_MAC_HEFRAG_SET_D3
+ #define WMI_HECAP_MAC_MAXFRAGMSDU_GET WMI_HECAP_MAC_MAXFRAGMSDU_GET_D3
+ #define WMI_HECAP_MAC_MAXFRAGMSDU_SET WMI_HECAP_MAC_MAXFRAGMSDU_SET_D3
+ #define WMI_HECAP_MAC_MINFRAGSZ_GET WMI_HECAP_MAC_MINFRAGSZ_GET_D3
+ #define WMI_HECAP_MAC_MINFRAGSZ_SET WMI_HECAP_MAC_MINFRAGSZ_SET_D3
+ #define WMI_HECAP_MAC_TRIGPADDUR_GET WMI_HECAP_MAC_TRIGPADDUR_GET_D3
+ #define WMI_HECAP_MAC_TRIGPADDUR_SET WMI_HECAP_MAC_TRIGPADDUR_SET_D3
+ #define WMI_HECAP_MAC_MTID_RX_GET WMI_HECAP_MAC_MTID_RX_GET_D3
+ #define WMI_HECAP_MAC_MTID_RX_SET WMI_HECAP_MAC_MTID_RX_SET_D3
+ #define WMI_HECAP_MAC_HELINK_ADPT_GET WMI_HECAP_MAC_HELINK_ADPT_GET_D3
+ #define WMI_HECAP_MAC_HELINK_ADPT_SET WMI_HECAP_MAC_HELINK_ADPT_SET_D3
+ #define WMI_HECAP_MAC_AACK_GET WMI_HECAP_MAC_AACK_GET_D3
+ #define WMI_HECAP_MAC_AACK_SET WMI_HECAP_MAC_AACK_SET_D3
+ #define WMI_HECAP_MAC_TRS_GET WMI_HECAP_MAC_TRS_GET_D3
+ #define WMI_HECAP_MAC_TRS_SET WMI_HECAP_MAC_TRS_SET_D3
+ #define WMI_HECAP_MAC_ULMURSP_GET(he_cap) (0) /* DEPRECATED, DO NOT USE */
+ #define WMI_HECAP_MAC_ULMURSP_SET(he_cap, value) /* DEPRECATED, DO NOT USE */
+ #define WMI_HECAP_MAC_BSR_GET WMI_HECAP_MAC_BSR_GET_D3
+ #define WMI_HECAP_MAC_BSR_SET WMI_HECAP_MAC_BSR_SET_D3
+ #define WMI_HECAP_MAC_BCSTTWT_GET WMI_HECAP_MAC_BCSTTWT_GET_D3
+ #define WMI_HECAP_MAC_BCSTTWT_SET WMI_HECAP_MAC_BCSTTWT_SET_D3
+ #define WMI_HECAP_MAC_32BITBA_GET WMI_HECAP_MAC_32BITBA_GET_D3
+ #define WMI_HECAP_MAC_32BITBA_SET WMI_HECAP_MAC_32BITBA_SET_D3
+ #define WMI_HECAP_MAC_MUCASCADE_GET WMI_HECAP_MAC_MUCASCADE_GET_D3
+ #define WMI_HECAP_MAC_MUCASCADE_SET WMI_HECAP_MAC_MUCASCADE_SET_D3
+ #define WMI_HECAP_MAC_ACKMTIDAMPDU_GET WMI_HECAP_MAC_ACKMTIDAMPDU_GET_D3
+ #define WMI_HECAP_MAC_ACKMTIDAMPDU_SET WMI_HECAP_MAC_ACKMTIDAMPDU_SET_D3
+ #define WMI_HECAP_MAC_GROUPMSTABA_GET(he_cap) (0) /* DEPRECATED, DO NOT USE */
+ #define WMI_HECAP_MAC_GROUPMSTABA_SET(he_cap, value) /* DEPRECATED, DO NOT USE */
+ #define WMI_HECAP_MAC_OMI_GET WMI_HECAP_MAC_OMI_GET_D3
+ #define WMI_HECAP_MAC_OMI_SET WMI_HECAP_MAC_OMI_SET_D3
+ #define WMI_HECAP_MAC_OFDMARA_GET WMI_HECAP_MAC_OFDMARA_GET_D3
+ #define WMI_HECAP_MAC_OFDMARA_SET WMI_HECAP_MAC_OFDMARA_SET_D3
+ #define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET_D3
+ #define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET_D3
+ #define WMI_HECAP_MAC_AMSDUFRAG_GET WMI_HECAP_MAC_AMSDUFRAG_GET_D3
+ #define WMI_HECAP_MAC_AMSDUFRAG_SET WMI_HECAP_MAC_AMSDUFRAG_SET_D3
+ #define WMI_HECAP_MAC_FLEXTWT_GET WMI_HECAP_MAC_FLEXTWT_GET_D3
+ #define WMI_HECAP_MAC_FLEXTWT_SET WMI_HECAP_MAC_FLEXTWT_SET_D3
+ #define WMI_HECAP_MAC_MBSS_GET WMI_HECAP_MAC_MBSS_GET_D3
+ #define WMI_HECAP_MAC_MBSS_SET WMI_HECAP_MAC_MBSS_SET_D3
+ #define WMI_HECAP_MAC_BSRPAMPDU_GET WMI_HECAP_MAC_BSRPAMPDU_GET_D3
+ #define WMI_HECAP_MAC_BSRPAMPDU_SET WMI_HECAP_MAC_BSRPAMPDU_SET_D3
+ #define WMI_HECAP_MAC_QTP_GET WMI_HECAP_MAC_QTP_GET_D3
+ #define WMI_HECAP_MAC_QTP_SET WMI_HECAP_MAC_QTP_SET_D3
+ #define WMI_HECAP_MAC_ABQR_GET WMI_HECAP_MAC_ABQR_GET_D3
+ #define WMI_HECAP_MAC_ABQR_SET WMI_HECAP_MAC_ABQR_SET_D3
+ #define WMI_HECAP_MAC_SRPRESP_GET WMI_HECAP_MAC_SRPRESP_GET_D3
+ #define WMI_HECAP_MAC_SRPRESP_SET WMI_HECAP_MAC_SRPRESP_SET_D3
+ #define WMI_HECAP_MAC_SRRESP_GET(he_cap2) (0) /* DEPRECATED, DO NOT USE */
+ #define WMI_HECAP_MAC_SRRESP_SET(he_cap2, value) /* DEPRECATED, DO NOT USE */
+ #define WMI_HECAP_MAC_NDPFDBKRPT_GET WMI_HECAP_MAC_NDPFDBKRPT_GET_D3
+ #define WMI_HECAP_MAC_NDPFDBKRPT_SET WMI_HECAP_MAC_NDPFDBKRPT_SET_D3
+ #define WMI_HECAP_MAC_OPS_GET WMI_HECAP_MAC_OPS_GET_D3
+ #define WMI_HECAP_MAC_OPS_SET WMI_HECAP_MAC_OPS_SET_D3
+ #define WMI_HECAP_MAC_AMSDUINAMPDU_GET WMI_HECAP_MAC_AMSDUINAMPDU_GET_D3
+ #define WMI_HECAP_MAC_AMSDUINAMPDU_SET WMI_HECAP_MAC_AMSDUINAMPDU_SET_D3
+ #define WMI_HECAP_MAC_MTID_TX_GET WMI_HECAP_MAC_MTID_TX_GET_D3
+ #define WMI_HECAP_MAC_MTID_TX_SET WMI_HECAP_MAC_MTID_TX_SET_D3
+ #define WMI_HECAP_MAC_SUBCHANSELTX_GET WMI_HECAP_MAC_SUBCHANSELTX_GET_D3
+ #define WMI_HECAP_MAC_SUBCHANSELTX_SET WMI_HECAP_MAC_SUBCHANSELTX_SET_D3
+ #define WMI_HECAP_MAC_UL2X996RU_GET WMI_HECAP_MAC_UL2X996RU_GET_D3
+ #define WMI_HECAP_MAC_UL2X996RU_SET WMI_HECAP_MAC_UL2X996RU_SET_D3
+ #define WMI_HECAP_MAC_OMCULMUDDIS_GET WMI_HECAP_MAC_OMCULMUDDIS_GET_D3
+ #define WMI_HECAP_MAC_OMCULMUDDIS_SET WMI_HECAP_MAC_OMCULMUDDIS_SET_D3
+ #define WMI_HECAP_MAC_HELKAD_GET(he_cap) (0) /* DEPRECATED, DO NOT USE */
+ #define WMI_HECAP_MAC_HELKAD_SET(he_cap, value) /* DEPRECATED, DO NOT USE */
+ #define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET_D3 /* DEPRECATED - DO NOT USE */
+ #define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET_D3 /* DEPRECATED - DO NOT USE */
+ #define WMI_HECAP_MAC_DYNSMPWRSAVE_GET WMI_HECAP_MAC_DYNSMPWRSAVE_GET_D3
+ #define WMI_HECAP_MAC_DYNSMPWRSAVE_SET WMI_HECAP_MAC_DYNSMPWRSAVE_SET_D3
+ #define WMI_HECAP_MAC_PUNCSOUNDING_GET WMI_HECAP_MAC_PUNCSOUNDING_GET_D3
+ #define WMI_HECAP_MAC_PUNCSOUNDING_SET WMI_HECAP_MAC_PUNCSOUNDING_SET_D3
+ #define WMI_HECAP_MAC_HTVHTTRIGRX_GET WMI_HECAP_MAC_HTVHTTRIGRX_GET_D3
+ #define WMI_HECAP_MAC_HTVHTTRIGRX_SET WMI_HECAP_MAC_HTVHTTRIGRX_SET_D3
+#else /* SUPPORT_11AX_D3 vs. D2 */
+ /* D2 and D2- */
+ #define WMI_HEOPS_COLOR_GET WMI_HEOPS_COLOR_GET_D2
+ #define WMI_HEOPS_COLOR_SET WMI_HEOPS_COLOR_SET_D2
+ #define WMI_HEOPS_DEFPE_GET WMI_HEOPS_DEFPE_GET_D2
+ #define WMI_HEOPS_DEFPE_SET WMI_HEOPS_DEFPE_SET_D2
+ #define WMI_HEOPS_TWT_REQUIRED_GET WMI_HEOPS_TWT_REQUIRED_GET_D2
+ #define WMI_HEOPS_TWT_REQUIRED_SET WMI_HEOPS_TWT_REQUIRED_SET_D2
+ #define WMI_HEOPS_TWT_GET WMI_HEOPS_TWT_GET_D2 /* Deprecated */
+ #define WMI_HEOPS_TWT_SET WMI_HEOPS_TWT_SET_D2 /* Deprecated */
+ #define WMI_HEOPS_RTSTHLD_GET WMI_HEOPS_RTSTHLD_GET_D2
+ #define WMI_HEOPS_RTSTHLD_SET WMI_HEOPS_RTSTHLD_SET_D2
+ #define WMI_HEOPS_PARTBSSCOLOR_GET WMI_HEOPS_PARTBSSCOLOR_GET_D2
+ #define WMI_HEOPS_PARTBSSCOLOR_SET WMI_HEOPS_PARTBSSCOLOR_SET_D2
+ #define WMI_HEOPS_MAXBSSID_GET WMI_HEOPS_MAXBSSID_GET_D2
+ #define WMI_HEOPS_MAXBSSID_SET WMI_HEOPS_MAXBSSID_SET_D2
+ #define WMI_HEOPS_TXBSSID_GET WMI_HEOPS_TXBSSID_GET_D2
+ #define WMI_HEOPS_TXBSSID_SET WMI_HEOPS_TXBSSID_SET_D2
+ #define WMI_HEOPS_BSSCOLORDISABLE_GET WMI_HEOPS_BSSCOLORDISABLE_GET_D2
+ #define WMI_HEOPS_BSSCOLORDISABLE_SET WMI_HEOPS_BSSCOLORDISABLE_SET_D2
+ #define WMI_HEOPS_DUALBEACON_GET WMI_HEOPS_DUALBEACON_GET_D2
+ #define WMI_HEOPS_DUALBEACON_SET WMI_HEOPS_DUALBEACON_SET_D2
+ #define WMI_HECAP_PHY_DB_GET WMI_HECAP_PHY_DB_GET_D2
+ #define WMI_HECAP_PHY_DB_SET WMI_HECAP_PHY_DB_SET_D2
+ #define WMI_HECAP_PHY_CBW_GET WMI_HECAP_PHY_CBW_GET_D2
+ #define WMI_HECAP_PHY_CBW_SET WMI_HECAP_PHY_CBW_SET_D2
+ #define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET WMI_HECAP_PHY_PREAMBLEPUNCRX_GET_D2
+ #define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET WMI_HECAP_PHY_PREAMBLEPUNCRX_SET_D2
+ #define WMI_HECAP_PHY_COD_GET WMI_HECAP_PHY_COD_GET_D2
+ #define WMI_HECAP_PHY_COD_SET WMI_HECAP_PHY_COD_SET_D2
+ #define WMI_HECAP_PHY_LDPC_GET WMI_HECAP_PHY_LDPC_GET_D2
+ #define WMI_HECAP_PHY_LDPC_SET WMI_HECAP_PHY_LDPC_SET_D2
+ #define WMI_HECAP_PHY_TXLDPC_GET WMI_HECAP_PHY_TXLDPC_GET_D2
+ #define WMI_HECAP_PHY_TXLDPC_SET WMI_HECAP_PHY_TXLDPC_SET_D2
+ #define WMI_HECAP_PHY_RXLDPC_GET WMI_HECAP_PHY_RXLDPC_GET_D2
+ #define WMI_HECAP_PHY_RXLDPC_SET WMI_HECAP_PHY_RXLDPC_SET_D2
+ #define WMI_HECAP_PHY_LTFGIFORHE_GET WMI_HECAP_PHY_LTFGIFORHE_GET_D2
+ #define WMI_HECAP_PHY_LTFGIFORHE_SET WMI_HECAP_PHY_LTFGIFORHE_SET_D2
+ #define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET_D2
+ #define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET_D2
+ #define WMI_HECAP_PHY_LTFGIFORNDP_GET WMI_HECAP_PHY_LTFGIFORNDP_GET_D2
+ #define WMI_HECAP_PHY_LTFGIFORNDP_SET WMI_HECAP_PHY_LTFGIFORNDP_SET_D2
+ #define WMI_HECAP_PHY_TXSTBC_GET WMI_HECAP_PHY_TXSTBC_GET_D2
+ #define WMI_HECAP_PHY_TXSTBC_SET WMI_HECAP_PHY_TXSTBC_SET_D2
+ #define WMI_HECAP_PHY_RXSTBC_GET WMI_HECAP_PHY_RXSTBC_GET_D2
+ #define WMI_HECAP_PHY_RXSTBC_SET WMI_HECAP_PHY_RXSTBC_SET_D2
+ #define WMI_HECAP_PHY_TXDOPPLER_GET WMI_HECAP_PHY_TXDOPPLER_GET_D2
+ #define WMI_HECAP_PHY_TXDOPPLER_SET WMI_HECAP_PHY_TXDOPPLER_SET_D2
+ #define WMI_HECAP_PHY_RXDOPPLER_GET WMI_HECAP_PHY_RXDOPPLER_GET_D2
+ #define WMI_HECAP_PHY_RXDOPPLER_SET WMI_HECAP_PHY_RXDOPPLER_SET_D2
+ #define WMI_HECAP_PHY_UL_MU_MIMO_GET WMI_HECAP_PHY_UL_MU_MIMO_GET_D2
+ #define WMI_HECAP_PHY_UL_MU_MIMO_SET WMI_HECAP_PHY_UL_MU_MIMO_SET_D2
+ #define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D2
+ #define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D2
+ #define WMI_HECAP_PHY_DCMTX_GET WMI_HECAP_PHY_DCMTX_GET_D2
+ #define WMI_HECAP_PHY_DCMTX_SET WMI_HECAP_PHY_DCMTX_SET_D2
+ #define WMI_HECAP_PHY_DCMRX_GET WMI_HECAP_PHY_DCMRX_GET_D2
+ #define WMI_HECAP_PHY_DCMRX_SET WMI_HECAP_PHY_DCMRX_SET_D2
+ #define WMI_HECAP_PHY_ULHEMU_GET WMI_HECAP_PHY_ULHEMU_GET_D2
+ #define WMI_HECAP_PHY_ULHEMU_SET WMI_HECAP_PHY_ULHEMU_SET_D2
+ #define WMI_HECAP_PHY_SUBFMR_GET WMI_HECAP_PHY_SUBFMR_GET_D2
+ #define WMI_HECAP_PHY_SUBFMR_SET WMI_HECAP_PHY_SUBFMR_SET_D2
+ #define WMI_HECAP_PHY_SUBFME_GET WMI_HECAP_PHY_SUBFME_GET_D2
+ #define WMI_HECAP_PHY_SUBFME_SET WMI_HECAP_PHY_SUBFME_SET_D2
+ #define WMI_HECAP_PHY_MUBFMR_GET WMI_HECAP_PHY_MUBFMR_GET_D2
+ #define WMI_HECAP_PHY_MUBFMR_SET WMI_HECAP_PHY_MUBFMR_SET_D2
+ #define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D2
+ #define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D2
+ #define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D2
+ #define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D2
+ #define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET_D2
+ #define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET_D2
+ #define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET_D2
+ #define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET_D2
+ #define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET_D2
+ #define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET_D2
+ #define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET_D2
+ #define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET_D2
+ #define WMI_HECAP_PHY_CODBK42SU_GET WMI_HECAP_PHY_CODBK42SU_GET_D2
+ #define WMI_HECAP_PHY_CODBK42SU_SET WMI_HECAP_PHY_CODBK42SU_SET_D2
+ #define WMI_HECAP_PHY_CODBK75MU_GET WMI_HECAP_PHY_CODBK75MU_GET_D2
+ #define WMI_HECAP_PHY_CODBK75MU_SET WMI_HECAP_PHY_CODBK75MU_SET_D2
+ #define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET WMI_HECAP_PHY_BFFEEDBACKTRIG_GET_D2
+ #define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET WMI_HECAP_PHY_BFFEEDBACKTRIG_SET_D2
+ #define WMI_HECAP_PHY_HEERSU_GET WMI_HECAP_PHY_HEERSU_GET_D2
+ #define WMI_HECAP_PHY_HEERSU_SET WMI_HECAP_PHY_HEERSU_SET_D2
+ #define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET_D2
+ #define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET_D2
+ #define WMI_HECAP_PHY_PETHRESPRESENT_GET WMI_HECAP_PHY_PETHRESPRESENT_GET_D2
+ #define WMI_HECAP_PHY_PETHRESPRESENT_SET WMI_HECAP_PHY_PETHRESPRESENT_SET_D2
+ #define WMI_HECAP_PHY_SRPSPRESENT_GET WMI_HECAP_PHY_SRPSPRESENT_GET_D2
+ #define WMI_HECAP_PHY_SRPPRESENT_SET WMI_HECAP_PHY_SRPPRESENT_SET_D2
+ #define WMI_HECAP_PHY_PWRBOOSTAR_GET WMI_HECAP_PHY_PWRBOOSTAR_GET_D2
+ #define WMI_HECAP_PHY_PWRBOOSTAR_SET WMI_HECAP_PHY_PWRBOOSTAR_SET_D2
+ #define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET_D2
+ #define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET_D2
+ #define WMI_HECAP_PHY_MAXNC_GET WMI_HECAP_PHY_MAXNC_GET_D2
+ #define WMI_HECAP_PHY_MAXNC_SET WMI_HECAP_PHY_MAXNC_SET_D2
+ #define WMI_HECAP_PHY_STBCTXGT80_GET WMI_HECAP_PHY_STBCTXGT80_GET_D2
+ #define WMI_HECAP_PHY_STBCTXGT80_SET WMI_HECAP_PHY_STBCTXGT80_SET_D2
+ #define WMI_HECAP_PHY_STBCRXGT80_GET WMI_HECAP_PHY_STBCRXGT80_GET_D2
+ #define WMI_HECAP_PHY_STBCRXGT80_SET WMI_HECAP_PHY_STBCRXGT80_SET_D2
+ #define WMI_HECAP_PHY_ERSU4X800NSECGI_GET WMI_HECAP_PHY_ERSU4X800NSECGI_GET_D2
+ #define WMI_HECAP_PHY_ERSU4X800NSECGI_SET WMI_HECAP_PHY_ERSU4X800NSECGI_SET_D2
+ #define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET_D2
+ #define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET_D2
+ #define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET_D2
+ #define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET_D2
+ #define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET_D2
+ #define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET_D2
+ #define WMI_HECAP_PHY_ERSU1X800NSECGI_GET WMI_HECAP_PHY_ERSU1X800NSECGI_GET_D2
+ #define WMI_HECAP_PHY_ERSU1X800NSECGI_SET WMI_HECAP_PHY_ERSU1X800NSECGI_SET_D2
+ #define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET_D2
+ #define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET_D2
+ #define WMI_HECAP_MAC_HECTRL_GET WMI_HECAP_MAC_HECTRL_GET_D2
+ #define WMI_HECAP_MAC_HECTRL_SET WMI_HECAP_MAC_HECTRL_SET_D2
+ #define WMI_HECAP_MAC_TWTREQ_GET WMI_HECAP_MAC_TWTREQ_GET_D2
+ #define WMI_HECAP_MAC_TWTREQ_SET WMI_HECAP_MAC_TWTREQ_SET_D2
+ #define WMI_HECAP_MAC_TWTRSP_GET WMI_HECAP_MAC_TWTRSP_GET_D2
+ #define WMI_HECAP_MAC_TWTRSP_SET WMI_HECAP_MAC_TWTRSP_SET_D2
+ #define WMI_HECAP_MAC_HEFRAG_GET WMI_HECAP_MAC_HEFRAG_GET_D2
+ #define WMI_HECAP_MAC_HEFRAG_SET WMI_HECAP_MAC_HEFRAG_SET_D2
+ #define WMI_HECAP_MAC_MAXFRAGMSDU_GET WMI_HECAP_MAC_MAXFRAGMSDU_GET_D2
+ #define WMI_HECAP_MAC_MAXFRAGMSDU_SET WMI_HECAP_MAC_MAXFRAGMSDU_SET_D2
+ #define WMI_HECAP_MAC_MINFRAGSZ_GET WMI_HECAP_MAC_MINFRAGSZ_GET_D2
+ #define WMI_HECAP_MAC_MINFRAGSZ_SET WMI_HECAP_MAC_MINFRAGSZ_SET_D2
+ #define WMI_HECAP_MAC_TRIGPADDUR_GET WMI_HECAP_MAC_TRIGPADDUR_GET_D2
+ #define WMI_HECAP_MAC_TRIGPADDUR_SET WMI_HECAP_MAC_TRIGPADDUR_SET_D2
+ #define WMI_HECAP_MAC_MTID_GET WMI_HECAP_MAC_MTID_GET_D2
+ #define WMI_HECAP_MAC_MTID_SET WMI_HECAP_MAC_MTID_SET_D2
+ #define WMI_HECAP_MAC_AMSDUINAMPDU_GET WMI_HECAP_MAC_AMSDUINAMPDU_GET_D2
+ #define WMI_HECAP_MAC_AMSDUINAMPDU_SET WMI_HECAP_MAC_AMSDUINAMPDU_SET_D2
+ #define WMI_HECAP_MAC_HELKAD_GET WMI_HECAP_MAC_HELKAD_GET_D2
+ #define WMI_HECAP_MAC_HELKAD_SET WMI_HECAP_MAC_HELKAD_SET_D2
+ #define WMI_HECAP_MAC_AACK_GET WMI_HECAP_MAC_AACK_GET_D2
+ #define WMI_HECAP_MAC_AACK_SET WMI_HECAP_MAC_AACK_SET_D2
+ #define WMI_HECAP_MAC_ULMURSP_GET WMI_HECAP_MAC_ULMURSP_GET_D2
+ #define WMI_HECAP_MAC_ULMURSP_SET WMI_HECAP_MAC_ULMURSP_SET_D2
+ #define WMI_HECAP_MAC_BSR_GET WMI_HECAP_MAC_BSR_GET_D2
+ #define WMI_HECAP_MAC_BSR_SET WMI_HECAP_MAC_BSR_SET_D2
+ #define WMI_HECAP_MAC_BCSTTWT_GET WMI_HECAP_MAC_BCSTTWT_GET_D2
+ #define WMI_HECAP_MAC_BCSTTWT_SET WMI_HECAP_MAC_BCSTTWT_SET_D2
+ #define WMI_HECAP_MAC_32BITBA_GET WMI_HECAP_MAC_32BITBA_GET_D2
+ #define WMI_HECAP_MAC_32BITBA_SET WMI_HECAP_MAC_32BITBA_SET_D2
+ #define WMI_HECAP_MAC_MUCASCADE_GET WMI_HECAP_MAC_MUCASCADE_GET_D2
+ #define WMI_HECAP_MAC_MUCASCADE_SET WMI_HECAP_MAC_MUCASCADE_SET_D2
+ #define WMI_HECAP_MAC_ACKMTIDAMPDU_GET WMI_HECAP_MAC_ACKMTIDAMPDU_GET_D2
+ #define WMI_HECAP_MAC_ACKMTIDAMPDU_SET WMI_HECAP_MAC_ACKMTIDAMPDU_SET_D2
+ #define WMI_HECAP_MAC_GROUPMSTABA_GET WMI_HECAP_MAC_GROUPMSTABA_GET_D2
+ #define WMI_HECAP_MAC_GROUPMSTABA_SET WMI_HECAP_MAC_GROUPMSTABA_SET_D2
+ #define WMI_HECAP_MAC_OMI_GET WMI_HECAP_MAC_OMI_GET_D2
+ #define WMI_HECAP_MAC_OMI_SET WMI_HECAP_MAC_OMI_SET_D2
+ #define WMI_HECAP_MAC_OFDMARA_GET WMI_HECAP_MAC_OFDMARA_GET_D2
+ #define WMI_HECAP_MAC_OFDMARA_SET WMI_HECAP_MAC_OFDMARA_SET_D2
+ #define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET_D2
+ #define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET_D2
+ #define WMI_HECAP_MAC_AMSDUFRAG_GET WMI_HECAP_MAC_AMSDUFRAG_GET_D2
+ #define WMI_HECAP_MAC_AMSDUFRAG_SET WMI_HECAP_MAC_AMSDUFRAG_SET_D2
+ #define WMI_HECAP_MAC_FLEXTWT_GET WMI_HECAP_MAC_FLEXTWT_GET_D2
+ #define WMI_HECAP_MAC_FLEXTWT_SET WMI_HECAP_MAC_FLEXTWT_SET_D2
+ #define WMI_HECAP_MAC_MBSS_GET WMI_HECAP_MAC_MBSS_GET_D2
+ #define WMI_HECAP_MAC_MBSS_SET WMI_HECAP_MAC_MBSS_SET_D2
+ #define WMI_HECAP_MAC_BSRPAMPDU_GET WMI_HECAP_MAC_BSRPAMPDU_GET_D2
+ #define WMI_HECAP_MAC_BSRPAMPDU_SET WMI_HECAP_MAC_BSRPAMPDU_SET_D2
+ #define WMI_HECAP_MAC_QTP_GET WMI_HECAP_MAC_QTP_GET_D2
+ #define WMI_HECAP_MAC_QTP_SET WMI_HECAP_MAC_QTP_SET_D2
+ #define WMI_HECAP_MAC_ABQR_GET WMI_HECAP_MAC_ABQR_GET_D2
+ #define WMI_HECAP_MAC_ABQR_SET WMI_HECAP_MAC_ABQR_SET_D2
+ #define WMI_HECAP_MAC_SRRESP_GET WMI_HECAP_MAC_SRRESP_GET_D2
+ #define WMI_HECAP_MAC_SRRESP_SET WMI_HECAP_MAC_SRRESP_SET_D2
+ #define WMI_HECAP_MAC_OPS_GET WMI_HECAP_MAC_OPS_GET_D2
+ #define WMI_HECAP_MAC_OPS_SET WMI_HECAP_MAC_OPS_SET_D2
+ #define WMI_HECAP_MAC_NDPFDBKRPT_GET WMI_HECAP_MAC_NDPFDBKRPT_GET_D2
+ #define WMI_HECAP_MAC_NDPFDBKRPT_SET WMI_HECAP_MAC_NDPFDBKRPT_SET_D2
+ #define WMI_HECAP_MAC_MBAHECTRL_GET WMI_HECAP_MAC_MBAHECTRL_GET_D2
+ #define WMI_HECAP_MAC_MBAHECTRL_SET WMI_HECAP_MAC_MBAHECTRL_SET_D2
+ #define WMI_HECAP_MAC_MURTS_GET WMI_HECAP_MAC_MURTS_GET_D2
+ #define WMI_HECAP_MAC_MURTS_SET WMI_HECAP_MAC_MURTS_SET_D2
+ #define WMI_HECAP_PHY_CBMODE_GET WMI_HECAP_PHY_CBMODE_GET_D2
+ #define WMI_HECAP_PHY_CBMODE_SET WMI_HECAP_PHY_CBMODE_SET_D2
+ #define WMI_HECAP_PHY_OLTF_GET WMI_HECAP_PHY_OLTF_GET_D2
+ #define WMI_HECAP_PHY_OLTF_SET WMI_HECAP_PHY_OLTF_SET_D2
+ #define WMI_HECAP_PHY_SUBFMESTS_GET WMI_HECAP_PHY_SUBFMESTS_GET_D2
+ #define WMI_HECAP_PHY_SUBFMESTS_SET WMI_HECAP_PHY_SUBFMESTS_SET_D2
+ #define WMI_HECAP_PHY_PADDING_GET WMI_HECAP_PHY_PADDING_GET_D2
+ #define WMI_HECAP_PHY_PADDING_SET WMI_HECAP_PHY_PADDING_SET_D2
+ #define WMI_HECAP_PHY_DLOFMAMUMIMO_GET WMI_HECAP_PHY_DLOFMAMUMIMO_GET_D2
+ #define WMI_HECAP_PHY_DLOFDMAMUMIO_SET WMI_HECAP_PHY_DLOFDMAMUMIO_SET_D2
+ #define WMI_HECAP_PHY_32GI_GET WMI_HECAP_PHY_32GI_GET_D2
+ #define WMI_HECAP_PHY_32GI_SET WMI_HECAP_PHY_32GI_SET_D2
+ #define WMI_HECAP_PHY_NOSUNDIMENS_GET WMI_HECAP_PHY_NOSUNDIMENS_GET_D2
+ #define WMI_HECAP_PHY_NOSUNDIMENS_SET WMI_HECAP_PHY_NOSUNDIMENS_SET_D2
+ #define WMI_HECAP_PHY_40MHZNSS_GET WMI_HECAP_PHY_40MHZNSS_GET_D2
+ #define WMI_HECAP_PHY_40MHZNSS_SET WMI_HECAP_PHY_40MHZNSS_SET_D2
+ #define WMI_HECAP_PHY_ULOFDMA_GET WMI_HECAP_PHY_ULOFDMA_GET_D2
+ #define WMI_HECAP_PHY_ULOFDMA_SET WMI_HECAP_PHY_ULOFDMA_SET_D2
+ #define WMI_HECAP_PHY_DCM_GET WMI_HECAP_PHY_DCM_GET_D2
+ #define WMI_HECAP_PHY_DCM_SET WMI_HECAP_PHY_DCM_SET_D2
+ #define WMI_HECAP_PHY_NSTSLT80MHZ_GET WMI_HECAP_PHY_NSTSLT80MHZ_GET_D2
+ #define WMI_HECAP_PHY_NSTSLT80MHZ_SET WMI_HECAP_PHY_NSTSLT80MHZ_SET_D2
+ #define WMI_HECAP_PHY_NSTSGT80MHZ_GET WMI_HECAP_PHY_NSTSGT80MHZ_GET_D2
+ #define WMI_HECAP_PHY_NSTSGT80MHZ_SET WMI_HECAP_PHY_NSTSGT80MHZ_SET_D2
+ #define WMI_HECAP_MAC_DYNSMPWRSAVE_GET WMI_HECAP_MAC_DYNSMPWRSAVE_GET_D2
+ #define WMI_HECAP_MAC_DYNSMPWRSAVE_SET WMI_HECAP_MAC_DYNSMPWRSAVE_SET_D2
+ #define WMI_HECAP_MAC_PUNCSOUNDING_GET WMI_HECAP_MAC_PUNCSOUNDING_GET_D2
+ #define WMI_HECAP_MAC_PUNCSOUNDING_SET WMI_HECAP_MAC_PUNCSOUNDING_SET_D2
+ #define WMI_HECAP_MAC_HTVHTTRIGRX_GET WMI_HECAP_MAC_HTVHTTRIGRX_GET_D2
+ #define WMI_HECAP_MAC_HTVHTTRIGRX_SET WMI_HECAP_MAC_HTVHTTRIGRX_SET_D2
+#endif /* SUPPORT_11AX_D3 */
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_cfr_capture_event_fixed_param */
+ A_UINT32 tlv_header;
+ /* Method used to capture CFR - of type WMI_PEER_CFR_CAPTURE_METHOD */
+ A_UINT32 capture_method;
+ /* VDEV identifier */
+ A_UINT32 vdev_id;
+ /* Peer MAC address. In AP mode, this is the address of the connected peer
+ * for which CFR capture is needed. In case of STA mode, this is the address
+ * of the AP to which the STA is connected
+ */
+ wmi_mac_addr mac_addr;
+ /* primary 20 MHz channel frequency in mhz */
+ A_UINT32 chan_mhz;
+ /* BW of measurement - of type WMI_PEER_CFR_CAPTURE_BW */
+ A_UINT32 bandwidth;
+ /* phy mode WLAN_PHY_MODE of the channel defined in wlan_defs.h*/
+ A_UINT32 phy_mode;
+ /* Center frequency 1 in MHz*/
+ A_UINT32 band_center_freq1;
+ /* Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/
+ A_UINT32 band_center_freq2;
+ /* Number of spatial streams */
+ A_UINT32 sts_count;
+ /* Bits 31:0: address of data from wmi_dma_buf_release_entry [31:0] */
+ A_UINT32 correlation_info_1;
+ /* Bits 11:0: address of data from wmi_dma_buf_release_entry [43:32]
+ * Bits 15:12: reserved (set to 0x0)
+ * Bits 31:16: hardware PPDU ID [15:0]
+ */
+ A_UINT32 correlation_info_2;
+ /* Bits 1:0: TX status (if any); values defined in enum
+ * WMI_FRAME_TX_STATUS
+ * Bits 30:2: reserved (set to 0x0)
+ * Bit 31: Status of the CFR capture of the peer
+ * 1 (True) - Successful; 0 (False) - Not successful
+ */
+ A_UINT32 status;
+ /* Timestamp in microseconds at which the CFR was captured in the hardware.
+ * The clock used for this timestamp is private to the target and
+ * is not visible to the host i.e., Host can interpret only the
+ * relative timestamp deltas from one message to the next,
+ * but can't interpret the absolute timestamp from a single message.
+ */
+ A_UINT32 timestamp_us;
+ /*
+ * Count of the current CFR capture from FW.
+ * This is helpful to identify any drops in FW.
+ */
+ A_UINT32 counter;
+ /* Per chain RSSI of the peer, for up to WMI_MAX_CHAINS.
+ * Each chain's entry reports the RSSI for different bands in dBm units.
+ * Use WMI_UNIFIED_CHAIN_RSSI_GET to extract the value for a particular
+ * band.
+ * A band value of 0x80 (-128) is invalid.
+ */
+ A_UINT32 chain_rssi[WMI_MAX_CHAINS];
+} wmi_peer_cfr_capture_event_fixed_param;
+
+#define WMI_UNIFIED_CHAIN_PHASE_MASK 0x0000ffff
+#define WMI_UNIFIED_CHAIN_PHASE_GET(tlv, chain_idx) \
+ ((A_UINT16) ((tlv)->chain_phase[chain_idx] & WMI_UNIFIED_CHAIN_PHASE_MASK))
+#define WMI_UNIFIED_CHAIN_PHASE_SET(tlv, chain_idx, value) \
+ (tlv)->chain_phase[chain_idx] = (WMI_UNIFIED_CHAIN_PHASE_MASK & (value))
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_peer_cfr_capture_event_phase_fixed_param */
+ A_UINT32 tlv_header;
+
+ /* Per chain AoA phase data of the Peer, for up to WMI_MAX_CHAINS.
+ * USE WMI_UNIFIED_CHAIN_PHASE_GET to extract the phase value for
+ * a particular chain.
+ * Only lower 2 bytes will contain phase data for a particular chain.
+ * The values in phase data will be from 0 1023 as mapping of
+ * 0-359 degrees using the formula -
+ * phase data = phase in degrees * 1024 / 360
+ *
+ * Target will set 0xFFFF for all invalid chains.
+ *
+ * The WMI_UNIFIED_CHAIN_PHASE_GET/SET macros can be used to access
+ * the valid portion of the 4-byte word containing the chain phase data.
+ */
+ A_UINT32 chain_phase[WMI_MAX_CHAINS];
+} wmi_peer_cfr_capture_event_phase_fixed_param;
+
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK 0x80000000
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_OK_S 31
+
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX 0x00000003
+#define WMI_PEER_CFR_CAPTURE_EVT_STATUS_TX_S 0
+
+/**
+ * wmi_cold_boot_cal_data config flags
+ * BIT 0 : 1 means more data will come, 0 means last event
+ * BIT 1-31 : Reserved
+ */
+#define WMI_COLD_BOOT_CAL_DATA_SET_IS_MORE_DATA(flags, val) WMI_SET_BITS(flags, 0, 1, val)
+#define WMI_COLD_BOOT_CAL_DATA_GET_IS_MORE_DATA(flags) WMI_GET_BITS(flags, 0, 1)
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_cold_boot_cal_data_fixed_param */
+ A_UINT32 data_len; /** length in byte of data[]. */
+ A_UINT32 flags; /** config flags : Only 0th bit is used, bit 1-31 are reserved */
+/* Following this structure is the TLV:
+ * A_UINT8 data[]; <-- length in byte given by field data_len.
+ * This data array contains cold boot data calibration raw data.
+ */
+} wmi_cold_boot_cal_data_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_rap_info_event_fixed_param */
+ /** pdev_id for identifying the MAC, the default value is WMI_PDEV_ID_SOC
+ * See macros starting with WMI_PDEV_ID_ for values.
+ */
+ A_UINT32 pdev_id;
+ A_UINT32 type; /** type of the rogue ap, see WMI_ROGUE_AP_TYPE */
+ wmi_mac_addr bssid; /** bssid of the rogue ap */
+} wmi_pdev_rap_info_event_fixed_param;
+
+/*
+ * WMI API for Firmware to indicate iface combinations which Firmware
+ * support to Host
+ */
+typedef struct {
+ A_UINT32 tlv_header; /* tag = WMITLV_TAG_STRUC_wmi_wlanfw_iface_cmb_ind_event_fixed_param */
+
+ /* common part */
+ /* Consider DBS/DBDC for this new implementation */
+ A_UINT32 pdev_n;
+
+ /* iface combinations part -
+ * Use subsequent TLV arrays to list supported combinations of interfaces.
+ */
+
+/*
+ * The TLVs listing interface combinations, will follow this TLV.
+ * The number of combinations can be calculated by dividing the
+ * TLV array length by the TLV array element length.
+ *
+ * The fixed_param TLV is directly followed by a list of
+ * wlanfw_iface_combination elements:
+ * wlanfw_iface_combination combinations[0];
+ * wlanfw_iface_combination combinations[1];
+ * ...
+ * wlanfw_iface_combination combinations[N];
+ *
+ * After the list of wlanfw_iface_combinations is a list of interface limits.
+ * The cmb_limits field of each wlanfw_iface_combination show which of the
+ * limits within the "wlanfw_ifact_limit limits" list belong to that
+ * iface_combination:
+ * limits[0] <- cmb 0, limit 0
+ * ...
+ * limits[cmb[0].cmb_limits-1] <- cmb 0, limit N
+ * limits[cmb[0].cmb_limits] <- cmb 1, limit 0
+ * ...
+ * limits[cmb[0].cmb_limits+cmb[1].cmb_limits-1] <- cmb 1, limit N
+ * limits[cmb[0].cmb_limits+cmb[1].cmb_limits] <- cmb 2, limit 0
+ * ...
+ */
+} wmi_wlanfw_iface_cmb_ind_event_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* tag = WMITLV_TAG_STRUC_wmi_wlanfw_iface_limit_param */
+ /*
+ * How many vdevs can work as below vdev_type/vdev_subtype
+ * in one combination.
+ */
+ A_UINT32 vdev_limit_n;
+ /*
+ * Indicate what role above vdevs can work as.
+ * Refer to "WMI_VDEV_TYPE_xx, WMI_UNIFIED_VDEV_SUBTYPE_xx"
+ * for roles definition.
+ */
+ A_UINT32 vdev_type;
+ A_UINT32 vdev_subtype;
+} wlanfw_iface_limit;
+
+/**
+ * @brief specific configuration of valid_fields for host.
+ * These flags are used for indicating which fields in wlanfw_iface_combination
+ * contains valid value for Host Driver.
+ * 0: Host can ignore this field
+ * 1: field contains valid value for Host Driver
+ */
+
+#define WMI_CMB_VALID_FIELDS_FLAG_PEER_MAX_S 0
+#define WMI_CMB_VALID_FIELDS_FLAG_PEER_MAX_M 0x1
+
+#define WMI_CMB_VALID_FIELDS_FLAG_STA_AP_BCN_INT_MATCH_S 1
+#define WMI_CMB_VALID_FIELDS_FLAG_STA_AP_BCN_INT_MATCH_M 0x2
+
+#define WMI_CMB_VALID_FIELDS_FLAG_BCN_INT_MIN_S 2
+#define WMI_CMB_VALID_FIELDS_FLAG_BCN_INT_MIN_M 0x4
+
+#define WMI_CMB_VALID_FIELDS_FLAG_BCN_INT_N_S 3
+#define WMI_CMB_VALID_FIELDS_FLAG_BCN_INT_N_M 0x8
+
+#define WMI_CMB_VALID_FIELDS_FLAG_SET(word32, flag, value) \
+ do { \
+ (word32) &= ~WMI_CMB_VALID_FIELDS_FLAG_ ## flag ## _M; \
+ (word32) |= ((value) << WMI_CMB_VALID_FIELDS_FLAG_ ## flag ## _S) & \
+ WMI_CMB_VALID_FIELDS_FLAG_ ## flag ## _M; \
+ } while (0)
+
+#define WMI_CMB_VALID_FIELDS_FLAG_GET(word32, flag) \
+ (((word32) & WMI_CMB_VALID_FIELDS_FLAG_ ## flag ## _M) >> \
+ WMI_CMB_VALID_FIELDS_FLAG_ ## flag ## _S)
+
+#define WMI_CMB_VALID_FIELDS_FLAG_PEER_MAX_SET(word32, value) \
+ WMI_CMB_VALID_FIELDS_FLAG_SET((word32), PEER_MAX, (value))
+#define WMI_CMB_VALID_FIELDS_FLAG_PEER_MAX_GET(word32) \
+ WMI_CMB_VALID_FIELDS_FLAG_GET((word32), PEER_MAX)
+
+#define WMI_CMB_VALID_FIELDS_FLAG_STA_AP_BCN_INT_MATCH_SET(word32, value) \
+ WMI_CMB_VALID_FIELDS_FLAG_SET((word32), STA_AP_BCN_INT_MATCH, (value))
+#define WMI_CMB_VALID_FIELDS_FLAG_STA_AP_BCN_INT_MATCH_GET(word32) \
+ WMI_CMB_VALID_FIELDS_FLAG_GET((word32), STA_AP_BCN_INT_MATCH)
+
+#define WMI_CMB_VALID_FIELDS_FLAG_BCN_INT_MIN_SET(word32, value) \
+ WMI_CMB_VALID_FIELDS_FLAG_SET((word32), BCN_INT_MIN, (value))
+#define WMI_CMB_VALID_FIELDS_FLAG_BCN_INT_MIN_GET(word32) \
+ WMI_CMB_VALID_FIELDS_FLAG_GET((word32), BCN_INT_MIN)
+
+#define WMI_CMB_VALID_FIELDS_FLAG_BCN_INT_N_SET(word32, value) \
+ WMI_CMB_VALID_FIELDS_FLAG_SET((word32), BCN_INT_N, (value))
+#define WMI_CMB_VALID_FIELDS_FLAG_BCN_INT_N_GET(word32) \
+ WMI_CMB_VALID_FIELDS_FLAG_GET((word32), BCN_INT_N)
+
+typedef struct {
+ A_UINT32 tlv_header;
+ /*
+ * Max num Peers can be supported in this combination.
+ * It excludes the self-peers associated with each vdev.
+ * It's the number of real remote peers.
+ * eg: when working as AP mode, indicating how many clients can be
+ * supported to connect with this AP.
+ */
+ A_UINT32 peer_max;
+ /* Home Channels supported on one single phy concurrently */
+ A_UINT32 channel_n;
+ /*
+ * The number of "wlanfw_iface_limit" for a specified combination.
+ * eg: there is 2 vdev, including 1 AP vdev and 1 STA vdev, then this
+ * cmb_limits will be 2 for this combination.
+ */
+ A_UINT32 cmb_limits;
+ /*
+ * Beacon intervals for STA and AP types need to be match or not.
+ * 1: need to be match
+ * 0: not need
+ */
+ A_UINT32 sta_ap_bcn_int_match;
+ /*
+ * This combination supports different beacon intervals or not.
+ * 0: Beacon interval is same for all interface
+ * !0: STA Beacon interval AND GCD of AP Beacon intervals
+ * should be greater or equal to this value.
+ */
+ A_UINT32 bcn_int_min;
+ /*
+ * Number of different Beacon intervals
+ */
+ A_UINT32 bcn_int_n;
+
+ /*
+ * This indicates which field in this struct
+ * contains valid value for Host Driver.
+ * Refer to definitions for "WMI_CMB_VALID_FIELDS_FLAG_xx".
+ */
+ A_UINT32 valid_fields;
+} wlanfw_iface_combination;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_set_elna_bypass_cmd_fixed_param */
+ A_UINT32 tlv_header;
+ /* VDEV identifier */
+ A_UINT32 vdev_id;
+ /** 1-Enable, 0-Disable */
+ A_UINT32 en_dis;
+} wmi_set_elna_bypass_cmd_fixed_param;
+
+typedef struct {
+ /** TLV tag and len; tag equals
+ * WMITLV_TAG_STRUC_wmi_get_elna_bypass_cmd_fixed_param */
+ A_UINT32 tlv_header;
+ /* VDEV identifier */
+ A_UINT32 vdev_id;
+} wmi_get_elna_bypass_cmd_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_get_elna_bypass_event_fixed_param */
+ /* VDEV identifier */
+ A_UINT32 vdev_id;
+ /** 1-Enable, 0-Disable */
+ A_UINT32 en_dis;
+} wmi_get_elna_bypass_event_fixed_param;
+
+
/* ADD NEW DEFS HERE */
diff --git a/drivers/staging/fw-api/fw/wmi_version.h b/drivers/staging/fw-api/fw/wmi_version.h
index 75c7c55..f17c1a0 100644
--- a/drivers/staging/fw-api/fw/wmi_version.h
+++ b/drivers/staging/fw-api/fw/wmi_version.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -36,7 +36,7 @@
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
-#define __WMI_REVISION_ 517
+#define __WMI_REVISION_ 702
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work
diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_param.h b/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_param.h
index cf6c7c0..97624c7 100644
--- a/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_param.h
+++ b/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_param.h
@@ -294,6 +294,28 @@
WMI_HOST_MODE_MAX = 16
} WMI_HOST_WLAN_PHY_MODE;
+/**
+ * enum wmi_host_channel_width: Channel operating width. Maps to
+ * wmi_channel_width used in firmware header file(s).
+ * @WMI_HOST_CHAN_WIDTH_20: 20 MHz channel operating width
+ * @WMI_HOST_CHAN_WIDTH_40: 40 MHz channel operating width
+ * @WMI_HOST_CHAN_WIDTH_80: 80 MHz channel operating width
+ * @WMI_HOST_CHAN_WIDTH_160: 160 MHz channel operating width
+ * @WMI_HOST_CHAN_WIDTH_80P80: 80+80 MHz channel operating width
+ * @WMI_HOST_CHAN_WIDTH_5: 5 MHz channel operating width
+ * @WMI_HOST_CHAN_WIDTH_10: 10 MHz channel operating width
+ * @WMI_HOST_CHAN_WIDTH_165: 165 MHz channel operating width
+ */
+typedef enum {
+ WMI_HOST_CHAN_WIDTH_20 = 0,
+ WMI_HOST_CHAN_WIDTH_40 = 1,
+ WMI_HOST_CHAN_WIDTH_80 = 2,
+ WMI_HOST_CHAN_WIDTH_160 = 3,
+ WMI_HOST_CHAN_WIDTH_80P80 = 4,
+ WMI_HOST_CHAN_WIDTH_5 = 5,
+ WMI_HOST_CHAN_WIDTH_10 = 6,
+ WMI_HOST_CHAN_WIDTH_165 = 7,
+} wmi_host_channel_width;
/**
* enum wmi_dwelltime_adaptive_mode: dwelltime_mode
@@ -1131,6 +1153,7 @@
/**
* struct scan_chan_list_params - scan channel list cmd parameter
* @num_scan_chans: no of scan channels
+ * @max_bw_support_present: max BW support present
* @chan_info: pointer to wmi channel info
*/
#ifdef CONFIG_MCL
@@ -1154,6 +1177,7 @@
struct scan_chan_list_params {
uint8_t num_scan_chans;
+ bool max_bw_support_present;
wmi_channel_param *chan_info;
};
#else
diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c
index 06c8180..7a392b6 100644
--- a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c
+++ b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c
@@ -1785,6 +1785,9 @@
WMI_LOGD("no of channels = %d, len = %d", chan_list->num_scan_chans, len);
cmd->num_scan_chans = chan_list->num_scan_chans;
+ if (chan_list->max_bw_support_present)
+ cmd->flags |= CHANNEL_MAX_BANDWIDTH_VALID;
+
WMITLV_SET_HDR((buf_ptr + sizeof(wmi_scan_chan_list_cmd_fixed_param)),
WMITLV_TAG_ARRAY_STRUC,
sizeof(wmi_channel) * chan_list->num_scan_chans);
diff --git a/drivers/staging/qcacld-3.0/core/cds/src/cds_api.c b/drivers/staging/qcacld-3.0/core/cds/src/cds_api.c
index cf44c89..bce02ec 100644
--- a/drivers/staging/qcacld-3.0/core/cds/src/cds_api.c
+++ b/drivers/staging/qcacld-3.0/core/cds/src/cds_api.c
@@ -2712,8 +2712,8 @@
inline void cds_pkt_stats_to_logger_thread(void *pl_hdr, void *pkt_dump,
void *data)
{
- if (cds_get_ring_log_level(RING_ID_PER_PACKET_STATS) !=
- WLAN_LOG_LEVEL_ACTIVE)
+ if (cds_get_ring_log_level(RING_ID_PER_PACKET_STATS) <
+ WLAN_LOG_LEVEL_REPRO)
return;
wlan_pkt_stats_to_logger_thread(pl_hdr, pkt_dump, data);
diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_assoc.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_assoc.c
index 82dfc3f..7f945ae 100644
--- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_assoc.c
+++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_assoc.c
@@ -6016,6 +6016,10 @@
RSNAuthType;
hdd_debug("updated profile authtype as %d",
RSNAuthType);
+ } else if (RSNAuthType == eCSR_AUTH_TYPE_SAE) {
+ /* SAE with open authentication case */
+ pRoamProfile->AuthType.authType[0] =
+ eCSR_AUTH_TYPE_SAE;
} else if ((RSNAuthType ==
eCSR_AUTH_TYPE_SUITEB_EAP_SHA256) &&
((pWextState->
diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_main.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_main.c
index fcd15a9..836ebc7 100644
--- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_main.c
+++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_main.c
@@ -9319,7 +9319,7 @@
start_log.ring_id = RING_ID_PER_PACKET_STATS;
start_log.verbose_level =
- enable ? WLAN_LOG_LEVEL_ACTIVE : WLAN_LOG_LEVEL_OFF;
+ enable ? WLAN_LOG_LEVEL_REPRO : WLAN_LOG_LEVEL_OFF;
start_log.ini_triggered = cds_is_packet_log_enabled();
start_log.user_triggered = user_triggered;
start_log.size = size;
diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c
index 6a2f7d4..1b61118 100644
--- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c
+++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c
@@ -3065,6 +3065,8 @@
c_auth_suites, authentication)) {
if (eCSR_AUTH_TYPE_SAE == auth_type->authType[index])
*neg_authtype = eCSR_AUTH_TYPE_SAE;
+ if (eCSR_AUTH_TYPE_OPEN_SYSTEM == auth_type->authType[index])
+ *neg_authtype = eCSR_AUTH_TYPE_OPEN_SYSTEM;
}
sme_debug("negotiated auth type is %d", *neg_authtype);
}
diff --git a/drivers/staging/qcacld-3.0/core/utils/logging/src/wlan_logging_sock_svc.c b/drivers/staging/qcacld-3.0/core/utils/logging/src/wlan_logging_sock_svc.c
index cf366b1a..d4c3274 100644
--- a/drivers/staging/qcacld-3.0/core/utils/logging/src/wlan_logging_sock_svc.c
+++ b/drivers/staging/qcacld-3.0/core/utils/logging/src/wlan_logging_sock_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2017 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -1161,7 +1161,7 @@
spin_lock_irqsave(&gwlan_logging.pkt_stats_lock, flags);
- if (!gwlan_logging.pkt_stats_pcur_node || (NULL == pkt_stats_dump)) {
+ if (!gwlan_logging.pkt_stats_pcur_node) {
spin_unlock_irqrestore(&gwlan_logging.pkt_stats_lock, flags);
return;
}
@@ -1194,7 +1194,7 @@
pktlog_hdr->size),
data, pktlog_hdr->size);
- if (pkt_stats_dump->type == STOP_MONITOR) {
+ if (pkt_stats_dump && pkt_stats_dump->type == STOP_MONITOR) {
wake_up_thread = true;
wlan_get_pkt_stats_free_node();
}
diff --git a/drivers/staging/qcacld-3.0/core/utils/pktlog/pktlog_internal.c b/drivers/staging/qcacld-3.0/core/utils/pktlog/pktlog_internal.c
index 94ef1a0..97d363b 100644
--- a/drivers/staging/qcacld-3.0/core/utils/pktlog/pktlog_internal.c
+++ b/drivers/staging/qcacld-3.0/core/utils/pktlog/pktlog_internal.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -927,6 +927,7 @@
qdf_mem_copy(sw_event.sw_event,
((char *)fw_data->data + sizeof(struct ath_pktlog_hdr)),
pl_hdr.size);
+ cds_pkt_stats_to_logger_thread(&pl_hdr, NULL, sw_event.sw_event);
return A_OK;
}
diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c
index f60892f..c2437202 100644
--- a/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c
+++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c
@@ -6548,7 +6548,7 @@
return;
}
- if (start_log->verbose_level == WLAN_LOG_LEVEL_ACTIVE) {
+ if (start_log->verbose_level >= WLAN_LOG_LEVEL_REPRO) {
pktlog_enable(scn, log_state, start_log->ini_triggered,
start_log->user_triggered,
start_log->is_iwpriv_command);
diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c
index 0883537..f18c7cda 100644
--- a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c
+++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c
@@ -692,6 +692,27 @@
return qdf_status;
}
+static inline wmi_host_channel_width
+wma_map_phy_ch_bw_to_wmi_channel_width(enum phy_ch_width ch_width)
+{
+ switch (ch_width) {
+ case CH_WIDTH_20MHZ:
+ return WMI_HOST_CHAN_WIDTH_20;
+ case CH_WIDTH_40MHZ:
+ return WMI_HOST_CHAN_WIDTH_40;
+ case CH_WIDTH_80MHZ:
+ return WMI_HOST_CHAN_WIDTH_80;
+ case CH_WIDTH_160MHZ:
+ return WMI_HOST_CHAN_WIDTH_160;
+ case CH_WIDTH_5MHZ:
+ return WMI_HOST_CHAN_WIDTH_5;
+ case CH_WIDTH_10MHZ:
+ return WMI_HOST_CHAN_WIDTH_10;
+ default:
+ return WMI_HOST_CHAN_WIDTH_20;
+ }
+}
+
/**
* wma_update_channel_list() - update channel list
* @handle: wma handle
@@ -709,6 +730,7 @@
int i;
struct scan_chan_list_params scan_ch_param = {0};
wmi_channel_param *tchan_info;
+ struct ch_params_s ch_params = {0};
scan_ch_param.chan_info = qdf_mem_malloc(sizeof(wmi_channel) *
chan_list->numChan);
@@ -721,6 +743,7 @@
WMA_LOGD("no of channels = %d", chan_list->numChan);
tchan_info = scan_ch_param.chan_info;
scan_ch_param.num_scan_chans = chan_list->numChan;
+ scan_ch_param.max_bw_support_present = true;
wma_handle->saved_chan.num_channels = chan_list->numChan;
WMA_LOGD("ht %d, vht %d, vht_24 %d", chan_list->ht_en,
chan_list->vht_en, chan_list->vht_24_en);
@@ -775,6 +798,14 @@
WMI_SET_CHANNEL_REG_POWER(tchan_info,
chan_list->chanParam[i].pwr);
+ ch_params.ch_width = CH_WIDTH_160MHZ;
+ cds_set_channel_params(chan_list->chanParam[i].chanId, 0,
+ &ch_params);
+
+ WMI_SET_CHANNEL_MAX_BANDWIDTH(tchan_info,
+ wma_map_phy_ch_bw_to_wmi_channel_width(
+ ch_params.ch_width));
+
tchan_info++;
}
diff --git a/drivers/thermal/msm_lmh_dcvs.c b/drivers/thermal/msm_lmh_dcvs.c
index 33a031d..6ade8b40 100644
--- a/drivers/thermal/msm_lmh_dcvs.c
+++ b/drivers/thermal/msm_lmh_dcvs.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016-2017, 2019 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -206,7 +206,7 @@
uint32_t payload_len;
payload_len = ((enable_val1) ? 6 : 5) * sizeof(uint32_t);
- payload = kcalloc((enable_val1) ? 6 : 5, sizeof(uint32_t), GFP_KERNEL);
+ payload = kzalloc(payload_len, GFP_KERNEL);
if (!payload)
return -ENOMEM;
@@ -230,7 +230,6 @@
ret = scm_call2(SCM_SIP_FNID(SCM_SVC_LMH, MSM_LIMITS_DCVSH), &desc_arg);
kfree(payload);
-
return ret;
}
@@ -359,6 +358,7 @@
return msm_lmh_dcvs_write(hw->affinity, MSM_LIMITS_SUB_FN_THERMAL,
MSM_LIMIT_FREQ_CAP, freq,
freq >= hw->max_freq ? 0 : 1, 1);
+
}
static int lmh_get_cur_limit(int cpu, unsigned long *freq)
@@ -442,7 +442,7 @@
/* Enable the thermal algorithm early */
ret = msm_lmh_dcvs_write(hw->affinity, MSM_LIMITS_SUB_FN_THERMAL,
- MSM_LIMITS_ALGO_MODE_ENABLE, 1, 0, 0);
+ MSM_LIMITS_ALGO_MODE_ENABLE, 1, 0, 0);
if (ret)
return ret;
diff --git a/drivers/thermal/msm_thermal.c b/drivers/thermal/msm_thermal.c
index c27e0f4..075e6eb 100644
--- a/drivers/thermal/msm_thermal.c
+++ b/drivers/thermal/msm_thermal.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1027,7 +1027,7 @@
uint32_t payload_len;
payload_len = ((enable_val1) ? 6 : 5) * sizeof(uint32_t);
- payload = kcalloc((enable_val1) ? 6 : 5, sizeof(uint32_t), GFP_KERNEL);
+ payload = kzalloc(payload_len, GFP_KERNEL);
if (!payload)
return -ENOMEM;
@@ -1051,7 +1051,6 @@
ret = scm_call2(SCM_SIP_FNID(SCM_SVC_LMH, MSM_LIMITS_DCVSH), &desc_arg);
kfree(payload);
-
return ret;
}
@@ -1066,7 +1065,7 @@
* It is better to use max limits of cluster for given
* cpu if cluster mitigation is supported. It ensures that it
* requests aggregated max limits of all cpus in that cluster.
- */
+ * */
if (core_ptr)
max_freq = cpus[cpu].parent_ptr->limited_max_freq;
@@ -1088,8 +1087,9 @@
cpus[cpu].parent_ptr->freq_idx_high].frequency;
ret = msm_lmh_dcvs_write(affinity, MSM_LIMITS_SUB_FN_THERMAL,
- MSM_LIMITS_FREQ_CAP, max_freq,
- max_freq >= hw_max_freq ? 0 : 1, 1);
+ MSM_LIMITS_FREQ_CAP, max_freq,
+ max_freq >= hw_max_freq ? 0 : 1, 1);
+
if (ret)
return ret;
/*
diff --git a/drivers/video/fbdev/msm/mdss_smmu.c b/drivers/video/fbdev/msm/mdss_smmu.c
index 62e2550..80eb297 100644
--- a/drivers/video/fbdev/msm/mdss_smmu.c
+++ b/drivers/video/fbdev/msm/mdss_smmu.c
@@ -573,7 +573,7 @@
}
*dma_addr = dma_map_single(mdss_smmu->base.dev, cpu_addr, size, dir);
- if (IS_ERR_VALUE(*dma_addr)) {
+ if (dma_mapping_error(mdss_smmu->base.dev, *dma_addr)) {
pr_err("dma map single failed\n");
return -ENOMEM;
}
diff --git a/include/linux/compiler-clang.h b/include/linux/compiler-clang.h
index e75255b..f459110 100644
--- a/include/linux/compiler-clang.h
+++ b/include/linux/compiler-clang.h
@@ -24,3 +24,13 @@
*/
#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
+#undef __no_sanitize_address
+#define __no_sanitize_address __attribute__((no_sanitize("address")))
+
+/* all clang versions usable with the kernel support KASAN ABI version 5 */
+#define KASAN_ABI_VERSION 5
+
+/* emulate gcc's __SANITIZE_ADDRESS__ flag */
+#if __has_feature(address_sanitizer)
+#define __SANITIZE_ADDRESS__
+#endif
diff --git a/include/linux/hid.h b/include/linux/hid.h
index 5f31318..8571c02 100644
--- a/include/linux/hid.h
+++ b/include/linux/hid.h
@@ -521,10 +521,12 @@
* battery is non-NULL.
*/
struct power_supply *battery;
+ __s32 battery_capacity;
__s32 battery_min;
__s32 battery_max;
__s32 battery_report_type;
__s32 battery_report_id;
+ bool battery_reported;
#endif
unsigned int status; /* see STAT flags above */
diff --git a/include/linux/input.h b/include/linux/input.h
index 1e96769..808a097 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -36,6 +36,13 @@
__s32 value;
};
+enum input_clock_type {
+ INPUT_CLK_REAL = 0,
+ INPUT_CLK_MONO,
+ INPUT_CLK_BOOT,
+ INPUT_CLK_MAX
+};
+
/**
* struct input_dev - represents an input device
* @name: name of the device
@@ -117,6 +124,8 @@
* @vals: array of values queued in the current frame
* @devres_managed: indicates that devices is managed with devres framework
* and needs not be explicitly unregistered or freed.
+ * @timestamp: storage for a timestamp set by input_set_timestamp called
+ * by a driver
*/
struct input_dev {
const char *name;
@@ -187,6 +196,8 @@
struct input_value *vals;
bool devres_managed;
+
+ ktime_t timestamp[INPUT_CLK_MAX];
};
#define to_input_dev(d) container_of(d, struct input_dev, dev)
@@ -381,6 +392,9 @@
int input_flush_device(struct input_handle *handle, struct file *file);
+void input_set_timestamp(struct input_dev *dev, ktime_t timestamp);
+ktime_t *input_get_timestamp(struct input_dev *dev);
+
void input_event(struct input_dev *dev, unsigned int type, unsigned int code, int value);
void input_inject_event(struct input_handle *handle, unsigned int type, unsigned int code, int value);
diff --git a/include/linux/phy/phy-qcom-ufs.h b/include/linux/phy/phy-qcom-ufs.h
index 25e7a5f..3564b57 100644
--- a/include/linux/phy/phy-qcom-ufs.h
+++ b/include/linux/phy/phy-qcom-ufs.h
@@ -59,5 +59,6 @@
const char *ufs_qcom_phy_name(struct phy *phy);
int ufs_qcom_phy_configure_lpm(struct phy *generic_phy, bool enable);
void ufs_qcom_phy_dbg_register_dump(struct phy *generic_phy);
+void ufs_qcom_phy_print_phy_state(struct phy *generic_phy);
#endif /* PHY_QCOM_UFS_H_ */
diff --git a/lib/test_kasan.c b/lib/test_kasan.c
index 0e70ecc..8fcad61 100644
--- a/lib/test_kasan.c
+++ b/lib/test_kasan.c
@@ -440,6 +440,26 @@
p[1023] = 1;
}
+static noinline void __init kasan_alloca_oob_left(void)
+{
+ volatile int i = 10;
+ char alloca_array[i];
+ char *p = alloca_array - 1;
+
+ pr_info("out-of-bounds to left on alloca\n");
+ *(volatile char *)p;
+}
+
+static noinline void __init kasan_alloca_oob_right(void)
+{
+ volatile int i = 10;
+ char alloca_array[i];
+ char *p = alloca_array + i;
+
+ pr_info("out-of-bounds to right on alloca\n");
+ *(volatile char *)p;
+}
+
static int __init kmalloc_tests_init(void)
{
/*
@@ -469,6 +489,8 @@
kmem_cache_oob();
kasan_stack_oob();
kasan_global_oob();
+ kasan_alloca_oob_left();
+ kasan_alloca_oob_right();
ksize_unpoisons_memory();
copy_user_test();
use_after_scope_test();
diff --git a/mm/kasan/kasan.c b/mm/kasan/kasan.c
index 2bfdb3c..3c57210 100644
--- a/mm/kasan/kasan.c
+++ b/mm/kasan/kasan.c
@@ -802,6 +802,55 @@
}
EXPORT_SYMBOL(__asan_unpoison_stack_memory);
+/* Emitted by compiler to poison alloca()ed objects. */
+void __asan_alloca_poison(unsigned long addr, size_t size)
+{
+ size_t rounded_up_size = round_up(size, KASAN_SHADOW_SCALE_SIZE);
+ size_t padding_size = round_up(size, KASAN_ALLOCA_REDZONE_SIZE) -
+ rounded_up_size;
+ size_t rounded_down_size = round_down(size, KASAN_SHADOW_SCALE_SIZE);
+
+ const void *left_redzone = (const void *)(addr -
+ KASAN_ALLOCA_REDZONE_SIZE);
+ const void *right_redzone = (const void *)(addr + rounded_up_size);
+
+ WARN_ON(!IS_ALIGNED(addr, KASAN_ALLOCA_REDZONE_SIZE));
+
+ kasan_unpoison_shadow((const void *)(addr + rounded_down_size),
+ size - rounded_down_size);
+ kasan_poison_shadow(left_redzone, KASAN_ALLOCA_REDZONE_SIZE,
+ KASAN_ALLOCA_LEFT);
+ kasan_poison_shadow(right_redzone,
+ padding_size + KASAN_ALLOCA_REDZONE_SIZE,
+ KASAN_ALLOCA_RIGHT);
+}
+EXPORT_SYMBOL(__asan_alloca_poison);
+
+/* Emitted by compiler to unpoison alloca()ed areas when the stack unwinds. */
+void __asan_allocas_unpoison(const void *stack_top, const void *stack_bottom)
+{
+ if (unlikely(!stack_top || stack_top > stack_bottom))
+ return;
+
+ kasan_unpoison_shadow(stack_top, stack_bottom - stack_top);
+}
+EXPORT_SYMBOL(__asan_allocas_unpoison);
+
+/* Emitted by the compiler to [un]poison local variables. */
+#define DEFINE_ASAN_SET_SHADOW(byte) \
+ void __asan_set_shadow_##byte(const void *addr, size_t size) \
+ { \
+ __memset((void *)addr, 0x##byte, size); \
+ } \
+ EXPORT_SYMBOL(__asan_set_shadow_##byte)
+
+DEFINE_ASAN_SET_SHADOW(00);
+DEFINE_ASAN_SET_SHADOW(f1);
+DEFINE_ASAN_SET_SHADOW(f2);
+DEFINE_ASAN_SET_SHADOW(f3);
+DEFINE_ASAN_SET_SHADOW(f5);
+DEFINE_ASAN_SET_SHADOW(f8);
+
#ifdef CONFIG_MEMORY_HOTPLUG
static int kasan_mem_notifier(struct notifier_block *nb,
unsigned long action, void *data)
diff --git a/mm/kasan/kasan.h b/mm/kasan/kasan.h
index 1229298..d9cf9e2 100644
--- a/mm/kasan/kasan.h
+++ b/mm/kasan/kasan.h
@@ -23,6 +23,14 @@
#define KASAN_STACK_PARTIAL 0xF4
#define KASAN_USE_AFTER_SCOPE 0xF8
+/*
+ * alloca redzone shadow values
+ */
+#define KASAN_ALLOCA_LEFT 0xCA
+#define KASAN_ALLOCA_RIGHT 0xCB
+
+#define KASAN_ALLOCA_REDZONE_SIZE 32
+
/* Don't break randconfig/all*config builds */
#ifndef KASAN_ABI_VERSION
#define KASAN_ABI_VERSION 1
@@ -112,4 +120,48 @@
static inline void quarantine_remove_cache(struct kmem_cache *cache) { }
#endif
+/*
+ * Exported functions for interfaces called from assembly or from generated
+ * code. Declarations here to avoid warning about missing declarations.
+ */
+asmlinkage void kasan_unpoison_task_stack_below(const void *watermark);
+void __asan_register_globals(struct kasan_global *globals, size_t size);
+void __asan_unregister_globals(struct kasan_global *globals, size_t size);
+void __asan_loadN(unsigned long addr, size_t size);
+void __asan_storeN(unsigned long addr, size_t size);
+void __asan_handle_no_return(void);
+void __asan_poison_stack_memory(const void *addr, size_t size);
+void __asan_unpoison_stack_memory(const void *addr, size_t size);
+void __asan_alloca_poison(unsigned long addr, size_t size);
+void __asan_allocas_unpoison(const void *stack_top, const void *stack_bottom);
+
+void __asan_load1(unsigned long addr);
+void __asan_store1(unsigned long addr);
+void __asan_load2(unsigned long addr);
+void __asan_store2(unsigned long addr);
+void __asan_load4(unsigned long addr);
+void __asan_store4(unsigned long addr);
+void __asan_load8(unsigned long addr);
+void __asan_store8(unsigned long addr);
+void __asan_load16(unsigned long addr);
+void __asan_store16(unsigned long addr);
+
+void __asan_load1_noabort(unsigned long addr);
+void __asan_store1_noabort(unsigned long addr);
+void __asan_load2_noabort(unsigned long addr);
+void __asan_store2_noabort(unsigned long addr);
+void __asan_load4_noabort(unsigned long addr);
+void __asan_store4_noabort(unsigned long addr);
+void __asan_load8_noabort(unsigned long addr);
+void __asan_store8_noabort(unsigned long addr);
+void __asan_load16_noabort(unsigned long addr);
+void __asan_store16_noabort(unsigned long addr);
+
+void __asan_set_shadow_00(const void *addr, size_t size);
+void __asan_set_shadow_f1(const void *addr, size_t size);
+void __asan_set_shadow_f2(const void *addr, size_t size);
+void __asan_set_shadow_f3(const void *addr, size_t size);
+void __asan_set_shadow_f5(const void *addr, size_t size);
+void __asan_set_shadow_f8(const void *addr, size_t size);
+
#endif
diff --git a/mm/kasan/report.c b/mm/kasan/report.c
index 775e214..d51bc21 100644
--- a/mm/kasan/report.c
+++ b/mm/kasan/report.c
@@ -102,6 +102,10 @@
case KASAN_USE_AFTER_SCOPE:
bug_type = "use-after-scope";
break;
+ case KASAN_ALLOCA_LEFT:
+ case KASAN_ALLOCA_RIGHT:
+ bug_type = "alloca-out-of-bounds";
+ break;
}
return bug_type;
@@ -134,7 +138,7 @@
pr_err("BUG: KASAN: %s in %pS\n",
bug_type, (void *)info->ip);
- pr_err("%s of size %zu at addr %p by task %s/%d\n",
+ pr_err("%s of size %zu at addr %px by task %s/%d\n",
info->is_write ? "Write" : "Read", info->access_size,
info->access_addr, current->comm, task_pid_nr(current));
}
@@ -205,7 +209,7 @@
const char *rel_type;
int rel_bytes;
- pr_err("The buggy address belongs to the object at %p\n"
+ pr_err("The buggy address belongs to the object at %px\n"
" which belongs to the cache %s of size %d\n",
object, cache->name, cache->object_size);
@@ -224,7 +228,7 @@
}
pr_err("The buggy address is located %d bytes %s of\n"
- " %d-byte region [%p, %p)\n",
+ " %d-byte region [%px, %px)\n",
rel_bytes, rel_type, cache->object_size, (void *)object_addr,
(void *)(object_addr + cache->object_size));
}
@@ -301,7 +305,7 @@
char shadow_buf[SHADOW_BYTES_PER_ROW];
snprintf(buffer, sizeof(buffer),
- (i == 0) ? ">%p: " : " %p: ", kaddr);
+ (i == 0) ? ">%px: " : " %px: ", kaddr);
/*
* We should not pass a shadow pointer to generic
* function, because generic functions may try to
diff --git a/scripts/Makefile.kasan b/scripts/Makefile.kasan
index 5d54925..d809e00 100644
--- a/scripts/Makefile.kasan
+++ b/scripts/Makefile.kasan
@@ -9,18 +9,7 @@
CFLAGS_KASAN_MINIMAL := -fsanitize=kernel-address
-ifeq ($(cc-name),clang)
-CFLAGS_KASAN := $(call cc-option, -fsanitize=kernel-address \
- -mllvm \
- -asan-mapping-offset=$(KASAN_SHADOW_OFFSET) \
- -asan-stack=1 -asan-globals=1 \
- -asan-instrumentation-with-call-threshold=$(call_threshold))
-else
-CFLAGS_KASAN := $(call cc-option, -fsanitize=kernel-address \
- -fasan-shadow-offset=$(KASAN_SHADOW_OFFSET) \
- --param asan-stack=1 --param asan-globals=1 \
- --param asan-instrumentation-with-call-threshold=$(call_threshold))
-endif
+cc-param = $(call cc-option, -mllvm -$(1), $(call cc-option, --param $(1)))
ifeq ($(call cc-option, $(CFLAGS_KASAN_MINIMAL) -Werror),)
ifneq ($(CONFIG_COMPILE_TEST),y)
@@ -28,13 +17,24 @@
-fsanitize=kernel-address is not supported by compiler)
endif
else
- ifeq ($(CFLAGS_KASAN),)
- ifneq ($(CONFIG_COMPILE_TEST),y)
- $(warning CONFIG_KASAN: compiler does not support all options.\
- Trying minimal configuration)
- endif
- CFLAGS_KASAN := $(CFLAGS_KASAN_MINIMAL)
- endif
+ # -fasan-shadow-offset fails without -fsanitize
+ CFLAGS_KASAN_SHADOW := $(call cc-option, -fsanitize=kernel-address \
+ -fasan-shadow-offset=$(KASAN_SHADOW_OFFSET), \
+ $(call cc-option, -fsanitize=kernel-address \
+ -mllvm -asan-mapping-offset=$(KASAN_SHADOW_OFFSET)))
+
+ ifeq ($(strip $(CFLAGS_KASAN_SHADOW)),)
+ CFLAGS_KASAN := $(CFLAGS_KASAN_MINIMAL)
+ else
+ # Now add all the compiler specific options that are valid standalone
+ CFLAGS_KASAN := $(CFLAGS_KASAN_SHADOW) \
+ $(call cc-param,asan-globals=1) \
+ $(call cc-param,asan-instrumentation-with-call-threshold=$(call_threshold)) \
+ $(call cc-param,asan-stack=1) \
+ $(call cc-param,asan-use-after-scope=1) \
+ $(call cc-param,asan-instrument-allocas=1)
+ endif
+
endif
CFLAGS_KASAN_NOSANITIZE := -fno-builtin
diff --git a/security/selinux/include/classmap.h b/security/selinux/include/classmap.h
index b393d29..31dc821 100644
--- a/security/selinux/include/classmap.h
+++ b/security/selinux/include/classmap.h
@@ -100,7 +100,7 @@
{ COMMON_IPC_PERMS, NULL } },
{ "netlink_route_socket",
{ COMMON_SOCK_PERMS,
- "nlmsg_read", "nlmsg_write", NULL } },
+ "nlmsg_read", "nlmsg_write", "nlmsg_readpriv", NULL } },
{ "netlink_tcpdiag_socket",
{ COMMON_SOCK_PERMS,
"nlmsg_read", "nlmsg_write", NULL } },
diff --git a/security/selinux/include/security.h b/security/selinux/include/security.h
index 0464cbb..b45a3a7 100644
--- a/security/selinux/include/security.h
+++ b/security/selinux/include/security.h
@@ -78,6 +78,7 @@
};
#define POLICYDB_CAPABILITY_MAX (__POLICYDB_CAPABILITY_MAX - 1)
+extern int selinux_android_netlink_route;
extern int selinux_policycap_netpeer;
extern int selinux_policycap_openperm;
extern int selinux_policycap_alwaysnetwork;
@@ -263,6 +264,7 @@
extern void selnl_notify_setenforce(int val);
extern void selnl_notify_policyload(u32 seqno);
extern int selinux_nlmsg_lookup(u16 sclass, u16 nlmsg_type, u32 *perm);
+extern void selinux_nlmsg_init(void);
#endif /* _SELINUX_SECURITY_H_ */
diff --git a/security/selinux/nlmsgtab.c b/security/selinux/nlmsgtab.c
index 7f947f7..e7b7462 100644
--- a/security/selinux/nlmsgtab.c
+++ b/security/selinux/nlmsgtab.c
@@ -191,3 +191,27 @@
return err;
}
+
+static void nlmsg_set_getlink_perm(u32 perm)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(nlmsg_route_perms); i++) {
+ if (nlmsg_route_perms[i].nlmsg_type == RTM_GETLINK) {
+ nlmsg_route_perms[i].perm = perm;
+ break;
+ }
+ }
+}
+
+/**
+ * Use nlmsg_readpriv as the permission for RTM_GETLINK messages if the
+ * netlink_route_getlink policy capability is set. Otherwise use nlmsg_read.
+ */
+void selinux_nlmsg_init(void)
+{
+ if (selinux_android_netlink_route)
+ nlmsg_set_getlink_perm(NETLINK_ROUTE_SOCKET__NLMSG_READPRIV);
+ else
+ nlmsg_set_getlink_perm(NETLINK_ROUTE_SOCKET__NLMSG_READ);
+}
diff --git a/security/selinux/ss/policydb.c b/security/selinux/ss/policydb.c
index 01fbbbf..5ee23e3 100644
--- a/security/selinux/ss/policydb.c
+++ b/security/selinux/ss/policydb.c
@@ -2329,6 +2329,10 @@
p->reject_unknown = !!(le32_to_cpu(buf[1]) & REJECT_UNKNOWN);
p->allow_unknown = !!(le32_to_cpu(buf[1]) & ALLOW_UNKNOWN);
+ if ((le32_to_cpu(buf[1]) & POLICYDB_CONFIG_ANDROID_NETLINK_ROUTE)) {
+ p->android_netlink_route = 1;
+ }
+
if (p->policyvers >= POLICYDB_VERSION_POLCAP) {
rc = ebitmap_read(&p->policycaps, fp);
if (rc)
diff --git a/security/selinux/ss/policydb.h b/security/selinux/ss/policydb.h
index 725d594..0d511cf 100644
--- a/security/selinux/ss/policydb.h
+++ b/security/selinux/ss/policydb.h
@@ -227,6 +227,7 @@
/* The policy database */
struct policydb {
int mls_enabled;
+ int android_netlink_route;
/* symbol tables */
struct symtab symtab[SYM_NUM];
@@ -313,6 +314,7 @@
#define PERM_SYMTAB_SIZE 32
#define POLICYDB_CONFIG_MLS 1
+#define POLICYDB_CONFIG_ANDROID_NETLINK_ROUTE (1 << 31)
/* the config flags related to unknown classes/perms are bits 2 and 3 */
#define REJECT_UNKNOWN 0x00000002
diff --git a/security/selinux/ss/services.c b/security/selinux/ss/services.c
index 0a258c0..2b3907e 100644
--- a/security/selinux/ss/services.c
+++ b/security/selinux/ss/services.c
@@ -70,6 +70,7 @@
#include "ebitmap.h"
#include "audit.h"
+int selinux_android_netlink_route;
int selinux_policycap_netpeer;
int selinux_policycap_openperm;
int selinux_policycap_alwaysnetwork;
@@ -1997,6 +1998,9 @@
POLICYDB_CAPABILITY_OPENPERM);
selinux_policycap_alwaysnetwork = ebitmap_get_bit(&policydb.policycaps,
POLICYDB_CAPABILITY_ALWAYSNETWORK);
+
+ selinux_android_netlink_route = policydb.android_netlink_route;
+ selinux_nlmsg_init();
}
static int security_preserve_bools(struct policydb *p);
