Merge branch 'android-msm-pixel-4.14-tm-security' into android-msm-pixel-4.14-tm
NOV 2022.2
Bug: 240449853
Change-Id: I2a56e22aec920eea34c5581f8d7562b8bccf828f
diff --git a/arch/arm64/boot/dts/google/sm7150-sunfish-battery.dtsi b/arch/arm64/boot/dts/google/sm7150-sunfish-battery.dtsi
index a3fb8aa..5e8a1e8 100644
--- a/arch/arm64/boot/dts/google/sm7150-sunfish-battery.dtsi
+++ b/arch/arm64/boot/dts/google/sm7150-sunfish-battery.dtsi
@@ -194,7 +194,7 @@
/* enable cycle counts */
google,cycle-counts;
/* rest charging */
- google,chg-rest-rate = <8>;
+ google,chg-rest-rate = <15>;
google,chg-rest-soc = <80>;
/* battery high temperature update threshold */
google,update-high-temp-threshold = <550>;
diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c
index f7dba10..932934f 100644
--- a/drivers/char/adsprpc.c
+++ b/drivers/char/adsprpc.c
@@ -2093,9 +2093,12 @@
int rc = wait_for_completion_timeout(&ctx->work,
msecs_to_jiffies(FASTRPC_TIMEOUT));
if (!rc) {
- pr_err("wait for completion timeout and trigger ADSP SSR b/132430192\n");
- /* b/132430192 WA to trigger adsp SSR */
- subsystem_restart("adsp");
+ pr_err("command timeout from domain id:%d\n", cid);
+ if (cid == ADSP_DOMAIN_ID) {
+ pr_err("trigger ADSP SSR b/132430192\n");
+ /* b/132430192 WA to trigger adsp SSR */
+ subsystem_restart("adsp");
+ }
goto bail;
}
} else
diff --git a/drivers/gpu/msm/a6xx_reg.h b/drivers/gpu/msm/a6xx_reg.h
index d0751f2..7deddcd 100644
--- a/drivers/gpu/msm/a6xx_reg.h
+++ b/drivers/gpu/msm/a6xx_reg.h
@@ -1,4 +1,5 @@
/* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -398,6 +399,8 @@
#define A6XX_RBBM_PERFCTR_RBBM_SEL_2 0x509
#define A6XX_RBBM_PERFCTR_RBBM_SEL_3 0x50A
#define A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x50B
+#define A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x50e
+#define A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x50f
#define A6XX_RBBM_ISDB_CNT 0x533
#define A6XX_RBBM_NC_MODE_CNTL 0x534
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c
index 7d0803c..c6fc09e 100644
--- a/drivers/gpu/msm/adreno.c
+++ b/drivers/gpu/msm/adreno.c
@@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -1445,6 +1446,8 @@
adreno_debugfs_init(adreno_dev);
adreno_profile_init(adreno_dev);
+ adreno_dev->perfcounter = false;
+
adreno_sysfs_init(adreno_dev);
kgsl_pwrscale_init(&pdev->dev, CONFIG_QCOM_ADRENO_DEFAULT_GOVERNOR);
diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h
index 1cc4fc0..a3016d7 100644
--- a/drivers/gpu/msm/adreno.h
+++ b/drivers/gpu/msm/adreno.h
@@ -1,4 +1,5 @@
/* Copyright (c) 2008-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -34,6 +35,9 @@
#define DEVICE_3D_NAME "kgsl-3d"
#define DEVICE_3D0_NAME "kgsl-3d0"
+/* Index to preemption scratch buffer to store KMD postamble */
+#define KMD_POSTAMBLE_IDX 100
+
/* ADRENO_DEVICE - Given a kgsl_device return the adreno device struct */
#define ADRENO_DEVICE(device) \
container_of(device, struct adreno_device, dev)
@@ -263,6 +267,9 @@
/* Time to allow preemption to complete (in ms) */
#define ADRENO_PREEMPT_TIMEOUT 10000
+#define PREEMPT_SCRATCH_ADDR(dev, id) \
+ ((dev)->preempt.scratch.gpuaddr + (id * sizeof(u64)))
+
#define ADRENO_INT_BIT(a, _bit) (((a)->gpucore->gpudev->int_bits) ? \
(adreno_get_int(a, _bit) < 0 ? 0 : \
BIT(adreno_get_int(a, _bit))) : 0)
@@ -299,6 +306,7 @@
* skipsaverestore: To skip saverestore during L1 preemption (for 6XX)
* usesgmem: enable GMEM save/restore across preemption (for 6XX)
* count: Track the number of preemptions triggered
+ * @postamble_len: Number of dwords in KMD postamble pm4 packet
*/
struct adreno_preemption {
atomic_t state;
@@ -310,6 +318,7 @@
bool skipsaverestore;
bool usesgmem;
unsigned int count;
+ u32 postamble_len;
};
@@ -604,6 +613,11 @@
void *zap_handle_ptr;
unsigned int soc_hw_rev;
bool gaming_bin;
+ /*
+ * @perfcounter: Flag to clear perfcounters across contexts and
+ * controls perfcounter ioctl read
+ */
+ bool perfcounter;
};
/**
diff --git a/drivers/gpu/msm/adreno_a6xx_preempt.c b/drivers/gpu/msm/adreno_a6xx_preempt.c
index ac928a6..7c4c621 100644
--- a/drivers/gpu/msm/adreno_a6xx_preempt.c
+++ b/drivers/gpu/msm/adreno_a6xx_preempt.c
@@ -1,4 +1,5 @@
/* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -548,13 +549,27 @@
if (context) {
struct adreno_context *drawctxt = ADRENO_CONTEXT(context);
struct adreno_ringbuffer *rb = drawctxt->rb;
- uint64_t dest = adreno_dev->preempt.scratch.gpuaddr +
- sizeof(u64) * rb->id;
+ uint64_t dest = PREEMPT_SCRATCH_ADDR(adreno_dev, rb->id);
*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 2);
cmds += cp_gpuaddr(adreno_dev, cmds, dest);
*cmds++ = lower_32_bits(gpuaddr);
*cmds++ = upper_32_bits(gpuaddr);
+
+ /*
+ * Add a KMD post amble to clear the perf counters during
+ * preemption
+ */
+ if (!adreno_dev->perfcounter) {
+ u64 kmd_postamble_addr =
+ PREEMPT_SCRATCH_ADDR(adreno_dev, KMD_POSTAMBLE_IDX);
+
+ *cmds++ = cp_type7_packet(CP_SET_AMBLE, 3);
+ *cmds++ = lower_32_bits(kmd_postamble_addr);
+ *cmds++ = upper_32_bits(kmd_postamble_addr);
+ *cmds++ = ((CP_KMD_AMBLE_TYPE << 20) | GENMASK(22, 20))
+ | (adreno_dev->preempt.postamble_len | GENMASK(19, 0));
+ }
}
return (unsigned int) (cmds - cmds_orig);
@@ -567,8 +582,7 @@
struct adreno_ringbuffer *rb = adreno_dev->cur_rb;
if (rb) {
- uint64_t dest = adreno_dev->preempt.scratch.gpuaddr +
- sizeof(u64) * rb->id;
+ uint64_t dest = PREEMPT_SCRATCH_ADDR(adreno_dev, rb->id);
*cmds++ = cp_mem_packet(adreno_dev, CP_MEM_WRITE, 2, 2);
cmds += cp_gpuaddr(adreno_dev, cmds, dest);
@@ -791,6 +805,33 @@
addr += A6XX_CP_CTXRECORD_PREEMPTION_COUNTER_SIZE;
}
+ /*
+ * First 8 dwords of the preemption scratch buffer is used to store the
+ * address for CP to save/restore VPC data. Reserve 11 dwords in the
+ * preemption scratch buffer from index KMD_POSTAMBLE_IDX for KMD
+ * postamble pm4 packets
+ */
+ if (!adreno_dev->perfcounter) {
+ u32 *postamble = preempt->scratch.hostptr +
+ (KMD_POSTAMBLE_IDX * sizeof(u64));
+ u32 count = 0;
+
+ postamble[count++] = cp_type7_packet(CP_REG_RMW, 3);
+ postamble[count++] = A6XX_RBBM_PERFCTR_SRAM_INIT_CMD;
+ postamble[count++] = 0x0;
+ postamble[count++] = 0x1;
+
+ postamble[count++] = cp_type7_packet(CP_WAIT_REG_MEM, 6);
+ postamble[count++] = 0x3;
+ postamble[count++] = A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS;
+ postamble[count++] = 0x0;
+ postamble[count++] = 0x1;
+ postamble[count++] = 0x1;
+ postamble[count++] = 0x0;
+
+ preempt->postamble_len = count;
+ }
+
ret = a6xx_preemption_iommu_init(adreno_dev);
err:
diff --git a/drivers/gpu/msm/adreno_compat.c b/drivers/gpu/msm/adreno_compat.c
index 8292a94..a144097 100644
--- a/drivers/gpu/msm/adreno_compat.c
+++ b/drivers/gpu/msm/adreno_compat.c
@@ -1,4 +1,5 @@
/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -230,6 +231,14 @@
struct kgsl_perfcounter_read_compat *read32 = data;
struct kgsl_perfcounter_read read;
+ /*
+ * When performance counter zapping is enabled, the counters are cleared
+ * across context switches. Reading the counters when they are zapped is
+ * not permitted.
+ */
+ if (!adreno_dev->perfcounter)
+ return -EPERM;
+
read.reads = (struct kgsl_perfcounter_read_group __user *)
(uintptr_t)read32->reads;
read.count = read32->count;
diff --git a/drivers/gpu/msm/adreno_ioctl.c b/drivers/gpu/msm/adreno_ioctl.c
index d18aa19..9ff82d6 100644
--- a/drivers/gpu/msm/adreno_ioctl.c
+++ b/drivers/gpu/msm/adreno_ioctl.c
@@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2018,2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -141,6 +142,14 @@
struct adreno_device *adreno_dev = ADRENO_DEVICE(dev_priv->device);
struct kgsl_perfcounter_read *read = data;
+ /*
+ * When performance counter zapping is enabled, the counters are cleared
+ * across context switches. Reading the counters when they are zapped is
+ * not permitted.
+ */
+ if (!adreno_dev->perfcounter)
+ return -EPERM;
+
return (long) adreno_perfcounter_read_group(adreno_dev, read->reads,
read->count);
}
diff --git a/drivers/gpu/msm/adreno_iommu.c b/drivers/gpu/msm/adreno_iommu.c
index 0fb7415..db6dff213 100644
--- a/drivers/gpu/msm/adreno_iommu.c
+++ b/drivers/gpu/msm/adreno_iommu.c
@@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -13,6 +14,7 @@
#include "adreno.h"
#include "kgsl_sharedmem.h"
#include "a3xx_reg.h"
+#include "a6xx_reg.h"
#include "adreno_pm4types.h"
#define A5XX_PFP_PER_PROCESS_UCODE_VER 0x5FF064
@@ -586,6 +588,12 @@
cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);
cmds += cp_wait_for_me(adreno_dev, cmds);
+ /* Clear performance counters during contect switches */
+ if (!adreno_dev->perfcounter) {
+ *cmds++ = cp_type4_packet(A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1);
+ *cmds++ = 0x1;
+ }
+
/* CP switches the pagetable and flushes the Caches */
*cmds++ = cp_packet(adreno_dev, CP_SMMU_TABLE_UPDATE, 4);
*cmds++ = lower_32_bits(ttbr0);
@@ -605,6 +613,17 @@
cmds += _adreno_iommu_add_idle_cmds(adreno_dev, cmds);
+ /* Wait for performance counter clear to finish */
+ if (!adreno_dev->perfcounter) {
+ *cmds++ = cp_type7_packet(CP_WAIT_REG_MEM, 6);
+ *cmds++ = 0x3;
+ *cmds++ = A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS;
+ *cmds++ = 0x0;
+ *cmds++ = 0x1;
+ *cmds++ = 0x1;
+ *cmds++ = 0x0;
+ }
+
return cmds - cmds_orig;
}
diff --git a/drivers/gpu/msm/adreno_perfcounter.c b/drivers/gpu/msm/adreno_perfcounter.c
index e7f2fd3..5527bf6 100644
--- a/drivers/gpu/msm/adreno_perfcounter.c
+++ b/drivers/gpu/msm/adreno_perfcounter.c
@@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -143,7 +144,8 @@
struct adreno_perfcount_group *group;
unsigned int counter, groupid;
- if (counters == NULL)
+ /* Do not save/restore if not requested */
+ if (counters == NULL || !adreno_dev->perfcounter)
return;
for (groupid = 0; groupid < counters->group_count; groupid++) {
@@ -176,7 +178,8 @@
struct adreno_perfcount_group *group;
unsigned int counter, groupid;
- if (counters == NULL)
+ /* Do not save/restore if not requested */
+ if (counters == NULL || !adreno_dev->perfcounter)
return;
for (groupid = 0; groupid < counters->group_count; groupid++) {
diff --git a/drivers/gpu/msm/adreno_pm4types.h b/drivers/gpu/msm/adreno_pm4types.h
index 5434963..282138e 100644
--- a/drivers/gpu/msm/adreno_pm4types.h
+++ b/drivers/gpu/msm/adreno_pm4types.h
@@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2017,2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -55,6 +56,9 @@
/* switches SMMU pagetable, used on a5xx only */
#define CP_SMMU_TABLE_UPDATE 0x53
+/* Designate command streams to be executed before/after state restore */
+#define CP_SET_AMBLE 0x55
+
/* Set internal CP registers, used to indicate context save data addresses */
#define CP_SET_PSEUDO_REGISTER 0x56
@@ -162,6 +166,9 @@
#define CP_LOADSTATE_STATETYPE_SHIFT 0x00000000
#define CP_LOADSTATE_EXTSRCADDR_SHIFT 0x00000002
+/* Used to define amble type in SET_AMBLE packet to execute during preemption */
+#define CP_KMD_AMBLE_TYPE 3
+
static inline uint pm4_calc_odd_parity_bit(uint val)
{
return (0x9669 >> (0xf & ((val) ^
diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c
index e325622..914014f 100644
--- a/drivers/gpu/msm/adreno_ringbuffer.c
+++ b/drivers/gpu/msm/adreno_ringbuffer.c
@@ -1,4 +1,5 @@
/* Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -592,7 +593,7 @@
if (gpudev->preemption_pre_ibsubmit &&
adreno_is_preemption_enabled(adreno_dev))
- total_sizedwords += 27;
+ total_sizedwords += 31;
if (gpudev->preemption_post_ibsubmit &&
adreno_is_preemption_enabled(adreno_dev))
diff --git a/drivers/gpu/msm/adreno_sysfs.c b/drivers/gpu/msm/adreno_sysfs.c
index 407c05b..13a5c0a 100644
--- a/drivers/gpu/msm/adreno_sysfs.c
+++ b/drivers/gpu/msm/adreno_sysfs.c
@@ -1,4 +1,5 @@
/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -528,6 +529,31 @@
return 0;
}
+static unsigned int _perfcounter_show(struct adreno_device *adreno_dev)
+{
+ return adreno_dev->perfcounter;
+}
+
+static int _perfcounter_store(struct adreno_device *adreno_dev,
+ unsigned int val)
+{
+ struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
+
+ if (adreno_dev->perfcounter == val)
+ return 0;
+
+ mutex_lock(&device->mutex);
+
+ /* Power down the GPU before changing the state */
+ kgsl_pwrctrl_change_state(device, KGSL_STATE_SUSPEND);
+ adreno_dev->perfcounter = val;
+ kgsl_pwrctrl_change_state(device, KGSL_STATE_SLUMBER);
+
+ mutex_unlock(&device->mutex);
+
+ return 0;
+}
+
static ssize_t _sysfs_store_u32(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
@@ -633,6 +659,7 @@
static ADRENO_SYSFS_BOOL(ifpc);
static ADRENO_SYSFS_RO_U32(ifpc_count);
static ADRENO_SYSFS_BOOL(acd);
+static ADRENO_SYSFS_BOOL(perfcounter);
static ADRENO_SYSFS_U32(acd_data_index);
static ADRENO_SYSFS_U32(acd_version);
@@ -662,6 +689,7 @@
&adreno_attr_ifpc_count.attr,
&adreno_attr_preempt_count.attr,
&adreno_attr_acd.attr,
+ &adreno_attr_perfcounter.attr,
&adreno_attr_acd_data_index.attr,
&adreno_attr_acd_version.attr,
&adreno_attr_acd_stride.attr,
@@ -820,8 +848,11 @@
ret = kgsl_create_device_sysfs_files(device->dev, _attr_list);
/* Add the PPD directory and files */
- if (ret == 0)
+ if (ret == 0) {
+ /* Notify userspace */
+ kobject_uevent(&device->dev->kobj, KOBJ_ADD);
ppd_sysfs_init(adreno_dev);
+ }
return 0;
}
diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
index 1fe016f..5a7a1fd 100644
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
@@ -209,6 +209,11 @@
goto err_exit;
if (fw.len == 0xFFFFU) {
+ if (sw.len > sizeof(self->rpc)) {
+ printk(KERN_INFO "Invalid sw len: %x\n", sw.len);
+ err = -EINVAL;
+ goto err_exit;
+ }
err = hw_atl_utils_fw_rpc_call(self, sw.len);
if (err < 0)
goto err_exit;
@@ -219,6 +224,11 @@
if (rpc) {
if (fw.len) {
+ if (fw.len > sizeof(self->rpc)) {
+ printk(KERN_INFO "Invalid fw len: %x\n", fw.len);
+ err = -EINVAL;
+ goto err_exit;
+ }
err =
hw_atl_utils_fw_downld_dwords(self,
PHAL_ATLANTIC->rpc_addr,
diff --git a/drivers/nfc/st21nfc.c b/drivers/nfc/st21nfc.c
index b83471a..28ffdad 100644
--- a/drivers/nfc/st21nfc.c
+++ b/drivers/nfc/st21nfc.c
@@ -107,6 +107,7 @@
wait_queue_head_t read_wq;
struct mutex read_mutex;
struct mutex pidle_mutex;
+ struct mutex polarity_mutex;
struct i2c_client *client;
struct miscdevice st21nfc_device;
uint8_t buffer[MAX_BUFFER_SIZE];
@@ -240,6 +241,7 @@
unsigned int irq_type;
int ret;
+ mutex_lock(&st21nfc_dev->polarity_mutex);
st21nfc_dev->polarity_mode = mode;
/* setup irq_flags */
switch (mode) {
@@ -260,6 +262,7 @@
ret = irq_set_irq_type(client->irq, irq_type);
if (ret) {
pr_err("%s : set_irq_type failed\n", __func__);
+ mutex_unlock(&st21nfc_dev->polarity_mutex);
return -ENODEV;
}
/* request irq. the irq is set whenever the chip has data available
@@ -273,10 +276,12 @@
client->name, st21nfc_dev);
if (ret) {
pr_err("%s : devm_request_irq failed\n", __func__);
+ mutex_unlock(&st21nfc_dev->polarity_mutex);
return -ENODEV;
}
st21nfc_dev->irq_is_attached = true;
st21nfc_disable_irq(st21nfc_dev);
+ mutex_unlock(&st21nfc_dev->polarity_mutex);
return ret;
}
@@ -932,6 +937,7 @@
/* init mutex and queues */
init_waitqueue_head(&st21nfc_dev->read_wq);
mutex_init(&st21nfc_dev->read_mutex);
+ mutex_init(&st21nfc_dev->polarity_mutex);
spin_lock_init(&st21nfc_dev->irq_enabled_lock);
pr_debug("%s : debug irq_gpio = %d, client-irq = %d\n",
__func__, desc_to_gpio(st21nfc_dev->gpiod_irq), client->irq);
@@ -963,6 +969,7 @@
err_misc_register:
mutex_destroy(&st21nfc_dev->read_mutex);
+ mutex_destroy(&st21nfc_dev->polarity_mutex);
err_sysfs_power_stats:
if (!IS_ERR(st21nfc_dev->gpiod_pidle)) {
sysfs_remove_group(&client->dev.kobj,
@@ -989,6 +996,7 @@
}
sysfs_remove_group(&client->dev.kobj, &st21nfc_attr_grp);
mutex_destroy(&st21nfc_dev->read_mutex);
+ mutex_destroy(&st21nfc_dev->polarity_mutex);
acpi_dev_remove_driver_gpios(ACPI_COMPANION(&client->dev));
return 0;
diff --git a/drivers/power/supply/google/google_charger.c b/drivers/power/supply/google/google_charger.c
index 02c98735..dab0f07 100644
--- a/drivers/power/supply/google/google_charger.c
+++ b/drivers/power/supply/google/google_charger.c
@@ -35,7 +35,6 @@
#include "google_bms.h"
#include "google_psy.h"
#include "logbuffer.h"
-#include "p9221_charger.h"
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
@@ -3718,14 +3717,9 @@
(dc_icl != -1),
dc_icl);
- if (ret < 0 || changed) {
- if (dc_icl == -1 && changed)
- ret = vote(chg_drv->dc_icl_votable, P9221_DEFAULT_VOTER,
- false, 0);
-
+ if (ret < 0 || changed)
pr_info("MSC_THERM_DC lvl=%d dc_icl=%d (%d)\n",
lvl, dc_icl, ret);
- }
/* make sure that fcc is reset to max when charging from WLC*/
if (ret ==0)
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index 1679ac6..e179425 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -3512,8 +3512,13 @@
if (!edev || !mdwc)
return NOTIFY_DONE;
- if (!mdwc->usb_data_enabled)
+ if (!mdwc->usb_data_enabled) {
+ if (event)
+ dwc3_msm_gadget_vbus_draw(mdwc, 500);
+ else
+ dwc3_msm_gadget_vbus_draw(mdwc, 0);
return NOTIFY_DONE;
+ }
dwc = platform_get_drvdata(mdwc->dwc3);
@@ -5141,7 +5146,8 @@
mdwc->drd_state = DRD_STATE_PERIPHERAL;
work = 1;
} else {
- dwc3_msm_gadget_vbus_draw(mdwc, 0);
+ if (mdwc->usb_data_enabled)
+ dwc3_msm_gadget_vbus_draw(mdwc, 0);
dev_dbg(mdwc->dev, "Cable disconnected\n");
}
break;
diff --git a/sound/soc/soc-ops.c b/sound/soc/soc-ops.c
index 07e4ac2..7260dd6 100644
--- a/sound/soc/soc-ops.c
+++ b/sound/soc/soc-ops.c
@@ -449,7 +449,7 @@
unsigned int val, val_mask, val2 = 0;
val = ucontrol->value.integer.value[0];
- if (mc->platform_max && val > mc->platform_max)
+ if (mc->platform_max && ((int)val + min) > mc->platform_max)
return -EINVAL;
if (val > max - min)
return -EINVAL;
