| /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/clock/qcom,gcc-qcs405.h> |
| #include <dt-bindings/msm/msm-bus-ids.h> |
| |
| &soc { |
| /* Secondary USB port related controller */ |
| usb3: ssusb@7580000 { |
| compatible = "qcom,dwc-usb3-msm"; |
| reg = <0x7580000 0x100000>; |
| reg-names = "core_base"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| interrupts = <0 25 0>, <0 319 0>; |
| interrupt-names = "pwr_event_irq", "hs_phy_irq"; |
| |
| dpdm-supply = <&usb2_phy0>; |
| clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, |
| <&clock_gcc GCC_SYS_NOC_USB3_CLK>, |
| <&clock_gcc GCC_USB30_SLEEP_CLK>, |
| <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>, |
| <&clock_rpmcc CXO_SMD_OTG_CLK>, |
| <&clock_gcc GCC_PCNOC_USB3_CLK>; |
| clock-names = "core_clk", "iface_clk", "sleep_clk", |
| "utmi_clk", "xo", "noc_aggr_clk"; |
| |
| qcom,core-clk-rate = <200000000>; |
| qcom,core-clk-rate-hs = <10000000>; |
| |
| qcom,pm-qos-latency = <181>; |
| qcom,msm-bus,name = "usb3"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_USB3 |
| MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_USB3 |
| MSM_BUS_SLAVE_EBI_CH0 240000 700000>; |
| |
| resets = <&clock_gcc GCC_USB_30_BCR>; |
| reset-names = "core_reset"; |
| |
| dwc3@7580000 { |
| compatible = "snps,dwc3"; |
| reg = <0x7580000 0xcd00>; |
| interrupts = <0 26 0>; |
| usb-phy = <&usb2_phy1>, <&usb_ss_phy>; |
| linux,sysdev_is_parent; |
| snps,disable-clk-gating; |
| snps,has-lpm-erratum; |
| snps,hird-threshold = /bits/ 8 <0x10>; |
| snps,usb3-u1u2-disable; |
| usb-core-id = <1>; |
| maximum-speed = "super-speed"; |
| dr_mode = "host"; |
| }; |
| }; |
| |
| /* Secondary USB port related High Speed PHY */ |
| usb2_phy1: hsphy@7a000 { |
| compatible = "qcom,usb-snps-hsphy"; |
| reg = <0x7a000 0x200>; |
| reg-names = "phy_csr"; |
| |
| vdd-supply = <&pms405_l4>; |
| vdda18-supply = <&pms405_l5>; |
| vdda33-supply = <&pms405_l12>; |
| qcom,vdd-voltage-level = <0 1144000 1200000>; |
| |
| clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>, |
| <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, |
| <&clock_gcc GCC_USB2A_PHY_SLEEP_CLK>; |
| clock-names = "ref_clk", "phy_csr_clk", "sleep_clk"; |
| |
| resets = <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, |
| <&clock_gcc GCC_USB2A_PHY_BCR>; |
| reset-names = "phy_reset", "phy_por_reset"; |
| |
| qcom,snps-hs-phy-init-seq = |
| <0xc0 0x01 0>, |
| <0xe8 0x0d 0>, |
| <0x74 0x12 0>, |
| <0x98 0x63 0>, |
| <0x9c 0x03 0>, |
| <0xa0 0x1d 0>, |
| <0xa4 0x03 0>, |
| <0x8c 0x23 0>, |
| <0x78 0x08 0>, |
| <0x7c 0xdc 0>, |
| <0x90 0xe0 20>, |
| <0x74 0x10 0>, |
| <0x90 0x60 0>, |
| <0xffffffff 0xffffffff 0>; |
| }; |
| |
| /* Secondary USB port related Super Speed PHY */ |
| usb_ss_phy: ssphy@78000 { |
| compatible = "qcom,usb-ssphy"; |
| reg = <0x78000 0x400>; |
| vdd-supply = <&pms405_l3>; |
| vdda18-supply = <&pms405_l5>; |
| qcom,vdd-voltage-level = <0 1050000 1050000>; |
| |
| clocks = <&clock_cmn_blk_pll CMN_BLK_PLL>, |
| <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, |
| <&clock_gcc GCC_USB3_PHY_PIPE_CLK>; |
| clock-names = "ref_clk", "cfg_ahb_clk", "pipe_clk"; |
| |
| resets = <&clock_gcc GCC_USB3_PHY_BCR>, |
| <&clock_gcc GCC_USB3PHY_PHY_BCR>; |
| reset-names = "phy_reset", "phy_com_reset"; |
| }; |
| |
| usb_nop_phy: usb_nop_phy { |
| compatible = "usb-nop-xceiv"; |
| }; |
| |
| /* Primary USB port related controller */ |
| usb2s: hsusb@78c0000 { |
| compatible = "qcom,dwc-usb3-msm"; |
| reg = <0x78c0000 0x100000>; |
| reg-names = "core_base"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| interrupts = <0 32 0>, <0 318 0>; |
| interrupt-names = "pwr_event_irq", "hs_phy_irq"; |
| |
| clocks = <&clock_gcc GCC_USB_HS_SYSTEM_CLK>, |
| <&clock_gcc GCC_PCNOC_USB2_CLK>, |
| <&clock_gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, |
| <&clock_gcc GCC_USB20_MOCK_UTMI_CLK>, |
| <&clock_rpmcc CXO_SMD_OTG_CLK>; |
| clock-names = "core_clk", "iface_clk", "sleep_clk", |
| "utmi_clk", "xo"; |
| |
| qcom,core-clk-rate = <133333333>; |
| qcom,msm-bus,name = "usb2s"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_USB_HS |
| MSM_BUS_SLAVE_EBI_CH0 0 0>, |
| <MSM_BUS_MASTER_USB_HS |
| MSM_BUS_SLAVE_EBI_CH0 60000 800000>; |
| |
| resets = <&clock_gcc GCC_USB_HS_BCR>; |
| reset-names = "core_reset"; |
| |
| dwc3@78c0000 { |
| compatible = "snps,dwc3"; |
| reg = <0x78c0000 0xcd00>; |
| interrupts = <0 44 0>; |
| usb-phy = <&usb2_phy0>, <&usb_nop_phy>; |
| linux,sysdev_is_parent; |
| snps,disable-clk-gating; |
| snps,has-lpm-erratum; |
| snps,hird-threshold = /bits/ 8 <0x10>; |
| snps,usb3_lpm_capable; |
| usb-core-id = <0>; |
| maximum-speed = "high-speed"; |
| dr_mode = "otg"; |
| }; |
| }; |
| |
| /* Primary USB port related High Speed PHY */ |
| usb2_phy0: hsphy@7c000 { |
| compatible = "qcom,usb-snps-hsphy"; |
| reg = <0x7c000 0x200>; |
| reg-names = "phy_csr"; |
| |
| vdd-supply = <&pms405_l4>; |
| vdda18-supply = <&pms405_l5>; |
| vdda33-supply = <&pms405_l12>; |
| qcom,vdd-voltage-level = <0 1144000 1200000>; |
| |
| clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK>, |
| <&clock_gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, |
| <&clock_gcc GCC_USB2A_PHY_SLEEP_CLK>; |
| clock-names = "ref_clk", "phy_csr_clk", "sleep_clk"; |
| |
| resets = <&clock_gcc GCC_QUSB2_PHY_BCR>, |
| <&clock_gcc GCC_USB2_HS_PHY_ONLY_BCR>; |
| reset-names = "phy_reset", "phy_por_reset"; |
| |
| qcom,snps-hs-phy-init-seq = |
| <0xc0 0x01 0>, |
| <0xe8 0x0d 0>, |
| <0x74 0x12 0>, |
| <0x98 0x63 0>, |
| <0x9c 0x03 0>, |
| <0xa0 0x1d 0>, |
| <0xa4 0x03 0>, |
| <0x8c 0x23 0>, |
| <0x78 0x08 0>, |
| <0x7c 0xdc 0>, |
| <0x90 0xe0 20>, |
| <0x74 0x10 0>, |
| <0x90 0x60 0>, |
| <0xffffffff 0xffffffff 0>; |
| }; |
| |
| }; |