| /* Copyright (c) 2013, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| &soc { |
| tmc_etr: tmc@fc326000 { |
| compatible = "arm,coresight-tmc"; |
| reg = <0xfc326000 0x1000>, |
| <0xfc37c000 0x3000>; |
| reg-names = "tmc-base", "bam-base"; |
| |
| qcom,memory-reservation-type = "EBI1"; |
| qcom,memory-reservation-size = <0x100000>; /* 1M EBI1 buffer */ |
| |
| coresight-id = <0>; |
| coresight-name = "coresight-tmc-etr"; |
| coresight-nr-inports = <1>; |
| coresight-ctis = <&cti0 &cti8>; |
| }; |
| |
| tpiu: tpiu@fc320000 { |
| compatible = "arm,coresight-tpiu"; |
| reg = <0xfc320000 0x1000>; |
| reg-names = "tpiu-base"; |
| |
| coresight-id = <1>; |
| coresight-name = "coresight-tpiu"; |
| coresight-nr-inports = <1>; |
| |
| vdd-supply = <&pm8110_l18>; |
| |
| qcom,vdd-voltage-level = <2950000 2950000>; |
| qcom,vdd-current-level = <15000 400000>; |
| }; |
| |
| replicator: replicator@fc324000 { |
| compatible = "qcom,coresight-replicator"; |
| reg = <0xfc324000 0x1000>; |
| reg-names = "replicator-base"; |
| |
| coresight-id = <2>; |
| coresight-name = "coresight-replicator"; |
| coresight-nr-inports = <1>; |
| coresight-outports = <0 1>; |
| coresight-child-list = <&tmc_etr &tpiu>; |
| coresight-child-ports = <0 0>; |
| }; |
| |
| tmc_etf: tmc@fc325000 { |
| compatible = "arm,coresight-tmc"; |
| reg = <0xfc325000 0x1000>; |
| reg-names = "tmc-base"; |
| |
| coresight-id = <3>; |
| coresight-name = "coresight-tmc-etf"; |
| coresight-nr-inports = <1>; |
| coresight-outports = <0>; |
| coresight-child-list = <&replicator>; |
| coresight-child-ports = <0>; |
| coresight-default-sink; |
| coresight-ctis = <&cti0 &cti8>; |
| }; |
| |
| funnel_merg: funnel@fc323000 { |
| compatible = "arm,coresight-funnel"; |
| reg = <0xfc323000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-id = <4>; |
| coresight-name = "coresight-funnel-merg"; |
| coresight-nr-inports = <2>; |
| coresight-outports = <0>; |
| coresight-child-list = <&tmc_etf>; |
| coresight-child-ports = <0>; |
| }; |
| |
| funnel_in0: funnel@fc321000 { |
| compatible = "arm,coresight-funnel"; |
| reg = <0xfc321000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-id = <5>; |
| coresight-name = "coresight-funnel-in0"; |
| coresight-nr-inports = <8>; |
| coresight-outports = <0>; |
| coresight-child-list = <&funnel_merg>; |
| coresight-child-ports = <0>; |
| }; |
| |
| funnel_in1: funnel@fc322000 { |
| compatible = "arm,coresight-funnel"; |
| reg = <0xfc322000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-id = <6>; |
| coresight-name = "coresight-funnel-in1"; |
| coresight-nr-inports = <8>; |
| coresight-outports = <0>; |
| coresight-child-list = <&funnel_merg>; |
| coresight-child-ports = <1>; |
| }; |
| |
| funnel_a7ss: funnel@fc355000 { |
| compatible = "arm,coresight-funnel"; |
| reg = <0xfc355000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-id = <7>; |
| coresight-name = "coresight-funnel-a7ss"; |
| coresight-nr-inports = <4>; |
| coresight-outports = <0>; |
| coresight-child-list = <&funnel_in1>; |
| coresight-child-ports = <6>; |
| }; |
| |
| stm: stm@fc302000 { |
| compatible = "arm,coresight-stm"; |
| reg = <0xfc302000 0x1000>, |
| <0xfa280000 0x180000>; |
| reg-names = "stm-base", "stm-data-base"; |
| |
| coresight-id = <8>; |
| coresight-name = "coresight-stm"; |
| coresight-nr-inports = <0>; |
| coresight-outports = <0>; |
| coresight-child-list = <&funnel_in0>; |
| coresight-child-ports = <7>; |
| }; |
| |
| etm0: etm@fc34c000 { |
| compatible = "arm,coresight-etm"; |
| reg = <0xfc34c000 0x1000>; |
| reg-names = "etm-base"; |
| |
| coresight-id = <9>; |
| coresight-name = "coresight-etm0"; |
| coresight-nr-inports = <0>; |
| coresight-outports = <0>; |
| coresight-child-list = <&funnel_a7ss>; |
| coresight-child-ports = <0>; |
| |
| qcom,pc-save; |
| qcom,round-robin; |
| }; |
| |
| etm1: etm@fc34d000 { |
| compatible = "arm,coresight-etm"; |
| reg = <0xfc34d000 0x1000>; |
| reg-names = "etm-base"; |
| |
| coresight-id = <10>; |
| coresight-name = "coresight-etm1"; |
| coresight-nr-inports = <0>; |
| coresight-outports = <0>; |
| coresight-child-list = <&funnel_a7ss>; |
| coresight-child-ports = <1>; |
| |
| qcom,pc-save; |
| qcom,round-robin; |
| }; |
| |
| etm2: etm@fc34e000 { |
| compatible = "arm,coresight-etm"; |
| reg = <0xfc34e000 0x1000>; |
| reg-names = "etm-base"; |
| |
| coresight-id = <11>; |
| coresight-name = "coresight-etm2"; |
| coresight-nr-inports = <0>; |
| coresight-outports = <0>; |
| coresight-child-list = <&funnel_a7ss>; |
| coresight-child-ports = <2>; |
| |
| qcom,pc-save; |
| qcom,round-robin; |
| }; |
| |
| etm3: etm@fc34f000 { |
| compatible = "arm,coresight-etm"; |
| reg = <0xfc34f000 0x1000>; |
| reg-names = "etm-base"; |
| |
| coresight-id = <12>; |
| coresight-name = "coresight-etm3"; |
| coresight-nr-inports = <0>; |
| coresight-outports = <0>; |
| coresight-child-list = <&funnel_a7ss>; |
| coresight-child-ports = <3>; |
| |
| qcom,pc-save; |
| qcom,round-robin; |
| }; |
| |
| csr: csr@fc301000 { |
| compatible = "qcom,coresight-csr"; |
| reg = <0xfc301000 0x1000>; |
| reg-names = "csr-base"; |
| |
| coresight-id = <13>; |
| coresight-name = "coresight-csr"; |
| coresight-nr-inports = <0>; |
| |
| qcom,blk-size = <1>; |
| }; |
| |
| cti0: cti@fc310000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc310000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <14>; |
| coresight-name = "coresight-cti0"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti1: cti@fc311000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc311000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <15>; |
| coresight-name = "coresight-cti1"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti2: cti@fc312000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc312000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <16>; |
| coresight-name = "coresight-cti2"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti3: cti@fc313000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc313000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <17>; |
| coresight-name = "coresight-cti3"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti4: cti@fc314000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc314000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <18>; |
| coresight-name = "coresight-cti4"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti5: cti@fc315000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc315000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <19>; |
| coresight-name = "coresight-cti5"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti6: cti@fc316000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc316000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <20>; |
| coresight-name = "coresight-cti6"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti7: cti@fc317000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc317000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <21>; |
| coresight-name = "coresight-cti7"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti8: cti@fc318000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc318000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <22>; |
| coresight-name = "coresight-cti8"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti_cpu0: cti@fc351000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc351000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <23>; |
| coresight-name = "coresight-cti-cpu0"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti_cpu1: cti@fc352000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc352000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <24>; |
| coresight-name = "coresight-cti-cpu1"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti_cpu2: cti@fc353000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc353000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <25>; |
| coresight-name = "coresight-cti-cpu2"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| cti_cpu3: cti@fc354000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0xfc354000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-id = <26>; |
| coresight-name = "coresight-cti-cpu3"; |
| coresight-nr-inports = <0>; |
| }; |
| |
| hwevent: hwevent@fd820018 { |
| compatible = "qcom,coresight-hwevent"; |
| reg = <0xfd820018 0x80>, |
| <0xf9011080 0x80>, |
| <0xfd4ab160 0x80>; |
| reg-names = "mmss-mux", "apcs-mux", "ppss-mux"; |
| |
| coresight-id = <27>; |
| coresight-name = "coresight-hwevent"; |
| coresight-nr-inports = <0>; |
| |
| qcom,hwevent-clks = "core_mmss_clk"; |
| }; |
| }; |
