arch/arm/boot/dts/apq8009-angelfish/apq8009-angelfish.dtsi

/* Copyright (c) 2016, LGE Inc. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "../qcom/msm8909.dtsi"
#include "../qcom/msm8909w-gpu.dtsi"
#include "../qcom/msm8909-pm8916.dtsi"
#include "../qcom/msm8909w.dtsi"
#include "apq8009-angelfish-pinctrl.dtsi"
#include "apq8009-angelfish-input.dtsi"
#include "apq8009-angelfish-regulator.dtsi"
#include "apq8009-angelfish-misc.dtsi"

/ {
	aliases {
		i2c6 = &i2c_6; /* I2C6 controller device */
	};
};

&external_image_mem {
	reg = <0x0 0x87a00000 0x0 0x0600000>;
};

&modem_adsp_mem {
	reg = <0x0 0x88000000 0x0 0x01800000>;
};

&peripheral_mem {
	reg = <0x0 0x89800000 0x0 0x0500000>;
};

&soc {

	i2c_6: i2c@78ba000 { /* BLSP1 QUP6 */
		status = "disabled";
		compatible = "qcom,i2c-msm-v2";
		#address-cells = <1>;
		#size-cells = <0>;
		reg-names = "qup_phys_addr", "bam_phys_addr";
		reg = <0x78ba000 0x1000>,
			  <0x7884000 0x23000>;
		interrupt-names = "qup_irq", "bam_irq";
		interrupts = <0 100 0>, <0 238 0>;
		qcom,clk-freq-out = <100000>;
		qcom,clk-freq-in  = <19200000>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			 <&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>;

		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_6_active>;
		pinctrl-1 = <&i2c_6_sleep>;
		qcom,noise-rjct-scl = <0>;
		qcom,noise-rjct-sda = <0>;
		qcom,bam-pipe-idx-cons = <14>;
		qcom,bam-pipe-idx-prod = <15>;
		qcom,master-id = <86>;
	};

	i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
		compatible = "qcom,i2c-msm-v2";
		reg-names = "qup_phys_addr";
		reg = <0x78b6000 0x1000>;
		interrupt-names = "qup_irq";
		interrupts = <0 96 0>;
		clock-names = "iface_clk", "core_clk";
		clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
			<&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;

		pinctrl-names = "i2c_active", "i2c_sleep";
		pinctrl-0 = <&i2c_2_active>;
		pinctrl-1 = <&i2c_2_sleep>;
		qcom,noise-rjct-scl = <0>;
		qcom,noise-rjct-sda = <0>;
		dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
			<&dma_blsp1 7 32 0x20000020 0x20>;
		dma-names = "tx", "rx";
		qcom,master-id = <86>;
	};

	qcom,venus@1de0000 {
		status = "disabled";
	};

	qcom,msm-ssc-sensors {
		compatible = "qcom,msm-ssc-sensors";
	};
};

&apc_vreg_corner {
	qcom,cpr-voltage-floor = <1050000 1125000 1155000>;
};

&spi_0 {
	cs-gpios = <&msm_gpio 10 0x00>;
};

&i2c_1 {
	status = "disabled";
};

&i2c_3 {
	status = "disabled";
};

&blsp1_uart1 {
	status = "ok";
	pinctrl-names = "default";
	pinctrl-0 = <&uart_console_sleep>;
};

&qcom_rng {
	status = "okay";
};

&qcom_crypto {
	status = "okay";
};

&qcom_cedev {
	status = "okay";
};

&qcom_seecom {
	status = "okay";
};

&qcom_tzlog {
	status = "okay";
};

&sdhc_1 {
	vdd-supply = <&pm8909_l8>;
	qcom,vdd-always-on;
	qcom,vdd-lpm-sup;
	qcom,vdd-voltage-level = <2900000 2900000>;
	qcom,vdd-current-level = <800 400000>;

	vdd-io-supply = <&pm8909_l5>;
	qcom,vdd-io-always-on;
	qcom,vdd-io-lpm-sup;
	qcom,vdd-io-voltage-level = <1800000 1800000>;
	qcom,vdd-io-current-level = <200 60000>;

	pinctrl-names = "active", "sleep";
	pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
	pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;

	qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
	qcom,nonremovable;

	status = "ok";
};

&venus_qseecom_mem {
	status = "disabled";
};

&gdsc_venus {
	status = "disabled";
};

&gdsc_venus_core0 {
	status = "disabled";
};

&usb_otg {
	qcom,no-set-vbus-power;
};