| /* manually add PCIE_POWER register details. Using GP 1 register */ |
| /* manual rework for FSP indexing */ |
| /* manual rework for EFUSE addressing and hwstrap */ |
| /* auto generated: Monday, August 15th, 2016 12:26:48pm */ |
| /* |
| * Copyright (c) 2016, Intel Corporation. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of Intel nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| #ifndef __MNH_HWIO_SCU_ |
| #define __MNH_HWIO_SCU_ |
| |
| #define HWIO_SCU_ID_REGOFF 0x0 |
| #define HWIO_SCU_ID_ADDR(bAddr, regX) (bAddr + HWIO_SCU_ID_REGOFF) |
| #define HWIO_SCU_ID_RSVD0_FLDMASK (0xff000000) |
| #define HWIO_SCU_ID_RSVD0_FLDSHFT (24) |
| #define HWIO_SCU_ID_MAJOR_REV_ID_FLDMASK (0xff0000) |
| #define HWIO_SCU_ID_MAJOR_REV_ID_FLDSHFT (16) |
| #define HWIO_SCU_ID_RSVD1_FLDMASK (0xff00) |
| #define HWIO_SCU_ID_RSVD1_FLDSHFT (8) |
| #define HWIO_SCU_ID_MINOR_REV_ID_FLDMASK (0xff) |
| #define HWIO_SCU_ID_MINOR_REV_ID_FLDSHFT (0) |
| |
| #define HWIO_SCU_CACHE_SIZE_REGOFF 0x4 |
| #define HWIO_SCU_CACHE_SIZE_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_CACHE_SIZE_REGOFF) |
| #define HWIO_SCU_CACHE_SIZE_CPU_L2_CAHCE_SIZE_FLDMASK (0xffff0000) |
| #define HWIO_SCU_CACHE_SIZE_CPU_L2_CAHCE_SIZE_FLDSHFT (16) |
| #define HWIO_SCU_CACHE_SIZE_CPU_L1_DATA_CAHCE_SIZE_FLDMASK (0xff00) |
| #define HWIO_SCU_CACHE_SIZE_CPU_L1_DATA_CAHCE_SIZE_FLDSHFT (8) |
| #define HWIO_SCU_CACHE_SIZE_CPU_L1_CODE_CAHCE_SIZE_FLDMASK (0xff) |
| #define HWIO_SCU_CACHE_SIZE_CPU_L1_CODE_CAHCE_SIZE_FLDSHFT (0) |
| |
| #define HWIO_SCU_LPDDR4_MEM_SIZE_REGOFF 0x8 |
| #define HWIO_SCU_LPDDR4_MEM_SIZE_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_LPDDR4_MEM_SIZE_REGOFF) |
| #define HWIO_SCU_LPDDR4_MEM_SIZE_LPDDR4_MEM_SIZE_FLDMASK (0xffffffff) |
| #define HWIO_SCU_LPDDR4_MEM_SIZE_LPDDR4_MEM_SIZE_FLDSHFT (0) |
| |
| #define HWIO_SCU_HW_STRAP_REGOFF 0x0C |
| #define HWIO_SCU_HW_STRAP_ADDR(bAddr, regX) (bAddr + HWIO_SCU_HW_STRAP_REGOFF) |
| #define HWIO_SCU_HW_STRAP_RSVD_FLDMASK (0xffffff00) |
| #define HWIO_SCU_HW_STRAP_RSVD_FLDSHFT (8) |
| #define HWIO_SCU_HW_STRAP_PCIE_LANE_FLDMASK (0x80) |
| #define HWIO_SCU_HW_STRAP_PCIE_LANE_FLDSHFT (7) |
| #define HWIO_SCU_HW_STRAP_SPIS_MODE_FLDMASK (0x40) |
| #define HWIO_SCU_HW_STRAP_SPIS_MODE_FLDSHFT (6) |
| #define HWIO_SCU_HW_STRAP_BOOT_DEBUG_FLDMASK (0x20) |
| #define HWIO_SCU_HW_STRAP_BOOT_DEBUG_FLDSHFT (5) |
| #define HWIO_SCU_HW_STRAP_BIT4_FLDMASK (0x10) |
| #define HWIO_SCU_HW_STRAP_BIT4_FLDSHFT (4) |
| #define HWIO_SCU_HW_STRAP_REF_CLK_SEL_FLDMASK (0x08) |
| #define HWIO_SCU_HW_STRAP_REF_CLK_SEL_FLDSHFT (3) |
| #define HWIO_SCU_HW_STRAP_PCIE_CLK_SEL_FLDMASK (0x04) |
| #define HWIO_SCU_HW_STRAP_PCIE_CLK_SEL_FLDSHFT (2) |
| #define HWIO_SCU_HW_STRAP_READY_FLDMASK (0x02) |
| #define HWIO_SCU_HW_STRAP_READY_FLDSHFT (1) |
| #define HWIO_SCU_HW_STRAP_BOOT_MODE_FLDMASK (0x01) |
| #define HWIO_SCU_HW_STRAP_BOOT_MODE_FLDSHFT (0) |
| |
| /* General Purpose Sticky */ |
| #define HWIO_SCU_GPS_REGNUM 4 |
| #define HWIO_SCU_GPS_REGOFF 0x10 |
| #define HWIO_SCU_GPS_ADDR(bAddr, regX) \ |
| (((regX >= 0) && (regX < HWIO_SCU_GPS_REGNUM)) ? \ |
| (bAddr + HWIO_SCU_GPS_REGOFF + (regX * 4)) : 0) |
| #define HWIO_SCU_GPS_GPS_FLDMASK (0xffffffff) |
| #define HWIO_SCU_GPS_GPS_FLDSHFT (0) |
| |
| #define MNH_BOOT_STAT (HWIO_SCU_GPS_ADDR(HWIO_SCU_BASE_ADDR, 0)) |
| |
| /* General Purpose Scratchpad */ |
| /* |
| * Allocation: |
| * 0 = pcie init done (from AP) |
| * 1 = Power mode register (from Easel) |
| * 2 = boot args mask (from AP) |
| * 3 = debug boot trace low (from Easel) |
| */ |
| #define HWIO_SCU_GP_REGNUM 4 |
| #define HWIO_SCU_GP_REGOFF 0x20 |
| #define HWIO_SCU_GP_ADDR(bAddr, regX) \ |
| (((regX >= 0) && (regX < HWIO_SCU_GP_REGNUM)) ? \ |
| (bAddr + HWIO_SCU_GP_REGOFF + (regX * 4)) : 0) |
| #define HWIO_SCU_GP_GP_FLDMASK (0xffffffff) |
| #define HWIO_SCU_GP_GP_FLDSHFT (0) |
| |
| #define HWIO_SCU_GP_POWER_MODE_REGOFF 0x24 |
| #define HWIO_SCU_GP_POWER_MODE_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_GP_POWER_MODE_REGOFF) |
| #define HWIO_SCU_GP_POWER_MODE_PCIE_L1_2_EN_FLDMASK (0x2) |
| #define HWIO_SCU_GP_POWER_MODE_PCIE_L1_2_EN_FLDSHFT (1) |
| #define HWIO_SCU_GP_POWER_MODE_PCIE_CLKPM_EN_FLDMASK (0x1) |
| #define HWIO_SCU_GP_POWER_MODE_PCIE_CLKPM_EN_FLDSHFT (0) |
| |
| #define HWIO_SCU_GP_BOOT_ARGS_REGOFF 0x28 |
| #define HWIO_SCU_GP_BOOT_ARGS_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_GP_BOOT_ARGS_REGOFF) |
| |
| #define MNH_BOOT_TRACE (HWIO_SCU_GP_ADDR(HWIO_SCU_BASE_ADDR, 3)) |
| |
| #define HWIO_SCU_GLOBAL_IRQ_STATUS_SET1_REGOFF 0x38 |
| #define HWIO_SCU_GLOBAL_IRQ_STATUS_SET1_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_GLOBAL_IRQ_STATUS_SET1_REGOFF) |
| #define HWIO_SCU_GLOBAL_IRQ_STATUS_SET1_GLOBAL_IRQ_STATUS_SET1_FLDMASK \ |
| (0xffffffff) |
| #define HWIO_SCU_GLOBAL_IRQ_STATUS_SET1_GLOBAL_IRQ_STATUS_SET1_FLDSHFT (0) |
| |
| #define HWIO_SCU_GLOBAL_IRQ_STATUS_SET0_REGOFF 0x3C |
| #define HWIO_SCU_GLOBAL_IRQ_STATUS_SET0_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_GLOBAL_IRQ_STATUS_SET0_REGOFF) |
| #define HWIO_SCU_GLOBAL_IRQ_STATUS_SET0_GLOBAL_IRQ_STATUS_SET0_FLDMASK \ |
| (0xffffffff) |
| #define HWIO_SCU_GLOBAL_IRQ_STATUS_SET0_GLOBAL_IRQ_STATUS_SET0_FLDSHFT (0) |
| |
| #define HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET1_REGOFF 0x48 |
| #define HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET1_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET1_REGOFF) |
| #define HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET1_GLOBAL_IRQ_HLT_RST_EN_SET1_FLDMASK \ |
| (0xffffffff) |
| #define HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET1_GLOBAL_IRQ_HLT_RST_EN_SET1_FLDSHFT \ |
| (0) |
| |
| #define HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET0_REGOFF 0x4C |
| #define HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET0_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET0_REGOFF) |
| #define HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET0_GLOBAL_IRQ_HLT_RST_EN_SET0_FLDMASK \ |
| (0xffffffff) |
| #define HWIO_SCU_GLOBAL_IRQ_HLT_RST_EN_SET0_GLOBAL_IRQ_HLT_RST_EN_SET0_FLDSHFT \ |
| (0) |
| |
| #define HWIO_SCU_GLOBAL_WAKE_EN_SET1_REGOFF 0x58 |
| #define HWIO_SCU_GLOBAL_WAKE_EN_SET1_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_GLOBAL_WAKE_EN_SET1_REGOFF) |
| #define HWIO_SCU_GLOBAL_WAKE_EN_SET1_GLOBAL_WAKE_EN_SET1_FLDMASK (0xffffffff) |
| #define HWIO_SCU_GLOBAL_WAKE_EN_SET1_GLOBAL_WAKE_EN_SET1_FLDSHFT (0) |
| |
| #define HWIO_SCU_GLOBAL_WAKE_EN_SET0_REGOFF 0x5C |
| #define HWIO_SCU_GLOBAL_WAKE_EN_SET0_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_GLOBAL_WAKE_EN_SET0_REGOFF) |
| #define HWIO_SCU_GLOBAL_WAKE_EN_SET0_GLOBAL_WAKE_EN_SET0_FLDMASK (0xffffffff) |
| #define HWIO_SCU_GLOBAL_WAKE_EN_SET0_GLOBAL_WAKE_EN_SET0_FLDSHFT (0) |
| |
| #define HWIO_SCU_SCU_IRQ_STATUS_REGOFF 0x70 |
| #define HWIO_SCU_SCU_IRQ_STATUS_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_SCU_IRQ_STATUS_REGOFF) |
| #define HWIO_SCU_SCU_IRQ_STATUS_RSVD0_FLDMASK (0xffffff80) |
| #define HWIO_SCU_SCU_IRQ_STATUS_RSVD0_FLDSHFT (7) |
| #define HWIO_SCU_SCU_IRQ_STATUS_LP4_FREQ_CHG_REQ_FLDMASK (0x40) |
| #define HWIO_SCU_SCU_IRQ_STATUS_LP4_FREQ_CHG_REQ_FLDSHFT (6) |
| #define HWIO_SCU_SCU_IRQ_STATUS_LP4_LPC_CMD_DONE_FLDMASK (0x20) |
| #define HWIO_SCU_SCU_IRQ_STATUS_LP4_LPC_CMD_DONE_FLDSHFT (5) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS4_DV_FLDMASK (0x10) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS4_DV_FLDSHFT (4) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS3_DV_FLDMASK (0x8) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS3_DV_FLDSHFT (3) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS2_DV_FLDMASK (0x4) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS2_DV_FLDSHFT (2) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS1_DV_FLDMASK (0x2) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS1_DV_FLDSHFT (1) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS0_DV_FLDMASK (0x1) |
| #define HWIO_SCU_SCU_IRQ_STATUS_PVT_SENS0_DV_FLDSHFT (0) |
| |
| #define HWIO_SCU_SCU_IRQ_ENABLE_REGOFF 0x74 |
| #define HWIO_SCU_SCU_IRQ_ENABLE_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_SCU_IRQ_ENABLE_REGOFF) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_RSVD0_FLDMASK (0xffffff80) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_RSVD0_FLDSHFT (7) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_LP4_FREQ_CHG_REQ_IE_FLDMASK (0x40) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_LP4_FREQ_CHG_REQ_IE_FLDSHFT (6) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_LP4_LPC_CMD_DONE_IE_FLDMASK (0x20) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_LP4_LPC_CMD_DONE_IE_FLDSHFT (5) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS4_IE_FLDMASK (0x10) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS4_IE_FLDSHFT (4) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS3_IE_FLDMASK (0x8) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS3_IE_FLDSHFT (3) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS2_IE_FLDMASK (0x4) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS2_IE_FLDSHFT (2) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS1_IE_FLDMASK (0x2) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS1_IE_FLDSHFT (1) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS0_IE_FLDMASK (0x1) |
| #define HWIO_SCU_SCU_IRQ_ENABLE_PVT_SENS0_IE_FLDSHFT (0) |
| |
| #define HWIO_SCU_RSTC_REGOFF 0x78 |
| #define HWIO_SCU_RSTC_ADDR(bAddr, regX) (bAddr + HWIO_SCU_RSTC_REGOFF) |
| #define HWIO_SCU_RSTC_INTR_HALT_RST_SEL_FLDMASK (0x80000000) |
| #define HWIO_SCU_RSTC_INTR_HALT_RST_SEL_FLDSHFT (31) |
| #define HWIO_SCU_RSTC_RSVD0_FLDMASK (0x70000000) |
| #define HWIO_SCU_RSTC_RSVD0_FLDSHFT (28) |
| #define HWIO_SCU_RSTC_I2C3_RST_FLDMASK (0x8000000) |
| #define HWIO_SCU_RSTC_I2C3_RST_FLDSHFT (27) |
| #define HWIO_SCU_RSTC_I2C2_RST_FLDMASK (0x4000000) |
| #define HWIO_SCU_RSTC_I2C2_RST_FLDSHFT (26) |
| #define HWIO_SCU_RSTC_I2C1_RST_FLDMASK (0x2000000) |
| #define HWIO_SCU_RSTC_I2C1_RST_FLDSHFT (25) |
| #define HWIO_SCU_RSTC_I2C0_RST_FLDMASK (0x1000000) |
| #define HWIO_SCU_RSTC_I2C0_RST_FLDSHFT (24) |
| #define HWIO_SCU_RSTC_UART1_RST_FLDMASK (0x800000) |
| #define HWIO_SCU_RSTC_UART1_RST_FLDSHFT (23) |
| #define HWIO_SCU_RSTC_UART0_RST_FLDMASK (0x400000) |
| #define HWIO_SCU_RSTC_UART0_RST_FLDSHFT (22) |
| #define HWIO_SCU_RSTC_SPIS_RST_FLDMASK (0x200000) |
| #define HWIO_SCU_RSTC_SPIS_RST_FLDSHFT (21) |
| #define HWIO_SCU_RSTC_SPIM_RST_FLDMASK (0x100000) |
| #define HWIO_SCU_RSTC_SPIM_RST_FLDSHFT (20) |
| #define HWIO_SCU_RSTC_GPIO_RST_FLDMASK (0x80000) |
| #define HWIO_SCU_RSTC_GPIO_RST_FLDSHFT (19) |
| #define HWIO_SCU_RSTC_PERI_DMA_RST_FLDMASK (0x40000) |
| #define HWIO_SCU_RSTC_PERI_DMA_RST_FLDSHFT (18) |
| #define HWIO_SCU_RSTC_TIMER_RST_FLDMASK (0x20000) |
| #define HWIO_SCU_RSTC_TIMER_RST_FLDSHFT (17) |
| #define HWIO_SCU_RSTC_WDT_RST_FLDMASK (0x10000) |
| #define HWIO_SCU_RSTC_WDT_RST_FLDSHFT (16) |
| #define HWIO_SCU_RSTC_RSVD1_FLDMASK (0xe000) |
| #define HWIO_SCU_RSTC_RSVD1_FLDSHFT (13) |
| #define HWIO_SCU_RSTC_PMON_RST_FLDMASK (0x1000) |
| #define HWIO_SCU_RSTC_PMON_RST_FLDSHFT (12) |
| #define HWIO_SCU_RSTC_MIPIRXPHY_RST_FLDMASK (0x800) |
| #define HWIO_SCU_RSTC_MIPIRXPHY_RST_FLDSHFT (11) |
| #define HWIO_SCU_RSTC_MIPITXPHY_RST_FLDMASK (0x400) |
| #define HWIO_SCU_RSTC_MIPITXPHY_RST_FLDSHFT (10) |
| #define HWIO_SCU_RSTC_MIPIRXCTL_RST_FLDMASK (0x200) |
| #define HWIO_SCU_RSTC_MIPIRXCTL_RST_FLDSHFT (9) |
| #define HWIO_SCU_RSTC_MIPITXCTL_RST_FLDMASK (0x100) |
| #define HWIO_SCU_RSTC_MIPITXCTL_RST_FLDSHFT (8) |
| #define HWIO_SCU_RSTC_PCIE_PHY_RST_FLDMASK (0x80) |
| #define HWIO_SCU_RSTC_PCIE_PHY_RST_FLDSHFT (7) |
| #define HWIO_SCU_RSTC_PCIE_CTL_RST_FLDMASK (0x40) |
| #define HWIO_SCU_RSTC_PCIE_CTL_RST_FLDSHFT (6) |
| #define HWIO_SCU_RSTC_RSVD2_FLDMASK (0x20) |
| #define HWIO_SCU_RSTC_RSVD2_FLDSHFT (5) |
| #define HWIO_SCU_RSTC_LP4PHY_RST_FLDMASK (0x10) |
| #define HWIO_SCU_RSTC_LP4PHY_RST_FLDSHFT (4) |
| #define HWIO_SCU_RSTC_LP4CTL_RST_FLDMASK (0x8) |
| #define HWIO_SCU_RSTC_LP4CTL_RST_FLDSHFT (3) |
| #define HWIO_SCU_RSTC_IPU_RST_FLDMASK (0x4) |
| #define HWIO_SCU_RSTC_IPU_RST_FLDSHFT (2) |
| #define HWIO_SCU_RSTC_CPU_RST_FLDMASK (0x2) |
| #define HWIO_SCU_RSTC_CPU_RST_FLDSHFT (1) |
| #define HWIO_SCU_RSTC_SW_COLDRST_FLDMASK (0x1) |
| #define HWIO_SCU_RSTC_SW_COLDRST_FLDSHFT (0) |
| |
| #define HWIO_SCU_RSTS_REGOFF 0x7C |
| #define HWIO_SCU_RSTS_ADDR(bAddr, regX) (bAddr + HWIO_SCU_RSTS_REGOFF) |
| #define HWIO_SCU_RSTS_RSVD0_FLDMASK (0xfffffc00) |
| #define HWIO_SCU_RSTS_RSVD0_FLDSHFT (10) |
| #define HWIO_SCU_RSTS_PVT3_ALARM_RESET_FLDMASK (0x200) |
| #define HWIO_SCU_RSTS_PVT3_ALARM_RESET_FLDSHFT (9) |
| #define HWIO_SCU_RSTS_PVT2_ALARM_RESET_FLDMASK (0x100) |
| #define HWIO_SCU_RSTS_PVT2_ALARM_RESET_FLDSHFT (8) |
| #define HWIO_SCU_RSTS_PVT1_ALARM_RESET_FLDMASK (0x80) |
| #define HWIO_SCU_RSTS_PVT1_ALARM_RESET_FLDSHFT (7) |
| #define HWIO_SCU_RSTS_PVT0_ALARM_RESET_FLDMASK (0x40) |
| #define HWIO_SCU_RSTS_PVT0_ALARM_RESET_FLDSHFT (6) |
| #define HWIO_SCU_RSTS_CPU_RST_FLDMASK (0x20) |
| #define HWIO_SCU_RSTS_CPU_RST_FLDSHFT (5) |
| #define HWIO_SCU_RSTS_INTR_RST_FLDMASK (0x10) |
| #define HWIO_SCU_RSTS_INTR_RST_FLDSHFT (4) |
| #define HWIO_SCU_RSTS_POR_RST_FLDMASK (0x8) |
| #define HWIO_SCU_RSTS_POR_RST_FLDSHFT (3) |
| #define HWIO_SCU_RSTS_WDT_WRST_FLDMASK (0x4) |
| #define HWIO_SCU_RSTS_WDT_WRST_FLDSHFT (2) |
| #define HWIO_SCU_RSTS_EXT_RST_FLDMASK (0x2) |
| #define HWIO_SCU_RSTS_EXT_RST_FLDSHFT (1) |
| #define HWIO_SCU_RSTS_SW_COLDRST_FLDMASK (0x1) |
| #define HWIO_SCU_RSTS_SW_COLDRST_FLDSHFT (0) |
| |
| #define HWIO_SCU_CCU_CLK_DIV_REGOFF 0x80 |
| #define HWIO_SCU_CCU_CLK_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_CCU_CLK_DIV_REGOFF) |
| #define HWIO_SCU_CCU_CLK_DIV_PVT_SENSOR_CLK_DIV_FLDMASK (0xfe000000) |
| #define HWIO_SCU_CCU_CLK_DIV_PVT_SENSOR_CLK_DIV_FLDSHFT (25) |
| #define HWIO_SCU_CCU_CLK_DIV_PCIE_AUX_CLK_DIV_FLDMASK (0x1f00000) |
| #define HWIO_SCU_CCU_CLK_DIV_PCIE_AUX_CLK_DIV_FLDSHFT (20) |
| #define HWIO_SCU_CCU_CLK_DIV_PCIE_AXI_CLK_DIV_FLDMASK (0xf0000) |
| #define HWIO_SCU_CCU_CLK_DIV_PCIE_AXI_CLK_DIV_FLDSHFT (16) |
| #define HWIO_SCU_CCU_CLK_DIV_AXI_FABRIC_CLK_DIV_FLDMASK (0xf000) |
| #define HWIO_SCU_CCU_CLK_DIV_AXI_FABRIC_CLK_DIV_FLDSHFT (12) |
| #define HWIO_SCU_CCU_CLK_DIV_LPDDR4_REFCLK_DIV_FLDMASK (0xf00) |
| #define HWIO_SCU_CCU_CLK_DIV_LPDDR4_REFCLK_DIV_FLDSHFT (8) |
| #define HWIO_SCU_CCU_CLK_DIV_IPU_CLK_DIV_FLDMASK (0xf0) |
| #define HWIO_SCU_CCU_CLK_DIV_IPU_CLK_DIV_FLDSHFT (4) |
| #define HWIO_SCU_CCU_CLK_DIV_CPU_CLK_DIV_FLDMASK (0xf) |
| #define HWIO_SCU_CCU_CLK_DIV_CPU_CLK_DIV_FLDSHFT (0) |
| |
| #define HWIO_SCU_CCU_CLK_CTL_REGOFF 0x84 |
| #define HWIO_SCU_CCU_CLK_CTL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_CCU_CLK_CTL_REGOFF) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_CPUCG_EN_FLDMASK (0x80000000) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_CPUCG_EN_FLDSHFT (31) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_LP4CG_EN_FLDMASK (0x40000000) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_LP4CG_EN_FLDSHFT (30) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_BTROMCG_EN_FLDMASK (0x20000000) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_BTROMCG_EN_FLDSHFT (29) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_BTSRAMCG_EN_FLDMASK (0x10000000) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_BTSRAMCG_EN_FLDSHFT (28) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_AXICG_EN_FLDMASK (0x8000000) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_AXICG_EN_FLDSHFT (27) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_AHBCG_EN_FLDMASK (0x4000000) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_AHBCG_EN_FLDSHFT (26) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_LP4_PLL_BYPCLK_CG_EN_FLDMASK (0x2000000) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_LP4_PLL_BYPCLK_CG_EN_FLDSHFT (25) |
| #define HWIO_SCU_CCU_CLK_CTL_LP4PHY_PLL_BYPASS_CLKEN_FLDMASK (0x1000000) |
| #define HWIO_SCU_CCU_CLK_CTL_LP4PHY_PLL_BYPASS_CLKEN_FLDSHFT (24) |
| #define HWIO_SCU_CCU_CLK_CTL_CPU_CLKEN_FLDMASK (0x800000) |
| #define HWIO_SCU_CCU_CLK_CTL_CPU_CLKEN_FLDSHFT (23) |
| #define HWIO_SCU_CCU_CLK_CTL_LP4_REFCLKEN_FLDMASK (0x400000) |
| #define HWIO_SCU_CCU_CLK_CTL_LP4_REFCLKEN_FLDSHFT (22) |
| #define HWIO_SCU_CCU_CLK_CTL_BTROM_CLKEN_FLDMASK (0x200000) |
| #define HWIO_SCU_CCU_CLK_CTL_BTROM_CLKEN_FLDSHFT (21) |
| #define HWIO_SCU_CCU_CLK_CTL_BTSRAM_CLKEN_FLDMASK (0x100000) |
| #define HWIO_SCU_CCU_CLK_CTL_BTSRAM_CLKEN_FLDSHFT (20) |
| #define HWIO_SCU_CCU_CLK_CTL_AXI_CLKEN_FLDMASK (0x80000) |
| #define HWIO_SCU_CCU_CLK_CTL_AXI_CLKEN_FLDSHFT (19) |
| #define HWIO_SCU_CCU_CLK_CTL_AHB_CLKEN_FLDMASK (0x40000) |
| #define HWIO_SCU_CCU_CLK_CTL_AHB_CLKEN_FLDSHFT (18) |
| #define HWIO_SCU_CCU_CLK_CTL_PCIE_AXI_CLKEN_FLDMASK (0x20000) |
| #define HWIO_SCU_CCU_CLK_CTL_PCIE_AXI_CLKEN_FLDSHFT (17) |
| #define HWIO_SCU_CCU_CLK_CTL_PCIE_AUX_CLKEN_FLDMASK (0x10000) |
| #define HWIO_SCU_CCU_CLK_CTL_PCIE_AUX_CLKEN_FLDSHFT (16) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_CLKGATE_CNT_FLDMASK (0xf000) |
| #define HWIO_SCU_CCU_CLK_CTL_HALT_CLKGATE_CNT_FLDSHFT (12) |
| #define HWIO_SCU_CCU_CLK_CTL_WAKE_CLKEN_CNT_FLDMASK (0xf00) |
| #define HWIO_SCU_CCU_CLK_CTL_WAKE_CLKEN_CNT_FLDSHFT (8) |
| #define HWIO_SCU_CCU_CLK_CTL_PMON_CLKEN_FLDMASK (0x80) |
| #define HWIO_SCU_CCU_CLK_CTL_PMON_CLKEN_FLDSHFT (7) |
| #define HWIO_SCU_CCU_CLK_CTL_MIPI_REFCLKEN_FLDMASK (0x40) |
| #define HWIO_SCU_CCU_CLK_CTL_MIPI_REFCLKEN_FLDSHFT (6) |
| #define HWIO_SCU_CCU_CLK_CTL_IPU_CLKEN_FLDMASK (0x20) |
| #define HWIO_SCU_CCU_CLK_CTL_IPU_CLKEN_FLDSHFT (5) |
| #define HWIO_SCU_CCU_CLK_CTL_MIPI_TESTCLKEN_FLDMASK (0x10) |
| #define HWIO_SCU_CCU_CLK_CTL_MIPI_TESTCLKEN_FLDSHFT (4) |
| #define HWIO_SCU_CCU_CLK_CTL_RSVD0_FLDMASK (0x8) |
| #define HWIO_SCU_CCU_CLK_CTL_RSVD0_FLDSHFT (3) |
| #define HWIO_SCU_CCU_CLK_CTL_IPU_CLK_SRC_FLDMASK (0x4) |
| #define HWIO_SCU_CCU_CLK_CTL_IPU_CLK_SRC_FLDSHFT (2) |
| #define HWIO_SCU_CCU_CLK_CTL_CPU_IPU_SYS200_MODE_FLDMASK (0x2) |
| #define HWIO_SCU_CCU_CLK_CTL_CPU_IPU_SYS200_MODE_FLDSHFT (1) |
| #define HWIO_SCU_CCU_CLK_CTL_LP4_AXI_SYS200_MODE_FLDMASK (0x1) |
| #define HWIO_SCU_CCU_CLK_CTL_LP4_AXI_SYS200_MODE_FLDSHFT (0) |
| |
| #define HWIO_SCU_PERIPH_CLK_CTRL_REGOFF 0x88 |
| #define HWIO_SCU_PERIPH_CLK_CTRL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_PERIPH_CLK_CTRL_REGOFF) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PCIE_CLK_MODE_FLDMASK (0x80000000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PCIE_CLK_MODE_FLDSHFT (31) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_RSVD0_FLDMASK (0x70000000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_RSVD0_FLDSHFT (28) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C3_CLK_MODE_FLDMASK (0x8000000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C3_CLK_MODE_FLDSHFT (27) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C2_CLK_MODE_FLDMASK (0x4000000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C2_CLK_MODE_FLDSHFT (26) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C1_CLK_MODE_FLDMASK (0x2000000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C1_CLK_MODE_FLDSHFT (25) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C0_CLK_MODE_FLDMASK (0x1000000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C0_CLK_MODE_FLDSHFT (24) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_UART1_CLK_MODE_FLDMASK (0x800000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_UART1_CLK_MODE_FLDSHFT (23) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_UART0_CLK_MODE_FLDMASK (0x400000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_UART0_CLK_MODE_FLDSHFT (22) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_SPIS_CLK_MODE_FLDMASK (0x200000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_SPIS_CLK_MODE_FLDSHFT (21) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_SPIM_CLK_MODE_FLDMASK (0x100000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_SPIM_CLK_MODE_FLDSHFT (20) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_RSVD1_FLDMASK (0xf0000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_RSVD1_FLDSHFT (16) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PCIE_REFCLKEN_FLDMASK (0x8000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PCIE_REFCLKEN_FLDSHFT (15) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PVT_CLKEN_FLDMASK (0x4000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PVT_CLKEN_FLDSHFT (14) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PERIPH_CLKEN_FLDMASK (0x2000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PERIPH_CLKEN_FLDSHFT (13) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_WDT_SPEED_UP_FLDMASK (0x1000) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_WDT_SPEED_UP_FLDSHFT (12) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C3_CLKEN_SW_FLDMASK (0x800) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C3_CLKEN_SW_FLDSHFT (11) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C2_CLKEN_SW_FLDMASK (0x400) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C2_CLKEN_SW_FLDSHFT (10) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C1_CLKEN_SW_FLDMASK (0x200) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C1_CLKEN_SW_FLDSHFT (9) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C0_CLKEN_SW_FLDMASK (0x100) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_I2C0_CLKEN_SW_FLDSHFT (8) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_UART1_CLKEN_SW_FLDMASK (0x80) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_UART1_CLKEN_SW_FLDSHFT (7) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_UART0_CLKEN_SW_FLDMASK (0x40) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_UART0_CLKEN_SW_FLDSHFT (6) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_SPIS_CLKEN_SW_FLDMASK (0x20) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_SPIS_CLKEN_SW_FLDSHFT (5) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_SPIM_CLKEN_SW_FLDMASK (0x10) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_SPIM_CLKEN_SW_FLDSHFT (4) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_GPIO_CLKEN_SW_FLDMASK (0x8) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_GPIO_CLKEN_SW_FLDSHFT (3) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PERI_DMA_CLKEN_SW_FLDMASK (0x4) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_PERI_DMA_CLKEN_SW_FLDSHFT (2) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_TIMER_CLKEN_SW_FLDMASK (0x2) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_TIMER_CLKEN_SW_FLDSHFT (1) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_WDT_CLKEN_SW_FLDMASK (0x1) |
| #define HWIO_SCU_PERIPH_CLK_CTRL_WDT_CLKEN_SW_FLDSHFT (0) |
| |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_REGOFF 0x8C |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_PERIPH_TMR_CLK_CTL_REGOFF) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_RSVD0_FLDMASK (0xfff00000) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_RSVD0_FLDSHFT (20) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR3_EXTCLK_SE_FLDMASK (0x80000) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR3_EXTCLK_SE_FLDSHFT (19) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR2_EXTCLK_SE_FLDMASK (0x40000) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR2_EXTCLK_SE_FLDSHFT (18) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR1_EXTCLK_SE_FLDMASK (0x20000) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR1_EXTCLK_SE_FLDSHFT (17) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR0_EXTCLK_SE_FLDMASK (0x10000) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR0_EXTCLK_SE_FLDSHFT (16) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_RSVD1_FLDMASK (0xf000) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_RSVD1_FLDSHFT (12) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR3_EXTPAUSE_POL_FLDMASK (0x800) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR3_EXTPAUSE_POL_FLDSHFT (11) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR2_EXTPAUSE_POL_FLDMASK (0x400) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR2_EXTPAUSE_POL_FLDSHFT (10) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR1_EXTPAUSE_POL_FLDMASK (0x200) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR1_EXTPAUSE_POL_FLDSHFT (9) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR0_EXTPAUSE_POL_FLDMASK (0x100) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR0_EXTPAUSE_POL_FLDSHFT (8) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_RSVD2_FLDMASK (0xf0) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_RSVD2_FLDSHFT (4) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR3_EXTPAUSE_EN_FLDMASK (0x8) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR3_EXTPAUSE_EN_FLDSHFT (3) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR2_EXTPAUSE_EN_FLDMASK (0x4) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR2_EXTPAUSE_EN_FLDSHFT (2) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR1_EXTPAUSE_EN_FLDMASK (0x2) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR1_EXTPAUSE_EN_FLDSHFT (1) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR0_EXTPAUSE_EN_FLDMASK (0x1) |
| #define HWIO_SCU_PERIPH_TMR_CLK_CTL_TMR0_EXTPAUSE_EN_FLDSHFT (0) |
| |
| #define HWIO_SCU_MEM_PWR_MGMNT_REGOFF 0x90 |
| #define HWIO_SCU_MEM_PWR_MGMNT_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_MEM_PWR_MGMNT_REGOFF) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_CPUMEM_PD_EN_FLDMASK (0x80000000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_CPUMEM_PD_EN_FLDSHFT (31) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_LP4CMEM_PD_EN_FLDMASK (0x40000000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_LP4CMEM_PD_EN_FLDSHFT (30) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_BTROM_PD_EN_FLDMASK (0x20000000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_BTROM_PD_EN_FLDSHFT (29) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_BTSRAM_PD_EN_FLDMASK (0x10000000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_BTSRAM_PD_EN_FLDSHFT (28) |
| #define HWIO_SCU_MEM_PWR_MGMNT_RSVD0_FLDMASK (0xc000000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_RSVD0_FLDSHFT (26) |
| #define HWIO_SCU_MEM_PWR_MGMNT_BTROM_SLP_FLDMASK (0x2000000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_BTROM_SLP_FLDSHFT (25) |
| #define HWIO_SCU_MEM_PWR_MGMNT_RSVD1_FLDMASK (0x1000000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_RSVD1_FLDSHFT (24) |
| #define HWIO_SCU_MEM_PWR_MGMNT_BTSRAM_DS_FLDMASK (0x800000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_BTSRAM_DS_FLDSHFT (23) |
| #define HWIO_SCU_MEM_PWR_MGMNT_BTSRAM_SD_FLDMASK (0x400000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_BTSRAM_SD_FLDSHFT (22) |
| #define HWIO_SCU_MEM_PWR_MGMNT_LP4C_MEM_DS_FLDMASK (0x200000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_LP4C_MEM_DS_FLDSHFT (21) |
| #define HWIO_SCU_MEM_PWR_MGMNT_LP4C_MEM_SD_FLDMASK (0x100000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_LP4C_MEM_SD_FLDSHFT (20) |
| #define HWIO_SCU_MEM_PWR_MGMNT_CPU_L2MEM_DS_FLDMASK (0x80000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_CPU_L2MEM_DS_FLDSHFT (19) |
| #define HWIO_SCU_MEM_PWR_MGMNT_CPU_L2MEM_SD_FLDMASK (0x40000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_CPU_L2MEM_SD_FLDSHFT (18) |
| #define HWIO_SCU_MEM_PWR_MGMNT_CPU_L1MEM_DS_FLDMASK (0x20000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_CPU_L1MEM_DS_FLDSHFT (17) |
| #define HWIO_SCU_MEM_PWR_MGMNT_CPU_L1MEM_SD_FLDMASK (0x10000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_CPU_L1MEM_SD_FLDSHFT (16) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_MEMPD_CNT_FLDMASK (0xf000) |
| #define HWIO_SCU_MEM_PWR_MGMNT_HALT_MEMPD_CNT_FLDSHFT (12) |
| #define HWIO_SCU_MEM_PWR_MGMNT_WAKE_MEMPU_CNT_FLDMASK (0xf00) |
| #define HWIO_SCU_MEM_PWR_MGMNT_WAKE_MEMPU_CNT_FLDSHFT (8) |
| #define HWIO_SCU_MEM_PWR_MGMNT_MIPITX_MEM_DS_FLDMASK (0x80) |
| #define HWIO_SCU_MEM_PWR_MGMNT_MIPITX_MEM_DS_FLDSHFT (7) |
| #define HWIO_SCU_MEM_PWR_MGMNT_MIPITX_MEM_SD_FLDMASK (0x40) |
| #define HWIO_SCU_MEM_PWR_MGMNT_MIPITX_MEM_SD_FLDSHFT (6) |
| #define HWIO_SCU_MEM_PWR_MGMNT_MIPIRX_MEM_DS_FLDMASK (0x20) |
| #define HWIO_SCU_MEM_PWR_MGMNT_MIPIRX_MEM_DS_FLDSHFT (5) |
| #define HWIO_SCU_MEM_PWR_MGMNT_MIPIRX_MEM_SD_FLDMASK (0x10) |
| #define HWIO_SCU_MEM_PWR_MGMNT_MIPIRX_MEM_SD_FLDSHFT (4) |
| #define HWIO_SCU_MEM_PWR_MGMNT_IPU_MEM_DS_FLDMASK (0x8) |
| #define HWIO_SCU_MEM_PWR_MGMNT_IPU_MEM_DS_FLDSHFT (3) |
| #define HWIO_SCU_MEM_PWR_MGMNT_IPU_MEM_SD_FLDMASK (0x4) |
| #define HWIO_SCU_MEM_PWR_MGMNT_IPU_MEM_SD_FLDSHFT (2) |
| #define HWIO_SCU_MEM_PWR_MGMNT_PCIE_MEM_DS_FLDMASK (0x2) |
| #define HWIO_SCU_MEM_PWR_MGMNT_PCIE_MEM_DS_FLDSHFT (1) |
| #define HWIO_SCU_MEM_PWR_MGMNT_PCIE_MEM_SD_FLDMASK (0x1) |
| #define HWIO_SCU_MEM_PWR_MGMNT_PCIE_MEM_SD_FLDSHFT (0) |
| |
| #define HWIO_SCU_DBG_CONFIG_REGOFF 0x0A0 |
| #define HWIO_SCU_DBG_CONFIG_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_DBG_CONFIG_REGOFF) |
| #define HWIO_SCU_DBG_CONFIG_DBG_CONFIG_FLDMASK (0xffffffff) |
| #define HWIO_SCU_DBG_CONFIG_DBG_CONFIG_FLDSHFT (0) |
| |
| #define HWIO_SCU_DBG_STATUS_REGOFF 0x0A4 |
| #define HWIO_SCU_DBG_STATUS_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_DBG_STATUS_REGOFF) |
| #define HWIO_SCU_DBG_STATUS_DBG_STATUS_FLDMASK (0xffffffff) |
| #define HWIO_SCU_DBG_STATUS_DBG_STATUS_FLDSHFT (0) |
| |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_REGOFF 0x0A8 |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_LPDDR4_LOW_POWER_CFG_REGOFF) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LP4_FSP_SW_OVERRIDE_FLDMASK \ |
| (0x80000000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LP4_FSP_SW_OVERRIDE_FLDSHFT (31) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LP4_PI_FREQCHG_EN_FLDMASK (0x40000000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LP4_PI_FREQCHG_EN_FLDSHFT (30) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LP4_FREQ_CHG_ACK_FLDMASK (0x20000000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LP4_FREQ_CHG_ACK_FLDSHFT (29) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_RSVD0_FLDMASK (0x1fff0000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_RSVD0_FLDSHFT (16) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LPC_EXT_CMD_REQ_FLDMASK (0x8000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LPC_EXT_CMD_REQ_FLDSHFT (15) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_RSVD1_FLDMASK (0x7c00) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_RSVD1_FLDSHFT (10) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LPC_FREQ_CHG_COPY_NUM_FLDMASK (0x300) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LPC_FREQ_CHG_COPY_NUM_FLDSHFT (8) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LPC_EXT_CMD_FLDMASK (0xff) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_CFG_LPC_EXT_CMD_FLDSHFT (0) |
| |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_REGOFF 0x0AC |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_LPDDR4_LOW_POWER_STS_REGOFF) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_RSVD0_FLDMASK (0xff800000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_RSVD0_FLDSHFT (23) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_LPDDR4_REQ_FSP_FLDMASK (0x700000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_LPDDR4_REQ_FSP_FLDSHFT (20) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_RSVD1_FLDMASK (0x80000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_RSVD1_FLDSHFT (19) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_LPDDR4_CUR_FSP_FLDMASK (0x70000) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_LPDDR4_CUR_FSP_FLDSHFT (16) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_RSVD2_FLDMASK (0xfffc) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_RSVD2_FLDSHFT (2) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_LPC_CMD_DONE_FLDMASK (0x2) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_LPC_CMD_DONE_FLDSHFT (1) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_LPC_CMD_RSP_FLDMASK (0x1) |
| #define HWIO_SCU_LPDDR4_LOW_POWER_STS_LPC_CMD_RSP_FLDSHFT (0) |
| |
| #define HWIO_SCU_EFUSE_PASSCODE_REGOFF 0x0B0 |
| #define HWIO_SCU_EFUSE_PASSCODE_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_EFUSE_PASSCODE_REGOFF) |
| #define HWIO_SCU_EFUSE_PASSCODE_RSVD0_FLDMASK (0xffff0000) |
| #define HWIO_SCU_EFUSE_PASSCODE_RSVD0_FLDSHFT (16) |
| #define HWIO_SCU_EFUSE_PASSCODE_PASSCODE_FLDMASK (0xffff) |
| #define HWIO_SCU_EFUSE_PASSCODE_PASSCODE_FLDSHFT (0) |
| |
| #define HWIO_SCU_PLL_PASSCODE_REGOFF 0x0B4 |
| #define HWIO_SCU_PLL_PASSCODE_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_PLL_PASSCODE_REGOFF) |
| #define HWIO_SCU_PLL_PASSCODE_RSVD0_FLDMASK (0xffff0000) |
| #define HWIO_SCU_PLL_PASSCODE_RSVD0_FLDSHFT (16) |
| #define HWIO_SCU_PLL_PASSCODE_PASSCODE_FLDMASK (0xffff) |
| #define HWIO_SCU_PLL_PASSCODE_PASSCODE_FLDSHFT (0) |
| |
| #define HWIO_SCU_SOC_GLOBAL_CONTROL_REGOFF 0x0B8 |
| #define HWIO_SCU_SOC_GLOBAL_CONTROL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_SOC_GLOBAL_CONTROL_REGOFF) |
| #define HWIO_SCU_SOC_GLOBAL_CONTROL_RSVD0_FLDMASK (0xfffffffe) |
| #define HWIO_SCU_SOC_GLOBAL_CONTROL_RSVD0_FLDSHFT (1) |
| #define HWIO_SCU_SOC_GLOBAL_CONTROL_GLOBAL_PAD_OUTPUT_DISABLE_FLDMASK (0x1) |
| #define HWIO_SCU_SOC_GLOBAL_CONTROL_GLOBAL_PAD_OUTPUT_DISABLE_FLDSHFT (0) |
| |
| #define HWIO_SCU_PCIE_REFCLK_PLL_FRAC_DIV_REGOFF 0x0C0 |
| #define HWIO_SCU_PCIE_REFCLK_PLL_FRAC_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_PCIE_REFCLK_PLL_FRAC_DIV_REGOFF) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_FRAC_DIV_RSVD0_FLDMASK (0xff000000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_FRAC_DIV_RSVD0_FLDSHFT (24) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_FRAC_DIV_FRAC_FLDMASK (0xffffff) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_FRAC_DIV_FRAC_FLDSHFT (0) |
| |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_REGOFF 0x0C4 |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_REGOFF) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_RSVD0_FLDMASK (0xc0000000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_RSVD0_FLDSHFT (30) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_REFDIV_FLDMASK (0x3f000000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_REFDIV_FLDSHFT (24) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_RSVD1_FLDMASK (0x800000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_RSVD1_FLDSHFT (23) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_POSTDIV1_FLDMASK (0x700000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_POSTDIV1_FLDSHFT (20) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_RSVD2_FLDMASK (0x80000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_RSVD2_FLDSHFT (19) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_POSTDIV2_FLDMASK (0x70000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_POSTDIV2_FLDSHFT (16) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_RSVD3_FLDMASK (0xf000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_RSVD3_FLDSHFT (12) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_FBDIV_FLDMASK (0xfff) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_INTGR_DIV_FBDIV_FLDSHFT (0) |
| |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_REGOFF 0x0C8 |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_PCIE_REFCLK_PLL_CTRL_REGOFF) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_RSVD0_FLDMASK (0xfffe0000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_RSVD0_FLDSHFT (17) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_FRZ_PLL_IN_FLDMASK (0x10000) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_FRZ_PLL_IN_FLDSHFT (16) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_RSVD1_FLDMASK (0xff80) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_RSVD1_FLDSHFT (7) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_PD_FLDMASK (0x40) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_PD_FLDSHFT (6) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_FOUTPOSTDIVPD_FLDMASK (0x20) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_FOUTPOSTDIVPD_FLDSHFT (5) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_FOUT4PHASEPD_FLDMASK (0x10) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_FOUT4PHASEPD_FLDSHFT (4) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_FOUTVCOPD_FLDMASK (0x8) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_FOUTVCOPD_FLDSHFT (3) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_DSMPD_FLDMASK (0x4) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_DSMPD_FLDSHFT (2) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_DACPD_FLDMASK (0x2) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_DACPD_FLDSHFT (1) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_BYPASS_FLDMASK (0x1) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_CTRL_BYPASS_FLDSHFT (0) |
| |
| #define HWIO_SCU_PCIE_REFCLK_PLL_STS_REGOFF 0x0CC |
| #define HWIO_SCU_PCIE_REFCLK_PLL_STS_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_PCIE_REFCLK_PLL_STS_REGOFF) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_STS_RSVD0_FLDMASK (0xfffffffe) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_STS_RSVD0_FLDSHFT (1) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_STS_LOCK_FLDMASK (0x1) |
| #define HWIO_SCU_PCIE_REFCLK_PLL_STS_LOCK_FLDSHFT (0) |
| |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_FRAC_DIV_REGOFF 0x0D0 |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_FRAC_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_LPDDR4_REFCLK_PLL_FRAC_DIV_REGOFF) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_FRAC_DIV_RSVD0_FLDMASK (0xff000000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_FRAC_DIV_RSVD0_FLDSHFT (24) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_FRAC_DIV_FRAC_FLDMASK (0xffffff) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_FRAC_DIV_FRAC_FLDSHFT (0) |
| |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_REGOFF 0x0D4 |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_REGOFF) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_RSVD0_FLDMASK (0xc0000000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_RSVD0_FLDSHFT (30) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_REFDIV_FLDMASK (0x3f000000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_REFDIV_FLDSHFT (24) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_RSVD1_FLDMASK (0x800000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_RSVD1_FLDSHFT (23) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_POSTDIV1_FLDMASK (0x700000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_POSTDIV1_FLDSHFT (20) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_RSVD2_FLDMASK (0x80000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_RSVD2_FLDSHFT (19) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_POSTDIV2_FLDMASK (0x70000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_POSTDIV2_FLDSHFT (16) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_RSVD3_FLDMASK (0xf000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_RSVD3_FLDSHFT (12) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_FBDIV_FLDMASK (0xfff) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_INTGR_DIV_FBDIV_FLDSHFT (0) |
| |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_REGOFF 0x0D8 |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_REGOFF) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_RSVD0_FLDMASK (0xfffe0000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_RSVD0_FLDSHFT (17) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_FRZ_PLL_IN_FLDMASK (0x10000) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_FRZ_PLL_IN_FLDSHFT (16) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_RSVD1_FLDMASK (0xff80) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_RSVD1_FLDSHFT (7) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_PD_FLDMASK (0x40) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_PD_FLDSHFT (6) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_FOUTPOSTDIVPD_FLDMASK (0x20) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_FOUTPOSTDIVPD_FLDSHFT (5) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_FOUT4PHASEPD_FLDMASK (0x10) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_FOUT4PHASEPD_FLDSHFT (4) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_FOUTVCOPD_FLDMASK (0x8) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_FOUTVCOPD_FLDSHFT (3) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_DSMPD_FLDMASK (0x4) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_DSMPD_FLDSHFT (2) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_DACPD_FLDMASK (0x2) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_DACPD_FLDSHFT (1) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_BYPASS_FLDMASK (0x1) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_CTRL_BYPASS_FLDSHFT (0) |
| |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_STS_REGOFF 0x0DC |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_STS_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_LPDDR4_REFCLK_PLL_STS_REGOFF) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_STS_RSVD0_FLDMASK (0xfffffffe) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_STS_RSVD0_FLDSHFT (1) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_STS_LOCK_FLDMASK (0x1) |
| #define HWIO_SCU_LPDDR4_REFCLK_PLL_STS_LOCK_FLDSHFT (0) |
| |
| #define HWIO_SCU_CPU_IPU_PLL_FRAC_DIV_REGOFF 0x0E0 |
| #define HWIO_SCU_CPU_IPU_PLL_FRAC_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_CPU_IPU_PLL_FRAC_DIV_REGOFF) |
| #define HWIO_SCU_CPU_IPU_PLL_FRAC_DIV_RSVD0_FLDMASK (0xff000000) |
| #define HWIO_SCU_CPU_IPU_PLL_FRAC_DIV_RSVD0_FLDSHFT (24) |
| #define HWIO_SCU_CPU_IPU_PLL_FRAC_DIV_FRAC_FLDMASK (0xffffff) |
| #define HWIO_SCU_CPU_IPU_PLL_FRAC_DIV_FRAC_FLDSHFT (0) |
| |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_REGOFF 0x0E4 |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_REGOFF) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_RSVD0_FLDMASK (0xc0000000) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_RSVD0_FLDSHFT (30) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_REFDIV_FLDMASK (0x3f000000) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_REFDIV_FLDSHFT (24) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_RSVD1_FLDMASK (0x800000) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_RSVD1_FLDSHFT (23) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_POSTDIV1_FLDMASK (0x700000) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_POSTDIV1_FLDSHFT (20) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_RSVD2_FLDMASK (0x80000) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_RSVD2_FLDSHFT (19) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_POSTDIV2_FLDMASK (0x70000) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_POSTDIV2_FLDSHFT (16) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_RSVD3_FLDMASK (0xf000) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_RSVD3_FLDSHFT (12) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_FBDIV_FLDMASK (0xfff) |
| #define HWIO_SCU_CPU_IPU_PLL_INTGR_DIV_FBDIV_FLDSHFT (0) |
| |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_REGOFF 0x0E8 |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_CPU_IPU_PLL_CTRL_REGOFF) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_RSVD0_FLDMASK (0xfffe0000) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_RSVD0_FLDSHFT (17) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_FRZ_PLL_IN_FLDMASK (0x10000) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_FRZ_PLL_IN_FLDSHFT (16) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_RSVD1_FLDMASK (0xff80) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_RSVD1_FLDSHFT (7) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_PD_FLDMASK (0x40) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_PD_FLDSHFT (6) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_FOUTPOSTDIVPD_FLDMASK (0x20) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_FOUTPOSTDIVPD_FLDSHFT (5) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_FOUT4PHASEPD_FLDMASK (0x10) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_FOUT4PHASEPD_FLDSHFT (4) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_FOUTVCOPD_FLDMASK (0x8) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_FOUTVCOPD_FLDSHFT (3) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_DSMPD_FLDMASK (0x4) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_DSMPD_FLDSHFT (2) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_DACPD_FLDMASK (0x2) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_DACPD_FLDSHFT (1) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_BYPASS_FLDMASK (0x1) |
| #define HWIO_SCU_CPU_IPU_PLL_CTRL_BYPASS_FLDSHFT (0) |
| |
| #define HWIO_SCU_CPU_IPU_PLL_STS_REGOFF 0x0EC |
| #define HWIO_SCU_CPU_IPU_PLL_STS_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_CPU_IPU_PLL_STS_REGOFF) |
| #define HWIO_SCU_CPU_IPU_PLL_STS_RSVD0_FLDMASK (0xfffffffe) |
| #define HWIO_SCU_CPU_IPU_PLL_STS_RSVD0_FLDSHFT (1) |
| #define HWIO_SCU_CPU_IPU_PLL_STS_LOCK_FLDMASK (0x1) |
| #define HWIO_SCU_CPU_IPU_PLL_STS_LOCK_FLDSHFT (0) |
| |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_REGNUM 4 |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_REGOFF 0x0F0 |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_ADDR(bAddr, regX) \ |
| (((regX >= 0) && (regX < HWIO_SCU_LPDDR4_FSP_SETTING_REGNUM)) ? \ |
| (bAddr + HWIO_SCU_LPDDR4_FSP_SETTING_REGOFF + (regX * 4)) : 0x0) |
| |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_RSVD0_FLDMASK (0xc0000000) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_RSVD0_FLDSHFT (30) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_SW_CTRL_FLDMASK (0x20000000) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_SW_CTRL_FLDSHFT (29) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_SYS200_MODE_FLDMASK (0x10000000) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_SYS200_MODE_FLDSHFT (28) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_PCIE_AXI_CLK_DIV_FLDMASK (0xf000000) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_PCIE_AXI_CLK_DIV_FLDSHFT (24) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_AXI_FABRIC_CLK_DIV_FLDMASK (0xf00000) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_AXI_FABRIC_CLK_DIV_FLDSHFT (20) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_LPDDR4_REFCLK_DIV_FLDMASK (0xf0000) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_LPDDR4_REFCLK_DIV_FLDSHFT (16) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_RSVD1_FLDMASK (0xf000) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_RSVD1_FLDSHFT (12) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_FBDIV_FLDMASK (0xfff) |
| #define HWIO_SCU_LPDDR4_FSP_SETTING_FSP_FBDIV_FLDSHFT (0) |
| |
| #define HWIO_SCU_PVT_CONTROL_REGNUM 4 |
| #define HWIO_SCU_PVT_CONTROL_REGOFF 0x100 |
| #define HWIO_SCU_PVT_CONTROL_ADDR(bAddr, regX) \ |
| (((regX >= 0) && (regX < HWIO_SCU_PVT_CONTROL_REGNUM)) ? \ |
| (bAddr + HWIO_SCU_PVT_CONTROL_REGOFF + (regX * 8)) : 0) |
| #define HWIO_SCU_PVT_CONTROL_ALARM_ENA_FLDMASK (0x80000000) |
| #define HWIO_SCU_PVT_CONTROL_ALARM_ENA_FLDSHFT (31) |
| #define HWIO_SCU_PVT_CONTROL_TRIG_FLDMASK (0x7fe00000) |
| #define HWIO_SCU_PVT_CONTROL_TRIG_FLDSHFT (21) |
| #define HWIO_SCU_PVT_CONTROL_TRIM_FLDMASK (0x1f0000) |
| #define HWIO_SCU_PVT_CONTROL_TRIM_FLDSHFT (16) |
| #define HWIO_SCU_PVT_CONTROL_RSVD0_FLDMASK (0xffc0) |
| #define HWIO_SCU_PVT_CONTROL_RSVD0_FLDSHFT (6) |
| #define HWIO_SCU_PVT_CONTROL_PRECISION_FLDMASK (0x30) |
| #define HWIO_SCU_PVT_CONTROL_PRECISION_FLDSHFT (4) |
| #define HWIO_SCU_PVT_CONTROL_PSAMPLE_FLDMASK (0xc) |
| #define HWIO_SCU_PVT_CONTROL_PSAMPLE_FLDSHFT (2) |
| #define HWIO_SCU_PVT_CONTROL_VSAMPLE_FLDMASK (0x2) |
| #define HWIO_SCU_PVT_CONTROL_VSAMPLE_FLDSHFT (1) |
| #define HWIO_SCU_PVT_CONTROL_ENA_FLDMASK (0x1) |
| #define HWIO_SCU_PVT_CONTROL_ENA_FLDSHFT (0) |
| |
| #define HWIO_SCU_PVT_DATA_REGNUM 4 |
| #define HWIO_SCU_PVT_DATA_REGOFF 0x104 |
| #define HWIO_SCU_PVT_DATA_ADDR(bAddr, regX) \ |
| (((regX >= 0) && (regX < HWIO_SCU_PVT_DATA_REGNUM)) ? \ |
| (bAddr + HWIO_SCU_PVT_DATA_REGOFF + (regX * 8)) : 0) |
| #define HWIO_SCU_PVT_DATA_RSVD0_FLDMASK (0xfffe0000) |
| #define HWIO_SCU_PVT_DATA_RSVD0_FLDSHFT (17) |
| #define HWIO_SCU_PVT_DATA_DATAVALID_FLDMASK (0x10000) |
| #define HWIO_SCU_PVT_DATA_DATAVALID_FLDSHFT (16) |
| #define HWIO_SCU_PVT_DATA_RSVD1_FLDMASK (0xfc00) |
| #define HWIO_SCU_PVT_DATA_RSVD1_FLDSHFT (10) |
| #define HWIO_SCU_PVT_DATA_DATA_FLDMASK (0x3ff) |
| #define HWIO_SCU_PVT_DATA_DATA_FLDSHFT (0) |
| |
| #define HWIO_SCU_EFUSE_CTRL_REGOFF 0x140 |
| #define HWIO_SCU_EFUSE_CTRL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_EFUSE_CTRL_REGOFF) |
| #define HWIO_SCU_EFUSE_CTRL_RSVD0_FLDMASK (0xffffff80) |
| #define HWIO_SCU_EFUSE_CTRL_RSVD0_FLDSHFT (7) |
| #define HWIO_SCU_EFUSE_CTRL_LOAD_FLDMASK (0x40) |
| #define HWIO_SCU_EFUSE_CTRL_LOAD_FLDSHFT (6) |
| #define HWIO_SCU_EFUSE_CTRL_PGENB_FLDMASK (0x20) |
| #define HWIO_SCU_EFUSE_CTRL_PGENB_FLDSHFT (5) |
| #define HWIO_SCU_EFUSE_CTRL_PS_FLDMASK (0x10) |
| #define HWIO_SCU_EFUSE_CTRL_PS_FLDSHFT (4) |
| #define HWIO_SCU_EFUSE_CTRL_PD_FLDMASK (0x8) |
| #define HWIO_SCU_EFUSE_CTRL_PD_FLDSHFT (3) |
| #define HWIO_SCU_EFUSE_CTRL_MR_FLDMASK (0x4) |
| #define HWIO_SCU_EFUSE_CTRL_MR_FLDSHFT (2) |
| #define HWIO_SCU_EFUSE_CTRL_RSB_FLDMASK (0x2) |
| #define HWIO_SCU_EFUSE_CTRL_RSB_FLDSHFT (1) |
| #define HWIO_SCU_EFUSE_CTRL_RWL_FLDMASK (0x1) |
| #define HWIO_SCU_EFUSE_CTRL_RWL_FLDSHFT (0) |
| |
| #define HWIO_SCU_EFUSE_ACC_REGOFF 0x144 |
| #define HWIO_SCU_EFUSE_ACC_ADDR(bAddr, regX) (bAddr + HWIO_SCU_EFUSE_ACC_REGOFF) |
| #define HWIO_SCU_EFUSE_ACC_RSVD0_FLDMASK (0xff000000) |
| #define HWIO_SCU_EFUSE_ACC_RSVD0_FLDSHFT (24) |
| #define HWIO_SCU_EFUSE_ACC_A7_FLDMASK (0x800000) |
| #define HWIO_SCU_EFUSE_ACC_A7_FLDSHFT (23) |
| #define HWIO_SCU_EFUSE_ACC_A6_FLDMASK (0x400000) |
| #define HWIO_SCU_EFUSE_ACC_A6_FLDSHFT (22) |
| #define HWIO_SCU_EFUSE_ACC_A5_FLDMASK (0x200000) |
| #define HWIO_SCU_EFUSE_ACC_A5_FLDSHFT (21) |
| #define HWIO_SCU_EFUSE_ACC_A4_FLDMASK (0x100000) |
| #define HWIO_SCU_EFUSE_ACC_A4_FLDSHFT (20) |
| #define HWIO_SCU_EFUSE_ACC_A3_FLDMASK (0x80000) |
| #define HWIO_SCU_EFUSE_ACC_A3_FLDSHFT (19) |
| #define HWIO_SCU_EFUSE_ACC_ZEROED_FLDMASK \ |
| (HWIO_SCU_EFUSE_ACC_A3_FLDMASK | \ |
| HWIO_SCU_EFUSE_ACC_A4_FLDMASK | \ |
| HWIO_SCU_EFUSE_ACC_A5_FLDMASK | \ |
| HWIO_SCU_EFUSE_ACC_A6_FLDMASK | \ |
| HWIO_SCU_EFUSE_ACC_A7_FLDMASK) |
| #define HWIO_SCU_EFUSE_ACC_ZEROED_FLDSHFT HWIO_SCU_EFUSE_ACC_A3_FLDSHFT |
| #define HWIO_SCU_EFUSE_ACC_A2_FLDMASK (0x40000) |
| #define HWIO_SCU_EFUSE_ACC_A2_FLDSHFT (18) |
| #define HWIO_SCU_EFUSE_ACC_A1_FLDMASK (0x20000) |
| #define HWIO_SCU_EFUSE_ACC_A1_FLDSHFT (17) |
| #define HWIO_SCU_EFUSE_ACC_A0_FLDMASK (0x10000) |
| #define HWIO_SCU_EFUSE_ACC_A0_FLDSHFT (16) |
| #define HWIO_SCU_EFUSE_ACC_ROW_FLDMASK \ |
| (HWIO_SCU_EFUSE_ACC_A0_FLDMASK | \ |
| HWIO_SCU_EFUSE_ACC_A1_FLDMASK | \ |
| HWIO_SCU_EFUSE_ACC_A2_FLDMASK) |
| #define HWIO_SCU_EFUSE_ACC_ROW_FLDSHFT HWIO_SCU_EFUSE_ACC_A0_FLDSHFT |
| #define HWIO_SCU_EFUSE_ACC_RSVD1_FLDMASK (0xfffc) |
| #define HWIO_SCU_EFUSE_ACC_RSVD1_FLDSHFT (2) |
| #define HWIO_SCU_EFUSE_ACC_CSB_FLDMASK (0x2) |
| #define HWIO_SCU_EFUSE_ACC_CSB_FLDSHFT (1) |
| #define HWIO_SCU_EFUSE_ACC_STROBE_FLDMASK (0x1) |
| #define HWIO_SCU_EFUSE_ACC_STROBE_FLDSHFT (0) |
| |
| #define HWIO_SCU_EFUSE_READ_DATA_REGOFF 0x148 |
| #define HWIO_SCU_EFUSE_READ_DATA_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_EFUSE_READ_DATA_REGOFF) |
| #define HWIO_SCU_EFUSE_READ_DATA_READ_DATA_FLDMASK (0xffffffff) |
| #define HWIO_SCU_EFUSE_READ_DATA_READ_DATA_FLDSHFT (0) |
| |
| #define HWIO_SCU_EFUSE_REDN_FLAG_REGOFF 0x14C |
| #define HWIO_SCU_EFUSE_REDN_FLAG_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_EFUSE_REDN_FLAG_REGOFF) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RSVD0_FLDMASK (0xfffffff0) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RSVD0_FLDSHFT (4) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RF3_FLDMASK (0x8) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RF3_FLDSHFT (3) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RF2_FLDMASK (0x4) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RF2_FLDSHFT (2) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RF1_FLDMASK (0x2) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RF1_FLDSHFT (1) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RF0_FLDMASK (0x1) |
| #define HWIO_SCU_EFUSE_REDN_FLAG_RF0_FLDSHFT (0) |
| |
| #define HWIO_SCU_IPU_PLL_FRAC_DIV_REGOFF 0x1C0 |
| #define HWIO_SCU_IPU_PLL_FRAC_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_IPU_PLL_FRAC_DIV_REGOFF) |
| #define HWIO_SCU_IPU_PLL_FRAC_DIV_RSVD0_FLDMASK (0xff000000) |
| #define HWIO_SCU_IPU_PLL_FRAC_DIV_RSVD0_FLDSHFT (24) |
| #define HWIO_SCU_IPU_PLL_FRAC_DIV_FRAC_FLDMASK (0xffffff) |
| #define HWIO_SCU_IPU_PLL_FRAC_DIV_FRAC_FLDSHFT (0) |
| |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_REGOFF 0x1C4 |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_IPU_PLL_INTGR_DIV_REGOFF) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_RSVD0_FLDMASK (0xc0000000) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_RSVD0_FLDSHFT (30) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_REFDIV_FLDMASK (0x3f000000) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_REFDIV_FLDSHFT (24) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_RSVD1_FLDMASK (0x800000) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_RSVD1_FLDSHFT (23) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_POSTDIV1_FLDMASK (0x700000) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_POSTDIV1_FLDSHFT (20) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_RSVD2_FLDMASK (0x80000) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_RSVD2_FLDSHFT (19) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_POSTDIV2_FLDMASK (0x70000) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_POSTDIV2_FLDSHFT (16) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_RSVD3_FLDMASK (0xf000) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_RSVD3_FLDSHFT (12) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_FBDIV_FLDMASK (0xfff) |
| #define HWIO_SCU_IPU_PLL_INTGR_DIV_FBDIV_FLDSHFT (0) |
| |
| #define HWIO_SCU_IPU_PLL_CTRL_REGOFF 0x1C8 |
| #define HWIO_SCU_IPU_PLL_CTRL_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_IPU_PLL_CTRL_REGOFF) |
| #define HWIO_SCU_IPU_PLL_CTRL_RSVD0_FLDMASK (0xfffe0000) |
| #define HWIO_SCU_IPU_PLL_CTRL_RSVD0_FLDSHFT (17) |
| #define HWIO_SCU_IPU_PLL_CTRL_FRZ_PLL_IN_FLDMASK (0x10000) |
| #define HWIO_SCU_IPU_PLL_CTRL_FRZ_PLL_IN_FLDSHFT (16) |
| #define HWIO_SCU_IPU_PLL_CTRL_RSVD1_FLDMASK (0xff80) |
| #define HWIO_SCU_IPU_PLL_CTRL_RSVD1_FLDSHFT (7) |
| #define HWIO_SCU_IPU_PLL_CTRL_PD_FLDMASK (0x40) |
| #define HWIO_SCU_IPU_PLL_CTRL_PD_FLDSHFT (6) |
| #define HWIO_SCU_IPU_PLL_CTRL_FOUTPOSTDIVPD_FLDMASK (0x20) |
| #define HWIO_SCU_IPU_PLL_CTRL_FOUTPOSTDIVPD_FLDSHFT (5) |
| #define HWIO_SCU_IPU_PLL_CTRL_FOUT4PHASEPD_FLDMASK (0x10) |
| #define HWIO_SCU_IPU_PLL_CTRL_FOUT4PHASEPD_FLDSHFT (4) |
| #define HWIO_SCU_IPU_PLL_CTRL_FOUTVCOPD_FLDMASK (0x8) |
| #define HWIO_SCU_IPU_PLL_CTRL_FOUTVCOPD_FLDSHFT (3) |
| #define HWIO_SCU_IPU_PLL_CTRL_DSMPD_FLDMASK (0x4) |
| #define HWIO_SCU_IPU_PLL_CTRL_DSMPD_FLDSHFT (2) |
| #define HWIO_SCU_IPU_PLL_CTRL_DACPD_FLDMASK (0x2) |
| #define HWIO_SCU_IPU_PLL_CTRL_DACPD_FLDSHFT (1) |
| #define HWIO_SCU_IPU_PLL_CTRL_BYPASS_FLDMASK (0x1) |
| #define HWIO_SCU_IPU_PLL_CTRL_BYPASS_FLDSHFT (0) |
| |
| #define HWIO_SCU_IPU_PLL_STS_REGOFF 0x1CC |
| #define HWIO_SCU_IPU_PLL_STS_ADDR(bAddr, regX) \ |
| (bAddr + HWIO_SCU_IPU_PLL_STS_REGOFF) |
| #define HWIO_SCU_IPU_PLL_STS_RSVD0_FLDMASK (0xfffffffe) |
| #define HWIO_SCU_IPU_PLL_STS_RSVD0_FLDSHFT (1) |
| #define HWIO_SCU_IPU_PLL_STS_LOCK_FLDMASK (0x1) |
| #define HWIO_SCU_IPU_PLL_STS_LOCK_FLDSHFT (0) |
| |
| |
| #define HWIO_SCU_PIN_CFG_REGNUM 55 |
| #define HWIO_SCU_PIN_CFG_REGOFF 0x200 |
| #define HWIO_SCU_PIN_CFG_ADDR(bAddr, regX) \ |
| (((regX >= 0) && (regX < HWIO_SCU_PIN_CFG_REGNUM)) ? \ |
| (bAddr + HWIO_SCU_PIN_CFG_REGOFF + (regX * 4)) : 0x0) |
| #define HWIO_SCU_PIN_CFG_RSVD0_FLDMASK (0xfffff800) |
| #define HWIO_SCU_PIN_CFG_RSVD0_FLDSHFT (11) |
| #define HWIO_SCU_PIN_CFG_PIN_SL_FLDMASK (0x400) |
| #define HWIO_SCU_PIN_CFG_PIN_SL_FLDSHFT (10) |
| #define HWIO_SCU_PIN_CFG_PIN_ST_FLDMASK (0x300) |
| #define HWIO_SCU_PIN_CFG_PIN_ST_FLDSHFT (8) |
| #define HWIO_SCU_PIN_CFG_PIN_DS_FLDMASK (0xc0) |
| #define HWIO_SCU_PIN_CFG_PIN_DS_FLDSHFT (6) |
| #define HWIO_SCU_PIN_CFG_PIN_HE_FLDMASK (0x20) |
| #define HWIO_SCU_PIN_CFG_PIN_HE_FLDSHFT (5) |
| #define HWIO_SCU_PIN_CFG_PIN_IE_FLDMASK (0x10) |
| #define HWIO_SCU_PIN_CFG_PIN_IE_FLDSHFT (4) |
| #define HWIO_SCU_PIN_CFG_PIN_PE_FLDMASK (0x8) |
| #define HWIO_SCU_PIN_CFG_PIN_PE_FLDSHFT (3) |
| #define HWIO_SCU_PIN_CFG_PIN_PS_FLDMASK (0x4) |
| #define HWIO_SCU_PIN_CFG_PIN_PS_FLDSHFT (2) |
| #define HWIO_SCU_PIN_CFG_PIN_MUXSEL_FLDMASK (0x3) |
| #define HWIO_SCU_PIN_CFG_PIN_MUXSEL_FLDSHFT (0) |
| |
| #endif /* __MNH_HWIO_SCU_ */ |
