| /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| &soc { |
| |
| replicator_qdss: replicator@6046000 { |
| compatible = "arm,coresight-replicator"; |
| |
| coresight-name = "coresight-replicator"; |
| |
| ports{ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| replicator_out_tmc_etr: endpoint { |
| remote-endpoint= |
| <&tmc_etr_in_replicator>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <0>; |
| replicator_in_tmc_etf: endpoint { |
| slave-mode; |
| remote-endpoint= |
| <&tmc_etf_out_replicator>; |
| }; |
| }; |
| }; |
| }; |
| |
| tmc_etr:tmc@6048000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b961>; |
| |
| reg = <0x6048000 0x1000>, |
| <0x6064000 0x15000>; |
| reg-names = "tmc-base", "bam-base"; |
| |
| arm,buffer-size = <0x400000>; |
| |
| coresight-name = "coresight-tmc-etr"; |
| coresight-ctis = <&cti0 &cti8>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| port { |
| tmc_etr_in_replicator: endpoint { |
| slave-mode; |
| remote-endpoint = <&replicator_out_tmc_etr>; |
| }; |
| }; |
| }; |
| |
| tmc_etf:tmc@6047000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b961>; |
| |
| reg = <0x6047000 0x1000>; |
| reg-names = "tmc-base"; |
| |
| coresight-name = "coresight-tmc-etf"; |
| coresight-ctis = <&cti0 &cti8>; |
| arm,default-sink; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| tmc_etf_out_replicator: endpoint { |
| remote-endpoint = |
| <&replicator_in_tmc_etf>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| tmc_etf_in_funnel_merg: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_merg_out_tmc_etf>; |
| }; |
| }; |
| }; |
| |
| }; |
| |
| stm: stm@6002000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b962>; |
| |
| reg = <0x6002000 0x1000>, |
| <0x16280000 0x180000>; |
| reg-names = "stm-base", "stm-stimulus-base"; |
| |
| coresight-name = "coresight-stm"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| port { |
| stm_out_funnel_in0: endpoint { |
| remote-endpoint = <&funnel_in0_in_stm>; |
| }; |
| }; |
| |
| }; |
| |
| funnel_in0: funnel@0x6041000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b908>; |
| |
| reg = <0x6041000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-in0"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_in0_out_funnel_merg: endpoint { |
| remote-endpoint = |
| <&funnel_merg_in_funnel_in0>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <7>; |
| funnel_in0_in_stm: endpoint { |
| slave-mode; |
| remote-endpoint = <&stm_out_funnel_in0>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel_merg:funnel@6045000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x0003b908>; |
| |
| reg = <0x6045000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel-merg"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "apb_pclk", "core_a_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel_merg_out_tmc_etf: endpoint { |
| remote-endpoint = |
| <&tmc_etf_in_funnel_merg>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <0>; |
| funnel_merg_in_funnel_in0: endpoint { |
| slave-mode; |
| remote-endpoint = |
| <&funnel_in0_out_funnel_merg>; |
| }; |
| }; |
| }; |
| }; |
| |
| cti0: cti@6010000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6010000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti0"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti1: cti@6011000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6011000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti1"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti2: cti@6012000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6012000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti2"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti3: cti@6013000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6013000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti3"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti4: cti@6014000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6014000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti4"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti5: cti@6015000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6015000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti5"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti6: cti@6016000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6016000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti6"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti7: cti@6017000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6017000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti7"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti8: cti@6018000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6018000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti8"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti9: cti@6019000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x6019000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti9"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti10: cti@601a000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x601a000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti10"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti11: cti@601b000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x601b000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti11"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti12: cti@601c000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x601c000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti12"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti13: cti@601d000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x601d000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti13"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti14: cti@601e000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x601e000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti14"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti15: cti@601f000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x601f000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti15"; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti_cpu0: cti@7420000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x7420000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu0"; |
| cpu = <&CPU0>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti_cpu1: cti@7520000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x7520000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu1"; |
| cpu = <&CPU1>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti_cpu2: cti@7620000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x7620000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu2"; |
| cpu = <&CPU2>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti_cpu3: cti@7720000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x7720000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu3"; |
| cpu = <&CPU3>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti_cpu4: cti@7020000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x7020000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu4"; |
| cpu = <&CPU4>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti_cpu5: cti@7120000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x7120000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu5"; |
| cpu = <&CPU5>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti_cpu6: cti@7220000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x7220000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu6"; |
| cpu = <&CPU6>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| |
| cti_cpu7: cti@7320000 { |
| compatible = "arm,coresight-cti"; |
| reg = <0x7320000 0x1000>; |
| reg-names = "cti-base"; |
| |
| coresight-name = "coresight-cti-cpu7"; |
| cpu = <&CPU7>; |
| |
| clocks = <&clock_gcc RPMH_QDSS_CLK>, |
| <&clock_gcc RPMH_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| }; |
| }; |
