| |
| /* |
| * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #ifndef __MDSS_10NM_PLL_CLK_H |
| #define __MDSS_10NM_PLL_CLK_H |
| |
| /* DSI PLL clocks */ |
| #define VCO_CLK_0 0 |
| #define PLL_OUT_DIV_0_CLK 1 |
| #define BITCLK_SRC_0_CLK 2 |
| #define BYTECLK_SRC_0_CLK 3 |
| #define POST_BIT_DIV_0_CLK 4 |
| #define POST_VCO_DIV_0_CLK 5 |
| #define BYTECLK_MUX_0_CLK 6 |
| #define PCLK_SRC_MUX_0_CLK 7 |
| #define PCLK_SRC_0_CLK 8 |
| #define PCLK_MUX_0_CLK 9 |
| #define VCO_CLK_1 10 |
| #define PLL_OUT_DIV_1_CLK 11 |
| #define BITCLK_SRC_1_CLK 12 |
| #define BYTECLK_SRC_1_CLK 13 |
| #define POST_BIT_DIV_1_CLK 14 |
| #define POST_VCO_DIV_1_CLK 15 |
| #define BYTECLK_MUX_1_CLK 16 |
| #define PCLK_SRC_MUX_1_CLK 17 |
| #define PCLK_SRC_1_CLK 18 |
| #define PCLK_MUX_1_CLK 19 |
| |
| /* DP PLL clocks */ |
| #define DP_VCO_CLK 0 |
| #define DP_LINK_CLK_DIVSEL_TEN 1 |
| #define DP_VCO_DIVIDED_TWO_CLK_SRC 2 |
| #define DP_VCO_DIVIDED_FOUR_CLK_SRC 3 |
| #define DP_VCO_DIVIDED_SIX_CLK_SRC 4 |
| #define DP_VCO_DIVIDED_CLK_SRC_MUX 5 |
| #endif |
