| /* auto generated: Friday, August 26th, 2016 11:42:18am */ |
| /* |
| * Copyright (c) 2016, Intel Corporation. All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are met: |
| * |
| * Redistributions of source code must retain the above copyright notice, this |
| * list of conditions and the following disclaimer. |
| * |
| * Redistributions in binary form must reproduce the above copyright notice, |
| * this list of conditions and the following disclaimer in the documentation |
| * and/or other materials provided with the distribution. |
| * |
| * Neither the name of Intel nor the names of its contributors may be used |
| * to endorse or promote products derived from this software without specific |
| * prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| * POSSIBILITY OF SUCH DAMAGE. |
| */ |
| #ifndef __MNH_HWIO_DDR_PHY_ |
| #define __MNH_HWIO_DDR_PHY_ |
| |
| #define HWIO_DDR_PHY_00_REGOFF 0x0 |
| #define HWIO_DDR_PHY_00_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_00_REGOFF) |
| #define HWIO_DDR_PHY_00_PHY_DQ_DM_SWIZZLE0_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_00_PHY_DQ_DM_SWIZZLE0_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_01_REGOFF 0x4 |
| #define HWIO_DDR_PHY_01_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_01_REGOFF) |
| #define HWIO_DDR_PHY_01_PHY_DQ_DM_SWIZZLE1_0_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_01_PHY_DQ_DM_SWIZZLE1_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_01_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_01_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_01_PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_01_PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_01_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_01_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_01_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_01_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_02_REGOFF 0x8 |
| #define HWIO_DDR_PHY_02_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_02_REGOFF) |
| #define HWIO_DDR_PHY_02_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_02_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_02_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_02_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_02_PHY_BYPASS_TWO_CYC_PREAMBLE_0_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_02_PHY_BYPASS_TWO_CYC_PREAMBLE_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_02_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_02_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_02_PHY_CLK_BYPASS_OVERRIDE_0_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_02_PHY_CLK_BYPASS_OVERRIDE_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_02_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_02_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_03_REGOFF 0xc |
| #define HWIO_DDR_PHY_03_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_03_REGOFF) |
| #define HWIO_DDR_PHY_03_PHY_SW_WRDQ0_SHIFT_0_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_03_PHY_SW_WRDQ0_SHIFT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_03_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_03_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_03_PHY_SW_WRDQ1_SHIFT_0_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_03_PHY_SW_WRDQ1_SHIFT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_03_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_03_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_03_PHY_SW_WRDQ2_SHIFT_0_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_03_PHY_SW_WRDQ2_SHIFT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_03_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_03_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_03_PHY_SW_WRDQ3_SHIFT_0_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_03_PHY_SW_WRDQ3_SHIFT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_03_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_03_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_04_REGOFF 0x10 |
| #define HWIO_DDR_PHY_04_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_04_REGOFF) |
| #define HWIO_DDR_PHY_04_PHY_SW_WRDQ4_SHIFT_0_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_04_PHY_SW_WRDQ4_SHIFT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_04_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_04_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_04_PHY_SW_WRDQ5_SHIFT_0_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_04_PHY_SW_WRDQ5_SHIFT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_04_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_04_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_04_PHY_SW_WRDQ6_SHIFT_0_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_04_PHY_SW_WRDQ6_SHIFT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_04_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_04_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_04_PHY_SW_WRDQ7_SHIFT_0_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_04_PHY_SW_WRDQ7_SHIFT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_04_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_04_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_05_REGOFF 0x14 |
| #define HWIO_DDR_PHY_05_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_05_REGOFF) |
| #define HWIO_DDR_PHY_05_PHY_SW_WRDM_SHIFT_0_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_05_PHY_SW_WRDM_SHIFT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_05_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_05_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_05_PHY_SW_WRDQS_SHIFT_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_05_PHY_SW_WRDQS_SHIFT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_05_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_05_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_05_PHY_DQ_TSEL_ENABLE_0_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_05_PHY_DQ_TSEL_ENABLE_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_05_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_05_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_05_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_05_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_06_REGOFF 0x18 |
| #define HWIO_DDR_PHY_06_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_06_REGOFF) |
| #define HWIO_DDR_PHY_06_PHY_DQ_TSEL_SELECT_0_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_06_PHY_DQ_TSEL_SELECT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_06_PHY_DQS_TSEL_ENABLE_0_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_06_PHY_DQS_TSEL_ENABLE_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_06_RESERVED_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_06_RESERVED_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_07_REGOFF 0x1c |
| #define HWIO_DDR_PHY_07_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_07_REGOFF) |
| #define HWIO_DDR_PHY_07_PHY_DQS_TSEL_SELECT_0_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_07_PHY_DQS_TSEL_SELECT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_07_PHY_TWO_CYC_PREAMBLE_0_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_07_PHY_TWO_CYC_PREAMBLE_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_07_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_07_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_08_REGOFF 0x20 |
| #define HWIO_DDR_PHY_08_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_08_REGOFF) |
| #define HWIO_DDR_PHY_08_PHY_DBI_MODE_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_08_PHY_DBI_MODE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_08_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_08_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_08_PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_08_PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_08_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_08_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_08_PHY_LP4_BOOT_RDDATA_EN_DLY_0_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_08_PHY_LP4_BOOT_RDDATA_EN_DLY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_08_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_08_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_08_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_08_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_08_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_08_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_09_REGOFF 0x24 |
| #define HWIO_DDR_PHY_09_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_09_REGOFF) |
| #define HWIO_DDR_PHY_09_PHY_LP4_BOOT_RPTR_UPDATE_0_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_09_PHY_LP4_BOOT_RPTR_UPDATE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_09_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_09_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_09_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_09_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_09_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_09_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_09_PHY_LPBK_CONTROL_0_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_09_PHY_LPBK_CONTROL_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_09_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_09_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_10_REGOFF 0x28 |
| #define HWIO_DDR_PHY_10_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_10_REGOFF) |
| #define HWIO_DDR_PHY_10_PHY_LPBK_DFX_TIMEOUT_EN_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_10_PHY_LPBK_DFX_TIMEOUT_EN_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_10_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_10_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_10_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_10_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_11_REGOFF 0x2c |
| #define HWIO_DDR_PHY_11_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_11_REGOFF) |
| #define HWIO_DDR_PHY_11_PHY_AUTO_TIMING_MARGIN_CONTROL_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_11_PHY_AUTO_TIMING_MARGIN_CONTROL_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_12_REGOFF 0x30 |
| #define HWIO_DDR_PHY_12_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_12_REGOFF) |
| #define HWIO_DDR_PHY_12_PHY_AUTO_TIMING_MARGIN_OBS_0_FLDMASK (0xfffffff) |
| #define HWIO_DDR_PHY_12_PHY_AUTO_TIMING_MARGIN_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_12_RESERVED_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_12_RESERVED_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_13_REGOFF 0x34 |
| #define HWIO_DDR_PHY_13_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_13_REGOFF) |
| #define HWIO_DDR_PHY_13_PHY_SLICE_PWR_RDC_DISABLE_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_13_PHY_SLICE_PWR_RDC_DISABLE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_13_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_13_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_13_PHY_PRBS_PATTERN_START_0_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_13_PHY_PRBS_PATTERN_START_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_13_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_13_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_13_PHY_PRBS_PATTERN_MASK_0_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_13_PHY_PRBS_PATTERN_MASK_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_13_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_13_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_14_REGOFF 0x38 |
| #define HWIO_DDR_PHY_14_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_14_REGOFF) |
| #define HWIO_DDR_PHY_14_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_14_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_14_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_14_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_14_PHY_GATE_ERROR_DELAY_SELECT_0_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_14_PHY_GATE_ERROR_DELAY_SELECT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_14_RESERVED1_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_14_RESERVED1_FLDSHFT (21) |
| #define HWIO_DDR_PHY_14_SC_PHY_SNAP_OBS_REGS_0_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_14_SC_PHY_SNAP_OBS_REGS_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_14_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_14_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_15_REGOFF 0x3c |
| #define HWIO_DDR_PHY_15_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_15_REGOFF) |
| #define HWIO_DDR_PHY_15_PHY_GATE_SMPL1_SLAVE_DELAY_0_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_15_PHY_GATE_SMPL1_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_15_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_15_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_15_PHY_LPDDR_0_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_15_PHY_LPDDR_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_15_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_15_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_15_PHY_LPDDR_TYPE_0_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_15_PHY_LPDDR_TYPE_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_15_RESERVED2_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_15_RESERVED2_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_16_REGOFF 0x40 |
| #define HWIO_DDR_PHY_16_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_16_REGOFF) |
| #define HWIO_DDR_PHY_16_PHY_GATE_SMPL2_SLAVE_DELAY_0_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_16_PHY_GATE_SMPL2_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_16_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_16_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_16_ON_FLY_GATE_ADJUST_EN_0_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_16_ON_FLY_GATE_ADJUST_EN_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_16_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_16_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_16_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_16_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_17_REGOFF 0x44 |
| #define HWIO_DDR_PHY_17_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_17_REGOFF) |
| #define HWIO_DDR_PHY_17_PHY_GATE_TRACKING_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_17_PHY_GATE_TRACKING_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_18_REGOFF 0x48 |
| #define HWIO_DDR_PHY_18_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_18_REGOFF) |
| #define HWIO_DDR_PHY_18_PHY_LP4_PST_AMBLE_0_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_18_PHY_LP4_PST_AMBLE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_18_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_18_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_18_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_18_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_19_REGOFF 0x4c |
| #define HWIO_DDR_PHY_19_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_19_REGOFF) |
| #define HWIO_DDR_PHY_19_PHY_LP4_RDLVL_PATT8_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_19_PHY_LP4_RDLVL_PATT8_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_20_REGOFF 0x50 |
| #define HWIO_DDR_PHY_20_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_20_REGOFF) |
| #define HWIO_DDR_PHY_20_PHY_LP4_RDLVL_PATT9_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_20_PHY_LP4_RDLVL_PATT9_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_21_REGOFF 0x54 |
| #define HWIO_DDR_PHY_21_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_21_REGOFF) |
| #define HWIO_DDR_PHY_21_PHY_LP4_RDLVL_PATT10_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_21_PHY_LP4_RDLVL_PATT10_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_22_REGOFF 0x58 |
| #define HWIO_DDR_PHY_22_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_22_REGOFF) |
| #define HWIO_DDR_PHY_22_PHY_LP4_RDLVL_PATT11_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_22_PHY_LP4_RDLVL_PATT11_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_23_REGOFF 0x5c |
| #define HWIO_DDR_PHY_23_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_23_REGOFF) |
| #define HWIO_DDR_PHY_23_PHY_SLAVE_LOOP_CNT_UPDATE_0_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_23_PHY_SLAVE_LOOP_CNT_UPDATE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_23_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_23_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_23_PHY_SW_FIFO_PTR_RST_DISABLE_0_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_23_PHY_SW_FIFO_PTR_RST_DISABLE_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_23_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_23_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_23_PHY_MASTER_DLY_LOCK_OBS_SELECT_0_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_23_PHY_MASTER_DLY_LOCK_OBS_SELECT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_23_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_23_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_23_PHY_RDDQ_ENC_OBS_SELECT_0_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_23_PHY_RDDQ_ENC_OBS_SELECT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_23_RESERVED3_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_23_RESERVED3_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_24_REGOFF 0x60 |
| #define HWIO_DDR_PHY_24_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_24_REGOFF) |
| #define HWIO_DDR_PHY_24_PHY_RDDQS_DQ_ENC_OBS_SELECT_0_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_24_PHY_RDDQS_DQ_ENC_OBS_SELECT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_24_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_24_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_24_PHY_WR_ENC_OBS_SELECT_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_24_PHY_WR_ENC_OBS_SELECT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_24_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_24_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_24_PHY_WR_SHIFT_OBS_SELECT_0_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_24_PHY_WR_SHIFT_OBS_SELECT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_24_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_24_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_24_PHY_FIFO_PTR_OBS_SELECT_0_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_24_PHY_FIFO_PTR_OBS_SELECT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_24_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_24_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_25_REGOFF 0x64 |
| #define HWIO_DDR_PHY_25_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_25_REGOFF) |
| #define HWIO_DDR_PHY_25_PHY_LVL_DEBUG_MODE_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_25_PHY_LVL_DEBUG_MODE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_25_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_25_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_25_SC_PHY_LVL_DEBUG_CONT_0_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_25_SC_PHY_LVL_DEBUG_CONT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_25_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_25_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_25_PHY_WRLVL_CAPTURE_CNT_0_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_25_PHY_WRLVL_CAPTURE_CNT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_25_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_25_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_25_PHY_WRLVL_UPDT_WAIT_CNT_0_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_25_PHY_WRLVL_UPDT_WAIT_CNT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_25_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_25_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_26_REGOFF 0x68 |
| #define HWIO_DDR_PHY_26_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_26_REGOFF) |
| #define HWIO_DDR_PHY_26_PHY_GTLVL_CAPTURE_CNT_0_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_26_PHY_GTLVL_CAPTURE_CNT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_26_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_26_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_26_PHY_GTLVL_UPDT_WAIT_CNT_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_26_PHY_GTLVL_UPDT_WAIT_CNT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_26_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_26_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_26_PHY_RDLVL_CAPTURE_CNT_0_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_26_PHY_RDLVL_CAPTURE_CNT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_26_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_26_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_26_PHY_RDLVL_UPDT_WAIT_CNT_0_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_26_PHY_RDLVL_UPDT_WAIT_CNT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_26_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_26_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_27_REGOFF 0x6c |
| #define HWIO_DDR_PHY_27_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_27_REGOFF) |
| #define HWIO_DDR_PHY_27_PHY_RDLVL_OP_MODE_0_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_27_PHY_RDLVL_OP_MODE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_27_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_27_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_27_PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_27_PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_27_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_27_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_27_PHY_RDLVL_DATA_MASK_0_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_27_PHY_RDLVL_DATA_MASK_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_27_PHY_WDQLVL_BURST_CNT_0_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_27_PHY_WDQLVL_BURST_CNT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_27_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_27_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_28_REGOFF 0x70 |
| #define HWIO_DDR_PHY_28_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_28_REGOFF) |
| #define HWIO_DDR_PHY_28_PHY_WDQLVL_PATT_0_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_28_PHY_WDQLVL_PATT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_28_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_28_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_28_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_28_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_28_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_28_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_28_PHY_WDQLVL_UPDT_WAIT_CNT_0_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_28_PHY_WDQLVL_UPDT_WAIT_CNT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_28_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_28_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_29_REGOFF 0x74 |
| #define HWIO_DDR_PHY_29_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_29_REGOFF) |
| #define HWIO_DDR_PHY_29_PHY_WDQLVL_DQDM_OBS_SELECT_0_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_29_PHY_WDQLVL_DQDM_OBS_SELECT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_29_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_29_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_29_PHY_WDQLVL_QTR_DLY_STEP_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_29_PHY_WDQLVL_QTR_DLY_STEP_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_29_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_29_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_29_SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_29_SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_29_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_29_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_29_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_29_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_30_REGOFF 0x78 |
| #define HWIO_DDR_PHY_30_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_30_REGOFF) |
| #define HWIO_DDR_PHY_30_PHY_WDQLVL_DATADM_MASK_0_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_30_PHY_WDQLVL_DATADM_MASK_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_30_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_30_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_30_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_30_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_31_REGOFF 0x7c |
| #define HWIO_DDR_PHY_31_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_31_REGOFF) |
| #define HWIO_DDR_PHY_31_PHY_USER_PATT0_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_31_PHY_USER_PATT0_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_32_REGOFF 0x80 |
| #define HWIO_DDR_PHY_32_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_32_REGOFF) |
| #define HWIO_DDR_PHY_32_PHY_USER_PATT1_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_32_PHY_USER_PATT1_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_33_REGOFF 0x84 |
| #define HWIO_DDR_PHY_33_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_33_REGOFF) |
| #define HWIO_DDR_PHY_33_PHY_USER_PATT2_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_33_PHY_USER_PATT2_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_34_REGOFF 0x88 |
| #define HWIO_DDR_PHY_34_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_34_REGOFF) |
| #define HWIO_DDR_PHY_34_PHY_USER_PATT3_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_34_PHY_USER_PATT3_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_35_REGOFF 0x8c |
| #define HWIO_DDR_PHY_35_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_35_REGOFF) |
| #define HWIO_DDR_PHY_35_PHY_USER_PATT4_0_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_35_PHY_USER_PATT4_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_35_PHY_CALVL_VREF_DRIVING_SLICE_0_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_35_PHY_CALVL_VREF_DRIVING_SLICE_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_35_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_35_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_35_SC_PHY_MANUAL_CLEAR_0_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_35_SC_PHY_MANUAL_CLEAR_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_35_RESERVED1_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_35_RESERVED1_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_36_REGOFF 0x90 |
| #define HWIO_DDR_PHY_36_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_36_REGOFF) |
| #define HWIO_DDR_PHY_36_PHY_FIFO_PTR_OBS_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_36_PHY_FIFO_PTR_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_36_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_36_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_37_REGOFF 0x94 |
| #define HWIO_DDR_PHY_37_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_37_REGOFF) |
| #define HWIO_DDR_PHY_37_PHY_LPBK_RESULT_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_37_PHY_LPBK_RESULT_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_38_REGOFF 0x98 |
| #define HWIO_DDR_PHY_38_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_38_REGOFF) |
| #define HWIO_DDR_PHY_38_PHY_LPBK_ERROR_COUNT_OBS_0_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_38_PHY_LPBK_ERROR_COUNT_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_38_PHY_MASTER_DLY_LOCK_OBS_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_38_PHY_MASTER_DLY_LOCK_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_38_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_38_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_39_REGOFF 0x9c |
| #define HWIO_DDR_PHY_39_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_39_REGOFF) |
| #define HWIO_DDR_PHY_39_PHY_RDDQ_SLV_DLY_ENC_OBS_0_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_39_PHY_RDDQ_SLV_DLY_ENC_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_39_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_39_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_39_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_39_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_39_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_39_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_39_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_FLDMASK \ |
| (0xff0000) |
| #define HWIO_DDR_PHY_39_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_39_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_FLDMASK \ |
| (0xff000000) |
| #define HWIO_DDR_PHY_39_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_40_REGOFF 0xa0 |
| #define HWIO_DDR_PHY_40_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_40_REGOFF) |
| #define HWIO_DDR_PHY_40_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_40_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_40_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_40_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_40_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_FLDMASK (0x7f0000) |
| #define HWIO_DDR_PHY_40_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_40_RESERVED1_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_40_RESERVED1_FLDSHFT (23) |
| #define HWIO_DDR_PHY_40_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_40_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_41_REGOFF 0xa4 |
| #define HWIO_DDR_PHY_41_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_41_REGOFF) |
| #define HWIO_DDR_PHY_41_PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_41_PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_41_PHY_WR_SHIFT_OBS_0_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_41_PHY_WR_SHIFT_OBS_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_41_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_41_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_41_PHY_WRLVL_HARD0_DELAY_OBS_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_41_PHY_WRLVL_HARD0_DELAY_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_41_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_41_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_42_REGOFF 0xa8 |
| #define HWIO_DDR_PHY_42_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_42_REGOFF) |
| #define HWIO_DDR_PHY_42_PHY_WRLVL_HARD1_DELAY_OBS_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_42_PHY_WRLVL_HARD1_DELAY_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_42_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_42_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_42_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_42_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_43_REGOFF 0xac |
| #define HWIO_DDR_PHY_43_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_43_REGOFF) |
| #define HWIO_DDR_PHY_43_PHY_WRLVL_STATUS_OBS_0_FLDMASK (0x1ffff) |
| #define HWIO_DDR_PHY_43_PHY_WRLVL_STATUS_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_43_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_43_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_43_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_43_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_44_REGOFF 0xb0 |
| #define HWIO_DDR_PHY_44_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_44_REGOFF) |
| #define HWIO_DDR_PHY_44_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_44_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_44_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_44_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_44_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_44_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_44_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_44_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_45_REGOFF 0xb4 |
| #define HWIO_DDR_PHY_45_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_45_REGOFF) |
| #define HWIO_DDR_PHY_45_PHY_GTLVL_HARD0_DELAY_OBS_0_FLDMASK (0x3fff) |
| #define HWIO_DDR_PHY_45_PHY_GTLVL_HARD0_DELAY_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_45_RESERVED_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_45_RESERVED_FLDSHFT (14) |
| #define HWIO_DDR_PHY_45_PHY_GTLVL_HARD1_DELAY_OBS_0_FLDMASK (0x3fff0000) |
| #define HWIO_DDR_PHY_45_PHY_GTLVL_HARD1_DELAY_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_45_RESERVED1_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_45_RESERVED1_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_46_REGOFF 0xb8 |
| #define HWIO_DDR_PHY_46_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_46_REGOFF) |
| #define HWIO_DDR_PHY_46_PHY_GTLVL_STATUS_OBS_0_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_46_PHY_GTLVL_STATUS_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_46_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_46_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_46_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_46_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_47_REGOFF 0xbc |
| #define HWIO_DDR_PHY_47_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_47_REGOFF) |
| #define HWIO_DDR_PHY_47_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_47_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_47_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_47_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_47_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_47_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_47_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_47_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_48_REGOFF 0xc0 |
| #define HWIO_DDR_PHY_48_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_48_REGOFF) |
| #define HWIO_DDR_PHY_48_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_48_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_48_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_48_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_48_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_48_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_49_REGOFF 0xc4 |
| #define HWIO_DDR_PHY_49_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_49_REGOFF) |
| #define HWIO_DDR_PHY_49_PHY_RDLVL_STATUS_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_49_PHY_RDLVL_STATUS_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_50_REGOFF 0xc8 |
| #define HWIO_DDR_PHY_50_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_50_REGOFF) |
| #define HWIO_DDR_PHY_50_PHY_WDQLVL_DQDM_LE_DLY_OBS_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_50_PHY_WDQLVL_DQDM_LE_DLY_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_50_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_50_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_50_PHY_WDQLVL_DQDM_TE_DLY_OBS_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_50_PHY_WDQLVL_DQDM_TE_DLY_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_50_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_50_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_51_REGOFF 0xcc |
| #define HWIO_DDR_PHY_51_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_51_REGOFF) |
| #define HWIO_DDR_PHY_51_PHY_WDQLVL_STATUS_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_51_PHY_WDQLVL_STATUS_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_52_REGOFF 0xd0 |
| #define HWIO_DDR_PHY_52_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_52_REGOFF) |
| #define HWIO_DDR_PHY_52_PHY_DDL_MODE_0_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_52_PHY_DDL_MODE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_52_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_52_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_52_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_52_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_53_REGOFF 0xd4 |
| #define HWIO_DDR_PHY_53_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_53_REGOFF) |
| #define HWIO_DDR_PHY_53_PHY_DDL_TEST_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_53_PHY_DDL_TEST_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_54_REGOFF 0xd8 |
| #define HWIO_DDR_PHY_54_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_54_REGOFF) |
| #define HWIO_DDR_PHY_54_PHY_DDL_TEST_MSTR_DLY_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_54_PHY_DDL_TEST_MSTR_DLY_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_55_REGOFF 0xdc |
| #define HWIO_DDR_PHY_55_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_55_REGOFF) |
| #define HWIO_DDR_PHY_55_PHY_DDL_TRACK_UPD_THRESHOLD_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_55_PHY_DDL_TRACK_UPD_THRESHOLD_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_55_PHY_LP4_WDQS_OE_EXTEND_0_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_55_PHY_LP4_WDQS_OE_EXTEND_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_55_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_55_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_55_SC_PHY_RX_CAL_START_0_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_55_SC_PHY_RX_CAL_START_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_55_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_55_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_55_PHY_RX_CAL_OVERRIDE_0_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_55_PHY_RX_CAL_OVERRIDE_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_55_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_55_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_56_REGOFF 0xe0 |
| #define HWIO_DDR_PHY_56_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_56_REGOFF) |
| #define HWIO_DDR_PHY_56_PHY_RX_CAL_SAMPLE_WAIT_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_56_PHY_RX_CAL_SAMPLE_WAIT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_56_PHY_RX_CAL_DQ0_0_FLDMASK (0xfff00) |
| #define HWIO_DDR_PHY_56_PHY_RX_CAL_DQ0_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_56_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_56_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_56_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_56_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_57_REGOFF 0xe4 |
| #define HWIO_DDR_PHY_57_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_57_REGOFF) |
| #define HWIO_DDR_PHY_57_PHY_RX_CAL_DQ1_0_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_57_PHY_RX_CAL_DQ1_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_57_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_57_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_57_PHY_RX_CAL_DQ2_0_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_57_PHY_RX_CAL_DQ2_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_57_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_57_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_58_REGOFF 0xe8 |
| #define HWIO_DDR_PHY_58_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_58_REGOFF) |
| #define HWIO_DDR_PHY_58_PHY_RX_CAL_DQ3_0_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_58_PHY_RX_CAL_DQ3_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_58_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_58_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_58_PHY_RX_CAL_DQ4_0_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_58_PHY_RX_CAL_DQ4_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_58_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_58_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_59_REGOFF 0xec |
| #define HWIO_DDR_PHY_59_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_59_REGOFF) |
| #define HWIO_DDR_PHY_59_PHY_RX_CAL_DQ5_0_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_59_PHY_RX_CAL_DQ5_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_59_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_59_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_59_PHY_RX_CAL_DQ6_0_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_59_PHY_RX_CAL_DQ6_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_59_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_59_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_60_REGOFF 0xf0 |
| #define HWIO_DDR_PHY_60_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_60_REGOFF) |
| #define HWIO_DDR_PHY_60_PHY_RX_CAL_DQ7_0_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_60_PHY_RX_CAL_DQ7_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_60_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_60_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_60_PHY_RX_CAL_DM_0_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_60_PHY_RX_CAL_DM_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_60_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_60_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_61_REGOFF 0xf4 |
| #define HWIO_DDR_PHY_61_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_61_REGOFF) |
| #define HWIO_DDR_PHY_61_PHY_RX_CAL_DQS_0_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_61_PHY_RX_CAL_DQS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_61_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_61_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_61_PHY_RX_CAL_FDBK_0_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_61_PHY_RX_CAL_FDBK_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_61_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_61_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_62_REGOFF 0xf8 |
| #define HWIO_DDR_PHY_62_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_62_REGOFF) |
| #define HWIO_DDR_PHY_62_PHY_RX_CAL_OBS_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_62_PHY_RX_CAL_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_62_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_62_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_62_PHY_RX_CAL_LOCK_OBS_0_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_62_PHY_RX_CAL_LOCK_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_62_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_62_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_63_REGOFF 0xfc |
| #define HWIO_DDR_PHY_63_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_63_REGOFF) |
| #define HWIO_DDR_PHY_63_PHY_RX_CAL_DISABLE_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_63_PHY_RX_CAL_DISABLE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_63_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_63_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_63_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_63_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_64_REGOFF 0x100 |
| #define HWIO_DDR_PHY_64_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_64_REGOFF) |
| #define HWIO_DDR_PHY_64_PHY_CLK_WRDQ0_SLAVE_DELAY_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_64_PHY_CLK_WRDQ0_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_64_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_64_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_64_PHY_CLK_WRDQ1_SLAVE_DELAY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_64_PHY_CLK_WRDQ1_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_64_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_64_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_65_REGOFF 0x104 |
| #define HWIO_DDR_PHY_65_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_65_REGOFF) |
| #define HWIO_DDR_PHY_65_PHY_CLK_WRDQ2_SLAVE_DELAY_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_65_PHY_CLK_WRDQ2_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_65_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_65_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_65_PHY_CLK_WRDQ3_SLAVE_DELAY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_65_PHY_CLK_WRDQ3_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_65_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_65_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_66_REGOFF 0x108 |
| #define HWIO_DDR_PHY_66_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_66_REGOFF) |
| #define HWIO_DDR_PHY_66_PHY_CLK_WRDQ4_SLAVE_DELAY_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_66_PHY_CLK_WRDQ4_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_66_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_66_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_66_PHY_CLK_WRDQ5_SLAVE_DELAY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_66_PHY_CLK_WRDQ5_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_66_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_66_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_67_REGOFF 0x10c |
| #define HWIO_DDR_PHY_67_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_67_REGOFF) |
| #define HWIO_DDR_PHY_67_PHY_CLK_WRDQ6_SLAVE_DELAY_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_67_PHY_CLK_WRDQ6_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_67_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_67_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_67_PHY_CLK_WRDQ7_SLAVE_DELAY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_67_PHY_CLK_WRDQ7_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_67_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_67_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_68_REGOFF 0x110 |
| #define HWIO_DDR_PHY_68_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_68_REGOFF) |
| #define HWIO_DDR_PHY_68_PHY_CLK_WRDM_SLAVE_DELAY_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_68_PHY_CLK_WRDM_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_68_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_68_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_68_PHY_CLK_WRDQS_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_68_PHY_CLK_WRDQS_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_68_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_68_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_69_REGOFF 0x114 |
| #define HWIO_DDR_PHY_69_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_69_REGOFF) |
| #define HWIO_DDR_PHY_69_PHY_WRLVL_THRESHOLD_ADJUST_0_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_69_PHY_WRLVL_THRESHOLD_ADJUST_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_69_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_69_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_69_PHY_RDDQ0_SLAVE_DELAY_0_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_69_PHY_RDDQ0_SLAVE_DELAY_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_69_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_69_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_69_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_69_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_70_REGOFF 0x118 |
| #define HWIO_DDR_PHY_70_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_70_REGOFF) |
| #define HWIO_DDR_PHY_70_PHY_RDDQ1_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_70_PHY_RDDQ1_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_70_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_70_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_70_PHY_RDDQ2_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_70_PHY_RDDQ2_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_70_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_70_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_71_REGOFF 0x11c |
| #define HWIO_DDR_PHY_71_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_71_REGOFF) |
| #define HWIO_DDR_PHY_71_PHY_RDDQ3_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_71_PHY_RDDQ3_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_71_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_71_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_71_PHY_RDDQ4_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_71_PHY_RDDQ4_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_71_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_71_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_72_REGOFF 0x120 |
| #define HWIO_DDR_PHY_72_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_72_REGOFF) |
| #define HWIO_DDR_PHY_72_PHY_RDDQ5_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_72_PHY_RDDQ5_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_72_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_72_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_72_PHY_RDDQ6_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_72_PHY_RDDQ6_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_72_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_72_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_73_REGOFF 0x124 |
| #define HWIO_DDR_PHY_73_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_73_REGOFF) |
| #define HWIO_DDR_PHY_73_PHY_RDDQ7_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_73_PHY_RDDQ7_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_73_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_73_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_73_PHY_RDDM_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_73_PHY_RDDM_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_73_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_73_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_74_REGOFF 0x128 |
| #define HWIO_DDR_PHY_74_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_74_REGOFF) |
| #define HWIO_DDR_PHY_74_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_74_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_74_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_74_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_74_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_74_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_74_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_74_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_75_REGOFF 0x12c |
| #define HWIO_DDR_PHY_75_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_75_REGOFF) |
| #define HWIO_DDR_PHY_75_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_75_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_75_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_75_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_75_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_75_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_75_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_75_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_76_REGOFF 0x130 |
| #define HWIO_DDR_PHY_76_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_76_REGOFF) |
| #define HWIO_DDR_PHY_76_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_76_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_76_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_76_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_76_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_76_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_76_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_76_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_77_REGOFF 0x134 |
| #define HWIO_DDR_PHY_77_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_77_REGOFF) |
| #define HWIO_DDR_PHY_77_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_77_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_77_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_77_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_77_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_77_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_77_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_77_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_78_REGOFF 0x138 |
| #define HWIO_DDR_PHY_78_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_78_REGOFF) |
| #define HWIO_DDR_PHY_78_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_78_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_78_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_78_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_78_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_78_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_78_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_78_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_79_REGOFF 0x13c |
| #define HWIO_DDR_PHY_79_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_79_REGOFF) |
| #define HWIO_DDR_PHY_79_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_79_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_79_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_79_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_79_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_79_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_79_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_79_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_80_REGOFF 0x140 |
| #define HWIO_DDR_PHY_80_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_80_REGOFF) |
| #define HWIO_DDR_PHY_80_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_80_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_80_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_80_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_80_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_80_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_80_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_80_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_81_REGOFF 0x144 |
| #define HWIO_DDR_PHY_81_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_81_REGOFF) |
| #define HWIO_DDR_PHY_81_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_81_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_81_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_81_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_81_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_81_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_81_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_81_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_82_REGOFF 0x148 |
| #define HWIO_DDR_PHY_82_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_82_REGOFF) |
| #define HWIO_DDR_PHY_82_PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_82_PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_82_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_82_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_82_PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_82_PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_82_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_82_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_83_REGOFF 0x14c |
| #define HWIO_DDR_PHY_83_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_83_REGOFF) |
| #define HWIO_DDR_PHY_83_PHY_RDDQS_GATE_SLAVE_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_83_PHY_RDDQS_GATE_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_83_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_83_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_83_PHY_RDDQS_LATENCY_ADJUST_0_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_83_PHY_RDDQS_LATENCY_ADJUST_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_83_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_83_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_83_PHY_WRITE_PATH_LAT_ADD_0_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_83_PHY_WRITE_PATH_LAT_ADD_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_83_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_83_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_84_REGOFF 0x150 |
| #define HWIO_DDR_PHY_84_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_84_REGOFF) |
| #define HWIO_DDR_PHY_84_PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_84_PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_84_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_84_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_84_PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_84_PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_84_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_84_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_85_REGOFF 0x154 |
| #define HWIO_DDR_PHY_85_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_85_REGOFF) |
| #define HWIO_DDR_PHY_85_PHY_WRLVL_EARLY_FORCE_0_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_85_PHY_WRLVL_EARLY_FORCE_0_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_85_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_85_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_85_PHY_GTLVL_RDDQS_SLV_DLY_START_0_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_85_PHY_GTLVL_RDDQS_SLV_DLY_START_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_85_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_85_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_85_PHY_GTLVL_LAT_ADJ_START_0_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_85_PHY_GTLVL_LAT_ADJ_START_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_85_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_85_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_86_REGOFF 0x158 |
| #define HWIO_DDR_PHY_86_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_86_REGOFF) |
| #define HWIO_DDR_PHY_86_PHY_WDQLVL_DQDM_SLV_DLY_START_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_86_PHY_WDQLVL_DQDM_SLV_DLY_START_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_86_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_86_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_86_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_86_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_86_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_86_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_87_REGOFF 0x15c |
| #define HWIO_DDR_PHY_87_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_87_REGOFF) |
| #define HWIO_DDR_PHY_87_PHY_FDBK_PWR_CTRL_0_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_87_PHY_FDBK_PWR_CTRL_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_87_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_87_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_87_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_87_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_88_REGOFF 0x160 |
| #define HWIO_DDR_PHY_88_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_88_REGOFF) |
| #define HWIO_DDR_PHY_88_PHY_DQ_OE_TIMING_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_88_PHY_DQ_OE_TIMING_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_88_PHY_DQ_TSEL_RD_TIMING_0_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_88_PHY_DQ_TSEL_RD_TIMING_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_88_PHY_DQ_TSEL_WR_TIMING_0_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_88_PHY_DQ_TSEL_WR_TIMING_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_88_PHY_DQS_OE_TIMING_0_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_88_PHY_DQS_OE_TIMING_0_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_89_REGOFF 0x164 |
| #define HWIO_DDR_PHY_89_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_89_REGOFF) |
| #define HWIO_DDR_PHY_89_PHY_DQS_TSEL_RD_TIMING_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_89_PHY_DQS_TSEL_RD_TIMING_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_89_PHY_DQS_TSEL_WR_TIMING_0_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_89_PHY_DQS_TSEL_WR_TIMING_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_89_PHY_DQ_IE_TIMING_0_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_89_PHY_DQ_IE_TIMING_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_89_PHY_DQS_IE_TIMING_0_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_89_PHY_DQS_IE_TIMING_0_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_90_REGOFF 0x168 |
| #define HWIO_DDR_PHY_90_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_90_REGOFF) |
| #define HWIO_DDR_PHY_90_PHY_RDDATA_EN_IE_DLY_0_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_90_PHY_RDDATA_EN_IE_DLY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_90_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_90_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_90_PHY_IE_MODE_0_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_90_PHY_IE_MODE_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_90_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_90_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_90_PHY_RDDATA_EN_DLY_0_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_90_PHY_RDDATA_EN_DLY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_90_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_90_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_90_PHY_RDDATA_EN_TSEL_DLY_0_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_90_PHY_RDDATA_EN_TSEL_DLY_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_90_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_90_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_91_REGOFF 0x16c |
| #define HWIO_DDR_PHY_91_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_91_REGOFF) |
| #define HWIO_DDR_PHY_91_PHY_SW_MASTER_MODE_0_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_91_PHY_SW_MASTER_MODE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_91_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_91_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_91_PHY_MASTER_DELAY_START_0_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_91_PHY_MASTER_DELAY_START_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_91_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_91_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_91_PHY_MASTER_DELAY_STEP_0_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_91_PHY_MASTER_DELAY_STEP_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_91_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_91_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_92_REGOFF 0x170 |
| #define HWIO_DDR_PHY_92_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_92_REGOFF) |
| #define HWIO_DDR_PHY_92_PHY_MASTER_DELAY_WAIT_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_92_PHY_MASTER_DELAY_WAIT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_92_PHY_MASTER_DELAY_HALF_MEASURE_0_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_92_PHY_MASTER_DELAY_HALF_MEASURE_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_92_PHY_RPTR_UPDATE_0_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_92_PHY_RPTR_UPDATE_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_92_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_92_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_92_PHY_WRLVL_DLY_STEP_0_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_92_PHY_WRLVL_DLY_STEP_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_92_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_92_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_93_REGOFF 0x174 |
| #define HWIO_DDR_PHY_93_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_93_REGOFF) |
| #define HWIO_DDR_PHY_93_PHY_WRLVL_RESP_WAIT_CNT_0_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_93_PHY_WRLVL_RESP_WAIT_CNT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_93_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_93_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_93_PHY_GTLVL_DLY_STEP_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_93_PHY_GTLVL_DLY_STEP_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_93_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_93_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_93_PHY_GTLVL_RESP_WAIT_CNT_0_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_93_PHY_GTLVL_RESP_WAIT_CNT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_93_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_93_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_93_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_93_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_94_REGOFF 0x178 |
| #define HWIO_DDR_PHY_94_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_94_REGOFF) |
| #define HWIO_DDR_PHY_94_PHY_GTLVL_BACK_STEP_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_94_PHY_GTLVL_BACK_STEP_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_94_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_94_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_94_PHY_GTLVL_FINAL_STEP_0_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_94_PHY_GTLVL_FINAL_STEP_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_94_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_94_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_95_REGOFF 0x17c |
| #define HWIO_DDR_PHY_95_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_95_REGOFF) |
| #define HWIO_DDR_PHY_95_PHY_WDQLVL_DLY_STEP_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_95_PHY_WDQLVL_DLY_STEP_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_95_PHY_RDLVL_DLY_STEP_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_95_PHY_RDLVL_DLY_STEP_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_95_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_95_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_95_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_95_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_96_REGOFF 0x180 |
| #define HWIO_DDR_PHY_96_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_96_REGOFF) |
| #define HWIO_DDR_PHY_96_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_96_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_97_REGOFF 0x184 |
| #define HWIO_DDR_PHY_97_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_97_REGOFF) |
| #define HWIO_DDR_PHY_97_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_97_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_98_REGOFF 0x188 |
| #define HWIO_DDR_PHY_98_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_98_REGOFF) |
| #define HWIO_DDR_PHY_98_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_98_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_99_REGOFF 0x18c |
| #define HWIO_DDR_PHY_99_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_99_REGOFF) |
| #define HWIO_DDR_PHY_99_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_99_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_100_REGOFF 0x190 |
| #define HWIO_DDR_PHY_100_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_100_REGOFF) |
| #define HWIO_DDR_PHY_100_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_100_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_101_REGOFF 0x194 |
| #define HWIO_DDR_PHY_101_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_101_REGOFF) |
| #define HWIO_DDR_PHY_101_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_101_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_102_REGOFF 0x198 |
| #define HWIO_DDR_PHY_102_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_102_REGOFF) |
| #define HWIO_DDR_PHY_102_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_102_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_103_REGOFF 0x19c |
| #define HWIO_DDR_PHY_103_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_103_REGOFF) |
| #define HWIO_DDR_PHY_103_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_103_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_104_REGOFF 0x1a0 |
| #define HWIO_DDR_PHY_104_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_104_REGOFF) |
| #define HWIO_DDR_PHY_104_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_104_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_105_REGOFF 0x1a4 |
| #define HWIO_DDR_PHY_105_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_105_REGOFF) |
| #define HWIO_DDR_PHY_105_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_105_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_106_REGOFF 0x1a8 |
| #define HWIO_DDR_PHY_106_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_106_REGOFF) |
| #define HWIO_DDR_PHY_106_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_106_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_107_REGOFF 0x1ac |
| #define HWIO_DDR_PHY_107_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_107_REGOFF) |
| #define HWIO_DDR_PHY_107_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_107_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_108_REGOFF 0x1b0 |
| #define HWIO_DDR_PHY_108_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_108_REGOFF) |
| #define HWIO_DDR_PHY_108_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_108_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_109_REGOFF 0x1b4 |
| #define HWIO_DDR_PHY_109_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_109_REGOFF) |
| #define HWIO_DDR_PHY_109_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_109_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_110_REGOFF 0x1b8 |
| #define HWIO_DDR_PHY_110_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_110_REGOFF) |
| #define HWIO_DDR_PHY_110_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_110_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_111_REGOFF 0x1bc |
| #define HWIO_DDR_PHY_111_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_111_REGOFF) |
| #define HWIO_DDR_PHY_111_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_111_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_112_REGOFF 0x1c0 |
| #define HWIO_DDR_PHY_112_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_112_REGOFF) |
| #define HWIO_DDR_PHY_112_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_112_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_113_REGOFF 0x1c4 |
| #define HWIO_DDR_PHY_113_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_113_REGOFF) |
| #define HWIO_DDR_PHY_113_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_113_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_114_REGOFF 0x1c8 |
| #define HWIO_DDR_PHY_114_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_114_REGOFF) |
| #define HWIO_DDR_PHY_114_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_114_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_115_REGOFF 0x1cc |
| #define HWIO_DDR_PHY_115_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_115_REGOFF) |
| #define HWIO_DDR_PHY_115_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_115_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_116_REGOFF 0x1d0 |
| #define HWIO_DDR_PHY_116_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_116_REGOFF) |
| #define HWIO_DDR_PHY_116_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_116_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_117_REGOFF 0x1d4 |
| #define HWIO_DDR_PHY_117_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_117_REGOFF) |
| #define HWIO_DDR_PHY_117_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_117_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_118_REGOFF 0x1d8 |
| #define HWIO_DDR_PHY_118_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_118_REGOFF) |
| #define HWIO_DDR_PHY_118_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_118_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_119_REGOFF 0x1dc |
| #define HWIO_DDR_PHY_119_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_119_REGOFF) |
| #define HWIO_DDR_PHY_119_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_119_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_120_REGOFF 0x1e0 |
| #define HWIO_DDR_PHY_120_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_120_REGOFF) |
| #define HWIO_DDR_PHY_120_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_120_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_121_REGOFF 0x1e4 |
| #define HWIO_DDR_PHY_121_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_121_REGOFF) |
| #define HWIO_DDR_PHY_121_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_121_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_122_REGOFF 0x1e8 |
| #define HWIO_DDR_PHY_122_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_122_REGOFF) |
| #define HWIO_DDR_PHY_122_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_122_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_123_REGOFF 0x1ec |
| #define HWIO_DDR_PHY_123_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_123_REGOFF) |
| #define HWIO_DDR_PHY_123_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_123_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_124_REGOFF 0x1f0 |
| #define HWIO_DDR_PHY_124_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_124_REGOFF) |
| #define HWIO_DDR_PHY_124_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_124_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_125_REGOFF 0x1f4 |
| #define HWIO_DDR_PHY_125_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_125_REGOFF) |
| #define HWIO_DDR_PHY_125_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_125_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_126_REGOFF 0x1f8 |
| #define HWIO_DDR_PHY_126_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_126_REGOFF) |
| #define HWIO_DDR_PHY_126_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_126_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_127_REGOFF 0x1fc |
| #define HWIO_DDR_PHY_127_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_127_REGOFF) |
| #define HWIO_DDR_PHY_127_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_127_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_128_REGOFF 0x200 |
| #define HWIO_DDR_PHY_128_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_128_REGOFF) |
| #define HWIO_DDR_PHY_128_PHY_DQ_DM_SWIZZLE0_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_128_PHY_DQ_DM_SWIZZLE0_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_129_REGOFF 0x204 |
| #define HWIO_DDR_PHY_129_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_129_REGOFF) |
| #define HWIO_DDR_PHY_129_PHY_DQ_DM_SWIZZLE1_1_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_129_PHY_DQ_DM_SWIZZLE1_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_129_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_129_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_129_PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_129_PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_129_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_129_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_129_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_129_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_130_REGOFF 0x208 |
| #define HWIO_DDR_PHY_130_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_130_REGOFF) |
| #define HWIO_DDR_PHY_130_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_130_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_130_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_130_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_130_PHY_BYPASS_TWO_CYC_PREAMBLE_1_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_130_PHY_BYPASS_TWO_CYC_PREAMBLE_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_130_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_130_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_130_PHY_CLK_BYPASS_OVERRIDE_1_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_130_PHY_CLK_BYPASS_OVERRIDE_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_130_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_130_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_131_REGOFF 0x20c |
| #define HWIO_DDR_PHY_131_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_131_REGOFF) |
| #define HWIO_DDR_PHY_131_PHY_SW_WRDQ0_SHIFT_1_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_131_PHY_SW_WRDQ0_SHIFT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_131_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_131_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_131_PHY_SW_WRDQ1_SHIFT_1_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_131_PHY_SW_WRDQ1_SHIFT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_131_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_131_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_131_PHY_SW_WRDQ2_SHIFT_1_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_131_PHY_SW_WRDQ2_SHIFT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_131_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_131_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_131_PHY_SW_WRDQ3_SHIFT_1_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_131_PHY_SW_WRDQ3_SHIFT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_131_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_131_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_132_REGOFF 0x210 |
| #define HWIO_DDR_PHY_132_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_132_REGOFF) |
| #define HWIO_DDR_PHY_132_PHY_SW_WRDQ4_SHIFT_1_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_132_PHY_SW_WRDQ4_SHIFT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_132_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_132_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_132_PHY_SW_WRDQ5_SHIFT_1_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_132_PHY_SW_WRDQ5_SHIFT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_132_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_132_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_132_PHY_SW_WRDQ6_SHIFT_1_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_132_PHY_SW_WRDQ6_SHIFT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_132_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_132_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_132_PHY_SW_WRDQ7_SHIFT_1_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_132_PHY_SW_WRDQ7_SHIFT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_132_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_132_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_133_REGOFF 0x214 |
| #define HWIO_DDR_PHY_133_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_133_REGOFF) |
| #define HWIO_DDR_PHY_133_PHY_SW_WRDM_SHIFT_1_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_133_PHY_SW_WRDM_SHIFT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_133_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_133_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_133_PHY_SW_WRDQS_SHIFT_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_133_PHY_SW_WRDQS_SHIFT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_133_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_133_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_133_PHY_DQ_TSEL_ENABLE_1_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_133_PHY_DQ_TSEL_ENABLE_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_133_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_133_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_133_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_133_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_134_REGOFF 0x218 |
| #define HWIO_DDR_PHY_134_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_134_REGOFF) |
| #define HWIO_DDR_PHY_134_PHY_DQ_TSEL_SELECT_1_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_134_PHY_DQ_TSEL_SELECT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_134_PHY_DQS_TSEL_ENABLE_1_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_134_PHY_DQS_TSEL_ENABLE_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_134_RESERVED_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_134_RESERVED_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_135_REGOFF 0x21c |
| #define HWIO_DDR_PHY_135_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_135_REGOFF) |
| #define HWIO_DDR_PHY_135_PHY_DQS_TSEL_SELECT_1_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_135_PHY_DQS_TSEL_SELECT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_135_PHY_TWO_CYC_PREAMBLE_1_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_135_PHY_TWO_CYC_PREAMBLE_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_135_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_135_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_136_REGOFF 0x220 |
| #define HWIO_DDR_PHY_136_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_136_REGOFF) |
| #define HWIO_DDR_PHY_136_PHY_DBI_MODE_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_136_PHY_DBI_MODE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_136_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_136_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_136_PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_136_PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_136_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_136_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_136_PHY_LP4_BOOT_RDDATA_EN_DLY_1_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_136_PHY_LP4_BOOT_RDDATA_EN_DLY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_136_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_136_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_136_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_136_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_136_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_136_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_137_REGOFF 0x224 |
| #define HWIO_DDR_PHY_137_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_137_REGOFF) |
| #define HWIO_DDR_PHY_137_PHY_LP4_BOOT_RPTR_UPDATE_1_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_137_PHY_LP4_BOOT_RPTR_UPDATE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_137_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_137_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_137_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_137_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_137_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_137_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_137_PHY_LPBK_CONTROL_1_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_137_PHY_LPBK_CONTROL_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_137_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_137_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_138_REGOFF 0x228 |
| #define HWIO_DDR_PHY_138_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_138_REGOFF) |
| #define HWIO_DDR_PHY_138_PHY_LPBK_DFX_TIMEOUT_EN_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_138_PHY_LPBK_DFX_TIMEOUT_EN_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_138_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_138_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_138_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_138_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_139_REGOFF 0x22c |
| #define HWIO_DDR_PHY_139_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_139_REGOFF) |
| #define HWIO_DDR_PHY_139_PHY_AUTO_TIMING_MARGIN_CONTROL_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_139_PHY_AUTO_TIMING_MARGIN_CONTROL_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_140_REGOFF 0x230 |
| #define HWIO_DDR_PHY_140_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_140_REGOFF) |
| #define HWIO_DDR_PHY_140_PHY_AUTO_TIMING_MARGIN_OBS_1_FLDMASK (0xfffffff) |
| #define HWIO_DDR_PHY_140_PHY_AUTO_TIMING_MARGIN_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_140_RESERVED_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_140_RESERVED_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_141_REGOFF 0x234 |
| #define HWIO_DDR_PHY_141_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_141_REGOFF) |
| #define HWIO_DDR_PHY_141_PHY_SLICE_PWR_RDC_DISABLE_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_141_PHY_SLICE_PWR_RDC_DISABLE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_141_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_141_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_141_PHY_PRBS_PATTERN_START_1_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_141_PHY_PRBS_PATTERN_START_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_141_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_141_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_141_PHY_PRBS_PATTERN_MASK_1_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_141_PHY_PRBS_PATTERN_MASK_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_141_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_141_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_142_REGOFF 0x238 |
| #define HWIO_DDR_PHY_142_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_142_REGOFF) |
| #define HWIO_DDR_PHY_142_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_142_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_142_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_142_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_142_PHY_GATE_ERROR_DELAY_SELECT_1_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_142_PHY_GATE_ERROR_DELAY_SELECT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_142_RESERVED1_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_142_RESERVED1_FLDSHFT (21) |
| #define HWIO_DDR_PHY_142_SC_PHY_SNAP_OBS_REGS_1_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_142_SC_PHY_SNAP_OBS_REGS_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_142_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_142_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_143_REGOFF 0x23c |
| #define HWIO_DDR_PHY_143_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_143_REGOFF) |
| #define HWIO_DDR_PHY_143_PHY_GATE_SMPL1_SLAVE_DELAY_1_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_143_PHY_GATE_SMPL1_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_143_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_143_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_143_PHY_LPDDR_1_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_143_PHY_LPDDR_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_143_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_143_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_143_PHY_LPDDR_TYPE_1_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_143_PHY_LPDDR_TYPE_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_143_RESERVED2_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_143_RESERVED2_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_144_REGOFF 0x240 |
| #define HWIO_DDR_PHY_144_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_144_REGOFF) |
| #define HWIO_DDR_PHY_144_PHY_GATE_SMPL2_SLAVE_DELAY_1_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_144_PHY_GATE_SMPL2_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_144_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_144_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_144_ON_FLY_GATE_ADJUST_EN_1_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_144_ON_FLY_GATE_ADJUST_EN_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_144_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_144_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_144_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_144_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_145_REGOFF 0x244 |
| #define HWIO_DDR_PHY_145_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_145_REGOFF) |
| #define HWIO_DDR_PHY_145_PHY_GATE_TRACKING_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_145_PHY_GATE_TRACKING_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_146_REGOFF 0x248 |
| #define HWIO_DDR_PHY_146_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_146_REGOFF) |
| #define HWIO_DDR_PHY_146_PHY_LP4_PST_AMBLE_1_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_146_PHY_LP4_PST_AMBLE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_146_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_146_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_146_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_146_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_147_REGOFF 0x24c |
| #define HWIO_DDR_PHY_147_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_147_REGOFF) |
| #define HWIO_DDR_PHY_147_PHY_LP4_RDLVL_PATT8_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_147_PHY_LP4_RDLVL_PATT8_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_148_REGOFF 0x250 |
| #define HWIO_DDR_PHY_148_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_148_REGOFF) |
| #define HWIO_DDR_PHY_148_PHY_LP4_RDLVL_PATT9_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_148_PHY_LP4_RDLVL_PATT9_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_149_REGOFF 0x254 |
| #define HWIO_DDR_PHY_149_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_149_REGOFF) |
| #define HWIO_DDR_PHY_149_PHY_LP4_RDLVL_PATT10_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_149_PHY_LP4_RDLVL_PATT10_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_150_REGOFF 0x258 |
| #define HWIO_DDR_PHY_150_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_150_REGOFF) |
| #define HWIO_DDR_PHY_150_PHY_LP4_RDLVL_PATT11_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_150_PHY_LP4_RDLVL_PATT11_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_151_REGOFF 0x25c |
| #define HWIO_DDR_PHY_151_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_151_REGOFF) |
| #define HWIO_DDR_PHY_151_PHY_SLAVE_LOOP_CNT_UPDATE_1_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_151_PHY_SLAVE_LOOP_CNT_UPDATE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_151_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_151_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_151_PHY_SW_FIFO_PTR_RST_DISABLE_1_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_151_PHY_SW_FIFO_PTR_RST_DISABLE_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_151_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_151_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_151_PHY_MASTER_DLY_LOCK_OBS_SELECT_1_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_151_PHY_MASTER_DLY_LOCK_OBS_SELECT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_151_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_151_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_151_PHY_RDDQ_ENC_OBS_SELECT_1_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_151_PHY_RDDQ_ENC_OBS_SELECT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_151_RESERVED3_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_151_RESERVED3_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_152_REGOFF 0x260 |
| #define HWIO_DDR_PHY_152_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_152_REGOFF) |
| #define HWIO_DDR_PHY_152_PHY_RDDQS_DQ_ENC_OBS_SELECT_1_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_152_PHY_RDDQS_DQ_ENC_OBS_SELECT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_152_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_152_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_152_PHY_WR_ENC_OBS_SELECT_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_152_PHY_WR_ENC_OBS_SELECT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_152_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_152_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_152_PHY_WR_SHIFT_OBS_SELECT_1_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_152_PHY_WR_SHIFT_OBS_SELECT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_152_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_152_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_152_PHY_FIFO_PTR_OBS_SELECT_1_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_152_PHY_FIFO_PTR_OBS_SELECT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_152_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_152_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_153_REGOFF 0x264 |
| #define HWIO_DDR_PHY_153_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_153_REGOFF) |
| #define HWIO_DDR_PHY_153_PHY_LVL_DEBUG_MODE_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_153_PHY_LVL_DEBUG_MODE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_153_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_153_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_153_SC_PHY_LVL_DEBUG_CONT_1_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_153_SC_PHY_LVL_DEBUG_CONT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_153_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_153_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_153_PHY_WRLVL_CAPTURE_CNT_1_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_153_PHY_WRLVL_CAPTURE_CNT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_153_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_153_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_153_PHY_WRLVL_UPDT_WAIT_CNT_1_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_153_PHY_WRLVL_UPDT_WAIT_CNT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_153_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_153_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_154_REGOFF 0x268 |
| #define HWIO_DDR_PHY_154_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_154_REGOFF) |
| #define HWIO_DDR_PHY_154_PHY_GTLVL_CAPTURE_CNT_1_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_154_PHY_GTLVL_CAPTURE_CNT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_154_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_154_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_154_PHY_GTLVL_UPDT_WAIT_CNT_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_154_PHY_GTLVL_UPDT_WAIT_CNT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_154_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_154_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_154_PHY_RDLVL_CAPTURE_CNT_1_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_154_PHY_RDLVL_CAPTURE_CNT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_154_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_154_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_154_PHY_RDLVL_UPDT_WAIT_CNT_1_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_154_PHY_RDLVL_UPDT_WAIT_CNT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_154_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_154_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_155_REGOFF 0x26c |
| #define HWIO_DDR_PHY_155_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_155_REGOFF) |
| #define HWIO_DDR_PHY_155_PHY_RDLVL_OP_MODE_1_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_155_PHY_RDLVL_OP_MODE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_155_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_155_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_155_PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_155_PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_155_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_155_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_155_PHY_RDLVL_DATA_MASK_1_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_155_PHY_RDLVL_DATA_MASK_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_155_PHY_WDQLVL_BURST_CNT_1_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_155_PHY_WDQLVL_BURST_CNT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_155_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_155_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_156_REGOFF 0x270 |
| #define HWIO_DDR_PHY_156_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_156_REGOFF) |
| #define HWIO_DDR_PHY_156_PHY_WDQLVL_PATT_1_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_156_PHY_WDQLVL_PATT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_156_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_156_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_156_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_156_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_156_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_156_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_156_PHY_WDQLVL_UPDT_WAIT_CNT_1_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_156_PHY_WDQLVL_UPDT_WAIT_CNT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_156_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_156_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_157_REGOFF 0x274 |
| #define HWIO_DDR_PHY_157_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_157_REGOFF) |
| #define HWIO_DDR_PHY_157_PHY_WDQLVL_DQDM_OBS_SELECT_1_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_157_PHY_WDQLVL_DQDM_OBS_SELECT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_157_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_157_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_157_PHY_WDQLVL_QTR_DLY_STEP_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_157_PHY_WDQLVL_QTR_DLY_STEP_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_157_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_157_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_157_SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_157_SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_157_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_157_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_157_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_157_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_158_REGOFF 0x278 |
| #define HWIO_DDR_PHY_158_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_158_REGOFF) |
| #define HWIO_DDR_PHY_158_PHY_WDQLVL_DATADM_MASK_1_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_158_PHY_WDQLVL_DATADM_MASK_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_158_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_158_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_158_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_158_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_159_REGOFF 0x27c |
| #define HWIO_DDR_PHY_159_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_159_REGOFF) |
| #define HWIO_DDR_PHY_159_PHY_USER_PATT0_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_159_PHY_USER_PATT0_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_160_REGOFF 0x280 |
| #define HWIO_DDR_PHY_160_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_160_REGOFF) |
| #define HWIO_DDR_PHY_160_PHY_USER_PATT1_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_160_PHY_USER_PATT1_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_161_REGOFF 0x284 |
| #define HWIO_DDR_PHY_161_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_161_REGOFF) |
| #define HWIO_DDR_PHY_161_PHY_USER_PATT2_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_161_PHY_USER_PATT2_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_162_REGOFF 0x288 |
| #define HWIO_DDR_PHY_162_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_162_REGOFF) |
| #define HWIO_DDR_PHY_162_PHY_USER_PATT3_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_162_PHY_USER_PATT3_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_163_REGOFF 0x28c |
| #define HWIO_DDR_PHY_163_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_163_REGOFF) |
| #define HWIO_DDR_PHY_163_PHY_USER_PATT4_1_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_163_PHY_USER_PATT4_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_163_PHY_CALVL_VREF_DRIVING_SLICE_1_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_163_PHY_CALVL_VREF_DRIVING_SLICE_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_163_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_163_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_163_SC_PHY_MANUAL_CLEAR_1_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_163_SC_PHY_MANUAL_CLEAR_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_163_RESERVED1_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_163_RESERVED1_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_164_REGOFF 0x290 |
| #define HWIO_DDR_PHY_164_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_164_REGOFF) |
| #define HWIO_DDR_PHY_164_PHY_FIFO_PTR_OBS_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_164_PHY_FIFO_PTR_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_164_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_164_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_165_REGOFF 0x294 |
| #define HWIO_DDR_PHY_165_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_165_REGOFF) |
| #define HWIO_DDR_PHY_165_PHY_LPBK_RESULT_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_165_PHY_LPBK_RESULT_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_166_REGOFF 0x298 |
| #define HWIO_DDR_PHY_166_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_166_REGOFF) |
| #define HWIO_DDR_PHY_166_PHY_LPBK_ERROR_COUNT_OBS_1_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_166_PHY_LPBK_ERROR_COUNT_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_166_PHY_MASTER_DLY_LOCK_OBS_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_166_PHY_MASTER_DLY_LOCK_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_166_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_166_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_167_REGOFF 0x29c |
| #define HWIO_DDR_PHY_167_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_167_REGOFF) |
| #define HWIO_DDR_PHY_167_PHY_RDDQ_SLV_DLY_ENC_OBS_1_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_167_PHY_RDDQ_SLV_DLY_ENC_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_167_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_167_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_167_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_167_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_167_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_167_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_167_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_FLDMASK \ |
| (0xff0000) |
| #define HWIO_DDR_PHY_167_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_167_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_FLDMASK \ |
| (0xff000000) |
| #define HWIO_DDR_PHY_167_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_168_REGOFF 0x2a0 |
| #define HWIO_DDR_PHY_168_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_168_REGOFF) |
| #define HWIO_DDR_PHY_168_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_168_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_168_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_168_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_168_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_FLDMASK (0x7f0000) |
| #define HWIO_DDR_PHY_168_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_168_RESERVED1_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_168_RESERVED1_FLDSHFT (23) |
| #define HWIO_DDR_PHY_168_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_168_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_169_REGOFF 0x2a4 |
| #define HWIO_DDR_PHY_169_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_169_REGOFF) |
| #define HWIO_DDR_PHY_169_PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_169_PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_169_PHY_WR_SHIFT_OBS_1_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_169_PHY_WR_SHIFT_OBS_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_169_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_169_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_169_PHY_WRLVL_HARD0_DELAY_OBS_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_169_PHY_WRLVL_HARD0_DELAY_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_169_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_169_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_170_REGOFF 0x2a8 |
| #define HWIO_DDR_PHY_170_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_170_REGOFF) |
| #define HWIO_DDR_PHY_170_PHY_WRLVL_HARD1_DELAY_OBS_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_170_PHY_WRLVL_HARD1_DELAY_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_170_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_170_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_170_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_170_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_171_REGOFF 0x2ac |
| #define HWIO_DDR_PHY_171_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_171_REGOFF) |
| #define HWIO_DDR_PHY_171_PHY_WRLVL_STATUS_OBS_1_FLDMASK (0x1ffff) |
| #define HWIO_DDR_PHY_171_PHY_WRLVL_STATUS_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_171_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_171_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_171_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_171_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_172_REGOFF 0x2b0 |
| #define HWIO_DDR_PHY_172_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_172_REGOFF) |
| #define HWIO_DDR_PHY_172_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_172_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_172_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_172_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_172_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_172_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_172_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_172_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_173_REGOFF 0x2b4 |
| #define HWIO_DDR_PHY_173_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_173_REGOFF) |
| #define HWIO_DDR_PHY_173_PHY_GTLVL_HARD0_DELAY_OBS_1_FLDMASK (0x3fff) |
| #define HWIO_DDR_PHY_173_PHY_GTLVL_HARD0_DELAY_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_173_RESERVED_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_173_RESERVED_FLDSHFT (14) |
| #define HWIO_DDR_PHY_173_PHY_GTLVL_HARD1_DELAY_OBS_1_FLDMASK (0x3fff0000) |
| #define HWIO_DDR_PHY_173_PHY_GTLVL_HARD1_DELAY_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_173_RESERVED1_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_173_RESERVED1_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_174_REGOFF 0x2b8 |
| #define HWIO_DDR_PHY_174_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_174_REGOFF) |
| #define HWIO_DDR_PHY_174_PHY_GTLVL_STATUS_OBS_1_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_174_PHY_GTLVL_STATUS_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_174_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_174_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_174_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_174_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_175_REGOFF 0x2bc |
| #define HWIO_DDR_PHY_175_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_175_REGOFF) |
| #define HWIO_DDR_PHY_175_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_175_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_175_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_175_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_175_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_175_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_175_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_175_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_176_REGOFF 0x2c0 |
| #define HWIO_DDR_PHY_176_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_176_REGOFF) |
| #define HWIO_DDR_PHY_176_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_176_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_176_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_176_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_176_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_176_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_177_REGOFF 0x2c4 |
| #define HWIO_DDR_PHY_177_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_177_REGOFF) |
| #define HWIO_DDR_PHY_177_PHY_RDLVL_STATUS_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_177_PHY_RDLVL_STATUS_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_178_REGOFF 0x2c8 |
| #define HWIO_DDR_PHY_178_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_178_REGOFF) |
| #define HWIO_DDR_PHY_178_PHY_WDQLVL_DQDM_LE_DLY_OBS_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_178_PHY_WDQLVL_DQDM_LE_DLY_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_178_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_178_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_178_PHY_WDQLVL_DQDM_TE_DLY_OBS_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_178_PHY_WDQLVL_DQDM_TE_DLY_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_178_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_178_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_179_REGOFF 0x2cc |
| #define HWIO_DDR_PHY_179_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_179_REGOFF) |
| #define HWIO_DDR_PHY_179_PHY_WDQLVL_STATUS_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_179_PHY_WDQLVL_STATUS_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_180_REGOFF 0x2d0 |
| #define HWIO_DDR_PHY_180_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_180_REGOFF) |
| #define HWIO_DDR_PHY_180_PHY_DDL_MODE_1_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_180_PHY_DDL_MODE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_180_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_180_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_180_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_180_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_181_REGOFF 0x2d4 |
| #define HWIO_DDR_PHY_181_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_181_REGOFF) |
| #define HWIO_DDR_PHY_181_PHY_DDL_TEST_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_181_PHY_DDL_TEST_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_182_REGOFF 0x2d8 |
| #define HWIO_DDR_PHY_182_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_182_REGOFF) |
| #define HWIO_DDR_PHY_182_PHY_DDL_TEST_MSTR_DLY_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_182_PHY_DDL_TEST_MSTR_DLY_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_183_REGOFF 0x2dc |
| #define HWIO_DDR_PHY_183_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_183_REGOFF) |
| #define HWIO_DDR_PHY_183_PHY_DDL_TRACK_UPD_THRESHOLD_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_183_PHY_DDL_TRACK_UPD_THRESHOLD_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_183_PHY_LP4_WDQS_OE_EXTEND_1_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_183_PHY_LP4_WDQS_OE_EXTEND_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_183_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_183_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_183_SC_PHY_RX_CAL_START_1_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_183_SC_PHY_RX_CAL_START_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_183_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_183_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_183_PHY_RX_CAL_OVERRIDE_1_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_183_PHY_RX_CAL_OVERRIDE_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_183_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_183_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_184_REGOFF 0x2e0 |
| #define HWIO_DDR_PHY_184_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_184_REGOFF) |
| #define HWIO_DDR_PHY_184_PHY_RX_CAL_SAMPLE_WAIT_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_184_PHY_RX_CAL_SAMPLE_WAIT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_184_PHY_RX_CAL_DQ0_1_FLDMASK (0xfff00) |
| #define HWIO_DDR_PHY_184_PHY_RX_CAL_DQ0_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_184_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_184_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_184_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_184_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_185_REGOFF 0x2e4 |
| #define HWIO_DDR_PHY_185_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_185_REGOFF) |
| #define HWIO_DDR_PHY_185_PHY_RX_CAL_DQ1_1_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_185_PHY_RX_CAL_DQ1_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_185_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_185_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_185_PHY_RX_CAL_DQ2_1_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_185_PHY_RX_CAL_DQ2_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_185_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_185_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_186_REGOFF 0x2e8 |
| #define HWIO_DDR_PHY_186_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_186_REGOFF) |
| #define HWIO_DDR_PHY_186_PHY_RX_CAL_DQ3_1_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_186_PHY_RX_CAL_DQ3_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_186_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_186_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_186_PHY_RX_CAL_DQ4_1_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_186_PHY_RX_CAL_DQ4_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_186_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_186_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_187_REGOFF 0x2ec |
| #define HWIO_DDR_PHY_187_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_187_REGOFF) |
| #define HWIO_DDR_PHY_187_PHY_RX_CAL_DQ5_1_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_187_PHY_RX_CAL_DQ5_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_187_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_187_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_187_PHY_RX_CAL_DQ6_1_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_187_PHY_RX_CAL_DQ6_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_187_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_187_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_188_REGOFF 0x2f0 |
| #define HWIO_DDR_PHY_188_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_188_REGOFF) |
| #define HWIO_DDR_PHY_188_PHY_RX_CAL_DQ7_1_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_188_PHY_RX_CAL_DQ7_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_188_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_188_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_188_PHY_RX_CAL_DM_1_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_188_PHY_RX_CAL_DM_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_188_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_188_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_189_REGOFF 0x2f4 |
| #define HWIO_DDR_PHY_189_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_189_REGOFF) |
| #define HWIO_DDR_PHY_189_PHY_RX_CAL_DQS_1_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_189_PHY_RX_CAL_DQS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_189_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_189_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_189_PHY_RX_CAL_FDBK_1_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_189_PHY_RX_CAL_FDBK_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_189_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_189_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_190_REGOFF 0x2f8 |
| #define HWIO_DDR_PHY_190_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_190_REGOFF) |
| #define HWIO_DDR_PHY_190_PHY_RX_CAL_OBS_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_190_PHY_RX_CAL_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_190_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_190_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_190_PHY_RX_CAL_LOCK_OBS_1_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_190_PHY_RX_CAL_LOCK_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_190_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_190_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_191_REGOFF 0x2fc |
| #define HWIO_DDR_PHY_191_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_191_REGOFF) |
| #define HWIO_DDR_PHY_191_PHY_RX_CAL_DISABLE_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_191_PHY_RX_CAL_DISABLE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_191_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_191_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_191_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_191_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_192_REGOFF 0x300 |
| #define HWIO_DDR_PHY_192_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_192_REGOFF) |
| #define HWIO_DDR_PHY_192_PHY_CLK_WRDQ0_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_192_PHY_CLK_WRDQ0_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_192_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_192_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_192_PHY_CLK_WRDQ1_SLAVE_DELAY_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_192_PHY_CLK_WRDQ1_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_192_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_192_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_193_REGOFF 0x304 |
| #define HWIO_DDR_PHY_193_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_193_REGOFF) |
| #define HWIO_DDR_PHY_193_PHY_CLK_WRDQ2_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_193_PHY_CLK_WRDQ2_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_193_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_193_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_193_PHY_CLK_WRDQ3_SLAVE_DELAY_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_193_PHY_CLK_WRDQ3_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_193_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_193_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_194_REGOFF 0x308 |
| #define HWIO_DDR_PHY_194_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_194_REGOFF) |
| #define HWIO_DDR_PHY_194_PHY_CLK_WRDQ4_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_194_PHY_CLK_WRDQ4_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_194_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_194_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_194_PHY_CLK_WRDQ5_SLAVE_DELAY_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_194_PHY_CLK_WRDQ5_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_194_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_194_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_195_REGOFF 0x30c |
| #define HWIO_DDR_PHY_195_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_195_REGOFF) |
| #define HWIO_DDR_PHY_195_PHY_CLK_WRDQ6_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_195_PHY_CLK_WRDQ6_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_195_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_195_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_195_PHY_CLK_WRDQ7_SLAVE_DELAY_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_195_PHY_CLK_WRDQ7_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_195_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_195_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_196_REGOFF 0x310 |
| #define HWIO_DDR_PHY_196_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_196_REGOFF) |
| #define HWIO_DDR_PHY_196_PHY_CLK_WRDM_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_196_PHY_CLK_WRDM_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_196_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_196_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_196_PHY_CLK_WRDQS_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_196_PHY_CLK_WRDQS_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_196_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_196_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_197_REGOFF 0x314 |
| #define HWIO_DDR_PHY_197_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_197_REGOFF) |
| #define HWIO_DDR_PHY_197_PHY_WRLVL_THRESHOLD_ADJUST_1_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_197_PHY_WRLVL_THRESHOLD_ADJUST_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_197_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_197_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_197_PHY_RDDQ0_SLAVE_DELAY_1_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_197_PHY_RDDQ0_SLAVE_DELAY_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_197_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_197_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_197_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_197_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_198_REGOFF 0x318 |
| #define HWIO_DDR_PHY_198_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_198_REGOFF) |
| #define HWIO_DDR_PHY_198_PHY_RDDQ1_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_198_PHY_RDDQ1_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_198_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_198_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_198_PHY_RDDQ2_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_198_PHY_RDDQ2_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_198_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_198_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_199_REGOFF 0x31c |
| #define HWIO_DDR_PHY_199_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_199_REGOFF) |
| #define HWIO_DDR_PHY_199_PHY_RDDQ3_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_199_PHY_RDDQ3_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_199_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_199_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_199_PHY_RDDQ4_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_199_PHY_RDDQ4_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_199_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_199_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_200_REGOFF 0x320 |
| #define HWIO_DDR_PHY_200_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_200_REGOFF) |
| #define HWIO_DDR_PHY_200_PHY_RDDQ5_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_200_PHY_RDDQ5_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_200_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_200_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_200_PHY_RDDQ6_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_200_PHY_RDDQ6_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_200_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_200_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_201_REGOFF 0x324 |
| #define HWIO_DDR_PHY_201_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_201_REGOFF) |
| #define HWIO_DDR_PHY_201_PHY_RDDQ7_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_201_PHY_RDDQ7_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_201_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_201_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_201_PHY_RDDM_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_201_PHY_RDDM_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_201_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_201_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_202_REGOFF 0x328 |
| #define HWIO_DDR_PHY_202_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_202_REGOFF) |
| #define HWIO_DDR_PHY_202_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_202_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_202_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_202_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_202_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_202_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_202_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_202_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_203_REGOFF 0x32c |
| #define HWIO_DDR_PHY_203_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_203_REGOFF) |
| #define HWIO_DDR_PHY_203_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_203_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_203_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_203_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_203_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_203_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_203_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_203_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_204_REGOFF 0x330 |
| #define HWIO_DDR_PHY_204_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_204_REGOFF) |
| #define HWIO_DDR_PHY_204_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_204_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_204_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_204_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_204_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_204_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_204_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_204_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_205_REGOFF 0x334 |
| #define HWIO_DDR_PHY_205_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_205_REGOFF) |
| #define HWIO_DDR_PHY_205_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_205_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_205_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_205_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_205_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_205_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_205_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_205_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_206_REGOFF 0x338 |
| #define HWIO_DDR_PHY_206_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_206_REGOFF) |
| #define HWIO_DDR_PHY_206_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_206_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_206_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_206_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_206_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_206_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_206_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_206_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_207_REGOFF 0x33c |
| #define HWIO_DDR_PHY_207_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_207_REGOFF) |
| #define HWIO_DDR_PHY_207_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_207_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_207_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_207_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_207_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_207_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_207_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_207_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_208_REGOFF 0x340 |
| #define HWIO_DDR_PHY_208_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_208_REGOFF) |
| #define HWIO_DDR_PHY_208_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_208_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_208_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_208_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_208_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_208_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_208_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_208_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_209_REGOFF 0x344 |
| #define HWIO_DDR_PHY_209_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_209_REGOFF) |
| #define HWIO_DDR_PHY_209_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_209_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_209_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_209_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_209_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_209_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_209_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_209_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_210_REGOFF 0x348 |
| #define HWIO_DDR_PHY_210_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_210_REGOFF) |
| #define HWIO_DDR_PHY_210_PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_210_PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_210_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_210_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_210_PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_210_PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_210_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_210_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_211_REGOFF 0x34c |
| #define HWIO_DDR_PHY_211_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_211_REGOFF) |
| #define HWIO_DDR_PHY_211_PHY_RDDQS_GATE_SLAVE_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_211_PHY_RDDQS_GATE_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_211_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_211_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_211_PHY_RDDQS_LATENCY_ADJUST_1_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_211_PHY_RDDQS_LATENCY_ADJUST_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_211_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_211_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_211_PHY_WRITE_PATH_LAT_ADD_1_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_211_PHY_WRITE_PATH_LAT_ADD_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_211_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_211_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_212_REGOFF 0x350 |
| #define HWIO_DDR_PHY_212_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_212_REGOFF) |
| #define HWIO_DDR_PHY_212_PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_212_PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_212_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_212_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_212_PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_212_PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_212_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_212_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_213_REGOFF 0x354 |
| #define HWIO_DDR_PHY_213_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_213_REGOFF) |
| #define HWIO_DDR_PHY_213_PHY_WRLVL_EARLY_FORCE_0_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_213_PHY_WRLVL_EARLY_FORCE_0_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_213_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_213_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_213_PHY_GTLVL_RDDQS_SLV_DLY_START_1_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_213_PHY_GTLVL_RDDQS_SLV_DLY_START_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_213_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_213_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_213_PHY_GTLVL_LAT_ADJ_START_1_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_213_PHY_GTLVL_LAT_ADJ_START_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_213_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_213_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_214_REGOFF 0x358 |
| #define HWIO_DDR_PHY_214_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_214_REGOFF) |
| #define HWIO_DDR_PHY_214_PHY_WDQLVL_DQDM_SLV_DLY_START_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_214_PHY_WDQLVL_DQDM_SLV_DLY_START_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_214_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_214_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_214_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_214_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_214_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_214_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_215_REGOFF 0x35c |
| #define HWIO_DDR_PHY_215_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_215_REGOFF) |
| #define HWIO_DDR_PHY_215_PHY_FDBK_PWR_CTRL_1_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_215_PHY_FDBK_PWR_CTRL_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_215_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_215_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_215_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_215_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_216_REGOFF 0x360 |
| #define HWIO_DDR_PHY_216_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_216_REGOFF) |
| #define HWIO_DDR_PHY_216_PHY_DQ_OE_TIMING_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_216_PHY_DQ_OE_TIMING_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_216_PHY_DQ_TSEL_RD_TIMING_1_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_216_PHY_DQ_TSEL_RD_TIMING_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_216_PHY_DQ_TSEL_WR_TIMING_1_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_216_PHY_DQ_TSEL_WR_TIMING_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_216_PHY_DQS_OE_TIMING_1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_216_PHY_DQS_OE_TIMING_1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_217_REGOFF 0x364 |
| #define HWIO_DDR_PHY_217_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_217_REGOFF) |
| #define HWIO_DDR_PHY_217_PHY_DQS_TSEL_RD_TIMING_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_217_PHY_DQS_TSEL_RD_TIMING_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_217_PHY_DQS_TSEL_WR_TIMING_1_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_217_PHY_DQS_TSEL_WR_TIMING_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_217_PHY_DQ_IE_TIMING_1_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_217_PHY_DQ_IE_TIMING_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_217_PHY_DQS_IE_TIMING_1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_217_PHY_DQS_IE_TIMING_1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_218_REGOFF 0x368 |
| #define HWIO_DDR_PHY_218_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_218_REGOFF) |
| #define HWIO_DDR_PHY_218_PHY_RDDATA_EN_IE_DLY_1_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_218_PHY_RDDATA_EN_IE_DLY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_218_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_218_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_218_PHY_IE_MODE_1_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_218_PHY_IE_MODE_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_218_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_218_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_218_PHY_RDDATA_EN_DLY_1_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_218_PHY_RDDATA_EN_DLY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_218_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_218_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_218_PHY_RDDATA_EN_TSEL_DLY_1_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_218_PHY_RDDATA_EN_TSEL_DLY_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_218_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_218_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_219_REGOFF 0x36c |
| #define HWIO_DDR_PHY_219_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_219_REGOFF) |
| #define HWIO_DDR_PHY_219_PHY_SW_MASTER_MODE_1_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_219_PHY_SW_MASTER_MODE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_219_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_219_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_219_PHY_MASTER_DELAY_START_1_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_219_PHY_MASTER_DELAY_START_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_219_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_219_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_219_PHY_MASTER_DELAY_STEP_1_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_219_PHY_MASTER_DELAY_STEP_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_219_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_219_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_220_REGOFF 0x370 |
| #define HWIO_DDR_PHY_220_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_220_REGOFF) |
| #define HWIO_DDR_PHY_220_PHY_MASTER_DELAY_WAIT_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_220_PHY_MASTER_DELAY_WAIT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_220_PHY_MASTER_DELAY_HALF_MEASURE_1_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_220_PHY_MASTER_DELAY_HALF_MEASURE_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_220_PHY_RPTR_UPDATE_1_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_220_PHY_RPTR_UPDATE_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_220_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_220_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_220_PHY_WRLVL_DLY_STEP_1_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_220_PHY_WRLVL_DLY_STEP_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_220_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_220_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_221_REGOFF 0x374 |
| #define HWIO_DDR_PHY_221_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_221_REGOFF) |
| #define HWIO_DDR_PHY_221_PHY_WRLVL_RESP_WAIT_CNT_1_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_221_PHY_WRLVL_RESP_WAIT_CNT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_221_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_221_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_221_PHY_GTLVL_DLY_STEP_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_221_PHY_GTLVL_DLY_STEP_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_221_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_221_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_221_PHY_GTLVL_RESP_WAIT_CNT_1_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_221_PHY_GTLVL_RESP_WAIT_CNT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_221_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_221_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_221_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_221_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_222_REGOFF 0x378 |
| #define HWIO_DDR_PHY_222_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_222_REGOFF) |
| #define HWIO_DDR_PHY_222_PHY_GTLVL_BACK_STEP_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_222_PHY_GTLVL_BACK_STEP_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_222_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_222_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_222_PHY_GTLVL_FINAL_STEP_1_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_222_PHY_GTLVL_FINAL_STEP_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_222_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_222_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_223_REGOFF 0x37c |
| #define HWIO_DDR_PHY_223_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_223_REGOFF) |
| #define HWIO_DDR_PHY_223_PHY_WDQLVL_DLY_STEP_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_223_PHY_WDQLVL_DLY_STEP_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_223_PHY_RDLVL_DLY_STEP_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_223_PHY_RDLVL_DLY_STEP_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_223_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_223_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_223_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_223_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_224_REGOFF 0x380 |
| #define HWIO_DDR_PHY_224_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_224_REGOFF) |
| #define HWIO_DDR_PHY_224_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_224_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_225_REGOFF 0x384 |
| #define HWIO_DDR_PHY_225_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_225_REGOFF) |
| #define HWIO_DDR_PHY_225_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_225_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_226_REGOFF 0x388 |
| #define HWIO_DDR_PHY_226_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_226_REGOFF) |
| #define HWIO_DDR_PHY_226_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_226_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_227_REGOFF 0x38c |
| #define HWIO_DDR_PHY_227_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_227_REGOFF) |
| #define HWIO_DDR_PHY_227_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_227_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_228_REGOFF 0x390 |
| #define HWIO_DDR_PHY_228_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_228_REGOFF) |
| #define HWIO_DDR_PHY_228_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_228_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_229_REGOFF 0x394 |
| #define HWIO_DDR_PHY_229_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_229_REGOFF) |
| #define HWIO_DDR_PHY_229_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_229_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_230_REGOFF 0x398 |
| #define HWIO_DDR_PHY_230_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_230_REGOFF) |
| #define HWIO_DDR_PHY_230_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_230_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_231_REGOFF 0x39c |
| #define HWIO_DDR_PHY_231_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_231_REGOFF) |
| #define HWIO_DDR_PHY_231_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_231_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_232_REGOFF 0x3a0 |
| #define HWIO_DDR_PHY_232_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_232_REGOFF) |
| #define HWIO_DDR_PHY_232_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_232_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_233_REGOFF 0x3a4 |
| #define HWIO_DDR_PHY_233_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_233_REGOFF) |
| #define HWIO_DDR_PHY_233_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_233_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_234_REGOFF 0x3a8 |
| #define HWIO_DDR_PHY_234_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_234_REGOFF) |
| #define HWIO_DDR_PHY_234_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_234_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_235_REGOFF 0x3ac |
| #define HWIO_DDR_PHY_235_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_235_REGOFF) |
| #define HWIO_DDR_PHY_235_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_235_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_236_REGOFF 0x3b0 |
| #define HWIO_DDR_PHY_236_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_236_REGOFF) |
| #define HWIO_DDR_PHY_236_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_236_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_237_REGOFF 0x3b4 |
| #define HWIO_DDR_PHY_237_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_237_REGOFF) |
| #define HWIO_DDR_PHY_237_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_237_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_238_REGOFF 0x3b8 |
| #define HWIO_DDR_PHY_238_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_238_REGOFF) |
| #define HWIO_DDR_PHY_238_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_238_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_239_REGOFF 0x3bc |
| #define HWIO_DDR_PHY_239_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_239_REGOFF) |
| #define HWIO_DDR_PHY_239_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_239_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_240_REGOFF 0x3c0 |
| #define HWIO_DDR_PHY_240_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_240_REGOFF) |
| #define HWIO_DDR_PHY_240_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_240_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_241_REGOFF 0x3c4 |
| #define HWIO_DDR_PHY_241_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_241_REGOFF) |
| #define HWIO_DDR_PHY_241_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_241_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_242_REGOFF 0x3c8 |
| #define HWIO_DDR_PHY_242_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_242_REGOFF) |
| #define HWIO_DDR_PHY_242_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_242_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_243_REGOFF 0x3cc |
| #define HWIO_DDR_PHY_243_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_243_REGOFF) |
| #define HWIO_DDR_PHY_243_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_243_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_244_REGOFF 0x3d0 |
| #define HWIO_DDR_PHY_244_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_244_REGOFF) |
| #define HWIO_DDR_PHY_244_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_244_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_245_REGOFF 0x3d4 |
| #define HWIO_DDR_PHY_245_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_245_REGOFF) |
| #define HWIO_DDR_PHY_245_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_245_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_246_REGOFF 0x3d8 |
| #define HWIO_DDR_PHY_246_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_246_REGOFF) |
| #define HWIO_DDR_PHY_246_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_246_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_247_REGOFF 0x3dc |
| #define HWIO_DDR_PHY_247_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_247_REGOFF) |
| #define HWIO_DDR_PHY_247_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_247_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_248_REGOFF 0x3e0 |
| #define HWIO_DDR_PHY_248_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_248_REGOFF) |
| #define HWIO_DDR_PHY_248_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_248_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_249_REGOFF 0x3e4 |
| #define HWIO_DDR_PHY_249_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_249_REGOFF) |
| #define HWIO_DDR_PHY_249_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_249_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_250_REGOFF 0x3e8 |
| #define HWIO_DDR_PHY_250_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_250_REGOFF) |
| #define HWIO_DDR_PHY_250_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_250_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_251_REGOFF 0x3ec |
| #define HWIO_DDR_PHY_251_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_251_REGOFF) |
| #define HWIO_DDR_PHY_251_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_251_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_252_REGOFF 0x3f0 |
| #define HWIO_DDR_PHY_252_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_252_REGOFF) |
| #define HWIO_DDR_PHY_252_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_252_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_253_REGOFF 0x3f4 |
| #define HWIO_DDR_PHY_253_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_253_REGOFF) |
| #define HWIO_DDR_PHY_253_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_253_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_254_REGOFF 0x3f8 |
| #define HWIO_DDR_PHY_254_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_254_REGOFF) |
| #define HWIO_DDR_PHY_254_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_254_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_255_REGOFF 0x3fc |
| #define HWIO_DDR_PHY_255_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_255_REGOFF) |
| #define HWIO_DDR_PHY_255_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_255_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_256_REGOFF 0x400 |
| #define HWIO_DDR_PHY_256_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_256_REGOFF) |
| #define HWIO_DDR_PHY_256_PHY_DQ_DM_SWIZZLE0_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_256_PHY_DQ_DM_SWIZZLE0_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_257_REGOFF 0x404 |
| #define HWIO_DDR_PHY_257_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_257_REGOFF) |
| #define HWIO_DDR_PHY_257_PHY_DQ_DM_SWIZZLE1_2_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_257_PHY_DQ_DM_SWIZZLE1_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_257_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_257_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_257_PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_257_PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_257_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_257_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_257_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_257_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_258_REGOFF 0x408 |
| #define HWIO_DDR_PHY_258_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_258_REGOFF) |
| #define HWIO_DDR_PHY_258_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_258_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_258_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_258_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_258_PHY_BYPASS_TWO_CYC_PREAMBLE_2_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_258_PHY_BYPASS_TWO_CYC_PREAMBLE_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_258_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_258_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_258_PHY_CLK_BYPASS_OVERRIDE_2_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_258_PHY_CLK_BYPASS_OVERRIDE_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_258_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_258_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_259_REGOFF 0x40c |
| #define HWIO_DDR_PHY_259_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_259_REGOFF) |
| #define HWIO_DDR_PHY_259_PHY_SW_WRDQ0_SHIFT_2_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_259_PHY_SW_WRDQ0_SHIFT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_259_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_259_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_259_PHY_SW_WRDQ1_SHIFT_2_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_259_PHY_SW_WRDQ1_SHIFT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_259_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_259_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_259_PHY_SW_WRDQ2_SHIFT_2_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_259_PHY_SW_WRDQ2_SHIFT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_259_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_259_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_259_PHY_SW_WRDQ3_SHIFT_2_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_259_PHY_SW_WRDQ3_SHIFT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_259_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_259_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_260_REGOFF 0x410 |
| #define HWIO_DDR_PHY_260_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_260_REGOFF) |
| #define HWIO_DDR_PHY_260_PHY_SW_WRDQ4_SHIFT_2_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_260_PHY_SW_WRDQ4_SHIFT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_260_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_260_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_260_PHY_SW_WRDQ5_SHIFT_2_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_260_PHY_SW_WRDQ5_SHIFT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_260_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_260_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_260_PHY_SW_WRDQ6_SHIFT_2_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_260_PHY_SW_WRDQ6_SHIFT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_260_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_260_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_260_PHY_SW_WRDQ7_SHIFT_2_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_260_PHY_SW_WRDQ7_SHIFT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_260_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_260_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_261_REGOFF 0x414 |
| #define HWIO_DDR_PHY_261_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_261_REGOFF) |
| #define HWIO_DDR_PHY_261_PHY_SW_WRDM_SHIFT_2_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_261_PHY_SW_WRDM_SHIFT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_261_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_261_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_261_PHY_SW_WRDQS_SHIFT_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_261_PHY_SW_WRDQS_SHIFT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_261_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_261_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_261_PHY_DQ_TSEL_ENABLE_2_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_261_PHY_DQ_TSEL_ENABLE_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_261_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_261_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_261_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_261_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_262_REGOFF 0x418 |
| #define HWIO_DDR_PHY_262_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_262_REGOFF) |
| #define HWIO_DDR_PHY_262_PHY_DQ_TSEL_SELECT_2_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_262_PHY_DQ_TSEL_SELECT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_262_PHY_DQS_TSEL_ENABLE_2_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_262_PHY_DQS_TSEL_ENABLE_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_262_RESERVED_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_262_RESERVED_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_263_REGOFF 0x41c |
| #define HWIO_DDR_PHY_263_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_263_REGOFF) |
| #define HWIO_DDR_PHY_263_PHY_DQS_TSEL_SELECT_2_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_263_PHY_DQS_TSEL_SELECT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_263_PHY_TWO_CYC_PREAMBLE_2_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_263_PHY_TWO_CYC_PREAMBLE_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_263_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_263_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_264_REGOFF 0x420 |
| #define HWIO_DDR_PHY_264_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_264_REGOFF) |
| #define HWIO_DDR_PHY_264_PHY_DBI_MODE_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_264_PHY_DBI_MODE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_264_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_264_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_264_PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_264_PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_264_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_264_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_264_PHY_LP4_BOOT_RDDATA_EN_DLY_2_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_264_PHY_LP4_BOOT_RDDATA_EN_DLY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_264_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_264_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_264_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_264_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_264_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_264_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_265_REGOFF 0x424 |
| #define HWIO_DDR_PHY_265_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_265_REGOFF) |
| #define HWIO_DDR_PHY_265_PHY_LP4_BOOT_RPTR_UPDATE_2_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_265_PHY_LP4_BOOT_RPTR_UPDATE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_265_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_265_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_265_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_265_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_265_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_265_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_265_PHY_LPBK_CONTROL_2_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_265_PHY_LPBK_CONTROL_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_265_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_265_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_266_REGOFF 0x428 |
| #define HWIO_DDR_PHY_266_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_266_REGOFF) |
| #define HWIO_DDR_PHY_266_PHY_LPBK_DFX_TIMEOUT_EN_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_266_PHY_LPBK_DFX_TIMEOUT_EN_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_266_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_266_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_266_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_266_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_267_REGOFF 0x42c |
| #define HWIO_DDR_PHY_267_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_267_REGOFF) |
| #define HWIO_DDR_PHY_267_PHY_AUTO_TIMING_MARGIN_CONTROL_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_267_PHY_AUTO_TIMING_MARGIN_CONTROL_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_268_REGOFF 0x430 |
| #define HWIO_DDR_PHY_268_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_268_REGOFF) |
| #define HWIO_DDR_PHY_268_PHY_AUTO_TIMING_MARGIN_OBS_2_FLDMASK (0xfffffff) |
| #define HWIO_DDR_PHY_268_PHY_AUTO_TIMING_MARGIN_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_268_RESERVED_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_268_RESERVED_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_269_REGOFF 0x434 |
| #define HWIO_DDR_PHY_269_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_269_REGOFF) |
| #define HWIO_DDR_PHY_269_PHY_SLICE_PWR_RDC_DISABLE_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_269_PHY_SLICE_PWR_RDC_DISABLE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_269_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_269_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_269_PHY_PRBS_PATTERN_START_2_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_269_PHY_PRBS_PATTERN_START_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_269_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_269_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_269_PHY_PRBS_PATTERN_MASK_2_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_269_PHY_PRBS_PATTERN_MASK_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_269_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_269_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_270_REGOFF 0x438 |
| #define HWIO_DDR_PHY_270_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_270_REGOFF) |
| #define HWIO_DDR_PHY_270_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_270_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_270_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_270_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_270_PHY_GATE_ERROR_DELAY_SELECT_2_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_270_PHY_GATE_ERROR_DELAY_SELECT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_270_RESERVED1_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_270_RESERVED1_FLDSHFT (21) |
| #define HWIO_DDR_PHY_270_SC_PHY_SNAP_OBS_REGS_2_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_270_SC_PHY_SNAP_OBS_REGS_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_270_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_270_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_271_REGOFF 0x43c |
| #define HWIO_DDR_PHY_271_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_271_REGOFF) |
| #define HWIO_DDR_PHY_271_PHY_GATE_SMPL1_SLAVE_DELAY_2_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_271_PHY_GATE_SMPL1_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_271_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_271_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_271_PHY_LPDDR_2_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_271_PHY_LPDDR_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_271_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_271_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_271_PHY_LPDDR_TYPE_2_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_271_PHY_LPDDR_TYPE_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_271_RESERVED2_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_271_RESERVED2_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_272_REGOFF 0x440 |
| #define HWIO_DDR_PHY_272_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_272_REGOFF) |
| #define HWIO_DDR_PHY_272_PHY_GATE_SMPL2_SLAVE_DELAY_2_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_272_PHY_GATE_SMPL2_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_272_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_272_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_272_ON_FLY_GATE_ADJUST_EN_2_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_272_ON_FLY_GATE_ADJUST_EN_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_272_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_272_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_272_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_272_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_273_REGOFF 0x444 |
| #define HWIO_DDR_PHY_273_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_273_REGOFF) |
| #define HWIO_DDR_PHY_273_PHY_GATE_TRACKING_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_273_PHY_GATE_TRACKING_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_274_REGOFF 0x448 |
| #define HWIO_DDR_PHY_274_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_274_REGOFF) |
| #define HWIO_DDR_PHY_274_PHY_LP4_PST_AMBLE_2_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_274_PHY_LP4_PST_AMBLE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_274_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_274_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_274_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_274_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_275_REGOFF 0x44c |
| #define HWIO_DDR_PHY_275_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_275_REGOFF) |
| #define HWIO_DDR_PHY_275_PHY_LP4_RDLVL_PATT8_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_275_PHY_LP4_RDLVL_PATT8_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_276_REGOFF 0x450 |
| #define HWIO_DDR_PHY_276_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_276_REGOFF) |
| #define HWIO_DDR_PHY_276_PHY_LP4_RDLVL_PATT9_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_276_PHY_LP4_RDLVL_PATT9_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_277_REGOFF 0x454 |
| #define HWIO_DDR_PHY_277_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_277_REGOFF) |
| #define HWIO_DDR_PHY_277_PHY_LP4_RDLVL_PATT10_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_277_PHY_LP4_RDLVL_PATT10_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_278_REGOFF 0x458 |
| #define HWIO_DDR_PHY_278_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_278_REGOFF) |
| #define HWIO_DDR_PHY_278_PHY_LP4_RDLVL_PATT11_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_278_PHY_LP4_RDLVL_PATT11_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_279_REGOFF 0x45c |
| #define HWIO_DDR_PHY_279_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_279_REGOFF) |
| #define HWIO_DDR_PHY_279_PHY_SLAVE_LOOP_CNT_UPDATE_2_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_279_PHY_SLAVE_LOOP_CNT_UPDATE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_279_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_279_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_279_PHY_SW_FIFO_PTR_RST_DISABLE_2_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_279_PHY_SW_FIFO_PTR_RST_DISABLE_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_279_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_279_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_279_PHY_MASTER_DLY_LOCK_OBS_SELECT_2_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_279_PHY_MASTER_DLY_LOCK_OBS_SELECT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_279_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_279_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_279_PHY_RDDQ_ENC_OBS_SELECT_2_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_279_PHY_RDDQ_ENC_OBS_SELECT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_279_RESERVED3_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_279_RESERVED3_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_280_REGOFF 0x460 |
| #define HWIO_DDR_PHY_280_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_280_REGOFF) |
| #define HWIO_DDR_PHY_280_PHY_RDDQS_DQ_ENC_OBS_SELECT_2_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_280_PHY_RDDQS_DQ_ENC_OBS_SELECT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_280_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_280_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_280_PHY_WR_ENC_OBS_SELECT_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_280_PHY_WR_ENC_OBS_SELECT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_280_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_280_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_280_PHY_WR_SHIFT_OBS_SELECT_2_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_280_PHY_WR_SHIFT_OBS_SELECT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_280_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_280_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_280_PHY_FIFO_PTR_OBS_SELECT_2_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_280_PHY_FIFO_PTR_OBS_SELECT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_280_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_280_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_281_REGOFF 0x464 |
| #define HWIO_DDR_PHY_281_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_281_REGOFF) |
| #define HWIO_DDR_PHY_281_PHY_LVL_DEBUG_MODE_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_281_PHY_LVL_DEBUG_MODE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_281_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_281_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_281_SC_PHY_LVL_DEBUG_CONT_2_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_281_SC_PHY_LVL_DEBUG_CONT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_281_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_281_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_281_PHY_WRLVL_CAPTURE_CNT_2_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_281_PHY_WRLVL_CAPTURE_CNT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_281_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_281_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_281_PHY_WRLVL_UPDT_WAIT_CNT_2_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_281_PHY_WRLVL_UPDT_WAIT_CNT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_281_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_281_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_282_REGOFF 0x468 |
| #define HWIO_DDR_PHY_282_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_282_REGOFF) |
| #define HWIO_DDR_PHY_282_PHY_GTLVL_CAPTURE_CNT_2_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_282_PHY_GTLVL_CAPTURE_CNT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_282_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_282_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_282_PHY_GTLVL_UPDT_WAIT_CNT_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_282_PHY_GTLVL_UPDT_WAIT_CNT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_282_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_282_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_282_PHY_RDLVL_CAPTURE_CNT_2_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_282_PHY_RDLVL_CAPTURE_CNT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_282_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_282_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_282_PHY_RDLVL_UPDT_WAIT_CNT_2_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_282_PHY_RDLVL_UPDT_WAIT_CNT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_282_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_282_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_283_REGOFF 0x46c |
| #define HWIO_DDR_PHY_283_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_283_REGOFF) |
| #define HWIO_DDR_PHY_283_PHY_RDLVL_OP_MODE_2_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_283_PHY_RDLVL_OP_MODE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_283_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_283_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_283_PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_283_PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_283_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_283_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_283_PHY_RDLVL_DATA_MASK_2_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_283_PHY_RDLVL_DATA_MASK_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_283_PHY_WDQLVL_BURST_CNT_2_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_283_PHY_WDQLVL_BURST_CNT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_283_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_283_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_284_REGOFF 0x470 |
| #define HWIO_DDR_PHY_284_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_284_REGOFF) |
| #define HWIO_DDR_PHY_284_PHY_WDQLVL_PATT_2_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_284_PHY_WDQLVL_PATT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_284_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_284_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_284_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_284_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_284_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_284_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_284_PHY_WDQLVL_UPDT_WAIT_CNT_2_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_284_PHY_WDQLVL_UPDT_WAIT_CNT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_284_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_284_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_285_REGOFF 0x474 |
| #define HWIO_DDR_PHY_285_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_285_REGOFF) |
| #define HWIO_DDR_PHY_285_PHY_WDQLVL_DQDM_OBS_SELECT_2_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_285_PHY_WDQLVL_DQDM_OBS_SELECT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_285_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_285_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_285_PHY_WDQLVL_QTR_DLY_STEP_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_285_PHY_WDQLVL_QTR_DLY_STEP_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_285_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_285_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_285_SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_285_SC_PHY_WDQLVL_CLR_PREV_RESULTS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_285_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_285_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_285_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_285_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_286_REGOFF 0x478 |
| #define HWIO_DDR_PHY_286_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_286_REGOFF) |
| #define HWIO_DDR_PHY_286_PHY_WDQLVL_DATADM_MASK_2_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_286_PHY_WDQLVL_DATADM_MASK_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_286_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_286_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_286_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_286_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_287_REGOFF 0x47c |
| #define HWIO_DDR_PHY_287_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_287_REGOFF) |
| #define HWIO_DDR_PHY_287_PHY_USER_PATT0_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_287_PHY_USER_PATT0_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_288_REGOFF 0x480 |
| #define HWIO_DDR_PHY_288_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_288_REGOFF) |
| #define HWIO_DDR_PHY_288_PHY_USER_PATT1_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_288_PHY_USER_PATT1_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_289_REGOFF 0x484 |
| #define HWIO_DDR_PHY_289_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_289_REGOFF) |
| #define HWIO_DDR_PHY_289_PHY_USER_PATT2_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_289_PHY_USER_PATT2_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_290_REGOFF 0x488 |
| #define HWIO_DDR_PHY_290_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_290_REGOFF) |
| #define HWIO_DDR_PHY_290_PHY_USER_PATT3_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_290_PHY_USER_PATT3_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_291_REGOFF 0x48c |
| #define HWIO_DDR_PHY_291_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_291_REGOFF) |
| #define HWIO_DDR_PHY_291_PHY_USER_PATT4_2_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_291_PHY_USER_PATT4_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_291_PHY_CALVL_VREF_DRIVING_SLICE_2_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_291_PHY_CALVL_VREF_DRIVING_SLICE_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_291_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_291_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_291_SC_PHY_MANUAL_CLEAR_2_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_291_SC_PHY_MANUAL_CLEAR_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_291_RESERVED1_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_291_RESERVED1_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_292_REGOFF 0x490 |
| #define HWIO_DDR_PHY_292_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_292_REGOFF) |
| #define HWIO_DDR_PHY_292_PHY_FIFO_PTR_OBS_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_292_PHY_FIFO_PTR_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_292_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_292_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_293_REGOFF 0x494 |
| #define HWIO_DDR_PHY_293_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_293_REGOFF) |
| #define HWIO_DDR_PHY_293_PHY_LPBK_RESULT_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_293_PHY_LPBK_RESULT_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_294_REGOFF 0x498 |
| #define HWIO_DDR_PHY_294_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_294_REGOFF) |
| #define HWIO_DDR_PHY_294_PHY_LPBK_ERROR_COUNT_OBS_2_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_294_PHY_LPBK_ERROR_COUNT_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_294_PHY_MASTER_DLY_LOCK_OBS_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_294_PHY_MASTER_DLY_LOCK_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_294_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_294_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_295_REGOFF 0x49c |
| #define HWIO_DDR_PHY_295_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_295_REGOFF) |
| #define HWIO_DDR_PHY_295_PHY_RDDQ_SLV_DLY_ENC_OBS_2_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_295_PHY_RDDQ_SLV_DLY_ENC_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_295_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_295_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_295_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_295_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_295_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_295_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_295_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_FLDMASK \ |
| (0xff0000) |
| #define HWIO_DDR_PHY_295_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_295_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_FLDMASK \ |
| (0xff000000) |
| #define HWIO_DDR_PHY_295_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_296_REGOFF 0x4a0 |
| #define HWIO_DDR_PHY_296_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_296_REGOFF) |
| #define HWIO_DDR_PHY_296_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_296_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_296_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_296_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_296_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_FLDMASK (0x7f0000) |
| #define HWIO_DDR_PHY_296_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_296_RESERVED1_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_296_RESERVED1_FLDSHFT (23) |
| #define HWIO_DDR_PHY_296_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_296_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_297_REGOFF 0x4a4 |
| #define HWIO_DDR_PHY_297_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_297_REGOFF) |
| #define HWIO_DDR_PHY_297_PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_297_PHY_WR_ADDER_SLV_DLY_ENC_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_297_PHY_WR_SHIFT_OBS_2_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_297_PHY_WR_SHIFT_OBS_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_297_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_297_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_297_PHY_WRLVL_HARD0_DELAY_OBS_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_297_PHY_WRLVL_HARD0_DELAY_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_297_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_297_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_298_REGOFF 0x4a8 |
| #define HWIO_DDR_PHY_298_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_298_REGOFF) |
| #define HWIO_DDR_PHY_298_PHY_WRLVL_HARD1_DELAY_OBS_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_298_PHY_WRLVL_HARD1_DELAY_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_298_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_298_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_298_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_298_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_299_REGOFF 0x4ac |
| #define HWIO_DDR_PHY_299_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_299_REGOFF) |
| #define HWIO_DDR_PHY_299_PHY_WRLVL_STATUS_OBS_2_FLDMASK (0x1ffff) |
| #define HWIO_DDR_PHY_299_PHY_WRLVL_STATUS_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_299_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_299_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_299_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_299_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_300_REGOFF 0x4b0 |
| #define HWIO_DDR_PHY_300_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_300_REGOFF) |
| #define HWIO_DDR_PHY_300_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_300_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_300_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_300_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_300_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_300_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_300_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_300_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_301_REGOFF 0x4b4 |
| #define HWIO_DDR_PHY_301_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_301_REGOFF) |
| #define HWIO_DDR_PHY_301_PHY_GTLVL_HARD0_DELAY_OBS_2_FLDMASK (0x3fff) |
| #define HWIO_DDR_PHY_301_PHY_GTLVL_HARD0_DELAY_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_301_RESERVED_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_301_RESERVED_FLDSHFT (14) |
| #define HWIO_DDR_PHY_301_PHY_GTLVL_HARD1_DELAY_OBS_2_FLDMASK (0x3fff0000) |
| #define HWIO_DDR_PHY_301_PHY_GTLVL_HARD1_DELAY_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_301_RESERVED1_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_301_RESERVED1_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_302_REGOFF 0x4b8 |
| #define HWIO_DDR_PHY_302_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_302_REGOFF) |
| #define HWIO_DDR_PHY_302_PHY_GTLVL_STATUS_OBS_2_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_302_PHY_GTLVL_STATUS_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_302_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_302_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_302_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_302_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_303_REGOFF 0x4bc |
| #define HWIO_DDR_PHY_303_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_303_REGOFF) |
| #define HWIO_DDR_PHY_303_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_303_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_303_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_303_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_303_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_303_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_303_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_303_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_304_REGOFF 0x4c0 |
| #define HWIO_DDR_PHY_304_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_304_REGOFF) |
| #define HWIO_DDR_PHY_304_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_304_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_304_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_304_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_304_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_304_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_305_REGOFF 0x4c4 |
| #define HWIO_DDR_PHY_305_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_305_REGOFF) |
| #define HWIO_DDR_PHY_305_PHY_RDLVL_STATUS_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_305_PHY_RDLVL_STATUS_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_306_REGOFF 0x4c8 |
| #define HWIO_DDR_PHY_306_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_306_REGOFF) |
| #define HWIO_DDR_PHY_306_PHY_WDQLVL_DQDM_LE_DLY_OBS_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_306_PHY_WDQLVL_DQDM_LE_DLY_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_306_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_306_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_306_PHY_WDQLVL_DQDM_TE_DLY_OBS_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_306_PHY_WDQLVL_DQDM_TE_DLY_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_306_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_306_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_307_REGOFF 0x4cc |
| #define HWIO_DDR_PHY_307_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_307_REGOFF) |
| #define HWIO_DDR_PHY_307_PHY_WDQLVL_STATUS_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_307_PHY_WDQLVL_STATUS_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_308_REGOFF 0x4d0 |
| #define HWIO_DDR_PHY_308_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_308_REGOFF) |
| #define HWIO_DDR_PHY_308_PHY_DDL_MODE_2_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_308_PHY_DDL_MODE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_308_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_308_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_308_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_308_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_309_REGOFF 0x4d4 |
| #define HWIO_DDR_PHY_309_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_309_REGOFF) |
| #define HWIO_DDR_PHY_309_PHY_DDL_TEST_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_309_PHY_DDL_TEST_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_310_REGOFF 0x4d8 |
| #define HWIO_DDR_PHY_310_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_310_REGOFF) |
| #define HWIO_DDR_PHY_310_PHY_DDL_TEST_MSTR_DLY_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_310_PHY_DDL_TEST_MSTR_DLY_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_311_REGOFF 0x4dc |
| #define HWIO_DDR_PHY_311_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_311_REGOFF) |
| #define HWIO_DDR_PHY_311_PHY_DDL_TRACK_UPD_THRESHOLD_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_311_PHY_DDL_TRACK_UPD_THRESHOLD_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_311_PHY_LP4_WDQS_OE_EXTEND_2_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_311_PHY_LP4_WDQS_OE_EXTEND_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_311_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_311_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_311_SC_PHY_RX_CAL_START_2_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_311_SC_PHY_RX_CAL_START_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_311_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_311_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_311_PHY_RX_CAL_OVERRIDE_2_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_311_PHY_RX_CAL_OVERRIDE_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_311_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_311_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_312_REGOFF 0x4e0 |
| #define HWIO_DDR_PHY_312_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_312_REGOFF) |
| #define HWIO_DDR_PHY_312_PHY_RX_CAL_SAMPLE_WAIT_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_312_PHY_RX_CAL_SAMPLE_WAIT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_312_PHY_RX_CAL_DQ0_2_FLDMASK (0xfff00) |
| #define HWIO_DDR_PHY_312_PHY_RX_CAL_DQ0_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_312_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_312_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_312_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_312_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_313_REGOFF 0x4e4 |
| #define HWIO_DDR_PHY_313_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_313_REGOFF) |
| #define HWIO_DDR_PHY_313_PHY_RX_CAL_DQ1_2_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_313_PHY_RX_CAL_DQ1_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_313_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_313_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_313_PHY_RX_CAL_DQ2_2_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_313_PHY_RX_CAL_DQ2_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_313_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_313_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_314_REGOFF 0x4e8 |
| #define HWIO_DDR_PHY_314_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_314_REGOFF) |
| #define HWIO_DDR_PHY_314_PHY_RX_CAL_DQ3_2_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_314_PHY_RX_CAL_DQ3_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_314_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_314_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_314_PHY_RX_CAL_DQ4_2_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_314_PHY_RX_CAL_DQ4_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_314_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_314_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_315_REGOFF 0x4ec |
| #define HWIO_DDR_PHY_315_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_315_REGOFF) |
| #define HWIO_DDR_PHY_315_PHY_RX_CAL_DQ5_2_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_315_PHY_RX_CAL_DQ5_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_315_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_315_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_315_PHY_RX_CAL_DQ6_2_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_315_PHY_RX_CAL_DQ6_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_315_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_315_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_316_REGOFF 0x4f0 |
| #define HWIO_DDR_PHY_316_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_316_REGOFF) |
| #define HWIO_DDR_PHY_316_PHY_RX_CAL_DQ7_2_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_316_PHY_RX_CAL_DQ7_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_316_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_316_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_316_PHY_RX_CAL_DM_2_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_316_PHY_RX_CAL_DM_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_316_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_316_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_317_REGOFF 0x4f4 |
| #define HWIO_DDR_PHY_317_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_317_REGOFF) |
| #define HWIO_DDR_PHY_317_PHY_RX_CAL_DQS_2_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_317_PHY_RX_CAL_DQS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_317_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_317_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_317_PHY_RX_CAL_FDBK_2_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_317_PHY_RX_CAL_FDBK_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_317_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_317_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_318_REGOFF 0x4f8 |
| #define HWIO_DDR_PHY_318_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_318_REGOFF) |
| #define HWIO_DDR_PHY_318_PHY_RX_CAL_OBS_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_318_PHY_RX_CAL_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_318_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_318_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_318_PHY_RX_CAL_LOCK_OBS_2_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_318_PHY_RX_CAL_LOCK_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_318_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_318_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_319_REGOFF 0x4fc |
| #define HWIO_DDR_PHY_319_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_319_REGOFF) |
| #define HWIO_DDR_PHY_319_PHY_RX_CAL_DISABLE_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_319_PHY_RX_CAL_DISABLE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_319_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_319_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_319_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_319_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_320_REGOFF 0x500 |
| #define HWIO_DDR_PHY_320_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_320_REGOFF) |
| #define HWIO_DDR_PHY_320_PHY_CLK_WRDQ0_SLAVE_DELAY_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_320_PHY_CLK_WRDQ0_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_320_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_320_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_320_PHY_CLK_WRDQ1_SLAVE_DELAY_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_320_PHY_CLK_WRDQ1_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_320_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_320_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_321_REGOFF 0x504 |
| #define HWIO_DDR_PHY_321_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_321_REGOFF) |
| #define HWIO_DDR_PHY_321_PHY_CLK_WRDQ2_SLAVE_DELAY_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_321_PHY_CLK_WRDQ2_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_321_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_321_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_321_PHY_CLK_WRDQ3_SLAVE_DELAY_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_321_PHY_CLK_WRDQ3_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_321_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_321_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_322_REGOFF 0x508 |
| #define HWIO_DDR_PHY_322_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_322_REGOFF) |
| #define HWIO_DDR_PHY_322_PHY_CLK_WRDQ4_SLAVE_DELAY_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_322_PHY_CLK_WRDQ4_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_322_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_322_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_322_PHY_CLK_WRDQ5_SLAVE_DELAY_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_322_PHY_CLK_WRDQ5_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_322_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_322_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_323_REGOFF 0x50c |
| #define HWIO_DDR_PHY_323_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_323_REGOFF) |
| #define HWIO_DDR_PHY_323_PHY_CLK_WRDQ6_SLAVE_DELAY_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_323_PHY_CLK_WRDQ6_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_323_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_323_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_323_PHY_CLK_WRDQ7_SLAVE_DELAY_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_323_PHY_CLK_WRDQ7_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_323_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_323_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_324_REGOFF 0x510 |
| #define HWIO_DDR_PHY_324_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_324_REGOFF) |
| #define HWIO_DDR_PHY_324_PHY_CLK_WRDM_SLAVE_DELAY_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_324_PHY_CLK_WRDM_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_324_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_324_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_324_PHY_CLK_WRDQS_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_324_PHY_CLK_WRDQS_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_324_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_324_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_325_REGOFF 0x514 |
| #define HWIO_DDR_PHY_325_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_325_REGOFF) |
| #define HWIO_DDR_PHY_325_PHY_WRLVL_THRESHOLD_ADJUST_2_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_325_PHY_WRLVL_THRESHOLD_ADJUST_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_325_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_325_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_325_PHY_RDDQ0_SLAVE_DELAY_2_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_325_PHY_RDDQ0_SLAVE_DELAY_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_325_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_325_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_325_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_325_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_326_REGOFF 0x518 |
| #define HWIO_DDR_PHY_326_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_326_REGOFF) |
| #define HWIO_DDR_PHY_326_PHY_RDDQ1_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_326_PHY_RDDQ1_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_326_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_326_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_326_PHY_RDDQ2_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_326_PHY_RDDQ2_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_326_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_326_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_327_REGOFF 0x51c |
| #define HWIO_DDR_PHY_327_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_327_REGOFF) |
| #define HWIO_DDR_PHY_327_PHY_RDDQ3_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_327_PHY_RDDQ3_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_327_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_327_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_327_PHY_RDDQ4_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_327_PHY_RDDQ4_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_327_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_327_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_328_REGOFF 0x520 |
| #define HWIO_DDR_PHY_328_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_328_REGOFF) |
| #define HWIO_DDR_PHY_328_PHY_RDDQ5_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_328_PHY_RDDQ5_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_328_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_328_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_328_PHY_RDDQ6_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_328_PHY_RDDQ6_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_328_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_328_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_329_REGOFF 0x524 |
| #define HWIO_DDR_PHY_329_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_329_REGOFF) |
| #define HWIO_DDR_PHY_329_PHY_RDDQ7_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_329_PHY_RDDQ7_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_329_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_329_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_329_PHY_RDDM_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_329_PHY_RDDM_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_329_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_329_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_330_REGOFF 0x528 |
| #define HWIO_DDR_PHY_330_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_330_REGOFF) |
| #define HWIO_DDR_PHY_330_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_330_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_330_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_330_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_330_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_330_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_330_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_330_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_331_REGOFF 0x52c |
| #define HWIO_DDR_PHY_331_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_331_REGOFF) |
| #define HWIO_DDR_PHY_331_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_331_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_331_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_331_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_331_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_331_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_331_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_331_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_332_REGOFF 0x530 |
| #define HWIO_DDR_PHY_332_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_332_REGOFF) |
| #define HWIO_DDR_PHY_332_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_332_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_332_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_332_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_332_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_332_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_332_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_332_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_333_REGOFF 0x534 |
| #define HWIO_DDR_PHY_333_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_333_REGOFF) |
| #define HWIO_DDR_PHY_333_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_333_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_333_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_333_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_333_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_333_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_333_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_333_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_334_REGOFF 0x538 |
| #define HWIO_DDR_PHY_334_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_334_REGOFF) |
| #define HWIO_DDR_PHY_334_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_334_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_334_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_334_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_334_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_334_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_334_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_334_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_335_REGOFF 0x53c |
| #define HWIO_DDR_PHY_335_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_335_REGOFF) |
| #define HWIO_DDR_PHY_335_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_335_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_335_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_335_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_335_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_335_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_335_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_335_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_336_REGOFF 0x540 |
| #define HWIO_DDR_PHY_336_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_336_REGOFF) |
| #define HWIO_DDR_PHY_336_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_336_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_336_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_336_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_336_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_336_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_336_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_336_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_337_REGOFF 0x544 |
| #define HWIO_DDR_PHY_337_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_337_REGOFF) |
| #define HWIO_DDR_PHY_337_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_337_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_337_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_337_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_337_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_337_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_337_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_337_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_338_REGOFF 0x548 |
| #define HWIO_DDR_PHY_338_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_338_REGOFF) |
| #define HWIO_DDR_PHY_338_PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_338_PHY_RDDQS_DM_RISE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_338_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_338_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_338_PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_338_PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_338_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_338_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_339_REGOFF 0x54c |
| #define HWIO_DDR_PHY_339_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_339_REGOFF) |
| #define HWIO_DDR_PHY_339_PHY_RDDQS_GATE_SLAVE_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_339_PHY_RDDQS_GATE_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_339_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_339_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_339_PHY_RDDQS_LATENCY_ADJUST_2_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_339_PHY_RDDQS_LATENCY_ADJUST_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_339_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_339_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_339_PHY_WRITE_PATH_LAT_ADD_2_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_339_PHY_WRITE_PATH_LAT_ADD_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_339_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_339_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_340_REGOFF 0x550 |
| #define HWIO_DDR_PHY_340_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_340_REGOFF) |
| #define HWIO_DDR_PHY_340_PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_340_PHY_WRLVL_DELAY_EARLY_THRESHOLD_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_340_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_340_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_340_PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_340_PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_340_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_340_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_341_REGOFF 0x554 |
| #define HWIO_DDR_PHY_341_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_341_REGOFF) |
| #define HWIO_DDR_PHY_341_PHY_WRLVL_EARLY_FORCE_0_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_341_PHY_WRLVL_EARLY_FORCE_0_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_341_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_341_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_341_PHY_GTLVL_RDDQS_SLV_DLY_START_2_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_341_PHY_GTLVL_RDDQS_SLV_DLY_START_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_341_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_341_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_341_PHY_GTLVL_LAT_ADJ_START_2_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_341_PHY_GTLVL_LAT_ADJ_START_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_341_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_341_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_342_REGOFF 0x558 |
| #define HWIO_DDR_PHY_342_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_342_REGOFF) |
| #define HWIO_DDR_PHY_342_PHY_WDQLVL_DQDM_SLV_DLY_START_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_342_PHY_WDQLVL_DQDM_SLV_DLY_START_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_342_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_342_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_342_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_342_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_342_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_342_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_343_REGOFF 0x55c |
| #define HWIO_DDR_PHY_343_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_343_REGOFF) |
| #define HWIO_DDR_PHY_343_PHY_FDBK_PWR_CTRL_2_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_343_PHY_FDBK_PWR_CTRL_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_343_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_343_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_343_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_343_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_344_REGOFF 0x560 |
| #define HWIO_DDR_PHY_344_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_344_REGOFF) |
| #define HWIO_DDR_PHY_344_PHY_DQ_OE_TIMING_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_344_PHY_DQ_OE_TIMING_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_344_PHY_DQ_TSEL_RD_TIMING_2_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_344_PHY_DQ_TSEL_RD_TIMING_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_344_PHY_DQ_TSEL_WR_TIMING_2_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_344_PHY_DQ_TSEL_WR_TIMING_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_344_PHY_DQS_OE_TIMING_2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_344_PHY_DQS_OE_TIMING_2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_345_REGOFF 0x564 |
| #define HWIO_DDR_PHY_345_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_345_REGOFF) |
| #define HWIO_DDR_PHY_345_PHY_DQS_TSEL_RD_TIMING_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_345_PHY_DQS_TSEL_RD_TIMING_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_345_PHY_DQS_TSEL_WR_TIMING_2_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_345_PHY_DQS_TSEL_WR_TIMING_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_345_PHY_DQ_IE_TIMING_2_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_345_PHY_DQ_IE_TIMING_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_345_PHY_DQS_IE_TIMING_2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_345_PHY_DQS_IE_TIMING_2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_346_REGOFF 0x568 |
| #define HWIO_DDR_PHY_346_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_346_REGOFF) |
| #define HWIO_DDR_PHY_346_PHY_RDDATA_EN_IE_DLY_2_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_346_PHY_RDDATA_EN_IE_DLY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_346_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_346_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_346_PHY_IE_MODE_2_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_346_PHY_IE_MODE_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_346_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_346_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_346_PHY_RDDATA_EN_DLY_2_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_346_PHY_RDDATA_EN_DLY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_346_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_346_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_346_PHY_RDDATA_EN_TSEL_DLY_2_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_346_PHY_RDDATA_EN_TSEL_DLY_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_346_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_346_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_347_REGOFF 0x56c |
| #define HWIO_DDR_PHY_347_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_347_REGOFF) |
| #define HWIO_DDR_PHY_347_PHY_SW_MASTER_MODE_2_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_347_PHY_SW_MASTER_MODE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_347_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_347_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_347_PHY_MASTER_DELAY_START_2_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_347_PHY_MASTER_DELAY_START_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_347_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_347_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_347_PHY_MASTER_DELAY_STEP_2_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_347_PHY_MASTER_DELAY_STEP_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_347_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_347_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_348_REGOFF 0x570 |
| #define HWIO_DDR_PHY_348_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_348_REGOFF) |
| #define HWIO_DDR_PHY_348_PHY_MASTER_DELAY_WAIT_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_348_PHY_MASTER_DELAY_WAIT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_348_PHY_MASTER_DELAY_HALF_MEASURE_2_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_348_PHY_MASTER_DELAY_HALF_MEASURE_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_348_PHY_RPTR_UPDATE_2_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_348_PHY_RPTR_UPDATE_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_348_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_348_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_348_PHY_WRLVL_DLY_STEP_2_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_348_PHY_WRLVL_DLY_STEP_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_348_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_348_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_349_REGOFF 0x574 |
| #define HWIO_DDR_PHY_349_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_349_REGOFF) |
| #define HWIO_DDR_PHY_349_PHY_WRLVL_RESP_WAIT_CNT_2_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_349_PHY_WRLVL_RESP_WAIT_CNT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_349_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_349_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_349_PHY_GTLVL_DLY_STEP_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_349_PHY_GTLVL_DLY_STEP_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_349_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_349_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_349_PHY_GTLVL_RESP_WAIT_CNT_2_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_349_PHY_GTLVL_RESP_WAIT_CNT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_349_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_349_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_349_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_349_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_350_REGOFF 0x578 |
| #define HWIO_DDR_PHY_350_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_350_REGOFF) |
| #define HWIO_DDR_PHY_350_PHY_GTLVL_BACK_STEP_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_350_PHY_GTLVL_BACK_STEP_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_350_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_350_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_350_PHY_GTLVL_FINAL_STEP_2_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_350_PHY_GTLVL_FINAL_STEP_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_350_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_350_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_351_REGOFF 0x57c |
| #define HWIO_DDR_PHY_351_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_351_REGOFF) |
| #define HWIO_DDR_PHY_351_PHY_WDQLVL_DLY_STEP_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_351_PHY_WDQLVL_DLY_STEP_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_351_PHY_RDLVL_DLY_STEP_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_351_PHY_RDLVL_DLY_STEP_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_351_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_351_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_351_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_351_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_352_REGOFF 0x580 |
| #define HWIO_DDR_PHY_352_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_352_REGOFF) |
| #define HWIO_DDR_PHY_352_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_352_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_353_REGOFF 0x584 |
| #define HWIO_DDR_PHY_353_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_353_REGOFF) |
| #define HWIO_DDR_PHY_353_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_353_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_354_REGOFF 0x588 |
| #define HWIO_DDR_PHY_354_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_354_REGOFF) |
| #define HWIO_DDR_PHY_354_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_354_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_355_REGOFF 0x58c |
| #define HWIO_DDR_PHY_355_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_355_REGOFF) |
| #define HWIO_DDR_PHY_355_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_355_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_356_REGOFF 0x590 |
| #define HWIO_DDR_PHY_356_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_356_REGOFF) |
| #define HWIO_DDR_PHY_356_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_356_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_357_REGOFF 0x594 |
| #define HWIO_DDR_PHY_357_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_357_REGOFF) |
| #define HWIO_DDR_PHY_357_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_357_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_358_REGOFF 0x598 |
| #define HWIO_DDR_PHY_358_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_358_REGOFF) |
| #define HWIO_DDR_PHY_358_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_358_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_359_REGOFF 0x59c |
| #define HWIO_DDR_PHY_359_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_359_REGOFF) |
| #define HWIO_DDR_PHY_359_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_359_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_360_REGOFF 0x5a0 |
| #define HWIO_DDR_PHY_360_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_360_REGOFF) |
| #define HWIO_DDR_PHY_360_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_360_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_361_REGOFF 0x5a4 |
| #define HWIO_DDR_PHY_361_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_361_REGOFF) |
| #define HWIO_DDR_PHY_361_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_361_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_362_REGOFF 0x5a8 |
| #define HWIO_DDR_PHY_362_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_362_REGOFF) |
| #define HWIO_DDR_PHY_362_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_362_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_363_REGOFF 0x5ac |
| #define HWIO_DDR_PHY_363_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_363_REGOFF) |
| #define HWIO_DDR_PHY_363_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_363_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_364_REGOFF 0x5b0 |
| #define HWIO_DDR_PHY_364_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_364_REGOFF) |
| #define HWIO_DDR_PHY_364_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_364_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_365_REGOFF 0x5b4 |
| #define HWIO_DDR_PHY_365_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_365_REGOFF) |
| #define HWIO_DDR_PHY_365_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_365_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_366_REGOFF 0x5b8 |
| #define HWIO_DDR_PHY_366_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_366_REGOFF) |
| #define HWIO_DDR_PHY_366_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_366_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_367_REGOFF 0x5bc |
| #define HWIO_DDR_PHY_367_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_367_REGOFF) |
| #define HWIO_DDR_PHY_367_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_367_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_368_REGOFF 0x5c0 |
| #define HWIO_DDR_PHY_368_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_368_REGOFF) |
| #define HWIO_DDR_PHY_368_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_368_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_369_REGOFF 0x5c4 |
| #define HWIO_DDR_PHY_369_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_369_REGOFF) |
| #define HWIO_DDR_PHY_369_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_369_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_370_REGOFF 0x5c8 |
| #define HWIO_DDR_PHY_370_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_370_REGOFF) |
| #define HWIO_DDR_PHY_370_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_370_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_371_REGOFF 0x5cc |
| #define HWIO_DDR_PHY_371_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_371_REGOFF) |
| #define HWIO_DDR_PHY_371_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_371_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_372_REGOFF 0x5d0 |
| #define HWIO_DDR_PHY_372_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_372_REGOFF) |
| #define HWIO_DDR_PHY_372_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_372_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_373_REGOFF 0x5d4 |
| #define HWIO_DDR_PHY_373_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_373_REGOFF) |
| #define HWIO_DDR_PHY_373_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_373_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_374_REGOFF 0x5d8 |
| #define HWIO_DDR_PHY_374_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_374_REGOFF) |
| #define HWIO_DDR_PHY_374_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_374_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_375_REGOFF 0x5dc |
| #define HWIO_DDR_PHY_375_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_375_REGOFF) |
| #define HWIO_DDR_PHY_375_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_375_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_376_REGOFF 0x5e0 |
| #define HWIO_DDR_PHY_376_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_376_REGOFF) |
| #define HWIO_DDR_PHY_376_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_376_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_377_REGOFF 0x5e4 |
| #define HWIO_DDR_PHY_377_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_377_REGOFF) |
| #define HWIO_DDR_PHY_377_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_377_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_378_REGOFF 0x5e8 |
| #define HWIO_DDR_PHY_378_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_378_REGOFF) |
| #define HWIO_DDR_PHY_378_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_378_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_379_REGOFF 0x5ec |
| #define HWIO_DDR_PHY_379_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_379_REGOFF) |
| #define HWIO_DDR_PHY_379_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_379_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_380_REGOFF 0x5f0 |
| #define HWIO_DDR_PHY_380_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_380_REGOFF) |
| #define HWIO_DDR_PHY_380_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_380_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_381_REGOFF 0x5f4 |
| #define HWIO_DDR_PHY_381_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_381_REGOFF) |
| #define HWIO_DDR_PHY_381_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_381_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_382_REGOFF 0x5f8 |
| #define HWIO_DDR_PHY_382_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_382_REGOFF) |
| #define HWIO_DDR_PHY_382_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_382_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_383_REGOFF 0x5fc |
| #define HWIO_DDR_PHY_383_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_383_REGOFF) |
| #define HWIO_DDR_PHY_383_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_383_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_384_REGOFF 0x600 |
| #define HWIO_DDR_PHY_384_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_384_REGOFF) |
| #define HWIO_DDR_PHY_384_PHY_DQ_DM_SWIZZLE0_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_384_PHY_DQ_DM_SWIZZLE0_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_385_REGOFF 0x604 |
| #define HWIO_DDR_PHY_385_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_385_REGOFF) |
| #define HWIO_DDR_PHY_385_PHY_DQ_DM_SWIZZLE1_3_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_385_PHY_DQ_DM_SWIZZLE1_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_385_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_385_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_385_PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_385_PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_385_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_385_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_385_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_385_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_386_REGOFF 0x608 |
| #define HWIO_DDR_PHY_386_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_386_REGOFF) |
| #define HWIO_DDR_PHY_386_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_386_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_386_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_386_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_386_PHY_BYPASS_TWO_CYC_PREAMBLE_3_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_386_PHY_BYPASS_TWO_CYC_PREAMBLE_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_386_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_386_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_386_PHY_CLK_BYPASS_OVERRIDE_3_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_386_PHY_CLK_BYPASS_OVERRIDE_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_386_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_386_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_387_REGOFF 0x60c |
| #define HWIO_DDR_PHY_387_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_387_REGOFF) |
| #define HWIO_DDR_PHY_387_PHY_SW_WRDQ0_SHIFT_3_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_387_PHY_SW_WRDQ0_SHIFT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_387_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_387_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_387_PHY_SW_WRDQ1_SHIFT_3_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_387_PHY_SW_WRDQ1_SHIFT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_387_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_387_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_387_PHY_SW_WRDQ2_SHIFT_3_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_387_PHY_SW_WRDQ2_SHIFT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_387_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_387_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_387_PHY_SW_WRDQ3_SHIFT_3_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_387_PHY_SW_WRDQ3_SHIFT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_387_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_387_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_388_REGOFF 0x610 |
| #define HWIO_DDR_PHY_388_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_388_REGOFF) |
| #define HWIO_DDR_PHY_388_PHY_SW_WRDQ4_SHIFT_3_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_388_PHY_SW_WRDQ4_SHIFT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_388_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_388_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_388_PHY_SW_WRDQ5_SHIFT_3_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_388_PHY_SW_WRDQ5_SHIFT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_388_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_388_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_388_PHY_SW_WRDQ6_SHIFT_3_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_388_PHY_SW_WRDQ6_SHIFT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_388_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_388_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_388_PHY_SW_WRDQ7_SHIFT_3_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_388_PHY_SW_WRDQ7_SHIFT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_388_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_388_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_389_REGOFF 0x614 |
| #define HWIO_DDR_PHY_389_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_389_REGOFF) |
| #define HWIO_DDR_PHY_389_PHY_SW_WRDM_SHIFT_3_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_389_PHY_SW_WRDM_SHIFT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_389_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_389_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_389_PHY_SW_WRDQS_SHIFT_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_389_PHY_SW_WRDQS_SHIFT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_389_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_389_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_389_PHY_DQ_TSEL_ENABLE_3_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_389_PHY_DQ_TSEL_ENABLE_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_389_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_389_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_389_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_389_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_390_REGOFF 0x618 |
| #define HWIO_DDR_PHY_390_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_390_REGOFF) |
| #define HWIO_DDR_PHY_390_PHY_DQ_TSEL_SELECT_3_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_390_PHY_DQ_TSEL_SELECT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_390_PHY_DQS_TSEL_ENABLE_3_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_390_PHY_DQS_TSEL_ENABLE_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_390_RESERVED_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_390_RESERVED_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_391_REGOFF 0x61c |
| #define HWIO_DDR_PHY_391_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_391_REGOFF) |
| #define HWIO_DDR_PHY_391_PHY_DQS_TSEL_SELECT_3_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_391_PHY_DQS_TSEL_SELECT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_391_PHY_TWO_CYC_PREAMBLE_3_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_391_PHY_TWO_CYC_PREAMBLE_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_391_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_391_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_392_REGOFF 0x620 |
| #define HWIO_DDR_PHY_392_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_392_REGOFF) |
| #define HWIO_DDR_PHY_392_PHY_DBI_MODE_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_392_PHY_DBI_MODE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_392_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_392_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_392_PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_392_PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_392_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_392_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_392_PHY_LP4_BOOT_RDDATA_EN_DLY_3_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_392_PHY_LP4_BOOT_RDDATA_EN_DLY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_392_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_392_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_392_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_392_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_392_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_392_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_393_REGOFF 0x624 |
| #define HWIO_DDR_PHY_393_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_393_REGOFF) |
| #define HWIO_DDR_PHY_393_PHY_LP4_BOOT_RPTR_UPDATE_3_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_393_PHY_LP4_BOOT_RPTR_UPDATE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_393_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_393_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_393_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_393_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_393_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_393_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_393_PHY_LPBK_CONTROL_3_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_393_PHY_LPBK_CONTROL_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_393_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_393_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_394_REGOFF 0x628 |
| #define HWIO_DDR_PHY_394_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_394_REGOFF) |
| #define HWIO_DDR_PHY_394_PHY_LPBK_DFX_TIMEOUT_EN_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_394_PHY_LPBK_DFX_TIMEOUT_EN_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_394_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_394_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_394_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_394_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_395_REGOFF 0x62c |
| #define HWIO_DDR_PHY_395_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_395_REGOFF) |
| #define HWIO_DDR_PHY_395_PHY_AUTO_TIMING_MARGIN_CONTROL_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_395_PHY_AUTO_TIMING_MARGIN_CONTROL_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_396_REGOFF 0x630 |
| #define HWIO_DDR_PHY_396_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_396_REGOFF) |
| #define HWIO_DDR_PHY_396_PHY_AUTO_TIMING_MARGIN_OBS_3_FLDMASK (0xfffffff) |
| #define HWIO_DDR_PHY_396_PHY_AUTO_TIMING_MARGIN_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_396_RESERVED_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_396_RESERVED_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_397_REGOFF 0x634 |
| #define HWIO_DDR_PHY_397_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_397_REGOFF) |
| #define HWIO_DDR_PHY_397_PHY_SLICE_PWR_RDC_DISABLE_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_397_PHY_SLICE_PWR_RDC_DISABLE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_397_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_397_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_397_PHY_PRBS_PATTERN_START_3_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_397_PHY_PRBS_PATTERN_START_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_397_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_397_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_397_PHY_PRBS_PATTERN_MASK_3_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_397_PHY_PRBS_PATTERN_MASK_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_397_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_397_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_398_REGOFF 0x638 |
| #define HWIO_DDR_PHY_398_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_398_REGOFF) |
| #define HWIO_DDR_PHY_398_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_398_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_398_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_398_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_398_PHY_GATE_ERROR_DELAY_SELECT_3_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_398_PHY_GATE_ERROR_DELAY_SELECT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_398_RESERVED1_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_398_RESERVED1_FLDSHFT (21) |
| #define HWIO_DDR_PHY_398_SC_PHY_SNAP_OBS_REGS_3_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_398_SC_PHY_SNAP_OBS_REGS_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_398_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_398_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_399_REGOFF 0x63c |
| #define HWIO_DDR_PHY_399_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_399_REGOFF) |
| #define HWIO_DDR_PHY_399_PHY_GATE_SMPL1_SLAVE_DELAY_3_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_399_PHY_GATE_SMPL1_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_399_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_399_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_399_PHY_LPDDR_3_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_399_PHY_LPDDR_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_399_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_399_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_399_PHY_LPDDR_TYPE_3_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_399_PHY_LPDDR_TYPE_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_399_RESERVED2_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_399_RESERVED2_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_400_REGOFF 0x640 |
| #define HWIO_DDR_PHY_400_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_400_REGOFF) |
| #define HWIO_DDR_PHY_400_PHY_GATE_SMPL2_SLAVE_DELAY_3_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_400_PHY_GATE_SMPL2_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_400_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_400_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_400_ON_FLY_GATE_ADJUST_EN_3_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_400_ON_FLY_GATE_ADJUST_EN_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_400_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_400_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_400_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_400_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_401_REGOFF 0x644 |
| #define HWIO_DDR_PHY_401_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_401_REGOFF) |
| #define HWIO_DDR_PHY_401_PHY_GATE_TRACKING_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_401_PHY_GATE_TRACKING_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_402_REGOFF 0x648 |
| #define HWIO_DDR_PHY_402_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_402_REGOFF) |
| #define HWIO_DDR_PHY_402_PHY_LP4_PST_AMBLE_3_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_402_PHY_LP4_PST_AMBLE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_402_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_402_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_402_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_402_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_403_REGOFF 0x64c |
| #define HWIO_DDR_PHY_403_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_403_REGOFF) |
| #define HWIO_DDR_PHY_403_PHY_LP4_RDLVL_PATT8_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_403_PHY_LP4_RDLVL_PATT8_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_404_REGOFF 0x650 |
| #define HWIO_DDR_PHY_404_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_404_REGOFF) |
| #define HWIO_DDR_PHY_404_PHY_LP4_RDLVL_PATT9_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_404_PHY_LP4_RDLVL_PATT9_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_405_REGOFF 0x654 |
| #define HWIO_DDR_PHY_405_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_405_REGOFF) |
| #define HWIO_DDR_PHY_405_PHY_LP4_RDLVL_PATT10_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_405_PHY_LP4_RDLVL_PATT10_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_406_REGOFF 0x658 |
| #define HWIO_DDR_PHY_406_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_406_REGOFF) |
| #define HWIO_DDR_PHY_406_PHY_LP4_RDLVL_PATT11_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_406_PHY_LP4_RDLVL_PATT11_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_407_REGOFF 0x65c |
| #define HWIO_DDR_PHY_407_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_407_REGOFF) |
| #define HWIO_DDR_PHY_407_PHY_SLAVE_LOOP_CNT_UPDATE_3_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_407_PHY_SLAVE_LOOP_CNT_UPDATE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_407_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_407_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_407_PHY_SW_FIFO_PTR_RST_DISABLE_3_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_407_PHY_SW_FIFO_PTR_RST_DISABLE_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_407_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_407_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_407_PHY_MASTER_DLY_LOCK_OBS_SELECT_3_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_407_PHY_MASTER_DLY_LOCK_OBS_SELECT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_407_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_407_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_407_PHY_RDDQ_ENC_OBS_SELECT_3_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_407_PHY_RDDQ_ENC_OBS_SELECT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_407_RESERVED3_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_407_RESERVED3_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_408_REGOFF 0x660 |
| #define HWIO_DDR_PHY_408_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_408_REGOFF) |
| #define HWIO_DDR_PHY_408_PHY_RDDQS_DQ_ENC_OBS_SELECT_3_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_408_PHY_RDDQS_DQ_ENC_OBS_SELECT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_408_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_408_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_408_PHY_WR_ENC_OBS_SELECT_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_408_PHY_WR_ENC_OBS_SELECT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_408_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_408_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_408_PHY_WR_SHIFT_OBS_SELECT_3_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_408_PHY_WR_SHIFT_OBS_SELECT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_408_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_408_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_408_PHY_FIFO_PTR_OBS_SELECT_3_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_408_PHY_FIFO_PTR_OBS_SELECT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_408_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_408_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_409_REGOFF 0x664 |
| #define HWIO_DDR_PHY_409_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_409_REGOFF) |
| #define HWIO_DDR_PHY_409_PHY_LVL_DEBUG_MODE_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_409_PHY_LVL_DEBUG_MODE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_409_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_409_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_409_SC_PHY_LVL_DEBUG_CONT_3_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_409_SC_PHY_LVL_DEBUG_CONT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_409_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_409_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_409_PHY_WRLVL_CAPTURE_CNT_3_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_409_PHY_WRLVL_CAPTURE_CNT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_409_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_409_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_409_PHY_WRLVL_UPDT_WAIT_CNT_3_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_409_PHY_WRLVL_UPDT_WAIT_CNT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_409_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_409_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_410_REGOFF 0x668 |
| #define HWIO_DDR_PHY_410_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_410_REGOFF) |
| #define HWIO_DDR_PHY_410_PHY_GTLVL_CAPTURE_CNT_3_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_410_PHY_GTLVL_CAPTURE_CNT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_410_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_410_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_410_PHY_GTLVL_UPDT_WAIT_CNT_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_410_PHY_GTLVL_UPDT_WAIT_CNT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_410_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_410_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_410_PHY_RDLVL_CAPTURE_CNT_3_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_410_PHY_RDLVL_CAPTURE_CNT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_410_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_410_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_410_PHY_RDLVL_UPDT_WAIT_CNT_3_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_410_PHY_RDLVL_UPDT_WAIT_CNT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_410_RESERVED3_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_410_RESERVED3_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_411_REGOFF 0x66c |
| #define HWIO_DDR_PHY_411_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_411_REGOFF) |
| #define HWIO_DDR_PHY_411_PHY_RDLVL_OP_MODE_3_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_411_PHY_RDLVL_OP_MODE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_411_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_411_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_411_PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_411_PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_411_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_411_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_411_PHY_RDLVL_DATA_MASK_3_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_411_PHY_RDLVL_DATA_MASK_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_411_PHY_WDQLVL_BURST_CNT_3_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_411_PHY_WDQLVL_BURST_CNT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_411_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_411_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_412_REGOFF 0x670 |
| #define HWIO_DDR_PHY_412_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_412_REGOFF) |
| #define HWIO_DDR_PHY_412_PHY_WDQLVL_PATT_3_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_412_PHY_WDQLVL_PATT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_412_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_412_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_412_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_412_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_412_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_412_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_412_PHY_WDQLVL_UPDT_WAIT_CNT_3_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_412_PHY_WDQLVL_UPDT_WAIT_CNT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_412_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_412_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_413_REGOFF 0x674 |
| #define HWIO_DDR_PHY_413_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_413_REGOFF) |
| #define HWIO_DDR_PHY_413_PHY_WDQLVL_DQDM_OBS_SELECT_3_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_413_PHY_WDQLVL_DQDM_OBS_SELECT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_413_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_413_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_413_PHY_WDQLVL_QTR_DLY_STEP_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_413_PHY_WDQLVL_QTR_DLY_STEP_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_413_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_413_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_413_SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_413_SC_PHY_WDQLVL_CLR_PREV_RESULTS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_413_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_413_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_413_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_413_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_414_REGOFF 0x678 |
| #define HWIO_DDR_PHY_414_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_414_REGOFF) |
| #define HWIO_DDR_PHY_414_PHY_WDQLVL_DATADM_MASK_3_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_414_PHY_WDQLVL_DATADM_MASK_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_414_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_414_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_414_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_414_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_415_REGOFF 0x67c |
| #define HWIO_DDR_PHY_415_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_415_REGOFF) |
| #define HWIO_DDR_PHY_415_PHY_USER_PATT0_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_415_PHY_USER_PATT0_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_416_REGOFF 0x680 |
| #define HWIO_DDR_PHY_416_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_416_REGOFF) |
| #define HWIO_DDR_PHY_416_PHY_USER_PATT1_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_416_PHY_USER_PATT1_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_417_REGOFF 0x684 |
| #define HWIO_DDR_PHY_417_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_417_REGOFF) |
| #define HWIO_DDR_PHY_417_PHY_USER_PATT2_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_417_PHY_USER_PATT2_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_418_REGOFF 0x688 |
| #define HWIO_DDR_PHY_418_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_418_REGOFF) |
| #define HWIO_DDR_PHY_418_PHY_USER_PATT3_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_418_PHY_USER_PATT3_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_419_REGOFF 0x68c |
| #define HWIO_DDR_PHY_419_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_419_REGOFF) |
| #define HWIO_DDR_PHY_419_PHY_USER_PATT4_3_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_419_PHY_USER_PATT4_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_419_PHY_CALVL_VREF_DRIVING_SLICE_3_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_419_PHY_CALVL_VREF_DRIVING_SLICE_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_419_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_419_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_419_SC_PHY_MANUAL_CLEAR_3_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_419_SC_PHY_MANUAL_CLEAR_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_419_RESERVED1_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_419_RESERVED1_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_420_REGOFF 0x690 |
| #define HWIO_DDR_PHY_420_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_420_REGOFF) |
| #define HWIO_DDR_PHY_420_PHY_FIFO_PTR_OBS_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_420_PHY_FIFO_PTR_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_420_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_420_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_421_REGOFF 0x694 |
| #define HWIO_DDR_PHY_421_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_421_REGOFF) |
| #define HWIO_DDR_PHY_421_PHY_LPBK_RESULT_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_421_PHY_LPBK_RESULT_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_422_REGOFF 0x698 |
| #define HWIO_DDR_PHY_422_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_422_REGOFF) |
| #define HWIO_DDR_PHY_422_PHY_LPBK_ERROR_COUNT_OBS_3_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_422_PHY_LPBK_ERROR_COUNT_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_422_PHY_MASTER_DLY_LOCK_OBS_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_422_PHY_MASTER_DLY_LOCK_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_422_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_422_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_423_REGOFF 0x69c |
| #define HWIO_DDR_PHY_423_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_423_REGOFF) |
| #define HWIO_DDR_PHY_423_PHY_RDDQ_SLV_DLY_ENC_OBS_3_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_423_PHY_RDDQ_SLV_DLY_ENC_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_423_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_423_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_423_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_423_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_423_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_423_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_423_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_FLDMASK \ |
| (0xff0000) |
| #define HWIO_DDR_PHY_423_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_423_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_FLDMASK \ |
| (0xff000000) |
| #define HWIO_DDR_PHY_423_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_424_REGOFF 0x6a0 |
| #define HWIO_DDR_PHY_424_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_424_REGOFF) |
| #define HWIO_DDR_PHY_424_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_424_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_424_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_424_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_424_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_FLDMASK (0x7f0000) |
| #define HWIO_DDR_PHY_424_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_424_RESERVED1_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_424_RESERVED1_FLDSHFT (23) |
| #define HWIO_DDR_PHY_424_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_424_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_425_REGOFF 0x6a4 |
| #define HWIO_DDR_PHY_425_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_425_REGOFF) |
| #define HWIO_DDR_PHY_425_PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_425_PHY_WR_ADDER_SLV_DLY_ENC_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_425_PHY_WR_SHIFT_OBS_3_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_425_PHY_WR_SHIFT_OBS_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_425_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_425_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_425_PHY_WRLVL_HARD0_DELAY_OBS_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_425_PHY_WRLVL_HARD0_DELAY_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_425_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_425_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_426_REGOFF 0x6a8 |
| #define HWIO_DDR_PHY_426_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_426_REGOFF) |
| #define HWIO_DDR_PHY_426_PHY_WRLVL_HARD1_DELAY_OBS_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_426_PHY_WRLVL_HARD1_DELAY_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_426_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_426_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_426_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_426_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_427_REGOFF 0x6ac |
| #define HWIO_DDR_PHY_427_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_427_REGOFF) |
| #define HWIO_DDR_PHY_427_PHY_WRLVL_STATUS_OBS_3_FLDMASK (0x1ffff) |
| #define HWIO_DDR_PHY_427_PHY_WRLVL_STATUS_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_427_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_427_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_427_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_427_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_428_REGOFF 0x6b0 |
| #define HWIO_DDR_PHY_428_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_428_REGOFF) |
| #define HWIO_DDR_PHY_428_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_428_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_428_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_428_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_428_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_428_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_428_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_428_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_429_REGOFF 0x6b4 |
| #define HWIO_DDR_PHY_429_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_429_REGOFF) |
| #define HWIO_DDR_PHY_429_PHY_GTLVL_HARD0_DELAY_OBS_3_FLDMASK (0x3fff) |
| #define HWIO_DDR_PHY_429_PHY_GTLVL_HARD0_DELAY_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_429_RESERVED_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_429_RESERVED_FLDSHFT (14) |
| #define HWIO_DDR_PHY_429_PHY_GTLVL_HARD1_DELAY_OBS_3_FLDMASK (0x3fff0000) |
| #define HWIO_DDR_PHY_429_PHY_GTLVL_HARD1_DELAY_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_429_RESERVED1_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_429_RESERVED1_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_430_REGOFF 0x6b8 |
| #define HWIO_DDR_PHY_430_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_430_REGOFF) |
| #define HWIO_DDR_PHY_430_PHY_GTLVL_STATUS_OBS_3_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_430_PHY_GTLVL_STATUS_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_430_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_430_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_430_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_430_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_431_REGOFF 0x6bc |
| #define HWIO_DDR_PHY_431_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_431_REGOFF) |
| #define HWIO_DDR_PHY_431_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_431_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_431_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_431_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_431_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_431_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_431_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_431_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_432_REGOFF 0x6c0 |
| #define HWIO_DDR_PHY_432_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_432_REGOFF) |
| #define HWIO_DDR_PHY_432_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_432_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_432_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_432_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_432_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_432_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_433_REGOFF 0x6c4 |
| #define HWIO_DDR_PHY_433_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_433_REGOFF) |
| #define HWIO_DDR_PHY_433_PHY_RDLVL_STATUS_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_433_PHY_RDLVL_STATUS_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_434_REGOFF 0x6c8 |
| #define HWIO_DDR_PHY_434_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_434_REGOFF) |
| #define HWIO_DDR_PHY_434_PHY_WDQLVL_DQDM_LE_DLY_OBS_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_434_PHY_WDQLVL_DQDM_LE_DLY_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_434_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_434_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_434_PHY_WDQLVL_DQDM_TE_DLY_OBS_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_434_PHY_WDQLVL_DQDM_TE_DLY_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_434_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_434_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_435_REGOFF 0x6cc |
| #define HWIO_DDR_PHY_435_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_435_REGOFF) |
| #define HWIO_DDR_PHY_435_PHY_WDQLVL_STATUS_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_435_PHY_WDQLVL_STATUS_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_436_REGOFF 0x6d0 |
| #define HWIO_DDR_PHY_436_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_436_REGOFF) |
| #define HWIO_DDR_PHY_436_PHY_DDL_MODE_3_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_436_PHY_DDL_MODE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_436_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_436_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_436_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_436_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_437_REGOFF 0x6d4 |
| #define HWIO_DDR_PHY_437_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_437_REGOFF) |
| #define HWIO_DDR_PHY_437_PHY_DDL_TEST_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_437_PHY_DDL_TEST_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_438_REGOFF 0x6d8 |
| #define HWIO_DDR_PHY_438_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_438_REGOFF) |
| #define HWIO_DDR_PHY_438_PHY_DDL_TEST_MSTR_DLY_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_438_PHY_DDL_TEST_MSTR_DLY_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_439_REGOFF 0x6dc |
| #define HWIO_DDR_PHY_439_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_439_REGOFF) |
| #define HWIO_DDR_PHY_439_PHY_DDL_TRACK_UPD_THRESHOLD_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_439_PHY_DDL_TRACK_UPD_THRESHOLD_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_439_PHY_LP4_WDQS_OE_EXTEND_3_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_439_PHY_LP4_WDQS_OE_EXTEND_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_439_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_439_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_439_SC_PHY_RX_CAL_START_3_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_439_SC_PHY_RX_CAL_START_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_439_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_439_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_439_PHY_RX_CAL_OVERRIDE_3_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_439_PHY_RX_CAL_OVERRIDE_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_439_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_439_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_440_REGOFF 0x6e0 |
| #define HWIO_DDR_PHY_440_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_440_REGOFF) |
| #define HWIO_DDR_PHY_440_PHY_RX_CAL_SAMPLE_WAIT_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_440_PHY_RX_CAL_SAMPLE_WAIT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_440_PHY_RX_CAL_DQ0_3_FLDMASK (0xfff00) |
| #define HWIO_DDR_PHY_440_PHY_RX_CAL_DQ0_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_440_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_440_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_440_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_440_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_441_REGOFF 0x6e4 |
| #define HWIO_DDR_PHY_441_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_441_REGOFF) |
| #define HWIO_DDR_PHY_441_PHY_RX_CAL_DQ1_3_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_441_PHY_RX_CAL_DQ1_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_441_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_441_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_441_PHY_RX_CAL_DQ2_3_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_441_PHY_RX_CAL_DQ2_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_441_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_441_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_442_REGOFF 0x6e8 |
| #define HWIO_DDR_PHY_442_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_442_REGOFF) |
| #define HWIO_DDR_PHY_442_PHY_RX_CAL_DQ3_3_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_442_PHY_RX_CAL_DQ3_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_442_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_442_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_442_PHY_RX_CAL_DQ4_3_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_442_PHY_RX_CAL_DQ4_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_442_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_442_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_443_REGOFF 0x6ec |
| #define HWIO_DDR_PHY_443_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_443_REGOFF) |
| #define HWIO_DDR_PHY_443_PHY_RX_CAL_DQ5_3_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_443_PHY_RX_CAL_DQ5_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_443_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_443_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_443_PHY_RX_CAL_DQ6_3_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_443_PHY_RX_CAL_DQ6_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_443_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_443_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_444_REGOFF 0x6f0 |
| #define HWIO_DDR_PHY_444_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_444_REGOFF) |
| #define HWIO_DDR_PHY_444_PHY_RX_CAL_DQ7_3_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_444_PHY_RX_CAL_DQ7_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_444_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_444_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_444_PHY_RX_CAL_DM_3_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_444_PHY_RX_CAL_DM_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_444_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_444_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_445_REGOFF 0x6f4 |
| #define HWIO_DDR_PHY_445_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_445_REGOFF) |
| #define HWIO_DDR_PHY_445_PHY_RX_CAL_DQS_3_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_445_PHY_RX_CAL_DQS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_445_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_445_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_445_PHY_RX_CAL_FDBK_3_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_445_PHY_RX_CAL_FDBK_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_445_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_445_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_446_REGOFF 0x6f8 |
| #define HWIO_DDR_PHY_446_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_446_REGOFF) |
| #define HWIO_DDR_PHY_446_PHY_RX_CAL_OBS_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_446_PHY_RX_CAL_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_446_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_446_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_446_PHY_RX_CAL_LOCK_OBS_3_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_446_PHY_RX_CAL_LOCK_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_446_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_446_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_447_REGOFF 0x6fc |
| #define HWIO_DDR_PHY_447_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_447_REGOFF) |
| #define HWIO_DDR_PHY_447_PHY_RX_CAL_DISABLE_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_447_PHY_RX_CAL_DISABLE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_447_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_447_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_447_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_447_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_448_REGOFF 0x700 |
| #define HWIO_DDR_PHY_448_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_448_REGOFF) |
| #define HWIO_DDR_PHY_448_PHY_CLK_WRDQ0_SLAVE_DELAY_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_448_PHY_CLK_WRDQ0_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_448_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_448_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_448_PHY_CLK_WRDQ1_SLAVE_DELAY_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_448_PHY_CLK_WRDQ1_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_448_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_448_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_449_REGOFF 0x704 |
| #define HWIO_DDR_PHY_449_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_449_REGOFF) |
| #define HWIO_DDR_PHY_449_PHY_CLK_WRDQ2_SLAVE_DELAY_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_449_PHY_CLK_WRDQ2_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_449_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_449_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_449_PHY_CLK_WRDQ3_SLAVE_DELAY_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_449_PHY_CLK_WRDQ3_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_449_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_449_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_450_REGOFF 0x708 |
| #define HWIO_DDR_PHY_450_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_450_REGOFF) |
| #define HWIO_DDR_PHY_450_PHY_CLK_WRDQ4_SLAVE_DELAY_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_450_PHY_CLK_WRDQ4_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_450_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_450_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_450_PHY_CLK_WRDQ5_SLAVE_DELAY_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_450_PHY_CLK_WRDQ5_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_450_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_450_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_451_REGOFF 0x70c |
| #define HWIO_DDR_PHY_451_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_451_REGOFF) |
| #define HWIO_DDR_PHY_451_PHY_CLK_WRDQ6_SLAVE_DELAY_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_451_PHY_CLK_WRDQ6_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_451_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_451_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_451_PHY_CLK_WRDQ7_SLAVE_DELAY_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_451_PHY_CLK_WRDQ7_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_451_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_451_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_452_REGOFF 0x710 |
| #define HWIO_DDR_PHY_452_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_452_REGOFF) |
| #define HWIO_DDR_PHY_452_PHY_CLK_WRDM_SLAVE_DELAY_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_452_PHY_CLK_WRDM_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_452_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_452_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_452_PHY_CLK_WRDQS_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_452_PHY_CLK_WRDQS_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_452_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_452_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_453_REGOFF 0x714 |
| #define HWIO_DDR_PHY_453_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_453_REGOFF) |
| #define HWIO_DDR_PHY_453_PHY_WRLVL_THRESHOLD_ADJUST_3_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_453_PHY_WRLVL_THRESHOLD_ADJUST_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_453_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_453_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_453_PHY_RDDQ0_SLAVE_DELAY_3_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_453_PHY_RDDQ0_SLAVE_DELAY_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_453_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_453_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_453_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_453_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_454_REGOFF 0x718 |
| #define HWIO_DDR_PHY_454_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_454_REGOFF) |
| #define HWIO_DDR_PHY_454_PHY_RDDQ1_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_454_PHY_RDDQ1_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_454_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_454_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_454_PHY_RDDQ2_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_454_PHY_RDDQ2_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_454_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_454_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_455_REGOFF 0x71c |
| #define HWIO_DDR_PHY_455_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_455_REGOFF) |
| #define HWIO_DDR_PHY_455_PHY_RDDQ3_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_455_PHY_RDDQ3_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_455_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_455_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_455_PHY_RDDQ4_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_455_PHY_RDDQ4_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_455_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_455_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_456_REGOFF 0x720 |
| #define HWIO_DDR_PHY_456_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_456_REGOFF) |
| #define HWIO_DDR_PHY_456_PHY_RDDQ5_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_456_PHY_RDDQ5_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_456_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_456_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_456_PHY_RDDQ6_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_456_PHY_RDDQ6_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_456_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_456_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_457_REGOFF 0x724 |
| #define HWIO_DDR_PHY_457_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_457_REGOFF) |
| #define HWIO_DDR_PHY_457_PHY_RDDQ7_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_457_PHY_RDDQ7_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_457_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_457_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_457_PHY_RDDM_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_457_PHY_RDDM_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_457_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_457_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_458_REGOFF 0x728 |
| #define HWIO_DDR_PHY_458_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_458_REGOFF) |
| #define HWIO_DDR_PHY_458_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_458_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_458_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_458_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_458_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_458_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_458_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_458_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_459_REGOFF 0x72c |
| #define HWIO_DDR_PHY_459_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_459_REGOFF) |
| #define HWIO_DDR_PHY_459_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_459_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_459_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_459_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_459_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_459_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_459_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_459_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_460_REGOFF 0x730 |
| #define HWIO_DDR_PHY_460_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_460_REGOFF) |
| #define HWIO_DDR_PHY_460_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_460_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_460_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_460_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_460_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_460_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_460_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_460_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_461_REGOFF 0x734 |
| #define HWIO_DDR_PHY_461_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_461_REGOFF) |
| #define HWIO_DDR_PHY_461_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_461_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_461_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_461_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_461_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_461_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_461_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_461_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_462_REGOFF 0x738 |
| #define HWIO_DDR_PHY_462_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_462_REGOFF) |
| #define HWIO_DDR_PHY_462_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_462_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_462_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_462_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_462_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_462_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_462_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_462_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_463_REGOFF 0x73c |
| #define HWIO_DDR_PHY_463_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_463_REGOFF) |
| #define HWIO_DDR_PHY_463_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_463_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_463_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_463_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_463_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_463_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_463_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_463_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_464_REGOFF 0x740 |
| #define HWIO_DDR_PHY_464_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_464_REGOFF) |
| #define HWIO_DDR_PHY_464_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_464_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_464_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_464_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_464_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_464_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_464_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_464_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_465_REGOFF 0x744 |
| #define HWIO_DDR_PHY_465_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_465_REGOFF) |
| #define HWIO_DDR_PHY_465_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_465_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_465_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_465_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_465_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_465_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_465_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_465_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_466_REGOFF 0x748 |
| #define HWIO_DDR_PHY_466_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_466_REGOFF) |
| #define HWIO_DDR_PHY_466_PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_466_PHY_RDDQS_DM_RISE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_466_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_466_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_466_PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_466_PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_466_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_466_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_467_REGOFF 0x74c |
| #define HWIO_DDR_PHY_467_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_467_REGOFF) |
| #define HWIO_DDR_PHY_467_PHY_RDDQS_GATE_SLAVE_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_467_PHY_RDDQS_GATE_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_467_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_467_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_467_PHY_RDDQS_LATENCY_ADJUST_3_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_467_PHY_RDDQS_LATENCY_ADJUST_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_467_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_467_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_467_PHY_WRITE_PATH_LAT_ADD_3_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_467_PHY_WRITE_PATH_LAT_ADD_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_467_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_467_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_468_REGOFF 0x750 |
| #define HWIO_DDR_PHY_468_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_468_REGOFF) |
| #define HWIO_DDR_PHY_468_PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_468_PHY_WRLVL_DELAY_EARLY_THRESHOLD_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_468_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_468_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_468_PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_468_PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_468_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_468_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_469_REGOFF 0x754 |
| #define HWIO_DDR_PHY_469_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_469_REGOFF) |
| #define HWIO_DDR_PHY_469_PHY_WRLVL_EARLY_FORCE_0_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_469_PHY_WRLVL_EARLY_FORCE_0_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_469_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_469_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_469_PHY_GTLVL_RDDQS_SLV_DLY_START_3_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_469_PHY_GTLVL_RDDQS_SLV_DLY_START_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_469_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_469_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_469_PHY_GTLVL_LAT_ADJ_START_3_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_469_PHY_GTLVL_LAT_ADJ_START_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_469_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_469_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_470_REGOFF 0x758 |
| #define HWIO_DDR_PHY_470_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_470_REGOFF) |
| #define HWIO_DDR_PHY_470_PHY_WDQLVL_DQDM_SLV_DLY_START_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_470_PHY_WDQLVL_DQDM_SLV_DLY_START_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_470_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_470_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_470_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_470_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_470_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_470_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_471_REGOFF 0x75c |
| #define HWIO_DDR_PHY_471_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_471_REGOFF) |
| #define HWIO_DDR_PHY_471_PHY_FDBK_PWR_CTRL_3_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_471_PHY_FDBK_PWR_CTRL_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_471_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_471_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_471_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_471_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_472_REGOFF 0x760 |
| #define HWIO_DDR_PHY_472_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_472_REGOFF) |
| #define HWIO_DDR_PHY_472_PHY_DQ_OE_TIMING_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_472_PHY_DQ_OE_TIMING_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_472_PHY_DQ_TSEL_RD_TIMING_3_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_472_PHY_DQ_TSEL_RD_TIMING_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_472_PHY_DQ_TSEL_WR_TIMING_3_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_472_PHY_DQ_TSEL_WR_TIMING_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_472_PHY_DQS_OE_TIMING_3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_472_PHY_DQS_OE_TIMING_3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_473_REGOFF 0x764 |
| #define HWIO_DDR_PHY_473_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_473_REGOFF) |
| #define HWIO_DDR_PHY_473_PHY_DQS_TSEL_RD_TIMING_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_473_PHY_DQS_TSEL_RD_TIMING_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_473_PHY_DQS_TSEL_WR_TIMING_3_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_473_PHY_DQS_TSEL_WR_TIMING_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_473_PHY_DQ_IE_TIMING_3_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_473_PHY_DQ_IE_TIMING_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_473_PHY_DQS_IE_TIMING_3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_473_PHY_DQS_IE_TIMING_3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_474_REGOFF 0x768 |
| #define HWIO_DDR_PHY_474_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_474_REGOFF) |
| #define HWIO_DDR_PHY_474_PHY_RDDATA_EN_IE_DLY_3_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_474_PHY_RDDATA_EN_IE_DLY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_474_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_474_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_474_PHY_IE_MODE_3_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_474_PHY_IE_MODE_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_474_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_474_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_474_PHY_RDDATA_EN_DLY_3_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_474_PHY_RDDATA_EN_DLY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_474_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_474_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_474_PHY_RDDATA_EN_TSEL_DLY_3_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_474_PHY_RDDATA_EN_TSEL_DLY_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_474_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_474_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_475_REGOFF 0x76c |
| #define HWIO_DDR_PHY_475_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_475_REGOFF) |
| #define HWIO_DDR_PHY_475_PHY_SW_MASTER_MODE_3_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_475_PHY_SW_MASTER_MODE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_475_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_475_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_475_PHY_MASTER_DELAY_START_3_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_475_PHY_MASTER_DELAY_START_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_475_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_475_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_475_PHY_MASTER_DELAY_STEP_3_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_475_PHY_MASTER_DELAY_STEP_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_475_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_475_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_476_REGOFF 0x770 |
| #define HWIO_DDR_PHY_476_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_476_REGOFF) |
| #define HWIO_DDR_PHY_476_PHY_MASTER_DELAY_WAIT_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_476_PHY_MASTER_DELAY_WAIT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_476_PHY_MASTER_DELAY_HALF_MEASURE_3_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_476_PHY_MASTER_DELAY_HALF_MEASURE_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_476_PHY_RPTR_UPDATE_3_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_476_PHY_RPTR_UPDATE_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_476_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_476_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_476_PHY_WRLVL_DLY_STEP_3_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_476_PHY_WRLVL_DLY_STEP_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_476_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_476_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_477_REGOFF 0x774 |
| #define HWIO_DDR_PHY_477_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_477_REGOFF) |
| #define HWIO_DDR_PHY_477_PHY_WRLVL_RESP_WAIT_CNT_3_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_477_PHY_WRLVL_RESP_WAIT_CNT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_477_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_477_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_477_PHY_GTLVL_DLY_STEP_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_477_PHY_GTLVL_DLY_STEP_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_477_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_477_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_477_PHY_GTLVL_RESP_WAIT_CNT_3_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_477_PHY_GTLVL_RESP_WAIT_CNT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_477_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_477_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_477_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_477_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_478_REGOFF 0x778 |
| #define HWIO_DDR_PHY_478_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_478_REGOFF) |
| #define HWIO_DDR_PHY_478_PHY_GTLVL_BACK_STEP_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_478_PHY_GTLVL_BACK_STEP_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_478_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_478_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_478_PHY_GTLVL_FINAL_STEP_3_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_478_PHY_GTLVL_FINAL_STEP_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_478_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_478_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_479_REGOFF 0x77c |
| #define HWIO_DDR_PHY_479_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_479_REGOFF) |
| #define HWIO_DDR_PHY_479_PHY_WDQLVL_DLY_STEP_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_479_PHY_WDQLVL_DLY_STEP_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_479_PHY_RDLVL_DLY_STEP_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_479_PHY_RDLVL_DLY_STEP_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_479_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_479_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_479_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_479_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_480_REGOFF 0x780 |
| #define HWIO_DDR_PHY_480_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_480_REGOFF) |
| #define HWIO_DDR_PHY_480_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_480_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_481_REGOFF 0x784 |
| #define HWIO_DDR_PHY_481_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_481_REGOFF) |
| #define HWIO_DDR_PHY_481_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_481_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_482_REGOFF 0x788 |
| #define HWIO_DDR_PHY_482_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_482_REGOFF) |
| #define HWIO_DDR_PHY_482_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_482_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_483_REGOFF 0x78c |
| #define HWIO_DDR_PHY_483_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_483_REGOFF) |
| #define HWIO_DDR_PHY_483_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_483_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_484_REGOFF 0x790 |
| #define HWIO_DDR_PHY_484_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_484_REGOFF) |
| #define HWIO_DDR_PHY_484_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_484_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_485_REGOFF 0x794 |
| #define HWIO_DDR_PHY_485_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_485_REGOFF) |
| #define HWIO_DDR_PHY_485_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_485_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_486_REGOFF 0x798 |
| #define HWIO_DDR_PHY_486_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_486_REGOFF) |
| #define HWIO_DDR_PHY_486_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_486_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_487_REGOFF 0x79c |
| #define HWIO_DDR_PHY_487_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_487_REGOFF) |
| #define HWIO_DDR_PHY_487_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_487_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_488_REGOFF 0x7a0 |
| #define HWIO_DDR_PHY_488_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_488_REGOFF) |
| #define HWIO_DDR_PHY_488_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_488_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_489_REGOFF 0x7a4 |
| #define HWIO_DDR_PHY_489_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_489_REGOFF) |
| #define HWIO_DDR_PHY_489_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_489_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_490_REGOFF 0x7a8 |
| #define HWIO_DDR_PHY_490_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_490_REGOFF) |
| #define HWIO_DDR_PHY_490_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_490_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_491_REGOFF 0x7ac |
| #define HWIO_DDR_PHY_491_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_491_REGOFF) |
| #define HWIO_DDR_PHY_491_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_491_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_492_REGOFF 0x7b0 |
| #define HWIO_DDR_PHY_492_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_492_REGOFF) |
| #define HWIO_DDR_PHY_492_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_492_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_493_REGOFF 0x7b4 |
| #define HWIO_DDR_PHY_493_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_493_REGOFF) |
| #define HWIO_DDR_PHY_493_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_493_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_494_REGOFF 0x7b8 |
| #define HWIO_DDR_PHY_494_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_494_REGOFF) |
| #define HWIO_DDR_PHY_494_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_494_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_495_REGOFF 0x7bc |
| #define HWIO_DDR_PHY_495_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_495_REGOFF) |
| #define HWIO_DDR_PHY_495_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_495_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_496_REGOFF 0x7c0 |
| #define HWIO_DDR_PHY_496_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_496_REGOFF) |
| #define HWIO_DDR_PHY_496_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_496_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_497_REGOFF 0x7c4 |
| #define HWIO_DDR_PHY_497_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_497_REGOFF) |
| #define HWIO_DDR_PHY_497_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_497_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_498_REGOFF 0x7c8 |
| #define HWIO_DDR_PHY_498_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_498_REGOFF) |
| #define HWIO_DDR_PHY_498_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_498_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_499_REGOFF 0x7cc |
| #define HWIO_DDR_PHY_499_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_499_REGOFF) |
| #define HWIO_DDR_PHY_499_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_499_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_500_REGOFF 0x7d0 |
| #define HWIO_DDR_PHY_500_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_500_REGOFF) |
| #define HWIO_DDR_PHY_500_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_500_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_501_REGOFF 0x7d4 |
| #define HWIO_DDR_PHY_501_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_501_REGOFF) |
| #define HWIO_DDR_PHY_501_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_501_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_502_REGOFF 0x7d8 |
| #define HWIO_DDR_PHY_502_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_502_REGOFF) |
| #define HWIO_DDR_PHY_502_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_502_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_503_REGOFF 0x7dc |
| #define HWIO_DDR_PHY_503_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_503_REGOFF) |
| #define HWIO_DDR_PHY_503_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_503_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_504_REGOFF 0x7e0 |
| #define HWIO_DDR_PHY_504_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_504_REGOFF) |
| #define HWIO_DDR_PHY_504_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_504_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_505_REGOFF 0x7e4 |
| #define HWIO_DDR_PHY_505_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_505_REGOFF) |
| #define HWIO_DDR_PHY_505_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_505_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_506_REGOFF 0x7e8 |
| #define HWIO_DDR_PHY_506_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_506_REGOFF) |
| #define HWIO_DDR_PHY_506_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_506_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_507_REGOFF 0x7ec |
| #define HWIO_DDR_PHY_507_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_507_REGOFF) |
| #define HWIO_DDR_PHY_507_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_507_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_508_REGOFF 0x7f0 |
| #define HWIO_DDR_PHY_508_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_508_REGOFF) |
| #define HWIO_DDR_PHY_508_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_508_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_509_REGOFF 0x7f4 |
| #define HWIO_DDR_PHY_509_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_509_REGOFF) |
| #define HWIO_DDR_PHY_509_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_509_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_510_REGOFF 0x7f8 |
| #define HWIO_DDR_PHY_510_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_510_REGOFF) |
| #define HWIO_DDR_PHY_510_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_510_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_511_REGOFF 0x7fc |
| #define HWIO_DDR_PHY_511_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_511_REGOFF) |
| #define HWIO_DDR_PHY_511_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_511_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_512_REGOFF 0x800 |
| #define HWIO_DDR_PHY_512_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_512_REGOFF) |
| #define HWIO_DDR_PHY_512_PHY_ADR0_SW_WRADDR_SHIFT_0_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_512_PHY_ADR0_SW_WRADDR_SHIFT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_512_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_512_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_512_PHY_ADR1_SW_WRADDR_SHIFT_0_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_512_PHY_ADR1_SW_WRADDR_SHIFT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_512_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_512_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_512_PHY_ADR2_SW_WRADDR_SHIFT_0_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_512_PHY_ADR2_SW_WRADDR_SHIFT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_512_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_512_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_512_PHY_ADR3_SW_WRADDR_SHIFT_0_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_512_PHY_ADR3_SW_WRADDR_SHIFT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_512_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_512_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_513_REGOFF 0x804 |
| #define HWIO_DDR_PHY_513_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_513_REGOFF) |
| #define HWIO_DDR_PHY_513_PHY_ADR4_SW_WRADDR_SHIFT_0_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_513_PHY_ADR4_SW_WRADDR_SHIFT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_513_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_513_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_513_PHY_ADR5_SW_WRADDR_SHIFT_0_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_513_PHY_ADR5_SW_WRADDR_SHIFT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_513_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_513_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_513_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_513_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_513_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_513_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_514_REGOFF 0x808 |
| #define HWIO_DDR_PHY_514_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_514_REGOFF) |
| #define HWIO_DDR_PHY_514_PHY_ADR_CLK_BYPASS_OVERRIDE_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_514_PHY_ADR_CLK_BYPASS_OVERRIDE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_514_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_514_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_514_SC_PHY_ADR_MANUAL_CLEAR_0_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_514_SC_PHY_ADR_MANUAL_CLEAR_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_514_RESERVED1_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_514_RESERVED1_FLDSHFT (11) |
| #define HWIO_DDR_PHY_514_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_514_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_515_REGOFF 0x80c |
| #define HWIO_DDR_PHY_515_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_515_REGOFF) |
| #define HWIO_DDR_PHY_515_PHY_ADR_LPBK_RESULT_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_515_PHY_ADR_LPBK_RESULT_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_516_REGOFF 0x810 |
| #define HWIO_DDR_PHY_516_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_516_REGOFF) |
| #define HWIO_DDR_PHY_516_PHY_ADR_LPBK_ERROR_COUNT_OBS_0_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_516_PHY_ADR_LPBK_ERROR_COUNT_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_516_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_516_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_516_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_516_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_516_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_516_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_517_REGOFF 0x814 |
| #define HWIO_DDR_PHY_517_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_517_REGOFF) |
| #define HWIO_DDR_PHY_517_PHY_ADR_MASTER_DLY_LOCK_OBS_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_517_PHY_ADR_MASTER_DLY_LOCK_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_517_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_517_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_517_PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_517_PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_517_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_517_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_518_REGOFF 0x818 |
| #define HWIO_DDR_PHY_518_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_518_REGOFF) |
| #define HWIO_DDR_PHY_518_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_518_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_518_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_518_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_518_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_518_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_518_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_518_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_518_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_518_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_518_SC_PHY_ADR_SNAP_OBS_REGS_0_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_518_SC_PHY_ADR_SNAP_OBS_REGS_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_518_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_518_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_519_REGOFF 0x81c |
| #define HWIO_DDR_PHY_519_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_519_REGOFF) |
| #define HWIO_DDR_PHY_519_PHY_ADR_TSEL_ENABLE_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_519_PHY_ADR_TSEL_ENABLE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_519_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_519_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_519_PHY_ADR_LPBK_CONTROL_0_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_519_PHY_ADR_LPBK_CONTROL_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_519_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_519_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_519_PHY_ADR_PRBS_PATTERN_START_0_FLDMASK (0x7f0000) |
| #define HWIO_DDR_PHY_519_PHY_ADR_PRBS_PATTERN_START_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_519_RESERVED2_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_519_RESERVED2_FLDSHFT (23) |
| #define HWIO_DDR_PHY_519_PHY_ADR_PRBS_PATTERN_MASK_0_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_519_PHY_ADR_PRBS_PATTERN_MASK_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_519_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_519_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_520_REGOFF 0x820 |
| #define HWIO_DDR_PHY_520_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_520_REGOFF) |
| #define HWIO_DDR_PHY_520_PHY_ADR_PWR_RDC_DISABLE_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_520_PHY_ADR_PWR_RDC_DISABLE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_520_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_520_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_520_PHY_ADR_TYPE_0_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_520_PHY_ADR_TYPE_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_520_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_520_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_520_PHY_ADR_WRADDR_SHIFT_OBS_0_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_520_PHY_ADR_WRADDR_SHIFT_OBS_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_520_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_520_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_520_PHY_ADR_IE_MODE_0_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_520_PHY_ADR_IE_MODE_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_520_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_520_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_521_REGOFF 0x824 |
| #define HWIO_DDR_PHY_521_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_521_REGOFF) |
| #define HWIO_DDR_PHY_521_PHY_ADR_DDL_MODE_0_FLDMASK (0x7fff) |
| #define HWIO_DDR_PHY_521_PHY_ADR_DDL_MODE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_521_RESERVED_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_521_RESERVED_FLDSHFT (15) |
| #define HWIO_DDR_PHY_521_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_521_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_522_REGOFF 0x828 |
| #define HWIO_DDR_PHY_522_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_522_REGOFF) |
| #define HWIO_DDR_PHY_522_PHY_ADR_DDL_TEST_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_522_PHY_ADR_DDL_TEST_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_523_REGOFF 0x82c |
| #define HWIO_DDR_PHY_523_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_523_REGOFF) |
| #define HWIO_DDR_PHY_523_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_523_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_524_REGOFF 0x830 |
| #define HWIO_DDR_PHY_524_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_524_REGOFF) |
| #define HWIO_DDR_PHY_524_PHY_ADR_CALVL_START_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_524_PHY_ADR_CALVL_START_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_524_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_524_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_524_PHY_ADR_CALVL_COARSE_DLY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_524_PHY_ADR_CALVL_COARSE_DLY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_524_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_524_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_525_REGOFF 0x834 |
| #define HWIO_DDR_PHY_525_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_525_REGOFF) |
| #define HWIO_DDR_PHY_525_PHY_ADR_CALVL_QTR_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_525_PHY_ADR_CALVL_QTR_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_525_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_525_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_525_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_525_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_526_REGOFF 0x838 |
| #define HWIO_DDR_PHY_526_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_526_REGOFF) |
| #define HWIO_DDR_PHY_526_PHY_ADR_CALVL_SWIZZLE0_0_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_526_PHY_ADR_CALVL_SWIZZLE0_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_526_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_526_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_527_REGOFF 0x83c |
| #define HWIO_DDR_PHY_527_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_527_REGOFF) |
| #define HWIO_DDR_PHY_527_PHY_ADR_CALVL_SWIZZLE1_0_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_527_PHY_ADR_CALVL_SWIZZLE1_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_527_PHY_ADR_CALVL_RANK_CTRL_0_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_527_PHY_ADR_CALVL_RANK_CTRL_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_527_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_527_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_528_REGOFF 0x840 |
| #define HWIO_DDR_PHY_528_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_528_REGOFF) |
| #define HWIO_DDR_PHY_528_PHY_ADR_CALVL_NUM_PATTERNS_0_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_528_PHY_ADR_CALVL_NUM_PATTERNS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_528_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_528_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_528_PHY_ADR_CALVL_CAPTURE_CNT_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_528_PHY_ADR_CALVL_CAPTURE_CNT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_528_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_528_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_528_PHY_ADR_CALVL_RESP_WAIT_CNT_0_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_528_PHY_ADR_CALVL_RESP_WAIT_CNT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_528_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_528_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_528_PHY_ADR_CALVL_DEBUG_MODE_0_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_528_PHY_ADR_CALVL_DEBUG_MODE_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_528_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_528_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_529_REGOFF 0x844 |
| #define HWIO_DDR_PHY_529_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_529_REGOFF) |
| #define HWIO_DDR_PHY_529_SC_PHY_ADR_CALVL_DEBUG_CONT_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_529_SC_PHY_ADR_CALVL_DEBUG_CONT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_529_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_529_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_529_SC_PHY_ADR_CALVL_ERROR_CLR_0_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_529_SC_PHY_ADR_CALVL_ERROR_CLR_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_529_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_529_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_529_PHY_ADR_CALVL_OBS_SELECT_0_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_529_PHY_ADR_CALVL_OBS_SELECT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_529_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_529_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_529_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_529_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_530_REGOFF 0x848 |
| #define HWIO_DDR_PHY_530_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_530_REGOFF) |
| #define HWIO_DDR_PHY_530_PHY_ADR_CALVL_OBS0_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_530_PHY_ADR_CALVL_OBS0_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_531_REGOFF 0x84c |
| #define HWIO_DDR_PHY_531_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_531_REGOFF) |
| #define HWIO_DDR_PHY_531_PHY_ADR_CALVL_OBS1_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_531_PHY_ADR_CALVL_OBS1_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_532_REGOFF 0x850 |
| #define HWIO_DDR_PHY_532_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_532_REGOFF) |
| #define HWIO_DDR_PHY_532_PHY_ADR_CALVL_FG_0_0_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_532_PHY_ADR_CALVL_FG_0_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_532_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_532_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_532_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_532_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_533_REGOFF 0x854 |
| #define HWIO_DDR_PHY_533_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_533_REGOFF) |
| #define HWIO_DDR_PHY_533_PHY_ADR_CALVL_BG_0_0_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_533_PHY_ADR_CALVL_BG_0_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_533_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_533_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_533_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_533_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_534_REGOFF 0x858 |
| #define HWIO_DDR_PHY_534_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_534_REGOFF) |
| #define HWIO_DDR_PHY_534_PHY_ADR_CALVL_FG_1_0_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_534_PHY_ADR_CALVL_FG_1_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_534_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_534_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_534_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_534_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_535_REGOFF 0x85c |
| #define HWIO_DDR_PHY_535_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_535_REGOFF) |
| #define HWIO_DDR_PHY_535_PHY_ADR_CALVL_BG_1_0_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_535_PHY_ADR_CALVL_BG_1_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_535_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_535_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_535_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_535_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_536_REGOFF 0x860 |
| #define HWIO_DDR_PHY_536_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_536_REGOFF) |
| #define HWIO_DDR_PHY_536_PHY_ADR_CALVL_FG_2_0_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_536_PHY_ADR_CALVL_FG_2_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_536_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_536_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_536_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_536_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_537_REGOFF 0x864 |
| #define HWIO_DDR_PHY_537_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_537_REGOFF) |
| #define HWIO_DDR_PHY_537_PHY_ADR_CALVL_BG_2_0_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_537_PHY_ADR_CALVL_BG_2_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_537_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_537_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_537_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_537_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_538_REGOFF 0x868 |
| #define HWIO_DDR_PHY_538_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_538_REGOFF) |
| #define HWIO_DDR_PHY_538_PHY_ADR_CALVL_FG_3_0_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_538_PHY_ADR_CALVL_FG_3_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_538_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_538_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_538_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_538_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_539_REGOFF 0x86c |
| #define HWIO_DDR_PHY_539_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_539_REGOFF) |
| #define HWIO_DDR_PHY_539_PHY_ADR_CALVL_BG_3_0_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_539_PHY_ADR_CALVL_BG_3_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_539_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_539_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_539_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_539_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_540_REGOFF 0x870 |
| #define HWIO_DDR_PHY_540_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_540_REGOFF) |
| #define HWIO_DDR_PHY_540_PHY_ADR_ADDR_SEL_0_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_540_PHY_ADR_ADDR_SEL_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_540_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_540_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_541_REGOFF 0x874 |
| #define HWIO_DDR_PHY_541_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_541_REGOFF) |
| #define HWIO_DDR_PHY_541_PHY_ADR_LP4_BOOT_SLV_DELAY_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_541_PHY_ADR_LP4_BOOT_SLV_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_541_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_541_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_541_PHY_ADR_BIT_MASK_0_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_541_PHY_ADR_BIT_MASK_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_541_RESERVED1_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_541_RESERVED1_FLDSHFT (22) |
| #define HWIO_DDR_PHY_541_PHY_ADR_SEG_MASK_0_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_541_PHY_ADR_SEG_MASK_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_541_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_541_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_542_REGOFF 0x878 |
| #define HWIO_DDR_PHY_542_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_542_REGOFF) |
| #define HWIO_DDR_PHY_542_PHY_ADR_CALVL_TRAIN_MASK_0_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_542_PHY_ADR_CALVL_TRAIN_MASK_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_542_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_542_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_542_PHY_ADR_SW_TXIO_CTRL_0_FLDMASK (0x3f00) |
| #define HWIO_DDR_PHY_542_PHY_ADR_SW_TXIO_CTRL_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_542_RESERVED1_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_542_RESERVED1_FLDSHFT (14) |
| #define HWIO_DDR_PHY_542_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_542_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_543_REGOFF 0x87c |
| #define HWIO_DDR_PHY_543_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_543_REGOFF) |
| #define HWIO_DDR_PHY_543_PHY_ADR_TSEL_SELECT_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_543_PHY_ADR_TSEL_SELECT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_543_PHY_ADR0_CLK_WR_SLAVE_DELAY_0_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_543_PHY_ADR0_CLK_WR_SLAVE_DELAY_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_543_RESERVED_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_543_RESERVED_FLDSHFT (19) |
| #define HWIO_DDR_PHY_543_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_543_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_544_REGOFF 0x880 |
| #define HWIO_DDR_PHY_544_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_544_REGOFF) |
| #define HWIO_DDR_PHY_544_PHY_ADR1_CLK_WR_SLAVE_DELAY_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_544_PHY_ADR1_CLK_WR_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_544_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_544_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_544_PHY_ADR2_CLK_WR_SLAVE_DELAY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_544_PHY_ADR2_CLK_WR_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_544_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_544_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_545_REGOFF 0x884 |
| #define HWIO_DDR_PHY_545_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_545_REGOFF) |
| #define HWIO_DDR_PHY_545_PHY_ADR3_CLK_WR_SLAVE_DELAY_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_545_PHY_ADR3_CLK_WR_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_545_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_545_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_545_PHY_ADR4_CLK_WR_SLAVE_DELAY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_545_PHY_ADR4_CLK_WR_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_545_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_545_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_546_REGOFF 0x888 |
| #define HWIO_DDR_PHY_546_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_546_REGOFF) |
| #define HWIO_DDR_PHY_546_PHY_ADR5_CLK_WR_SLAVE_DELAY_0_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_546_PHY_ADR5_CLK_WR_SLAVE_DELAY_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_546_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_546_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_546_PHY_ADR_SW_MASTER_MODE_0_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_546_PHY_ADR_SW_MASTER_MODE_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_546_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_546_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_546_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_546_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_547_REGOFF 0x88c |
| #define HWIO_DDR_PHY_547_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_547_REGOFF) |
| #define HWIO_DDR_PHY_547_PHY_ADR_MASTER_DELAY_START_0_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_547_PHY_ADR_MASTER_DELAY_START_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_547_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_547_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_547_PHY_ADR_MASTER_DELAY_STEP_0_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_547_PHY_ADR_MASTER_DELAY_STEP_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_547_RESERVED1_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_547_RESERVED1_FLDSHFT (22) |
| #define HWIO_DDR_PHY_547_PHY_ADR_MASTER_DELAY_WAIT_0_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_547_PHY_ADR_MASTER_DELAY_WAIT_0_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_548_REGOFF 0x890 |
| #define HWIO_DDR_PHY_548_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_548_REGOFF) |
| #define HWIO_DDR_PHY_548_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_548_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_548_PHY_ADR_CALVL_DLY_STEP_0_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_548_PHY_ADR_CALVL_DLY_STEP_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_548_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_548_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_548_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_548_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_549_REGOFF 0x894 |
| #define HWIO_DDR_PHY_549_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_549_REGOFF) |
| #define HWIO_DDR_PHY_549_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_549_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_550_REGOFF 0x898 |
| #define HWIO_DDR_PHY_550_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_550_REGOFF) |
| #define HWIO_DDR_PHY_550_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_550_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_551_REGOFF 0x89c |
| #define HWIO_DDR_PHY_551_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_551_REGOFF) |
| #define HWIO_DDR_PHY_551_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_551_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_552_REGOFF 0x8a0 |
| #define HWIO_DDR_PHY_552_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_552_REGOFF) |
| #define HWIO_DDR_PHY_552_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_552_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_553_REGOFF 0x8a4 |
| #define HWIO_DDR_PHY_553_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_553_REGOFF) |
| #define HWIO_DDR_PHY_553_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_553_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_554_REGOFF 0x8a8 |
| #define HWIO_DDR_PHY_554_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_554_REGOFF) |
| #define HWIO_DDR_PHY_554_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_554_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_555_REGOFF 0x8ac |
| #define HWIO_DDR_PHY_555_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_555_REGOFF) |
| #define HWIO_DDR_PHY_555_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_555_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_556_REGOFF 0x8b0 |
| #define HWIO_DDR_PHY_556_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_556_REGOFF) |
| #define HWIO_DDR_PHY_556_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_556_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_557_REGOFF 0x8b4 |
| #define HWIO_DDR_PHY_557_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_557_REGOFF) |
| #define HWIO_DDR_PHY_557_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_557_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_558_REGOFF 0x8b8 |
| #define HWIO_DDR_PHY_558_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_558_REGOFF) |
| #define HWIO_DDR_PHY_558_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_558_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_559_REGOFF 0x8bc |
| #define HWIO_DDR_PHY_559_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_559_REGOFF) |
| #define HWIO_DDR_PHY_559_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_559_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_560_REGOFF 0x8c0 |
| #define HWIO_DDR_PHY_560_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_560_REGOFF) |
| #define HWIO_DDR_PHY_560_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_560_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_561_REGOFF 0x8c4 |
| #define HWIO_DDR_PHY_561_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_561_REGOFF) |
| #define HWIO_DDR_PHY_561_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_561_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_562_REGOFF 0x8c8 |
| #define HWIO_DDR_PHY_562_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_562_REGOFF) |
| #define HWIO_DDR_PHY_562_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_562_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_563_REGOFF 0x8cc |
| #define HWIO_DDR_PHY_563_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_563_REGOFF) |
| #define HWIO_DDR_PHY_563_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_563_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_564_REGOFF 0x8d0 |
| #define HWIO_DDR_PHY_564_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_564_REGOFF) |
| #define HWIO_DDR_PHY_564_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_564_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_565_REGOFF 0x8d4 |
| #define HWIO_DDR_PHY_565_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_565_REGOFF) |
| #define HWIO_DDR_PHY_565_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_565_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_566_REGOFF 0x8d8 |
| #define HWIO_DDR_PHY_566_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_566_REGOFF) |
| #define HWIO_DDR_PHY_566_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_566_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_567_REGOFF 0x8dc |
| #define HWIO_DDR_PHY_567_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_567_REGOFF) |
| #define HWIO_DDR_PHY_567_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_567_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_568_REGOFF 0x8e0 |
| #define HWIO_DDR_PHY_568_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_568_REGOFF) |
| #define HWIO_DDR_PHY_568_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_568_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_569_REGOFF 0x8e4 |
| #define HWIO_DDR_PHY_569_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_569_REGOFF) |
| #define HWIO_DDR_PHY_569_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_569_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_570_REGOFF 0x8e8 |
| #define HWIO_DDR_PHY_570_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_570_REGOFF) |
| #define HWIO_DDR_PHY_570_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_570_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_571_REGOFF 0x8ec |
| #define HWIO_DDR_PHY_571_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_571_REGOFF) |
| #define HWIO_DDR_PHY_571_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_571_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_572_REGOFF 0x8f0 |
| #define HWIO_DDR_PHY_572_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_572_REGOFF) |
| #define HWIO_DDR_PHY_572_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_572_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_573_REGOFF 0x8f4 |
| #define HWIO_DDR_PHY_573_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_573_REGOFF) |
| #define HWIO_DDR_PHY_573_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_573_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_574_REGOFF 0x8f8 |
| #define HWIO_DDR_PHY_574_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_574_REGOFF) |
| #define HWIO_DDR_PHY_574_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_574_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_575_REGOFF 0x8fc |
| #define HWIO_DDR_PHY_575_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_575_REGOFF) |
| #define HWIO_DDR_PHY_575_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_575_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_576_REGOFF 0x900 |
| #define HWIO_DDR_PHY_576_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_576_REGOFF) |
| #define HWIO_DDR_PHY_576_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_576_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_577_REGOFF 0x904 |
| #define HWIO_DDR_PHY_577_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_577_REGOFF) |
| #define HWIO_DDR_PHY_577_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_577_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_578_REGOFF 0x908 |
| #define HWIO_DDR_PHY_578_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_578_REGOFF) |
| #define HWIO_DDR_PHY_578_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_578_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_579_REGOFF 0x90c |
| #define HWIO_DDR_PHY_579_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_579_REGOFF) |
| #define HWIO_DDR_PHY_579_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_579_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_580_REGOFF 0x910 |
| #define HWIO_DDR_PHY_580_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_580_REGOFF) |
| #define HWIO_DDR_PHY_580_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_580_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_581_REGOFF 0x914 |
| #define HWIO_DDR_PHY_581_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_581_REGOFF) |
| #define HWIO_DDR_PHY_581_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_581_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_582_REGOFF 0x918 |
| #define HWIO_DDR_PHY_582_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_582_REGOFF) |
| #define HWIO_DDR_PHY_582_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_582_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_583_REGOFF 0x91c |
| #define HWIO_DDR_PHY_583_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_583_REGOFF) |
| #define HWIO_DDR_PHY_583_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_583_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_584_REGOFF 0x920 |
| #define HWIO_DDR_PHY_584_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_584_REGOFF) |
| #define HWIO_DDR_PHY_584_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_584_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_585_REGOFF 0x924 |
| #define HWIO_DDR_PHY_585_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_585_REGOFF) |
| #define HWIO_DDR_PHY_585_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_585_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_586_REGOFF 0x928 |
| #define HWIO_DDR_PHY_586_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_586_REGOFF) |
| #define HWIO_DDR_PHY_586_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_586_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_587_REGOFF 0x92c |
| #define HWIO_DDR_PHY_587_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_587_REGOFF) |
| #define HWIO_DDR_PHY_587_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_587_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_588_REGOFF 0x930 |
| #define HWIO_DDR_PHY_588_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_588_REGOFF) |
| #define HWIO_DDR_PHY_588_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_588_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_589_REGOFF 0x934 |
| #define HWIO_DDR_PHY_589_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_589_REGOFF) |
| #define HWIO_DDR_PHY_589_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_589_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_590_REGOFF 0x938 |
| #define HWIO_DDR_PHY_590_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_590_REGOFF) |
| #define HWIO_DDR_PHY_590_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_590_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_591_REGOFF 0x93c |
| #define HWIO_DDR_PHY_591_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_591_REGOFF) |
| #define HWIO_DDR_PHY_591_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_591_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_592_REGOFF 0x940 |
| #define HWIO_DDR_PHY_592_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_592_REGOFF) |
| #define HWIO_DDR_PHY_592_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_592_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_593_REGOFF 0x944 |
| #define HWIO_DDR_PHY_593_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_593_REGOFF) |
| #define HWIO_DDR_PHY_593_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_593_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_594_REGOFF 0x948 |
| #define HWIO_DDR_PHY_594_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_594_REGOFF) |
| #define HWIO_DDR_PHY_594_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_594_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_595_REGOFF 0x94c |
| #define HWIO_DDR_PHY_595_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_595_REGOFF) |
| #define HWIO_DDR_PHY_595_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_595_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_596_REGOFF 0x950 |
| #define HWIO_DDR_PHY_596_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_596_REGOFF) |
| #define HWIO_DDR_PHY_596_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_596_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_597_REGOFF 0x954 |
| #define HWIO_DDR_PHY_597_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_597_REGOFF) |
| #define HWIO_DDR_PHY_597_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_597_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_598_REGOFF 0x958 |
| #define HWIO_DDR_PHY_598_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_598_REGOFF) |
| #define HWIO_DDR_PHY_598_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_598_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_599_REGOFF 0x95c |
| #define HWIO_DDR_PHY_599_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_599_REGOFF) |
| #define HWIO_DDR_PHY_599_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_599_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_600_REGOFF 0x960 |
| #define HWIO_DDR_PHY_600_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_600_REGOFF) |
| #define HWIO_DDR_PHY_600_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_600_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_601_REGOFF 0x964 |
| #define HWIO_DDR_PHY_601_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_601_REGOFF) |
| #define HWIO_DDR_PHY_601_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_601_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_602_REGOFF 0x968 |
| #define HWIO_DDR_PHY_602_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_602_REGOFF) |
| #define HWIO_DDR_PHY_602_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_602_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_603_REGOFF 0x96c |
| #define HWIO_DDR_PHY_603_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_603_REGOFF) |
| #define HWIO_DDR_PHY_603_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_603_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_604_REGOFF 0x970 |
| #define HWIO_DDR_PHY_604_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_604_REGOFF) |
| #define HWIO_DDR_PHY_604_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_604_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_605_REGOFF 0x974 |
| #define HWIO_DDR_PHY_605_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_605_REGOFF) |
| #define HWIO_DDR_PHY_605_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_605_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_606_REGOFF 0x978 |
| #define HWIO_DDR_PHY_606_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_606_REGOFF) |
| #define HWIO_DDR_PHY_606_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_606_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_607_REGOFF 0x97c |
| #define HWIO_DDR_PHY_607_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_607_REGOFF) |
| #define HWIO_DDR_PHY_607_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_607_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_608_REGOFF 0x980 |
| #define HWIO_DDR_PHY_608_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_608_REGOFF) |
| #define HWIO_DDR_PHY_608_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_608_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_609_REGOFF 0x984 |
| #define HWIO_DDR_PHY_609_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_609_REGOFF) |
| #define HWIO_DDR_PHY_609_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_609_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_610_REGOFF 0x988 |
| #define HWIO_DDR_PHY_610_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_610_REGOFF) |
| #define HWIO_DDR_PHY_610_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_610_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_611_REGOFF 0x98c |
| #define HWIO_DDR_PHY_611_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_611_REGOFF) |
| #define HWIO_DDR_PHY_611_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_611_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_612_REGOFF 0x990 |
| #define HWIO_DDR_PHY_612_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_612_REGOFF) |
| #define HWIO_DDR_PHY_612_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_612_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_613_REGOFF 0x994 |
| #define HWIO_DDR_PHY_613_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_613_REGOFF) |
| #define HWIO_DDR_PHY_613_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_613_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_614_REGOFF 0x998 |
| #define HWIO_DDR_PHY_614_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_614_REGOFF) |
| #define HWIO_DDR_PHY_614_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_614_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_615_REGOFF 0x99c |
| #define HWIO_DDR_PHY_615_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_615_REGOFF) |
| #define HWIO_DDR_PHY_615_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_615_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_616_REGOFF 0x9a0 |
| #define HWIO_DDR_PHY_616_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_616_REGOFF) |
| #define HWIO_DDR_PHY_616_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_616_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_617_REGOFF 0x9a4 |
| #define HWIO_DDR_PHY_617_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_617_REGOFF) |
| #define HWIO_DDR_PHY_617_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_617_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_618_REGOFF 0x9a8 |
| #define HWIO_DDR_PHY_618_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_618_REGOFF) |
| #define HWIO_DDR_PHY_618_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_618_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_619_REGOFF 0x9ac |
| #define HWIO_DDR_PHY_619_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_619_REGOFF) |
| #define HWIO_DDR_PHY_619_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_619_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_620_REGOFF 0x9b0 |
| #define HWIO_DDR_PHY_620_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_620_REGOFF) |
| #define HWIO_DDR_PHY_620_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_620_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_621_REGOFF 0x9b4 |
| #define HWIO_DDR_PHY_621_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_621_REGOFF) |
| #define HWIO_DDR_PHY_621_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_621_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_622_REGOFF 0x9b8 |
| #define HWIO_DDR_PHY_622_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_622_REGOFF) |
| #define HWIO_DDR_PHY_622_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_622_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_623_REGOFF 0x9bc |
| #define HWIO_DDR_PHY_623_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_623_REGOFF) |
| #define HWIO_DDR_PHY_623_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_623_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_624_REGOFF 0x9c0 |
| #define HWIO_DDR_PHY_624_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_624_REGOFF) |
| #define HWIO_DDR_PHY_624_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_624_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_625_REGOFF 0x9c4 |
| #define HWIO_DDR_PHY_625_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_625_REGOFF) |
| #define HWIO_DDR_PHY_625_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_625_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_626_REGOFF 0x9c8 |
| #define HWIO_DDR_PHY_626_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_626_REGOFF) |
| #define HWIO_DDR_PHY_626_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_626_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_627_REGOFF 0x9cc |
| #define HWIO_DDR_PHY_627_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_627_REGOFF) |
| #define HWIO_DDR_PHY_627_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_627_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_628_REGOFF 0x9d0 |
| #define HWIO_DDR_PHY_628_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_628_REGOFF) |
| #define HWIO_DDR_PHY_628_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_628_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_629_REGOFF 0x9d4 |
| #define HWIO_DDR_PHY_629_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_629_REGOFF) |
| #define HWIO_DDR_PHY_629_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_629_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_630_REGOFF 0x9d8 |
| #define HWIO_DDR_PHY_630_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_630_REGOFF) |
| #define HWIO_DDR_PHY_630_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_630_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_631_REGOFF 0x9dc |
| #define HWIO_DDR_PHY_631_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_631_REGOFF) |
| #define HWIO_DDR_PHY_631_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_631_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_632_REGOFF 0x9e0 |
| #define HWIO_DDR_PHY_632_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_632_REGOFF) |
| #define HWIO_DDR_PHY_632_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_632_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_633_REGOFF 0x9e4 |
| #define HWIO_DDR_PHY_633_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_633_REGOFF) |
| #define HWIO_DDR_PHY_633_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_633_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_634_REGOFF 0x9e8 |
| #define HWIO_DDR_PHY_634_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_634_REGOFF) |
| #define HWIO_DDR_PHY_634_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_634_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_635_REGOFF 0x9ec |
| #define HWIO_DDR_PHY_635_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_635_REGOFF) |
| #define HWIO_DDR_PHY_635_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_635_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_636_REGOFF 0x9f0 |
| #define HWIO_DDR_PHY_636_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_636_REGOFF) |
| #define HWIO_DDR_PHY_636_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_636_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_637_REGOFF 0x9f4 |
| #define HWIO_DDR_PHY_637_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_637_REGOFF) |
| #define HWIO_DDR_PHY_637_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_637_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_638_REGOFF 0x9f8 |
| #define HWIO_DDR_PHY_638_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_638_REGOFF) |
| #define HWIO_DDR_PHY_638_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_638_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_639_REGOFF 0x9fc |
| #define HWIO_DDR_PHY_639_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_639_REGOFF) |
| #define HWIO_DDR_PHY_639_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_639_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_640_REGOFF 0xa00 |
| #define HWIO_DDR_PHY_640_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_640_REGOFF) |
| #define HWIO_DDR_PHY_640_PHY_ADR0_SW_WRADDR_SHIFT_1_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_640_PHY_ADR0_SW_WRADDR_SHIFT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_640_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_640_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_640_PHY_ADR1_SW_WRADDR_SHIFT_1_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_640_PHY_ADR1_SW_WRADDR_SHIFT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_640_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_640_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_640_PHY_ADR2_SW_WRADDR_SHIFT_1_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_640_PHY_ADR2_SW_WRADDR_SHIFT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_640_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_640_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_640_PHY_ADR3_SW_WRADDR_SHIFT_1_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_640_PHY_ADR3_SW_WRADDR_SHIFT_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_640_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_640_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_641_REGOFF 0xa04 |
| #define HWIO_DDR_PHY_641_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_641_REGOFF) |
| #define HWIO_DDR_PHY_641_PHY_ADR4_SW_WRADDR_SHIFT_1_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_641_PHY_ADR4_SW_WRADDR_SHIFT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_641_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_641_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_641_PHY_ADR5_SW_WRADDR_SHIFT_1_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_641_PHY_ADR5_SW_WRADDR_SHIFT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_641_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_641_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_641_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_641_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_641_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_641_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_642_REGOFF 0xa08 |
| #define HWIO_DDR_PHY_642_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_642_REGOFF) |
| #define HWIO_DDR_PHY_642_PHY_ADR_CLK_BYPASS_OVERRIDE_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_642_PHY_ADR_CLK_BYPASS_OVERRIDE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_642_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_642_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_642_SC_PHY_ADR_MANUAL_CLEAR_1_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_642_SC_PHY_ADR_MANUAL_CLEAR_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_642_RESERVED1_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_642_RESERVED1_FLDSHFT (11) |
| #define HWIO_DDR_PHY_642_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_642_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_643_REGOFF 0xa0c |
| #define HWIO_DDR_PHY_643_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_643_REGOFF) |
| #define HWIO_DDR_PHY_643_PHY_ADR_LPBK_RESULT_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_643_PHY_ADR_LPBK_RESULT_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_644_REGOFF 0xa10 |
| #define HWIO_DDR_PHY_644_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_644_REGOFF) |
| #define HWIO_DDR_PHY_644_PHY_ADR_LPBK_ERROR_COUNT_OBS_1_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_644_PHY_ADR_LPBK_ERROR_COUNT_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_644_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_644_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_644_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_644_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_644_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_644_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_645_REGOFF 0xa14 |
| #define HWIO_DDR_PHY_645_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_645_REGOFF) |
| #define HWIO_DDR_PHY_645_PHY_ADR_MASTER_DLY_LOCK_OBS_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_645_PHY_ADR_MASTER_DLY_LOCK_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_645_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_645_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_645_PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_645_PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_645_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_645_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_646_REGOFF 0xa18 |
| #define HWIO_DDR_PHY_646_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_646_REGOFF) |
| #define HWIO_DDR_PHY_646_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_646_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_646_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_646_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_646_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_646_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_646_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_646_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_646_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_646_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_646_SC_PHY_ADR_SNAP_OBS_REGS_1_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_646_SC_PHY_ADR_SNAP_OBS_REGS_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_646_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_646_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_647_REGOFF 0xa1c |
| #define HWIO_DDR_PHY_647_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_647_REGOFF) |
| #define HWIO_DDR_PHY_647_PHY_ADR_TSEL_ENABLE_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_647_PHY_ADR_TSEL_ENABLE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_647_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_647_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_647_PHY_ADR_LPBK_CONTROL_1_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_647_PHY_ADR_LPBK_CONTROL_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_647_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_647_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_647_PHY_ADR_PRBS_PATTERN_START_1_FLDMASK (0x7f0000) |
| #define HWIO_DDR_PHY_647_PHY_ADR_PRBS_PATTERN_START_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_647_RESERVED2_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_647_RESERVED2_FLDSHFT (23) |
| #define HWIO_DDR_PHY_647_PHY_ADR_PRBS_PATTERN_MASK_1_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_647_PHY_ADR_PRBS_PATTERN_MASK_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_647_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_647_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_648_REGOFF 0xa20 |
| #define HWIO_DDR_PHY_648_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_648_REGOFF) |
| #define HWIO_DDR_PHY_648_PHY_ADR_PWR_RDC_DISABLE_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_648_PHY_ADR_PWR_RDC_DISABLE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_648_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_648_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_648_PHY_ADR_TYPE_1_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_648_PHY_ADR_TYPE_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_648_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_648_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_648_PHY_ADR_WRADDR_SHIFT_OBS_1_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_648_PHY_ADR_WRADDR_SHIFT_OBS_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_648_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_648_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_648_PHY_ADR_IE_MODE_1_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_648_PHY_ADR_IE_MODE_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_648_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_648_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_649_REGOFF 0xa24 |
| #define HWIO_DDR_PHY_649_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_649_REGOFF) |
| #define HWIO_DDR_PHY_649_PHY_ADR_DDL_MODE_1_FLDMASK (0x7fff) |
| #define HWIO_DDR_PHY_649_PHY_ADR_DDL_MODE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_649_RESERVED_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_649_RESERVED_FLDSHFT (15) |
| #define HWIO_DDR_PHY_649_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_649_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_650_REGOFF 0xa28 |
| #define HWIO_DDR_PHY_650_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_650_REGOFF) |
| #define HWIO_DDR_PHY_650_PHY_ADR_DDL_TEST_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_650_PHY_ADR_DDL_TEST_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_651_REGOFF 0xa2c |
| #define HWIO_DDR_PHY_651_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_651_REGOFF) |
| #define HWIO_DDR_PHY_651_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_651_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_652_REGOFF 0xa30 |
| #define HWIO_DDR_PHY_652_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_652_REGOFF) |
| #define HWIO_DDR_PHY_652_PHY_ADR_CALVL_START_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_652_PHY_ADR_CALVL_START_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_652_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_652_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_652_PHY_ADR_CALVL_COARSE_DLY_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_652_PHY_ADR_CALVL_COARSE_DLY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_652_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_652_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_653_REGOFF 0xa34 |
| #define HWIO_DDR_PHY_653_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_653_REGOFF) |
| #define HWIO_DDR_PHY_653_PHY_ADR_CALVL_QTR_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_653_PHY_ADR_CALVL_QTR_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_653_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_653_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_653_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_653_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_654_REGOFF 0xa38 |
| #define HWIO_DDR_PHY_654_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_654_REGOFF) |
| #define HWIO_DDR_PHY_654_PHY_ADR_CALVL_SWIZZLE0_1_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_654_PHY_ADR_CALVL_SWIZZLE0_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_654_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_654_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_655_REGOFF 0xa3c |
| #define HWIO_DDR_PHY_655_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_655_REGOFF) |
| #define HWIO_DDR_PHY_655_PHY_ADR_CALVL_SWIZZLE1_1_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_655_PHY_ADR_CALVL_SWIZZLE1_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_655_PHY_ADR_CALVL_RANK_CTRL_1_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_655_PHY_ADR_CALVL_RANK_CTRL_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_655_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_655_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_656_REGOFF 0xa40 |
| #define HWIO_DDR_PHY_656_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_656_REGOFF) |
| #define HWIO_DDR_PHY_656_PHY_ADR_CALVL_NUM_PATTERNS_1_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_656_PHY_ADR_CALVL_NUM_PATTERNS_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_656_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_656_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_656_PHY_ADR_CALVL_CAPTURE_CNT_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_656_PHY_ADR_CALVL_CAPTURE_CNT_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_656_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_656_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_656_PHY_ADR_CALVL_RESP_WAIT_CNT_1_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_656_PHY_ADR_CALVL_RESP_WAIT_CNT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_656_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_656_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_656_PHY_ADR_CALVL_DEBUG_MODE_1_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_656_PHY_ADR_CALVL_DEBUG_MODE_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_656_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_656_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_657_REGOFF 0xa44 |
| #define HWIO_DDR_PHY_657_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_657_REGOFF) |
| #define HWIO_DDR_PHY_657_SC_PHY_ADR_CALVL_DEBUG_CONT_1_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_657_SC_PHY_ADR_CALVL_DEBUG_CONT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_657_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_657_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_657_SC_PHY_ADR_CALVL_ERROR_CLR_1_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_657_SC_PHY_ADR_CALVL_ERROR_CLR_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_657_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_657_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_657_PHY_ADR_CALVL_OBS_SELECT_1_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_657_PHY_ADR_CALVL_OBS_SELECT_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_657_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_657_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_657_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_657_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_658_REGOFF 0xa48 |
| #define HWIO_DDR_PHY_658_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_658_REGOFF) |
| #define HWIO_DDR_PHY_658_PHY_ADR_CALVL_OBS0_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_658_PHY_ADR_CALVL_OBS0_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_659_REGOFF 0xa4c |
| #define HWIO_DDR_PHY_659_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_659_REGOFF) |
| #define HWIO_DDR_PHY_659_PHY_ADR_CALVL_OBS1_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_659_PHY_ADR_CALVL_OBS1_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_660_REGOFF 0xa50 |
| #define HWIO_DDR_PHY_660_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_660_REGOFF) |
| #define HWIO_DDR_PHY_660_PHY_ADR_CALVL_FG_0_1_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_660_PHY_ADR_CALVL_FG_0_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_660_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_660_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_660_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_660_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_661_REGOFF 0xa54 |
| #define HWIO_DDR_PHY_661_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_661_REGOFF) |
| #define HWIO_DDR_PHY_661_PHY_ADR_CALVL_BG_0_1_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_661_PHY_ADR_CALVL_BG_0_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_661_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_661_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_661_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_661_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_662_REGOFF 0xa58 |
| #define HWIO_DDR_PHY_662_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_662_REGOFF) |
| #define HWIO_DDR_PHY_662_PHY_ADR_CALVL_FG_1_1_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_662_PHY_ADR_CALVL_FG_1_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_662_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_662_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_662_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_662_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_663_REGOFF 0xa5c |
| #define HWIO_DDR_PHY_663_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_663_REGOFF) |
| #define HWIO_DDR_PHY_663_PHY_ADR_CALVL_BG_1_1_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_663_PHY_ADR_CALVL_BG_1_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_663_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_663_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_663_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_663_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_664_REGOFF 0xa60 |
| #define HWIO_DDR_PHY_664_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_664_REGOFF) |
| #define HWIO_DDR_PHY_664_PHY_ADR_CALVL_FG_2_1_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_664_PHY_ADR_CALVL_FG_2_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_664_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_664_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_664_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_664_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_665_REGOFF 0xa64 |
| #define HWIO_DDR_PHY_665_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_665_REGOFF) |
| #define HWIO_DDR_PHY_665_PHY_ADR_CALVL_BG_2_1_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_665_PHY_ADR_CALVL_BG_2_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_665_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_665_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_665_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_665_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_666_REGOFF 0xa68 |
| #define HWIO_DDR_PHY_666_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_666_REGOFF) |
| #define HWIO_DDR_PHY_666_PHY_ADR_CALVL_FG_3_1_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_666_PHY_ADR_CALVL_FG_3_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_666_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_666_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_666_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_666_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_667_REGOFF 0xa6c |
| #define HWIO_DDR_PHY_667_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_667_REGOFF) |
| #define HWIO_DDR_PHY_667_PHY_ADR_CALVL_BG_3_1_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_667_PHY_ADR_CALVL_BG_3_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_667_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_667_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_667_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_667_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_668_REGOFF 0xa70 |
| #define HWIO_DDR_PHY_668_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_668_REGOFF) |
| #define HWIO_DDR_PHY_668_PHY_ADR_ADDR_SEL_1_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_668_PHY_ADR_ADDR_SEL_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_668_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_668_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_669_REGOFF 0xa74 |
| #define HWIO_DDR_PHY_669_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_669_REGOFF) |
| #define HWIO_DDR_PHY_669_PHY_ADR_LP4_BOOT_SLV_DELAY_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_669_PHY_ADR_LP4_BOOT_SLV_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_669_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_669_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_669_PHY_ADR_BIT_MASK_1_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_669_PHY_ADR_BIT_MASK_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_669_RESERVED1_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_669_RESERVED1_FLDSHFT (22) |
| #define HWIO_DDR_PHY_669_PHY_ADR_SEG_MASK_1_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_669_PHY_ADR_SEG_MASK_1_FLDSHFT (24) |
| #define HWIO_DDR_PHY_669_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_669_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_670_REGOFF 0xa78 |
| #define HWIO_DDR_PHY_670_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_670_REGOFF) |
| #define HWIO_DDR_PHY_670_PHY_ADR_CALVL_TRAIN_MASK_1_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_670_PHY_ADR_CALVL_TRAIN_MASK_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_670_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_670_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_670_PHY_ADR_SW_TXIO_CTRL_1_FLDMASK (0x3f00) |
| #define HWIO_DDR_PHY_670_PHY_ADR_SW_TXIO_CTRL_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_670_RESERVED1_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_670_RESERVED1_FLDSHFT (14) |
| #define HWIO_DDR_PHY_670_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_670_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_671_REGOFF 0xa7c |
| #define HWIO_DDR_PHY_671_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_671_REGOFF) |
| #define HWIO_DDR_PHY_671_PHY_ADR_TSEL_SELECT_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_671_PHY_ADR_TSEL_SELECT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_671_PHY_ADR0_CLK_WR_SLAVE_DELAY_1_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_671_PHY_ADR0_CLK_WR_SLAVE_DELAY_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_671_RESERVED_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_671_RESERVED_FLDSHFT (19) |
| #define HWIO_DDR_PHY_671_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_671_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_672_REGOFF 0xa80 |
| #define HWIO_DDR_PHY_672_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_672_REGOFF) |
| #define HWIO_DDR_PHY_672_PHY_ADR1_CLK_WR_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_672_PHY_ADR1_CLK_WR_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_672_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_672_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_672_PHY_ADR2_CLK_WR_SLAVE_DELAY_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_672_PHY_ADR2_CLK_WR_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_672_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_672_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_673_REGOFF 0xa84 |
| #define HWIO_DDR_PHY_673_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_673_REGOFF) |
| #define HWIO_DDR_PHY_673_PHY_ADR3_CLK_WR_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_673_PHY_ADR3_CLK_WR_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_673_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_673_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_673_PHY_ADR4_CLK_WR_SLAVE_DELAY_1_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_673_PHY_ADR4_CLK_WR_SLAVE_DELAY_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_673_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_673_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_674_REGOFF 0xa88 |
| #define HWIO_DDR_PHY_674_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_674_REGOFF) |
| #define HWIO_DDR_PHY_674_PHY_ADR5_CLK_WR_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_674_PHY_ADR5_CLK_WR_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_674_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_674_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_674_PHY_ADR_SW_MASTER_MODE_1_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_674_PHY_ADR_SW_MASTER_MODE_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_674_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_674_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_674_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_674_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_675_REGOFF 0xa8c |
| #define HWIO_DDR_PHY_675_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_675_REGOFF) |
| #define HWIO_DDR_PHY_675_PHY_ADR_MASTER_DELAY_START_1_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_675_PHY_ADR_MASTER_DELAY_START_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_675_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_675_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_675_PHY_ADR_MASTER_DELAY_STEP_1_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_675_PHY_ADR_MASTER_DELAY_STEP_1_FLDSHFT (16) |
| #define HWIO_DDR_PHY_675_RESERVED1_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_675_RESERVED1_FLDSHFT (22) |
| #define HWIO_DDR_PHY_675_PHY_ADR_MASTER_DELAY_WAIT_1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_675_PHY_ADR_MASTER_DELAY_WAIT_1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_676_REGOFF 0xa90 |
| #define HWIO_DDR_PHY_676_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_676_REGOFF) |
| #define HWIO_DDR_PHY_676_PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_676_PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_676_PHY_ADR_CALVL_DLY_STEP_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_676_PHY_ADR_CALVL_DLY_STEP_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_676_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_676_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_676_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_676_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_677_REGOFF 0xa94 |
| #define HWIO_DDR_PHY_677_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_677_REGOFF) |
| #define HWIO_DDR_PHY_677_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_677_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_678_REGOFF 0xa98 |
| #define HWIO_DDR_PHY_678_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_678_REGOFF) |
| #define HWIO_DDR_PHY_678_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_678_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_679_REGOFF 0xa9c |
| #define HWIO_DDR_PHY_679_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_679_REGOFF) |
| #define HWIO_DDR_PHY_679_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_679_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_680_REGOFF 0xaa0 |
| #define HWIO_DDR_PHY_680_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_680_REGOFF) |
| #define HWIO_DDR_PHY_680_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_680_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_681_REGOFF 0xaa4 |
| #define HWIO_DDR_PHY_681_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_681_REGOFF) |
| #define HWIO_DDR_PHY_681_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_681_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_682_REGOFF 0xaa8 |
| #define HWIO_DDR_PHY_682_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_682_REGOFF) |
| #define HWIO_DDR_PHY_682_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_682_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_683_REGOFF 0xaac |
| #define HWIO_DDR_PHY_683_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_683_REGOFF) |
| #define HWIO_DDR_PHY_683_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_683_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_684_REGOFF 0xab0 |
| #define HWIO_DDR_PHY_684_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_684_REGOFF) |
| #define HWIO_DDR_PHY_684_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_684_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_685_REGOFF 0xab4 |
| #define HWIO_DDR_PHY_685_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_685_REGOFF) |
| #define HWIO_DDR_PHY_685_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_685_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_686_REGOFF 0xab8 |
| #define HWIO_DDR_PHY_686_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_686_REGOFF) |
| #define HWIO_DDR_PHY_686_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_686_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_687_REGOFF 0xabc |
| #define HWIO_DDR_PHY_687_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_687_REGOFF) |
| #define HWIO_DDR_PHY_687_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_687_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_688_REGOFF 0xac0 |
| #define HWIO_DDR_PHY_688_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_688_REGOFF) |
| #define HWIO_DDR_PHY_688_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_688_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_689_REGOFF 0xac4 |
| #define HWIO_DDR_PHY_689_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_689_REGOFF) |
| #define HWIO_DDR_PHY_689_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_689_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_690_REGOFF 0xac8 |
| #define HWIO_DDR_PHY_690_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_690_REGOFF) |
| #define HWIO_DDR_PHY_690_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_690_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_691_REGOFF 0xacc |
| #define HWIO_DDR_PHY_691_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_691_REGOFF) |
| #define HWIO_DDR_PHY_691_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_691_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_692_REGOFF 0xad0 |
| #define HWIO_DDR_PHY_692_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_692_REGOFF) |
| #define HWIO_DDR_PHY_692_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_692_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_693_REGOFF 0xad4 |
| #define HWIO_DDR_PHY_693_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_693_REGOFF) |
| #define HWIO_DDR_PHY_693_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_693_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_694_REGOFF 0xad8 |
| #define HWIO_DDR_PHY_694_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_694_REGOFF) |
| #define HWIO_DDR_PHY_694_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_694_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_695_REGOFF 0xadc |
| #define HWIO_DDR_PHY_695_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_695_REGOFF) |
| #define HWIO_DDR_PHY_695_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_695_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_696_REGOFF 0xae0 |
| #define HWIO_DDR_PHY_696_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_696_REGOFF) |
| #define HWIO_DDR_PHY_696_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_696_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_697_REGOFF 0xae4 |
| #define HWIO_DDR_PHY_697_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_697_REGOFF) |
| #define HWIO_DDR_PHY_697_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_697_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_698_REGOFF 0xae8 |
| #define HWIO_DDR_PHY_698_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_698_REGOFF) |
| #define HWIO_DDR_PHY_698_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_698_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_699_REGOFF 0xaec |
| #define HWIO_DDR_PHY_699_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_699_REGOFF) |
| #define HWIO_DDR_PHY_699_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_699_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_700_REGOFF 0xaf0 |
| #define HWIO_DDR_PHY_700_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_700_REGOFF) |
| #define HWIO_DDR_PHY_700_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_700_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_701_REGOFF 0xaf4 |
| #define HWIO_DDR_PHY_701_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_701_REGOFF) |
| #define HWIO_DDR_PHY_701_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_701_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_702_REGOFF 0xaf8 |
| #define HWIO_DDR_PHY_702_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_702_REGOFF) |
| #define HWIO_DDR_PHY_702_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_702_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_703_REGOFF 0xafc |
| #define HWIO_DDR_PHY_703_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_703_REGOFF) |
| #define HWIO_DDR_PHY_703_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_703_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_704_REGOFF 0xb00 |
| #define HWIO_DDR_PHY_704_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_704_REGOFF) |
| #define HWIO_DDR_PHY_704_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_704_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_705_REGOFF 0xb04 |
| #define HWIO_DDR_PHY_705_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_705_REGOFF) |
| #define HWIO_DDR_PHY_705_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_705_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_706_REGOFF 0xb08 |
| #define HWIO_DDR_PHY_706_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_706_REGOFF) |
| #define HWIO_DDR_PHY_706_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_706_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_707_REGOFF 0xb0c |
| #define HWIO_DDR_PHY_707_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_707_REGOFF) |
| #define HWIO_DDR_PHY_707_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_707_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_708_REGOFF 0xb10 |
| #define HWIO_DDR_PHY_708_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_708_REGOFF) |
| #define HWIO_DDR_PHY_708_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_708_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_709_REGOFF 0xb14 |
| #define HWIO_DDR_PHY_709_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_709_REGOFF) |
| #define HWIO_DDR_PHY_709_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_709_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_710_REGOFF 0xb18 |
| #define HWIO_DDR_PHY_710_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_710_REGOFF) |
| #define HWIO_DDR_PHY_710_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_710_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_711_REGOFF 0xb1c |
| #define HWIO_DDR_PHY_711_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_711_REGOFF) |
| #define HWIO_DDR_PHY_711_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_711_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_712_REGOFF 0xb20 |
| #define HWIO_DDR_PHY_712_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_712_REGOFF) |
| #define HWIO_DDR_PHY_712_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_712_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_713_REGOFF 0xb24 |
| #define HWIO_DDR_PHY_713_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_713_REGOFF) |
| #define HWIO_DDR_PHY_713_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_713_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_714_REGOFF 0xb28 |
| #define HWIO_DDR_PHY_714_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_714_REGOFF) |
| #define HWIO_DDR_PHY_714_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_714_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_715_REGOFF 0xb2c |
| #define HWIO_DDR_PHY_715_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_715_REGOFF) |
| #define HWIO_DDR_PHY_715_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_715_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_716_REGOFF 0xb30 |
| #define HWIO_DDR_PHY_716_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_716_REGOFF) |
| #define HWIO_DDR_PHY_716_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_716_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_717_REGOFF 0xb34 |
| #define HWIO_DDR_PHY_717_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_717_REGOFF) |
| #define HWIO_DDR_PHY_717_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_717_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_718_REGOFF 0xb38 |
| #define HWIO_DDR_PHY_718_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_718_REGOFF) |
| #define HWIO_DDR_PHY_718_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_718_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_719_REGOFF 0xb3c |
| #define HWIO_DDR_PHY_719_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_719_REGOFF) |
| #define HWIO_DDR_PHY_719_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_719_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_720_REGOFF 0xb40 |
| #define HWIO_DDR_PHY_720_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_720_REGOFF) |
| #define HWIO_DDR_PHY_720_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_720_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_721_REGOFF 0xb44 |
| #define HWIO_DDR_PHY_721_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_721_REGOFF) |
| #define HWIO_DDR_PHY_721_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_721_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_722_REGOFF 0xb48 |
| #define HWIO_DDR_PHY_722_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_722_REGOFF) |
| #define HWIO_DDR_PHY_722_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_722_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_723_REGOFF 0xb4c |
| #define HWIO_DDR_PHY_723_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_723_REGOFF) |
| #define HWIO_DDR_PHY_723_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_723_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_724_REGOFF 0xb50 |
| #define HWIO_DDR_PHY_724_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_724_REGOFF) |
| #define HWIO_DDR_PHY_724_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_724_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_725_REGOFF 0xb54 |
| #define HWIO_DDR_PHY_725_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_725_REGOFF) |
| #define HWIO_DDR_PHY_725_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_725_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_726_REGOFF 0xb58 |
| #define HWIO_DDR_PHY_726_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_726_REGOFF) |
| #define HWIO_DDR_PHY_726_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_726_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_727_REGOFF 0xb5c |
| #define HWIO_DDR_PHY_727_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_727_REGOFF) |
| #define HWIO_DDR_PHY_727_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_727_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_728_REGOFF 0xb60 |
| #define HWIO_DDR_PHY_728_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_728_REGOFF) |
| #define HWIO_DDR_PHY_728_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_728_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_729_REGOFF 0xb64 |
| #define HWIO_DDR_PHY_729_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_729_REGOFF) |
| #define HWIO_DDR_PHY_729_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_729_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_730_REGOFF 0xb68 |
| #define HWIO_DDR_PHY_730_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_730_REGOFF) |
| #define HWIO_DDR_PHY_730_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_730_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_731_REGOFF 0xb6c |
| #define HWIO_DDR_PHY_731_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_731_REGOFF) |
| #define HWIO_DDR_PHY_731_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_731_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_732_REGOFF 0xb70 |
| #define HWIO_DDR_PHY_732_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_732_REGOFF) |
| #define HWIO_DDR_PHY_732_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_732_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_733_REGOFF 0xb74 |
| #define HWIO_DDR_PHY_733_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_733_REGOFF) |
| #define HWIO_DDR_PHY_733_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_733_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_734_REGOFF 0xb78 |
| #define HWIO_DDR_PHY_734_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_734_REGOFF) |
| #define HWIO_DDR_PHY_734_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_734_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_735_REGOFF 0xb7c |
| #define HWIO_DDR_PHY_735_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_735_REGOFF) |
| #define HWIO_DDR_PHY_735_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_735_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_736_REGOFF 0xb80 |
| #define HWIO_DDR_PHY_736_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_736_REGOFF) |
| #define HWIO_DDR_PHY_736_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_736_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_737_REGOFF 0xb84 |
| #define HWIO_DDR_PHY_737_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_737_REGOFF) |
| #define HWIO_DDR_PHY_737_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_737_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_738_REGOFF 0xb88 |
| #define HWIO_DDR_PHY_738_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_738_REGOFF) |
| #define HWIO_DDR_PHY_738_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_738_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_739_REGOFF 0xb8c |
| #define HWIO_DDR_PHY_739_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_739_REGOFF) |
| #define HWIO_DDR_PHY_739_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_739_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_740_REGOFF 0xb90 |
| #define HWIO_DDR_PHY_740_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_740_REGOFF) |
| #define HWIO_DDR_PHY_740_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_740_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_741_REGOFF 0xb94 |
| #define HWIO_DDR_PHY_741_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_741_REGOFF) |
| #define HWIO_DDR_PHY_741_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_741_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_742_REGOFF 0xb98 |
| #define HWIO_DDR_PHY_742_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_742_REGOFF) |
| #define HWIO_DDR_PHY_742_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_742_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_743_REGOFF 0xb9c |
| #define HWIO_DDR_PHY_743_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_743_REGOFF) |
| #define HWIO_DDR_PHY_743_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_743_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_744_REGOFF 0xba0 |
| #define HWIO_DDR_PHY_744_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_744_REGOFF) |
| #define HWIO_DDR_PHY_744_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_744_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_745_REGOFF 0xba4 |
| #define HWIO_DDR_PHY_745_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_745_REGOFF) |
| #define HWIO_DDR_PHY_745_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_745_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_746_REGOFF 0xba8 |
| #define HWIO_DDR_PHY_746_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_746_REGOFF) |
| #define HWIO_DDR_PHY_746_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_746_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_747_REGOFF 0xbac |
| #define HWIO_DDR_PHY_747_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_747_REGOFF) |
| #define HWIO_DDR_PHY_747_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_747_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_748_REGOFF 0xbb0 |
| #define HWIO_DDR_PHY_748_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_748_REGOFF) |
| #define HWIO_DDR_PHY_748_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_748_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_749_REGOFF 0xbb4 |
| #define HWIO_DDR_PHY_749_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_749_REGOFF) |
| #define HWIO_DDR_PHY_749_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_749_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_750_REGOFF 0xbb8 |
| #define HWIO_DDR_PHY_750_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_750_REGOFF) |
| #define HWIO_DDR_PHY_750_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_750_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_751_REGOFF 0xbbc |
| #define HWIO_DDR_PHY_751_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_751_REGOFF) |
| #define HWIO_DDR_PHY_751_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_751_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_752_REGOFF 0xbc0 |
| #define HWIO_DDR_PHY_752_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_752_REGOFF) |
| #define HWIO_DDR_PHY_752_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_752_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_753_REGOFF 0xbc4 |
| #define HWIO_DDR_PHY_753_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_753_REGOFF) |
| #define HWIO_DDR_PHY_753_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_753_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_754_REGOFF 0xbc8 |
| #define HWIO_DDR_PHY_754_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_754_REGOFF) |
| #define HWIO_DDR_PHY_754_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_754_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_755_REGOFF 0xbcc |
| #define HWIO_DDR_PHY_755_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_755_REGOFF) |
| #define HWIO_DDR_PHY_755_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_755_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_756_REGOFF 0xbd0 |
| #define HWIO_DDR_PHY_756_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_756_REGOFF) |
| #define HWIO_DDR_PHY_756_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_756_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_757_REGOFF 0xbd4 |
| #define HWIO_DDR_PHY_757_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_757_REGOFF) |
| #define HWIO_DDR_PHY_757_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_757_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_758_REGOFF 0xbd8 |
| #define HWIO_DDR_PHY_758_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_758_REGOFF) |
| #define HWIO_DDR_PHY_758_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_758_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_759_REGOFF 0xbdc |
| #define HWIO_DDR_PHY_759_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_759_REGOFF) |
| #define HWIO_DDR_PHY_759_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_759_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_760_REGOFF 0xbe0 |
| #define HWIO_DDR_PHY_760_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_760_REGOFF) |
| #define HWIO_DDR_PHY_760_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_760_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_761_REGOFF 0xbe4 |
| #define HWIO_DDR_PHY_761_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_761_REGOFF) |
| #define HWIO_DDR_PHY_761_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_761_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_762_REGOFF 0xbe8 |
| #define HWIO_DDR_PHY_762_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_762_REGOFF) |
| #define HWIO_DDR_PHY_762_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_762_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_763_REGOFF 0xbec |
| #define HWIO_DDR_PHY_763_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_763_REGOFF) |
| #define HWIO_DDR_PHY_763_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_763_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_764_REGOFF 0xbf0 |
| #define HWIO_DDR_PHY_764_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_764_REGOFF) |
| #define HWIO_DDR_PHY_764_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_764_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_765_REGOFF 0xbf4 |
| #define HWIO_DDR_PHY_765_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_765_REGOFF) |
| #define HWIO_DDR_PHY_765_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_765_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_766_REGOFF 0xbf8 |
| #define HWIO_DDR_PHY_766_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_766_REGOFF) |
| #define HWIO_DDR_PHY_766_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_766_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_767_REGOFF 0xbfc |
| #define HWIO_DDR_PHY_767_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_767_REGOFF) |
| #define HWIO_DDR_PHY_767_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_767_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_768_REGOFF 0xc00 |
| #define HWIO_DDR_PHY_768_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_768_REGOFF) |
| #define HWIO_DDR_PHY_768_PHY_ADR0_SW_WRADDR_SHIFT_2_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_768_PHY_ADR0_SW_WRADDR_SHIFT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_768_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_768_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_768_PHY_ADR1_SW_WRADDR_SHIFT_2_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_768_PHY_ADR1_SW_WRADDR_SHIFT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_768_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_768_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_768_PHY_ADR2_SW_WRADDR_SHIFT_2_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_768_PHY_ADR2_SW_WRADDR_SHIFT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_768_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_768_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_768_PHY_ADR3_SW_WRADDR_SHIFT_2_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_768_PHY_ADR3_SW_WRADDR_SHIFT_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_768_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_768_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_769_REGOFF 0xc04 |
| #define HWIO_DDR_PHY_769_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_769_REGOFF) |
| #define HWIO_DDR_PHY_769_PHY_ADR4_SW_WRADDR_SHIFT_2_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_769_PHY_ADR4_SW_WRADDR_SHIFT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_769_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_769_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_769_PHY_ADR5_SW_WRADDR_SHIFT_2_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_769_PHY_ADR5_SW_WRADDR_SHIFT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_769_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_769_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_769_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_769_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_769_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_769_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_770_REGOFF 0xc08 |
| #define HWIO_DDR_PHY_770_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_770_REGOFF) |
| #define HWIO_DDR_PHY_770_PHY_ADR_CLK_BYPASS_OVERRIDE_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_770_PHY_ADR_CLK_BYPASS_OVERRIDE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_770_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_770_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_770_SC_PHY_ADR_MANUAL_CLEAR_2_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_770_SC_PHY_ADR_MANUAL_CLEAR_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_770_RESERVED1_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_770_RESERVED1_FLDSHFT (11) |
| #define HWIO_DDR_PHY_770_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_770_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_771_REGOFF 0xc0c |
| #define HWIO_DDR_PHY_771_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_771_REGOFF) |
| #define HWIO_DDR_PHY_771_PHY_ADR_LPBK_RESULT_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_771_PHY_ADR_LPBK_RESULT_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_772_REGOFF 0xc10 |
| #define HWIO_DDR_PHY_772_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_772_REGOFF) |
| #define HWIO_DDR_PHY_772_PHY_ADR_LPBK_ERROR_COUNT_OBS_2_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_772_PHY_ADR_LPBK_ERROR_COUNT_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_772_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_772_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_772_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_772_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_772_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_772_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_773_REGOFF 0xc14 |
| #define HWIO_DDR_PHY_773_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_773_REGOFF) |
| #define HWIO_DDR_PHY_773_PHY_ADR_MASTER_DLY_LOCK_OBS_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_773_PHY_ADR_MASTER_DLY_LOCK_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_773_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_773_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_773_PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_773_PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_773_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_773_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_774_REGOFF 0xc18 |
| #define HWIO_DDR_PHY_774_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_774_REGOFF) |
| #define HWIO_DDR_PHY_774_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_774_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_774_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_774_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_774_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_774_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_774_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_774_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_774_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_774_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_774_SC_PHY_ADR_SNAP_OBS_REGS_2_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_774_SC_PHY_ADR_SNAP_OBS_REGS_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_774_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_774_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_775_REGOFF 0xc1c |
| #define HWIO_DDR_PHY_775_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_775_REGOFF) |
| #define HWIO_DDR_PHY_775_PHY_ADR_TSEL_ENABLE_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_775_PHY_ADR_TSEL_ENABLE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_775_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_775_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_775_PHY_ADR_LPBK_CONTROL_2_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_775_PHY_ADR_LPBK_CONTROL_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_775_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_775_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_775_PHY_ADR_PRBS_PATTERN_START_2_FLDMASK (0x7f0000) |
| #define HWIO_DDR_PHY_775_PHY_ADR_PRBS_PATTERN_START_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_775_RESERVED2_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_775_RESERVED2_FLDSHFT (23) |
| #define HWIO_DDR_PHY_775_PHY_ADR_PRBS_PATTERN_MASK_2_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_775_PHY_ADR_PRBS_PATTERN_MASK_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_775_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_775_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_776_REGOFF 0xc20 |
| #define HWIO_DDR_PHY_776_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_776_REGOFF) |
| #define HWIO_DDR_PHY_776_PHY_ADR_PWR_RDC_DISABLE_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_776_PHY_ADR_PWR_RDC_DISABLE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_776_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_776_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_776_PHY_ADR_TYPE_2_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_776_PHY_ADR_TYPE_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_776_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_776_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_776_PHY_ADR_WRADDR_SHIFT_OBS_2_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_776_PHY_ADR_WRADDR_SHIFT_OBS_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_776_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_776_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_776_PHY_ADR_IE_MODE_2_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_776_PHY_ADR_IE_MODE_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_776_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_776_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_777_REGOFF 0xc24 |
| #define HWIO_DDR_PHY_777_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_777_REGOFF) |
| #define HWIO_DDR_PHY_777_PHY_ADR_DDL_MODE_2_FLDMASK (0x7fff) |
| #define HWIO_DDR_PHY_777_PHY_ADR_DDL_MODE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_777_RESERVED_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_777_RESERVED_FLDSHFT (15) |
| #define HWIO_DDR_PHY_777_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_777_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_778_REGOFF 0xc28 |
| #define HWIO_DDR_PHY_778_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_778_REGOFF) |
| #define HWIO_DDR_PHY_778_PHY_ADR_DDL_TEST_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_778_PHY_ADR_DDL_TEST_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_779_REGOFF 0xc2c |
| #define HWIO_DDR_PHY_779_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_779_REGOFF) |
| #define HWIO_DDR_PHY_779_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_779_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_780_REGOFF 0xc30 |
| #define HWIO_DDR_PHY_780_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_780_REGOFF) |
| #define HWIO_DDR_PHY_780_PHY_ADR_CALVL_START_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_780_PHY_ADR_CALVL_START_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_780_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_780_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_780_PHY_ADR_CALVL_COARSE_DLY_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_780_PHY_ADR_CALVL_COARSE_DLY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_780_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_780_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_781_REGOFF 0xc34 |
| #define HWIO_DDR_PHY_781_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_781_REGOFF) |
| #define HWIO_DDR_PHY_781_PHY_ADR_CALVL_QTR_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_781_PHY_ADR_CALVL_QTR_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_781_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_781_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_781_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_781_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_782_REGOFF 0xc38 |
| #define HWIO_DDR_PHY_782_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_782_REGOFF) |
| #define HWIO_DDR_PHY_782_PHY_ADR_CALVL_SWIZZLE0_2_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_782_PHY_ADR_CALVL_SWIZZLE0_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_782_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_782_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_783_REGOFF 0xc3c |
| #define HWIO_DDR_PHY_783_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_783_REGOFF) |
| #define HWIO_DDR_PHY_783_PHY_ADR_CALVL_SWIZZLE1_2_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_783_PHY_ADR_CALVL_SWIZZLE1_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_783_PHY_ADR_CALVL_RANK_CTRL_2_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_783_PHY_ADR_CALVL_RANK_CTRL_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_783_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_783_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_784_REGOFF 0xc40 |
| #define HWIO_DDR_PHY_784_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_784_REGOFF) |
| #define HWIO_DDR_PHY_784_PHY_ADR_CALVL_NUM_PATTERNS_2_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_784_PHY_ADR_CALVL_NUM_PATTERNS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_784_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_784_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_784_PHY_ADR_CALVL_CAPTURE_CNT_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_784_PHY_ADR_CALVL_CAPTURE_CNT_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_784_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_784_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_784_PHY_ADR_CALVL_RESP_WAIT_CNT_2_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_784_PHY_ADR_CALVL_RESP_WAIT_CNT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_784_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_784_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_784_PHY_ADR_CALVL_DEBUG_MODE_2_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_784_PHY_ADR_CALVL_DEBUG_MODE_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_784_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_784_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_785_REGOFF 0xc44 |
| #define HWIO_DDR_PHY_785_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_785_REGOFF) |
| #define HWIO_DDR_PHY_785_SC_PHY_ADR_CALVL_DEBUG_CONT_2_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_785_SC_PHY_ADR_CALVL_DEBUG_CONT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_785_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_785_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_785_SC_PHY_ADR_CALVL_ERROR_CLR_2_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_785_SC_PHY_ADR_CALVL_ERROR_CLR_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_785_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_785_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_785_PHY_ADR_CALVL_OBS_SELECT_2_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_785_PHY_ADR_CALVL_OBS_SELECT_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_785_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_785_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_785_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_785_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_786_REGOFF 0xc48 |
| #define HWIO_DDR_PHY_786_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_786_REGOFF) |
| #define HWIO_DDR_PHY_786_PHY_ADR_CALVL_OBS0_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_786_PHY_ADR_CALVL_OBS0_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_787_REGOFF 0xc4c |
| #define HWIO_DDR_PHY_787_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_787_REGOFF) |
| #define HWIO_DDR_PHY_787_PHY_ADR_CALVL_OBS1_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_787_PHY_ADR_CALVL_OBS1_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_788_REGOFF 0xc50 |
| #define HWIO_DDR_PHY_788_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_788_REGOFF) |
| #define HWIO_DDR_PHY_788_PHY_ADR_CALVL_FG_0_2_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_788_PHY_ADR_CALVL_FG_0_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_788_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_788_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_788_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_788_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_789_REGOFF 0xc54 |
| #define HWIO_DDR_PHY_789_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_789_REGOFF) |
| #define HWIO_DDR_PHY_789_PHY_ADR_CALVL_BG_0_2_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_789_PHY_ADR_CALVL_BG_0_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_789_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_789_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_789_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_789_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_790_REGOFF 0xc58 |
| #define HWIO_DDR_PHY_790_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_790_REGOFF) |
| #define HWIO_DDR_PHY_790_PHY_ADR_CALVL_FG_1_2_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_790_PHY_ADR_CALVL_FG_1_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_790_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_790_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_790_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_790_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_791_REGOFF 0xc5c |
| #define HWIO_DDR_PHY_791_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_791_REGOFF) |
| #define HWIO_DDR_PHY_791_PHY_ADR_CALVL_BG_1_2_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_791_PHY_ADR_CALVL_BG_1_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_791_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_791_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_791_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_791_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_792_REGOFF 0xc60 |
| #define HWIO_DDR_PHY_792_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_792_REGOFF) |
| #define HWIO_DDR_PHY_792_PHY_ADR_CALVL_FG_2_2_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_792_PHY_ADR_CALVL_FG_2_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_792_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_792_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_792_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_792_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_793_REGOFF 0xc64 |
| #define HWIO_DDR_PHY_793_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_793_REGOFF) |
| #define HWIO_DDR_PHY_793_PHY_ADR_CALVL_BG_2_2_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_793_PHY_ADR_CALVL_BG_2_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_793_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_793_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_793_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_793_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_794_REGOFF 0xc68 |
| #define HWIO_DDR_PHY_794_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_794_REGOFF) |
| #define HWIO_DDR_PHY_794_PHY_ADR_CALVL_FG_3_2_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_794_PHY_ADR_CALVL_FG_3_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_794_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_794_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_794_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_794_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_795_REGOFF 0xc6c |
| #define HWIO_DDR_PHY_795_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_795_REGOFF) |
| #define HWIO_DDR_PHY_795_PHY_ADR_CALVL_BG_3_2_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_795_PHY_ADR_CALVL_BG_3_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_795_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_795_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_795_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_795_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_796_REGOFF 0xc70 |
| #define HWIO_DDR_PHY_796_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_796_REGOFF) |
| #define HWIO_DDR_PHY_796_PHY_ADR_ADDR_SEL_2_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_796_PHY_ADR_ADDR_SEL_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_796_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_796_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_797_REGOFF 0xc74 |
| #define HWIO_DDR_PHY_797_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_797_REGOFF) |
| #define HWIO_DDR_PHY_797_PHY_ADR_LP4_BOOT_SLV_DELAY_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_797_PHY_ADR_LP4_BOOT_SLV_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_797_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_797_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_797_PHY_ADR_BIT_MASK_2_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_797_PHY_ADR_BIT_MASK_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_797_RESERVED1_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_797_RESERVED1_FLDSHFT (22) |
| #define HWIO_DDR_PHY_797_PHY_ADR_SEG_MASK_2_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_797_PHY_ADR_SEG_MASK_2_FLDSHFT (24) |
| #define HWIO_DDR_PHY_797_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_797_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_798_REGOFF 0xc78 |
| #define HWIO_DDR_PHY_798_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_798_REGOFF) |
| #define HWIO_DDR_PHY_798_PHY_ADR_CALVL_TRAIN_MASK_2_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_798_PHY_ADR_CALVL_TRAIN_MASK_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_798_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_798_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_798_PHY_ADR_SW_TXIO_CTRL_2_FLDMASK (0x3f00) |
| #define HWIO_DDR_PHY_798_PHY_ADR_SW_TXIO_CTRL_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_798_RESERVED1_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_798_RESERVED1_FLDSHFT (14) |
| #define HWIO_DDR_PHY_798_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_798_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_799_REGOFF 0xc7c |
| #define HWIO_DDR_PHY_799_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_799_REGOFF) |
| #define HWIO_DDR_PHY_799_PHY_ADR_TSEL_SELECT_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_799_PHY_ADR_TSEL_SELECT_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_799_PHY_ADR0_CLK_WR_SLAVE_DELAY_2_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_799_PHY_ADR0_CLK_WR_SLAVE_DELAY_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_799_RESERVED_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_799_RESERVED_FLDSHFT (19) |
| #define HWIO_DDR_PHY_799_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_799_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_800_REGOFF 0xc80 |
| #define HWIO_DDR_PHY_800_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_800_REGOFF) |
| #define HWIO_DDR_PHY_800_PHY_ADR1_CLK_WR_SLAVE_DELAY_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_800_PHY_ADR1_CLK_WR_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_800_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_800_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_800_PHY_ADR2_CLK_WR_SLAVE_DELAY_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_800_PHY_ADR2_CLK_WR_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_800_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_800_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_801_REGOFF 0xc84 |
| #define HWIO_DDR_PHY_801_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_801_REGOFF) |
| #define HWIO_DDR_PHY_801_PHY_ADR3_CLK_WR_SLAVE_DELAY_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_801_PHY_ADR3_CLK_WR_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_801_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_801_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_801_PHY_ADR4_CLK_WR_SLAVE_DELAY_2_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_801_PHY_ADR4_CLK_WR_SLAVE_DELAY_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_801_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_801_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_802_REGOFF 0xc88 |
| #define HWIO_DDR_PHY_802_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_802_REGOFF) |
| #define HWIO_DDR_PHY_802_PHY_ADR5_CLK_WR_SLAVE_DELAY_2_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_802_PHY_ADR5_CLK_WR_SLAVE_DELAY_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_802_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_802_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_802_PHY_ADR_SW_MASTER_MODE_2_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_802_PHY_ADR_SW_MASTER_MODE_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_802_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_802_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_802_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_802_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_803_REGOFF 0xc8c |
| #define HWIO_DDR_PHY_803_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_803_REGOFF) |
| #define HWIO_DDR_PHY_803_PHY_ADR_MASTER_DELAY_START_2_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_803_PHY_ADR_MASTER_DELAY_START_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_803_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_803_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_803_PHY_ADR_MASTER_DELAY_STEP_2_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_803_PHY_ADR_MASTER_DELAY_STEP_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_803_RESERVED1_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_803_RESERVED1_FLDSHFT (22) |
| #define HWIO_DDR_PHY_803_PHY_ADR_MASTER_DELAY_WAIT_2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_803_PHY_ADR_MASTER_DELAY_WAIT_2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_804_REGOFF 0xc90 |
| #define HWIO_DDR_PHY_804_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_804_REGOFF) |
| #define HWIO_DDR_PHY_804_PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_804_PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_804_PHY_ADR_CALVL_DLY_STEP_2_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_804_PHY_ADR_CALVL_DLY_STEP_2_FLDSHFT (8) |
| #define HWIO_DDR_PHY_804_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_804_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_804_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_804_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_805_REGOFF 0xc94 |
| #define HWIO_DDR_PHY_805_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_805_REGOFF) |
| #define HWIO_DDR_PHY_805_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_805_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_806_REGOFF 0xc98 |
| #define HWIO_DDR_PHY_806_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_806_REGOFF) |
| #define HWIO_DDR_PHY_806_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_806_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_807_REGOFF 0xc9c |
| #define HWIO_DDR_PHY_807_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_807_REGOFF) |
| #define HWIO_DDR_PHY_807_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_807_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_808_REGOFF 0xca0 |
| #define HWIO_DDR_PHY_808_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_808_REGOFF) |
| #define HWIO_DDR_PHY_808_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_808_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_809_REGOFF 0xca4 |
| #define HWIO_DDR_PHY_809_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_809_REGOFF) |
| #define HWIO_DDR_PHY_809_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_809_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_810_REGOFF 0xca8 |
| #define HWIO_DDR_PHY_810_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_810_REGOFF) |
| #define HWIO_DDR_PHY_810_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_810_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_811_REGOFF 0xcac |
| #define HWIO_DDR_PHY_811_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_811_REGOFF) |
| #define HWIO_DDR_PHY_811_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_811_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_812_REGOFF 0xcb0 |
| #define HWIO_DDR_PHY_812_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_812_REGOFF) |
| #define HWIO_DDR_PHY_812_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_812_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_813_REGOFF 0xcb4 |
| #define HWIO_DDR_PHY_813_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_813_REGOFF) |
| #define HWIO_DDR_PHY_813_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_813_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_814_REGOFF 0xcb8 |
| #define HWIO_DDR_PHY_814_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_814_REGOFF) |
| #define HWIO_DDR_PHY_814_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_814_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_815_REGOFF 0xcbc |
| #define HWIO_DDR_PHY_815_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_815_REGOFF) |
| #define HWIO_DDR_PHY_815_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_815_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_816_REGOFF 0xcc0 |
| #define HWIO_DDR_PHY_816_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_816_REGOFF) |
| #define HWIO_DDR_PHY_816_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_816_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_817_REGOFF 0xcc4 |
| #define HWIO_DDR_PHY_817_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_817_REGOFF) |
| #define HWIO_DDR_PHY_817_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_817_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_818_REGOFF 0xcc8 |
| #define HWIO_DDR_PHY_818_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_818_REGOFF) |
| #define HWIO_DDR_PHY_818_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_818_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_819_REGOFF 0xccc |
| #define HWIO_DDR_PHY_819_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_819_REGOFF) |
| #define HWIO_DDR_PHY_819_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_819_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_820_REGOFF 0xcd0 |
| #define HWIO_DDR_PHY_820_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_820_REGOFF) |
| #define HWIO_DDR_PHY_820_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_820_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_821_REGOFF 0xcd4 |
| #define HWIO_DDR_PHY_821_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_821_REGOFF) |
| #define HWIO_DDR_PHY_821_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_821_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_822_REGOFF 0xcd8 |
| #define HWIO_DDR_PHY_822_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_822_REGOFF) |
| #define HWIO_DDR_PHY_822_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_822_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_823_REGOFF 0xcdc |
| #define HWIO_DDR_PHY_823_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_823_REGOFF) |
| #define HWIO_DDR_PHY_823_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_823_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_824_REGOFF 0xce0 |
| #define HWIO_DDR_PHY_824_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_824_REGOFF) |
| #define HWIO_DDR_PHY_824_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_824_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_825_REGOFF 0xce4 |
| #define HWIO_DDR_PHY_825_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_825_REGOFF) |
| #define HWIO_DDR_PHY_825_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_825_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_826_REGOFF 0xce8 |
| #define HWIO_DDR_PHY_826_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_826_REGOFF) |
| #define HWIO_DDR_PHY_826_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_826_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_827_REGOFF 0xcec |
| #define HWIO_DDR_PHY_827_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_827_REGOFF) |
| #define HWIO_DDR_PHY_827_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_827_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_828_REGOFF 0xcf0 |
| #define HWIO_DDR_PHY_828_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_828_REGOFF) |
| #define HWIO_DDR_PHY_828_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_828_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_829_REGOFF 0xcf4 |
| #define HWIO_DDR_PHY_829_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_829_REGOFF) |
| #define HWIO_DDR_PHY_829_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_829_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_830_REGOFF 0xcf8 |
| #define HWIO_DDR_PHY_830_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_830_REGOFF) |
| #define HWIO_DDR_PHY_830_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_830_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_831_REGOFF 0xcfc |
| #define HWIO_DDR_PHY_831_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_831_REGOFF) |
| #define HWIO_DDR_PHY_831_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_831_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_832_REGOFF 0xd00 |
| #define HWIO_DDR_PHY_832_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_832_REGOFF) |
| #define HWIO_DDR_PHY_832_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_832_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_833_REGOFF 0xd04 |
| #define HWIO_DDR_PHY_833_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_833_REGOFF) |
| #define HWIO_DDR_PHY_833_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_833_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_834_REGOFF 0xd08 |
| #define HWIO_DDR_PHY_834_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_834_REGOFF) |
| #define HWIO_DDR_PHY_834_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_834_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_835_REGOFF 0xd0c |
| #define HWIO_DDR_PHY_835_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_835_REGOFF) |
| #define HWIO_DDR_PHY_835_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_835_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_836_REGOFF 0xd10 |
| #define HWIO_DDR_PHY_836_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_836_REGOFF) |
| #define HWIO_DDR_PHY_836_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_836_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_837_REGOFF 0xd14 |
| #define HWIO_DDR_PHY_837_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_837_REGOFF) |
| #define HWIO_DDR_PHY_837_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_837_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_838_REGOFF 0xd18 |
| #define HWIO_DDR_PHY_838_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_838_REGOFF) |
| #define HWIO_DDR_PHY_838_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_838_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_839_REGOFF 0xd1c |
| #define HWIO_DDR_PHY_839_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_839_REGOFF) |
| #define HWIO_DDR_PHY_839_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_839_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_840_REGOFF 0xd20 |
| #define HWIO_DDR_PHY_840_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_840_REGOFF) |
| #define HWIO_DDR_PHY_840_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_840_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_841_REGOFF 0xd24 |
| #define HWIO_DDR_PHY_841_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_841_REGOFF) |
| #define HWIO_DDR_PHY_841_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_841_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_842_REGOFF 0xd28 |
| #define HWIO_DDR_PHY_842_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_842_REGOFF) |
| #define HWIO_DDR_PHY_842_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_842_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_843_REGOFF 0xd2c |
| #define HWIO_DDR_PHY_843_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_843_REGOFF) |
| #define HWIO_DDR_PHY_843_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_843_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_844_REGOFF 0xd30 |
| #define HWIO_DDR_PHY_844_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_844_REGOFF) |
| #define HWIO_DDR_PHY_844_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_844_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_845_REGOFF 0xd34 |
| #define HWIO_DDR_PHY_845_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_845_REGOFF) |
| #define HWIO_DDR_PHY_845_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_845_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_846_REGOFF 0xd38 |
| #define HWIO_DDR_PHY_846_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_846_REGOFF) |
| #define HWIO_DDR_PHY_846_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_846_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_847_REGOFF 0xd3c |
| #define HWIO_DDR_PHY_847_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_847_REGOFF) |
| #define HWIO_DDR_PHY_847_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_847_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_848_REGOFF 0xd40 |
| #define HWIO_DDR_PHY_848_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_848_REGOFF) |
| #define HWIO_DDR_PHY_848_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_848_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_849_REGOFF 0xd44 |
| #define HWIO_DDR_PHY_849_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_849_REGOFF) |
| #define HWIO_DDR_PHY_849_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_849_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_850_REGOFF 0xd48 |
| #define HWIO_DDR_PHY_850_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_850_REGOFF) |
| #define HWIO_DDR_PHY_850_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_850_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_851_REGOFF 0xd4c |
| #define HWIO_DDR_PHY_851_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_851_REGOFF) |
| #define HWIO_DDR_PHY_851_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_851_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_852_REGOFF 0xd50 |
| #define HWIO_DDR_PHY_852_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_852_REGOFF) |
| #define HWIO_DDR_PHY_852_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_852_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_853_REGOFF 0xd54 |
| #define HWIO_DDR_PHY_853_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_853_REGOFF) |
| #define HWIO_DDR_PHY_853_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_853_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_854_REGOFF 0xd58 |
| #define HWIO_DDR_PHY_854_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_854_REGOFF) |
| #define HWIO_DDR_PHY_854_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_854_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_855_REGOFF 0xd5c |
| #define HWIO_DDR_PHY_855_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_855_REGOFF) |
| #define HWIO_DDR_PHY_855_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_855_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_856_REGOFF 0xd60 |
| #define HWIO_DDR_PHY_856_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_856_REGOFF) |
| #define HWIO_DDR_PHY_856_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_856_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_857_REGOFF 0xd64 |
| #define HWIO_DDR_PHY_857_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_857_REGOFF) |
| #define HWIO_DDR_PHY_857_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_857_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_858_REGOFF 0xd68 |
| #define HWIO_DDR_PHY_858_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_858_REGOFF) |
| #define HWIO_DDR_PHY_858_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_858_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_859_REGOFF 0xd6c |
| #define HWIO_DDR_PHY_859_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_859_REGOFF) |
| #define HWIO_DDR_PHY_859_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_859_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_860_REGOFF 0xd70 |
| #define HWIO_DDR_PHY_860_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_860_REGOFF) |
| #define HWIO_DDR_PHY_860_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_860_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_861_REGOFF 0xd74 |
| #define HWIO_DDR_PHY_861_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_861_REGOFF) |
| #define HWIO_DDR_PHY_861_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_861_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_862_REGOFF 0xd78 |
| #define HWIO_DDR_PHY_862_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_862_REGOFF) |
| #define HWIO_DDR_PHY_862_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_862_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_863_REGOFF 0xd7c |
| #define HWIO_DDR_PHY_863_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_863_REGOFF) |
| #define HWIO_DDR_PHY_863_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_863_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_864_REGOFF 0xd80 |
| #define HWIO_DDR_PHY_864_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_864_REGOFF) |
| #define HWIO_DDR_PHY_864_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_864_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_865_REGOFF 0xd84 |
| #define HWIO_DDR_PHY_865_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_865_REGOFF) |
| #define HWIO_DDR_PHY_865_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_865_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_866_REGOFF 0xd88 |
| #define HWIO_DDR_PHY_866_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_866_REGOFF) |
| #define HWIO_DDR_PHY_866_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_866_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_867_REGOFF 0xd8c |
| #define HWIO_DDR_PHY_867_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_867_REGOFF) |
| #define HWIO_DDR_PHY_867_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_867_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_868_REGOFF 0xd90 |
| #define HWIO_DDR_PHY_868_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_868_REGOFF) |
| #define HWIO_DDR_PHY_868_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_868_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_869_REGOFF 0xd94 |
| #define HWIO_DDR_PHY_869_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_869_REGOFF) |
| #define HWIO_DDR_PHY_869_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_869_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_870_REGOFF 0xd98 |
| #define HWIO_DDR_PHY_870_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_870_REGOFF) |
| #define HWIO_DDR_PHY_870_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_870_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_871_REGOFF 0xd9c |
| #define HWIO_DDR_PHY_871_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_871_REGOFF) |
| #define HWIO_DDR_PHY_871_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_871_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_872_REGOFF 0xda0 |
| #define HWIO_DDR_PHY_872_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_872_REGOFF) |
| #define HWIO_DDR_PHY_872_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_872_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_873_REGOFF 0xda4 |
| #define HWIO_DDR_PHY_873_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_873_REGOFF) |
| #define HWIO_DDR_PHY_873_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_873_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_874_REGOFF 0xda8 |
| #define HWIO_DDR_PHY_874_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_874_REGOFF) |
| #define HWIO_DDR_PHY_874_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_874_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_875_REGOFF 0xdac |
| #define HWIO_DDR_PHY_875_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_875_REGOFF) |
| #define HWIO_DDR_PHY_875_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_875_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_876_REGOFF 0xdb0 |
| #define HWIO_DDR_PHY_876_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_876_REGOFF) |
| #define HWIO_DDR_PHY_876_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_876_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_877_REGOFF 0xdb4 |
| #define HWIO_DDR_PHY_877_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_877_REGOFF) |
| #define HWIO_DDR_PHY_877_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_877_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_878_REGOFF 0xdb8 |
| #define HWIO_DDR_PHY_878_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_878_REGOFF) |
| #define HWIO_DDR_PHY_878_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_878_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_879_REGOFF 0xdbc |
| #define HWIO_DDR_PHY_879_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_879_REGOFF) |
| #define HWIO_DDR_PHY_879_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_879_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_880_REGOFF 0xdc0 |
| #define HWIO_DDR_PHY_880_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_880_REGOFF) |
| #define HWIO_DDR_PHY_880_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_880_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_881_REGOFF 0xdc4 |
| #define HWIO_DDR_PHY_881_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_881_REGOFF) |
| #define HWIO_DDR_PHY_881_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_881_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_882_REGOFF 0xdc8 |
| #define HWIO_DDR_PHY_882_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_882_REGOFF) |
| #define HWIO_DDR_PHY_882_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_882_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_883_REGOFF 0xdcc |
| #define HWIO_DDR_PHY_883_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_883_REGOFF) |
| #define HWIO_DDR_PHY_883_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_883_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_884_REGOFF 0xdd0 |
| #define HWIO_DDR_PHY_884_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_884_REGOFF) |
| #define HWIO_DDR_PHY_884_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_884_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_885_REGOFF 0xdd4 |
| #define HWIO_DDR_PHY_885_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_885_REGOFF) |
| #define HWIO_DDR_PHY_885_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_885_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_886_REGOFF 0xdd8 |
| #define HWIO_DDR_PHY_886_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_886_REGOFF) |
| #define HWIO_DDR_PHY_886_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_886_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_887_REGOFF 0xddc |
| #define HWIO_DDR_PHY_887_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_887_REGOFF) |
| #define HWIO_DDR_PHY_887_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_887_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_888_REGOFF 0xde0 |
| #define HWIO_DDR_PHY_888_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_888_REGOFF) |
| #define HWIO_DDR_PHY_888_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_888_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_889_REGOFF 0xde4 |
| #define HWIO_DDR_PHY_889_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_889_REGOFF) |
| #define HWIO_DDR_PHY_889_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_889_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_890_REGOFF 0xde8 |
| #define HWIO_DDR_PHY_890_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_890_REGOFF) |
| #define HWIO_DDR_PHY_890_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_890_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_891_REGOFF 0xdec |
| #define HWIO_DDR_PHY_891_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_891_REGOFF) |
| #define HWIO_DDR_PHY_891_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_891_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_892_REGOFF 0xdf0 |
| #define HWIO_DDR_PHY_892_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_892_REGOFF) |
| #define HWIO_DDR_PHY_892_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_892_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_893_REGOFF 0xdf4 |
| #define HWIO_DDR_PHY_893_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_893_REGOFF) |
| #define HWIO_DDR_PHY_893_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_893_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_894_REGOFF 0xdf8 |
| #define HWIO_DDR_PHY_894_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_894_REGOFF) |
| #define HWIO_DDR_PHY_894_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_894_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_895_REGOFF 0xdfc |
| #define HWIO_DDR_PHY_895_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_895_REGOFF) |
| #define HWIO_DDR_PHY_895_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_895_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_896_REGOFF 0xe00 |
| #define HWIO_DDR_PHY_896_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_896_REGOFF) |
| #define HWIO_DDR_PHY_896_PHY_ADR0_SW_WRADDR_SHIFT_3_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_896_PHY_ADR0_SW_WRADDR_SHIFT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_896_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_896_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_896_PHY_ADR1_SW_WRADDR_SHIFT_3_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_896_PHY_ADR1_SW_WRADDR_SHIFT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_896_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_896_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_896_PHY_ADR2_SW_WRADDR_SHIFT_3_FLDMASK (0x1f0000) |
| #define HWIO_DDR_PHY_896_PHY_ADR2_SW_WRADDR_SHIFT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_896_RESERVED2_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_896_RESERVED2_FLDSHFT (21) |
| #define HWIO_DDR_PHY_896_PHY_ADR3_SW_WRADDR_SHIFT_3_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_896_PHY_ADR3_SW_WRADDR_SHIFT_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_896_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_896_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_897_REGOFF 0xe04 |
| #define HWIO_DDR_PHY_897_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_897_REGOFF) |
| #define HWIO_DDR_PHY_897_PHY_ADR4_SW_WRADDR_SHIFT_3_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_897_PHY_ADR4_SW_WRADDR_SHIFT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_897_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_897_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_897_PHY_ADR5_SW_WRADDR_SHIFT_3_FLDMASK (0x1f00) |
| #define HWIO_DDR_PHY_897_PHY_ADR5_SW_WRADDR_SHIFT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_897_RESERVED1_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_897_RESERVED1_FLDSHFT (13) |
| #define HWIO_DDR_PHY_897_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_897_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_897_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_897_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_898_REGOFF 0xe08 |
| #define HWIO_DDR_PHY_898_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_898_REGOFF) |
| #define HWIO_DDR_PHY_898_PHY_ADR_CLK_BYPASS_OVERRIDE_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_898_PHY_ADR_CLK_BYPASS_OVERRIDE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_898_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_898_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_898_SC_PHY_ADR_MANUAL_CLEAR_3_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_898_SC_PHY_ADR_MANUAL_CLEAR_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_898_RESERVED1_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_898_RESERVED1_FLDSHFT (11) |
| #define HWIO_DDR_PHY_898_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_898_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_899_REGOFF 0xe0c |
| #define HWIO_DDR_PHY_899_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_899_REGOFF) |
| #define HWIO_DDR_PHY_899_PHY_ADR_LPBK_RESULT_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_899_PHY_ADR_LPBK_RESULT_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_900_REGOFF 0xe10 |
| #define HWIO_DDR_PHY_900_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_900_REGOFF) |
| #define HWIO_DDR_PHY_900_PHY_ADR_LPBK_ERROR_COUNT_OBS_3_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_900_PHY_ADR_LPBK_ERROR_COUNT_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_900_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_3_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_900_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_900_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_900_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_900_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_900_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_901_REGOFF 0xe14 |
| #define HWIO_DDR_PHY_901_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_901_REGOFF) |
| #define HWIO_DDR_PHY_901_PHY_ADR_MASTER_DLY_LOCK_OBS_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_901_PHY_ADR_MASTER_DLY_LOCK_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_901_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_901_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_901_PHY_ADR_BASE_SLV_DLY_ENC_OBS_3_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_901_PHY_ADR_BASE_SLV_DLY_ENC_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_901_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_901_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_902_REGOFF 0xe18 |
| #define HWIO_DDR_PHY_902_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_902_REGOFF) |
| #define HWIO_DDR_PHY_902_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_902_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_902_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_3_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_902_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_902_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_902_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_902_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_3_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_902_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_902_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_902_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_902_SC_PHY_ADR_SNAP_OBS_REGS_3_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_902_SC_PHY_ADR_SNAP_OBS_REGS_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_902_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_902_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_903_REGOFF 0xe1c |
| #define HWIO_DDR_PHY_903_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_903_REGOFF) |
| #define HWIO_DDR_PHY_903_PHY_ADR_TSEL_ENABLE_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_903_PHY_ADR_TSEL_ENABLE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_903_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_903_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_903_PHY_ADR_LPBK_CONTROL_3_FLDMASK (0x7f00) |
| #define HWIO_DDR_PHY_903_PHY_ADR_LPBK_CONTROL_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_903_RESERVED1_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_903_RESERVED1_FLDSHFT (15) |
| #define HWIO_DDR_PHY_903_PHY_ADR_PRBS_PATTERN_START_3_FLDMASK (0x7f0000) |
| #define HWIO_DDR_PHY_903_PHY_ADR_PRBS_PATTERN_START_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_903_RESERVED2_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_903_RESERVED2_FLDSHFT (23) |
| #define HWIO_DDR_PHY_903_PHY_ADR_PRBS_PATTERN_MASK_3_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_903_PHY_ADR_PRBS_PATTERN_MASK_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_903_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_903_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_904_REGOFF 0xe20 |
| #define HWIO_DDR_PHY_904_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_904_REGOFF) |
| #define HWIO_DDR_PHY_904_PHY_ADR_PWR_RDC_DISABLE_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_904_PHY_ADR_PWR_RDC_DISABLE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_904_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_904_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_904_PHY_ADR_TYPE_3_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_904_PHY_ADR_TYPE_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_904_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_904_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_904_PHY_ADR_WRADDR_SHIFT_OBS_3_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_904_PHY_ADR_WRADDR_SHIFT_OBS_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_904_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_904_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_904_PHY_ADR_IE_MODE_3_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_904_PHY_ADR_IE_MODE_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_904_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_904_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_905_REGOFF 0xe24 |
| #define HWIO_DDR_PHY_905_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_905_REGOFF) |
| #define HWIO_DDR_PHY_905_PHY_ADR_DDL_MODE_3_FLDMASK (0x7fff) |
| #define HWIO_DDR_PHY_905_PHY_ADR_DDL_MODE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_905_RESERVED_FLDMASK (0x8000) |
| #define HWIO_DDR_PHY_905_RESERVED_FLDSHFT (15) |
| #define HWIO_DDR_PHY_905_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_905_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_906_REGOFF 0xe28 |
| #define HWIO_DDR_PHY_906_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_906_REGOFF) |
| #define HWIO_DDR_PHY_906_PHY_ADR_DDL_TEST_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_906_PHY_ADR_DDL_TEST_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_907_REGOFF 0xe2c |
| #define HWIO_DDR_PHY_907_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_907_REGOFF) |
| #define HWIO_DDR_PHY_907_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_907_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_908_REGOFF 0xe30 |
| #define HWIO_DDR_PHY_908_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_908_REGOFF) |
| #define HWIO_DDR_PHY_908_PHY_ADR_CALVL_START_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_908_PHY_ADR_CALVL_START_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_908_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_908_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_908_PHY_ADR_CALVL_COARSE_DLY_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_908_PHY_ADR_CALVL_COARSE_DLY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_908_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_908_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_909_REGOFF 0xe34 |
| #define HWIO_DDR_PHY_909_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_909_REGOFF) |
| #define HWIO_DDR_PHY_909_PHY_ADR_CALVL_QTR_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_909_PHY_ADR_CALVL_QTR_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_909_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_909_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_909_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_909_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_910_REGOFF 0xe38 |
| #define HWIO_DDR_PHY_910_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_910_REGOFF) |
| #define HWIO_DDR_PHY_910_PHY_ADR_CALVL_SWIZZLE0_3_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_910_PHY_ADR_CALVL_SWIZZLE0_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_910_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_910_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_911_REGOFF 0xe3c |
| #define HWIO_DDR_PHY_911_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_911_REGOFF) |
| #define HWIO_DDR_PHY_911_PHY_ADR_CALVL_SWIZZLE1_3_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_911_PHY_ADR_CALVL_SWIZZLE1_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_911_PHY_ADR_CALVL_RANK_CTRL_3_FLDMASK (0x3000000) |
| #define HWIO_DDR_PHY_911_PHY_ADR_CALVL_RANK_CTRL_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_911_RESERVED_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_911_RESERVED_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_912_REGOFF 0xe40 |
| #define HWIO_DDR_PHY_912_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_912_REGOFF) |
| #define HWIO_DDR_PHY_912_PHY_ADR_CALVL_NUM_PATTERNS_3_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_912_PHY_ADR_CALVL_NUM_PATTERNS_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_912_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_912_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_912_PHY_ADR_CALVL_CAPTURE_CNT_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_912_PHY_ADR_CALVL_CAPTURE_CNT_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_912_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_912_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_912_PHY_ADR_CALVL_RESP_WAIT_CNT_3_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_912_PHY_ADR_CALVL_RESP_WAIT_CNT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_912_RESERVED2_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_912_RESERVED2_FLDSHFT (20) |
| #define HWIO_DDR_PHY_912_PHY_ADR_CALVL_DEBUG_MODE_3_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_912_PHY_ADR_CALVL_DEBUG_MODE_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_912_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_912_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_913_REGOFF 0xe44 |
| #define HWIO_DDR_PHY_913_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_913_REGOFF) |
| #define HWIO_DDR_PHY_913_SC_PHY_ADR_CALVL_DEBUG_CONT_3_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_913_SC_PHY_ADR_CALVL_DEBUG_CONT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_913_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_913_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_913_SC_PHY_ADR_CALVL_ERROR_CLR_3_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_913_SC_PHY_ADR_CALVL_ERROR_CLR_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_913_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_913_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_913_PHY_ADR_CALVL_OBS_SELECT_3_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_913_PHY_ADR_CALVL_OBS_SELECT_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_913_RESERVED2_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_913_RESERVED2_FLDSHFT (19) |
| #define HWIO_DDR_PHY_913_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_913_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_914_REGOFF 0xe48 |
| #define HWIO_DDR_PHY_914_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_914_REGOFF) |
| #define HWIO_DDR_PHY_914_PHY_ADR_CALVL_OBS0_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_914_PHY_ADR_CALVL_OBS0_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_915_REGOFF 0xe4c |
| #define HWIO_DDR_PHY_915_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_915_REGOFF) |
| #define HWIO_DDR_PHY_915_PHY_ADR_CALVL_OBS1_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_915_PHY_ADR_CALVL_OBS1_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_916_REGOFF 0xe50 |
| #define HWIO_DDR_PHY_916_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_916_REGOFF) |
| #define HWIO_DDR_PHY_916_PHY_ADR_CALVL_FG_0_3_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_916_PHY_ADR_CALVL_FG_0_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_916_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_916_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_916_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_916_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_917_REGOFF 0xe54 |
| #define HWIO_DDR_PHY_917_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_917_REGOFF) |
| #define HWIO_DDR_PHY_917_PHY_ADR_CALVL_BG_0_3_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_917_PHY_ADR_CALVL_BG_0_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_917_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_917_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_917_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_917_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_918_REGOFF 0xe58 |
| #define HWIO_DDR_PHY_918_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_918_REGOFF) |
| #define HWIO_DDR_PHY_918_PHY_ADR_CALVL_FG_1_3_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_918_PHY_ADR_CALVL_FG_1_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_918_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_918_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_918_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_918_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_919_REGOFF 0xe5c |
| #define HWIO_DDR_PHY_919_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_919_REGOFF) |
| #define HWIO_DDR_PHY_919_PHY_ADR_CALVL_BG_1_3_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_919_PHY_ADR_CALVL_BG_1_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_919_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_919_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_919_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_919_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_920_REGOFF 0xe60 |
| #define HWIO_DDR_PHY_920_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_920_REGOFF) |
| #define HWIO_DDR_PHY_920_PHY_ADR_CALVL_FG_2_3_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_920_PHY_ADR_CALVL_FG_2_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_920_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_920_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_920_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_920_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_921_REGOFF 0xe64 |
| #define HWIO_DDR_PHY_921_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_921_REGOFF) |
| #define HWIO_DDR_PHY_921_PHY_ADR_CALVL_BG_2_3_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_921_PHY_ADR_CALVL_BG_2_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_921_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_921_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_921_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_921_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_922_REGOFF 0xe68 |
| #define HWIO_DDR_PHY_922_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_922_REGOFF) |
| #define HWIO_DDR_PHY_922_PHY_ADR_CALVL_FG_3_3_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_922_PHY_ADR_CALVL_FG_3_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_922_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_922_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_922_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_922_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_923_REGOFF 0xe6c |
| #define HWIO_DDR_PHY_923_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_923_REGOFF) |
| #define HWIO_DDR_PHY_923_PHY_ADR_CALVL_BG_3_3_FLDMASK (0xfffff) |
| #define HWIO_DDR_PHY_923_PHY_ADR_CALVL_BG_3_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_923_RESERVED_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_923_RESERVED_FLDSHFT (20) |
| #define HWIO_DDR_PHY_923_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_923_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_924_REGOFF 0xe70 |
| #define HWIO_DDR_PHY_924_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_924_REGOFF) |
| #define HWIO_DDR_PHY_924_PHY_ADR_ADDR_SEL_3_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_924_PHY_ADR_ADDR_SEL_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_924_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_924_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_925_REGOFF 0xe74 |
| #define HWIO_DDR_PHY_925_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_925_REGOFF) |
| #define HWIO_DDR_PHY_925_PHY_ADR_LP4_BOOT_SLV_DELAY_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_925_PHY_ADR_LP4_BOOT_SLV_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_925_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_925_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_925_PHY_ADR_BIT_MASK_3_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_925_PHY_ADR_BIT_MASK_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_925_RESERVED1_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_925_RESERVED1_FLDSHFT (22) |
| #define HWIO_DDR_PHY_925_PHY_ADR_SEG_MASK_3_FLDMASK (0x3f000000) |
| #define HWIO_DDR_PHY_925_PHY_ADR_SEG_MASK_3_FLDSHFT (24) |
| #define HWIO_DDR_PHY_925_RESERVED2_FLDMASK (0xc0000000) |
| #define HWIO_DDR_PHY_925_RESERVED2_FLDSHFT (30) |
| |
| #define HWIO_DDR_PHY_926_REGOFF 0xe78 |
| #define HWIO_DDR_PHY_926_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_926_REGOFF) |
| #define HWIO_DDR_PHY_926_PHY_ADR_CALVL_TRAIN_MASK_3_FLDMASK (0x3f) |
| #define HWIO_DDR_PHY_926_PHY_ADR_CALVL_TRAIN_MASK_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_926_RESERVED_FLDMASK (0xc0) |
| #define HWIO_DDR_PHY_926_RESERVED_FLDSHFT (6) |
| #define HWIO_DDR_PHY_926_PHY_ADR_SW_TXIO_CTRL_3_FLDMASK (0x3f00) |
| #define HWIO_DDR_PHY_926_PHY_ADR_SW_TXIO_CTRL_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_926_RESERVED1_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_926_RESERVED1_FLDSHFT (14) |
| #define HWIO_DDR_PHY_926_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_926_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_927_REGOFF 0xe7c |
| #define HWIO_DDR_PHY_927_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_927_REGOFF) |
| #define HWIO_DDR_PHY_927_PHY_ADR_TSEL_SELECT_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_927_PHY_ADR_TSEL_SELECT_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_927_PHY_ADR0_CLK_WR_SLAVE_DELAY_3_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_927_PHY_ADR0_CLK_WR_SLAVE_DELAY_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_927_RESERVED_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_927_RESERVED_FLDSHFT (19) |
| #define HWIO_DDR_PHY_927_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_927_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_928_REGOFF 0xe80 |
| #define HWIO_DDR_PHY_928_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_928_REGOFF) |
| #define HWIO_DDR_PHY_928_PHY_ADR1_CLK_WR_SLAVE_DELAY_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_928_PHY_ADR1_CLK_WR_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_928_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_928_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_928_PHY_ADR2_CLK_WR_SLAVE_DELAY_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_928_PHY_ADR2_CLK_WR_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_928_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_928_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_929_REGOFF 0xe84 |
| #define HWIO_DDR_PHY_929_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_929_REGOFF) |
| #define HWIO_DDR_PHY_929_PHY_ADR3_CLK_WR_SLAVE_DELAY_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_929_PHY_ADR3_CLK_WR_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_929_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_929_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_929_PHY_ADR4_CLK_WR_SLAVE_DELAY_3_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_929_PHY_ADR4_CLK_WR_SLAVE_DELAY_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_929_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_929_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_930_REGOFF 0xe88 |
| #define HWIO_DDR_PHY_930_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_930_REGOFF) |
| #define HWIO_DDR_PHY_930_PHY_ADR5_CLK_WR_SLAVE_DELAY_3_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_930_PHY_ADR5_CLK_WR_SLAVE_DELAY_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_930_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_930_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_930_PHY_ADR_SW_MASTER_MODE_3_FLDMASK (0xf0000) |
| #define HWIO_DDR_PHY_930_PHY_ADR_SW_MASTER_MODE_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_930_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_930_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_930_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_930_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_931_REGOFF 0xe8c |
| #define HWIO_DDR_PHY_931_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_931_REGOFF) |
| #define HWIO_DDR_PHY_931_PHY_ADR_MASTER_DELAY_START_3_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_931_PHY_ADR_MASTER_DELAY_START_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_931_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_931_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_931_PHY_ADR_MASTER_DELAY_STEP_3_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_931_PHY_ADR_MASTER_DELAY_STEP_3_FLDSHFT (16) |
| #define HWIO_DDR_PHY_931_RESERVED1_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_931_RESERVED1_FLDSHFT (22) |
| #define HWIO_DDR_PHY_931_PHY_ADR_MASTER_DELAY_WAIT_3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_931_PHY_ADR_MASTER_DELAY_WAIT_3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_932_REGOFF 0xe90 |
| #define HWIO_DDR_PHY_932_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_932_REGOFF) |
| #define HWIO_DDR_PHY_932_PHY_ADR_MASTER_DELAY_HALF_MEASURE_3_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_932_PHY_ADR_MASTER_DELAY_HALF_MEASURE_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_932_PHY_ADR_CALVL_DLY_STEP_3_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_932_PHY_ADR_CALVL_DLY_STEP_3_FLDSHFT (8) |
| #define HWIO_DDR_PHY_932_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_932_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_932_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_932_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_933_REGOFF 0xe94 |
| #define HWIO_DDR_PHY_933_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_933_REGOFF) |
| #define HWIO_DDR_PHY_933_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_933_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_934_REGOFF 0xe98 |
| #define HWIO_DDR_PHY_934_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_934_REGOFF) |
| #define HWIO_DDR_PHY_934_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_934_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_935_REGOFF 0xe9c |
| #define HWIO_DDR_PHY_935_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_935_REGOFF) |
| #define HWIO_DDR_PHY_935_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_935_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_936_REGOFF 0xea0 |
| #define HWIO_DDR_PHY_936_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_936_REGOFF) |
| #define HWIO_DDR_PHY_936_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_936_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_937_REGOFF 0xea4 |
| #define HWIO_DDR_PHY_937_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_937_REGOFF) |
| #define HWIO_DDR_PHY_937_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_937_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_938_REGOFF 0xea8 |
| #define HWIO_DDR_PHY_938_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_938_REGOFF) |
| #define HWIO_DDR_PHY_938_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_938_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_939_REGOFF 0xeac |
| #define HWIO_DDR_PHY_939_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_939_REGOFF) |
| #define HWIO_DDR_PHY_939_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_939_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_940_REGOFF 0xeb0 |
| #define HWIO_DDR_PHY_940_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_940_REGOFF) |
| #define HWIO_DDR_PHY_940_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_940_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_941_REGOFF 0xeb4 |
| #define HWIO_DDR_PHY_941_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_941_REGOFF) |
| #define HWIO_DDR_PHY_941_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_941_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_942_REGOFF 0xeb8 |
| #define HWIO_DDR_PHY_942_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_942_REGOFF) |
| #define HWIO_DDR_PHY_942_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_942_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_943_REGOFF 0xebc |
| #define HWIO_DDR_PHY_943_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_943_REGOFF) |
| #define HWIO_DDR_PHY_943_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_943_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_944_REGOFF 0xec0 |
| #define HWIO_DDR_PHY_944_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_944_REGOFF) |
| #define HWIO_DDR_PHY_944_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_944_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_945_REGOFF 0xec4 |
| #define HWIO_DDR_PHY_945_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_945_REGOFF) |
| #define HWIO_DDR_PHY_945_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_945_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_946_REGOFF 0xec8 |
| #define HWIO_DDR_PHY_946_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_946_REGOFF) |
| #define HWIO_DDR_PHY_946_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_946_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_947_REGOFF 0xecc |
| #define HWIO_DDR_PHY_947_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_947_REGOFF) |
| #define HWIO_DDR_PHY_947_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_947_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_948_REGOFF 0xed0 |
| #define HWIO_DDR_PHY_948_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_948_REGOFF) |
| #define HWIO_DDR_PHY_948_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_948_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_949_REGOFF 0xed4 |
| #define HWIO_DDR_PHY_949_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_949_REGOFF) |
| #define HWIO_DDR_PHY_949_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_949_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_950_REGOFF 0xed8 |
| #define HWIO_DDR_PHY_950_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_950_REGOFF) |
| #define HWIO_DDR_PHY_950_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_950_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_951_REGOFF 0xedc |
| #define HWIO_DDR_PHY_951_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_951_REGOFF) |
| #define HWIO_DDR_PHY_951_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_951_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_952_REGOFF 0xee0 |
| #define HWIO_DDR_PHY_952_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_952_REGOFF) |
| #define HWIO_DDR_PHY_952_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_952_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_953_REGOFF 0xee4 |
| #define HWIO_DDR_PHY_953_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_953_REGOFF) |
| #define HWIO_DDR_PHY_953_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_953_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_954_REGOFF 0xee8 |
| #define HWIO_DDR_PHY_954_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_954_REGOFF) |
| #define HWIO_DDR_PHY_954_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_954_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_955_REGOFF 0xeec |
| #define HWIO_DDR_PHY_955_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_955_REGOFF) |
| #define HWIO_DDR_PHY_955_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_955_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_956_REGOFF 0xef0 |
| #define HWIO_DDR_PHY_956_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_956_REGOFF) |
| #define HWIO_DDR_PHY_956_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_956_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_957_REGOFF 0xef4 |
| #define HWIO_DDR_PHY_957_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_957_REGOFF) |
| #define HWIO_DDR_PHY_957_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_957_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_958_REGOFF 0xef8 |
| #define HWIO_DDR_PHY_958_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_958_REGOFF) |
| #define HWIO_DDR_PHY_958_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_958_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_959_REGOFF 0xefc |
| #define HWIO_DDR_PHY_959_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_959_REGOFF) |
| #define HWIO_DDR_PHY_959_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_959_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_960_REGOFF 0xf00 |
| #define HWIO_DDR_PHY_960_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_960_REGOFF) |
| #define HWIO_DDR_PHY_960_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_960_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_961_REGOFF 0xf04 |
| #define HWIO_DDR_PHY_961_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_961_REGOFF) |
| #define HWIO_DDR_PHY_961_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_961_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_962_REGOFF 0xf08 |
| #define HWIO_DDR_PHY_962_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_962_REGOFF) |
| #define HWIO_DDR_PHY_962_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_962_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_963_REGOFF 0xf0c |
| #define HWIO_DDR_PHY_963_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_963_REGOFF) |
| #define HWIO_DDR_PHY_963_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_963_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_964_REGOFF 0xf10 |
| #define HWIO_DDR_PHY_964_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_964_REGOFF) |
| #define HWIO_DDR_PHY_964_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_964_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_965_REGOFF 0xf14 |
| #define HWIO_DDR_PHY_965_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_965_REGOFF) |
| #define HWIO_DDR_PHY_965_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_965_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_966_REGOFF 0xf18 |
| #define HWIO_DDR_PHY_966_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_966_REGOFF) |
| #define HWIO_DDR_PHY_966_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_966_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_967_REGOFF 0xf1c |
| #define HWIO_DDR_PHY_967_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_967_REGOFF) |
| #define HWIO_DDR_PHY_967_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_967_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_968_REGOFF 0xf20 |
| #define HWIO_DDR_PHY_968_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_968_REGOFF) |
| #define HWIO_DDR_PHY_968_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_968_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_969_REGOFF 0xf24 |
| #define HWIO_DDR_PHY_969_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_969_REGOFF) |
| #define HWIO_DDR_PHY_969_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_969_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_970_REGOFF 0xf28 |
| #define HWIO_DDR_PHY_970_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_970_REGOFF) |
| #define HWIO_DDR_PHY_970_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_970_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_971_REGOFF 0xf2c |
| #define HWIO_DDR_PHY_971_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_971_REGOFF) |
| #define HWIO_DDR_PHY_971_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_971_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_972_REGOFF 0xf30 |
| #define HWIO_DDR_PHY_972_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_972_REGOFF) |
| #define HWIO_DDR_PHY_972_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_972_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_973_REGOFF 0xf34 |
| #define HWIO_DDR_PHY_973_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_973_REGOFF) |
| #define HWIO_DDR_PHY_973_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_973_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_974_REGOFF 0xf38 |
| #define HWIO_DDR_PHY_974_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_974_REGOFF) |
| #define HWIO_DDR_PHY_974_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_974_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_975_REGOFF 0xf3c |
| #define HWIO_DDR_PHY_975_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_975_REGOFF) |
| #define HWIO_DDR_PHY_975_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_975_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_976_REGOFF 0xf40 |
| #define HWIO_DDR_PHY_976_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_976_REGOFF) |
| #define HWIO_DDR_PHY_976_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_976_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_977_REGOFF 0xf44 |
| #define HWIO_DDR_PHY_977_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_977_REGOFF) |
| #define HWIO_DDR_PHY_977_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_977_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_978_REGOFF 0xf48 |
| #define HWIO_DDR_PHY_978_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_978_REGOFF) |
| #define HWIO_DDR_PHY_978_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_978_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_979_REGOFF 0xf4c |
| #define HWIO_DDR_PHY_979_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_979_REGOFF) |
| #define HWIO_DDR_PHY_979_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_979_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_980_REGOFF 0xf50 |
| #define HWIO_DDR_PHY_980_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_980_REGOFF) |
| #define HWIO_DDR_PHY_980_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_980_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_981_REGOFF 0xf54 |
| #define HWIO_DDR_PHY_981_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_981_REGOFF) |
| #define HWIO_DDR_PHY_981_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_981_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_982_REGOFF 0xf58 |
| #define HWIO_DDR_PHY_982_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_982_REGOFF) |
| #define HWIO_DDR_PHY_982_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_982_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_983_REGOFF 0xf5c |
| #define HWIO_DDR_PHY_983_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_983_REGOFF) |
| #define HWIO_DDR_PHY_983_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_983_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_984_REGOFF 0xf60 |
| #define HWIO_DDR_PHY_984_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_984_REGOFF) |
| #define HWIO_DDR_PHY_984_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_984_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_985_REGOFF 0xf64 |
| #define HWIO_DDR_PHY_985_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_985_REGOFF) |
| #define HWIO_DDR_PHY_985_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_985_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_986_REGOFF 0xf68 |
| #define HWIO_DDR_PHY_986_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_986_REGOFF) |
| #define HWIO_DDR_PHY_986_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_986_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_987_REGOFF 0xf6c |
| #define HWIO_DDR_PHY_987_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_987_REGOFF) |
| #define HWIO_DDR_PHY_987_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_987_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_988_REGOFF 0xf70 |
| #define HWIO_DDR_PHY_988_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_988_REGOFF) |
| #define HWIO_DDR_PHY_988_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_988_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_989_REGOFF 0xf74 |
| #define HWIO_DDR_PHY_989_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_989_REGOFF) |
| #define HWIO_DDR_PHY_989_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_989_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_990_REGOFF 0xf78 |
| #define HWIO_DDR_PHY_990_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_990_REGOFF) |
| #define HWIO_DDR_PHY_990_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_990_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_991_REGOFF 0xf7c |
| #define HWIO_DDR_PHY_991_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_991_REGOFF) |
| #define HWIO_DDR_PHY_991_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_991_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_992_REGOFF 0xf80 |
| #define HWIO_DDR_PHY_992_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_992_REGOFF) |
| #define HWIO_DDR_PHY_992_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_992_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_993_REGOFF 0xf84 |
| #define HWIO_DDR_PHY_993_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_993_REGOFF) |
| #define HWIO_DDR_PHY_993_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_993_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_994_REGOFF 0xf88 |
| #define HWIO_DDR_PHY_994_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_994_REGOFF) |
| #define HWIO_DDR_PHY_994_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_994_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_995_REGOFF 0xf8c |
| #define HWIO_DDR_PHY_995_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_995_REGOFF) |
| #define HWIO_DDR_PHY_995_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_995_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_996_REGOFF 0xf90 |
| #define HWIO_DDR_PHY_996_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_996_REGOFF) |
| #define HWIO_DDR_PHY_996_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_996_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_997_REGOFF 0xf94 |
| #define HWIO_DDR_PHY_997_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_997_REGOFF) |
| #define HWIO_DDR_PHY_997_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_997_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_998_REGOFF 0xf98 |
| #define HWIO_DDR_PHY_998_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_998_REGOFF) |
| #define HWIO_DDR_PHY_998_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_998_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_999_REGOFF 0xf9c |
| #define HWIO_DDR_PHY_999_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_999_REGOFF) |
| #define HWIO_DDR_PHY_999_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_999_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1000_REGOFF 0xfa0 |
| #define HWIO_DDR_PHY_1000_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1000_REGOFF) |
| #define HWIO_DDR_PHY_1000_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1000_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1001_REGOFF 0xfa4 |
| #define HWIO_DDR_PHY_1001_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1001_REGOFF) |
| #define HWIO_DDR_PHY_1001_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1001_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1002_REGOFF 0xfa8 |
| #define HWIO_DDR_PHY_1002_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1002_REGOFF) |
| #define HWIO_DDR_PHY_1002_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1002_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1003_REGOFF 0xfac |
| #define HWIO_DDR_PHY_1003_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1003_REGOFF) |
| #define HWIO_DDR_PHY_1003_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1003_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1004_REGOFF 0xfb0 |
| #define HWIO_DDR_PHY_1004_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1004_REGOFF) |
| #define HWIO_DDR_PHY_1004_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1004_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1005_REGOFF 0xfb4 |
| #define HWIO_DDR_PHY_1005_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1005_REGOFF) |
| #define HWIO_DDR_PHY_1005_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1005_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1006_REGOFF 0xfb8 |
| #define HWIO_DDR_PHY_1006_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1006_REGOFF) |
| #define HWIO_DDR_PHY_1006_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1006_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1007_REGOFF 0xfbc |
| #define HWIO_DDR_PHY_1007_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1007_REGOFF) |
| #define HWIO_DDR_PHY_1007_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1007_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1008_REGOFF 0xfc0 |
| #define HWIO_DDR_PHY_1008_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1008_REGOFF) |
| #define HWIO_DDR_PHY_1008_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1008_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1009_REGOFF 0xfc4 |
| #define HWIO_DDR_PHY_1009_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1009_REGOFF) |
| #define HWIO_DDR_PHY_1009_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1009_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1010_REGOFF 0xfc8 |
| #define HWIO_DDR_PHY_1010_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1010_REGOFF) |
| #define HWIO_DDR_PHY_1010_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1010_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1011_REGOFF 0xfcc |
| #define HWIO_DDR_PHY_1011_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1011_REGOFF) |
| #define HWIO_DDR_PHY_1011_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1011_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1012_REGOFF 0xfd0 |
| #define HWIO_DDR_PHY_1012_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1012_REGOFF) |
| #define HWIO_DDR_PHY_1012_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1012_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1013_REGOFF 0xfd4 |
| #define HWIO_DDR_PHY_1013_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1013_REGOFF) |
| #define HWIO_DDR_PHY_1013_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1013_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1014_REGOFF 0xfd8 |
| #define HWIO_DDR_PHY_1014_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1014_REGOFF) |
| #define HWIO_DDR_PHY_1014_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1014_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1015_REGOFF 0xfdc |
| #define HWIO_DDR_PHY_1015_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1015_REGOFF) |
| #define HWIO_DDR_PHY_1015_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1015_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1016_REGOFF 0xfe0 |
| #define HWIO_DDR_PHY_1016_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1016_REGOFF) |
| #define HWIO_DDR_PHY_1016_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1016_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1017_REGOFF 0xfe4 |
| #define HWIO_DDR_PHY_1017_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1017_REGOFF) |
| #define HWIO_DDR_PHY_1017_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1017_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1018_REGOFF 0xfe8 |
| #define HWIO_DDR_PHY_1018_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1018_REGOFF) |
| #define HWIO_DDR_PHY_1018_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1018_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1019_REGOFF 0xfec |
| #define HWIO_DDR_PHY_1019_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1019_REGOFF) |
| #define HWIO_DDR_PHY_1019_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1019_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1020_REGOFF 0xff0 |
| #define HWIO_DDR_PHY_1020_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1020_REGOFF) |
| #define HWIO_DDR_PHY_1020_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1020_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1021_REGOFF 0xff4 |
| #define HWIO_DDR_PHY_1021_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1021_REGOFF) |
| #define HWIO_DDR_PHY_1021_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1021_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1022_REGOFF 0xff8 |
| #define HWIO_DDR_PHY_1022_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1022_REGOFF) |
| #define HWIO_DDR_PHY_1022_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1022_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1023_REGOFF 0xffc |
| #define HWIO_DDR_PHY_1023_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1023_REGOFF) |
| #define HWIO_DDR_PHY_1023_OBSOLETE0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1023_OBSOLETE0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1024_REGOFF 0x1000 |
| #define HWIO_DDR_PHY_1024_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1024_REGOFF) |
| #define HWIO_DDR_PHY_1024_PHY_FREQ_SEL_FLDMASK (0x7) |
| #define HWIO_DDR_PHY_1024_PHY_FREQ_SEL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1024_RESERVED_FLDMASK (0xf8) |
| #define HWIO_DDR_PHY_1024_RESERVED_FLDSHFT (3) |
| #define HWIO_DDR_PHY_1024_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_1024_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_1025_REGOFF 0x1004 |
| #define HWIO_DDR_PHY_1025_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1025_REGOFF) |
| #define HWIO_DDR_PHY_1025_PHY_FREQ_SEL_FROM_REGIF_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1025_PHY_FREQ_SEL_FROM_REGIF_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1025_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1025_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1025_PHY_FREQ_SEL_MULTICAST_EN_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_1025_PHY_FREQ_SEL_MULTICAST_EN_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1025_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_1025_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_1025_PHY_FREQ_SEL_INDEX_FLDMASK (0x30000) |
| #define HWIO_DDR_PHY_1025_PHY_FREQ_SEL_INDEX_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1025_RESERVED2_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1025_RESERVED2_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1025_PHY_SW_GRP_SHIFT_0_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_1025_PHY_SW_GRP_SHIFT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1025_RESERVED3_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1025_RESERVED3_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1026_REGOFF 0x1008 |
| #define HWIO_DDR_PHY_1026_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1026_REGOFF) |
| #define HWIO_DDR_PHY_1026_PHY_SW_GRP_SHIFT_1_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_1026_PHY_SW_GRP_SHIFT_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1026_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_1026_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_1026_PHY_GRP_BYPASS_SLAVE_DELAY_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_1026_PHY_GRP_BYPASS_SLAVE_DELAY_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1026_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_1026_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_1026_PHY_SW_GRP_BYPASS_SHIFT_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_1026_PHY_SW_GRP_BYPASS_SHIFT_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1026_RESERVED2_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1026_RESERVED2_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1027_REGOFF 0x100c |
| #define HWIO_DDR_PHY_1027_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1027_REGOFF) |
| #define HWIO_DDR_PHY_1027_PHY_GRP_BYPASS_OVERRIDE_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1027_PHY_GRP_BYPASS_OVERRIDE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1027_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1027_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1027_SC_PHY_MANUAL_UPDATE_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_1027_SC_PHY_MANUAL_UPDATE_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1027_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_1027_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_1027_PHY_LP4_BOOT_DISABLE_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1027_PHY_LP4_BOOT_DISABLE_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1027_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1027_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1027_PHY_CSLVL_ENABLE_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_1027_PHY_CSLVL_ENABLE_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1027_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_1027_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_1028_REGOFF 0x1010 |
| #define HWIO_DDR_PHY_1028_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1028_REGOFF) |
| #define HWIO_DDR_PHY_1028_PHY_CSLVL_CS_MAP_FLDMASK (0x3) |
| #define HWIO_DDR_PHY_1028_PHY_CSLVL_CS_MAP_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1028_RESERVED_FLDMASK (0xfc) |
| #define HWIO_DDR_PHY_1028_RESERVED_FLDSHFT (2) |
| #define HWIO_DDR_PHY_1028_PHY_CSLVL_START_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_1028_PHY_CSLVL_START_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1028_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_1028_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_1028_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1028_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1029_REGOFF 0x1014 |
| #define HWIO_DDR_PHY_1029_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1029_REGOFF) |
| #define HWIO_DDR_PHY_1029_PHY_CSLVL_QTR_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_1029_PHY_CSLVL_QTR_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1029_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_1029_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_1029_PHY_CSLVL_COARSE_CHK_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_1029_PHY_CSLVL_COARSE_CHK_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1029_RESERVED1_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_1029_RESERVED1_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_1030_REGOFF 0x1018 |
| #define HWIO_DDR_PHY_1030_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1030_REGOFF) |
| #define HWIO_DDR_PHY_1030_PHY_CSLVL_CAPTURE_CNT_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_1030_PHY_CSLVL_CAPTURE_CNT_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1030_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_1030_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_1030_PHY_CSLVL_COARSE_DLY_FLDMASK (0x7ff00) |
| #define HWIO_DDR_PHY_1030_PHY_CSLVL_COARSE_DLY_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1030_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_1030_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_1030_PHY_CSLVL_COARSE_CAPTURE_CNT_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_1030_PHY_CSLVL_COARSE_CAPTURE_CNT_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1030_RESERVED2_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_1030_RESERVED2_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_1031_REGOFF 0x101c |
| #define HWIO_DDR_PHY_1031_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1031_REGOFF) |
| #define HWIO_DDR_PHY_1031_PHY_CSLVL_DEBUG_MODE_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1031_PHY_CSLVL_DEBUG_MODE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1031_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1031_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1031_SC_PHY_CSLVL_DEBUG_CONT_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_1031_SC_PHY_CSLVL_DEBUG_CONT_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1031_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_1031_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_1031_SC_PHY_CSLVL_ERROR_CLR_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1031_SC_PHY_CSLVL_ERROR_CLR_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1031_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1031_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1031_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1031_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1032_REGOFF 0x1020 |
| #define HWIO_DDR_PHY_1032_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1032_REGOFF) |
| #define HWIO_DDR_PHY_1032_PHY_CSLVL_OBS0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1032_PHY_CSLVL_OBS0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1033_REGOFF 0x1024 |
| #define HWIO_DDR_PHY_1033_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1033_REGOFF) |
| #define HWIO_DDR_PHY_1033_PHY_CSLVL_OBS1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1033_PHY_CSLVL_OBS1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1034_REGOFF 0x1028 |
| #define HWIO_DDR_PHY_1034_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1034_REGOFF) |
| #define HWIO_DDR_PHY_1034_PHY_CALVL_CS_MAP_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_1034_PHY_CALVL_CS_MAP_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1034_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_1034_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_1034_PHY_GRP_SLV_DLY_ENC_OBS_SELECT_FLDMASK (0x3ff00) |
| #define HWIO_DDR_PHY_1034_PHY_GRP_SLV_DLY_ENC_OBS_SELECT_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1034_RESERVED1_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1034_RESERVED1_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1034_PHY_GRP_SHIFT_OBS_SELECT_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_1034_PHY_GRP_SHIFT_OBS_SELECT_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1034_RESERVED2_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1034_RESERVED2_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1035_REGOFF 0x102c |
| #define HWIO_DDR_PHY_1035_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1035_REGOFF) |
| #define HWIO_DDR_PHY_1035_PHY_GRP_SLV_DLY_ENC_OBS_FLDMASK (0x3ff) |
| #define HWIO_DDR_PHY_1035_PHY_GRP_SLV_DLY_ENC_OBS_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1035_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_1035_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_1035_PHY_GRP_SHIFT_OBS_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_1035_PHY_GRP_SHIFT_OBS_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1035_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_1035_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_1035_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_1035_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1035_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_1035_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_1036_REGOFF 0x1030 |
| #define HWIO_DDR_PHY_1036_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1036_REGOFF) |
| #define HWIO_DDR_PHY_1036_PHY_ADRCTL_SNAP_OBS_REGS_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1036_PHY_ADRCTL_SNAP_OBS_REGS_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1036_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1036_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1036_PHY_DFI_PHYUPD_TYPE_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_1036_PHY_DFI_PHYUPD_TYPE_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1036_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_1036_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_1036_PHY_ADRCTL_LPDDR_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1036_PHY_ADRCTL_LPDDR_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1036_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1036_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1036_PHY_LP4_ACTIVE_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_1036_PHY_LP4_ACTIVE_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1036_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_1036_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_1037_REGOFF 0x1034 |
| #define HWIO_DDR_PHY_1037_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1037_REGOFF) |
| #define HWIO_DDR_PHY_1037_PHY_LPDDR3_CS_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1037_PHY_LPDDR3_CS_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1037_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1037_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1037_PHY_CALVL_RESULT_MASK_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_1037_PHY_CALVL_RESULT_MASK_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1037_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_1037_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_1037_SC_PHY_UPDATE_CLK_CAL_VALUES_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1037_SC_PHY_UPDATE_CLK_CAL_VALUES_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1037_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1037_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1037_PHY_CONTINUOUS_CLK_CAL_UPDATE_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_1037_PHY_CONTINUOUS_CLK_CAL_UPDATE_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1037_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_1037_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_1038_REGOFF 0x1038 |
| #define HWIO_DDR_PHY_1038_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1038_REGOFF) |
| #define HWIO_DDR_PHY_1038_PHY_SW_TXIO_CTRL_0_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_1038_PHY_SW_TXIO_CTRL_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1038_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_1038_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_1038_PHY_SW_TXIO_CTRL_1_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_1038_PHY_SW_TXIO_CTRL_1_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1038_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_1038_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_1038_PHY_MEMCLK_SW_TXIO_CTRL_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1038_PHY_MEMCLK_SW_TXIO_CTRL_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1038_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1038_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1038_PHY_CA_SW_TXPWR_CTRL_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_1038_PHY_CA_SW_TXPWR_CTRL_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1038_RESERVED3_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_1038_RESERVED3_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_1039_REGOFF 0x103c |
| #define HWIO_DDR_PHY_1039_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1039_REGOFF) |
| #define HWIO_DDR_PHY_1039_PHY_MEMCLK_SW_TXPWR_CTRL_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1039_PHY_MEMCLK_SW_TXPWR_CTRL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1039_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1039_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1039_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_1039_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_1040_REGOFF 0x1040 |
| #define HWIO_DDR_PHY_1040_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1040_REGOFF) |
| #define HWIO_DDR_PHY_1040_PHY_USER_DEF_REG_AC_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1040_PHY_USER_DEF_REG_AC_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1041_REGOFF 0x1044 |
| #define HWIO_DDR_PHY_1041_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1041_REGOFF) |
| #define HWIO_DDR_PHY_1041_PHY_USER_DEF_REG_AC_1_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1041_PHY_USER_DEF_REG_AC_1_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1042_REGOFF 0x1048 |
| #define HWIO_DDR_PHY_1042_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1042_REGOFF) |
| #define HWIO_DDR_PHY_1042_PHY_USER_DEF_REG_AC_2_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1042_PHY_USER_DEF_REG_AC_2_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1043_REGOFF 0x104c |
| #define HWIO_DDR_PHY_1043_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1043_REGOFF) |
| #define HWIO_DDR_PHY_1043_PHY_USER_DEF_REG_AC_3_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1043_PHY_USER_DEF_REG_AC_3_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1044_REGOFF 0x1050 |
| #define HWIO_DDR_PHY_1044_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1044_REGOFF) |
| #define HWIO_DDR_PHY_1044_PHY_PLL_WAIT_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_1044_PHY_PLL_WAIT_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1044_PHY_PLL_WAIT_TOP_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_1044_PHY_PLL_WAIT_TOP_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1044_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1044_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1045_REGOFF 0x1054 |
| #define HWIO_DDR_PHY_1045_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1045_REGOFF) |
| #define HWIO_DDR_PHY_1045_PHY_PLL_CTRL_FLDMASK (0x1fff) |
| #define HWIO_DDR_PHY_1045_PHY_PLL_CTRL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1045_RESERVED_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_1045_RESERVED_FLDSHFT (13) |
| #define HWIO_DDR_PHY_1045_PHY_PLL_CTRL_TOP_FLDMASK (0x1fff0000) |
| #define HWIO_DDR_PHY_1045_PHY_PLL_CTRL_TOP_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1045_RESERVED1_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1045_RESERVED1_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1046_REGOFF 0x1058 |
| #define HWIO_DDR_PHY_1046_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1046_REGOFF) |
| #define HWIO_DDR_PHY_1046_PHY_PLL_CTRL_CA_FLDMASK (0x1fff) |
| #define HWIO_DDR_PHY_1046_PHY_PLL_CTRL_CA_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1046_RESERVED_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_1046_RESERVED_FLDSHFT (13) |
| #define HWIO_DDR_PHY_1046_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1046_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1047_REGOFF 0x105c |
| #define HWIO_DDR_PHY_1047_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1047_REGOFF) |
| #define HWIO_DDR_PHY_1047_PHY_PLL_BYPASS_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_1047_PHY_PLL_BYPASS_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1047_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_1047_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_1047_OBSOLETE1_FLDMASK (0xffffff00) |
| #define HWIO_DDR_PHY_1047_OBSOLETE1_FLDSHFT (8) |
| |
| #define HWIO_DDR_PHY_1048_REGOFF 0x1060 |
| #define HWIO_DDR_PHY_1048_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1048_REGOFF) |
| #define HWIO_DDR_PHY_1048_PHY_LOW_FREQ_SEL_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1048_PHY_LOW_FREQ_SEL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1048_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1048_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1048_PHY_PAD_VREF_CTRL_DQ_0_FLDMASK (0xfff00) |
| #define HWIO_DDR_PHY_1048_PHY_PAD_VREF_CTRL_DQ_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1048_RESERVED1_FLDMASK (0xf00000) |
| #define HWIO_DDR_PHY_1048_RESERVED1_FLDSHFT (20) |
| #define HWIO_DDR_PHY_1048_OBSOLETE2_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1048_OBSOLETE2_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1049_REGOFF 0x1064 |
| #define HWIO_DDR_PHY_1049_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1049_REGOFF) |
| #define HWIO_DDR_PHY_1049_PHY_PAD_VREF_CTRL_DQ_1_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_1049_PHY_PAD_VREF_CTRL_DQ_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1049_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_1049_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_1049_PHY_PAD_VREF_CTRL_DQ_2_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_1049_PHY_PAD_VREF_CTRL_DQ_2_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1049_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_1049_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_1050_REGOFF 0x1068 |
| #define HWIO_DDR_PHY_1050_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1050_REGOFF) |
| #define HWIO_DDR_PHY_1050_PHY_PAD_VREF_CTRL_DQ_3_FLDMASK (0xfff) |
| #define HWIO_DDR_PHY_1050_PHY_PAD_VREF_CTRL_DQ_3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1050_RESERVED_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_1050_RESERVED_FLDSHFT (12) |
| #define HWIO_DDR_PHY_1050_PHY_PAD_VREF_CTRL_AC_FLDMASK (0xfff0000) |
| #define HWIO_DDR_PHY_1050_PHY_PAD_VREF_CTRL_AC_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1050_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_1050_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_1051_REGOFF 0x106c |
| #define HWIO_DDR_PHY_1051_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1051_REGOFF) |
| #define HWIO_DDR_PHY_1051_PHY_CSLVL_DLY_STEP_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_1051_PHY_CSLVL_DLY_STEP_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1051_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_1051_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_1051_PHY_SET_DFI_INPUT_RST_PAD_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_1051_PHY_SET_DFI_INPUT_RST_PAD_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1051_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_1051_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_1051_PHY_GRP_SLAVE_DELAY_0_FLDMASK (0x7ff0000) |
| #define HWIO_DDR_PHY_1051_PHY_GRP_SLAVE_DELAY_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1051_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_1051_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_1052_REGOFF 0x1070 |
| #define HWIO_DDR_PHY_1052_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1052_REGOFF) |
| #define HWIO_DDR_PHY_1052_PHY_GRP_SLAVE_DELAY_1_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_1052_PHY_GRP_SLAVE_DELAY_1_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1052_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_1052_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_1052_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1052_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1053_REGOFF 0x1074 |
| #define HWIO_DDR_PHY_1053_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1053_REGOFF) |
| #define HWIO_DDR_PHY_1053_PHY_LP4_BOOT_PLL_CTRL_FLDMASK (0x1fff) |
| #define HWIO_DDR_PHY_1053_PHY_LP4_BOOT_PLL_CTRL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1053_RESERVED_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_1053_RESERVED_FLDSHFT (13) |
| #define HWIO_DDR_PHY_1053_PHY_LP4_BOOT_PLL_CTRL_CA_FLDMASK (0x1fff0000) |
| #define HWIO_DDR_PHY_1053_PHY_LP4_BOOT_PLL_CTRL_CA_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1053_RESERVED1_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1053_RESERVED1_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1054_REGOFF 0x1078 |
| #define HWIO_DDR_PHY_1054_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1054_REGOFF) |
| #define HWIO_DDR_PHY_1054_PHY_LP4_BOOT_TOP_PLL_CTRL_FLDMASK (0x1fff) |
| #define HWIO_DDR_PHY_1054_PHY_LP4_BOOT_TOP_PLL_CTRL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1054_RESERVED_FLDMASK (0xe000) |
| #define HWIO_DDR_PHY_1054_RESERVED_FLDSHFT (13) |
| #define HWIO_DDR_PHY_1054_PHY_PLL_CTRL_OVERRIDE_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1054_PHY_PLL_CTRL_OVERRIDE_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1055_REGOFF 0x107c |
| #define HWIO_DDR_PHY_1055_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1055_REGOFF) |
| #define HWIO_DDR_PHY_1055_PHY_PLL_OBS_0_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_1055_PHY_PLL_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1055_PHY_PLL_OBS_1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1055_PHY_PLL_OBS_1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1056_REGOFF 0x1080 |
| #define HWIO_DDR_PHY_1056_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1056_REGOFF) |
| #define HWIO_DDR_PHY_1056_PHY_PLL_OBS_2_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_1056_PHY_PLL_OBS_2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1056_PHY_PLL_OBS_3_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1056_PHY_PLL_OBS_3_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1057_REGOFF 0x1084 |
| #define HWIO_DDR_PHY_1057_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1057_REGOFF) |
| #define HWIO_DDR_PHY_1057_PHY_PLL_OBS_4_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_1057_PHY_PLL_OBS_4_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1057_PHY_PLL_TESTOUT_SEL_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_1057_PHY_PLL_TESTOUT_SEL_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1057_RESERVED_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_1057_RESERVED_FLDSHFT (19) |
| #define HWIO_DDR_PHY_1057_PHY_TCKSRE_WAIT_FLDMASK (0xf000000) |
| #define HWIO_DDR_PHY_1057_PHY_TCKSRE_WAIT_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1057_RESERVED1_FLDMASK (0xf0000000) |
| #define HWIO_DDR_PHY_1057_RESERVED1_FLDSHFT (28) |
| |
| #define HWIO_DDR_PHY_1058_REGOFF 0x1088 |
| #define HWIO_DDR_PHY_1058_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1058_REGOFF) |
| #define HWIO_DDR_PHY_1058_PHY_LP4_BOOT_LOW_FREQ_SEL_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1058_PHY_LP4_BOOT_LOW_FREQ_SEL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1058_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1058_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1058_PHY_LP_WAKEUP_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_1058_PHY_LP_WAKEUP_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1058_PHY_LS_IDLE_EN_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1058_PHY_LS_IDLE_EN_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1058_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1058_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1058_PHY_LP_CTRLUPD_CNTR_CFG_FLDMASK (0x1f000000) |
| #define HWIO_DDR_PHY_1058_PHY_LP_CTRLUPD_CNTR_CFG_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1058_RESERVED2_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1058_RESERVED2_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1059_REGOFF 0x108c |
| #define HWIO_DDR_PHY_1059_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1059_REGOFF) |
| #define HWIO_DDR_PHY_1059_PHY_TDFI_PHY_WRDELAY_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1059_PHY_TDFI_PHY_WRDELAY_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1059_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1059_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1059_PHY_PAD_FDBK_DRIVE_FLDMASK (0x7fffff00) |
| #define HWIO_DDR_PHY_1059_PHY_PAD_FDBK_DRIVE_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1059_RESERVED1_FLDMASK (0x80000000) |
| #define HWIO_DDR_PHY_1059_RESERVED1_FLDSHFT (31) |
| |
| #define HWIO_DDR_PHY_1060_REGOFF 0x1090 |
| #define HWIO_DDR_PHY_1060_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1060_REGOFF) |
| #define HWIO_DDR_PHY_1060_PHY_PAD_FDBK_DRIVE2_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_1060_PHY_PAD_FDBK_DRIVE2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1060_OBSOLETE1_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1060_OBSOLETE1_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1061_REGOFF 0x1094 |
| #define HWIO_DDR_PHY_1061_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1061_REGOFF) |
| #define HWIO_DDR_PHY_1061_PHY_PAD_DATA_DRIVE_FLDMASK (0x1fffff) |
| #define HWIO_DDR_PHY_1061_PHY_PAD_DATA_DRIVE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1061_RESERVED_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_1061_RESERVED_FLDSHFT (21) |
| #define HWIO_DDR_PHY_1061_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1061_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1062_REGOFF 0x1098 |
| #define HWIO_DDR_PHY_1062_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1062_REGOFF) |
| #define HWIO_DDR_PHY_1062_PHY_PAD_DQS_DRIVE_FLDMASK (0x7fffff) |
| #define HWIO_DDR_PHY_1062_PHY_PAD_DQS_DRIVE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1062_RESERVED_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_1062_RESERVED_FLDSHFT (23) |
| #define HWIO_DDR_PHY_1062_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1062_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1063_REGOFF 0x109c |
| #define HWIO_DDR_PHY_1063_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1063_REGOFF) |
| #define HWIO_DDR_PHY_1063_PHY_PAD_ADDR_DRIVE_FLDMASK (0x1fffffff) |
| #define HWIO_DDR_PHY_1063_PHY_PAD_ADDR_DRIVE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1063_RESERVED_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1063_RESERVED_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1064_REGOFF 0x10a0 |
| #define HWIO_DDR_PHY_1064_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1064_REGOFF) |
| #define HWIO_DDR_PHY_1064_PHY_PAD_CLK_DRIVE_FLDMASK (0x7fffffff) |
| #define HWIO_DDR_PHY_1064_PHY_PAD_CLK_DRIVE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1064_RESERVED_FLDMASK (0x80000000) |
| #define HWIO_DDR_PHY_1064_RESERVED_FLDSHFT (31) |
| |
| #define HWIO_DDR_PHY_1065_REGOFF 0x10a4 |
| #define HWIO_DDR_PHY_1065_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1065_REGOFF) |
| #define HWIO_DDR_PHY_1065_PHY_PAD_FDBK_TERM_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_1065_PHY_PAD_FDBK_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1065_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1065_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1065_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1065_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1066_REGOFF 0x10a8 |
| #define HWIO_DDR_PHY_1066_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1066_REGOFF) |
| #define HWIO_DDR_PHY_1066_PHY_PAD_DATA_TERM_FLDMASK (0x1ffff) |
| #define HWIO_DDR_PHY_1066_PHY_PAD_DATA_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1066_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1066_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1066_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1066_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1067_REGOFF 0x10ac |
| #define HWIO_DDR_PHY_1067_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1067_REGOFF) |
| #define HWIO_DDR_PHY_1067_PHY_PAD_DQS_TERM_FLDMASK (0x1ffff) |
| #define HWIO_DDR_PHY_1067_PHY_PAD_DQS_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1067_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1067_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1067_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1067_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1068_REGOFF 0x10b0 |
| #define HWIO_DDR_PHY_1068_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1068_REGOFF) |
| #define HWIO_DDR_PHY_1068_PHY_PAD_ADDR_TERM_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_1068_PHY_PAD_ADDR_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1068_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1068_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1068_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1068_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1069_REGOFF 0x10b4 |
| #define HWIO_DDR_PHY_1069_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1069_REGOFF) |
| #define HWIO_DDR_PHY_1069_PHY_PAD_CLK_TERM_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_1069_PHY_PAD_CLK_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1069_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1069_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1069_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1069_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1070_REGOFF 0x10b8 |
| #define HWIO_DDR_PHY_1070_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1070_REGOFF) |
| #define HWIO_DDR_PHY_1070_PHY_PAD_CKE_DRIVE_FLDMASK (0x1fffffff) |
| #define HWIO_DDR_PHY_1070_PHY_PAD_CKE_DRIVE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1070_RESERVED_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1070_RESERVED_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1071_REGOFF 0x10bc |
| #define HWIO_DDR_PHY_1071_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1071_REGOFF) |
| #define HWIO_DDR_PHY_1071_PHY_PAD_CKE_TERM_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_1071_PHY_PAD_CKE_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1071_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1071_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1071_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1071_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1072_REGOFF 0x10c0 |
| #define HWIO_DDR_PHY_1072_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1072_REGOFF) |
| #define HWIO_DDR_PHY_1072_PHY_PAD_RST_DRIVE_FLDMASK (0x1fffffff) |
| #define HWIO_DDR_PHY_1072_PHY_PAD_RST_DRIVE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1072_RESERVED_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1072_RESERVED_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1073_REGOFF 0x10c4 |
| #define HWIO_DDR_PHY_1073_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1073_REGOFF) |
| #define HWIO_DDR_PHY_1073_PHY_PAD_RST_TERM_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_1073_PHY_PAD_RST_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1073_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1073_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1073_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1073_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1074_REGOFF 0x10c8 |
| #define HWIO_DDR_PHY_1074_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1074_REGOFF) |
| #define HWIO_DDR_PHY_1074_PHY_PAD_CS_DRIVE_FLDMASK (0x1fffffff) |
| #define HWIO_DDR_PHY_1074_PHY_PAD_CS_DRIVE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1074_RESERVED_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1074_RESERVED_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1075_REGOFF 0x10cc |
| #define HWIO_DDR_PHY_1075_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1075_REGOFF) |
| #define HWIO_DDR_PHY_1075_PHY_PAD_CS_TERM_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_1075_PHY_PAD_CS_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1075_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1075_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1075_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1075_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1076_REGOFF 0x10d0 |
| #define HWIO_DDR_PHY_1076_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1076_REGOFF) |
| #define HWIO_DDR_PHY_1076_PHY_PAD_ODT_DRIVE_FLDMASK (0x1fffffff) |
| #define HWIO_DDR_PHY_1076_PHY_PAD_ODT_DRIVE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1076_RESERVED_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1076_RESERVED_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1077_REGOFF 0x10d4 |
| #define HWIO_DDR_PHY_1077_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1077_REGOFF) |
| #define HWIO_DDR_PHY_1077_PHY_PAD_ODT_TERM_FLDMASK (0x3ffff) |
| #define HWIO_DDR_PHY_1077_PHY_PAD_ODT_TERM_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1077_RESERVED_FLDMASK (0xfc0000) |
| #define HWIO_DDR_PHY_1077_RESERVED_FLDSHFT (18) |
| #define HWIO_DDR_PHY_1077_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1077_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1078_REGOFF 0x10d8 |
| #define HWIO_DDR_PHY_1078_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1078_REGOFF) |
| #define HWIO_DDR_PHY_1078_PHY_ADRCTL_RX_CAL_FLDMASK (0x3fff) |
| #define HWIO_DDR_PHY_1078_PHY_ADRCTL_RX_CAL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1078_RESERVED_FLDMASK (0xc000) |
| #define HWIO_DDR_PHY_1078_RESERVED_FLDSHFT (14) |
| #define HWIO_DDR_PHY_1078_PHY_ADRCTL_LP3_RX_CAL_FLDMASK (0x1fff0000) |
| #define HWIO_DDR_PHY_1078_PHY_ADRCTL_LP3_RX_CAL_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1078_RESERVED1_FLDMASK (0xe0000000) |
| #define HWIO_DDR_PHY_1078_RESERVED1_FLDSHFT (29) |
| |
| #define HWIO_DDR_PHY_1079_REGOFF 0x10dc |
| #define HWIO_DDR_PHY_1079_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1079_REGOFF) |
| #define HWIO_DDR_PHY_1079_PHY_TST_CLK_PAD_CTRL_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1079_PHY_TST_CLK_PAD_CTRL_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1080_REGOFF 0x10e0 |
| #define HWIO_DDR_PHY_1080_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1080_REGOFF) |
| #define HWIO_DDR_PHY_1080_PHY_TST_CLK_PAD_CTRL2_FLDMASK (0x7fffff) |
| #define HWIO_DDR_PHY_1080_PHY_TST_CLK_PAD_CTRL2_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1080_RESERVED_FLDMASK (0x800000) |
| #define HWIO_DDR_PHY_1080_RESERVED_FLDSHFT (23) |
| #define HWIO_DDR_PHY_1080_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1080_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1081_REGOFF 0x10e4 |
| #define HWIO_DDR_PHY_1081_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1081_REGOFF) |
| #define HWIO_DDR_PHY_1081_PHY_TST_CLK_PAD_CTRL3_FLDMASK (0x1fffff) |
| #define HWIO_DDR_PHY_1081_PHY_TST_CLK_PAD_CTRL3_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1081_RESERVED_FLDMASK (0xe00000) |
| #define HWIO_DDR_PHY_1081_RESERVED_FLDSHFT (21) |
| #define HWIO_DDR_PHY_1081_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1081_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1082_REGOFF 0x10e8 |
| #define HWIO_DDR_PHY_1082_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1082_REGOFF) |
| #define HWIO_DDR_PHY_1082_PHY_CAL_MODE_0_FLDMASK (0x1ff) |
| #define HWIO_DDR_PHY_1082_PHY_CAL_MODE_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1082_RESERVED_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_1082_RESERVED_FLDSHFT (9) |
| #define HWIO_DDR_PHY_1082_PHY_CAL_CLEAR_0_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1082_PHY_CAL_CLEAR_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1082_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1082_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1082_PHY_CAL_START_0_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_1082_PHY_CAL_START_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1082_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_1082_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_1083_REGOFF 0x10ec |
| #define HWIO_DDR_PHY_1083_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1083_REGOFF) |
| #define HWIO_DDR_PHY_1083_PHY_CAL_INTERVAL_COUNT_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1083_PHY_CAL_INTERVAL_COUNT_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1084_REGOFF 0x10f0 |
| #define HWIO_DDR_PHY_1084_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1084_REGOFF) |
| #define HWIO_DDR_PHY_1084_PHY_CAL_SAMPLE_WAIT_0_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_1084_PHY_CAL_SAMPLE_WAIT_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1084_PHY_LP4_BOOT_CAL_CLK_SELECT_0_FLDMASK (0x700) |
| #define HWIO_DDR_PHY_1084_PHY_LP4_BOOT_CAL_CLK_SELECT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1084_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_1084_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_1084_PHY_CAL_CLK_SELECT_0_FLDMASK (0x70000) |
| #define HWIO_DDR_PHY_1084_PHY_CAL_CLK_SELECT_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1084_RESERVED1_FLDMASK (0xf80000) |
| #define HWIO_DDR_PHY_1084_RESERVED1_FLDSHFT (19) |
| #define HWIO_DDR_PHY_1084_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1084_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1085_REGOFF 0x10f4 |
| #define HWIO_DDR_PHY_1085_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1085_REGOFF) |
| #define HWIO_DDR_PHY_1085_PHY_CAL_RESULT_OBS_0_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_1085_PHY_CAL_RESULT_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1085_OBSOLETE1_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1085_OBSOLETE1_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1086_REGOFF 0x10f8 |
| #define HWIO_DDR_PHY_1086_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1086_REGOFF) |
| #define HWIO_DDR_PHY_1086_PHY_CAL_RESULT2_OBS_0_FLDMASK (0xffffff) |
| #define HWIO_DDR_PHY_1086_PHY_CAL_RESULT2_OBS_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1086_PHY_CAL_CPTR_CNT_0_FLDMASK (0x7f000000) |
| #define HWIO_DDR_PHY_1086_PHY_CAL_CPTR_CNT_0_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1086_RESERVED_FLDMASK (0x80000000) |
| #define HWIO_DDR_PHY_1086_RESERVED_FLDSHFT (31) |
| |
| #define HWIO_DDR_PHY_1087_REGOFF 0x10fc |
| #define HWIO_DDR_PHY_1087_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1087_REGOFF) |
| #define HWIO_DDR_PHY_1087_PHY_CAL_SETTLING_PRD_0_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_1087_PHY_CAL_SETTLING_PRD_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1087_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_1087_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_1087_PHY_CAL_PU_FINE_ADJ_0_FLDMASK (0xff00) |
| #define HWIO_DDR_PHY_1087_PHY_CAL_PU_FINE_ADJ_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1087_PHY_CAL_PD_FINE_ADJ_0_FLDMASK (0xff0000) |
| #define HWIO_DDR_PHY_1087_PHY_CAL_PD_FINE_ADJ_0_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1087_PHY_CAL_RCV_FINE_ADJ_0_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1087_PHY_CAL_RCV_FINE_ADJ_0_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1088_REGOFF 0x1100 |
| #define HWIO_DDR_PHY_1088_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1088_REGOFF) |
| #define HWIO_DDR_PHY_1088_PHY_CAL_DBG_CFG_0_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1088_PHY_CAL_DBG_CFG_0_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1088_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1088_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1088_SC_PHY_PAD_DBG_CONT_0_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_1088_SC_PHY_PAD_DBG_CONT_0_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1088_RESERVED1_FLDMASK (0xfe00) |
| #define HWIO_DDR_PHY_1088_RESERVED1_FLDSHFT (9) |
| #define HWIO_DDR_PHY_1088_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1088_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1089_REGOFF 0x1104 |
| #define HWIO_DDR_PHY_1089_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1089_REGOFF) |
| #define HWIO_DDR_PHY_1089_PHY_CAL_RESULT3_OBS_0_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1089_PHY_CAL_RESULT3_OBS_0_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1090_REGOFF 0x1108 |
| #define HWIO_DDR_PHY_1090_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1090_REGOFF) |
| #define HWIO_DDR_PHY_1090_PHY_PAD_ATB_CTRL_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_1090_PHY_PAD_ATB_CTRL_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1090_PHY_ADRCTL_MANUAL_UPDATE_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1090_PHY_ADRCTL_MANUAL_UPDATE_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1090_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1090_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1090_PHY_AC_LPBK_ERR_CLEAR_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_1090_PHY_AC_LPBK_ERR_CLEAR_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1090_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_1090_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_1091_REGOFF 0x110c |
| #define HWIO_DDR_PHY_1091_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1091_REGOFF) |
| #define HWIO_DDR_PHY_1091_PHY_AC_LPBK_OBS_SELECT_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1091_PHY_AC_LPBK_OBS_SELECT_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1091_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1091_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1091_PHY_AC_LPBK_ENABLE_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_1091_PHY_AC_LPBK_ENABLE_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1091_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_1091_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_1091_PHY_AC_LPBK_CONTROL_FLDMASK (0x1ff0000) |
| #define HWIO_DDR_PHY_1091_PHY_AC_LPBK_CONTROL_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1091_RESERVED2_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_1091_RESERVED2_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_1092_REGOFF 0x1110 |
| #define HWIO_DDR_PHY_1092_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1092_REGOFF) |
| #define HWIO_DDR_PHY_1092_PHY_AC_PRBS_PATTERN_START_FLDMASK (0x7f) |
| #define HWIO_DDR_PHY_1092_PHY_AC_PRBS_PATTERN_START_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1092_RESERVED_FLDMASK (0x80) |
| #define HWIO_DDR_PHY_1092_RESERVED_FLDSHFT (7) |
| #define HWIO_DDR_PHY_1092_PHY_AC_PRBS_PATTERN_MASK_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_1092_PHY_AC_PRBS_PATTERN_MASK_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1092_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_1092_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_1092_OBSOLETE2_FLDMASK (0xffff0000) |
| #define HWIO_DDR_PHY_1092_OBSOLETE2_FLDSHFT (16) |
| |
| #define HWIO_DDR_PHY_1093_REGOFF 0x1114 |
| #define HWIO_DDR_PHY_1093_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1093_REGOFF) |
| #define HWIO_DDR_PHY_1093_PHY_AC_LPBK_RESULT_OBS_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1093_PHY_AC_LPBK_RESULT_OBS_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1094_REGOFF 0x1118 |
| #define HWIO_DDR_PHY_1094_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1094_REGOFF) |
| #define HWIO_DDR_PHY_1094_PHY_AC_CLK_LPBK_OBS_SELECT_FLDMASK (0x1) |
| #define HWIO_DDR_PHY_1094_PHY_AC_CLK_LPBK_OBS_SELECT_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1094_RESERVED_FLDMASK (0xfe) |
| #define HWIO_DDR_PHY_1094_RESERVED_FLDSHFT (1) |
| #define HWIO_DDR_PHY_1094_PHY_AC_CLK_LPBK_ENABLE_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_1094_PHY_AC_CLK_LPBK_ENABLE_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1094_RESERVED1_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_1094_RESERVED1_FLDSHFT (10) |
| #define HWIO_DDR_PHY_1094_PHY_AC_CLK_LPBK_CONTROL_FLDMASK (0x3f0000) |
| #define HWIO_DDR_PHY_1094_PHY_AC_CLK_LPBK_CONTROL_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1094_RESERVED2_FLDMASK (0xc00000) |
| #define HWIO_DDR_PHY_1094_RESERVED2_FLDSHFT (22) |
| #define HWIO_DDR_PHY_1094_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1094_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1095_REGOFF 0x111c |
| #define HWIO_DDR_PHY_1095_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1095_REGOFF) |
| #define HWIO_DDR_PHY_1095_PHY_AC_CLK_LPBK_RESULT_OBS_FLDMASK (0xffff) |
| #define HWIO_DDR_PHY_1095_PHY_AC_CLK_LPBK_RESULT_OBS_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1095_PHY_AC_PWR_RDC_DISABLE_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1095_PHY_AC_PWR_RDC_DISABLE_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1095_RESERVED_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1095_RESERVED_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1095_PHY_LPDDR4_CONNECT_FLDMASK (0x1000000) |
| #define HWIO_DDR_PHY_1095_PHY_LPDDR4_CONNECT_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1095_RESERVED1_FLDMASK (0xfe000000) |
| #define HWIO_DDR_PHY_1095_RESERVED1_FLDSHFT (25) |
| |
| #define HWIO_DDR_PHY_1096_REGOFF 0x1120 |
| #define HWIO_DDR_PHY_1096_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1096_REGOFF) |
| #define HWIO_DDR_PHY_1096_PHY_CALVL_DEVICE_MAP_FLDMASK (0x1f) |
| #define HWIO_DDR_PHY_1096_PHY_CALVL_DEVICE_MAP_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1096_RESERVED_FLDMASK (0xe0) |
| #define HWIO_DDR_PHY_1096_RESERVED_FLDSHFT (5) |
| #define HWIO_DDR_PHY_1096_PHY_ADRCTL_MSTR_DLY_ENC_SEL_FLDMASK (0xf00) |
| #define HWIO_DDR_PHY_1096_PHY_ADRCTL_MSTR_DLY_ENC_SEL_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1096_RESERVED1_FLDMASK (0xf000) |
| #define HWIO_DDR_PHY_1096_RESERVED1_FLDSHFT (12) |
| #define HWIO_DDR_PHY_1096_PHY_CS_DLY_UPT_PER_AC_SLICE_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1096_PHY_CS_DLY_UPT_PER_AC_SLICE_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1096_RESERVED2_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1096_RESERVED2_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1096_OBSOLETE3_FLDMASK (0xff000000) |
| #define HWIO_DDR_PHY_1096_OBSOLETE3_FLDSHFT (24) |
| |
| #define HWIO_DDR_PHY_1097_REGOFF 0x1124 |
| #define HWIO_DDR_PHY_1097_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1097_REGOFF) |
| #define HWIO_DDR_PHY_1097_PHY_DDL_AC_ENABLE_FLDMASK (0xffffffff) |
| #define HWIO_DDR_PHY_1097_PHY_DDL_AC_ENABLE_FLDSHFT (0) |
| |
| #define HWIO_DDR_PHY_1098_REGOFF 0x1128 |
| #define HWIO_DDR_PHY_1098_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1098_REGOFF) |
| #define HWIO_DDR_PHY_1098_PHY_DDL_AC_MODE_FLDMASK (0x7ff) |
| #define HWIO_DDR_PHY_1098_PHY_DDL_AC_MODE_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1098_RESERVED_FLDMASK (0xf800) |
| #define HWIO_DDR_PHY_1098_RESERVED_FLDSHFT (11) |
| #define HWIO_DDR_PHY_1098_PHY_PAD_BACKGROUND_CAL_FLDMASK (0x10000) |
| #define HWIO_DDR_PHY_1098_PHY_PAD_BACKGROUND_CAL_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1098_RESERVED1_FLDMASK (0xfe0000) |
| #define HWIO_DDR_PHY_1098_RESERVED1_FLDSHFT (17) |
| #define HWIO_DDR_PHY_1098_PHY_INIT_UPDATE_CONFIG_FLDMASK (0x7000000) |
| #define HWIO_DDR_PHY_1098_PHY_INIT_UPDATE_CONFIG_FLDSHFT (24) |
| #define HWIO_DDR_PHY_1098_RESERVED2_FLDMASK (0xf8000000) |
| #define HWIO_DDR_PHY_1098_RESERVED2_FLDSHFT (27) |
| |
| #define HWIO_DDR_PHY_1099_REGOFF 0x112c |
| #define HWIO_DDR_PHY_1099_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1099_REGOFF) |
| #define HWIO_DDR_PHY_1099_PHY_DDL_TRACK_UPD_THRESHOLD_AC_FLDMASK (0xff) |
| #define HWIO_DDR_PHY_1099_PHY_DDL_TRACK_UPD_THRESHOLD_AC_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1099_PHY_DLL_RST_EN_FLDMASK (0x300) |
| #define HWIO_DDR_PHY_1099_PHY_DLL_RST_EN_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1099_RESERVED_FLDMASK (0xfc00) |
| #define HWIO_DDR_PHY_1099_RESERVED_FLDSHFT (10) |
| #define HWIO_DDR_PHY_1099_PHY_AC_INIT_COMPLETE_OBS_FLDMASK (0x3ff0000) |
| #define HWIO_DDR_PHY_1099_PHY_AC_INIT_COMPLETE_OBS_FLDSHFT (16) |
| #define HWIO_DDR_PHY_1099_RESERVED1_FLDMASK (0xfc000000) |
| #define HWIO_DDR_PHY_1099_RESERVED1_FLDSHFT (26) |
| |
| #define HWIO_DDR_PHY_1100_REGOFF 0x1130 |
| #define HWIO_DDR_PHY_1100_ADDR(bAddr, regX) (bAddr + HWIO_DDR_PHY_1100_REGOFF) |
| #define HWIO_DDR_PHY_1100_PHY_DS_INIT_COMPLETE_OBS_FLDMASK (0xf) |
| #define HWIO_DDR_PHY_1100_PHY_DS_INIT_COMPLETE_OBS_FLDSHFT (0) |
| #define HWIO_DDR_PHY_1100_RESERVED_FLDMASK (0xf0) |
| #define HWIO_DDR_PHY_1100_RESERVED_FLDSHFT (4) |
| #define HWIO_DDR_PHY_1100_PHY_UPDATE_MASK_FLDMASK (0x100) |
| #define HWIO_DDR_PHY_1100_PHY_UPDATE_MASK_FLDSHFT (8) |
| #define HWIO_DDR_PHY_1100_RESERVED1_FLDMASK (0xfffffe00) |
| #define HWIO_DDR_PHY_1100_RESERVED1_FLDSHFT (9) |
| |
| #endif /* __MNH_HWIO_DDR_PHY_ */ |
