arch/arm64/Kconfig

config ARM64
	def_bool y
	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
	select ARCH_HAS_ELF_RANDOMIZE
	select ARCH_HAS_KCOV
	select ARCH_HAS_SG_CHAIN
	select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
	select ARCH_USE_CMPXCHG_LOCKREF
	select ARCH_SUPPORTS_ATOMIC_RMW
	select ARCH_WANT_OPTIONAL_GPIOLIB
	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
	select ARCH_WANT_FRAME_POINTERS
	select ARCH_HAVE_CUSTOM_GPIO_H
	select ARCH_HAS_UBSAN_SANITIZE_ALL
	select ARM_AMBA
	select ARM_ARCH_TIMER
	select HAVE_KERNEL_GZIP
	select HAVE_KERNEL_LZ4
	select ARM_GIC
	select AUDIT_ARCH_COMPAT_GENERIC
	select ARM_GIC_V2M if PCI_MSI
	select ARM_GIC_V3
	select ARM_GIC_V3_ITS if PCI_MSI
	select BUILDTIME_EXTABLE_SORT
	select CLONE_BACKWARDS
	select COMMON_CLK if !ARCH_MSM
	select CPU_PM if (SUSPEND || CPU_IDLE)
	select DCACHE_WORD_ACCESS
	select GENERIC_ALLOCATOR
	select EDAC_SUPPORT
	select GENERIC_CLOCKEVENTS
	select GENERIC_CLOCKEVENTS_BROADCAST
	select GENERIC_CPU_AUTOPROBE
	select GENERIC_EARLY_IOREMAP
	select GENERIC_IOMAP
	select GENERIC_IRQ_PROBE
	select GENERIC_IRQ_SHOW
	select GENERIC_SCHED_CLOCK
	select GENERIC_SMP_IDLE_THREAD
	select GENERIC_STRNCPY_FROM_USER
	select GENERIC_STRNLEN_USER
	select GENERIC_TIME_VSYSCALL
	select HANDLE_DOMAIN_IRQ
	select HARDIRQS_SW_RESEND
	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
	select HAVE_ARCH_AUDITSYSCALL
	select HAVE_ARCH_HARDENED_USERCOPY
	select HAVE_ARCH_JUMP_LABEL
	select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
	select HAVE_ARCH_KGDB
	select HAVE_ARCH_MMAP_RND_BITS
	select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
	select HAVE_ARCH_SECCOMP_FILTER
	select HAVE_ARCH_TRACEHOOK
	select HAVE_BPF_JIT
	select HAVE_C_RECORDMCOUNT
	select HAVE_CC_STACKPROTECTOR
	select HAVE_CMPXCHG_DOUBLE
	select HAVE_DEBUG_BUGVERBOSE
	select HAVE_DEBUG_KMEMLEAK
	select HAVE_DMA_API_DEBUG
	select HAVE_DMA_ATTRS
	select HAVE_DMA_CONTIGUOUS
	select HAVE_DYNAMIC_FTRACE
	select HAVE_EFFICIENT_UNALIGNED_ACCESS
	select HAVE_FTRACE_MCOUNT_RECORD
	select HAVE_FUNCTION_TRACER
	select HAVE_FUNCTION_GRAPH_TRACER
	select HAVE_GENERIC_DMA_COHERENT
	select HAVE_IRQ_TIME_ACCOUNTING
	select HAVE_HW_BREAKPOINT if PERF_EVENTS
	select HAVE_MEMBLOCK
	select HAVE_PATA_PLATFORM
	select HAVE_PERF_EVENTS
	select HAVE_PERF_REGS
	select HAVE_PERF_USER_STACK_DUMP
	select HAVE_RCU_TABLE_FREE
	select HAVE_SYSCALL_TRACEPOINTS
	select IRQ_DOMAIN
	select MODULES_USE_ELF_RELA
	select NO_BOOTMEM
	select OF
	select OF_EARLY_FLATTREE
	select OF_RESERVED_MEM
	select PERF_USE_VMALLOC
	select POWER_RESET
	select POWER_SUPPLY
	select RTC_LIB
	select SPARSE_IRQ
	select SYSCTL_EXCEPTION_TRACE
	select HAVE_CONTEXT_TRACKING
	select MSM_JTAGV8 if CORESIGHT_ETMV4
	help
	  ARM 64-bit (AArch64) Linux support.

config 64BIT
	def_bool y

config ARCH_PHYS_ADDR_T_64BIT
	def_bool y

config MMU
	def_bool y

config ARCH_MMAP_RND_BITS_MIN
       default 14 if ARM64_64K_PAGES
       default 16 if ARM64_16K_PAGES
       default 18

# max bits determined by the following formula:
#  VA_BITS - PAGE_SHIFT - 3
config ARCH_MMAP_RND_BITS_MAX
       default 19 if ARM64_VA_BITS=36
       default 24 if ARM64_VA_BITS=39
       default 27 if ARM64_VA_BITS=42
       default 30 if ARM64_VA_BITS=47
       default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
       default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
       default 33 if ARM64_VA_BITS=48
       default 14 if ARM64_64K_PAGES
       default 16 if ARM64_16K_PAGES
       default 18

config ARCH_MMAP_RND_COMPAT_BITS_MIN
       default 7 if ARM64_64K_PAGES
       default 9 if ARM64_16K_PAGES
       default 11

config ARCH_MMAP_RND_COMPAT_BITS_MAX
       default 16

config NO_IOPORT_MAP
	def_bool y if !PCI

config ILLEGAL_POINTER_VALUE
	hex
	default 0xdead000000000000

config STACKTRACE_SUPPORT
	def_bool y

config ILLEGAL_POINTER_VALUE
	hex
	default 0xdead000000000000

config LOCKDEP_SUPPORT
	def_bool y

config TRACE_IRQFLAGS_SUPPORT
	def_bool y

config RWSEM_XCHGADD_ALGORITHM
	def_bool y

config GENERIC_BUG
	def_bool y
	depends on BUG

config GENERIC_HWEIGHT
	def_bool y

config GENERIC_CSUM
        def_bool y

config GENERIC_CALIBRATE_DELAY
	def_bool y

config ZONE_DMA
	def_bool y

config HAVE_GENERIC_RCU_GUP
	def_bool y

config ARCH_DMA_ADDR_T_64BIT
	def_bool y

config NEED_DMA_MAP_STATE
	def_bool y

config NEED_SG_DMA_LENGTH
	def_bool y

config ARM64_DMA_USE_IOMMU
	bool
	select ARM_HAS_SG_CHAIN
	select NEED_SG_DMA_LENGTH

if ARM64_DMA_USE_IOMMU

config ARM64_DMA_IOMMU_ALIGNMENT
	int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
	range 4 9
	default 8
	help
	  DMA mapping framework by default aligns all buffers to the smallest
	  PAGE_SIZE order which is greater than or equal to the requested buffer
	  size. This works well for buffers up to a few hundreds kilobytes, but
	  for larger buffers it just a waste of address space. Drivers which has
	  relatively small addressing window (like 64Mib) might run out of
	  virtual space with just a few allocations.

	  With this parameter you can specify the maximum PAGE_SIZE order for
	  DMA IOMMU buffers. Larger buffers will be aligned only to this
	  specified order. The order is expressed as a power of two multiplied
	  by the PAGE_SIZE.

endif

config SMP
	def_bool y

config SWIOTLB
	def_bool y

config IOMMU_HELPER
	def_bool SWIOTLB

config KERNEL_MODE_NEON
	def_bool y

config FIX_EARLYCON_MEM
	def_bool y

config PGTABLE_LEVELS
	int
	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
	default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48

source "init/Kconfig"

source "kernel/Kconfig.freezer"

menu "Platform selection"

config ARCH_THUNDER
	bool "Cavium Inc. Thunder SoC Family"
	help
	  This enables support for Cavium's Thunder Family of SoCs.

config ARCH_VEXPRESS
	bool "ARMv8 software model (Versatile Express)"
	select ARCH_REQUIRE_GPIOLIB
	select COMMON_CLK_VERSATILE
	select POWER_RESET_VEXPRESS
	select VEXPRESS_CONFIG
	help
	  This enables support for the ARMv8 software model (Versatile
	  Express).

config ARCH_XGENE
	bool "AppliedMicro X-Gene SOC Family"
	help
	  This enables support for AppliedMicro X-Gene SOC Family

config ARCH_MSM
	bool "Qualcomm Platforms"
	select ARCH_REQUIRE_GPIOLIB
	select CLKDEV_LOOKUP
	select HAVE_CLK
	select HAVE_CLK_PREPARE
	select MSM_IRQ
	select PINCTRL
	select SOC_BUS
	select PM_OPP
	select PCI
	select PM_DEVFREQ
	select MSM_DEVFREQ_DEVBW
	select MSM_BIMC_BWMON
	select MSMCCI_HWMON
	select MSM_M4M_HWMON
	select DEVFREQ_GOV_MSM_BW_HWMON
	select DEVFREQ_GOV_MSM_CACHE_HWMON
	select DEVFREQ_SIMPLE_DEV
	select ARCH_HAS_OPP
	select THERMAL_WRITABLE_TRIPS
	select CPU_FREQ_MSM
	select ARM_MEMLAT_MON
	select DEVFREQ_GOV_MEMLAT
	help
	  This enables support for the ARMv8 based Qualcomm chipsets.

config ARCH_MSM8916
	bool "Enable Support for Qualcomm MSM8916"
	depends on ARCH_MSM
	help
	  This enables support for the MSM8916 chipset. If you don't
	  know what to do here, say N

config ARCH_MSM8917
	bool "Enable Support for Qualcomm Technologies Inc MSM8917"
	depends on ARCH_MSM
	help
	  This enables support for the MSM8917 chipset. If you don't
	  know what to do here, say N

config ARCH_MSM8940
	bool "Enable Support for Qualcomm Technologies Inc MSM8940"
	depends on ARCH_MSM
	help
	  This enables support for the MSM8940 chipset. If you don't
	  know what to do here, say N

config ARCH_MSM8953
	bool "Enable Support for Qualcomm Technologies Inc MSM8953"
	depends on ARCH_MSM
	help
	  This enables support for the MSM8953 chipset. If you don't
	  know what to do here, say N

config ARCH_MSM8937
	bool "Enable Support for Qualcomm Technologies Inc MSM8937"
	depends on ARCH_MSM
	help
	  This enables support for the MSM8937 chipset. If you don't
	  know what to do here, say N

config ARCH_MSM8996
	bool "Enable Support for Qualcomm MSM8996"
	depends on ARCH_MSM
	help
	  This enables support for the MSM8996 chipset. If you don't
	  know what to do here, say N

config ARCH_MSMCOBALT
	bool "Enable Support for Qualcomm MSMCOBALT"
	depends on ARCH_MSM
	help
	  This enables support for the MSMCOBALT chipset. If you do not
	  wish to build a kernel that runs on this chipset, say 'N' here.

config ARCH_MSM8994_V1_TLBI_WA
	bool "Enable MSM8994 v1 TLBI workaround"
	depends on ARCH_MSM8994
	help
	  This enables support for the MSM8994 v1 TLBI workaround. This
	  workaround is required for MSM8994 V1 revision where the
	  [39:38] bits of VA are tied to zero and due to which TLBI
	  operations with VA or ASID will not work.

endmenu

menu "Bus support"

config ARM_AMBA
	bool

config PCI
	bool "PCI support"
	help
	  This feature enables support for PCI bus system. If you say Y
	  here, the kernel will include drivers and infrastructure code
	  to support PCI bus devices.

config PCI_DOMAINS
	def_bool PCI

config PCI_DOMAINS_GENERIC
	def_bool PCI

config PCI_SYSCALL
	def_bool PCI

source "drivers/pci/Kconfig"
source "drivers/pci/pcie/Kconfig"
source "drivers/pci/hotplug/Kconfig"

endmenu

menu "Kernel Features"

menu "ARM errata workarounds via the alternatives framework"

config ARM64_ERRATUM_826319
	bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
	  AXI master interface and an L2 cache.

	  If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
	  and is unable to accept a certain write via this interface, it will
	  not progress on read data presented on the read data channel and the
	  system can deadlock.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_827319
	bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
	  master interface and an L2 cache.

	  Under certain conditions this erratum can cause a clean line eviction
	  to occur at the same time as another transaction to the same address
	  on the AMBA 5 CHI interface, which can cause data corruption if the
	  interconnect reorders the two transactions.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_824069
	bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
	  to a coherent interconnect.

	  If a Cortex-A53 processor is executing a store or prefetch for
	  write instruction at the same time as a processor in another
	  cluster is executing a cache maintenance operation to the same
	  address, then this erratum might cause a clean cache line to be
	  incorrectly marked as dirty.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this option does not necessarily enable the
	  workaround, as it depends on the alternative framework, which will
	  only patch the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_819472
	bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
	  present when it is connected to a coherent interconnect.

	  If the processor is executing a load and store exclusive sequence at
	  the same time as a processor in another cluster is executing a cache
	  maintenance operation to the same address, then this erratum might
	  cause data corruption.

	  The workaround promotes data cache clean instructions to
	  data cache clean-and-invalidate.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_832075
	bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 832075 on Cortex-A57 parts up to r1p2.

	  Affected Cortex-A57 parts might deadlock when exclusive load/store
	  instructions to Write-Back memory are mixed with Device loads.

	  The workaround is to promote device loads to use Load-Acquire
	  semantics.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

config ARM64_ERRATUM_845719
	bool "Cortex-A53: 845719: a load might read incorrect data"
	depends on COMPAT
	default y
	help
	  This option adds an alternative code sequence to work around ARM
	  erratum 845719 on Cortex-A53 parts up to r0p4.

	  When running a compat (AArch32) userspace on an affected Cortex-A53
	  part, a load at EL0 from a virtual address that matches the bottom 32
	  bits of the virtual address used by a recent load at (AArch64) EL1
	  might return incorrect data.

	  The workaround is to write the contextidr_el1 register on exception
	  return to a 32-bit task.
	  Please note that this does not necessarily enable the workaround,
	  as it depends on the alternative framework, which will only patch
	  the kernel if an affected CPU is detected.

	  If unsure, say Y.

endmenu


choice
	prompt "Page size"
	default ARM64_4K_PAGES
	help
	  Page size (translation granule) configuration.

config ARM64_4K_PAGES
	bool "4KB"
	help
	  This feature enables 4KB pages support.

config ARM64_64K_PAGES
	bool "64KB"
	help
	  This feature enables 64KB pages support (4KB by default)
	  allowing only two levels of page tables and faster TLB
	  look-up. AArch32 emulation is not available when this feature
	  is enabled.

endchoice

config ARM64_DCACHE_DISABLE
	bool "Disable CPU Data Caches"
	help
	  Disable CPU data cache usage by setting the SCTLR[C] bit during
	  kernel initialization. This will result in a considerable
	  performance impact, but may be useful in certain situations.

	  If you are not sure what to do, select 'N' here.

config ARM64_ICACHE_DISABLE
	bool "Disable CPU Instruction Caches"
	help
	  Disable CPU instruction cache usage by setting the SCTLR[I]
	  bit during kernel initialization. This will result in a
	  considerable performance impact, but may be useful in certain
	  situations.

	  If you are not sure what to do, select 'N' here.

config MSM_APP_API
	bool "API support to enable / disable app settings for MSM8996"
	depends on ARCH_MSM8996 && (ENABLE_FP_SIMD_SETTINGS || MSM_APP_SETTINGS)
	help
	  Add API support to enable / disable the app settings to be used
	  at runtime. These APIs are used to enable / disable app setting
	  when specific aarch32 or aarch64 processes are running.

	  If you are not sure what to do, select 'N' here.

config ENABLE_FP_SIMD_SETTINGS
	bool "Enable FP(Floating Point) Settings for Qualcomm MSM8996"
	depends on ARCH_MSM8996
	select MSM_APP_API
	help
	  Enable FP(Floating Point) and SIMD settings for the MSM8996 during
	  the execution of the aarch32 processes and disable these settings
	  when you switch to the aarch64 processes.

	  If you are not sure what to do, select 'N' here.

config MSM_APP_SETTINGS
	bool "Support to enable / disable app settings for MSM8996"
	depends on ARCH_MSM8996
	select MSM_APP_API
	help
	  Expose an interface used by the userspace at runtime to
	  enable / disable the app specific settings.

	  If you are not sure what to do, select 'N' here.

choice
	prompt "Virtual address space size"
	default ARM64_VA_BITS_39 if ARM64_4K_PAGES
	default ARM64_VA_BITS_42 if ARM64_64K_PAGES
	help
	  Allows choosing one of multiple possible virtual address
	  space sizes. The level of translation table is determined by
	  a combination of page size and virtual address space size.

config ARM64_VA_BITS_39
	bool "39-bit"
	depends on ARM64_4K_PAGES

config ARM64_VA_BITS_42
	bool "42-bit"
	depends on ARM64_64K_PAGES

config ARM64_VA_BITS_48
	bool "48-bit"
	depends on !ARM_SMMU

endchoice

config ARM64_VA_BITS
	int
	default 39 if ARM64_VA_BITS_39
	default 42 if ARM64_VA_BITS_42
	default 48 if ARM64_VA_BITS_48

config ARM64_PGTABLE_LEVELS
	int
	default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
	default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
	default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
	default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48

config CPU_BIG_ENDIAN
       bool "Build big-endian kernel"
       help
         Say Y if you plan on running a kernel in big-endian mode.

config ARM64_SEV_IN_LOCK_UNLOCK
	bool "Add explicit SEV in the spinlock unlock code path"
	help
	  In certain unexplained cases, the stlr alone might not wakeup
	  the processor waiting in WFE on a spinlock.
	  Add an explicity dsb and SEV in write_unlock, read_unlock
	  and spin_unlock to ensure that the core waiting on the lock
	  wakes up from WFE.

config SCHED_MC
	bool "Multi-core scheduler support"
	help
	  Multi-core scheduler support improves the CPU scheduler's decision
	  making when dealing with multi-core CPU chips at a cost of slightly
	  increased overhead in some places. If unsure say N here.

config SCHED_SMT
	bool "SMT scheduler support"
	help
	  Improves the CPU scheduler's decision making when dealing with
	  MultiThreading at a cost of slightly increased overhead in some
	  places. If unsure say N here.

config SCHED_MC
	bool "Multi-core scheduler support"
	depends on ARM_CPU_TOPOLOGY
	help
	  Multi-core scheduler support improves the CPU scheduler's decision
	  making when dealing with multi-core CPU chips at a cost of slightly
	  increased overhead in some places. If unsure say N here.

config SCHED_SMT
	bool "SMT scheduler support"
	depends on ARM_CPU_TOPOLOGY
	help
	  Improves the CPU scheduler's decision making when dealing with
	  MultiThreading at a cost of slightly increased overhead in some
	  places. If unsure say N here.

config NR_CPUS
	int "Maximum number of CPUs (2-64)"
	# These have to remain sorted largest to smallest
	default "8"

config HTC_POWER_DEBUG
	bool "Support htc power debug feature"
	help
	 Use this to enable htc power debug feature including pm statistics,
	 clock/gpio/qpnp pin dump, wakeup source, kernel top and autosuspend
	 stage footprintconfig HTC_POWER_DEBUG

config HOTPLUG_CPU
	bool "Support for hot-pluggable CPUs"
	help
	  Say Y here to experiment with turning CPUs off and on.  CPUs
	  can be controlled through /sys/devices/system/cpu.

# The GPIO number here must be sorted by descending number. In case of
# a multiplatform kernel, we just want the highest value required by the
# selected platforms.
config ARCH_NR_GPIO
        int
        default 1024 if ARCH_TEGRA
        default 1024 if ARCH_MSM
        default 256
        help
          Maximum number of GPIOs in the system.

          If unsure, leave the default value.


source kernel/Kconfig.preempt

source kernel/Kconfig.hz

config ARCH_HAS_HOLES_MEMORYMODEL
	def_bool y if SPARSEMEM

config ARCH_SPARSEMEM_ENABLE
	def_bool y
	select SPARSEMEM_VMEMMAP_ENABLE

config ARCH_SPARSEMEM_DEFAULT
	def_bool ARCH_SPARSEMEM_ENABLE

config ARCH_SELECT_MEMORY_MODEL
	def_bool ARCH_SPARSEMEM_ENABLE

config HAVE_ARCH_PFN_VALID
	def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM

config HW_PERF_EVENTS
	bool "Enable hardware performance counter support for perf events"
	depends on PERF_EVENTS
	default y
	help
	  Enable hardware performance counter support for perf events. If
	  disabled, perf events will use software events only.

config PERF_EVENTS_USERMODE
	bool "Enable usermode access for perf events"
	depends on PERF_EVENTS
	help
	  Enable user-mode access to performance counters for perf events.
	  If enabled, the access permissions allowing CPU performance
	  counters to be accessed from user-mode are set.

	  If you want user-mode programs to access perf events, say Y

config PERF_EVENTS_RESET_PMU_DEBUGFS
	bool "Reset PMU via debugfs node"
	depends on PERF_EVENTS
	help
		Enable the debugfs node that can be used to reset PMUs and all
		state variables associated with PMUs. If enabled, PMU and internal
		state variable are cleared.
		If you want to reset PMU and PMU related internal Perf variables
		via debugfs then say Y.

config ARM64_REG_REBALANCE_ON_CTX_SW
	bool "Rebalance registers during context switches."
	def_bool ARCH_MSM8996
	help
	 Forcefully re-balance register rename pools on context switches for
	 improved performance on some devices.

config SYS_SUPPORTS_HUGETLBFS
	def_bool y

config ARCH_WANT_GENERAL_HUGETLB
	def_bool y

config ARCH_WANT_HUGE_PMD_SHARE
	def_bool y if !ARM64_64K_PAGES

config HAVE_ARCH_TRANSPARENT_HUGEPAGE
	def_bool y

config ARCH_HAS_CACHE_LINE_SIZE
	def_bool y

source "mm/Kconfig"

config SECCOMP
	bool "Enable seccomp to safely compute untrusted bytecode"
	---help---
	  This kernel feature is useful for number crunching applications
	  that may need to compute untrusted bytecode during their
	  execution. By using pipes or other transports made available to
	  the process as file descriptors supporting the read/write
	  syscalls, it's possible to isolate those applications in
	  their own address space using seccomp. Once seccomp is
	  enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
	  and the task is only allowed to execute a few safe syscalls
	  defined by each seccomp mode.

config XEN_DOM0
	def_bool y
	depends on XEN

config XEN
	bool "Xen guest support on ARM64"
	depends on ARM64 && OF
	select SWIOTLB_XEN
	help
	  Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.

config FORCE_MAX_ZONEORDER
	int
	default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
	default "11"

menuconfig ARMV8_DEPRECATED
	bool "Emulate deprecated/obsolete ARMv8 instructions"
	depends on COMPAT
	help
	  Legacy software support may require certain instructions
	  that have been deprecated or obsoleted in the architecture.

	  Enable this config to enable selective emulation of these
	  features.

	  If unsure, say Y

if ARMV8_DEPRECATED

config SWP_EMULATION
	bool "Emulate SWP/SWPB instructions"
	help
	  ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
	  they are always undefined. Say Y here to enable software
	  emulation of these instructions for userspace using LDXR/STXR.

	  In some older versions of glibc [<=2.8] SWP is used during futex
	  trylock() operations with the assumption that the code will not
	  be preempted. This invalid assumption may be more likely to fail
	  with SWP emulation enabled, leading to deadlock of the user
	  application.

	  NOTE: when accessing uncached shared regions, LDXR/STXR rely
	  on an external transaction monitoring block called a global
	  monitor to maintain update atomicity. If your system does not
	  implement a global monitor, this option can cause programs that
	  perform SWP operations to uncached memory to deadlock.

	  If unsure, say Y

config CP15_BARRIER_EMULATION
	bool "Emulate CP15 Barrier instructions"
	help
	  The CP15 barrier instructions - CP15ISB, CP15DSB, and
	  CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
	  strongly recommended to use the ISB, DSB, and DMB
	  instructions instead.

	  Say Y here to enable software emulation of these
	  instructions for AArch32 userspace code. When this option is
	  enabled, CP15 barrier usage is traced which can help
	  identify software that needs updating.

	  If unsure, say Y

config SETEND_EMULATION
	bool "Emulate SETEND instruction"
	help
	  The SETEND instruction alters the data-endianness of the
	  AArch32 EL0, and is deprecated in ARMv8.

	  Say Y here to enable software emulation of the instruction
	  for AArch32 userspace code.

	  Note: All the cpus on the system must have mixed endian support at EL0
	  for this feature to be enabled. If a new CPU - which doesn't support mixed
	  endian - is hotplugged in after this feature has been enabled, there could
	  be unexpected results in the applications.

	  If unsure, say Y

endif

config ARM64_SW_TTBR0_PAN
	bool "Emulate Priviledged Access Never using TTBR0_EL1 switching"
	help
	  Enabling this option prevents the kernel from accessing
	  user-space memory directly by pointing TTBR0_EL1 to a reserved
	  zeroed area and reserved ASID. The user access routines
	  restore the valid TTBR0_EL1 temporarily.

menu "ARMv8.1 architectural features"

config ARM64_PAN
	bool "Enable support for Privileged Access Never (PAN)"
	default y
	help
	 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
	 prevents the kernel or hypervisor from accessing user-space (EL0)
	 memory directly.

	 Choosing this option will cause any unprotected (not using
	 copy_to_user et al) memory access to fail with a permission fault.

	 The feature is detected at runtime, and will remain as a 'nop'
	 instruction if the cpu does not implement the feature.

endmenu

config ARM64_UAO
	bool "Enable support for User Access Override (UAO)"
	default y
	help
	  User Access Override (UAO; part of the ARMv8.2 Extensions)
	  causes the 'unprivileged' variant of the load/store instructions to
	  be overriden to be privileged.

	  This option changes get_user() and friends to use the 'unprivileged'
	  variant of the load/store instructions. This ensures that user-space
	  really did have access to the supplied memory. When addr_limit is
	  set to kernel memory the UAO bit will be set, allowing privileged
	  access to kernel memory.

	  Choosing this option will cause copy_to_user() et al to use user-space
	  memory permissions.

	  The feature is detected at runtime, the kernel will use the
	  regular load/store instructions if the cpu does not implement the
	  feature.

endmenu

menu "Boot options"

config CMDLINE
	string "Default kernel command string"
	default ""
	help
	  Provide a set of default command-line options at build time by
	  entering them here. As a minimum, you should specify the the
	  root device (e.g. root=/dev/nfs).

choice
	prompt "Kernel command line type" if CMDLINE != ""
	default CMDLINE_FROM_BOOTLOADER

config CMDLINE_FROM_BOOTLOADER
	bool "Use bootloader kernel arguments if available"
	help
	  Uses the command-line options passed by the boot loader. If
	  the boot loader doesn't provide any, the default kernel command
	  string provided in CMDLINE will be used.

config CMDLINE_EXTEND
	bool "Extend bootloader kernel arguments"
	help
	  The command-line arguments provided by the boot loader will be
	  appended to the default kernel command string.

config CMDLINE_FORCE
	bool "Always use the default kernel command string"
	help
	  Always use the default kernel command string, even if the boot
	  loader passes other arguments to the kernel.
	  This is useful if you cannot or don't want to change the
	  command-line options your boot loader passes to the kernel.
endchoice

config EFI_STUB
	bool

config EFI
	bool "UEFI runtime support"
	depends on OF && !CPU_BIG_ENDIAN
	select LIBFDT
	select UCS2_STRING
	select EFI_PARAMS_FROM_FDT
	select EFI_RUNTIME_WRAPPERS
	select EFI_STUB
	select EFI_ARMSTUB
	default y
	help
	  This option provides support for runtime services provided
	  by UEFI firmware (such as non-volatile variables, realtime
          clock, and platform reset). A UEFI stub is also provided to
	  allow the kernel to be booted as an EFI application. This
	  is only useful on systems that have UEFI firmware.

config BUILD_ARM64_APPENDED_DTB_IMAGE
	bool "Build a concatenated Image.gz/dtb by default"
	depends on OF
	help
	  Enabling this option will cause a concatenated Image.gz and list of
	  DTBs to be built by default (instead of a standalone Image.gz.)
	  The image will built in arch/arm64/boot/Image.gz-dtb

config BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES
	string "Default dtb names"
	depends on BUILD_ARM64_APPENDED_DTB_IMAGE
	help
	  Space separated list of names of dtbs to append when
	  building a concatenated Image.gz-dtb.

config DMI
	bool "Enable support for SMBIOS (DMI) tables"
	depends on EFI
	default y
	help
	  This enables SMBIOS/DMI feature for systems.

	  This option is only useful on systems that have UEFI firmware.
	  However, even with this option, the resultant kernel should
	  continue to boot on existing non-UEFI platforms.

endmenu

menu "Userspace binary formats"

source "fs/Kconfig.binfmt"

config COMPAT
	bool "Kernel support for 32-bit EL0"
	depends on !ARM64_64K_PAGES
	select COMPAT_BINFMT_ELF
	select HAVE_UID16
	select OLD_SIGSUSPEND3
	select COMPAT_OLD_SIGACTION
	help
	  This option enables support for a 32-bit EL0 running under a 64-bit
	  kernel at EL1. AArch32-specific components such as system calls,
	  the user helper functions, VFP support and the ptrace interface are
	  handled appropriately by the kernel.

	  If you want to execute 32-bit userspace applications, say Y.

config SYSVIPC_COMPAT
	def_bool y
	depends on COMPAT && SYSVIPC

endmenu

menu "Power management options"

source "kernel/power/Kconfig"

config ARCH_SUSPEND_POSSIBLE
	def_bool y

config ARM64_CPU_SUSPEND
	def_bool PM_SLEEP

endmenu

menu "CPU Power Management"

source "drivers/cpuidle/Kconfig"

source "drivers/cpufreq/Kconfig"

config ARM64_ERRATUM_843419
	bool "Cortex-A53: 843419: A load or store might access an incorrect address"
	depends on MODULES
	default y
	help
	  This option builds kernel modules using the large memory model in
	  order to avoid the use of the ADRP instruction, which can cause
	  a subsequent memory access to use an incorrect address on Cortex-A53
	  parts up to r0p4.

	  Note that the kernel itself must be linked with a version of ld
	  which fixes potentially affected ADRP instructions through the
	  use of veneers.

	  If unsure, say Y.

endmenu

menu "Expermimental Security Enhancements"

config KUSER_HELPERS_SELECTIVE_DISABLE
	bool "Disable KUSER_HELPERS selectively"
	depends on ARM64
	help
	  Kuser_Helpers is a set of functions in the vector page at a fixed address that
	  are used to support applications compiled for legacy ARM <7.  These functions
	  being at a fixed address creates an ASLR bypass.

	  Do not enable this feature unless you know what you are doing, this is
	  experimental, and will break any application that uses the Kuser_Helpers or
	  registers a signal handler and uses the kernel trampolines.

	  If unsure, say N.

endmenu

source "net/Kconfig"

source "drivers/Kconfig"

source "drivers/firmware/Kconfig"

source "fs/Kconfig"

source "arch/arm64/kvm/Kconfig"

source "arch/arm64/Kconfig.htc"

source "arch/arm64/Kconfig.debug"

source "security/Kconfig"

source "crypto/Kconfig"
if CRYPTO
source "arch/arm64/crypto/Kconfig"
endif

source "lib/Kconfig"