drivers/misc/ipu/ipu-regs-v2-generated.h

/*
 * Register definitions for the Paintbox programmable IPU
 *
 * Copyright (C) 2017 Google, Inc.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

 /* This file is generated from RTL, do not hand edit. */
#ifndef __IPU_REGS_V2_GENERATED_H__
#define __IPU_REGS_V2_GENERATED_H__

/* Date created: Thu Dec  7 08:13:26 2017 */
/* Git commit: d596b54b8 */
/* Cfg: airbrush.cfg */

/* Register Group Offsets */
#define IPU_CSR_AON_OFFSET 0x0
#define IPU_CSR_JQS_OFFSET 0x800
#define IPU_CSR_APB_OFFSET 0x1000
#define IPU_CSR_AXI_OFFSET 0x1400
#define IPU_CSR_MIF_OFFSET 0x1800
#define IPU_CSR_DMA_TOP_OFFSET 0x1c00
#define IPU_CSR_DMA_GRP_OFFSET 0x2000
#define IPU_CSR_STP_OFFSET 0x2400
#define IPU_CSR_LBP_OFFSET 0x2800


/* Module : IPU_LIB_DREGFILE_AON*/
#define IPU_VERSION 0x0
#define IPU_VERSION_DEF 0x2000000
#define IPU_VERSION_MINOR_M 0xffULL
#define IPU_VERSION_MINOR_SHIFT 8
#define IPU_VERSION_MINOR_MASK (IPU_VERSION_MINOR_M << IPU_VERSION_MINOR_SHIFT)
#define IPU_VERSION_MAJOR_M 0xffULL
#define IPU_VERSION_MAJOR_SHIFT 24
#define IPU_VERSION_MAJOR_MASK (IPU_VERSION_MAJOR_M << IPU_VERSION_MAJOR_SHIFT)
#define IPU_VERSION_INCR_M 0xffULL
#define IPU_VERSION_INCR_SHIFT 0
#define IPU_VERSION_INCR_MASK (IPU_VERSION_INCR_M << IPU_VERSION_INCR_SHIFT)
#define IPU_VERSION_FPGA_BUILD_M 0x1ULL
#define IPU_VERSION_FPGA_BUILD_SHIFT 23
#define IPU_VERSION_FPGA_BUILD_MASK (IPU_VERSION_FPGA_BUILD_M << \
		IPU_VERSION_FPGA_BUILD_SHIFT)
#define IPU_CHECKSUM 0x8
#define IPU_CHECKSUM_DEF 0x9e34590d1020ef6fL
#define IPU_CHECKSUM_HIGH_M 0xffffffffULL
#define IPU_CHECKSUM_HIGH_SHIFT 32
#define IPU_CHECKSUM_HIGH_MASK (IPU_CHECKSUM_HIGH_M << IPU_CHECKSUM_HIGH_SHIFT)
#define IPU_CHECKSUM_LOW_M 0xffffffffULL
#define IPU_CHECKSUM_LOW_SHIFT 0
#define IPU_CHECKSUM_LOW_MASK (IPU_CHECKSUM_LOW_M << IPU_CHECKSUM_LOW_SHIFT)
#define IPU_CAP 0x10
#define IPU_CAP_DEF 0x20100e
#define IPU_CAP_NUM_LBP_M 0xffULL
#define IPU_CAP_NUM_LBP_SHIFT 8
#define IPU_CAP_NUM_LBP_MASK (IPU_CAP_NUM_LBP_M << IPU_CAP_NUM_LBP_SHIFT)
#define IPU_CAP_NUM_MPI_IFC_M 0xfULL
#define IPU_CAP_NUM_MPI_IFC_SHIFT 24
#define IPU_CAP_NUM_MPI_IFC_MASK (IPU_CAP_NUM_MPI_IFC_M << \
		IPU_CAP_NUM_MPI_IFC_SHIFT)
#define IPU_CAP_NUM_MPO_IFC_M 0xfULL
#define IPU_CAP_NUM_MPO_IFC_SHIFT 28
#define IPU_CAP_NUM_MPO_IFC_MASK (IPU_CAP_NUM_MPO_IFC_M << \
		IPU_CAP_NUM_MPO_IFC_SHIFT)
#define IPU_CAP_NUM_DMA_CHAN_M 0xffULL
#define IPU_CAP_NUM_DMA_CHAN_SHIFT 16
#define IPU_CAP_NUM_DMA_CHAN_MASK (IPU_CAP_NUM_DMA_CHAN_M << \
		IPU_CAP_NUM_DMA_CHAN_SHIFT)
#define IPU_CAP_MAX_MPI_STRM_M 0xffULL
#define IPU_CAP_MAX_MPI_STRM_SHIFT 32
#define IPU_CAP_MAX_MPI_STRM_MASK (IPU_CAP_MAX_MPI_STRM_M << \
		IPU_CAP_MAX_MPI_STRM_SHIFT)
#define IPU_CAP_MAX_MPO_STRM_M 0xffULL
#define IPU_CAP_MAX_MPO_STRM_SHIFT 40
#define IPU_CAP_MAX_MPO_STRM_MASK (IPU_CAP_MAX_MPO_STRM_M << \
		IPU_CAP_MAX_MPO_STRM_SHIFT)
#define IPU_CAP_NUM_STP_M 0xffULL
#define IPU_CAP_NUM_STP_SHIFT 0
#define IPU_CAP_NUM_STP_MASK (IPU_CAP_NUM_STP_M << IPU_CAP_NUM_STP_SHIFT)
#define CLK_GATE_CONTROL_STP_IDLE_GATE_DIS 0x18
#define CLK_GATE_CONTROL_STP_IDLE_GATE_DIS_DEF 0x3fff
#define CLK_GATE_CONTROL_STP_IDLE_GATE_DIS_VAL_M 0x3fffULL
#define CLK_GATE_CONTROL_STP_IDLE_GATE_DIS_VAL_SHIFT 0
#define CLK_GATE_CONTROL_STP_IDLE_GATE_DIS_VAL_MASK \
		(CLK_GATE_CONTROL_STP_IDLE_GATE_DIS_VAL_M << \
		CLK_GATE_CONTROL_STP_IDLE_GATE_DIS_VAL_SHIFT)
#define CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS 0x20
#define CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS_DEF 0xffff
#define CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS_VAL_M 0xffffULL
#define CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS_VAL_SHIFT 0
#define CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS_VAL_MASK \
		(CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS_VAL_M << \
		CLK_GATE_CONTROL_LBP_IDLE_GATE_DIS_VAL_SHIFT)
#define CLK_GATE_CONTROL 0x28
#define CLK_GATE_CONTROL_DEF 0xf
#define CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_M 0x1ULL
#define CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_SHIFT 3
#define CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_MASK \
		(CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_M << \
		CLK_GATE_CONTROL_SSP_IDLE_GATE_DIS_SHIFT)
#define CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_M 0x1ULL
#define CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_SHIFT 2
#define CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_MASK \
		(CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_M << \
		CLK_GATE_CONTROL_BIF_IDLE_GATE_DIS_SHIFT)
#define CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_M 0x1ULL
#define CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_SHIFT 1
#define CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_MASK \
		(CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_M << \
		CLK_GATE_CONTROL_MMU_IDLE_GATE_DIS_SHIFT)
#define CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_M 0x1ULL
#define CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_SHIFT 0
#define CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_MASK \
		(CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_M << \
		CLK_GATE_CONTROL_DMA_IDLE_GATE_DIS_SHIFT)
#define IDLE_CLK_COUNT 0x30
#define IDLE_CLK_COUNT_DEF 0xf0f000f0f0f0f
#define IDLE_CLK_COUNT_STP_COUNT_M 0x3fULL
#define IDLE_CLK_COUNT_STP_COUNT_SHIFT 48
#define IDLE_CLK_COUNT_STP_COUNT_MASK (IDLE_CLK_COUNT_STP_COUNT_M << \
		IDLE_CLK_COUNT_STP_COUNT_SHIFT)
#define IDLE_CLK_COUNT_DMA_COUNT_M 0x3fULL
#define IDLE_CLK_COUNT_DMA_COUNT_SHIFT 0
#define IDLE_CLK_COUNT_DMA_COUNT_MASK (IDLE_CLK_COUNT_DMA_COUNT_M << \
		IDLE_CLK_COUNT_DMA_COUNT_SHIFT)
#define IDLE_CLK_COUNT_BIF_COUNT_M 0x3fULL
#define IDLE_CLK_COUNT_BIF_COUNT_SHIFT 16
#define IDLE_CLK_COUNT_BIF_COUNT_MASK (IDLE_CLK_COUNT_BIF_COUNT_M << \
		IDLE_CLK_COUNT_BIF_COUNT_SHIFT)
#define IDLE_CLK_COUNT_LBP_COUNT_M 0x3fULL
#define IDLE_CLK_COUNT_LBP_COUNT_SHIFT 40
#define IDLE_CLK_COUNT_LBP_COUNT_MASK (IDLE_CLK_COUNT_LBP_COUNT_M << \
		IDLE_CLK_COUNT_LBP_COUNT_SHIFT)
#define IDLE_CLK_COUNT_MMU_COUNT_M 0x3fULL
#define IDLE_CLK_COUNT_MMU_COUNT_SHIFT 8
#define IDLE_CLK_COUNT_MMU_COUNT_MASK (IDLE_CLK_COUNT_MMU_COUNT_M << \
		IDLE_CLK_COUNT_MMU_COUNT_SHIFT)
#define IDLE_CLK_COUNT_SSP_COUNT_M 0x3fULL
#define IDLE_CLK_COUNT_SSP_COUNT_SHIFT 24
#define IDLE_CLK_COUNT_SSP_COUNT_MASK (IDLE_CLK_COUNT_SSP_COUNT_M << \
		IDLE_CLK_COUNT_SSP_COUNT_SHIFT)
#define IPU_IO_SWITCHED_CLK_EN 0x38
#define IPU_IO_SWITCHED_CLK_EN_DEF 0x0
#define IPU_IO_SWITCHED_CLK_EN_VAL_M 0x1ULL
#define IPU_IO_SWITCHED_CLK_EN_VAL_SHIFT 0
#define IPU_IO_SWITCHED_CLK_EN_VAL_MASK (IPU_IO_SWITCHED_CLK_EN_VAL_M << \
		IPU_IO_SWITCHED_CLK_EN_VAL_SHIFT)
#define IPU_CORE_PAIRS_EN 0x40
#define IPU_CORE_PAIRS_EN_DEF 0x0
#define IPU_CORE_PAIRS_EN_SECONDARY_M 0x7ULL
#define IPU_CORE_PAIRS_EN_SECONDARY_SHIFT 8
#define IPU_CORE_PAIRS_EN_SECONDARY_MASK (IPU_CORE_PAIRS_EN_SECONDARY_M << \
		IPU_CORE_PAIRS_EN_SECONDARY_SHIFT)
#define IPU_CORE_PAIRS_EN_PRIMARY_M 0x7ULL
#define IPU_CORE_PAIRS_EN_PRIMARY_SHIFT 0
#define IPU_CORE_PAIRS_EN_PRIMARY_MASK (IPU_CORE_PAIRS_EN_PRIMARY_M << \
		IPU_CORE_PAIRS_EN_PRIMARY_SHIFT)
#define IPU_DMA_CHAN_EN 0x48
#define IPU_DMA_CHAN_EN_DEF 0x0
#define IPU_DMA_CHAN_EN_VAL_M 0xffffffffULL
#define IPU_DMA_CHAN_EN_VAL_SHIFT 0
#define IPU_DMA_CHAN_EN_VAL_MASK (IPU_DMA_CHAN_EN_VAL_M << \
		IPU_DMA_CHAN_EN_VAL_SHIFT)
#define CORE_POWER_ON_N 0x50
#define CORE_POWER_ON_N_DEF 0x3fff00003fff
#define CORE_POWER_ON_N_MAIN_M 0x3fffULL
#define CORE_POWER_ON_N_MAIN_SHIFT 0
#define CORE_POWER_ON_N_MAIN_MASK (CORE_POWER_ON_N_MAIN_M << \
		CORE_POWER_ON_N_MAIN_SHIFT)
#define CORE_POWER_ON_N_PRE_M 0x3fffULL
#define CORE_POWER_ON_N_PRE_SHIFT 32
#define CORE_POWER_ON_N_PRE_MASK (CORE_POWER_ON_N_PRE_M << \
		CORE_POWER_ON_N_PRE_SHIFT)
#define CORE_ISO_ON 0x58
#define CORE_ISO_ON_DEF 0x3fff
#define CORE_ISO_ON_VAL_M 0x3fffULL
#define CORE_ISO_ON_VAL_SHIFT 0
#define CORE_ISO_ON_VAL_MASK (CORE_ISO_ON_VAL_M << CORE_ISO_ON_VAL_SHIFT)
#define CORE_RAM_ON_N 0x60
#define CORE_RAM_ON_N_DEF 0x3fff
#define CORE_RAM_ON_N_VAL_M 0x3fffULL
#define CORE_RAM_ON_N_VAL_SHIFT 0
#define CORE_RAM_ON_N_VAL_MASK (CORE_RAM_ON_N_VAL_M << CORE_RAM_ON_N_VAL_SHIFT)
#define IO_POWER_ON_N 0x68
#define IO_POWER_ON_N_DEF 0x100000001
#define IO_POWER_ON_N_PRE_M 0x1ULL
#define IO_POWER_ON_N_PRE_SHIFT 32
#define IO_POWER_ON_N_PRE_MASK (IO_POWER_ON_N_PRE_M << IO_POWER_ON_N_PRE_SHIFT)
#define IO_POWER_ON_N_MAIN_M 0x1ULL
#define IO_POWER_ON_N_MAIN_SHIFT 0
#define IO_POWER_ON_N_MAIN_MASK (IO_POWER_ON_N_MAIN_M << \
		IO_POWER_ON_N_MAIN_SHIFT)
#define IO_ISO_ON 0x70
#define IO_ISO_ON_DEF 0x1
#define IO_ISO_ON_VAL_M 0x1ULL
#define IO_ISO_ON_VAL_SHIFT 0
#define IO_ISO_ON_VAL_MASK (IO_ISO_ON_VAL_M << IO_ISO_ON_VAL_SHIFT)
#define IO_RAM_ON_N 0x78
#define IO_RAM_ON_N_DEF 0x1
#define IO_RAM_ON_N_VAL_M 0x1ULL
#define IO_RAM_ON_N_VAL_SHIFT 0
#define IO_RAM_ON_N_VAL_MASK (IO_RAM_ON_N_VAL_M << IO_RAM_ON_N_VAL_SHIFT)
#define SOFT_RESET 0x80
#define SOFT_RESET_DEF 0x0
#define SOFT_RESET_IPU_M 0x1ULL
#define SOFT_RESET_IPU_SHIFT 0
#define SOFT_RESET_IPU_MASK (SOFT_RESET_IPU_M << SOFT_RESET_IPU_SHIFT)
#define JQS_BOOT_ADDR 0x88
#define JQS_BOOT_ADDR_DEF 0x48040000
#define JQS_BOOT_ADDR_VAL_M 0xffffffffULL
#define JQS_BOOT_ADDR_VAL_SHIFT 0
#define JQS_BOOT_ADDR_VAL_MASK (JQS_BOOT_ADDR_VAL_M << JQS_BOOT_ADDR_VAL_SHIFT)
#define JQS_CONTROL 0x90
#define JQS_CONTROL_DEF 0x0
#define JQS_CONTROL_CORE_FETCH_EN_M 0x1ULL
#define JQS_CONTROL_CORE_FETCH_EN_SHIFT 0
#define JQS_CONTROL_CORE_FETCH_EN_MASK (JQS_CONTROL_CORE_FETCH_EN_M << \
		JQS_CONTROL_CORE_FETCH_EN_SHIFT)
#define JQS_WATCHDOG_CMP_INIT 0x98
#define JQS_WATCHDOG_CMP_INIT_DEF 0x1cb0a21
#define JQS_WATCHDOG_CMP_INIT_VAL_M 0xffffffffULL
#define JQS_WATCHDOG_CMP_INIT_VAL_SHIFT 0
#define JQS_WATCHDOG_CMP_INIT_VAL_MASK (JQS_WATCHDOG_CMP_INIT_VAL_M << \
		JQS_WATCHDOG_CMP_INIT_VAL_SHIFT)
#define JQS_CACHE_ENABLE 0xa0
#define JQS_CACHE_ENABLE_DEF 0x0
#define JQS_CACHE_ENABLE_I_CACHE_M 0x1ULL
#define JQS_CACHE_ENABLE_I_CACHE_SHIFT 0
#define JQS_CACHE_ENABLE_I_CACHE_MASK (JQS_CACHE_ENABLE_I_CACHE_M << \
		JQS_CACHE_ENABLE_I_CACHE_SHIFT)
#define JQS_CACHE_ENABLE_D_CACHE_M 0x1ULL
#define JQS_CACHE_ENABLE_D_CACHE_SHIFT 1
#define JQS_CACHE_ENABLE_D_CACHE_MASK (JQS_CACHE_ENABLE_D_CACHE_M << \
		JQS_CACHE_ENABLE_D_CACHE_SHIFT)
#define JQS_CACHE_END_ADDR_MSB 0xa8
#define JQS_CACHE_END_ADDR_MSB_DEF 0x3f3f
#define JQS_CACHE_END_ADDR_MSB_D_CACHE_M 0xffULL
#define JQS_CACHE_END_ADDR_MSB_D_CACHE_SHIFT 8
#define JQS_CACHE_END_ADDR_MSB_D_CACHE_MASK \
		(JQS_CACHE_END_ADDR_MSB_D_CACHE_M << \
		JQS_CACHE_END_ADDR_MSB_D_CACHE_SHIFT)
#define JQS_CACHE_END_ADDR_MSB_I_CACHE_M 0xffULL
#define JQS_CACHE_END_ADDR_MSB_I_CACHE_SHIFT 0
#define JQS_CACHE_END_ADDR_MSB_I_CACHE_MASK \
		(JQS_CACHE_END_ADDR_MSB_I_CACHE_M << \
		JQS_CACHE_END_ADDR_MSB_I_CACHE_SHIFT)
#define JQS_I_CACHE_CTRL 0xb0
#define JQS_I_CACHE_CTRL_DEF 0x0
#define JQS_I_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_M 0x1ULL
#define JQS_I_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_SHIFT 0
#define JQS_I_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_MASK \
		(JQS_I_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_M << \
		JQS_I_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_SHIFT)
#define JQS_I_CACHE_CTRL_FLUSH_FENCE_STRICT_M 0x1ULL
#define JQS_I_CACHE_CTRL_FLUSH_FENCE_STRICT_SHIFT 1
#define JQS_I_CACHE_CTRL_FLUSH_FENCE_STRICT_MASK \
		(JQS_I_CACHE_CTRL_FLUSH_FENCE_STRICT_M << \
		JQS_I_CACHE_CTRL_FLUSH_FENCE_STRICT_SHIFT)
#define JQS_D_CACHE_CTRL 0xb8
#define JQS_D_CACHE_CTRL_DEF 0x0
#define JQS_D_CACHE_CTRL_FLUSH_FENCE_STRICT_M 0x1ULL
#define JQS_D_CACHE_CTRL_FLUSH_FENCE_STRICT_SHIFT 1
#define JQS_D_CACHE_CTRL_FLUSH_FENCE_STRICT_MASK \
		(JQS_D_CACHE_CTRL_FLUSH_FENCE_STRICT_M << \
		JQS_D_CACHE_CTRL_FLUSH_FENCE_STRICT_SHIFT)
#define JQS_D_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_M 0x1ULL
#define JQS_D_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_SHIFT 0
#define JQS_D_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_MASK \
		(JQS_D_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_M << \
		JQS_D_CACHE_CTRL_STALL_MISS_WHEN_PREF_ACTIVE_N_SHIFT)
#define IPU_STATUS 0xc0
#define IPU_STATUS_DEF 0x0
#define IPU_STATUS_BIF_RST_DONE_M 0x1ULL
#define IPU_STATUS_BIF_RST_DONE_SHIFT 0
#define IPU_STATUS_BIF_RST_DONE_MASK (IPU_STATUS_BIF_RST_DONE_M << \
		IPU_STATUS_BIF_RST_DONE_SHIFT)
#define AON_SPARE 0xc8
#define AON_SPARE_DEF 0x0
#define AON_SPARE_SPARE15_M 0x1ULL
#define AON_SPARE_SPARE15_SHIFT 15
#define AON_SPARE_SPARE15_MASK (AON_SPARE_SPARE15_M << AON_SPARE_SPARE15_SHIFT)
#define AON_SPARE_SPARE11_M 0x1ULL
#define AON_SPARE_SPARE11_SHIFT 11
#define AON_SPARE_SPARE11_MASK (AON_SPARE_SPARE11_M << AON_SPARE_SPARE11_SHIFT)
#define AON_SPARE_SPARE12_M 0x1ULL
#define AON_SPARE_SPARE12_SHIFT 12
#define AON_SPARE_SPARE12_MASK (AON_SPARE_SPARE12_M << AON_SPARE_SPARE12_SHIFT)
#define AON_SPARE_SPARE14_M 0x1ULL
#define AON_SPARE_SPARE14_SHIFT 14
#define AON_SPARE_SPARE14_MASK (AON_SPARE_SPARE14_M << AON_SPARE_SPARE14_SHIFT)
#define AON_SPARE_SPARE13_M 0x1ULL
#define AON_SPARE_SPARE13_SHIFT 13
#define AON_SPARE_SPARE13_MASK (AON_SPARE_SPARE13_M << AON_SPARE_SPARE13_SHIFT)
#define AON_SPARE_SPARE8_M 0x1ULL
#define AON_SPARE_SPARE8_SHIFT 8
#define AON_SPARE_SPARE8_MASK (AON_SPARE_SPARE8_M << AON_SPARE_SPARE8_SHIFT)
#define AON_SPARE_SPARE9_M 0x1ULL
#define AON_SPARE_SPARE9_SHIFT 9
#define AON_SPARE_SPARE9_MASK (AON_SPARE_SPARE9_M << AON_SPARE_SPARE9_SHIFT)
#define AON_SPARE_SPARE10_M 0x1ULL
#define AON_SPARE_SPARE10_SHIFT 10
#define AON_SPARE_SPARE10_MASK (AON_SPARE_SPARE10_M << AON_SPARE_SPARE10_SHIFT)
#define AON_SPARE_SPARE4_M 0x1ULL
#define AON_SPARE_SPARE4_SHIFT 4
#define AON_SPARE_SPARE4_MASK (AON_SPARE_SPARE4_M << AON_SPARE_SPARE4_SHIFT)
#define AON_SPARE_SPARE5_M 0x1ULL
#define AON_SPARE_SPARE5_SHIFT 5
#define AON_SPARE_SPARE5_MASK (AON_SPARE_SPARE5_M << AON_SPARE_SPARE5_SHIFT)
#define AON_SPARE_SPARE6_M 0x1ULL
#define AON_SPARE_SPARE6_SHIFT 6
#define AON_SPARE_SPARE6_MASK (AON_SPARE_SPARE6_M << AON_SPARE_SPARE6_SHIFT)
#define AON_SPARE_SPARE7_M 0x1ULL
#define AON_SPARE_SPARE7_SHIFT 7
#define AON_SPARE_SPARE7_MASK (AON_SPARE_SPARE7_M << AON_SPARE_SPARE7_SHIFT)
#define AON_SPARE_SPARE0_M 0x1ULL
#define AON_SPARE_SPARE0_SHIFT 0
#define AON_SPARE_SPARE0_MASK (AON_SPARE_SPARE0_M << AON_SPARE_SPARE0_SHIFT)
#define AON_SPARE_SPARE1_M 0x1ULL
#define AON_SPARE_SPARE1_SHIFT 1
#define AON_SPARE_SPARE1_MASK (AON_SPARE_SPARE1_M << AON_SPARE_SPARE1_SHIFT)
#define AON_SPARE_SPARE2_M 0x1ULL
#define AON_SPARE_SPARE2_SHIFT 2
#define AON_SPARE_SPARE2_MASK (AON_SPARE_SPARE2_M << AON_SPARE_SPARE2_SHIFT)
#define AON_SPARE_SPARE3_M 0x1ULL
#define AON_SPARE_SPARE3_SHIFT 3
#define AON_SPARE_SPARE3_MASK (AON_SPARE_SPARE3_M << AON_SPARE_SPARE3_SHIFT)

/* Module : IPU_LIB_DREGFILE_AXI*/
#define MMU_CTRL 0x0
#define MMU_CTRL_DEF 0x0
#define MMU_CTRL_SOFT_RST_M 0x1ULL
#define MMU_CTRL_SOFT_RST_SHIFT 4
#define MMU_CTRL_SOFT_RST_MASK (MMU_CTRL_SOFT_RST_M << MMU_CTRL_SOFT_RST_SHIFT)
#define MMU_CTRL_SINGLE_TWE_M 0x1ULL
#define MMU_CTRL_SINGLE_TWE_SHIFT 0
#define MMU_CTRL_SINGLE_TWE_MASK (MMU_CTRL_SINGLE_TWE_M << \
		MMU_CTRL_SINGLE_TWE_SHIFT)
#define MMU_ENABLE_CTRL 0x8
#define MMU_ENABLE_CTRL_DEF 0x0
#define MMU_ENABLE_CTRL_MMU_ENABLE_M 0x1ffffffffULL
#define MMU_ENABLE_CTRL_MMU_ENABLE_SHIFT 0
#define MMU_ENABLE_CTRL_MMU_ENABLE_MASK (MMU_ENABLE_CTRL_MMU_ENABLE_M << \
		MMU_ENABLE_CTRL_MMU_ENABLE_SHIFT)
#define MMU_PREFETCH_CTRL 0x10
#define MMU_PREFETCH_CTRL_DEF 0x1ffffffff
#define MMU_PREFETCH_CTRL_PREFETCH_ENABLE_M 0x1ffffffffULL
#define MMU_PREFETCH_CTRL_PREFETCH_ENABLE_SHIFT 0
#define MMU_PREFETCH_CTRL_PREFETCH_ENABLE_MASK \
		(MMU_PREFETCH_CTRL_PREFETCH_ENABLE_M << \
		MMU_PREFETCH_CTRL_PREFETCH_ENABLE_SHIFT)
#define MMU_TABLE_BASE 0x18
#define MMU_TABLE_BASE_DEF 0x0
#define MMU_TABLE_BASE_ADDR_M 0x3ffffULL
#define MMU_TABLE_BASE_ADDR_SHIFT 4
#define MMU_TABLE_BASE_ADDR_MASK (MMU_TABLE_BASE_ADDR_M << \
		MMU_TABLE_BASE_ADDR_SHIFT)
#define MMU_ERR_BASE 0x20
#define MMU_ERR_BASE_DEF 0x0
#define MMU_ERR_BASE_ADDR_M 0x3fffffULL
#define MMU_ERR_BASE_ADDR_SHIFT 0
#define MMU_ERR_BASE_ADDR_MASK (MMU_ERR_BASE_ADDR_M << MMU_ERR_BASE_ADDR_SHIFT)
#define MMU_SYNC 0x28
#define MMU_SYNC_DEF 0x0
#define MMU_SYNC_SYNC_M 0x1ULL
#define MMU_SYNC_SYNC_SHIFT 0
#define MMU_SYNC_SYNC_MASK (MMU_SYNC_SYNC_M << MMU_SYNC_SYNC_SHIFT)
#define MMU_FLUSH_CHANNEL 0x30
#define MMU_FLUSH_CHANNEL_DEF 0x0
#define MMU_FLUSH_CHANNEL_VAL_M 0x3fULL
#define MMU_FLUSH_CHANNEL_VAL_SHIFT 0
#define MMU_FLUSH_CHANNEL_VAL_MASK (MMU_FLUSH_CHANNEL_VAL_M << \
		MMU_FLUSH_CHANNEL_VAL_SHIFT)
#define MMU_FLUSH_CHANNEL_ALL_CHAN_M 0x1ULL
#define MMU_FLUSH_CHANNEL_ALL_CHAN_SHIFT 6
#define MMU_FLUSH_CHANNEL_ALL_CHAN_MASK (MMU_FLUSH_CHANNEL_ALL_CHAN_M << \
		MMU_FLUSH_CHANNEL_ALL_CHAN_SHIFT)
#define MMU_FLUSH_ADDRESS 0x38
#define MMU_FLUSH_ADDRESS_DEF 0x0
#define MMU_FLUSH_ADDRESS_VAL_M 0x7fffffffULL
#define MMU_FLUSH_ADDRESS_VAL_SHIFT 0
#define MMU_FLUSH_ADDRESS_VAL_MASK (MMU_FLUSH_ADDRESS_VAL_M << \
		MMU_FLUSH_ADDRESS_VAL_SHIFT)
#define MMU_FLUSH_FIFO_STATUS 0x40
#define MMU_FLUSH_FIFO_STATUS_DEF 0x0
#define MMU_FLUSH_FIFO_STATUS_FULL_M 0x1ULL
#define MMU_FLUSH_FIFO_STATUS_FULL_SHIFT 8
#define MMU_FLUSH_FIFO_STATUS_FULL_MASK (MMU_FLUSH_FIFO_STATUS_FULL_M << \
		MMU_FLUSH_FIFO_STATUS_FULL_SHIFT)
#define MMU_FLUSH_FIFO_STATUS_LEVEL_M 0x7ULL
#define MMU_FLUSH_FIFO_STATUS_LEVEL_SHIFT 0
#define MMU_FLUSH_FIFO_STATUS_LEVEL_MASK (MMU_FLUSH_FIFO_STATUS_LEVEL_M << \
		MMU_FLUSH_FIFO_STATUS_LEVEL_SHIFT)
#define MMU_ISR 0x48
#define MMU_ISR_DEF 0x0
#define MMU_ISR_FLUSH_MEMRD_ERR_M 0x1ULL
#define MMU_ISR_FLUSH_MEMRD_ERR_SHIFT 4
#define MMU_ISR_FLUSH_MEMRD_ERR_MASK (MMU_ISR_FLUSH_MEMRD_ERR_M << \
		MMU_ISR_FLUSH_MEMRD_ERR_SHIFT)
#define MMU_ISR_TWE_MEMRD_ERR_M 0x1ULL
#define MMU_ISR_TWE_MEMRD_ERR_SHIFT 2
#define MMU_ISR_TWE_MEMRD_ERR_MASK (MMU_ISR_TWE_MEMRD_ERR_M << \
		MMU_ISR_TWE_MEMRD_ERR_SHIFT)
#define MMU_ISR_FLUSH_FULL_ERR_M 0x1ULL
#define MMU_ISR_FLUSH_FULL_ERR_SHIFT 6
#define MMU_ISR_FLUSH_FULL_ERR_MASK (MMU_ISR_FLUSH_FULL_ERR_M << \
		MMU_ISR_FLUSH_FULL_ERR_SHIFT)
#define MMU_ISR_TWE_ACCESS_VIO_M 0x1ULL
#define MMU_ISR_TWE_ACCESS_VIO_SHIFT 0
#define MMU_ISR_TWE_ACCESS_VIO_MASK (MMU_ISR_TWE_ACCESS_VIO_M << \
		MMU_ISR_TWE_ACCESS_VIO_SHIFT)
#define MMU_ISR_PREFETCH_MEMRD_ERR_M 0x1ULL
#define MMU_ISR_PREFETCH_MEMRD_ERR_SHIFT 5
#define MMU_ISR_PREFETCH_MEMRD_ERR_MASK (MMU_ISR_PREFETCH_MEMRD_ERR_M << \
		MMU_ISR_PREFETCH_MEMRD_ERR_SHIFT)
#define MMU_ISR_TWE_INVALID_TABLE_M 0x1ULL
#define MMU_ISR_TWE_INVALID_TABLE_SHIFT 1
#define MMU_ISR_TWE_INVALID_TABLE_MASK (MMU_ISR_TWE_INVALID_TABLE_M << \
		MMU_ISR_TWE_INVALID_TABLE_SHIFT)
#define MMU_ISR_FLUSH_INVALID_TABLE_M 0x1ULL
#define MMU_ISR_FLUSH_INVALID_TABLE_SHIFT 3
#define MMU_ISR_FLUSH_INVALID_TABLE_MASK (MMU_ISR_FLUSH_INVALID_TABLE_M << \
		MMU_ISR_FLUSH_INVALID_TABLE_SHIFT)
#define MMU_ITR 0x50
#define MMU_ITR_DEF 0x0
#define MMU_ITR_TWE_ACCESS_VIO_M 0x1ULL
#define MMU_ITR_TWE_ACCESS_VIO_SHIFT 0
#define MMU_ITR_TWE_ACCESS_VIO_MASK (MMU_ITR_TWE_ACCESS_VIO_M << \
		MMU_ITR_TWE_ACCESS_VIO_SHIFT)
#define MMU_ITR_FLUSH_INVALID_TABLE_M 0x1ULL
#define MMU_ITR_FLUSH_INVALID_TABLE_SHIFT 3
#define MMU_ITR_FLUSH_INVALID_TABLE_MASK (MMU_ITR_FLUSH_INVALID_TABLE_M << \
		MMU_ITR_FLUSH_INVALID_TABLE_SHIFT)
#define MMU_ITR_TWE_MEMRD_ERR_M 0x1ULL
#define MMU_ITR_TWE_MEMRD_ERR_SHIFT 2
#define MMU_ITR_TWE_MEMRD_ERR_MASK (MMU_ITR_TWE_MEMRD_ERR_M << \
		MMU_ITR_TWE_MEMRD_ERR_SHIFT)
#define MMU_ITR_FLUSH_FULL_ERR_M 0x1ULL
#define MMU_ITR_FLUSH_FULL_ERR_SHIFT 6
#define MMU_ITR_FLUSH_FULL_ERR_MASK (MMU_ITR_FLUSH_FULL_ERR_M << \
		MMU_ITR_FLUSH_FULL_ERR_SHIFT)
#define MMU_ITR_PREFETCH_MEMRD_ERR_M 0x1ULL
#define MMU_ITR_PREFETCH_MEMRD_ERR_SHIFT 5
#define MMU_ITR_PREFETCH_MEMRD_ERR_MASK (MMU_ITR_PREFETCH_MEMRD_ERR_M << \
		MMU_ITR_PREFETCH_MEMRD_ERR_SHIFT)
#define MMU_ITR_FLUSH_MEMRD_ERR_M 0x1ULL
#define MMU_ITR_FLUSH_MEMRD_ERR_SHIFT 4
#define MMU_ITR_FLUSH_MEMRD_ERR_MASK (MMU_ITR_FLUSH_MEMRD_ERR_M << \
		MMU_ITR_FLUSH_MEMRD_ERR_SHIFT)
#define MMU_ITR_TWE_INVALID_TABLE_M 0x1ULL
#define MMU_ITR_TWE_INVALID_TABLE_SHIFT 1
#define MMU_ITR_TWE_INVALID_TABLE_MASK (MMU_ITR_TWE_INVALID_TABLE_M << \
		MMU_ITR_TWE_INVALID_TABLE_SHIFT)
#define MMU_IER 0x58
#define MMU_IER_DEF 0x7f
#define MMU_IER_TWE_INVALID_TABLE_M 0x1ULL
#define MMU_IER_TWE_INVALID_TABLE_SHIFT 1
#define MMU_IER_TWE_INVALID_TABLE_MASK (MMU_IER_TWE_INVALID_TABLE_M << \
		MMU_IER_TWE_INVALID_TABLE_SHIFT)
#define MMU_IER_FLUSH_FULL_ERR_M 0x1ULL
#define MMU_IER_FLUSH_FULL_ERR_SHIFT 6
#define MMU_IER_FLUSH_FULL_ERR_MASK (MMU_IER_FLUSH_FULL_ERR_M << \
		MMU_IER_FLUSH_FULL_ERR_SHIFT)
#define MMU_IER_TWE_MEMRD_ERR_M 0x1ULL
#define MMU_IER_TWE_MEMRD_ERR_SHIFT 2
#define MMU_IER_TWE_MEMRD_ERR_MASK (MMU_IER_TWE_MEMRD_ERR_M << \
		MMU_IER_TWE_MEMRD_ERR_SHIFT)
#define MMU_IER_TWE_ACCESS_VIO_M 0x1ULL
#define MMU_IER_TWE_ACCESS_VIO_SHIFT 0
#define MMU_IER_TWE_ACCESS_VIO_MASK (MMU_IER_TWE_ACCESS_VIO_M << \
		MMU_IER_TWE_ACCESS_VIO_SHIFT)
#define MMU_IER_FLUSH_MEMRD_ERR_M 0x1ULL
#define MMU_IER_FLUSH_MEMRD_ERR_SHIFT 4
#define MMU_IER_FLUSH_MEMRD_ERR_MASK (MMU_IER_FLUSH_MEMRD_ERR_M << \
		MMU_IER_FLUSH_MEMRD_ERR_SHIFT)
#define MMU_IER_FLUSH_INVALID_TABLE_M 0x1ULL
#define MMU_IER_FLUSH_INVALID_TABLE_SHIFT 3
#define MMU_IER_FLUSH_INVALID_TABLE_MASK (MMU_IER_FLUSH_INVALID_TABLE_M << \
		MMU_IER_FLUSH_INVALID_TABLE_SHIFT)
#define MMU_IER_PREFETCH_MEMRD_ERR_M 0x1ULL
#define MMU_IER_PREFETCH_MEMRD_ERR_SHIFT 5
#define MMU_IER_PREFETCH_MEMRD_ERR_MASK (MMU_IER_PREFETCH_MEMRD_ERR_M << \
		MMU_IER_PREFETCH_MEMRD_ERR_SHIFT)
#define MMU_IMR 0x60
#define MMU_IMR_DEF 0x0
#define MMU_IMR_PREFETCH_MEMRD_ERR_M 0x1ULL
#define MMU_IMR_PREFETCH_MEMRD_ERR_SHIFT 5
#define MMU_IMR_PREFETCH_MEMRD_ERR_MASK (MMU_IMR_PREFETCH_MEMRD_ERR_M << \
		MMU_IMR_PREFETCH_MEMRD_ERR_SHIFT)
#define MMU_IMR_TWE_ACCESS_VIO_M 0x1ULL
#define MMU_IMR_TWE_ACCESS_VIO_SHIFT 0
#define MMU_IMR_TWE_ACCESS_VIO_MASK (MMU_IMR_TWE_ACCESS_VIO_M << \
		MMU_IMR_TWE_ACCESS_VIO_SHIFT)
#define MMU_IMR_TWE_MEMRD_ERR_M 0x1ULL
#define MMU_IMR_TWE_MEMRD_ERR_SHIFT 2
#define MMU_IMR_TWE_MEMRD_ERR_MASK (MMU_IMR_TWE_MEMRD_ERR_M << \
		MMU_IMR_TWE_MEMRD_ERR_SHIFT)
#define MMU_IMR_FLUSH_MEMRD_ERR_M 0x1ULL
#define MMU_IMR_FLUSH_MEMRD_ERR_SHIFT 4
#define MMU_IMR_FLUSH_MEMRD_ERR_MASK (MMU_IMR_FLUSH_MEMRD_ERR_M << \
		MMU_IMR_FLUSH_MEMRD_ERR_SHIFT)
#define MMU_IMR_TWE_INVALID_TABLE_M 0x1ULL
#define MMU_IMR_TWE_INVALID_TABLE_SHIFT 1
#define MMU_IMR_TWE_INVALID_TABLE_MASK (MMU_IMR_TWE_INVALID_TABLE_M << \
		MMU_IMR_TWE_INVALID_TABLE_SHIFT)
#define MMU_IMR_FLUSH_FULL_ERR_M 0x1ULL
#define MMU_IMR_FLUSH_FULL_ERR_SHIFT 6
#define MMU_IMR_FLUSH_FULL_ERR_MASK (MMU_IMR_FLUSH_FULL_ERR_M << \
		MMU_IMR_FLUSH_FULL_ERR_SHIFT)
#define MMU_IMR_FLUSH_INVALID_TABLE_M 0x1ULL
#define MMU_IMR_FLUSH_INVALID_TABLE_SHIFT 3
#define MMU_IMR_FLUSH_INVALID_TABLE_MASK (MMU_IMR_FLUSH_INVALID_TABLE_M << \
		MMU_IMR_FLUSH_INVALID_TABLE_SHIFT)
#define MMU_ISR_OVF 0x68
#define MMU_ISR_OVF_DEF 0x0
#define MMU_ISR_OVF_FLUSH_MEMRD_ERR_M 0x1ULL
#define MMU_ISR_OVF_FLUSH_MEMRD_ERR_SHIFT 4
#define MMU_ISR_OVF_FLUSH_MEMRD_ERR_MASK (MMU_ISR_OVF_FLUSH_MEMRD_ERR_M << \
		MMU_ISR_OVF_FLUSH_MEMRD_ERR_SHIFT)
#define MMU_ISR_OVF_TWE_INVALID_TABLE_M 0x1ULL
#define MMU_ISR_OVF_TWE_INVALID_TABLE_SHIFT 1
#define MMU_ISR_OVF_TWE_INVALID_TABLE_MASK (MMU_ISR_OVF_TWE_INVALID_TABLE_M << \
		MMU_ISR_OVF_TWE_INVALID_TABLE_SHIFT)
#define MMU_ISR_OVF_TWE_MEMRD_ERR_M 0x1ULL
#define MMU_ISR_OVF_TWE_MEMRD_ERR_SHIFT 2
#define MMU_ISR_OVF_TWE_MEMRD_ERR_MASK (MMU_ISR_OVF_TWE_MEMRD_ERR_M << \
		MMU_ISR_OVF_TWE_MEMRD_ERR_SHIFT)
#define MMU_ISR_OVF_TWE_ACCESS_VIO_M 0x1ULL
#define MMU_ISR_OVF_TWE_ACCESS_VIO_SHIFT 0
#define MMU_ISR_OVF_TWE_ACCESS_VIO_MASK (MMU_ISR_OVF_TWE_ACCESS_VIO_M << \
		MMU_ISR_OVF_TWE_ACCESS_VIO_SHIFT)
#define MMU_ISR_OVF_FLUSH_FULL_ERR_M 0x1ULL
#define MMU_ISR_OVF_FLUSH_FULL_ERR_SHIFT 6
#define MMU_ISR_OVF_FLUSH_FULL_ERR_MASK (MMU_ISR_OVF_FLUSH_FULL_ERR_M << \
		MMU_ISR_OVF_FLUSH_FULL_ERR_SHIFT)
#define MMU_ISR_OVF_PREFETCH_MEMRD_ERR_M 0x1ULL
#define MMU_ISR_OVF_PREFETCH_MEMRD_ERR_SHIFT 5
#define MMU_ISR_OVF_PREFETCH_MEMRD_ERR_MASK \
		(MMU_ISR_OVF_PREFETCH_MEMRD_ERR_M << \
		MMU_ISR_OVF_PREFETCH_MEMRD_ERR_SHIFT)
#define MMU_ISR_OVF_FLUSH_INVALID_TABLE_M 0x1ULL
#define MMU_ISR_OVF_FLUSH_INVALID_TABLE_SHIFT 3
#define MMU_ISR_OVF_FLUSH_INVALID_TABLE_MASK \
		(MMU_ISR_OVF_FLUSH_INVALID_TABLE_M << \
		MMU_ISR_OVF_FLUSH_INVALID_TABLE_SHIFT)
#define MMU_ERR_LOG 0x70
#define MMU_ERR_LOG_DEF 0x0
#define MMU_ERR_LOG_ID_M 0xffULL
#define MMU_ERR_LOG_ID_SHIFT 32
#define MMU_ERR_LOG_ID_MASK (MMU_ERR_LOG_ID_M << MMU_ERR_LOG_ID_SHIFT)
#define MMU_ERR_LOG_VPAGEADDR_M 0x7fffffffULL
#define MMU_ERR_LOG_VPAGEADDR_SHIFT 0
#define MMU_ERR_LOG_VPAGEADDR_MASK (MMU_ERR_LOG_VPAGEADDR_M << \
		MMU_ERR_LOG_VPAGEADDR_SHIFT)
#define MMU_ERR_LOG_RD_WR_N_M 0x1ULL
#define MMU_ERR_LOG_RD_WR_N_SHIFT 40
#define MMU_ERR_LOG_RD_WR_N_MASK (MMU_ERR_LOG_RD_WR_N_M << \
		MMU_ERR_LOG_RD_WR_N_SHIFT)
#define BIF_AXI_CTRL_DMA0 0x80
#define BIF_AXI_CTRL_DMA0_DEF 0x0
#define BIF_AXI_CTRL_DMA0_CH0_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA0_CH0_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_DMA0_CH0_AXQOS_MASK (BIF_AXI_CTRL_DMA0_CH0_AXQOS_M << \
		BIF_AXI_CTRL_DMA0_CH0_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH0_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA0_CH0_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_DMA0_CH0_AXCACHE_MASK (BIF_AXI_CTRL_DMA0_CH0_AXCACHE_M << \
		BIF_AXI_CTRL_DMA0_CH0_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH2_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA0_CH2_AXQOS_SHIFT 39
#define BIF_AXI_CTRL_DMA0_CH2_AXQOS_MASK (BIF_AXI_CTRL_DMA0_CH2_AXQOS_M << \
		BIF_AXI_CTRL_DMA0_CH2_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH3_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA0_CH3_AXCACHE_SHIFT 48
#define BIF_AXI_CTRL_DMA0_CH3_AXCACHE_MASK (BIF_AXI_CTRL_DMA0_CH3_AXCACHE_M << \
		BIF_AXI_CTRL_DMA0_CH3_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH1_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA0_CH1_AXQOS_SHIFT 23
#define BIF_AXI_CTRL_DMA0_CH1_AXQOS_MASK (BIF_AXI_CTRL_DMA0_CH1_AXQOS_M << \
		BIF_AXI_CTRL_DMA0_CH1_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH0_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA0_CH0_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_DMA0_CH0_AXPROT_MASK (BIF_AXI_CTRL_DMA0_CH0_AXPROT_M << \
		BIF_AXI_CTRL_DMA0_CH0_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH1_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA0_CH1_AXPROT_SHIFT 20
#define BIF_AXI_CTRL_DMA0_CH1_AXPROT_MASK (BIF_AXI_CTRL_DMA0_CH1_AXPROT_M << \
		BIF_AXI_CTRL_DMA0_CH1_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH3_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA0_CH3_AXQOS_SHIFT 55
#define BIF_AXI_CTRL_DMA0_CH3_AXQOS_MASK (BIF_AXI_CTRL_DMA0_CH3_AXQOS_M << \
		BIF_AXI_CTRL_DMA0_CH3_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH2_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA0_CH2_AXCACHE_SHIFT 32
#define BIF_AXI_CTRL_DMA0_CH2_AXCACHE_MASK (BIF_AXI_CTRL_DMA0_CH2_AXCACHE_M << \
		BIF_AXI_CTRL_DMA0_CH2_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH2_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA0_CH2_AXPROT_SHIFT 36
#define BIF_AXI_CTRL_DMA0_CH2_AXPROT_MASK (BIF_AXI_CTRL_DMA0_CH2_AXPROT_M << \
		BIF_AXI_CTRL_DMA0_CH2_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH1_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA0_CH1_AXCACHE_SHIFT 16
#define BIF_AXI_CTRL_DMA0_CH1_AXCACHE_MASK (BIF_AXI_CTRL_DMA0_CH1_AXCACHE_M << \
		BIF_AXI_CTRL_DMA0_CH1_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA0_CH3_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA0_CH3_AXPROT_SHIFT 52
#define BIF_AXI_CTRL_DMA0_CH3_AXPROT_MASK (BIF_AXI_CTRL_DMA0_CH3_AXPROT_M << \
		BIF_AXI_CTRL_DMA0_CH3_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA1 0x88
#define BIF_AXI_CTRL_DMA1_DEF 0x0
#define BIF_AXI_CTRL_DMA1_CH5_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA1_CH5_AXPROT_SHIFT 20
#define BIF_AXI_CTRL_DMA1_CH5_AXPROT_MASK (BIF_AXI_CTRL_DMA1_CH5_AXPROT_M << \
		BIF_AXI_CTRL_DMA1_CH5_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH4_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA1_CH4_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_DMA1_CH4_AXCACHE_MASK (BIF_AXI_CTRL_DMA1_CH4_AXCACHE_M << \
		BIF_AXI_CTRL_DMA1_CH4_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH5_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA1_CH5_AXCACHE_SHIFT 16
#define BIF_AXI_CTRL_DMA1_CH5_AXCACHE_MASK (BIF_AXI_CTRL_DMA1_CH5_AXCACHE_M << \
		BIF_AXI_CTRL_DMA1_CH5_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH4_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA1_CH4_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_DMA1_CH4_AXQOS_MASK (BIF_AXI_CTRL_DMA1_CH4_AXQOS_M << \
		BIF_AXI_CTRL_DMA1_CH4_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH6_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA1_CH6_AXQOS_SHIFT 39
#define BIF_AXI_CTRL_DMA1_CH6_AXQOS_MASK (BIF_AXI_CTRL_DMA1_CH6_AXQOS_M << \
		BIF_AXI_CTRL_DMA1_CH6_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH6_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA1_CH6_AXPROT_SHIFT 36
#define BIF_AXI_CTRL_DMA1_CH6_AXPROT_MASK (BIF_AXI_CTRL_DMA1_CH6_AXPROT_M << \
		BIF_AXI_CTRL_DMA1_CH6_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH4_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA1_CH4_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_DMA1_CH4_AXPROT_MASK (BIF_AXI_CTRL_DMA1_CH4_AXPROT_M << \
		BIF_AXI_CTRL_DMA1_CH4_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH5_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA1_CH5_AXQOS_SHIFT 23
#define BIF_AXI_CTRL_DMA1_CH5_AXQOS_MASK (BIF_AXI_CTRL_DMA1_CH5_AXQOS_M << \
		BIF_AXI_CTRL_DMA1_CH5_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH7_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA1_CH7_AXQOS_SHIFT 55
#define BIF_AXI_CTRL_DMA1_CH7_AXQOS_MASK (BIF_AXI_CTRL_DMA1_CH7_AXQOS_M << \
		BIF_AXI_CTRL_DMA1_CH7_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH6_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA1_CH6_AXCACHE_SHIFT 32
#define BIF_AXI_CTRL_DMA1_CH6_AXCACHE_MASK (BIF_AXI_CTRL_DMA1_CH6_AXCACHE_M << \
		BIF_AXI_CTRL_DMA1_CH6_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH7_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA1_CH7_AXCACHE_SHIFT 48
#define BIF_AXI_CTRL_DMA1_CH7_AXCACHE_MASK (BIF_AXI_CTRL_DMA1_CH7_AXCACHE_M << \
		BIF_AXI_CTRL_DMA1_CH7_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA1_CH7_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA1_CH7_AXPROT_SHIFT 52
#define BIF_AXI_CTRL_DMA1_CH7_AXPROT_MASK (BIF_AXI_CTRL_DMA1_CH7_AXPROT_M << \
		BIF_AXI_CTRL_DMA1_CH7_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA2 0x90
#define BIF_AXI_CTRL_DMA2_DEF 0x0
#define BIF_AXI_CTRL_DMA2_CH9_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA2_CH9_AXPROT_SHIFT 20
#define BIF_AXI_CTRL_DMA2_CH9_AXPROT_MASK (BIF_AXI_CTRL_DMA2_CH9_AXPROT_M << \
		BIF_AXI_CTRL_DMA2_CH9_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH10_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA2_CH10_AXCACHE_SHIFT 32
#define BIF_AXI_CTRL_DMA2_CH10_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA2_CH10_AXCACHE_M << \
		BIF_AXI_CTRL_DMA2_CH10_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH11_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA2_CH11_AXPROT_SHIFT 52
#define BIF_AXI_CTRL_DMA2_CH11_AXPROT_MASK (BIF_AXI_CTRL_DMA2_CH11_AXPROT_M << \
		BIF_AXI_CTRL_DMA2_CH11_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH8_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA2_CH8_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_DMA2_CH8_AXQOS_MASK (BIF_AXI_CTRL_DMA2_CH8_AXQOS_M << \
		BIF_AXI_CTRL_DMA2_CH8_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH9_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA2_CH9_AXCACHE_SHIFT 16
#define BIF_AXI_CTRL_DMA2_CH9_AXCACHE_MASK (BIF_AXI_CTRL_DMA2_CH9_AXCACHE_M << \
		BIF_AXI_CTRL_DMA2_CH9_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH11_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA2_CH11_AXCACHE_SHIFT 48
#define BIF_AXI_CTRL_DMA2_CH11_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA2_CH11_AXCACHE_M << \
		BIF_AXI_CTRL_DMA2_CH11_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH8_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA2_CH8_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_DMA2_CH8_AXCACHE_MASK (BIF_AXI_CTRL_DMA2_CH8_AXCACHE_M << \
		BIF_AXI_CTRL_DMA2_CH8_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH10_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA2_CH10_AXQOS_SHIFT 39
#define BIF_AXI_CTRL_DMA2_CH10_AXQOS_MASK (BIF_AXI_CTRL_DMA2_CH10_AXQOS_M << \
		BIF_AXI_CTRL_DMA2_CH10_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH8_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA2_CH8_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_DMA2_CH8_AXPROT_MASK (BIF_AXI_CTRL_DMA2_CH8_AXPROT_M << \
		BIF_AXI_CTRL_DMA2_CH8_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH10_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA2_CH10_AXPROT_SHIFT 36
#define BIF_AXI_CTRL_DMA2_CH10_AXPROT_MASK (BIF_AXI_CTRL_DMA2_CH10_AXPROT_M << \
		BIF_AXI_CTRL_DMA2_CH10_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH11_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA2_CH11_AXQOS_SHIFT 55
#define BIF_AXI_CTRL_DMA2_CH11_AXQOS_MASK (BIF_AXI_CTRL_DMA2_CH11_AXQOS_M << \
		BIF_AXI_CTRL_DMA2_CH11_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA2_CH9_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA2_CH9_AXQOS_SHIFT 23
#define BIF_AXI_CTRL_DMA2_CH9_AXQOS_MASK (BIF_AXI_CTRL_DMA2_CH9_AXQOS_M << \
		BIF_AXI_CTRL_DMA2_CH9_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA3 0x98
#define BIF_AXI_CTRL_DMA3_DEF 0x0
#define BIF_AXI_CTRL_DMA3_CH13_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA3_CH13_AXPROT_SHIFT 20
#define BIF_AXI_CTRL_DMA3_CH13_AXPROT_MASK (BIF_AXI_CTRL_DMA3_CH13_AXPROT_M << \
		BIF_AXI_CTRL_DMA3_CH13_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH15_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA3_CH15_AXQOS_SHIFT 55
#define BIF_AXI_CTRL_DMA3_CH15_AXQOS_MASK (BIF_AXI_CTRL_DMA3_CH15_AXQOS_M << \
		BIF_AXI_CTRL_DMA3_CH15_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH12_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA3_CH12_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_DMA3_CH12_AXQOS_MASK (BIF_AXI_CTRL_DMA3_CH12_AXQOS_M << \
		BIF_AXI_CTRL_DMA3_CH12_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH14_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA3_CH14_AXCACHE_SHIFT 32
#define BIF_AXI_CTRL_DMA3_CH14_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA3_CH14_AXCACHE_M << \
		BIF_AXI_CTRL_DMA3_CH14_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH14_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA3_CH14_AXPROT_SHIFT 36
#define BIF_AXI_CTRL_DMA3_CH14_AXPROT_MASK (BIF_AXI_CTRL_DMA3_CH14_AXPROT_M << \
		BIF_AXI_CTRL_DMA3_CH14_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH14_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA3_CH14_AXQOS_SHIFT 39
#define BIF_AXI_CTRL_DMA3_CH14_AXQOS_MASK (BIF_AXI_CTRL_DMA3_CH14_AXQOS_M << \
		BIF_AXI_CTRL_DMA3_CH14_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH15_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA3_CH15_AXPROT_SHIFT 52
#define BIF_AXI_CTRL_DMA3_CH15_AXPROT_MASK (BIF_AXI_CTRL_DMA3_CH15_AXPROT_M << \
		BIF_AXI_CTRL_DMA3_CH15_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH13_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA3_CH13_AXCACHE_SHIFT 16
#define BIF_AXI_CTRL_DMA3_CH13_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA3_CH13_AXCACHE_M << \
		BIF_AXI_CTRL_DMA3_CH13_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH12_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA3_CH12_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_DMA3_CH12_AXPROT_MASK (BIF_AXI_CTRL_DMA3_CH12_AXPROT_M << \
		BIF_AXI_CTRL_DMA3_CH12_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH15_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA3_CH15_AXCACHE_SHIFT 48
#define BIF_AXI_CTRL_DMA3_CH15_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA3_CH15_AXCACHE_M << \
		BIF_AXI_CTRL_DMA3_CH15_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH12_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA3_CH12_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_DMA3_CH12_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA3_CH12_AXCACHE_M << \
		BIF_AXI_CTRL_DMA3_CH12_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA3_CH13_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA3_CH13_AXQOS_SHIFT 23
#define BIF_AXI_CTRL_DMA3_CH13_AXQOS_MASK (BIF_AXI_CTRL_DMA3_CH13_AXQOS_M << \
		BIF_AXI_CTRL_DMA3_CH13_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA4 0xa0
#define BIF_AXI_CTRL_DMA4_DEF 0x0
#define BIF_AXI_CTRL_DMA4_CH17_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA4_CH17_AXQOS_SHIFT 23
#define BIF_AXI_CTRL_DMA4_CH17_AXQOS_MASK (BIF_AXI_CTRL_DMA4_CH17_AXQOS_M << \
		BIF_AXI_CTRL_DMA4_CH17_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH17_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA4_CH17_AXCACHE_SHIFT 16
#define BIF_AXI_CTRL_DMA4_CH17_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA4_CH17_AXCACHE_M << \
		BIF_AXI_CTRL_DMA4_CH17_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH19_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA4_CH19_AXPROT_SHIFT 52
#define BIF_AXI_CTRL_DMA4_CH19_AXPROT_MASK (BIF_AXI_CTRL_DMA4_CH19_AXPROT_M << \
		BIF_AXI_CTRL_DMA4_CH19_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH18_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA4_CH18_AXQOS_SHIFT 39
#define BIF_AXI_CTRL_DMA4_CH18_AXQOS_MASK (BIF_AXI_CTRL_DMA4_CH18_AXQOS_M << \
		BIF_AXI_CTRL_DMA4_CH18_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH16_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA4_CH16_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_DMA4_CH16_AXQOS_MASK (BIF_AXI_CTRL_DMA4_CH16_AXQOS_M << \
		BIF_AXI_CTRL_DMA4_CH16_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH19_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA4_CH19_AXQOS_SHIFT 55
#define BIF_AXI_CTRL_DMA4_CH19_AXQOS_MASK (BIF_AXI_CTRL_DMA4_CH19_AXQOS_M << \
		BIF_AXI_CTRL_DMA4_CH19_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH16_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA4_CH16_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_DMA4_CH16_AXPROT_MASK (BIF_AXI_CTRL_DMA4_CH16_AXPROT_M << \
		BIF_AXI_CTRL_DMA4_CH16_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH16_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA4_CH16_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_DMA4_CH16_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA4_CH16_AXCACHE_M << \
		BIF_AXI_CTRL_DMA4_CH16_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH17_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA4_CH17_AXPROT_SHIFT 20
#define BIF_AXI_CTRL_DMA4_CH17_AXPROT_MASK (BIF_AXI_CTRL_DMA4_CH17_AXPROT_M << \
		BIF_AXI_CTRL_DMA4_CH17_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH18_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA4_CH18_AXCACHE_SHIFT 32
#define BIF_AXI_CTRL_DMA4_CH18_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA4_CH18_AXCACHE_M << \
		BIF_AXI_CTRL_DMA4_CH18_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH19_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA4_CH19_AXCACHE_SHIFT 48
#define BIF_AXI_CTRL_DMA4_CH19_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA4_CH19_AXCACHE_M << \
		BIF_AXI_CTRL_DMA4_CH19_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA4_CH18_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA4_CH18_AXPROT_SHIFT 36
#define BIF_AXI_CTRL_DMA4_CH18_AXPROT_MASK (BIF_AXI_CTRL_DMA4_CH18_AXPROT_M << \
		BIF_AXI_CTRL_DMA4_CH18_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA5 0xa8
#define BIF_AXI_CTRL_DMA5_DEF 0x0
#define BIF_AXI_CTRL_DMA5_CH20_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA5_CH20_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_DMA5_CH20_AXQOS_MASK (BIF_AXI_CTRL_DMA5_CH20_AXQOS_M << \
		BIF_AXI_CTRL_DMA5_CH20_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH22_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA5_CH22_AXQOS_SHIFT 39
#define BIF_AXI_CTRL_DMA5_CH22_AXQOS_MASK (BIF_AXI_CTRL_DMA5_CH22_AXQOS_M << \
		BIF_AXI_CTRL_DMA5_CH22_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH21_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA5_CH21_AXPROT_SHIFT 20
#define BIF_AXI_CTRL_DMA5_CH21_AXPROT_MASK (BIF_AXI_CTRL_DMA5_CH21_AXPROT_M << \
		BIF_AXI_CTRL_DMA5_CH21_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH21_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA5_CH21_AXQOS_SHIFT 23
#define BIF_AXI_CTRL_DMA5_CH21_AXQOS_MASK (BIF_AXI_CTRL_DMA5_CH21_AXQOS_M << \
		BIF_AXI_CTRL_DMA5_CH21_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH23_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA5_CH23_AXQOS_SHIFT 55
#define BIF_AXI_CTRL_DMA5_CH23_AXQOS_MASK (BIF_AXI_CTRL_DMA5_CH23_AXQOS_M << \
		BIF_AXI_CTRL_DMA5_CH23_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH22_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA5_CH22_AXCACHE_SHIFT 32
#define BIF_AXI_CTRL_DMA5_CH22_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA5_CH22_AXCACHE_M << \
		BIF_AXI_CTRL_DMA5_CH22_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH23_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA5_CH23_AXCACHE_SHIFT 48
#define BIF_AXI_CTRL_DMA5_CH23_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA5_CH23_AXCACHE_M << \
		BIF_AXI_CTRL_DMA5_CH23_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH20_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA5_CH20_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_DMA5_CH20_AXPROT_MASK (BIF_AXI_CTRL_DMA5_CH20_AXPROT_M << \
		BIF_AXI_CTRL_DMA5_CH20_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH20_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA5_CH20_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_DMA5_CH20_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA5_CH20_AXCACHE_M << \
		BIF_AXI_CTRL_DMA5_CH20_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH23_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA5_CH23_AXPROT_SHIFT 52
#define BIF_AXI_CTRL_DMA5_CH23_AXPROT_MASK (BIF_AXI_CTRL_DMA5_CH23_AXPROT_M << \
		BIF_AXI_CTRL_DMA5_CH23_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH22_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA5_CH22_AXPROT_SHIFT 36
#define BIF_AXI_CTRL_DMA5_CH22_AXPROT_MASK (BIF_AXI_CTRL_DMA5_CH22_AXPROT_M << \
		BIF_AXI_CTRL_DMA5_CH22_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA5_CH21_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA5_CH21_AXCACHE_SHIFT 16
#define BIF_AXI_CTRL_DMA5_CH21_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA5_CH21_AXCACHE_M << \
		BIF_AXI_CTRL_DMA5_CH21_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA6 0xb0
#define BIF_AXI_CTRL_DMA6_DEF 0x0
#define BIF_AXI_CTRL_DMA6_CH26_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA6_CH26_AXCACHE_SHIFT 32
#define BIF_AXI_CTRL_DMA6_CH26_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA6_CH26_AXCACHE_M << \
		BIF_AXI_CTRL_DMA6_CH26_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH27_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA6_CH27_AXQOS_SHIFT 55
#define BIF_AXI_CTRL_DMA6_CH27_AXQOS_MASK (BIF_AXI_CTRL_DMA6_CH27_AXQOS_M << \
		BIF_AXI_CTRL_DMA6_CH27_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH27_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA6_CH27_AXPROT_SHIFT 52
#define BIF_AXI_CTRL_DMA6_CH27_AXPROT_MASK (BIF_AXI_CTRL_DMA6_CH27_AXPROT_M << \
		BIF_AXI_CTRL_DMA6_CH27_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH24_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA6_CH24_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_DMA6_CH24_AXQOS_MASK (BIF_AXI_CTRL_DMA6_CH24_AXQOS_M << \
		BIF_AXI_CTRL_DMA6_CH24_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH26_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA6_CH26_AXQOS_SHIFT 39
#define BIF_AXI_CTRL_DMA6_CH26_AXQOS_MASK (BIF_AXI_CTRL_DMA6_CH26_AXQOS_M << \
		BIF_AXI_CTRL_DMA6_CH26_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH24_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA6_CH24_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_DMA6_CH24_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA6_CH24_AXCACHE_M << \
		BIF_AXI_CTRL_DMA6_CH24_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH27_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA6_CH27_AXCACHE_SHIFT 48
#define BIF_AXI_CTRL_DMA6_CH27_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA6_CH27_AXCACHE_M << \
		BIF_AXI_CTRL_DMA6_CH27_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH26_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA6_CH26_AXPROT_SHIFT 36
#define BIF_AXI_CTRL_DMA6_CH26_AXPROT_MASK (BIF_AXI_CTRL_DMA6_CH26_AXPROT_M << \
		BIF_AXI_CTRL_DMA6_CH26_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH25_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA6_CH25_AXQOS_SHIFT 23
#define BIF_AXI_CTRL_DMA6_CH25_AXQOS_MASK (BIF_AXI_CTRL_DMA6_CH25_AXQOS_M << \
		BIF_AXI_CTRL_DMA6_CH25_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH25_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA6_CH25_AXPROT_SHIFT 20
#define BIF_AXI_CTRL_DMA6_CH25_AXPROT_MASK (BIF_AXI_CTRL_DMA6_CH25_AXPROT_M << \
		BIF_AXI_CTRL_DMA6_CH25_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH25_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA6_CH25_AXCACHE_SHIFT 16
#define BIF_AXI_CTRL_DMA6_CH25_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA6_CH25_AXCACHE_M << \
		BIF_AXI_CTRL_DMA6_CH25_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA6_CH24_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA6_CH24_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_DMA6_CH24_AXPROT_MASK (BIF_AXI_CTRL_DMA6_CH24_AXPROT_M << \
		BIF_AXI_CTRL_DMA6_CH24_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA7 0xb8
#define BIF_AXI_CTRL_DMA7_DEF 0x0
#define BIF_AXI_CTRL_DMA7_CH29_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA7_CH29_AXQOS_SHIFT 23
#define BIF_AXI_CTRL_DMA7_CH29_AXQOS_MASK (BIF_AXI_CTRL_DMA7_CH29_AXQOS_M << \
		BIF_AXI_CTRL_DMA7_CH29_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH30_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA7_CH30_AXPROT_SHIFT 36
#define BIF_AXI_CTRL_DMA7_CH30_AXPROT_MASK (BIF_AXI_CTRL_DMA7_CH30_AXPROT_M << \
		BIF_AXI_CTRL_DMA7_CH30_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH28_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA7_CH28_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_DMA7_CH28_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA7_CH28_AXCACHE_M << \
		BIF_AXI_CTRL_DMA7_CH28_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH30_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA7_CH30_AXCACHE_SHIFT 32
#define BIF_AXI_CTRL_DMA7_CH30_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA7_CH30_AXCACHE_M << \
		BIF_AXI_CTRL_DMA7_CH30_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH31_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA7_CH31_AXCACHE_SHIFT 48
#define BIF_AXI_CTRL_DMA7_CH31_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA7_CH31_AXCACHE_M << \
		BIF_AXI_CTRL_DMA7_CH31_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH31_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA7_CH31_AXQOS_SHIFT 55
#define BIF_AXI_CTRL_DMA7_CH31_AXQOS_MASK (BIF_AXI_CTRL_DMA7_CH31_AXQOS_M << \
		BIF_AXI_CTRL_DMA7_CH31_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH31_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA7_CH31_AXPROT_SHIFT 52
#define BIF_AXI_CTRL_DMA7_CH31_AXPROT_MASK (BIF_AXI_CTRL_DMA7_CH31_AXPROT_M << \
		BIF_AXI_CTRL_DMA7_CH31_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH30_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA7_CH30_AXQOS_SHIFT 39
#define BIF_AXI_CTRL_DMA7_CH30_AXQOS_MASK (BIF_AXI_CTRL_DMA7_CH30_AXQOS_M << \
		BIF_AXI_CTRL_DMA7_CH30_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH29_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA7_CH29_AXPROT_SHIFT 20
#define BIF_AXI_CTRL_DMA7_CH29_AXPROT_MASK (BIF_AXI_CTRL_DMA7_CH29_AXPROT_M << \
		BIF_AXI_CTRL_DMA7_CH29_AXPROT_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH29_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_DMA7_CH29_AXCACHE_SHIFT 16
#define BIF_AXI_CTRL_DMA7_CH29_AXCACHE_MASK \
		(BIF_AXI_CTRL_DMA7_CH29_AXCACHE_M << \
		BIF_AXI_CTRL_DMA7_CH29_AXCACHE_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH28_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_DMA7_CH28_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_DMA7_CH28_AXQOS_MASK (BIF_AXI_CTRL_DMA7_CH28_AXQOS_M << \
		BIF_AXI_CTRL_DMA7_CH28_AXQOS_SHIFT)
#define BIF_AXI_CTRL_DMA7_CH28_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_DMA7_CH28_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_DMA7_CH28_AXPROT_MASK (BIF_AXI_CTRL_DMA7_CH28_AXPROT_M << \
		BIF_AXI_CTRL_DMA7_CH28_AXPROT_SHIFT)
#define BIF_AXI_CTRL_MMU 0xc0
#define BIF_AXI_CTRL_MMU_DEF 0x0
#define BIF_AXI_CTRL_MMU_AXPROT_M 0x7ULL
#define BIF_AXI_CTRL_MMU_AXPROT_SHIFT 4
#define BIF_AXI_CTRL_MMU_AXPROT_MASK (BIF_AXI_CTRL_MMU_AXPROT_M << \
		BIF_AXI_CTRL_MMU_AXPROT_SHIFT)
#define BIF_AXI_CTRL_MMU_AXQOS_M 0xfULL
#define BIF_AXI_CTRL_MMU_AXQOS_SHIFT 7
#define BIF_AXI_CTRL_MMU_AXQOS_MASK (BIF_AXI_CTRL_MMU_AXQOS_M << \
		BIF_AXI_CTRL_MMU_AXQOS_SHIFT)
#define BIF_AXI_CTRL_MMU_AXCACHE_M 0xfULL
#define BIF_AXI_CTRL_MMU_AXCACHE_SHIFT 0
#define BIF_AXI_CTRL_MMU_AXCACHE_MASK (BIF_AXI_CTRL_MMU_AXCACHE_M << \
		BIF_AXI_CTRL_MMU_AXCACHE_SHIFT)
#define BIF_ISR 0xc8
#define BIF_ISR_DEF 0x0
#define BIF_ISR_TO_ERR_MMU_RD_M 0x1ULL
#define BIF_ISR_TO_ERR_MMU_RD_SHIFT 4
#define BIF_ISR_TO_ERR_MMU_RD_MASK (BIF_ISR_TO_ERR_MMU_RD_M << \
		BIF_ISR_TO_ERR_MMU_RD_SHIFT)
#define BIF_ISR_TO_ERR_CHAN_WR_M 0x1ULL
#define BIF_ISR_TO_ERR_CHAN_WR_SHIFT 3
#define BIF_ISR_TO_ERR_CHAN_WR_MASK (BIF_ISR_TO_ERR_CHAN_WR_M << \
		BIF_ISR_TO_ERR_CHAN_WR_SHIFT)
#define BIF_ISR_BUS_ERR_MMU_M 0x1ULL
#define BIF_ISR_BUS_ERR_MMU_SHIFT 1
#define BIF_ISR_BUS_ERR_MMU_MASK (BIF_ISR_BUS_ERR_MMU_M << \
		BIF_ISR_BUS_ERR_MMU_SHIFT)
#define BIF_ISR_BUS_ERR_CHAN_M 0x1ULL
#define BIF_ISR_BUS_ERR_CHAN_SHIFT 0
#define BIF_ISR_BUS_ERR_CHAN_MASK (BIF_ISR_BUS_ERR_CHAN_M << \
		BIF_ISR_BUS_ERR_CHAN_SHIFT)
#define BIF_ISR_TO_ERR_CHAN_RD_M 0x1ULL
#define BIF_ISR_TO_ERR_CHAN_RD_SHIFT 2
#define BIF_ISR_TO_ERR_CHAN_RD_MASK (BIF_ISR_TO_ERR_CHAN_RD_M << \
		BIF_ISR_TO_ERR_CHAN_RD_SHIFT)
#define BIF_ITR 0xd0
#define BIF_ITR_DEF 0x0
#define BIF_ITR_TO_ERR_CHAN_RD_M 0x1ULL
#define BIF_ITR_TO_ERR_CHAN_RD_SHIFT 2
#define BIF_ITR_TO_ERR_CHAN_RD_MASK (BIF_ITR_TO_ERR_CHAN_RD_M << \
		BIF_ITR_TO_ERR_CHAN_RD_SHIFT)
#define BIF_ITR_TO_ERR_MMU_RD_M 0x1ULL
#define BIF_ITR_TO_ERR_MMU_RD_SHIFT 4
#define BIF_ITR_TO_ERR_MMU_RD_MASK (BIF_ITR_TO_ERR_MMU_RD_M << \
		BIF_ITR_TO_ERR_MMU_RD_SHIFT)
#define BIF_ITR_TO_ERR_CHAN_WR_M 0x1ULL
#define BIF_ITR_TO_ERR_CHAN_WR_SHIFT 3
#define BIF_ITR_TO_ERR_CHAN_WR_MASK (BIF_ITR_TO_ERR_CHAN_WR_M << \
		BIF_ITR_TO_ERR_CHAN_WR_SHIFT)
#define BIF_ITR_BUS_ERR_CHAN_M 0x1ULL
#define BIF_ITR_BUS_ERR_CHAN_SHIFT 0
#define BIF_ITR_BUS_ERR_CHAN_MASK (BIF_ITR_BUS_ERR_CHAN_M << \
		BIF_ITR_BUS_ERR_CHAN_SHIFT)
#define BIF_ITR_BUS_ERR_MMU_M 0x1ULL
#define BIF_ITR_BUS_ERR_MMU_SHIFT 1
#define BIF_ITR_BUS_ERR_MMU_MASK (BIF_ITR_BUS_ERR_MMU_M << \
		BIF_ITR_BUS_ERR_MMU_SHIFT)
#define BIF_IER 0xd8
#define BIF_IER_DEF 0x1f
#define BIF_IER_BUS_ERR_CHAN_M 0x1ULL
#define BIF_IER_BUS_ERR_CHAN_SHIFT 0
#define BIF_IER_BUS_ERR_CHAN_MASK (BIF_IER_BUS_ERR_CHAN_M << \
		BIF_IER_BUS_ERR_CHAN_SHIFT)
#define BIF_IER_TO_ERR_CHAN_RD_M 0x1ULL
#define BIF_IER_TO_ERR_CHAN_RD_SHIFT 2
#define BIF_IER_TO_ERR_CHAN_RD_MASK (BIF_IER_TO_ERR_CHAN_RD_M << \
		BIF_IER_TO_ERR_CHAN_RD_SHIFT)
#define BIF_IER_BUS_ERR_MMU_M 0x1ULL
#define BIF_IER_BUS_ERR_MMU_SHIFT 1
#define BIF_IER_BUS_ERR_MMU_MASK (BIF_IER_BUS_ERR_MMU_M << \
		BIF_IER_BUS_ERR_MMU_SHIFT)
#define BIF_IER_TO_ERR_MMU_RD_M 0x1ULL
#define BIF_IER_TO_ERR_MMU_RD_SHIFT 4
#define BIF_IER_TO_ERR_MMU_RD_MASK (BIF_IER_TO_ERR_MMU_RD_M << \
		BIF_IER_TO_ERR_MMU_RD_SHIFT)
#define BIF_IER_TO_ERR_CHAN_WR_M 0x1ULL
#define BIF_IER_TO_ERR_CHAN_WR_SHIFT 3
#define BIF_IER_TO_ERR_CHAN_WR_MASK (BIF_IER_TO_ERR_CHAN_WR_M << \
		BIF_IER_TO_ERR_CHAN_WR_SHIFT)
#define BIF_IMR 0xe0
#define BIF_IMR_DEF 0x0
#define BIF_IMR_BUS_ERR_CHAN_M 0x1ULL
#define BIF_IMR_BUS_ERR_CHAN_SHIFT 0
#define BIF_IMR_BUS_ERR_CHAN_MASK (BIF_IMR_BUS_ERR_CHAN_M << \
		BIF_IMR_BUS_ERR_CHAN_SHIFT)
#define BIF_IMR_TO_ERR_CHAN_RD_M 0x1ULL
#define BIF_IMR_TO_ERR_CHAN_RD_SHIFT 2
#define BIF_IMR_TO_ERR_CHAN_RD_MASK (BIF_IMR_TO_ERR_CHAN_RD_M << \
		BIF_IMR_TO_ERR_CHAN_RD_SHIFT)
#define BIF_IMR_TO_ERR_MMU_RD_M 0x1ULL
#define BIF_IMR_TO_ERR_MMU_RD_SHIFT 4
#define BIF_IMR_TO_ERR_MMU_RD_MASK (BIF_IMR_TO_ERR_MMU_RD_M << \
		BIF_IMR_TO_ERR_MMU_RD_SHIFT)
#define BIF_IMR_BUS_ERR_MMU_M 0x1ULL
#define BIF_IMR_BUS_ERR_MMU_SHIFT 1
#define BIF_IMR_BUS_ERR_MMU_MASK (BIF_IMR_BUS_ERR_MMU_M << \
		BIF_IMR_BUS_ERR_MMU_SHIFT)
#define BIF_IMR_TO_ERR_CHAN_WR_M 0x1ULL
#define BIF_IMR_TO_ERR_CHAN_WR_SHIFT 3
#define BIF_IMR_TO_ERR_CHAN_WR_MASK (BIF_IMR_TO_ERR_CHAN_WR_M << \
		BIF_IMR_TO_ERR_CHAN_WR_SHIFT)
#define BIF_ISR_OVF 0xe8
#define BIF_ISR_OVF_DEF 0x0
#define BIF_ISR_OVF_BUS_ERR_MMU_M 0x1ULL
#define BIF_ISR_OVF_BUS_ERR_MMU_SHIFT 1
#define BIF_ISR_OVF_BUS_ERR_MMU_MASK (BIF_ISR_OVF_BUS_ERR_MMU_M << \
		BIF_ISR_OVF_BUS_ERR_MMU_SHIFT)
#define BIF_ISR_OVF_TO_ERR_CHAN_RD_M 0x1ULL
#define BIF_ISR_OVF_TO_ERR_CHAN_RD_SHIFT 2
#define BIF_ISR_OVF_TO_ERR_CHAN_RD_MASK (BIF_ISR_OVF_TO_ERR_CHAN_RD_M << \
		BIF_ISR_OVF_TO_ERR_CHAN_RD_SHIFT)
#define BIF_ISR_OVF_TO_ERR_MMU_RD_M 0x1ULL
#define BIF_ISR_OVF_TO_ERR_MMU_RD_SHIFT 4
#define BIF_ISR_OVF_TO_ERR_MMU_RD_MASK (BIF_ISR_OVF_TO_ERR_MMU_RD_M << \
		BIF_ISR_OVF_TO_ERR_MMU_RD_SHIFT)
#define BIF_ISR_OVF_BUS_ERR_CHAN_M 0x1ULL
#define BIF_ISR_OVF_BUS_ERR_CHAN_SHIFT 0
#define BIF_ISR_OVF_BUS_ERR_CHAN_MASK (BIF_ISR_OVF_BUS_ERR_CHAN_M << \
		BIF_ISR_OVF_BUS_ERR_CHAN_SHIFT)
#define BIF_ISR_OVF_TO_ERR_CHAN_WR_M 0x1ULL
#define BIF_ISR_OVF_TO_ERR_CHAN_WR_SHIFT 3
#define BIF_ISR_OVF_TO_ERR_CHAN_WR_MASK (BIF_ISR_OVF_TO_ERR_CHAN_WR_M << \
		BIF_ISR_OVF_TO_ERR_CHAN_WR_SHIFT)
#define BIF_TO_ERR_CFG 0xf0
#define BIF_TO_ERR_CFG_DEF 0x1f0000
#define BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_M 0x1fULL
#define BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_SHIFT 16
#define BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_MASK \
		(BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_M << \
		BIF_TO_ERR_CFG_TIMEOUT_PRESCALE_SHIFT)
#define BIF_ERR_LOG 0xf8
#define BIF_ERR_LOG_DEF 0x0
#define BIF_ERR_LOG_BUS_ERR_CHAN_WR_ID_M 0x3fULL
#define BIF_ERR_LOG_BUS_ERR_CHAN_WR_ID_SHIFT 8
#define BIF_ERR_LOG_BUS_ERR_CHAN_WR_ID_MASK \
		(BIF_ERR_LOG_BUS_ERR_CHAN_WR_ID_M << \
		BIF_ERR_LOG_BUS_ERR_CHAN_WR_ID_SHIFT)
#define BIF_ERR_LOG_TO_ERR_MMU_RD_RX_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_MMU_RD_RX_PEND_SHIFT 47
#define BIF_ERR_LOG_TO_ERR_MMU_RD_RX_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_MMU_RD_RX_PEND_M << \
		BIF_ERR_LOG_TO_ERR_MMU_RD_RX_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_RID_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_RID_PEND_SHIFT 49
#define BIF_ERR_LOG_TO_ERR_RID_PEND_MASK (BIF_ERR_LOG_TO_ERR_RID_PEND_M << \
		BIF_ERR_LOG_TO_ERR_RID_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_WID_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_WID_PEND_SHIFT 50
#define BIF_ERR_LOG_TO_ERR_WID_PEND_MASK (BIF_ERR_LOG_TO_ERR_WID_PEND_M << \
		BIF_ERR_LOG_TO_ERR_WID_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_DMA_RD_IN_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_DMA_RD_IN_PEND_SHIFT 34
#define BIF_ERR_LOG_TO_ERR_DMA_RD_IN_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_DMA_RD_IN_PEND_M << \
		BIF_ERR_LOG_TO_ERR_DMA_RD_IN_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_PEND_SHIFT 48
#define BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_PEND_M << \
		BIF_ERR_LOG_TO_ERR_MMU_RD_OUT_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_PEND_SHIFT 36
#define BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_PEND_M << \
		BIF_ERR_LOG_TO_ERR_DMA_RD_OUT_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_JQS_RD_OUT_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_JQS_RD_OUT_PEND_SHIFT 37
#define BIF_ERR_LOG_TO_ERR_JQS_RD_OUT_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_JQS_RD_OUT_PEND_M << \
		BIF_ERR_LOG_TO_ERR_JQS_RD_OUT_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_PEND_SHIFT 40
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_PEND_M << \
		BIF_ERR_LOG_TO_ERR_DMA_WR_WPULL_PEND_SHIFT)
#define BIF_ERR_LOG_BUS_ERR_CHAN_M 0x3fULL
#define BIF_ERR_LOG_BUS_ERR_CHAN_SHIFT 14
#define BIF_ERR_LOG_BUS_ERR_CHAN_MASK (BIF_ERR_LOG_BUS_ERR_CHAN_M << \
		BIF_ERR_LOG_BUS_ERR_CHAN_SHIFT)
#define BIF_ERR_LOG_TO_ERR_JQS_RD_IN_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_JQS_RD_IN_PEND_SHIFT 35
#define BIF_ERR_LOG_TO_ERR_JQS_RD_IN_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_JQS_RD_IN_PEND_M << \
		BIF_ERR_LOG_TO_ERR_JQS_RD_IN_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_CHAN_RD_RX_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_CHAN_RD_RX_PEND_SHIFT 33
#define BIF_ERR_LOG_TO_ERR_CHAN_RD_RX_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_CHAN_RD_RX_PEND_M << \
		BIF_ERR_LOG_TO_ERR_CHAN_RD_RX_PEND_SHIFT)
#define BIF_ERR_LOG_BUS_ERR_CHAN_WRITE_M 0x1ULL
#define BIF_ERR_LOG_BUS_ERR_CHAN_WRITE_SHIFT 0
#define BIF_ERR_LOG_BUS_ERR_CHAN_WRITE_MASK \
		(BIF_ERR_LOG_BUS_ERR_CHAN_WRITE_M << \
		BIF_ERR_LOG_BUS_ERR_CHAN_WRITE_SHIFT)
#define BIF_ERR_LOG_BUS_ERR_AXI_ID_M 0x7fULL
#define BIF_ERR_LOG_BUS_ERR_AXI_ID_SHIFT 1
#define BIF_ERR_LOG_BUS_ERR_AXI_ID_MASK (BIF_ERR_LOG_BUS_ERR_AXI_ID_M << \
		BIF_ERR_LOG_BUS_ERR_AXI_ID_SHIFT)
#define BIF_ERR_LOG_TO_ERR_DMA_WR_IN_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_DMA_WR_IN_PEND_SHIFT 38
#define BIF_ERR_LOG_TO_ERR_DMA_WR_IN_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_DMA_WR_IN_PEND_M << \
		BIF_ERR_LOG_TO_ERR_DMA_WR_IN_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_JQS_WR_WDATA_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_JQS_WR_WDATA_PEND_SHIFT 45
#define BIF_ERR_LOG_TO_ERR_JQS_WR_WDATA_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_JQS_WR_WDATA_PEND_M << \
		BIF_ERR_LOG_TO_ERR_JQS_WR_WDATA_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_PEND_SHIFT 44
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_PEND_M << \
		BIF_ERR_LOG_TO_ERR_DMA_WR_WDATA_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_CHAN_WR_TX_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_CHAN_WR_TX_PEND_SHIFT 46
#define BIF_ERR_LOG_TO_ERR_CHAN_WR_TX_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_CHAN_WR_TX_PEND_M << \
		BIF_ERR_LOG_TO_ERR_CHAN_WR_TX_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_JQS_WR_RSP_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_JQS_WR_RSP_PEND_SHIFT 43
#define BIF_ERR_LOG_TO_ERR_JQS_WR_RSP_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_JQS_WR_RSP_PEND_M << \
		BIF_ERR_LOG_TO_ERR_JQS_WR_RSP_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_JQS_WR_PENDID_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_JQS_WR_PENDID_PEND_SHIFT 41
#define BIF_ERR_LOG_TO_ERR_JQS_WR_PENDID_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_JQS_WR_PENDID_PEND_M << \
		BIF_ERR_LOG_TO_ERR_JQS_WR_PENDID_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_CHAN_RD_TX_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_CHAN_RD_TX_PEND_SHIFT 32
#define BIF_ERR_LOG_TO_ERR_CHAN_RD_TX_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_CHAN_RD_TX_PEND_M << \
		BIF_ERR_LOG_TO_ERR_CHAN_RD_TX_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_PEND_SHIFT 42
#define BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_PEND_M << \
		BIF_ERR_LOG_TO_ERR_DMA_WR_WACK_PEND_SHIFT)
#define BIF_ERR_LOG_TO_ERR_JQS_WR_IN_PEND_M 0x1ULL
#define BIF_ERR_LOG_TO_ERR_JQS_WR_IN_PEND_SHIFT 39
#define BIF_ERR_LOG_TO_ERR_JQS_WR_IN_PEND_MASK \
		(BIF_ERR_LOG_TO_ERR_JQS_WR_IN_PEND_M << \
		BIF_ERR_LOG_TO_ERR_JQS_WR_IN_PEND_SHIFT)
#define BIF_ERR_LOG_BUS_ADDR 0x100
#define BIF_ERR_LOG_BUS_ADDR_DEF 0x0
#define BIF_ERR_LOG_BUS_ADDR_PADDR_M 0x3ffffffffULL
#define BIF_ERR_LOG_BUS_ADDR_PADDR_SHIFT 0
#define BIF_ERR_LOG_BUS_ADDR_PADDR_MASK (BIF_ERR_LOG_BUS_ADDR_PADDR_M << \
		BIF_ERR_LOG_BUS_ADDR_PADDR_SHIFT)
#define BIF_PMON_CFG 0x108
#define BIF_PMON_CFG_DEF 0x0
#define BIF_PMON_CFG_ENABLE_M 0x1ULL
#define BIF_PMON_CFG_ENABLE_SHIFT 0
#define BIF_PMON_CFG_ENABLE_MASK (BIF_PMON_CFG_ENABLE_M << \
		BIF_PMON_CFG_ENABLE_SHIFT)
#define BIF_PMON_CNT_0_CFG 0x110
#define BIF_PMON_CNT_0_CFG_DEF 0x0
#define BIF_PMON_CNT_0_CFG_MODE_M 0x7ULL
#define BIF_PMON_CNT_0_CFG_MODE_SHIFT 0
#define BIF_PMON_CNT_0_CFG_MODE_MASK (BIF_PMON_CNT_0_CFG_MODE_M << \
		BIF_PMON_CNT_0_CFG_MODE_SHIFT)
#define BIF_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
#define BIF_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
#define BIF_PMON_CNT_0_CFG_DEC_MASK_MASK (BIF_PMON_CNT_0_CFG_DEC_MASK_M << \
		BIF_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
#define BIF_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
#define BIF_PMON_CNT_0_CFG_INC_INV_SHIFT 47
#define BIF_PMON_CNT_0_CFG_INC_INV_MASK (BIF_PMON_CNT_0_CFG_INC_INV_M << \
		BIF_PMON_CNT_0_CFG_INC_INV_SHIFT)
#define BIF_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
#define BIF_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
#define BIF_PMON_CNT_0_CFG_INC_MASK_MASK (BIF_PMON_CNT_0_CFG_INC_MASK_M << \
		BIF_PMON_CNT_0_CFG_INC_MASK_SHIFT)
#define BIF_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
#define BIF_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
#define BIF_PMON_CNT_0_CFG_INC_MATCH_MASK (BIF_PMON_CNT_0_CFG_INC_MATCH_M << \
		BIF_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
#define BIF_PMON_CNT_0_CFG_DEC_SEL_M 0xfULL
#define BIF_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
#define BIF_PMON_CNT_0_CFG_DEC_SEL_MASK (BIF_PMON_CNT_0_CFG_DEC_SEL_M << \
		BIF_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
#define BIF_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
#define BIF_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
#define BIF_PMON_CNT_0_CFG_DEC_INV_MASK (BIF_PMON_CNT_0_CFG_DEC_INV_M << \
		BIF_PMON_CNT_0_CFG_DEC_INV_SHIFT)
#define BIF_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
#define BIF_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
#define BIF_PMON_CNT_0_CFG_THRESHOLD_MASK (BIF_PMON_CNT_0_CFG_THRESHOLD_M << \
		BIF_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
#define BIF_PMON_CNT_0_CFG_INC_SEL_M 0xfULL
#define BIF_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
#define BIF_PMON_CNT_0_CFG_INC_SEL_MASK (BIF_PMON_CNT_0_CFG_INC_SEL_M << \
		BIF_PMON_CNT_0_CFG_INC_SEL_SHIFT)
#define BIF_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
#define BIF_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
#define BIF_PMON_CNT_0_CFG_DEC_MATCH_MASK (BIF_PMON_CNT_0_CFG_DEC_MATCH_M << \
		BIF_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
#define BIF_PMON_CNT_0 0x118
#define BIF_PMON_CNT_0_DEF 0x0
#define BIF_PMON_CNT_0_CNT_M 0xffffffffffULL
#define BIF_PMON_CNT_0_CNT_SHIFT 0
#define BIF_PMON_CNT_0_CNT_MASK (BIF_PMON_CNT_0_CNT_M << \
		BIF_PMON_CNT_0_CNT_SHIFT)
#define BIF_PMON_CNT_0_STS_ACC 0x120
#define BIF_PMON_CNT_0_STS_ACC_DEF 0x0
#define BIF_PMON_CNT_0_STS_ACC_VAL_M 0xffULL
#define BIF_PMON_CNT_0_STS_ACC_VAL_SHIFT 0
#define BIF_PMON_CNT_0_STS_ACC_VAL_MASK (BIF_PMON_CNT_0_STS_ACC_VAL_M << \
		BIF_PMON_CNT_0_STS_ACC_VAL_SHIFT)
#define BIF_PMON_CNT_0_STS 0x128
#define BIF_PMON_CNT_0_STS_DEF 0x0
#define BIF_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
#define BIF_PMON_CNT_0_STS_CNT_OF_SHIFT 2
#define BIF_PMON_CNT_0_STS_CNT_OF_MASK (BIF_PMON_CNT_0_STS_CNT_OF_M << \
		BIF_PMON_CNT_0_STS_CNT_OF_SHIFT)
#define BIF_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
#define BIF_PMON_CNT_0_STS_ACC_UF_SHIFT 1
#define BIF_PMON_CNT_0_STS_ACC_UF_MASK (BIF_PMON_CNT_0_STS_ACC_UF_M << \
		BIF_PMON_CNT_0_STS_ACC_UF_SHIFT)
#define BIF_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
#define BIF_PMON_CNT_0_STS_ACC_OF_SHIFT 0
#define BIF_PMON_CNT_0_STS_ACC_OF_MASK (BIF_PMON_CNT_0_STS_ACC_OF_M << \
		BIF_PMON_CNT_0_STS_ACC_OF_SHIFT)
#define BIF_PMON_CNT_1_CFG 0x130
#define BIF_PMON_CNT_1_CFG_DEF 0x0
#define BIF_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
#define BIF_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
#define BIF_PMON_CNT_1_CFG_INC_MATCH_MASK (BIF_PMON_CNT_1_CFG_INC_MATCH_M << \
		BIF_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
#define BIF_PMON_CNT_1_CFG_INC_SEL_M 0xfULL
#define BIF_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
#define BIF_PMON_CNT_1_CFG_INC_SEL_MASK (BIF_PMON_CNT_1_CFG_INC_SEL_M << \
		BIF_PMON_CNT_1_CFG_INC_SEL_SHIFT)
#define BIF_PMON_CNT_1_CFG_DEC_SEL_M 0xfULL
#define BIF_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
#define BIF_PMON_CNT_1_CFG_DEC_SEL_MASK (BIF_PMON_CNT_1_CFG_DEC_SEL_M << \
		BIF_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
#define BIF_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
#define BIF_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
#define BIF_PMON_CNT_1_CFG_THRESHOLD_MASK (BIF_PMON_CNT_1_CFG_THRESHOLD_M << \
		BIF_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
#define BIF_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
#define BIF_PMON_CNT_1_CFG_INC_INV_SHIFT 47
#define BIF_PMON_CNT_1_CFG_INC_INV_MASK (BIF_PMON_CNT_1_CFG_INC_INV_M << \
		BIF_PMON_CNT_1_CFG_INC_INV_SHIFT)
#define BIF_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
#define BIF_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
#define BIF_PMON_CNT_1_CFG_DEC_MASK_MASK (BIF_PMON_CNT_1_CFG_DEC_MASK_M << \
		BIF_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
#define BIF_PMON_CNT_1_CFG_MODE_M 0x7ULL
#define BIF_PMON_CNT_1_CFG_MODE_SHIFT 0
#define BIF_PMON_CNT_1_CFG_MODE_MASK (BIF_PMON_CNT_1_CFG_MODE_M << \
		BIF_PMON_CNT_1_CFG_MODE_SHIFT)
#define BIF_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
#define BIF_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
#define BIF_PMON_CNT_1_CFG_DEC_INV_MASK (BIF_PMON_CNT_1_CFG_DEC_INV_M << \
		BIF_PMON_CNT_1_CFG_DEC_INV_SHIFT)
#define BIF_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
#define BIF_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
#define BIF_PMON_CNT_1_CFG_DEC_MATCH_MASK (BIF_PMON_CNT_1_CFG_DEC_MATCH_M << \
		BIF_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
#define BIF_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
#define BIF_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
#define BIF_PMON_CNT_1_CFG_INC_MASK_MASK (BIF_PMON_CNT_1_CFG_INC_MASK_M << \
		BIF_PMON_CNT_1_CFG_INC_MASK_SHIFT)
#define BIF_PMON_CNT_1 0x138
#define BIF_PMON_CNT_1_DEF 0x0
#define BIF_PMON_CNT_1_CNT_M 0xffffffffffULL
#define BIF_PMON_CNT_1_CNT_SHIFT 0
#define BIF_PMON_CNT_1_CNT_MASK (BIF_PMON_CNT_1_CNT_M << \
		BIF_PMON_CNT_1_CNT_SHIFT)
#define BIF_PMON_CNT_1_STS_ACC 0x140
#define BIF_PMON_CNT_1_STS_ACC_DEF 0x0
#define BIF_PMON_CNT_1_STS_ACC_VAL_M 0xffULL
#define BIF_PMON_CNT_1_STS_ACC_VAL_SHIFT 0
#define BIF_PMON_CNT_1_STS_ACC_VAL_MASK (BIF_PMON_CNT_1_STS_ACC_VAL_M << \
		BIF_PMON_CNT_1_STS_ACC_VAL_SHIFT)
#define BIF_PMON_CNT_1_STS 0x148
#define BIF_PMON_CNT_1_STS_DEF 0x0
#define BIF_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
#define BIF_PMON_CNT_1_STS_ACC_UF_SHIFT 1
#define BIF_PMON_CNT_1_STS_ACC_UF_MASK (BIF_PMON_CNT_1_STS_ACC_UF_M << \
		BIF_PMON_CNT_1_STS_ACC_UF_SHIFT)
#define BIF_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
#define BIF_PMON_CNT_1_STS_ACC_OF_SHIFT 0
#define BIF_PMON_CNT_1_STS_ACC_OF_MASK (BIF_PMON_CNT_1_STS_ACC_OF_M << \
		BIF_PMON_CNT_1_STS_ACC_OF_SHIFT)
#define BIF_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
#define BIF_PMON_CNT_1_STS_CNT_OF_SHIFT 2
#define BIF_PMON_CNT_1_STS_CNT_OF_MASK (BIF_PMON_CNT_1_STS_CNT_OF_M << \
		BIF_PMON_CNT_1_STS_CNT_OF_SHIFT)
#define MMU_PMON_CFG 0x150
#define MMU_PMON_CFG_DEF 0x10000
#define MMU_PMON_CFG_CHAN_GRP1_SEL_M 0x7ULL
#define MMU_PMON_CFG_CHAN_GRP1_SEL_SHIFT 16
#define MMU_PMON_CFG_CHAN_GRP1_SEL_MASK (MMU_PMON_CFG_CHAN_GRP1_SEL_M << \
		MMU_PMON_CFG_CHAN_GRP1_SEL_SHIFT)
#define MMU_PMON_CFG_ENABLE_M 0x1ULL
#define MMU_PMON_CFG_ENABLE_SHIFT 0
#define MMU_PMON_CFG_ENABLE_MASK (MMU_PMON_CFG_ENABLE_M << \
		MMU_PMON_CFG_ENABLE_SHIFT)
#define MMU_PMON_CFG_CHAN_GRP0_SEL_M 0x7ULL
#define MMU_PMON_CFG_CHAN_GRP0_SEL_SHIFT 8
#define MMU_PMON_CFG_CHAN_GRP0_SEL_MASK (MMU_PMON_CFG_CHAN_GRP0_SEL_M << \
		MMU_PMON_CFG_CHAN_GRP0_SEL_SHIFT)
#define MMU_PMON_CNT_0_CFG 0x158
#define MMU_PMON_CNT_0_CFG_DEF 0x0
#define MMU_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
#define MMU_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
#define MMU_PMON_CNT_0_CFG_THRESHOLD_MASK (MMU_PMON_CNT_0_CFG_THRESHOLD_M << \
		MMU_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
#define MMU_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
#define MMU_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
#define MMU_PMON_CNT_0_CFG_INC_MATCH_MASK (MMU_PMON_CNT_0_CFG_INC_MATCH_M << \
		MMU_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
#define MMU_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
#define MMU_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
#define MMU_PMON_CNT_0_CFG_DEC_INV_MASK (MMU_PMON_CNT_0_CFG_DEC_INV_M << \
		MMU_PMON_CNT_0_CFG_DEC_INV_SHIFT)
#define MMU_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
#define MMU_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
#define MMU_PMON_CNT_0_CFG_DEC_MATCH_MASK (MMU_PMON_CNT_0_CFG_DEC_MATCH_M << \
		MMU_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
#define MMU_PMON_CNT_0_CFG_MODE_M 0x7ULL
#define MMU_PMON_CNT_0_CFG_MODE_SHIFT 0
#define MMU_PMON_CNT_0_CFG_MODE_MASK (MMU_PMON_CNT_0_CFG_MODE_M << \
		MMU_PMON_CNT_0_CFG_MODE_SHIFT)
#define MMU_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
#define MMU_PMON_CNT_0_CFG_INC_INV_SHIFT 47
#define MMU_PMON_CNT_0_CFG_INC_INV_MASK (MMU_PMON_CNT_0_CFG_INC_INV_M << \
		MMU_PMON_CNT_0_CFG_INC_INV_SHIFT)
#define MMU_PMON_CNT_0_CFG_INC_SEL_M 0x1fULL
#define MMU_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
#define MMU_PMON_CNT_0_CFG_INC_SEL_MASK (MMU_PMON_CNT_0_CFG_INC_SEL_M << \
		MMU_PMON_CNT_0_CFG_INC_SEL_SHIFT)
#define MMU_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
#define MMU_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
#define MMU_PMON_CNT_0_CFG_INC_MASK_MASK (MMU_PMON_CNT_0_CFG_INC_MASK_M << \
		MMU_PMON_CNT_0_CFG_INC_MASK_SHIFT)
#define MMU_PMON_CNT_0_CFG_DEC_SEL_M 0x1fULL
#define MMU_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
#define MMU_PMON_CNT_0_CFG_DEC_SEL_MASK (MMU_PMON_CNT_0_CFG_DEC_SEL_M << \
		MMU_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
#define MMU_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
#define MMU_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
#define MMU_PMON_CNT_0_CFG_DEC_MASK_MASK (MMU_PMON_CNT_0_CFG_DEC_MASK_M << \
		MMU_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
#define MMU_PMON_CNT_0 0x160
#define MMU_PMON_CNT_0_DEF 0x0
#define MMU_PMON_CNT_0_CNT_M 0xffffffffffULL
#define MMU_PMON_CNT_0_CNT_SHIFT 0
#define MMU_PMON_CNT_0_CNT_MASK (MMU_PMON_CNT_0_CNT_M << \
		MMU_PMON_CNT_0_CNT_SHIFT)
#define MMU_PMON_CNT_0_STS_ACC 0x168
#define MMU_PMON_CNT_0_STS_ACC_DEF 0x0
#define MMU_PMON_CNT_0_STS_ACC_VAL_M 0xffULL
#define MMU_PMON_CNT_0_STS_ACC_VAL_SHIFT 0
#define MMU_PMON_CNT_0_STS_ACC_VAL_MASK (MMU_PMON_CNT_0_STS_ACC_VAL_M << \
		MMU_PMON_CNT_0_STS_ACC_VAL_SHIFT)
#define MMU_PMON_CNT_0_STS 0x170
#define MMU_PMON_CNT_0_STS_DEF 0x0
#define MMU_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
#define MMU_PMON_CNT_0_STS_CNT_OF_SHIFT 2
#define MMU_PMON_CNT_0_STS_CNT_OF_MASK (MMU_PMON_CNT_0_STS_CNT_OF_M << \
		MMU_PMON_CNT_0_STS_CNT_OF_SHIFT)
#define MMU_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
#define MMU_PMON_CNT_0_STS_ACC_UF_SHIFT 1
#define MMU_PMON_CNT_0_STS_ACC_UF_MASK (MMU_PMON_CNT_0_STS_ACC_UF_M << \
		MMU_PMON_CNT_0_STS_ACC_UF_SHIFT)
#define MMU_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
#define MMU_PMON_CNT_0_STS_ACC_OF_SHIFT 0
#define MMU_PMON_CNT_0_STS_ACC_OF_MASK (MMU_PMON_CNT_0_STS_ACC_OF_M << \
		MMU_PMON_CNT_0_STS_ACC_OF_SHIFT)
#define MMU_PMON_CNT_1_CFG 0x178
#define MMU_PMON_CNT_1_CFG_DEF 0x0
#define MMU_PMON_CNT_1_CFG_MODE_M 0x7ULL
#define MMU_PMON_CNT_1_CFG_MODE_SHIFT 0
#define MMU_PMON_CNT_1_CFG_MODE_MASK (MMU_PMON_CNT_1_CFG_MODE_M << \
		MMU_PMON_CNT_1_CFG_MODE_SHIFT)
#define MMU_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
#define MMU_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
#define MMU_PMON_CNT_1_CFG_DEC_MASK_MASK (MMU_PMON_CNT_1_CFG_DEC_MASK_M << \
		MMU_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
#define MMU_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
#define MMU_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
#define MMU_PMON_CNT_1_CFG_INC_MASK_MASK (MMU_PMON_CNT_1_CFG_INC_MASK_M << \
		MMU_PMON_CNT_1_CFG_INC_MASK_SHIFT)
#define MMU_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
#define MMU_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
#define MMU_PMON_CNT_1_CFG_DEC_INV_MASK (MMU_PMON_CNT_1_CFG_DEC_INV_M << \
		MMU_PMON_CNT_1_CFG_DEC_INV_SHIFT)
#define MMU_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
#define MMU_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
#define MMU_PMON_CNT_1_CFG_DEC_MATCH_MASK (MMU_PMON_CNT_1_CFG_DEC_MATCH_M << \
		MMU_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
#define MMU_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
#define MMU_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
#define MMU_PMON_CNT_1_CFG_THRESHOLD_MASK (MMU_PMON_CNT_1_CFG_THRESHOLD_M << \
		MMU_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
#define MMU_PMON_CNT_1_CFG_DEC_SEL_M 0x1fULL
#define MMU_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
#define MMU_PMON_CNT_1_CFG_DEC_SEL_MASK (MMU_PMON_CNT_1_CFG_DEC_SEL_M << \
		MMU_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
#define MMU_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
#define MMU_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
#define MMU_PMON_CNT_1_CFG_INC_MATCH_MASK (MMU_PMON_CNT_1_CFG_INC_MATCH_M << \
		MMU_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
#define MMU_PMON_CNT_1_CFG_INC_SEL_M 0x1fULL
#define MMU_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
#define MMU_PMON_CNT_1_CFG_INC_SEL_MASK (MMU_PMON_CNT_1_CFG_INC_SEL_M << \
		MMU_PMON_CNT_1_CFG_INC_SEL_SHIFT)
#define MMU_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
#define MMU_PMON_CNT_1_CFG_INC_INV_SHIFT 47
#define MMU_PMON_CNT_1_CFG_INC_INV_MASK (MMU_PMON_CNT_1_CFG_INC_INV_M << \
		MMU_PMON_CNT_1_CFG_INC_INV_SHIFT)
#define MMU_PMON_CNT_1 0x180
#define MMU_PMON_CNT_1_DEF 0x0
#define MMU_PMON_CNT_1_CNT_M 0xffffffffffULL
#define MMU_PMON_CNT_1_CNT_SHIFT 0
#define MMU_PMON_CNT_1_CNT_MASK (MMU_PMON_CNT_1_CNT_M << \
		MMU_PMON_CNT_1_CNT_SHIFT)
#define MMU_PMON_CNT_1_STS_ACC 0x188
#define MMU_PMON_CNT_1_STS_ACC_DEF 0x0
#define MMU_PMON_CNT_1_STS_ACC_VAL_M 0xffULL
#define MMU_PMON_CNT_1_STS_ACC_VAL_SHIFT 0
#define MMU_PMON_CNT_1_STS_ACC_VAL_MASK (MMU_PMON_CNT_1_STS_ACC_VAL_M << \
		MMU_PMON_CNT_1_STS_ACC_VAL_SHIFT)
#define MMU_PMON_CNT_1_STS 0x190
#define MMU_PMON_CNT_1_STS_DEF 0x0
#define MMU_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
#define MMU_PMON_CNT_1_STS_ACC_UF_SHIFT 1
#define MMU_PMON_CNT_1_STS_ACC_UF_MASK (MMU_PMON_CNT_1_STS_ACC_UF_M << \
		MMU_PMON_CNT_1_STS_ACC_UF_SHIFT)
#define MMU_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
#define MMU_PMON_CNT_1_STS_ACC_OF_SHIFT 0
#define MMU_PMON_CNT_1_STS_ACC_OF_MASK (MMU_PMON_CNT_1_STS_ACC_OF_M << \
		MMU_PMON_CNT_1_STS_ACC_OF_SHIFT)
#define MMU_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
#define MMU_PMON_CNT_1_STS_CNT_OF_SHIFT 2
#define MMU_PMON_CNT_1_STS_CNT_OF_MASK (MMU_PMON_CNT_1_STS_CNT_OF_M << \
		MMU_PMON_CNT_1_STS_CNT_OF_SHIFT)
#define AXI_SPARE 0x198
#define AXI_SPARE_DEF 0x0
#define AXI_SPARE_SPARE15_M 0x1ULL
#define AXI_SPARE_SPARE15_SHIFT 15
#define AXI_SPARE_SPARE15_MASK (AXI_SPARE_SPARE15_M << AXI_SPARE_SPARE15_SHIFT)
#define AXI_SPARE_SPARE12_M 0x1ULL
#define AXI_SPARE_SPARE12_SHIFT 12
#define AXI_SPARE_SPARE12_MASK (AXI_SPARE_SPARE12_M << AXI_SPARE_SPARE12_SHIFT)
#define AXI_SPARE_SPARE11_M 0x1ULL
#define AXI_SPARE_SPARE11_SHIFT 11
#define AXI_SPARE_SPARE11_MASK (AXI_SPARE_SPARE11_M << AXI_SPARE_SPARE11_SHIFT)
#define AXI_SPARE_SPARE10_M 0x1ULL
#define AXI_SPARE_SPARE10_SHIFT 10
#define AXI_SPARE_SPARE10_MASK (AXI_SPARE_SPARE10_M << AXI_SPARE_SPARE10_SHIFT)
#define AXI_SPARE_SPARE13_M 0x1ULL
#define AXI_SPARE_SPARE13_SHIFT 13
#define AXI_SPARE_SPARE13_MASK (AXI_SPARE_SPARE13_M << AXI_SPARE_SPARE13_SHIFT)
#define AXI_SPARE_SPARE8_M 0x1ULL
#define AXI_SPARE_SPARE8_SHIFT 8
#define AXI_SPARE_SPARE8_MASK (AXI_SPARE_SPARE8_M << AXI_SPARE_SPARE8_SHIFT)
#define AXI_SPARE_SPARE9_M 0x1ULL
#define AXI_SPARE_SPARE9_SHIFT 9
#define AXI_SPARE_SPARE9_MASK (AXI_SPARE_SPARE9_M << AXI_SPARE_SPARE9_SHIFT)
#define AXI_SPARE_SPARE14_M 0x1ULL
#define AXI_SPARE_SPARE14_SHIFT 14
#define AXI_SPARE_SPARE14_MASK (AXI_SPARE_SPARE14_M << AXI_SPARE_SPARE14_SHIFT)
#define AXI_SPARE_SPARE4_M 0x1ULL
#define AXI_SPARE_SPARE4_SHIFT 4
#define AXI_SPARE_SPARE4_MASK (AXI_SPARE_SPARE4_M << AXI_SPARE_SPARE4_SHIFT)
#define AXI_SPARE_SPARE5_M 0x1ULL
#define AXI_SPARE_SPARE5_SHIFT 5
#define AXI_SPARE_SPARE5_MASK (AXI_SPARE_SPARE5_M << AXI_SPARE_SPARE5_SHIFT)
#define AXI_SPARE_SPARE6_M 0x1ULL
#define AXI_SPARE_SPARE6_SHIFT 6
#define AXI_SPARE_SPARE6_MASK (AXI_SPARE_SPARE6_M << AXI_SPARE_SPARE6_SHIFT)
#define AXI_SPARE_SPARE7_M 0x1ULL
#define AXI_SPARE_SPARE7_SHIFT 7
#define AXI_SPARE_SPARE7_MASK (AXI_SPARE_SPARE7_M << AXI_SPARE_SPARE7_SHIFT)
#define AXI_SPARE_SPARE0_M 0x1ULL
#define AXI_SPARE_SPARE0_SHIFT 0
#define AXI_SPARE_SPARE0_MASK (AXI_SPARE_SPARE0_M << AXI_SPARE_SPARE0_SHIFT)
#define AXI_SPARE_SPARE1_M 0x1ULL
#define AXI_SPARE_SPARE1_SHIFT 1
#define AXI_SPARE_SPARE1_MASK (AXI_SPARE_SPARE1_M << AXI_SPARE_SPARE1_SHIFT)
#define AXI_SPARE_SPARE2_M 0x1ULL
#define AXI_SPARE_SPARE2_SHIFT 2
#define AXI_SPARE_SPARE2_MASK (AXI_SPARE_SPARE2_M << AXI_SPARE_SPARE2_SHIFT)
#define AXI_SPARE_SPARE3_M 0x1ULL
#define AXI_SPARE_SPARE3_SHIFT 3
#define AXI_SPARE_SPARE3_MASK (AXI_SPARE_SPARE3_M << AXI_SPARE_SPARE3_SHIFT)

/* Module : IPU_LIB_DREGFILE_DMA_GRP*/
#define DMA_SEL 0x0
#define DMA_SEL_DEF 0x0
#define DMA_SEL_CHAN_SEL_M 0x7ULL
#define DMA_SEL_CHAN_SEL_SHIFT 0
#define DMA_SEL_CHAN_SEL_MASK (DMA_SEL_CHAN_SEL_M << DMA_SEL_CHAN_SEL_SHIFT)
#define DMA_SEL_GRP_SEL_M 0x3ULL
#define DMA_SEL_GRP_SEL_SHIFT 3
#define DMA_SEL_GRP_SEL_MASK (DMA_SEL_GRP_SEL_M << DMA_SEL_GRP_SEL_SHIFT)
#define DMA_CHAN_CTRL 0x8
#define DMA_CHAN_CTRL_DEF 0x0
#define DMA_CHAN_CTRL_CONTINUOUS_M 0x1ULL
#define DMA_CHAN_CTRL_CONTINUOUS_SHIFT 1
#define DMA_CHAN_CTRL_CONTINUOUS_MASK (DMA_CHAN_CTRL_CONTINUOUS_M << \
		DMA_CHAN_CTRL_CONTINUOUS_SHIFT)
#define DMA_CHAN_CTRL_STOP_M 0x1ULL
#define DMA_CHAN_CTRL_STOP_SHIFT 2
#define DMA_CHAN_CTRL_STOP_MASK (DMA_CHAN_CTRL_STOP_M << \
		DMA_CHAN_CTRL_STOP_SHIFT)
#define DMA_CHAN_CTRL_CHAN_RESET_M 0x1ULL
#define DMA_CHAN_CTRL_CHAN_RESET_SHIFT 0
#define DMA_CHAN_CTRL_CHAN_RESET_MASK (DMA_CHAN_CTRL_CHAN_RESET_M << \
		DMA_CHAN_CTRL_CHAN_RESET_SHIFT)
#define DMA_CHAN_MODE 0x10
#define DMA_CHAN_MODE_DEF 0x40
#define DMA_CHAN_MODE_ADDR_MODE_M 0x1ULL
#define DMA_CHAN_MODE_ADDR_MODE_SHIFT 8
#define DMA_CHAN_MODE_ADDR_MODE_MASK (DMA_CHAN_MODE_ADDR_MODE_M << \
		DMA_CHAN_MODE_ADDR_MODE_SHIFT)
#define DMA_CHAN_MODE_GATHER_M 0x1ULL
#define DMA_CHAN_MODE_GATHER_SHIFT 9
#define DMA_CHAN_MODE_GATHER_MASK (DMA_CHAN_MODE_GATHER_M << \
		DMA_CHAN_MODE_GATHER_SHIFT)
#define DMA_CHAN_MODE_SRC_M 0x3ULL
#define DMA_CHAN_MODE_SRC_SHIFT 4
#define DMA_CHAN_MODE_SRC_MASK (DMA_CHAN_MODE_SRC_M << DMA_CHAN_MODE_SRC_SHIFT)
#define DMA_CHAN_MODE_CHAN_ENA_M 0x1ULL
#define DMA_CHAN_MODE_CHAN_ENA_SHIFT 0
#define DMA_CHAN_MODE_CHAN_ENA_MASK (DMA_CHAN_MODE_CHAN_ENA_M << \
		DMA_CHAN_MODE_CHAN_ENA_SHIFT)
#define DMA_CHAN_MODE_PRI_M 0x1ULL
#define DMA_CHAN_MODE_PRI_SHIFT 11
#define DMA_CHAN_MODE_PRI_MASK (DMA_CHAN_MODE_PRI_M << DMA_CHAN_MODE_PRI_SHIFT)
#define DMA_CHAN_MODE_SIGN_EXT_M 0x1ULL
#define DMA_CHAN_MODE_SIGN_EXT_SHIFT 10
#define DMA_CHAN_MODE_SIGN_EXT_MASK (DMA_CHAN_MODE_SIGN_EXT_M << \
		DMA_CHAN_MODE_SIGN_EXT_SHIFT)
#define DMA_CHAN_MODE_DST_M 0x3ULL
#define DMA_CHAN_MODE_DST_SHIFT 6
#define DMA_CHAN_MODE_DST_MASK (DMA_CHAN_MODE_DST_M << DMA_CHAN_MODE_DST_SHIFT)
#define DMA_CHAN_IMG_FORMAT 0x18
#define DMA_CHAN_IMG_FORMAT_DEF 0x0
#define DMA_CHAN_IMG_FORMAT_COMPONENTS_M 0x3ULL
#define DMA_CHAN_IMG_FORMAT_COMPONENTS_SHIFT 0
#define DMA_CHAN_IMG_FORMAT_COMPONENTS_MASK \
		(DMA_CHAN_IMG_FORMAT_COMPONENTS_M << \
		DMA_CHAN_IMG_FORMAT_COMPONENTS_SHIFT)
#define DMA_CHAN_IMG_FORMAT_PLANES_M 0x3fULL
#define DMA_CHAN_IMG_FORMAT_PLANES_SHIFT 4
#define DMA_CHAN_IMG_FORMAT_PLANES_MASK (DMA_CHAN_IMG_FORMAT_PLANES_M << \
		DMA_CHAN_IMG_FORMAT_PLANES_SHIFT)
#define DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_M 0x1ULL
#define DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_SHIFT 20
#define DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_MASK \
		(DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_M << \
		DMA_CHAN_IMG_FORMAT_MIPI_RAW_FORMAT_SHIFT)
#define DMA_CHAN_IMG_FORMAT_BIT_DEPTH_M 0x7ULL
#define DMA_CHAN_IMG_FORMAT_BIT_DEPTH_SHIFT 12
#define DMA_CHAN_IMG_FORMAT_BIT_DEPTH_MASK (DMA_CHAN_IMG_FORMAT_BIT_DEPTH_M << \
		DMA_CHAN_IMG_FORMAT_BIT_DEPTH_SHIFT)
#define DMA_CHAN_IMG_FORMAT_BLOCK_4X4_M 0x1ULL
#define DMA_CHAN_IMG_FORMAT_BLOCK_4X4_SHIFT 26
#define DMA_CHAN_IMG_FORMAT_BLOCK_4X4_MASK (DMA_CHAN_IMG_FORMAT_BLOCK_4X4_M << \
		DMA_CHAN_IMG_FORMAT_BLOCK_4X4_SHIFT)
#define DMA_CHAN_IMG_SIZE 0x20
#define DMA_CHAN_IMG_SIZE_DEF 0x200080
#define DMA_CHAN_IMG_SIZE_IMG_HEIGHT_M 0xffffULL
#define DMA_CHAN_IMG_SIZE_IMG_HEIGHT_SHIFT 16
#define DMA_CHAN_IMG_SIZE_IMG_HEIGHT_MASK (DMA_CHAN_IMG_SIZE_IMG_HEIGHT_M << \
		DMA_CHAN_IMG_SIZE_IMG_HEIGHT_SHIFT)
#define DMA_CHAN_IMG_SIZE_IMG_WIDTH_M 0xffffULL
#define DMA_CHAN_IMG_SIZE_IMG_WIDTH_SHIFT 0
#define DMA_CHAN_IMG_SIZE_IMG_WIDTH_MASK (DMA_CHAN_IMG_SIZE_IMG_WIDTH_M << \
		DMA_CHAN_IMG_SIZE_IMG_WIDTH_SHIFT)
#define DMA_CHAN_IMG_POS 0x28
#define DMA_CHAN_IMG_POS_DEF 0x0
#define DMA_CHAN_IMG_POS_START_X_M 0xffffULL
#define DMA_CHAN_IMG_POS_START_X_SHIFT 0
#define DMA_CHAN_IMG_POS_START_X_MASK (DMA_CHAN_IMG_POS_START_X_M << \
		DMA_CHAN_IMG_POS_START_X_SHIFT)
#define DMA_CHAN_IMG_POS_START_Y_M 0xffffULL
#define DMA_CHAN_IMG_POS_START_Y_SHIFT 16
#define DMA_CHAN_IMG_POS_START_Y_MASK (DMA_CHAN_IMG_POS_START_Y_M << \
		DMA_CHAN_IMG_POS_START_Y_SHIFT)
#define DMA_CHAN_IMG_POS_LB_START_X_M 0xffffULL
#define DMA_CHAN_IMG_POS_LB_START_X_SHIFT 32
#define DMA_CHAN_IMG_POS_LB_START_X_MASK (DMA_CHAN_IMG_POS_LB_START_X_M << \
		DMA_CHAN_IMG_POS_LB_START_X_SHIFT)
#define DMA_CHAN_IMG_POS_LB_START_Y_M 0xffffULL
#define DMA_CHAN_IMG_POS_LB_START_Y_SHIFT 48
#define DMA_CHAN_IMG_POS_LB_START_Y_MASK (DMA_CHAN_IMG_POS_LB_START_Y_M << \
		DMA_CHAN_IMG_POS_LB_START_Y_SHIFT)
#define DMA_CHAN_IMG_LAYOUT 0x30
#define DMA_CHAN_IMG_LAYOUT_DEF 0x0
#define DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_M 0x7ffffffffULL
#define DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_SHIFT 0
#define DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_MASK \
		(DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_M << \
		DMA_CHAN_IMG_LAYOUT_PLANE_STRIDE_SHIFT)
#define DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_M 0xffffULL
#define DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_SHIFT 35
#define DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_MASK \
		(DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_M << \
		DMA_CHAN_IMG_LAYOUT_ROW_STRIDE_SHIFT)
#define DMA_CHAN_BIF_XFER 0x38
#define DMA_CHAN_BIF_XFER_DEF 0x100004
#define DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_M 0xffffULL
#define DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_SHIFT 0
#define DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_MASK \
		(DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_M << \
		DMA_CHAN_BIF_XFER_STRIPE_HEIGHT_SHIFT)
#define DMA_CHAN_BIF_XFER_OUTSTANDING_M 0x7fULL
#define DMA_CHAN_BIF_XFER_OUTSTANDING_SHIFT 16
#define DMA_CHAN_BIF_XFER_OUTSTANDING_MASK (DMA_CHAN_BIF_XFER_OUTSTANDING_M << \
		DMA_CHAN_BIF_XFER_OUTSTANDING_SHIFT)
#define DMA_CHAN_VA 0x40
#define DMA_CHAN_VA_DEF 0x0
#define DMA_CHAN_VA_BASE_M 0x7ffffffffffULL
#define DMA_CHAN_VA_BASE_SHIFT 0
#define DMA_CHAN_VA_BASE_MASK (DMA_CHAN_VA_BASE_M << DMA_CHAN_VA_BASE_SHIFT)
#define DMA_CHAN_VA_BDRY 0x48
#define DMA_CHAN_VA_BDRY_DEF 0x0
#define DMA_CHAN_VA_BDRY_LEN_M 0x1ffffffffffULL
#define DMA_CHAN_VA_BDRY_LEN_SHIFT 0
#define DMA_CHAN_VA_BDRY_LEN_MASK (DMA_CHAN_VA_BDRY_LEN_M << \
		DMA_CHAN_VA_BDRY_LEN_SHIFT)
#define DMA_CHAN_NOC_XFER 0x50
#define DMA_CHAN_NOC_XFER_DEF 0x6400804040
#define DMA_CHAN_NOC_XFER_SHEET_WIDTH_M 0x1ffULL
#define DMA_CHAN_NOC_XFER_SHEET_WIDTH_SHIFT 0
#define DMA_CHAN_NOC_XFER_SHEET_WIDTH_MASK (DMA_CHAN_NOC_XFER_SHEET_WIDTH_M << \
		DMA_CHAN_NOC_XFER_SHEET_WIDTH_SHIFT)
#define DMA_CHAN_NOC_XFER_OUTSTANDING_M 0xfULL
#define DMA_CHAN_NOC_XFER_OUTSTANDING_SHIFT 20
#define DMA_CHAN_NOC_XFER_OUTSTANDING_MASK (DMA_CHAN_NOC_XFER_OUTSTANDING_M << \
		DMA_CHAN_NOC_XFER_OUTSTANDING_SHIFT)
#define DMA_CHAN_NOC_XFER_SHEET_HEIGHT_M 0x1fULL
#define DMA_CHAN_NOC_XFER_SHEET_HEIGHT_SHIFT 12
#define DMA_CHAN_NOC_XFER_SHEET_HEIGHT_MASK \
		(DMA_CHAN_NOC_XFER_SHEET_HEIGHT_M << \
		DMA_CHAN_NOC_XFER_SHEET_HEIGHT_SHIFT)
#define DMA_CHAN_NOC_XFER_RETRY_INTERVAL_M 0x3ffULL
#define DMA_CHAN_NOC_XFER_RETRY_INTERVAL_SHIFT 32
#define DMA_CHAN_NOC_XFER_RETRY_INTERVAL_MASK \
		(DMA_CHAN_NOC_XFER_RETRY_INTERVAL_M << \
		DMA_CHAN_NOC_XFER_RETRY_INTERVAL_SHIFT)
#define DMA_CHAN_SSP_CFG 0x58
#define DMA_CHAN_SSP_CFG_DEF 0x530410
#define DMA_CHAN_SSP_CFG_PTRS_FIFO_DEPTH_M 0x7ULL
#define DMA_CHAN_SSP_CFG_PTRS_FIFO_DEPTH_SHIFT 20
#define DMA_CHAN_SSP_CFG_PTRS_FIFO_DEPTH_MASK \
		(DMA_CHAN_SSP_CFG_PTRS_FIFO_DEPTH_M << \
		DMA_CHAN_SSP_CFG_PTRS_FIFO_DEPTH_SHIFT)
#define DMA_CHAN_SSP_CFG_MULT_SHEETS_M 0x1ULL
#define DMA_CHAN_SSP_CFG_MULT_SHEETS_SHIFT 16
#define DMA_CHAN_SSP_CFG_MULT_SHEETS_MASK (DMA_CHAN_SSP_CFG_MULT_SHEETS_M << \
		DMA_CHAN_SSP_CFG_MULT_SHEETS_SHIFT)
#define DMA_CHAN_SSP_CFG_MULT_SEGS_M 0x1ULL
#define DMA_CHAN_SSP_CFG_MULT_SEGS_SHIFT 17
#define DMA_CHAN_SSP_CFG_MULT_SEGS_MASK (DMA_CHAN_SSP_CFG_MULT_SEGS_M << \
		DMA_CHAN_SSP_CFG_MULT_SEGS_SHIFT)
#define DMA_CHAN_SSP_CFG_PIX_PER_LOC_M 0x1fULL
#define DMA_CHAN_SSP_CFG_PIX_PER_LOC_SHIFT 0
#define DMA_CHAN_SSP_CFG_PIX_PER_LOC_MASK (DMA_CHAN_SSP_CFG_PIX_PER_LOC_M << \
		DMA_CHAN_SSP_CFG_PIX_PER_LOC_SHIFT)
#define DMA_CHAN_SSP_CFG_LOCS_PER_ROW_M 0x1fULL
#define DMA_CHAN_SSP_CFG_LOCS_PER_ROW_SHIFT 8
#define DMA_CHAN_SSP_CFG_LOCS_PER_ROW_MASK (DMA_CHAN_SSP_CFG_LOCS_PER_ROW_M << \
		DMA_CHAN_SSP_CFG_LOCS_PER_ROW_SHIFT)
#define DMA_CHAN_NODE 0x60
#define DMA_CHAN_NODE_DEF 0x0
#define DMA_CHAN_NODE_CORE_ID_M 0xfULL
#define DMA_CHAN_NODE_CORE_ID_SHIFT 0
#define DMA_CHAN_NODE_CORE_ID_MASK (DMA_CHAN_NODE_CORE_ID_M << \
		DMA_CHAN_NODE_CORE_ID_SHIFT)
#define DMA_CHAN_NODE_LB_ID_M 0x7ULL
#define DMA_CHAN_NODE_LB_ID_SHIFT 8
#define DMA_CHAN_NODE_LB_ID_MASK (DMA_CHAN_NODE_LB_ID_M << \
		DMA_CHAN_NODE_LB_ID_SHIFT)
#define DMA_CHAN_NODE_SLICE_ID_WIDTH_M 0x3ULL
#define DMA_CHAN_NODE_SLICE_ID_WIDTH_SHIFT 28
#define DMA_CHAN_NODE_SLICE_ID_WIDTH_MASK (DMA_CHAN_NODE_SLICE_ID_WIDTH_M << \
		DMA_CHAN_NODE_SLICE_ID_WIDTH_SHIFT)
#define DMA_CHAN_NODE_SLICE_ID_LSB_M 0xfULL
#define DMA_CHAN_NODE_SLICE_ID_LSB_SHIFT 32
#define DMA_CHAN_NODE_SLICE_ID_LSB_MASK (DMA_CHAN_NODE_SLICE_ID_LSB_M << \
		DMA_CHAN_NODE_SLICE_ID_LSB_SHIFT)
#define DMA_CHAN_NODE_RPTR_ID_M 0x7ULL
#define DMA_CHAN_NODE_RPTR_ID_SHIFT 16
#define DMA_CHAN_NODE_RPTR_ID_MASK (DMA_CHAN_NODE_RPTR_ID_M << \
		DMA_CHAN_NODE_RPTR_ID_SHIFT)
#define DMA_CHAN_NODE_NOC_PORT_M 0x1ULL
#define DMA_CHAN_NODE_NOC_PORT_SHIFT 24
#define DMA_CHAN_NODE_NOC_PORT_MASK (DMA_CHAN_NODE_NOC_PORT_M << \
		DMA_CHAN_NODE_NOC_PORT_SHIFT)
#define DMA_CHAN_MODE_RO 0x68
#define DMA_CHAN_MODE_RO_DEF 0x40
#define DMA_CHAN_MODE_RO_GATHER_M 0x1ULL
#define DMA_CHAN_MODE_RO_GATHER_SHIFT 9
#define DMA_CHAN_MODE_RO_GATHER_MASK (DMA_CHAN_MODE_RO_GATHER_M << \
		DMA_CHAN_MODE_RO_GATHER_SHIFT)
#define DMA_CHAN_MODE_RO_ADDR_MODE_M 0x1ULL
#define DMA_CHAN_MODE_RO_ADDR_MODE_SHIFT 8
#define DMA_CHAN_MODE_RO_ADDR_MODE_MASK (DMA_CHAN_MODE_RO_ADDR_MODE_M << \
		DMA_CHAN_MODE_RO_ADDR_MODE_SHIFT)
#define DMA_CHAN_MODE_RO_SIGN_EXT_M 0x1ULL
#define DMA_CHAN_MODE_RO_SIGN_EXT_SHIFT 10
#define DMA_CHAN_MODE_RO_SIGN_EXT_MASK (DMA_CHAN_MODE_RO_SIGN_EXT_M << \
		DMA_CHAN_MODE_RO_SIGN_EXT_SHIFT)
#define DMA_CHAN_MODE_RO_CHAN_ENA_M 0x1ULL
#define DMA_CHAN_MODE_RO_CHAN_ENA_SHIFT 0
#define DMA_CHAN_MODE_RO_CHAN_ENA_MASK (DMA_CHAN_MODE_RO_CHAN_ENA_M << \
		DMA_CHAN_MODE_RO_CHAN_ENA_SHIFT)
#define DMA_CHAN_MODE_RO_PRI_M 0x1ULL
#define DMA_CHAN_MODE_RO_PRI_SHIFT 11
#define DMA_CHAN_MODE_RO_PRI_MASK (DMA_CHAN_MODE_RO_PRI_M << \
		DMA_CHAN_MODE_RO_PRI_SHIFT)
#define DMA_CHAN_MODE_RO_SRC_M 0x3ULL
#define DMA_CHAN_MODE_RO_SRC_SHIFT 4
#define DMA_CHAN_MODE_RO_SRC_MASK (DMA_CHAN_MODE_RO_SRC_M << \
		DMA_CHAN_MODE_RO_SRC_SHIFT)
#define DMA_CHAN_MODE_RO_DST_M 0x3ULL
#define DMA_CHAN_MODE_RO_DST_SHIFT 6
#define DMA_CHAN_MODE_RO_DST_MASK (DMA_CHAN_MODE_RO_DST_M << \
		DMA_CHAN_MODE_RO_DST_SHIFT)
#define DMA_CHAN_IMG_FORMAT_RO 0x70
#define DMA_CHAN_IMG_FORMAT_RO_DEF 0x0
#define DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_M 0x7ULL
#define DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_SHIFT 12
#define DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_MASK \
		(DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_M << \
		DMA_CHAN_IMG_FORMAT_RO_BIT_DEPTH_SHIFT)
#define DMA_CHAN_IMG_FORMAT_RO_PLANES_M 0x3fULL
#define DMA_CHAN_IMG_FORMAT_RO_PLANES_SHIFT 4
#define DMA_CHAN_IMG_FORMAT_RO_PLANES_MASK (DMA_CHAN_IMG_FORMAT_RO_PLANES_M << \
		DMA_CHAN_IMG_FORMAT_RO_PLANES_SHIFT)
#define DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_M 0x3ULL
#define DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_SHIFT 0
#define DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_MASK \
		(DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_M << \
		DMA_CHAN_IMG_FORMAT_RO_COMPONENTS_SHIFT)
#define DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_M 0x1ULL
#define DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_SHIFT 26
#define DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_MASK \
		(DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_M << \
		DMA_CHAN_IMG_FORMAT_RO_BLOCK_4X4_SHIFT)
#define DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_M 0x1ULL
#define DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_SHIFT 20
#define DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_MASK \
		(DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_M << \
		DMA_CHAN_IMG_FORMAT_RO_MIPI_RAW_FORMAT_SHIFT)
#define DMA_CHAN_IMG_SIZE_RO 0x78
#define DMA_CHAN_IMG_SIZE_RO_DEF 0x200080
#define DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_M 0xffffULL
#define DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_SHIFT 16
#define DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_MASK \
		(DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_M << \
		DMA_CHAN_IMG_SIZE_RO_IMG_HEIGHT_SHIFT)
#define DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_M 0xffffULL
#define DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_SHIFT 0
#define DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_MASK \
		(DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_M << \
		DMA_CHAN_IMG_SIZE_RO_IMG_WIDTH_SHIFT)
#define DMA_CHAN_IMG_POS_RO 0x80
#define DMA_CHAN_IMG_POS_RO_DEF 0x0
#define DMA_CHAN_IMG_POS_RO_LB_START_Y_M 0xffffULL
#define DMA_CHAN_IMG_POS_RO_LB_START_Y_SHIFT 48
#define DMA_CHAN_IMG_POS_RO_LB_START_Y_MASK \
		(DMA_CHAN_IMG_POS_RO_LB_START_Y_M << \
		DMA_CHAN_IMG_POS_RO_LB_START_Y_SHIFT)
#define DMA_CHAN_IMG_POS_RO_LB_START_X_M 0xffffULL
#define DMA_CHAN_IMG_POS_RO_LB_START_X_SHIFT 32
#define DMA_CHAN_IMG_POS_RO_LB_START_X_MASK \
		(DMA_CHAN_IMG_POS_RO_LB_START_X_M << \
		DMA_CHAN_IMG_POS_RO_LB_START_X_SHIFT)
#define DMA_CHAN_IMG_POS_RO_START_Y_M 0xffffULL
#define DMA_CHAN_IMG_POS_RO_START_Y_SHIFT 16
#define DMA_CHAN_IMG_POS_RO_START_Y_MASK (DMA_CHAN_IMG_POS_RO_START_Y_M << \
		DMA_CHAN_IMG_POS_RO_START_Y_SHIFT)
#define DMA_CHAN_IMG_POS_RO_START_X_M 0xffffULL
#define DMA_CHAN_IMG_POS_RO_START_X_SHIFT 0
#define DMA_CHAN_IMG_POS_RO_START_X_MASK (DMA_CHAN_IMG_POS_RO_START_X_M << \
		DMA_CHAN_IMG_POS_RO_START_X_SHIFT)
#define DMA_CHAN_IMG_LAYOUT_RO 0x88
#define DMA_CHAN_IMG_LAYOUT_RO_DEF 0x0
#define DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_M 0xffffULL
#define DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_SHIFT 35
#define DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_MASK \
		(DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_M << \
		DMA_CHAN_IMG_LAYOUT_RO_ROW_STRIDE_SHIFT)
#define DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_M 0x7ffffffffULL
#define DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_SHIFT 0
#define DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_MASK \
		(DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_M << \
		DMA_CHAN_IMG_LAYOUT_RO_PLANE_STRIDE_SHIFT)
#define DMA_CHAN_BIF_XFER_RO 0x90
#define DMA_CHAN_BIF_XFER_RO_DEF 0x100004
#define DMA_CHAN_BIF_XFER_RO_OUTSTANDING_M 0x7fULL
#define DMA_CHAN_BIF_XFER_RO_OUTSTANDING_SHIFT 16
#define DMA_CHAN_BIF_XFER_RO_OUTSTANDING_MASK \
		(DMA_CHAN_BIF_XFER_RO_OUTSTANDING_M << \
		DMA_CHAN_BIF_XFER_RO_OUTSTANDING_SHIFT)
#define DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_M 0xffffULL
#define DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_SHIFT 0
#define DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_MASK \
		(DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_M << \
		DMA_CHAN_BIF_XFER_RO_STRIPE_HEIGHT_SHIFT)
#define DMA_CHAN_VA_RO 0x98
#define DMA_CHAN_VA_RO_DEF 0x0
#define DMA_CHAN_VA_RO_BASE_M 0x7ffffffffffULL
#define DMA_CHAN_VA_RO_BASE_SHIFT 0
#define DMA_CHAN_VA_RO_BASE_MASK (DMA_CHAN_VA_RO_BASE_M << \
		DMA_CHAN_VA_RO_BASE_SHIFT)
#define DMA_CHAN_VA_BDRY_RO 0xa0
#define DMA_CHAN_VA_BDRY_RO_DEF 0x0
#define DMA_CHAN_VA_BDRY_RO_LEN_M 0x1ffffffffffULL
#define DMA_CHAN_VA_BDRY_RO_LEN_SHIFT 0
#define DMA_CHAN_VA_BDRY_RO_LEN_MASK (DMA_CHAN_VA_BDRY_RO_LEN_M << \
		DMA_CHAN_VA_BDRY_RO_LEN_SHIFT)
#define DMA_CHAN_NOC_XFER_RO 0xa8
#define DMA_CHAN_NOC_XFER_RO_DEF 0x6400804040
#define DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_M 0x1ffULL
#define DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_SHIFT 0
#define DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_MASK \
		(DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_M << \
		DMA_CHAN_NOC_XFER_RO_SHEET_WIDTH_SHIFT)
#define DMA_CHAN_NOC_XFER_RO_OUTSTANDING_M 0xfULL
#define DMA_CHAN_NOC_XFER_RO_OUTSTANDING_SHIFT 20
#define DMA_CHAN_NOC_XFER_RO_OUTSTANDING_MASK \
		(DMA_CHAN_NOC_XFER_RO_OUTSTANDING_M << \
		DMA_CHAN_NOC_XFER_RO_OUTSTANDING_SHIFT)
#define DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_M 0x3ffULL
#define DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_SHIFT 32
#define DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_MASK \
		(DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_M << \
		DMA_CHAN_NOC_XFER_RO_RETRY_INTERVAL_SHIFT)
#define DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_M 0x1fULL
#define DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_SHIFT 12
#define DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_MASK \
		(DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_M << \
		DMA_CHAN_NOC_XFER_RO_SHEET_HEIGHT_SHIFT)
#define DMA_CHAN_SSP_CFG_RO 0xb0
#define DMA_CHAN_SSP_CFG_RO_DEF 0x530410
#define DMA_CHAN_SSP_CFG_RO_MULT_SEGS_M 0x1ULL
#define DMA_CHAN_SSP_CFG_RO_MULT_SEGS_SHIFT 17
#define DMA_CHAN_SSP_CFG_RO_MULT_SEGS_MASK (DMA_CHAN_SSP_CFG_RO_MULT_SEGS_M << \
		DMA_CHAN_SSP_CFG_RO_MULT_SEGS_SHIFT)
#define DMA_CHAN_SSP_CFG_RO_PTRS_FIFO_DEPTH_M 0x7ULL
#define DMA_CHAN_SSP_CFG_RO_PTRS_FIFO_DEPTH_SHIFT 20
#define DMA_CHAN_SSP_CFG_RO_PTRS_FIFO_DEPTH_MASK \
		(DMA_CHAN_SSP_CFG_RO_PTRS_FIFO_DEPTH_M << \
		DMA_CHAN_SSP_CFG_RO_PTRS_FIFO_DEPTH_SHIFT)
#define DMA_CHAN_SSP_CFG_RO_MULT_SHEETS_M 0x1ULL
#define DMA_CHAN_SSP_CFG_RO_MULT_SHEETS_SHIFT 16
#define DMA_CHAN_SSP_CFG_RO_MULT_SHEETS_MASK \
		(DMA_CHAN_SSP_CFG_RO_MULT_SHEETS_M << \
		DMA_CHAN_SSP_CFG_RO_MULT_SHEETS_SHIFT)
#define DMA_CHAN_SSP_CFG_RO_PIX_PER_LOC_M 0x1fULL
#define DMA_CHAN_SSP_CFG_RO_PIX_PER_LOC_SHIFT 0
#define DMA_CHAN_SSP_CFG_RO_PIX_PER_LOC_MASK \
		(DMA_CHAN_SSP_CFG_RO_PIX_PER_LOC_M << \
		DMA_CHAN_SSP_CFG_RO_PIX_PER_LOC_SHIFT)
#define DMA_CHAN_SSP_CFG_RO_LOCS_PER_ROW_M 0x1fULL
#define DMA_CHAN_SSP_CFG_RO_LOCS_PER_ROW_SHIFT 8
#define DMA_CHAN_SSP_CFG_RO_LOCS_PER_ROW_MASK \
		(DMA_CHAN_SSP_CFG_RO_LOCS_PER_ROW_M << \
		DMA_CHAN_SSP_CFG_RO_LOCS_PER_ROW_SHIFT)
#define DMA_CHAN_NODE_RO 0xb8
#define DMA_CHAN_NODE_RO_DEF 0x0
#define DMA_CHAN_NODE_RO_SLICE_ID_WIDTH_M 0x3ULL
#define DMA_CHAN_NODE_RO_SLICE_ID_WIDTH_SHIFT 28
#define DMA_CHAN_NODE_RO_SLICE_ID_WIDTH_MASK \
		(DMA_CHAN_NODE_RO_SLICE_ID_WIDTH_M << \
		DMA_CHAN_NODE_RO_SLICE_ID_WIDTH_SHIFT)
#define DMA_CHAN_NODE_RO_RPTR_ID_M 0x7ULL
#define DMA_CHAN_NODE_RO_RPTR_ID_SHIFT 16
#define DMA_CHAN_NODE_RO_RPTR_ID_MASK (DMA_CHAN_NODE_RO_RPTR_ID_M << \
		DMA_CHAN_NODE_RO_RPTR_ID_SHIFT)
#define DMA_CHAN_NODE_RO_NOC_PORT_M 0x1ULL
#define DMA_CHAN_NODE_RO_NOC_PORT_SHIFT 24
#define DMA_CHAN_NODE_RO_NOC_PORT_MASK (DMA_CHAN_NODE_RO_NOC_PORT_M << \
		DMA_CHAN_NODE_RO_NOC_PORT_SHIFT)
#define DMA_CHAN_NODE_RO_SLICE_ID_LSB_M 0xfULL
#define DMA_CHAN_NODE_RO_SLICE_ID_LSB_SHIFT 32
#define DMA_CHAN_NODE_RO_SLICE_ID_LSB_MASK (DMA_CHAN_NODE_RO_SLICE_ID_LSB_M << \
		DMA_CHAN_NODE_RO_SLICE_ID_LSB_SHIFT)
#define DMA_CHAN_NODE_RO_CORE_ID_M 0xfULL
#define DMA_CHAN_NODE_RO_CORE_ID_SHIFT 0
#define DMA_CHAN_NODE_RO_CORE_ID_MASK (DMA_CHAN_NODE_RO_CORE_ID_M << \
		DMA_CHAN_NODE_RO_CORE_ID_SHIFT)
#define DMA_CHAN_NODE_RO_LB_ID_M 0x7ULL
#define DMA_CHAN_NODE_RO_LB_ID_SHIFT 8
#define DMA_CHAN_NODE_RO_LB_ID_MASK (DMA_CHAN_NODE_RO_LB_ID_M << \
		DMA_CHAN_NODE_RO_LB_ID_SHIFT)
#define DMA_GRP_SPARE 0xc0
#define DMA_GRP_SPARE_DEF 0x0
#define DMA_GRP_SPARE_SPARE8_M 0x1ULL
#define DMA_GRP_SPARE_SPARE8_SHIFT 8
#define DMA_GRP_SPARE_SPARE8_MASK (DMA_GRP_SPARE_SPARE8_M << \
		DMA_GRP_SPARE_SPARE8_SHIFT)
#define DMA_GRP_SPARE_SPARE9_M 0x1ULL
#define DMA_GRP_SPARE_SPARE9_SHIFT 9
#define DMA_GRP_SPARE_SPARE9_MASK (DMA_GRP_SPARE_SPARE9_M << \
		DMA_GRP_SPARE_SPARE9_SHIFT)
#define DMA_GRP_SPARE_SPARE0_M 0x1ULL
#define DMA_GRP_SPARE_SPARE0_SHIFT 0
#define DMA_GRP_SPARE_SPARE0_MASK (DMA_GRP_SPARE_SPARE0_M << \
		DMA_GRP_SPARE_SPARE0_SHIFT)
#define DMA_GRP_SPARE_SPARE1_M 0x1ULL
#define DMA_GRP_SPARE_SPARE1_SHIFT 1
#define DMA_GRP_SPARE_SPARE1_MASK (DMA_GRP_SPARE_SPARE1_M << \
		DMA_GRP_SPARE_SPARE1_SHIFT)
#define DMA_GRP_SPARE_SPARE2_M 0x1ULL
#define DMA_GRP_SPARE_SPARE2_SHIFT 2
#define DMA_GRP_SPARE_SPARE2_MASK (DMA_GRP_SPARE_SPARE2_M << \
		DMA_GRP_SPARE_SPARE2_SHIFT)
#define DMA_GRP_SPARE_SPARE3_M 0x1ULL
#define DMA_GRP_SPARE_SPARE3_SHIFT 3
#define DMA_GRP_SPARE_SPARE3_MASK (DMA_GRP_SPARE_SPARE3_M << \
		DMA_GRP_SPARE_SPARE3_SHIFT)
#define DMA_GRP_SPARE_SPARE4_M 0x1ULL
#define DMA_GRP_SPARE_SPARE4_SHIFT 4
#define DMA_GRP_SPARE_SPARE4_MASK (DMA_GRP_SPARE_SPARE4_M << \
		DMA_GRP_SPARE_SPARE4_SHIFT)
#define DMA_GRP_SPARE_SPARE5_M 0x1ULL
#define DMA_GRP_SPARE_SPARE5_SHIFT 5
#define DMA_GRP_SPARE_SPARE5_MASK (DMA_GRP_SPARE_SPARE5_M << \
		DMA_GRP_SPARE_SPARE5_SHIFT)
#define DMA_GRP_SPARE_SPARE6_M 0x1ULL
#define DMA_GRP_SPARE_SPARE6_SHIFT 6
#define DMA_GRP_SPARE_SPARE6_MASK (DMA_GRP_SPARE_SPARE6_M << \
		DMA_GRP_SPARE_SPARE6_SHIFT)
#define DMA_GRP_SPARE_SPARE7_M 0x1ULL
#define DMA_GRP_SPARE_SPARE7_SHIFT 7
#define DMA_GRP_SPARE_SPARE7_MASK (DMA_GRP_SPARE_SPARE7_M << \
		DMA_GRP_SPARE_SPARE7_SHIFT)
#define DMA_GRP_SPARE_SPARE12_M 0x1ULL
#define DMA_GRP_SPARE_SPARE12_SHIFT 12
#define DMA_GRP_SPARE_SPARE12_MASK (DMA_GRP_SPARE_SPARE12_M << \
		DMA_GRP_SPARE_SPARE12_SHIFT)
#define DMA_GRP_SPARE_SPARE13_M 0x1ULL
#define DMA_GRP_SPARE_SPARE13_SHIFT 13
#define DMA_GRP_SPARE_SPARE13_MASK (DMA_GRP_SPARE_SPARE13_M << \
		DMA_GRP_SPARE_SPARE13_SHIFT)
#define DMA_GRP_SPARE_SPARE10_M 0x1ULL
#define DMA_GRP_SPARE_SPARE10_SHIFT 10
#define DMA_GRP_SPARE_SPARE10_MASK (DMA_GRP_SPARE_SPARE10_M << \
		DMA_GRP_SPARE_SPARE10_SHIFT)
#define DMA_GRP_SPARE_SPARE11_M 0x1ULL
#define DMA_GRP_SPARE_SPARE11_SHIFT 11
#define DMA_GRP_SPARE_SPARE11_MASK (DMA_GRP_SPARE_SPARE11_M << \
		DMA_GRP_SPARE_SPARE11_SHIFT)
#define DMA_GRP_SPARE_SPARE14_M 0x1ULL
#define DMA_GRP_SPARE_SPARE14_SHIFT 14
#define DMA_GRP_SPARE_SPARE14_MASK (DMA_GRP_SPARE_SPARE14_M << \
		DMA_GRP_SPARE_SPARE14_SHIFT)
#define DMA_GRP_SPARE_SPARE15_M 0x1ULL
#define DMA_GRP_SPARE_SPARE15_SHIFT 15
#define DMA_GRP_SPARE_SPARE15_MASK (DMA_GRP_SPARE_SPARE15_M << \
		DMA_GRP_SPARE_SPARE15_SHIFT)

/* Module : IPU_LIB_DREGFILE_DMA_TOP*/
#define DMA_CTRL 0x0
#define DMA_CTRL_DEF 0x0
#define DMA_CTRL_DMA_RESET_M 0x1ULL
#define DMA_CTRL_DMA_RESET_SHIFT 0
#define DMA_CTRL_DMA_RESET_MASK (DMA_CTRL_DMA_RESET_M << \
		DMA_CTRL_DMA_RESET_SHIFT)
#define DMA_CTRL_AXI_SWIZZLE_M 0x3ULL
#define DMA_CTRL_AXI_SWIZZLE_SHIFT 1
#define DMA_CTRL_AXI_SWIZZLE_MASK (DMA_CTRL_AXI_SWIZZLE_M << \
		DMA_CTRL_AXI_SWIZZLE_SHIFT)
#define DMA_IRQ_ISR 0x8
#define DMA_IRQ_ISR_DEF 0x0
#define DMA_IRQ_ISR_EOF_INTR_M 0xffffffffULL
#define DMA_IRQ_ISR_EOF_INTR_SHIFT 0
#define DMA_IRQ_ISR_EOF_INTR_MASK (DMA_IRQ_ISR_EOF_INTR_M << \
		DMA_IRQ_ISR_EOF_INTR_SHIFT)
#define DMA_IRQ_VA_ERR_ISR 0x10
#define DMA_IRQ_VA_ERR_ISR_DEF 0x0
#define DMA_IRQ_VA_ERR_ISR_VA_ERR_M 0xffffffffULL
#define DMA_IRQ_VA_ERR_ISR_VA_ERR_SHIFT 0
#define DMA_IRQ_VA_ERR_ISR_VA_ERR_MASK (DMA_IRQ_VA_ERR_ISR_VA_ERR_M << \
		DMA_IRQ_VA_ERR_ISR_VA_ERR_SHIFT)
#define DMA_IRQ_SSP_ERR_ISR 0x18
#define DMA_IRQ_SSP_ERR_ISR_DEF 0x0
#define DMA_IRQ_SSP_ERR_ISR_SSP_ERR_M 0x1ULL
#define DMA_IRQ_SSP_ERR_ISR_SSP_ERR_SHIFT 0
#define DMA_IRQ_SSP_ERR_ISR_SSP_ERR_MASK (DMA_IRQ_SSP_ERR_ISR_SSP_ERR_M << \
		DMA_IRQ_SSP_ERR_ISR_SSP_ERR_SHIFT)
#define DMA_IRQ_ITR 0x20
#define DMA_IRQ_ITR_DEF 0x0
#define DMA_IRQ_ITR_EOF_INTR_M 0xffffffffULL
#define DMA_IRQ_ITR_EOF_INTR_SHIFT 0
#define DMA_IRQ_ITR_EOF_INTR_MASK (DMA_IRQ_ITR_EOF_INTR_M << \
		DMA_IRQ_ITR_EOF_INTR_SHIFT)
#define DMA_IRQ_VA_ERR_ITR 0x28
#define DMA_IRQ_VA_ERR_ITR_DEF 0x0
#define DMA_IRQ_VA_ERR_ITR_VA_ERR_M 0xffffffffULL
#define DMA_IRQ_VA_ERR_ITR_VA_ERR_SHIFT 0
#define DMA_IRQ_VA_ERR_ITR_VA_ERR_MASK (DMA_IRQ_VA_ERR_ITR_VA_ERR_M << \
		DMA_IRQ_VA_ERR_ITR_VA_ERR_SHIFT)
#define DMA_IRQ_SSP_ERR_ITR 0x30
#define DMA_IRQ_SSP_ERR_ITR_DEF 0x0
#define DMA_IRQ_SSP_ERR_ITR_SSP_ERR_M 0x1ULL
#define DMA_IRQ_SSP_ERR_ITR_SSP_ERR_SHIFT 0
#define DMA_IRQ_SSP_ERR_ITR_SSP_ERR_MASK (DMA_IRQ_SSP_ERR_ITR_SSP_ERR_M << \
		DMA_IRQ_SSP_ERR_ITR_SSP_ERR_SHIFT)
#define DMA_IRQ_IER 0x38
#define DMA_IRQ_IER_DEF 0xffffffff
#define DMA_IRQ_IER_EOF_INTR_M 0xffffffffULL
#define DMA_IRQ_IER_EOF_INTR_SHIFT 0
#define DMA_IRQ_IER_EOF_INTR_MASK (DMA_IRQ_IER_EOF_INTR_M << \
		DMA_IRQ_IER_EOF_INTR_SHIFT)
#define DMA_IRQ_VA_ERR_IER 0x40
#define DMA_IRQ_VA_ERR_IER_DEF 0xffffffff
#define DMA_IRQ_VA_ERR_IER_VA_ERR_M 0xffffffffULL
#define DMA_IRQ_VA_ERR_IER_VA_ERR_SHIFT 0
#define DMA_IRQ_VA_ERR_IER_VA_ERR_MASK (DMA_IRQ_VA_ERR_IER_VA_ERR_M << \
		DMA_IRQ_VA_ERR_IER_VA_ERR_SHIFT)
#define DMA_IRQ_SSP_ERR_IER 0x48
#define DMA_IRQ_SSP_ERR_IER_DEF 0x1
#define DMA_IRQ_SSP_ERR_IER_SSP_ERR_M 0x1ULL
#define DMA_IRQ_SSP_ERR_IER_SSP_ERR_SHIFT 0
#define DMA_IRQ_SSP_ERR_IER_SSP_ERR_MASK (DMA_IRQ_SSP_ERR_IER_SSP_ERR_M << \
		DMA_IRQ_SSP_ERR_IER_SSP_ERR_SHIFT)
#define DMA_IRQ_IMR 0x50
#define DMA_IRQ_IMR_DEF 0x0
#define DMA_IRQ_IMR_EOF_INTR_M 0xffffffffULL
#define DMA_IRQ_IMR_EOF_INTR_SHIFT 0
#define DMA_IRQ_IMR_EOF_INTR_MASK (DMA_IRQ_IMR_EOF_INTR_M << \
		DMA_IRQ_IMR_EOF_INTR_SHIFT)
#define DMA_IRQ_VA_ERR_IMR 0x58
#define DMA_IRQ_VA_ERR_IMR_DEF 0x0
#define DMA_IRQ_VA_ERR_IMR_VA_ERR_M 0xffffffffULL
#define DMA_IRQ_VA_ERR_IMR_VA_ERR_SHIFT 0
#define DMA_IRQ_VA_ERR_IMR_VA_ERR_MASK (DMA_IRQ_VA_ERR_IMR_VA_ERR_M << \
		DMA_IRQ_VA_ERR_IMR_VA_ERR_SHIFT)
#define DMA_IRQ_SSP_ERR_IMR 0x60
#define DMA_IRQ_SSP_ERR_IMR_DEF 0x0
#define DMA_IRQ_SSP_ERR_IMR_SSP_ERR_M 0x1ULL
#define DMA_IRQ_SSP_ERR_IMR_SSP_ERR_SHIFT 0
#define DMA_IRQ_SSP_ERR_IMR_SSP_ERR_MASK (DMA_IRQ_SSP_ERR_IMR_SSP_ERR_M << \
		DMA_IRQ_SSP_ERR_IMR_SSP_ERR_SHIFT)
#define DMA_IRQ_ISR_OVF 0x68
#define DMA_IRQ_ISR_OVF_DEF 0x0
#define DMA_IRQ_ISR_OVF_EOF_INTR_M 0xffffffffULL
#define DMA_IRQ_ISR_OVF_EOF_INTR_SHIFT 0
#define DMA_IRQ_ISR_OVF_EOF_INTR_MASK (DMA_IRQ_ISR_OVF_EOF_INTR_M << \
		DMA_IRQ_ISR_OVF_EOF_INTR_SHIFT)
#define DMA_IRQ_VA_ERR_ISR_OVF 0x70
#define DMA_IRQ_VA_ERR_ISR_OVF_DEF 0x0
#define DMA_IRQ_VA_ERR_ISR_OVF_VA_ERR_M 0xffffffffULL
#define DMA_IRQ_VA_ERR_ISR_OVF_VA_ERR_SHIFT 0
#define DMA_IRQ_VA_ERR_ISR_OVF_VA_ERR_MASK (DMA_IRQ_VA_ERR_ISR_OVF_VA_ERR_M << \
		DMA_IRQ_VA_ERR_ISR_OVF_VA_ERR_SHIFT)
#define DMA_IRQ_SSP_ERR_ISR_OVF 0x78
#define DMA_IRQ_SSP_ERR_ISR_OVF_DEF 0x0
#define DMA_IRQ_SSP_ERR_ISR_OVF_SSP_ERR_M 0x1ULL
#define DMA_IRQ_SSP_ERR_ISR_OVF_SSP_ERR_SHIFT 0
#define DMA_IRQ_SSP_ERR_ISR_OVF_SSP_ERR_MASK \
		(DMA_IRQ_SSP_ERR_ISR_OVF_SSP_ERR_M << \
		DMA_IRQ_SSP_ERR_ISR_OVF_SSP_ERR_SHIFT)
#define DMA_PMON_CFG 0x100
#define DMA_PMON_CFG_DEF 0x0
#define DMA_PMON_CFG_CNT_0_CHAN_M 0x1fULL
#define DMA_PMON_CFG_CNT_0_CHAN_SHIFT 4
#define DMA_PMON_CFG_CNT_0_CHAN_MASK (DMA_PMON_CFG_CNT_0_CHAN_M << \
		DMA_PMON_CFG_CNT_0_CHAN_SHIFT)
#define DMA_PMON_CFG_CNT_1_CHAN_M 0x1fULL
#define DMA_PMON_CFG_CNT_1_CHAN_SHIFT 12
#define DMA_PMON_CFG_CNT_1_CHAN_MASK (DMA_PMON_CFG_CNT_1_CHAN_M << \
		DMA_PMON_CFG_CNT_1_CHAN_SHIFT)
#define DMA_PMON_CFG_ENABLE_M 0x1ULL
#define DMA_PMON_CFG_ENABLE_SHIFT 0
#define DMA_PMON_CFG_ENABLE_MASK (DMA_PMON_CFG_ENABLE_M << \
		DMA_PMON_CFG_ENABLE_SHIFT)
#define DMA_PMON_CNT_0_CFG 0x108
#define DMA_PMON_CNT_0_CFG_DEF 0x0
#define DMA_PMON_CNT_0_CFG_MODE_M 0x7ULL
#define DMA_PMON_CNT_0_CFG_MODE_SHIFT 0
#define DMA_PMON_CNT_0_CFG_MODE_MASK (DMA_PMON_CNT_0_CFG_MODE_M << \
		DMA_PMON_CNT_0_CFG_MODE_SHIFT)
#define DMA_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
#define DMA_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
#define DMA_PMON_CNT_0_CFG_INC_MATCH_MASK (DMA_PMON_CNT_0_CFG_INC_MATCH_M << \
		DMA_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
#define DMA_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
#define DMA_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
#define DMA_PMON_CNT_0_CFG_INC_MASK_MASK (DMA_PMON_CNT_0_CFG_INC_MASK_M << \
		DMA_PMON_CNT_0_CFG_INC_MASK_SHIFT)
#define DMA_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
#define DMA_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
#define DMA_PMON_CNT_0_CFG_DEC_MATCH_MASK (DMA_PMON_CNT_0_CFG_DEC_MATCH_M << \
		DMA_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
#define DMA_PMON_CNT_0_CFG_DEC_SEL_M 0x3fULL
#define DMA_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
#define DMA_PMON_CNT_0_CFG_DEC_SEL_MASK (DMA_PMON_CNT_0_CFG_DEC_SEL_M << \
		DMA_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
#define DMA_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
#define DMA_PMON_CNT_0_CFG_INC_INV_SHIFT 47
#define DMA_PMON_CNT_0_CFG_INC_INV_MASK (DMA_PMON_CNT_0_CFG_INC_INV_M << \
		DMA_PMON_CNT_0_CFG_INC_INV_SHIFT)
#define DMA_PMON_CNT_0_CFG_INC_SEL_M 0x3fULL
#define DMA_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
#define DMA_PMON_CNT_0_CFG_INC_SEL_MASK (DMA_PMON_CNT_0_CFG_INC_SEL_M << \
		DMA_PMON_CNT_0_CFG_INC_SEL_SHIFT)
#define DMA_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
#define DMA_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
#define DMA_PMON_CNT_0_CFG_THRESHOLD_MASK (DMA_PMON_CNT_0_CFG_THRESHOLD_M << \
		DMA_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
#define DMA_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
#define DMA_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
#define DMA_PMON_CNT_0_CFG_DEC_INV_MASK (DMA_PMON_CNT_0_CFG_DEC_INV_M << \
		DMA_PMON_CNT_0_CFG_DEC_INV_SHIFT)
#define DMA_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
#define DMA_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
#define DMA_PMON_CNT_0_CFG_DEC_MASK_MASK (DMA_PMON_CNT_0_CFG_DEC_MASK_M << \
		DMA_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
#define DMA_PMON_CNT_0 0x110
#define DMA_PMON_CNT_0_DEF 0x0
#define DMA_PMON_CNT_0_CNT_M 0xffffffffffULL
#define DMA_PMON_CNT_0_CNT_SHIFT 0
#define DMA_PMON_CNT_0_CNT_MASK (DMA_PMON_CNT_0_CNT_M << \
		DMA_PMON_CNT_0_CNT_SHIFT)
#define DMA_PMON_CNT_0_STS_ACC 0x118
#define DMA_PMON_CNT_0_STS_ACC_DEF 0x0
#define DMA_PMON_CNT_0_STS_ACC_VAL_M 0xffULL
#define DMA_PMON_CNT_0_STS_ACC_VAL_SHIFT 0
#define DMA_PMON_CNT_0_STS_ACC_VAL_MASK (DMA_PMON_CNT_0_STS_ACC_VAL_M << \
		DMA_PMON_CNT_0_STS_ACC_VAL_SHIFT)
#define DMA_PMON_CNT_0_STS 0x120
#define DMA_PMON_CNT_0_STS_DEF 0x0
#define DMA_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
#define DMA_PMON_CNT_0_STS_ACC_UF_SHIFT 1
#define DMA_PMON_CNT_0_STS_ACC_UF_MASK (DMA_PMON_CNT_0_STS_ACC_UF_M << \
		DMA_PMON_CNT_0_STS_ACC_UF_SHIFT)
#define DMA_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
#define DMA_PMON_CNT_0_STS_ACC_OF_SHIFT 0
#define DMA_PMON_CNT_0_STS_ACC_OF_MASK (DMA_PMON_CNT_0_STS_ACC_OF_M << \
		DMA_PMON_CNT_0_STS_ACC_OF_SHIFT)
#define DMA_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
#define DMA_PMON_CNT_0_STS_CNT_OF_SHIFT 2
#define DMA_PMON_CNT_0_STS_CNT_OF_MASK (DMA_PMON_CNT_0_STS_CNT_OF_M << \
		DMA_PMON_CNT_0_STS_CNT_OF_SHIFT)
#define DMA_PMON_CNT_1_CFG 0x128
#define DMA_PMON_CNT_1_CFG_DEF 0x0
#define DMA_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
#define DMA_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
#define DMA_PMON_CNT_1_CFG_DEC_INV_MASK (DMA_PMON_CNT_1_CFG_DEC_INV_M << \
		DMA_PMON_CNT_1_CFG_DEC_INV_SHIFT)
#define DMA_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
#define DMA_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
#define DMA_PMON_CNT_1_CFG_THRESHOLD_MASK (DMA_PMON_CNT_1_CFG_THRESHOLD_M << \
		DMA_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
#define DMA_PMON_CNT_1_CFG_INC_SEL_M 0x3fULL
#define DMA_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
#define DMA_PMON_CNT_1_CFG_INC_SEL_MASK (DMA_PMON_CNT_1_CFG_INC_SEL_M << \
		DMA_PMON_CNT_1_CFG_INC_SEL_SHIFT)
#define DMA_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
#define DMA_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
#define DMA_PMON_CNT_1_CFG_INC_MASK_MASK (DMA_PMON_CNT_1_CFG_INC_MASK_M << \
		DMA_PMON_CNT_1_CFG_INC_MASK_SHIFT)
#define DMA_PMON_CNT_1_CFG_MODE_M 0x7ULL
#define DMA_PMON_CNT_1_CFG_MODE_SHIFT 0
#define DMA_PMON_CNT_1_CFG_MODE_MASK (DMA_PMON_CNT_1_CFG_MODE_M << \
		DMA_PMON_CNT_1_CFG_MODE_SHIFT)
#define DMA_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
#define DMA_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
#define DMA_PMON_CNT_1_CFG_DEC_MATCH_MASK (DMA_PMON_CNT_1_CFG_DEC_MATCH_M << \
		DMA_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
#define DMA_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
#define DMA_PMON_CNT_1_CFG_INC_INV_SHIFT 47
#define DMA_PMON_CNT_1_CFG_INC_INV_MASK (DMA_PMON_CNT_1_CFG_INC_INV_M << \
		DMA_PMON_CNT_1_CFG_INC_INV_SHIFT)
#define DMA_PMON_CNT_1_CFG_DEC_SEL_M 0x3fULL
#define DMA_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
#define DMA_PMON_CNT_1_CFG_DEC_SEL_MASK (DMA_PMON_CNT_1_CFG_DEC_SEL_M << \
		DMA_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
#define DMA_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
#define DMA_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
#define DMA_PMON_CNT_1_CFG_DEC_MASK_MASK (DMA_PMON_CNT_1_CFG_DEC_MASK_M << \
		DMA_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
#define DMA_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
#define DMA_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
#define DMA_PMON_CNT_1_CFG_INC_MATCH_MASK (DMA_PMON_CNT_1_CFG_INC_MATCH_M << \
		DMA_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
#define DMA_PMON_CNT_1 0x130
#define DMA_PMON_CNT_1_DEF 0x0
#define DMA_PMON_CNT_1_CNT_M 0xffffffffffULL
#define DMA_PMON_CNT_1_CNT_SHIFT 0
#define DMA_PMON_CNT_1_CNT_MASK (DMA_PMON_CNT_1_CNT_M << \
		DMA_PMON_CNT_1_CNT_SHIFT)
#define DMA_PMON_CNT_1_STS_ACC 0x138
#define DMA_PMON_CNT_1_STS_ACC_DEF 0x0
#define DMA_PMON_CNT_1_STS_ACC_VAL_M 0xffULL
#define DMA_PMON_CNT_1_STS_ACC_VAL_SHIFT 0
#define DMA_PMON_CNT_1_STS_ACC_VAL_MASK (DMA_PMON_CNT_1_STS_ACC_VAL_M << \
		DMA_PMON_CNT_1_STS_ACC_VAL_SHIFT)
#define DMA_PMON_CNT_1_STS 0x140
#define DMA_PMON_CNT_1_STS_DEF 0x0
#define DMA_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
#define DMA_PMON_CNT_1_STS_CNT_OF_SHIFT 2
#define DMA_PMON_CNT_1_STS_CNT_OF_MASK (DMA_PMON_CNT_1_STS_CNT_OF_M << \
		DMA_PMON_CNT_1_STS_CNT_OF_SHIFT)
#define DMA_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
#define DMA_PMON_CNT_1_STS_ACC_UF_SHIFT 1
#define DMA_PMON_CNT_1_STS_ACC_UF_MASK (DMA_PMON_CNT_1_STS_ACC_UF_M << \
		DMA_PMON_CNT_1_STS_ACC_UF_SHIFT)
#define DMA_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
#define DMA_PMON_CNT_1_STS_ACC_OF_SHIFT 0
#define DMA_PMON_CNT_1_STS_ACC_OF_MASK (DMA_PMON_CNT_1_STS_ACC_OF_M << \
		DMA_PMON_CNT_1_STS_ACC_OF_SHIFT)
#define DMA_PMON_CNT_2_CFG 0x148
#define DMA_PMON_CNT_2_CFG_DEF 0x0
#define DMA_PMON_CNT_2_CFG_DEC_SEL_M 0x3fULL
#define DMA_PMON_CNT_2_CFG_DEC_SEL_SHIFT 48
#define DMA_PMON_CNT_2_CFG_DEC_SEL_MASK (DMA_PMON_CNT_2_CFG_DEC_SEL_M << \
		DMA_PMON_CNT_2_CFG_DEC_SEL_SHIFT)
#define DMA_PMON_CNT_2_CFG_INC_INV_M 0x1ULL
#define DMA_PMON_CNT_2_CFG_INC_INV_SHIFT 47
#define DMA_PMON_CNT_2_CFG_INC_INV_MASK (DMA_PMON_CNT_2_CFG_INC_INV_M << \
		DMA_PMON_CNT_2_CFG_INC_INV_SHIFT)
#define DMA_PMON_CNT_2_CFG_INC_MASK_M 0xfULL
#define DMA_PMON_CNT_2_CFG_INC_MASK_SHIFT 39
#define DMA_PMON_CNT_2_CFG_INC_MASK_MASK (DMA_PMON_CNT_2_CFG_INC_MASK_M << \
		DMA_PMON_CNT_2_CFG_INC_MASK_SHIFT)
#define DMA_PMON_CNT_2_CFG_MODE_M 0x7ULL
#define DMA_PMON_CNT_2_CFG_MODE_SHIFT 0
#define DMA_PMON_CNT_2_CFG_MODE_MASK (DMA_PMON_CNT_2_CFG_MODE_M << \
		DMA_PMON_CNT_2_CFG_MODE_SHIFT)
#define DMA_PMON_CNT_2_CFG_DEC_MASK_M 0xfULL
#define DMA_PMON_CNT_2_CFG_DEC_MASK_SHIFT 55
#define DMA_PMON_CNT_2_CFG_DEC_MASK_MASK (DMA_PMON_CNT_2_CFG_DEC_MASK_M << \
		DMA_PMON_CNT_2_CFG_DEC_MASK_SHIFT)
#define DMA_PMON_CNT_2_CFG_DEC_MATCH_M 0xfULL
#define DMA_PMON_CNT_2_CFG_DEC_MATCH_SHIFT 59
#define DMA_PMON_CNT_2_CFG_DEC_MATCH_MASK (DMA_PMON_CNT_2_CFG_DEC_MATCH_M << \
		DMA_PMON_CNT_2_CFG_DEC_MATCH_SHIFT)
#define DMA_PMON_CNT_2_CFG_THRESHOLD_M 0xffULL
#define DMA_PMON_CNT_2_CFG_THRESHOLD_SHIFT 3
#define DMA_PMON_CNT_2_CFG_THRESHOLD_MASK (DMA_PMON_CNT_2_CFG_THRESHOLD_M << \
		MA_PMON_CNT_2_CFG_THRESHOLD_SHIFT)
#define DMA_PMON_CNT_2_CFG_DEC_INV_M 0x1ULL
#define DMA_PMON_CNT_2_CFG_DEC_INV_SHIFT 63
#define DMA_PMON_CNT_2_CFG_DEC_INV_MASK (DMA_PMON_CNT_2_CFG_DEC_INV_M << \
		DMA_PMON_CNT_2_CFG_DEC_INV_SHIFT)
#define DMA_PMON_CNT_2_CFG_INC_SEL_M 0x3fULL
#define DMA_PMON_CNT_2_CFG_INC_SEL_SHIFT 32
#define DMA_PMON_CNT_2_CFG_INC_SEL_MASK (DMA_PMON_CNT_2_CFG_INC_SEL_M << \
		DMA_PMON_CNT_2_CFG_INC_SEL_SHIFT)
#define DMA_PMON_CNT_2_CFG_INC_MATCH_M 0xfULL
#define DMA_PMON_CNT_2_CFG_INC_MATCH_SHIFT 43
#define DMA_PMON_CNT_2_CFG_INC_MATCH_MASK (DMA_PMON_CNT_2_CFG_INC_MATCH_M << \
		DMA_PMON_CNT_2_CFG_INC_MATCH_SHIFT)
#define DMA_PMON_CNT_2 0x150
#define DMA_PMON_CNT_2_DEF 0x0
#define DMA_PMON_CNT_2_CNT_M 0xffffffffffULL
#define DMA_PMON_CNT_2_CNT_SHIFT 0
#define DMA_PMON_CNT_2_CNT_MASK (DMA_PMON_CNT_2_CNT_M << \
		DMA_PMON_CNT_2_CNT_SHIFT)
#define DMA_PMON_CNT_2_STS_ACC 0x158
#define DMA_PMON_CNT_2_STS_ACC_DEF 0x0
#define DMA_PMON_CNT_2_STS_ACC_VAL_M 0xffULL
#define DMA_PMON_CNT_2_STS_ACC_VAL_SHIFT 0
#define DMA_PMON_CNT_2_STS_ACC_VAL_MASK (DMA_PMON_CNT_2_STS_ACC_VAL_M << \
		DMA_PMON_CNT_2_STS_ACC_VAL_SHIFT)
#define DMA_PMON_CNT_2_STS 0x160
#define DMA_PMON_CNT_2_STS_DEF 0x0
#define DMA_PMON_CNT_2_STS_CNT_OF_M 0x1ULL
#define DMA_PMON_CNT_2_STS_CNT_OF_SHIFT 2
#define DMA_PMON_CNT_2_STS_CNT_OF_MASK (DMA_PMON_CNT_2_STS_CNT_OF_M << \
		DMA_PMON_CNT_2_STS_CNT_OF_SHIFT)
#define DMA_PMON_CNT_2_STS_ACC_OF_M 0x1ULL
#define DMA_PMON_CNT_2_STS_ACC_OF_SHIFT 0
#define DMA_PMON_CNT_2_STS_ACC_OF_MASK (DMA_PMON_CNT_2_STS_ACC_OF_M << \
		DMA_PMON_CNT_2_STS_ACC_OF_SHIFT)
#define DMA_PMON_CNT_2_STS_ACC_UF_M 0x1ULL
#define DMA_PMON_CNT_2_STS_ACC_UF_SHIFT 1
#define DMA_PMON_CNT_2_STS_ACC_UF_MASK (DMA_PMON_CNT_2_STS_ACC_UF_M << \
		DMA_PMON_CNT_2_STS_ACC_UF_SHIFT)
#define DMA_PMON_CNT_3_CFG 0x168
#define DMA_PMON_CNT_3_CFG_DEF 0x0
#define DMA_PMON_CNT_3_CFG_INC_MATCH_M 0xfULL
#define DMA_PMON_CNT_3_CFG_INC_MATCH_SHIFT 43
#define DMA_PMON_CNT_3_CFG_INC_MATCH_MASK (DMA_PMON_CNT_3_CFG_INC_MATCH_M << \
		DMA_PMON_CNT_3_CFG_INC_MATCH_SHIFT)
#define DMA_PMON_CNT_3_CFG_DEC_MASK_M 0xfULL
#define DMA_PMON_CNT_3_CFG_DEC_MASK_SHIFT 55
#define DMA_PMON_CNT_3_CFG_DEC_MASK_MASK (DMA_PMON_CNT_3_CFG_DEC_MASK_M << \
		DMA_PMON_CNT_3_CFG_DEC_MASK_SHIFT)
#define DMA_PMON_CNT_3_CFG_DEC_MATCH_M 0xfULL
#define DMA_PMON_CNT_3_CFG_DEC_MATCH_SHIFT 59
#define DMA_PMON_CNT_3_CFG_DEC_MATCH_MASK (DMA_PMON_CNT_3_CFG_DEC_MATCH_M << \
		DMA_PMON_CNT_3_CFG_DEC_MATCH_SHIFT)
#define DMA_PMON_CNT_3_CFG_MODE_M 0x7ULL
#define DMA_PMON_CNT_3_CFG_MODE_SHIFT 0
#define DMA_PMON_CNT_3_CFG_MODE_MASK (DMA_PMON_CNT_3_CFG_MODE_M << \
		DMA_PMON_CNT_3_CFG_MODE_SHIFT)
#define DMA_PMON_CNT_3_CFG_THRESHOLD_M 0xffULL
#define DMA_PMON_CNT_3_CFG_THRESHOLD_SHIFT 3
#define DMA_PMON_CNT_3_CFG_THRESHOLD_MASK (DMA_PMON_CNT_3_CFG_THRESHOLD_M << \
		DMA_PMON_CNT_3_CFG_THRESHOLD_SHIFT)
#define DMA_PMON_CNT_3_CFG_DEC_INV_M 0x1ULL
#define DMA_PMON_CNT_3_CFG_DEC_INV_SHIFT 63
#define DMA_PMON_CNT_3_CFG_DEC_INV_MASK (DMA_PMON_CNT_3_CFG_DEC_INV_M << \
		DMA_PMON_CNT_3_CFG_DEC_INV_SHIFT)
#define DMA_PMON_CNT_3_CFG_INC_SEL_M 0x3fULL
#define DMA_PMON_CNT_3_CFG_INC_SEL_SHIFT 32
#define DMA_PMON_CNT_3_CFG_INC_SEL_MASK (DMA_PMON_CNT_3_CFG_INC_SEL_M << \
		DMA_PMON_CNT_3_CFG_INC_SEL_SHIFT)
#define DMA_PMON_CNT_3_CFG_INC_INV_M 0x1ULL
#define DMA_PMON_CNT_3_CFG_INC_INV_SHIFT 47
#define DMA_PMON_CNT_3_CFG_INC_INV_MASK (DMA_PMON_CNT_3_CFG_INC_INV_M << \
		DMA_PMON_CNT_3_CFG_INC_INV_SHIFT)
#define DMA_PMON_CNT_3_CFG_DEC_SEL_M 0x3fULL
#define DMA_PMON_CNT_3_CFG_DEC_SEL_SHIFT 48
#define DMA_PMON_CNT_3_CFG_DEC_SEL_MASK (DMA_PMON_CNT_3_CFG_DEC_SEL_M << \
		DMA_PMON_CNT_3_CFG_DEC_SEL_SHIFT)
#define DMA_PMON_CNT_3_CFG_INC_MASK_M 0xfULL
#define DMA_PMON_CNT_3_CFG_INC_MASK_SHIFT 39
#define DMA_PMON_CNT_3_CFG_INC_MASK_MASK (DMA_PMON_CNT_3_CFG_INC_MASK_M << \
		DMA_PMON_CNT_3_CFG_INC_MASK_SHIFT)
#define DMA_PMON_CNT_3 0x170
#define DMA_PMON_CNT_3_DEF 0x0
#define DMA_PMON_CNT_3_CNT_M 0xffffffffffULL
#define DMA_PMON_CNT_3_CNT_SHIFT 0
#define DMA_PMON_CNT_3_CNT_MASK (DMA_PMON_CNT_3_CNT_M << \
		DMA_PMON_CNT_3_CNT_SHIFT)
#define DMA_PMON_CNT_3_STS_ACC 0x178
#define DMA_PMON_CNT_3_STS_ACC_DEF 0x0
#define DMA_PMON_CNT_3_STS_ACC_VAL_M 0xffULL
#define DMA_PMON_CNT_3_STS_ACC_VAL_SHIFT 0
#define DMA_PMON_CNT_3_STS_ACC_VAL_MASK (DMA_PMON_CNT_3_STS_ACC_VAL_M << \
		DMA_PMON_CNT_3_STS_ACC_VAL_SHIFT)
#define DMA_PMON_CNT_3_STS 0x180
#define DMA_PMON_CNT_3_STS_DEF 0x0
#define DMA_PMON_CNT_3_STS_CNT_OF_M 0x1ULL
#define DMA_PMON_CNT_3_STS_CNT_OF_SHIFT 2
#define DMA_PMON_CNT_3_STS_CNT_OF_MASK (DMA_PMON_CNT_3_STS_CNT_OF_M << \
		DMA_PMON_CNT_3_STS_CNT_OF_SHIFT)
#define DMA_PMON_CNT_3_STS_ACC_OF_M 0x1ULL
#define DMA_PMON_CNT_3_STS_ACC_OF_SHIFT 0
#define DMA_PMON_CNT_3_STS_ACC_OF_MASK (DMA_PMON_CNT_3_STS_ACC_OF_M << \
		DMA_PMON_CNT_3_STS_ACC_OF_SHIFT)
#define DMA_PMON_CNT_3_STS_ACC_UF_M 0x1ULL
#define DMA_PMON_CNT_3_STS_ACC_UF_SHIFT 1
#define DMA_PMON_CNT_3_STS_ACC_UF_MASK (DMA_PMON_CNT_3_STS_ACC_UF_M << \\
		DMA_PMON_CNT_3_STS_ACC_UF_SHIFT)
#define DMA_STAT_CTRL 0x188
#define DMA_STAT_CTRL_DEF 0x0
#define DMA_STAT_CTRL_NOC_MNGR_PORT_M 0x1ULL
#define DMA_STAT_CTRL_NOC_MNGR_PORT_SHIFT 8
#define DMA_STAT_CTRL_NOC_MNGR_PORT_MASK (DMA_STAT_CTRL_NOC_MNGR_PORT_M << \
		DMA_STAT_CTRL_NOC_MNGR_PORT_SHIFT)
#define DMA_STAT_CTRL_ENABLE_M 0x1ULL
#define DMA_STAT_CTRL_ENABLE_SHIFT 0
#define DMA_STAT_CTRL_ENABLE_MASK (DMA_STAT_CTRL_ENABLE_M << \
		DMA_STAT_CTRL_ENABLE_SHIFT)
#define DMA_STAT_CTRL_ADDR_MODE_M 0x1ULL
#define DMA_STAT_CTRL_ADDR_MODE_SHIFT 7
#define DMA_STAT_CTRL_ADDR_MODE_MASK (DMA_STAT_CTRL_ADDR_MODE_M << \
		DMA_STAT_CTRL_ADDR_MODE_SHIFT)
#define DMA_STAT_CTRL_DST_BIF_SEL_SSP_M 0x1ULL
#define DMA_STAT_CTRL_DST_BIF_SEL_SSP_SHIFT 6
#define DMA_STAT_CTRL_DST_BIF_SEL_SSP_MASK (DMA_STAT_CTRL_DST_BIF_SEL_SSP_M << \
		DMA_STAT_CTRL_DST_BIF_SEL_SSP_SHIFT)
#define DMA_STAT_STATE 0x190
#define DMA_STAT_STATE_DEF 0x0
#define DMA_STAT_STATE_WR_MNGR_STATE_M 0x3ULL
#define DMA_STAT_STATE_WR_MNGR_STATE_SHIFT 28
#define DMA_STAT_STATE_WR_MNGR_STATE_MASK (DMA_STAT_STATE_WR_MNGR_STATE_M << \
		DMA_STAT_STATE_WR_MNGR_STATE_SHIFT)
#define DMA_STAT_STATE_RD_MNGR_CHAN_MODE_M 0x1ULL
#define DMA_STAT_STATE_RD_MNGR_CHAN_MODE_SHIFT 26
#define DMA_STAT_STATE_RD_MNGR_CHAN_MODE_MASK \
		(DMA_STAT_STATE_RD_MNGR_CHAN_MODE_M << \
		DMA_STAT_STATE_RD_MNGR_CHAN_MODE_SHIFT)
#define DMA_STAT_STATE_DST_MODE_M 0x1ULL
#define DMA_STAT_STATE_DST_MODE_SHIFT 25
#define DMA_STAT_STATE_DST_MODE_MASK (DMA_STAT_STATE_DST_MODE_M << \
		DMA_STAT_STATE_DST_MODE_SHIFT)
#define DMA_STAT_STATE_SRC_MODE_M 0x1ULL
#define DMA_STAT_STATE_SRC_MODE_SHIFT 24
#define DMA_STAT_STATE_SRC_MODE_MASK (DMA_STAT_STATE_SRC_MODE_M << \
		DMA_STAT_STATE_SRC_MODE_SHIFT)
#define DMA_STAT_STATE_RD_MNGR_CHAN_M 0x1fULL
#define DMA_STAT_STATE_RD_MNGR_CHAN_SHIFT 8
#define DMA_STAT_STATE_RD_MNGR_CHAN_MASK (DMA_STAT_STATE_RD_MNGR_CHAN_M << \
		DMA_STAT_STATE_RD_MNGR_CHAN_SHIFT)
#define DMA_STAT_STATE_WR_MNGR_CHAN_MODE_M 0x1ULL
#define DMA_STAT_STATE_WR_MNGR_CHAN_MODE_SHIFT 27
#define DMA_STAT_STATE_WR_MNGR_CHAN_MODE_MASK \
		(DMA_STAT_STATE_WR_MNGR_CHAN_MODE_M << \
		DMA_STAT_STATE_WR_MNGR_CHAN_MODE_SHIFT)
#define DMA_STAT_STATE_WR_MNGR_CHAN_M 0x1fULL
#define DMA_STAT_STATE_WR_MNGR_CHAN_SHIFT 13
#define DMA_STAT_STATE_WR_MNGR_CHAN_MASK (DMA_STAT_STATE_WR_MNGR_CHAN_M << \
		DMA_STAT_STATE_WR_MNGR_CHAN_SHIFT)
#define DMA_STAT_STATE_DST_M 0xfULL
#define DMA_STAT_STATE_DST_SHIFT 4
#define DMA_STAT_STATE_DST_MASK (DMA_STAT_STATE_DST_M << \
		DMA_STAT_STATE_DST_SHIFT)
#define DMA_STAT_STATE_SRC_M 0xfULL
#define DMA_STAT_STATE_SRC_SHIFT 0
#define DMA_STAT_STATE_SRC_MASK (DMA_STAT_STATE_SRC_M << \
		DMA_STAT_STATE_SRC_SHIFT)
#define DMA_STAT_STATE_WR_MNGR_STATE_MODE_M 0x1ULL
#define DMA_STAT_STATE_WR_MNGR_STATE_MODE_SHIFT 30
#define DMA_STAT_STATE_WR_MNGR_STATE_MODE_MASK \
		(DMA_STAT_STATE_WR_MNGR_STATE_MODE_M << \
		DMA_STAT_STATE_WR_MNGR_STATE_MODE_SHIFT)
#define DMA_STAT_PTR 0x198
#define DMA_STAT_PTR_DEF 0x0
#define DMA_STAT_PTR_MODE_M 0x1ULL
#define DMA_STAT_PTR_MODE_SHIFT 63
#define DMA_STAT_PTR_MODE_MASK (DMA_STAT_PTR_MODE_M << DMA_STAT_PTR_MODE_SHIFT)
#define DMA_STAT_PTR_Y_M 0xffffULL
#define DMA_STAT_PTR_Y_SHIFT 16
#define DMA_STAT_PTR_Y_MASK (DMA_STAT_PTR_Y_M << DMA_STAT_PTR_Y_SHIFT)
#define DMA_STAT_PTR_X_M 0xffffULL
#define DMA_STAT_PTR_X_SHIFT 0
#define DMA_STAT_PTR_X_MASK (DMA_STAT_PTR_X_M << DMA_STAT_PTR_X_SHIFT)
#define DMA_STAT_PTR_SHEET_HEIGHT_M 0x1fULL
#define DMA_STAT_PTR_SHEET_HEIGHT_SHIFT 44
#define DMA_STAT_PTR_SHEET_HEIGHT_MASK (DMA_STAT_PTR_SHEET_HEIGHT_M << \
		DMA_STAT_PTR_SHEET_HEIGHT_SHIFT)
#define DMA_STAT_PTR_SHEET_WIDTH_M 0x1ffULL
#define DMA_STAT_PTR_SHEET_WIDTH_SHIFT 32
#define DMA_STAT_PTR_SHEET_WIDTH_MASK (DMA_STAT_PTR_SHEET_WIDTH_M << \
		DMA_STAT_PTR_SHEET_WIDTH_SHIFT)
#define DMA_STAT_ADDR 0x1a0
#define DMA_STAT_ADDR_DEF 0x0
#define DMA_STAT_ADDR_ADDR_M 0x7ffffffffffULL
#define DMA_STAT_ADDR_ADDR_SHIFT 0
#define DMA_STAT_ADDR_ADDR_MASK (DMA_STAT_ADDR_ADDR_M << \
		DMA_STAT_ADDR_ADDR_SHIFT)
#define SSP_STATUS 0x1a8
#define SSP_STATUS_DEF 0x100
#define SSP_STATUS_SEG_AVAIL_M 0x1ffULL
#define SSP_STATUS_SEG_AVAIL_SHIFT 0
#define SSP_STATUS_SEG_AVAIL_MASK (SSP_STATUS_SEG_AVAIL_M << \
		SSP_STATUS_SEG_AVAIL_SHIFT)
#define DMA_SPARE 0x1b0
#define DMA_SPARE_DEF 0x0
#define DMA_SPARE_SPARE0_M 0x1ULL
#define DMA_SPARE_SPARE0_SHIFT 0
#define DMA_SPARE_SPARE0_MASK (DMA_SPARE_SPARE0_M << DMA_SPARE_SPARE0_SHIFT)
#define DMA_SPARE_SPARE1_M 0x1ULL
#define DMA_SPARE_SPARE1_SHIFT 1
#define DMA_SPARE_SPARE1_MASK (DMA_SPARE_SPARE1_M << DMA_SPARE_SPARE1_SHIFT)
#define DMA_SPARE_SPARE2_M 0x1ULL
#define DMA_SPARE_SPARE2_SHIFT 2
#define DMA_SPARE_SPARE2_MASK (DMA_SPARE_SPARE2_M << DMA_SPARE_SPARE2_SHIFT)
#define DMA_SPARE_SPARE3_M 0x1ULL
#define DMA_SPARE_SPARE3_SHIFT 3
#define DMA_SPARE_SPARE3_MASK (DMA_SPARE_SPARE3_M << DMA_SPARE_SPARE3_SHIFT)
#define DMA_SPARE_SPARE4_M 0x1ULL
#define DMA_SPARE_SPARE4_SHIFT 4
#define DMA_SPARE_SPARE4_MASK (DMA_SPARE_SPARE4_M << DMA_SPARE_SPARE4_SHIFT)
#define DMA_SPARE_SPARE5_M 0x1ULL
#define DMA_SPARE_SPARE5_SHIFT 5
#define DMA_SPARE_SPARE5_MASK (DMA_SPARE_SPARE5_M << DMA_SPARE_SPARE5_SHIFT)
#define DMA_SPARE_SPARE6_M 0x1ULL
#define DMA_SPARE_SPARE6_SHIFT 6
#define DMA_SPARE_SPARE6_MASK (DMA_SPARE_SPARE6_M << DMA_SPARE_SPARE6_SHIFT)
#define DMA_SPARE_SPARE7_M 0x1ULL
#define DMA_SPARE_SPARE7_SHIFT 7
#define DMA_SPARE_SPARE7_MASK (DMA_SPARE_SPARE7_M << DMA_SPARE_SPARE7_SHIFT)

/* Module : IPU_LIB_DREGFILE_HP_JQS*/
#define SYS_JQS_DBL 0x0
#define SYS_JQS_DBL_DEF 0x0
#define SYS_JQS_DBL_DBL_IRQ_M 0xffffffffULL
#define SYS_JQS_DBL_DBL_IRQ_SHIFT 0
#define SYS_JQS_DBL_DBL_IRQ_MASK (SYS_JQS_DBL_DBL_IRQ_M << \
		SYS_JQS_DBL_DBL_IRQ_SHIFT)
#define JQS_SYS_DBL 0x8
#define JQS_SYS_DBL_DEF 0x0
#define JQS_SYS_DBL_DBL_IRQ_M 0xffffffffULL
#define JQS_SYS_DBL_DBL_IRQ_SHIFT 0
#define JQS_SYS_DBL_DBL_IRQ_MASK (JQS_SYS_DBL_DBL_IRQ_M << \
		JQS_SYS_DBL_DBL_IRQ_SHIFT)
#define SYS_JQS_GPR_0 0x10
#define SYS_JQS_GPR_0_DEF 0x0
#define SYS_JQS_GPR_0_GPR_M 0xffffffffULL
#define SYS_JQS_GPR_0_GPR_SHIFT 0
#define SYS_JQS_GPR_0_GPR_MASK (SYS_JQS_GPR_0_GPR_M << SYS_JQS_GPR_0_GPR_SHIFT)
#define SYS_JQS_GPR_1 0x18
#define SYS_JQS_GPR_1_DEF 0x0
#define SYS_JQS_GPR_1_GPR_M 0xffffffffULL
#define SYS_JQS_GPR_1_GPR_SHIFT 0
#define SYS_JQS_GPR_1_GPR_MASK (SYS_JQS_GPR_1_GPR_M << SYS_JQS_GPR_1_GPR_SHIFT)
#define SYS_JQS_GPR_2 0x20
#define SYS_JQS_GPR_2_DEF 0x0
#define SYS_JQS_GPR_2_GPR_M 0xffffffffULL
#define SYS_JQS_GPR_2_GPR_SHIFT 0
#define SYS_JQS_GPR_2_GPR_MASK (SYS_JQS_GPR_2_GPR_M << SYS_JQS_GPR_2_GPR_SHIFT)
#define SYS_JQS_GPR_3 0x28
#define SYS_JQS_GPR_3_DEF 0x0
#define SYS_JQS_GPR_3_GPR_M 0xffffffffULL
#define SYS_JQS_GPR_3_GPR_SHIFT 0
#define SYS_JQS_GPR_3_GPR_MASK (SYS_JQS_GPR_3_GPR_M << SYS_JQS_GPR_3_GPR_SHIFT)
#define SYS_JQS_GPR_4 0x30
#define SYS_JQS_GPR_4_DEF 0x0
#define SYS_JQS_GPR_4_GPR_M 0xffffffffULL
#define SYS_JQS_GPR_4_GPR_SHIFT 0
#define SYS_JQS_GPR_4_GPR_MASK (SYS_JQS_GPR_4_GPR_M << SYS_JQS_GPR_4_GPR_SHIFT)
#define SYS_JQS_GPR_5 0x38
#define SYS_JQS_GPR_5_DEF 0x0
#define SYS_JQS_GPR_5_GPR_M 0xffffffffULL
#define SYS_JQS_GPR_5_GPR_SHIFT 0
#define SYS_JQS_GPR_5_GPR_MASK (SYS_JQS_GPR_5_GPR_M << SYS_JQS_GPR_5_GPR_SHIFT)
#define SYS_JQS_GPR_6 0x40
#define SYS_JQS_GPR_6_DEF 0x0
#define SYS_JQS_GPR_6_GPR_M 0xffffffffULL
#define SYS_JQS_GPR_6_GPR_SHIFT 0
#define SYS_JQS_GPR_6_GPR_MASK (SYS_JQS_GPR_6_GPR_M << SYS_JQS_GPR_6_GPR_SHIFT)
#define SYS_JQS_GPR_7 0x48
#define SYS_JQS_GPR_7_DEF 0x0
#define SYS_JQS_GPR_7_GPR_M 0xffffffffULL
#define SYS_JQS_GPR_7_GPR_SHIFT 0
#define SYS_JQS_GPR_7_GPR_MASK (SYS_JQS_GPR_7_GPR_M << SYS_JQS_GPR_7_GPR_SHIFT)
#define JQS_SYS_GPR_0 0x50
#define JQS_SYS_GPR_0_DEF 0x0
#define JQS_SYS_GPR_0_GPR_M 0xffffffffULL
#define JQS_SYS_GPR_0_GPR_SHIFT 0
#define JQS_SYS_GPR_0_GPR_MASK (JQS_SYS_GPR_0_GPR_M << JQS_SYS_GPR_0_GPR_SHIFT)
#define JQS_SYS_GPR_1 0x58
#define JQS_SYS_GPR_1_DEF 0x0
#define JQS_SYS_GPR_1_GPR_M 0xffffffffULL
#define JQS_SYS_GPR_1_GPR_SHIFT 0
#define JQS_SYS_GPR_1_GPR_MASK (JQS_SYS_GPR_1_GPR_M << JQS_SYS_GPR_1_GPR_SHIFT)
#define JQS_SYS_GPR_2 0x60
#define JQS_SYS_GPR_2_DEF 0x0
#define JQS_SYS_GPR_2_GPR_M 0xffffffffULL
#define JQS_SYS_GPR_2_GPR_SHIFT 0
#define JQS_SYS_GPR_2_GPR_MASK (JQS_SYS_GPR_2_GPR_M << JQS_SYS_GPR_2_GPR_SHIFT)
#define JQS_SYS_GPR_3 0x68
#define JQS_SYS_GPR_3_DEF 0x0
#define JQS_SYS_GPR_3_GPR_M 0xffffffffULL
#define JQS_SYS_GPR_3_GPR_SHIFT 0
#define JQS_SYS_GPR_3_GPR_MASK (JQS_SYS_GPR_3_GPR_M << JQS_SYS_GPR_3_GPR_SHIFT)
#define JQS_SYS_GPR_4 0x70
#define JQS_SYS_GPR_4_DEF 0x0
#define JQS_SYS_GPR_4_GPR_M 0xffffffffULL
#define JQS_SYS_GPR_4_GPR_SHIFT 0
#define JQS_SYS_GPR_4_GPR_MASK (JQS_SYS_GPR_4_GPR_M << JQS_SYS_GPR_4_GPR_SHIFT)
#define JQS_SYS_GPR_5 0x78
#define JQS_SYS_GPR_5_DEF 0x0
#define JQS_SYS_GPR_5_GPR_M 0xffffffffULL
#define JQS_SYS_GPR_5_GPR_SHIFT 0
#define JQS_SYS_GPR_5_GPR_MASK (JQS_SYS_GPR_5_GPR_M << JQS_SYS_GPR_5_GPR_SHIFT)
#define JQS_SYS_GPR_6 0x80
#define JQS_SYS_GPR_6_DEF 0x0
#define JQS_SYS_GPR_6_GPR_M 0xffffffffULL
#define JQS_SYS_GPR_6_GPR_SHIFT 0
#define JQS_SYS_GPR_6_GPR_MASK (JQS_SYS_GPR_6_GPR_M << JQS_SYS_GPR_6_GPR_SHIFT)
#define JQS_SYS_GPR_7 0x88
#define JQS_SYS_GPR_7_DEF 0x0
#define JQS_SYS_GPR_7_GPR_M 0xffffffffULL
#define JQS_SYS_GPR_7_GPR_SHIFT 0
#define JQS_SYS_GPR_7_GPR_MASK (JQS_SYS_GPR_7_GPR_M << JQS_SYS_GPR_7_GPR_SHIFT)
#define SYS_JQS_IRQ_INTENT 0x90
#define SYS_JQS_IRQ_INTENT_DEF 0x0
#define SYS_JQS_IRQ_INTENT_IRQ_EN_M 0xffffffffULL
#define SYS_JQS_IRQ_INTENT_IRQ_EN_SHIFT 0
#define SYS_JQS_IRQ_INTENT_IRQ_EN_MASK (SYS_JQS_IRQ_INTENT_IRQ_EN_M << \
		SYS_JQS_IRQ_INTENT_IRQ_EN_SHIFT)
#define JQS_SYS_STAT 0x98
#define JQS_SYS_STAT_DEF 0x0
#define JQS_SYS_STAT_CORE_CLK_GATE_M 0x1ULL
#define JQS_SYS_STAT_CORE_CLK_GATE_SHIFT 2
#define JQS_SYS_STAT_CORE_CLK_GATE_MASK (JQS_SYS_STAT_CORE_CLK_GATE_M << \
		JQS_SYS_STAT_CORE_CLK_GATE_SHIFT)
#define JQS_SYS_STAT_CORE_BUSY_M 0x1ULL
#define JQS_SYS_STAT_CORE_BUSY_SHIFT 1
#define JQS_SYS_STAT_CORE_BUSY_MASK (JQS_SYS_STAT_CORE_BUSY_M << \
		JQS_SYS_STAT_CORE_BUSY_SHIFT)
#define JQS_SYS_STAT_WATCHDOG_TIMER_OVFLW_M 0x1ULL
#define JQS_SYS_STAT_WATCHDOG_TIMER_OVFLW_SHIFT 3
#define JQS_SYS_STAT_WATCHDOG_TIMER_OVFLW_MASK \
		(JQS_SYS_STAT_WATCHDOG_TIMER_OVFLW_M << \
		JQS_SYS_STAT_WATCHDOG_TIMER_OVFLW_SHIFT)
#define JQS_SYS_STAT_USER_TIMER_CMP_M 0x1ULL
#define JQS_SYS_STAT_USER_TIMER_CMP_SHIFT 6
#define JQS_SYS_STAT_USER_TIMER_CMP_MASK (JQS_SYS_STAT_USER_TIMER_CMP_M << \
		JQS_SYS_STAT_USER_TIMER_CMP_SHIFT)
#define JQS_SYS_STAT_WATCHDOG_TIMER_CMP_M 0x1ULL
#define JQS_SYS_STAT_WATCHDOG_TIMER_CMP_SHIFT 4
#define JQS_SYS_STAT_WATCHDOG_TIMER_CMP_MASK \
		(JQS_SYS_STAT_WATCHDOG_TIMER_CMP_M << \
		JQS_SYS_STAT_WATCHDOG_TIMER_CMP_SHIFT)
#define JQS_SYS_STAT_USER_TIMER_OVFLW_M 0x1ULL
#define JQS_SYS_STAT_USER_TIMER_OVFLW_SHIFT 5
#define JQS_SYS_STAT_USER_TIMER_OVFLW_MASK (JQS_SYS_STAT_USER_TIMER_OVFLW_M << \
		JQS_SYS_STAT_USER_TIMER_OVFLW_SHIFT)
#define JQS_SYS_STAT_AXI_ERR_M 0x1ULL
#define JQS_SYS_STAT_AXI_ERR_SHIFT 7
#define JQS_SYS_STAT_AXI_ERR_MASK (JQS_SYS_STAT_AXI_ERR_M << \
		JQS_SYS_STAT_AXI_ERR_SHIFT)
#define JQS_SYS_STAT_FETCH_ENABLE_M 0x1ULL
#define JQS_SYS_STAT_FETCH_ENABLE_SHIFT 0
#define JQS_SYS_STAT_FETCH_ENABLE_MASK (JQS_SYS_STAT_FETCH_ENABLE_M << \
		JQS_SYS_STAT_FETCH_ENABLE_SHIFT)

/* Module : IPU_LIB_DREGFILE_IRQ*/
#define IPU_ISR 0x0
#define IPU_ISR_DEF 0x0
#define IPU_ISR_SSP_ERR_INTR_M 0x1ULL
#define IPU_ISR_SSP_ERR_INTR_SHIFT 5
#define IPU_ISR_SSP_ERR_INTR_MASK (IPU_ISR_SSP_ERR_INTR_M << \
		IPU_ISR_SSP_ERR_INTR_SHIFT)
#define IPU_ISR_STP_INTR_M 0x1ULL
#define IPU_ISR_STP_INTR_SHIFT 2
#define IPU_ISR_STP_INTR_MASK (IPU_ISR_STP_INTR_M << IPU_ISR_STP_INTR_SHIFT)
#define IPU_ISR_DMA_CHAN_INTR_M 0x1ULL
#define IPU_ISR_DMA_CHAN_INTR_SHIFT 0
#define IPU_ISR_DMA_CHAN_INTR_MASK (IPU_ISR_DMA_CHAN_INTR_M << \
		IPU_ISR_DMA_CHAN_INTR_SHIFT)
#define IPU_ISR_STP_ERR_INTR_M 0x1ULL
#define IPU_ISR_STP_ERR_INTR_SHIFT 4
#define IPU_ISR_STP_ERR_INTR_MASK (IPU_ISR_STP_ERR_INTR_M << \
		IPU_ISR_STP_ERR_INTR_SHIFT)
#define IPU_ISR_DMA_ERR_INTR_M 0x1ULL
#define IPU_ISR_DMA_ERR_INTR_SHIFT 1
#define IPU_ISR_DMA_ERR_INTR_MASK (IPU_ISR_DMA_ERR_INTR_M << \
		IPU_ISR_DMA_ERR_INTR_SHIFT)
#define IPU_ISR_MMU_INTR_M 0x1ULL
#define IPU_ISR_MMU_INTR_SHIFT 7
#define IPU_ISR_MMU_INTR_MASK (IPU_ISR_MMU_INTR_M << IPU_ISR_MMU_INTR_SHIFT)
#define IPU_ISR_STP_GRP_INTR_M 0x1ULL
#define IPU_ISR_STP_GRP_INTR_SHIFT 3
#define IPU_ISR_STP_GRP_INTR_MASK (IPU_ISR_STP_GRP_INTR_M << \
		IPU_ISR_STP_GRP_INTR_SHIFT)
#define IPU_ISR_BIF_INTR_M 0x1ULL
#define IPU_ISR_BIF_INTR_SHIFT 6
#define IPU_ISR_BIF_INTR_MASK (IPU_ISR_BIF_INTR_M << IPU_ISR_BIF_INTR_SHIFT)
#define IPU_ITR 0x8
#define IPU_ITR_DEF 0x0
#define IPU_ITR_DMA_ERR_INTR_M 0x1ULL
#define IPU_ITR_DMA_ERR_INTR_SHIFT 1
#define IPU_ITR_DMA_ERR_INTR_MASK (IPU_ITR_DMA_ERR_INTR_M << \
		IPU_ITR_DMA_ERR_INTR_SHIFT)
#define IPU_ITR_MMU_INTR_M 0x1ULL
#define IPU_ITR_MMU_INTR_SHIFT 7
#define IPU_ITR_MMU_INTR_MASK (IPU_ITR_MMU_INTR_M << IPU_ITR_MMU_INTR_SHIFT)
#define IPU_ITR_STP_GRP_INTR_M 0x1ULL
#define IPU_ITR_STP_GRP_INTR_SHIFT 3
#define IPU_ITR_STP_GRP_INTR_MASK (IPU_ITR_STP_GRP_INTR_M << \
		IPU_ITR_STP_GRP_INTR_SHIFT)
#define IPU_ITR_BIF_INTR_M 0x1ULL
#define IPU_ITR_BIF_INTR_SHIFT 6
#define IPU_ITR_BIF_INTR_MASK (IPU_ITR_BIF_INTR_M << IPU_ITR_BIF_INTR_SHIFT)
#define IPU_ITR_DMA_CHAN_INTR_M 0x1ULL
#define IPU_ITR_DMA_CHAN_INTR_SHIFT 0
#define IPU_ITR_DMA_CHAN_INTR_MASK (IPU_ITR_DMA_CHAN_INTR_M << \
		IPU_ITR_DMA_CHAN_INTR_SHIFT)
#define IPU_ITR_STP_INTR_M 0x1ULL
#define IPU_ITR_STP_INTR_SHIFT 2
#define IPU_ITR_STP_INTR_MASK (IPU_ITR_STP_INTR_M << IPU_ITR_STP_INTR_SHIFT)
#define IPU_ITR_SSP_ERR_INTR_M 0x1ULL
#define IPU_ITR_SSP_ERR_INTR_SHIFT 5
#define IPU_ITR_SSP_ERR_INTR_MASK (IPU_ITR_SSP_ERR_INTR_M << \
		IPU_ITR_SSP_ERR_INTR_SHIFT)
#define IPU_ITR_STP_ERR_INTR_M 0x1ULL
#define IPU_ITR_STP_ERR_INTR_SHIFT 4
#define IPU_ITR_STP_ERR_INTR_MASK (IPU_ITR_STP_ERR_INTR_M << \
		IPU_ITR_STP_ERR_INTR_SHIFT)
#define IPU_IER 0x10
#define IPU_IER_DEF 0xff
#define IPU_IER_STP_GRP_INTR_M 0x1ULL
#define IPU_IER_STP_GRP_INTR_SHIFT 3
#define IPU_IER_STP_GRP_INTR_MASK (IPU_IER_STP_GRP_INTR_M << \
		IPU_IER_STP_GRP_INTR_SHIFT)
#define IPU_IER_DMA_CHAN_INTR_M 0x1ULL
#define IPU_IER_DMA_CHAN_INTR_SHIFT 0
#define IPU_IER_DMA_CHAN_INTR_MASK (IPU_IER_DMA_CHAN_INTR_M << \
		IPU_IER_DMA_CHAN_INTR_SHIFT)
#define IPU_IER_MMU_INTR_M 0x1ULL
#define IPU_IER_MMU_INTR_SHIFT 7
#define IPU_IER_MMU_INTR_MASK (IPU_IER_MMU_INTR_M << IPU_IER_MMU_INTR_SHIFT)
#define IPU_IER_STP_INTR_M 0x1ULL
#define IPU_IER_STP_INTR_SHIFT 2
#define IPU_IER_STP_INTR_MASK (IPU_IER_STP_INTR_M << IPU_IER_STP_INTR_SHIFT)
#define IPU_IER_SSP_ERR_INTR_M 0x1ULL
#define IPU_IER_SSP_ERR_INTR_SHIFT 5
#define IPU_IER_SSP_ERR_INTR_MASK (IPU_IER_SSP_ERR_INTR_M << \
		IPU_IER_SSP_ERR_INTR_SHIFT)
#define IPU_IER_DMA_ERR_INTR_M 0x1ULL
#define IPU_IER_DMA_ERR_INTR_SHIFT 1
#define IPU_IER_DMA_ERR_INTR_MASK (IPU_IER_DMA_ERR_INTR_M << \
		IPU_IER_DMA_ERR_INTR_SHIFT)
#define IPU_IER_STP_ERR_INTR_M 0x1ULL
#define IPU_IER_STP_ERR_INTR_SHIFT 4
#define IPU_IER_STP_ERR_INTR_MASK (IPU_IER_STP_ERR_INTR_M << \
		IPU_IER_STP_ERR_INTR_SHIFT)
#define IPU_IER_BIF_INTR_M 0x1ULL
#define IPU_IER_BIF_INTR_SHIFT 6
#define IPU_IER_BIF_INTR_MASK (IPU_IER_BIF_INTR_M << IPU_IER_BIF_INTR_SHIFT)
#define DMA_CHAN_ISR 0x18
#define DMA_CHAN_ISR_DEF 0x0
#define DMA_CHAN_ISR_DMA_CHAN_M 0xffffffffULL
#define DMA_CHAN_ISR_DMA_CHAN_SHIFT 0
#define DMA_CHAN_ISR_DMA_CHAN_MASK (DMA_CHAN_ISR_DMA_CHAN_M << \
		DMA_CHAN_ISR_DMA_CHAN_SHIFT)
#define DMA_CHAN_ITR 0x20
#define DMA_CHAN_ITR_DEF 0x0
#define DMA_CHAN_ITR_DMA_CHAN_M 0xffffffffULL
#define DMA_CHAN_ITR_DMA_CHAN_SHIFT 0
#define DMA_CHAN_ITR_DMA_CHAN_MASK (DMA_CHAN_ITR_DMA_CHAN_M << \
		DMA_CHAN_ITR_DMA_CHAN_SHIFT)
#define DMA_CHAN_IER 0x28
#define DMA_CHAN_IER_DEF 0xffffffff
#define DMA_CHAN_IER_DMA_CHAN_M 0xffffffffULL
#define DMA_CHAN_IER_DMA_CHAN_SHIFT 0
#define DMA_CHAN_IER_DMA_CHAN_MASK (DMA_CHAN_IER_DMA_CHAN_M << \
		DMA_CHAN_IER_DMA_CHAN_SHIFT)
#define DMA_CHAN_IMR 0x30
#define DMA_CHAN_IMR_DEF 0x0
#define DMA_CHAN_IMR_DMA_CHAN_M 0xffffffffULL
#define DMA_CHAN_IMR_DMA_CHAN_SHIFT 0
#define DMA_CHAN_IMR_DMA_CHAN_MASK (DMA_CHAN_IMR_DMA_CHAN_M << \
		DMA_CHAN_IMR_DMA_CHAN_SHIFT)
#define DMA_ERR_ISR 0x38
#define DMA_ERR_ISR_DEF 0x0
#define DMA_ERR_ISR_DMA_CHAN_ERR_M 0xffffffffULL
#define DMA_ERR_ISR_DMA_CHAN_ERR_SHIFT 0
#define DMA_ERR_ISR_DMA_CHAN_ERR_MASK (DMA_ERR_ISR_DMA_CHAN_ERR_M << \
		DMA_ERR_ISR_DMA_CHAN_ERR_SHIFT)
#define DMA_ERR_ITR 0x40
#define DMA_ERR_ITR_DEF 0x0
#define DMA_ERR_ITR_DMA_CHAN_ERR_M 0xffffffffULL
#define DMA_ERR_ITR_DMA_CHAN_ERR_SHIFT 0
#define DMA_ERR_ITR_DMA_CHAN_ERR_MASK (DMA_ERR_ITR_DMA_CHAN_ERR_M << \
		DMA_ERR_ITR_DMA_CHAN_ERR_SHIFT)
#define DMA_ERR_IER 0x48
#define DMA_ERR_IER_DEF 0xffffffff
#define DMA_ERR_IER_DMA_CHAN_ERR_M 0xffffffffULL
#define DMA_ERR_IER_DMA_CHAN_ERR_SHIFT 0
#define DMA_ERR_IER_DMA_CHAN_ERR_MASK (DMA_ERR_IER_DMA_CHAN_ERR_M << \
		DMA_ERR_IER_DMA_CHAN_ERR_SHIFT)
#define DMA_ERR_IMR 0x50
#define DMA_ERR_IMR_DEF 0x0
#define DMA_ERR_IMR_DMA_CHAN_ERR_M 0xffffffffULL
#define DMA_ERR_IMR_DMA_CHAN_ERR_SHIFT 0
#define DMA_ERR_IMR_DMA_CHAN_ERR_MASK (DMA_ERR_IMR_DMA_CHAN_ERR_M << \
		DMA_ERR_IMR_DMA_CHAN_ERR_SHIFT)
#define IPU_STP_ISR 0x58
#define IPU_STP_ISR_DEF 0x0
#define IPU_STP_ISR_STP_M 0x3fffULL
#define IPU_STP_ISR_STP_SHIFT 0
#define IPU_STP_ISR_STP_MASK (IPU_STP_ISR_STP_M << IPU_STP_ISR_STP_SHIFT)
#define IPU_STP_ITR 0x60
#define IPU_STP_ITR_DEF 0x0
#define IPU_STP_ITR_STP_M 0x3fffULL
#define IPU_STP_ITR_STP_SHIFT 0
#define IPU_STP_ITR_STP_MASK (IPU_STP_ITR_STP_M << IPU_STP_ITR_STP_SHIFT)
#define IPU_STP_IER 0x68
#define IPU_STP_IER_DEF 0x3fff
#define IPU_STP_IER_STP_M 0x3fffULL
#define IPU_STP_IER_STP_SHIFT 0
#define IPU_STP_IER_STP_MASK (IPU_STP_IER_STP_M << IPU_STP_IER_STP_SHIFT)
#define IPU_STP_IMR 0x70
#define IPU_STP_IMR_DEF 0x0
#define IPU_STP_IMR_STP_M 0x3fffULL
#define IPU_STP_IMR_STP_SHIFT 0
#define IPU_STP_IMR_STP_MASK (IPU_STP_IMR_STP_M << IPU_STP_IMR_STP_SHIFT)
#define STP_ERR_ISR 0x78
#define STP_ERR_ISR_DEF 0x0
#define STP_ERR_ISR_STP_ERR_M 0x3fffULL
#define STP_ERR_ISR_STP_ERR_SHIFT 0
#define STP_ERR_ISR_STP_ERR_MASK (STP_ERR_ISR_STP_ERR_M << \
		STP_ERR_ISR_STP_ERR_SHIFT)
#define STP_ERR_ITR 0x80
#define STP_ERR_ITR_DEF 0x0
#define STP_ERR_ITR_STP_ERR_M 0x3fffULL
#define STP_ERR_ITR_STP_ERR_SHIFT 0
#define STP_ERR_ITR_STP_ERR_MASK (STP_ERR_ITR_STP_ERR_M << \
		STP_ERR_ITR_STP_ERR_SHIFT)
#define STP_ERR_IER 0x88
#define STP_ERR_IER_DEF 0x3fff
#define STP_ERR_IER_STP_ERR_M 0x3fffULL
#define STP_ERR_IER_STP_ERR_SHIFT 0
#define STP_ERR_IER_STP_ERR_MASK (STP_ERR_IER_STP_ERR_M << \
		STP_ERR_IER_STP_ERR_SHIFT)
#define STP_ERR_IMR 0x90
#define STP_ERR_IMR_DEF 0x0
#define STP_ERR_IMR_STP_ERR_M 0x3fffULL
#define STP_ERR_IMR_STP_ERR_SHIFT 0
#define STP_ERR_IMR_STP_ERR_MASK (STP_ERR_IMR_STP_ERR_M << \
		STP_ERR_IMR_STP_ERR_SHIFT)
#define IPU_STP_GRP_SEL 0x98
#define IPU_STP_GRP_SEL_DEF 0x0
#define IPU_STP_GRP_SEL_MASK_M 0x3fffULL
#define IPU_STP_GRP_SEL_MASK_SHIFT 0
#define IPU_STP_GRP_SEL_MASK_MASK (IPU_STP_GRP_SEL_MASK_M << \
		IPU_STP_GRP_SEL_MASK_SHIFT)
#define IRQ_SPARE 0xa0
#define IRQ_SPARE_DEF 0x0
#define IRQ_SPARE_SPARE15_M 0x1ULL
#define IRQ_SPARE_SPARE15_SHIFT 15
#define IRQ_SPARE_SPARE15_MASK (IRQ_SPARE_SPARE15_M << IRQ_SPARE_SPARE15_SHIFT)
#define IRQ_SPARE_SPARE14_M 0x1ULL
#define IRQ_SPARE_SPARE14_SHIFT 14
#define IRQ_SPARE_SPARE14_MASK (IRQ_SPARE_SPARE14_M << IRQ_SPARE_SPARE14_SHIFT)
#define IRQ_SPARE_SPARE12_M 0x1ULL
#define IRQ_SPARE_SPARE12_SHIFT 12
#define IRQ_SPARE_SPARE12_MASK (IRQ_SPARE_SPARE12_M << IRQ_SPARE_SPARE12_SHIFT)
#define IRQ_SPARE_SPARE13_M 0x1ULL
#define IRQ_SPARE_SPARE13_SHIFT 13
#define IRQ_SPARE_SPARE13_MASK (IRQ_SPARE_SPARE13_M << IRQ_SPARE_SPARE13_SHIFT)
#define IRQ_SPARE_SPARE11_M 0x1ULL
#define IRQ_SPARE_SPARE11_SHIFT 11
#define IRQ_SPARE_SPARE11_MASK (IRQ_SPARE_SPARE11_M << IRQ_SPARE_SPARE11_SHIFT)
#define IRQ_SPARE_SPARE8_M 0x1ULL
#define IRQ_SPARE_SPARE8_SHIFT 8
#define IRQ_SPARE_SPARE8_MASK (IRQ_SPARE_SPARE8_M << IRQ_SPARE_SPARE8_SHIFT)
#define IRQ_SPARE_SPARE9_M 0x1ULL
#define IRQ_SPARE_SPARE9_SHIFT 9
#define IRQ_SPARE_SPARE9_MASK (IRQ_SPARE_SPARE9_M << IRQ_SPARE_SPARE9_SHIFT)
#define IRQ_SPARE_SPARE10_M 0x1ULL
#define IRQ_SPARE_SPARE10_SHIFT 10
#define IRQ_SPARE_SPARE10_MASK (IRQ_SPARE_SPARE10_M << IRQ_SPARE_SPARE10_SHIFT)
#define IRQ_SPARE_SPARE4_M 0x1ULL
#define IRQ_SPARE_SPARE4_SHIFT 4
#define IRQ_SPARE_SPARE4_MASK (IRQ_SPARE_SPARE4_M << IRQ_SPARE_SPARE4_SHIFT)
#define IRQ_SPARE_SPARE5_M 0x1ULL
#define IRQ_SPARE_SPARE5_SHIFT 5
#define IRQ_SPARE_SPARE5_MASK (IRQ_SPARE_SPARE5_M << IRQ_SPARE_SPARE5_SHIFT)
#define IRQ_SPARE_SPARE6_M 0x1ULL
#define IRQ_SPARE_SPARE6_SHIFT 6
#define IRQ_SPARE_SPARE6_MASK (IRQ_SPARE_SPARE6_M << IRQ_SPARE_SPARE6_SHIFT)
#define IRQ_SPARE_SPARE7_M 0x1ULL
#define IRQ_SPARE_SPARE7_SHIFT 7
#define IRQ_SPARE_SPARE7_MASK (IRQ_SPARE_SPARE7_M << IRQ_SPARE_SPARE7_SHIFT)
#define IRQ_SPARE_SPARE0_M 0x1ULL
#define IRQ_SPARE_SPARE0_SHIFT 0
#define IRQ_SPARE_SPARE0_MASK (IRQ_SPARE_SPARE0_M << IRQ_SPARE_SPARE0_SHIFT)
#define IRQ_SPARE_SPARE1_M 0x1ULL
#define IRQ_SPARE_SPARE1_SHIFT 1
#define IRQ_SPARE_SPARE1_MASK (IRQ_SPARE_SPARE1_M << IRQ_SPARE_SPARE1_SHIFT)
#define IRQ_SPARE_SPARE2_M 0x1ULL
#define IRQ_SPARE_SPARE2_SHIFT 2
#define IRQ_SPARE_SPARE2_MASK (IRQ_SPARE_SPARE2_M << IRQ_SPARE_SPARE2_SHIFT)
#define IRQ_SPARE_SPARE3_M 0x1ULL
#define IRQ_SPARE_SPARE3_SHIFT 3
#define IRQ_SPARE_SPARE3_MASK (IRQ_SPARE_SPARE3_M << IRQ_SPARE_SPARE3_SHIFT)

/* Module : IPU_LIB_DREGFILE_LBP*/
#define LBP_SEL 0x0
#define LBP_SEL_DEF 0xf1f
#define LBP_SEL_LBP_SEL_M 0x1fULL
#define LBP_SEL_LBP_SEL_SHIFT 0
#define LBP_SEL_LBP_SEL_MASK (LBP_SEL_LBP_SEL_M << LBP_SEL_LBP_SEL_SHIFT)
#define LBP_SEL_LB_SEL_M 0xfULL
#define LBP_SEL_LB_SEL_SHIFT 8
#define LBP_SEL_LB_SEL_MASK (LBP_SEL_LB_SEL_M << LBP_SEL_LB_SEL_SHIFT)
#define LBP_CTRL 0x8
#define LBP_CTRL_DEF 0x1
#define LBP_CTRL_LB_RESET_M 0xffULL
#define LBP_CTRL_LB_RESET_SHIFT 16
#define LBP_CTRL_LB_RESET_MASK (LBP_CTRL_LB_RESET_M << LBP_CTRL_LB_RESET_SHIFT)
#define LBP_CTRL_LB_ENA_M 0xffULL
#define LBP_CTRL_LB_ENA_SHIFT 0
#define LBP_CTRL_LB_ENA_MASK (LBP_CTRL_LB_ENA_M << LBP_CTRL_LB_ENA_SHIFT)
#define LBP_CTRL_LB_INIT_M 0xffULL
#define LBP_CTRL_LB_INIT_SHIFT 32
#define LBP_CTRL_LB_INIT_MASK (LBP_CTRL_LB_INIT_M << LBP_CTRL_LB_INIT_SHIFT)
#define LBP_CTRL_PMON_RD_SEL_M 0xffULL
#define LBP_CTRL_PMON_RD_SEL_SHIFT 48
#define LBP_CTRL_PMON_RD_SEL_MASK (LBP_CTRL_PMON_RD_SEL_M << \
		LBP_CTRL_PMON_RD_SEL_SHIFT)
#define LBP_CTRL_LBP_RESET_M 0x1ULL
#define LBP_CTRL_LBP_RESET_SHIFT 8
#define LBP_CTRL_LBP_RESET_MASK (LBP_CTRL_LBP_RESET_M << \
		LBP_CTRL_LBP_RESET_SHIFT)
#define LBP_STAT 0x10
#define LBP_STAT_DEF 0x0
#define LBP_STAT_CRB_READY_M 0x1ULL
#define LBP_STAT_CRB_READY_SHIFT 0
#define LBP_STAT_CRB_READY_MASK (LBP_STAT_CRB_READY_M << \
		LBP_STAT_CRB_READY_SHIFT)
#define LBP_STAT_WDC_READY_M 0x1ULL
#define LBP_STAT_WDC_READY_SHIFT 1
#define LBP_STAT_WDC_READY_MASK (LBP_STAT_WDC_READY_M << \
		LBP_STAT_WDC_READY_SHIFT)
#define LBP_STAT_RD_READY_M 0x1ULL
#define LBP_STAT_RD_READY_SHIFT 2
#define LBP_STAT_RD_READY_MASK (LBP_STAT_RD_READY_M << LBP_STAT_RD_READY_SHIFT)
#define LBP_CAP0 0x18
#define LBP_CAP0_DEF 0x8fff1008
#define LBP_CAP0_MAX_CHAN_M 0x1ffULL
#define LBP_CAP0_MAX_CHAN_SHIFT 4
#define LBP_CAP0_MAX_CHAN_MASK (LBP_CAP0_MAX_CHAN_M << LBP_CAP0_MAX_CHAN_SHIFT)
#define LBP_CAP0_MAX_RPTR_M 0xfULL
#define LBP_CAP0_MAX_RPTR_SHIFT 28
#define LBP_CAP0_MAX_RPTR_MASK (LBP_CAP0_MAX_RPTR_M << LBP_CAP0_MAX_RPTR_SHIFT)
#define LBP_CAP0_MAX_FB_ROWS_M 0xfffULL
#define LBP_CAP0_MAX_FB_ROWS_SHIFT 16
#define LBP_CAP0_MAX_FB_ROWS_MASK (LBP_CAP0_MAX_FB_ROWS_M << \
		LBP_CAP0_MAX_FB_ROWS_SHIFT)
#define LBP_CAP0_MAX_LB_M 0xfULL
#define LBP_CAP0_MAX_LB_SHIFT 0
#define LBP_CAP0_MAX_LB_MASK (LBP_CAP0_MAX_LB_M << LBP_CAP0_MAX_LB_SHIFT)
#define LBP_CAP1 0x20
#define LBP_CAP1_DEF 0x40000
#define LBP_CAP1_MEM_SIZE_M 0xffffffffULL
#define LBP_CAP1_MEM_SIZE_SHIFT 0
#define LBP_CAP1_MEM_SIZE_MASK (LBP_CAP1_MEM_SIZE_M << LBP_CAP1_MEM_SIZE_SHIFT)
#define LBP_RAM_CTRL 0x28
#define LBP_RAM_CTRL_DEF 0x0
#define LBP_RAM_CTRL_RUN_M 0x1ULL
#define LBP_RAM_CTRL_RUN_SHIFT 0
#define LBP_RAM_CTRL_RUN_MASK (LBP_RAM_CTRL_RUN_M << LBP_RAM_CTRL_RUN_SHIFT)
#define LBP_RAM_CTRL_WRITE_M 0x1ULL
#define LBP_RAM_CTRL_WRITE_SHIFT 1
#define LBP_RAM_CTRL_WRITE_MASK (LBP_RAM_CTRL_WRITE_M << \
		LBP_RAM_CTRL_WRITE_SHIFT)
#define LBP_RAM_CTRL_RAM_ADDR_M 0x1fffULL
#define LBP_RAM_CTRL_RAM_ADDR_SHIFT 16
#define LBP_RAM_CTRL_RAM_ADDR_MASK (LBP_RAM_CTRL_RAM_ADDR_M << \
		LBP_RAM_CTRL_RAM_ADDR_SHIFT)
#define LBP_RAM_DATA0 0x30
#define LBP_RAM_DATA0_DEF 0x0
#define LBP_RAM_DATA0_VAL_M 0xffffffffffffffffULL
#define LBP_RAM_DATA0_VAL_SHIFT 0
#define LBP_RAM_DATA0_VAL_MASK (LBP_RAM_DATA0_VAL_M << LBP_RAM_DATA0_VAL_SHIFT)
#define LBP_RAM_DATA1 0x38
#define LBP_RAM_DATA1_DEF 0x0
#define LBP_RAM_DATA1_VAL_M 0xffffffffffffffffULL
#define LBP_RAM_DATA1_VAL_SHIFT 0
#define LBP_RAM_DATA1_VAL_MASK (LBP_RAM_DATA1_VAL_M << LBP_RAM_DATA1_VAL_SHIFT)
#define LBP_RAM_DATA2 0x40
#define LBP_RAM_DATA2_DEF 0x0
#define LBP_RAM_DATA2_VAL_M 0xffffffffffffffffULL
#define LBP_RAM_DATA2_VAL_SHIFT 0
#define LBP_RAM_DATA2_VAL_MASK (LBP_RAM_DATA2_VAL_M << LBP_RAM_DATA2_VAL_SHIFT)
#define LBP_RAM_DATA3 0x48
#define LBP_RAM_DATA3_DEF 0x0
#define LBP_RAM_DATA3_VAL_M 0xffffffffffffffffULL
#define LBP_RAM_DATA3_VAL_SHIFT 0
#define LBP_RAM_DATA3_VAL_MASK (LBP_RAM_DATA3_VAL_M << LBP_RAM_DATA3_VAL_SHIFT)
#define LBP_PMON_CFG 0x50
#define LBP_PMON_CFG_DEF 0x0
#define LBP_PMON_CFG_ENABLE_M 0x1ULL
#define LBP_PMON_CFG_ENABLE_SHIFT 0
#define LBP_PMON_CFG_ENABLE_MASK (LBP_PMON_CFG_ENABLE_M << \
		LBP_PMON_CFG_ENABLE_SHIFT)
#define LBP_PMON_CNT_0_CFG 0x58
#define LBP_PMON_CNT_0_CFG_DEF 0x0
#define LBP_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
#define LBP_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
#define LBP_PMON_CNT_0_CFG_DEC_INV_MASK (LBP_PMON_CNT_0_CFG_DEC_INV_M << \
		LBP_PMON_CNT_0_CFG_DEC_INV_SHIFT)
#define LBP_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
#define LBP_PMON_CNT_0_CFG_INC_INV_SHIFT 47
#define LBP_PMON_CNT_0_CFG_INC_INV_MASK (LBP_PMON_CNT_0_CFG_INC_INV_M << \
		LBP_PMON_CNT_0_CFG_INC_INV_SHIFT)
#define LBP_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
#define LBP_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
#define LBP_PMON_CNT_0_CFG_INC_MATCH_MASK (LBP_PMON_CNT_0_CFG_INC_MATCH_M << \
		LBP_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
#define LBP_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
#define LBP_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
#define LBP_PMON_CNT_0_CFG_THRESHOLD_MASK (LBP_PMON_CNT_0_CFG_THRESHOLD_M << \
		LBP_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
#define LBP_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
#define LBP_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
#define LBP_PMON_CNT_0_CFG_DEC_MASK_MASK (LBP_PMON_CNT_0_CFG_DEC_MASK_M << \
		LBP_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
#define LBP_PMON_CNT_0_CFG_MODE_M 0x7ULL
#define LBP_PMON_CNT_0_CFG_MODE_SHIFT 0
#define LBP_PMON_CNT_0_CFG_MODE_MASK (LBP_PMON_CNT_0_CFG_MODE_M << \
		LBP_PMON_CNT_0_CFG_MODE_SHIFT)
#define LBP_PMON_CNT_0_CFG_INC_SEL_M 0x3fULL
#define LBP_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
#define LBP_PMON_CNT_0_CFG_INC_SEL_MASK (LBP_PMON_CNT_0_CFG_INC_SEL_M << \
		LBP_PMON_CNT_0_CFG_INC_SEL_SHIFT)
#define LBP_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
#define LBP_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
#define LBP_PMON_CNT_0_CFG_DEC_MATCH_MASK (LBP_PMON_CNT_0_CFG_DEC_MATCH_M << \
		LBP_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
#define LBP_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
#define LBP_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
#define LBP_PMON_CNT_0_CFG_INC_MASK_MASK (LBP_PMON_CNT_0_CFG_INC_MASK_M << \
		LBP_PMON_CNT_0_CFG_INC_MASK_SHIFT)
#define LBP_PMON_CNT_0_CFG_DEC_SEL_M 0x3fULL
#define LBP_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
#define LBP_PMON_CNT_0_CFG_DEC_SEL_MASK (LBP_PMON_CNT_0_CFG_DEC_SEL_M << \
		LBP_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
#define LBP_PMON_CNT_0 0x60
#define LBP_PMON_CNT_0_DEF 0x0
#define LBP_PMON_CNT_0_CNT_M 0xffffffffffULL
#define LBP_PMON_CNT_0_CNT_SHIFT 0
#define LBP_PMON_CNT_0_CNT_MASK (LBP_PMON_CNT_0_CNT_M << \
		LBP_PMON_CNT_0_CNT_SHIFT)
#define LBP_PMON_CNT_0_STS_ACC 0x68
#define LBP_PMON_CNT_0_STS_ACC_DEF 0x0
#define LBP_PMON_CNT_0_STS_ACC_VAL_M 0xffULL
#define LBP_PMON_CNT_0_STS_ACC_VAL_SHIFT 0
#define LBP_PMON_CNT_0_STS_ACC_VAL_MASK (LBP_PMON_CNT_0_STS_ACC_VAL_M << \
		LBP_PMON_CNT_0_STS_ACC_VAL_SHIFT)
#define LBP_PMON_CNT_0_STS 0x70
#define LBP_PMON_CNT_0_STS_DEF 0x0
#define LBP_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
#define LBP_PMON_CNT_0_STS_ACC_OF_SHIFT 0
#define LBP_PMON_CNT_0_STS_ACC_OF_MASK (LBP_PMON_CNT_0_STS_ACC_OF_M << \
		LBP_PMON_CNT_0_STS_ACC_OF_SHIFT)
#define LBP_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
#define LBP_PMON_CNT_0_STS_CNT_OF_SHIFT 2
#define LBP_PMON_CNT_0_STS_CNT_OF_MASK (LBP_PMON_CNT_0_STS_CNT_OF_M << \
		LBP_PMON_CNT_0_STS_CNT_OF_SHIFT)
#define LBP_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
#define LBP_PMON_CNT_0_STS_ACC_UF_SHIFT 1
#define LBP_PMON_CNT_0_STS_ACC_UF_MASK (LBP_PMON_CNT_0_STS_ACC_UF_M << \
		LBP_PMON_CNT_0_STS_ACC_UF_SHIFT)
#define LBP_PMON_CNT_1_CFG 0x78
#define LBP_PMON_CNT_1_CFG_DEF 0x0
#define LBP_PMON_CNT_1_CFG_INC_SEL_M 0x3fULL
#define LBP_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
#define LBP_PMON_CNT_1_CFG_INC_SEL_MASK (LBP_PMON_CNT_1_CFG_INC_SEL_M << \
		LBP_PMON_CNT_1_CFG_INC_SEL_SHIFT)
#define LBP_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
#define LBP_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
#define LBP_PMON_CNT_1_CFG_DEC_MATCH_MASK (LBP_PMON_CNT_1_CFG_DEC_MATCH_M << \
		LBP_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
#define LBP_PMON_CNT_1_CFG_DEC_SEL_M 0x3fULL
#define LBP_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
#define LBP_PMON_CNT_1_CFG_DEC_SEL_MASK (LBP_PMON_CNT_1_CFG_DEC_SEL_M << \
		LBP_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
#define LBP_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
#define LBP_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
#define LBP_PMON_CNT_1_CFG_INC_MATCH_MASK (LBP_PMON_CNT_1_CFG_INC_MATCH_M << \
		LBP_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
#define LBP_PMON_CNT_1_CFG_MODE_M 0x7ULL
#define LBP_PMON_CNT_1_CFG_MODE_SHIFT 0
#define LBP_PMON_CNT_1_CFG_MODE_MASK (LBP_PMON_CNT_1_CFG_MODE_M << \
		LBP_PMON_CNT_1_CFG_MODE_SHIFT)
#define LBP_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
#define LBP_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
#define LBP_PMON_CNT_1_CFG_DEC_MASK_MASK (LBP_PMON_CNT_1_CFG_DEC_MASK_M << \
		LBP_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
#define LBP_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
#define LBP_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
#define LBP_PMON_CNT_1_CFG_DEC_INV_MASK (LBP_PMON_CNT_1_CFG_DEC_INV_M << \
		LBP_PMON_CNT_1_CFG_DEC_INV_SHIFT)
#define LBP_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
#define LBP_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
#define LBP_PMON_CNT_1_CFG_INC_MASK_MASK (LBP_PMON_CNT_1_CFG_INC_MASK_M << \
		LBP_PMON_CNT_1_CFG_INC_MASK_SHIFT)
#define LBP_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
#define LBP_PMON_CNT_1_CFG_INC_INV_SHIFT 47
#define LBP_PMON_CNT_1_CFG_INC_INV_MASK (LBP_PMON_CNT_1_CFG_INC_INV_M << \
		LBP_PMON_CNT_1_CFG_INC_INV_SHIFT)
#define LBP_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
#define LBP_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
#define LBP_PMON_CNT_1_CFG_THRESHOLD_MASK (LBP_PMON_CNT_1_CFG_THRESHOLD_M << \
		LBP_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
#define LBP_PMON_CNT_1 0x80
#define LBP_PMON_CNT_1_DEF 0x0
#define LBP_PMON_CNT_1_CNT_M 0xffffffffffULL
#define LBP_PMON_CNT_1_CNT_SHIFT 0
#define LBP_PMON_CNT_1_CNT_MASK (LBP_PMON_CNT_1_CNT_M << \
		LBP_PMON_CNT_1_CNT_SHIFT)
#define LBP_PMON_CNT_1_STS_ACC 0x88
#define LBP_PMON_CNT_1_STS_ACC_DEF 0x0
#define LBP_PMON_CNT_1_STS_ACC_VAL_M 0xffULL
#define LBP_PMON_CNT_1_STS_ACC_VAL_SHIFT 0
#define LBP_PMON_CNT_1_STS_ACC_VAL_MASK (LBP_PMON_CNT_1_STS_ACC_VAL_M << \
		LBP_PMON_CNT_1_STS_ACC_VAL_SHIFT)
#define LBP_PMON_CNT_1_STS 0x90
#define LBP_PMON_CNT_1_STS_DEF 0x0
#define LBP_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
#define LBP_PMON_CNT_1_STS_ACC_UF_SHIFT 1
#define LBP_PMON_CNT_1_STS_ACC_UF_MASK (LBP_PMON_CNT_1_STS_ACC_UF_M << \
		LBP_PMON_CNT_1_STS_ACC_UF_SHIFT)
#define LBP_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
#define LBP_PMON_CNT_1_STS_ACC_OF_SHIFT 0
#define LBP_PMON_CNT_1_STS_ACC_OF_MASK (LBP_PMON_CNT_1_STS_ACC_OF_M << \
		LBP_PMON_CNT_1_STS_ACC_OF_SHIFT)
#define LBP_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
#define LBP_PMON_CNT_1_STS_CNT_OF_SHIFT 2
#define LBP_PMON_CNT_1_STS_CNT_OF_MASK (LBP_PMON_CNT_1_STS_CNT_OF_M << \
		LBP_PMON_CNT_1_STS_CNT_OF_SHIFT)
#define LB_CTRL0 0xc0
#define LB_CTRL0_DEF 0x280021
#define LB_CTRL0_FB_ROWS_M 0xfffULL
#define LB_CTRL0_FB_ROWS_SHIFT 16
#define LB_CTRL0_FB_ROWS_MASK (LB_CTRL0_FB_ROWS_M << LB_CTRL0_FB_ROWS_SHIFT)
#define LB_CTRL0_EN_CHAIN_M 0x1ULL
#define LB_CTRL0_EN_CHAIN_SHIFT 15
#define LB_CTRL0_EN_CHAIN_MASK (LB_CTRL0_EN_CHAIN_M << LB_CTRL0_EN_CHAIN_SHIFT)
#define LB_CTRL0_ADDR_MODE_M 0x1ULL
#define LB_CTRL0_ADDR_MODE_SHIFT 14
#define LB_CTRL0_ADDR_MODE_MASK (LB_CTRL0_ADDR_MODE_M << \
		LB_CTRL0_ADDR_MODE_SHIFT)
#define LB_CTRL0_NUM_CHAN_M 0x1ffULL
#define LB_CTRL0_NUM_CHAN_SHIFT 4
#define LB_CTRL0_NUM_CHAN_MASK (LB_CTRL0_NUM_CHAN_M << LB_CTRL0_NUM_CHAN_SHIFT)
#define LB_CTRL0_REUSE_ROWS_M 0x1fULL
#define LB_CTRL0_REUSE_ROWS_SHIFT 32
#define LB_CTRL0_REUSE_ROWS_MASK (LB_CTRL0_REUSE_ROWS_M << \
		LB_CTRL0_REUSE_ROWS_SHIFT)
#define LB_CTRL0_NUM_RPTR_M 0xfULL
#define LB_CTRL0_NUM_RPTR_SHIFT 0
#define LB_CTRL0_NUM_RPTR_MASK (LB_CTRL0_NUM_RPTR_M << LB_CTRL0_NUM_RPTR_SHIFT)
#define LB_OFFSET 0xc8
#define LB_OFFSET_DEF 0x0
#define LB_OFFSET_OFFSET_Y_M 0xffffULL
#define LB_OFFSET_OFFSET_Y_SHIFT 16
#define LB_OFFSET_OFFSET_Y_MASK (LB_OFFSET_OFFSET_Y_M << \
		LB_OFFSET_OFFSET_Y_SHIFT)
#define LB_OFFSET_OFFSET_X_M 0xffffULL
#define LB_OFFSET_OFFSET_X_SHIFT 0
#define LB_OFFSET_OFFSET_X_MASK (LB_OFFSET_OFFSET_X_M << \
		LB_OFFSET_OFFSET_X_SHIFT)
#define LB_OFFSET_FB_OFFSET_M 0xffULL
#define LB_OFFSET_FB_OFFSET_SHIFT 48
#define LB_OFFSET_FB_OFFSET_MASK (LB_OFFSET_FB_OFFSET_M << \
		LB_OFFSET_FB_OFFSET_SHIFT)
#define LB_OFFSET_OFFSET_CHAN_M 0x1ffULL
#define LB_OFFSET_OFFSET_CHAN_SHIFT 32
#define LB_OFFSET_OFFSET_CHAN_MASK (LB_OFFSET_OFFSET_CHAN_M << \
		LB_OFFSET_OFFSET_CHAN_SHIFT)
#define LB_BDRY 0xd0
#define LB_BDRY_DEF 0x0
#define LB_BDRY_BDRY_M 0x3ULL
#define LB_BDRY_BDRY_SHIFT 0
#define LB_BDRY_BDRY_MASK (LB_BDRY_BDRY_M << LB_BDRY_BDRY_SHIFT)
#define LB_BDRY_BDRY_VAL_M 0xffffULL
#define LB_BDRY_BDRY_VAL_SHIFT 16
#define LB_BDRY_BDRY_VAL_MASK (LB_BDRY_BDRY_VAL_M << LB_BDRY_BDRY_VAL_SHIFT)
#define LB_IMG_SIZE 0xd8
#define LB_IMG_SIZE_DEF 0x1e00280
#define LB_IMG_SIZE_IMG_HEIGHT_M 0xffffULL
#define LB_IMG_SIZE_IMG_HEIGHT_SHIFT 16
#define LB_IMG_SIZE_IMG_HEIGHT_MASK (LB_IMG_SIZE_IMG_HEIGHT_M << \
		LB_IMG_SIZE_IMG_HEIGHT_SHIFT)
#define LB_IMG_SIZE_IMG_WIDTH_M 0xffffULL
#define LB_IMG_SIZE_IMG_WIDTH_SHIFT 0
#define LB_IMG_SIZE_IMG_WIDTH_MASK (LB_IMG_SIZE_IMG_WIDTH_M << \
		LB_IMG_SIZE_IMG_WIDTH_SHIFT)
#define LB_SB_SIZE 0xe0
#define LB_SB_SIZE_DEF 0x0
#define LB_SB_SIZE_SB_ROWS_M 0xfffULL
#define LB_SB_SIZE_SB_ROWS_SHIFT 16
#define LB_SB_SIZE_SB_ROWS_MASK (LB_SB_SIZE_SB_ROWS_M << \
		LB_SB_SIZE_SB_ROWS_SHIFT)
#define LB_SB_SIZE_SB_COLS_M 0xffffULL
#define LB_SB_SIZE_SB_COLS_SHIFT 0
#define LB_SB_SIZE_SB_COLS_MASK (LB_SB_SIZE_SB_COLS_M << \
		LB_SB_SIZE_SB_COLS_SHIFT)
#define LB_BASE 0xe8
#define LB_BASE_DEF 0x0
#define LB_BASE_FB_BASE_ADDR_M 0x1fffULL
#define LB_BASE_FB_BASE_ADDR_SHIFT 0
#define LB_BASE_FB_BASE_ADDR_MASK (LB_BASE_FB_BASE_ADDR_M << \
		LB_BASE_FB_BASE_ADDR_SHIFT)
#define LB_BASE_SB_BASE_ADDR_M 0x1fffULL
#define LB_BASE_SB_BASE_ADDR_SHIFT 16
#define LB_BASE_SB_BASE_ADDR_MASK (LB_BASE_SB_BASE_ADDR_M << \
		LB_BASE_SB_BASE_ADDR_SHIFT)
#define LB_STAT 0xf0
#define LB_STAT_DEF 0x0
#define LB_STAT_EMPTY_M 0xffULL
#define LB_STAT_EMPTY_SHIFT 1
#define LB_STAT_EMPTY_MASK (LB_STAT_EMPTY_M << LB_STAT_EMPTY_SHIFT)
#define LB_STAT_FULL_M 0x1ULL
#define LB_STAT_FULL_SHIFT 0
#define LB_STAT_FULL_MASK (LB_STAT_FULL_M << LB_STAT_FULL_SHIFT)
#define LB_L_PARAM 0xf8
#define LB_L_PARAM_DEF 0x0
#define LB_L_PARAM_L_INC_M 0x3fffULL
#define LB_L_PARAM_L_INC_SHIFT 0
#define LB_L_PARAM_L_INC_MASK (LB_L_PARAM_L_INC_M << LB_L_PARAM_L_INC_SHIFT)
#define LB_L_PARAM_L_WIDTH_M 0x3fffULL
#define LB_L_PARAM_L_WIDTH_SHIFT 16
#define LB_L_PARAM_L_WIDTH_MASK (LB_L_PARAM_L_WIDTH_M << \
		LB_L_PARAM_L_WIDTH_SHIFT)
#define LB_SB_DELTA 0x100
#define LB_SB_DELTA_DEF 0x0
#define LB_SB_DELTA_SB_DELTA_M 0x3fffULL
#define LB_SB_DELTA_SB_DELTA_SHIFT 0
#define LB_SB_DELTA_SB_DELTA_MASK (LB_SB_DELTA_SB_DELTA_M << \
		LB_SB_DELTA_SB_DELTA_SHIFT)
#define LBP_SPARE 0x108
#define LBP_SPARE_DEF 0x0
#define LBP_SPARE_SPARE16_M 0x1ULL
#define LBP_SPARE_SPARE16_SHIFT 16
#define LBP_SPARE_SPARE16_MASK (LBP_SPARE_SPARE16_M << LBP_SPARE_SPARE16_SHIFT)
#define LBP_SPARE_SPARE17_M 0x1ULL
#define LBP_SPARE_SPARE17_SHIFT 17
#define LBP_SPARE_SPARE17_MASK (LBP_SPARE_SPARE17_M << LBP_SPARE_SPARE17_SHIFT)
#define LBP_SPARE_SPARE14_M 0x1ULL
#define LBP_SPARE_SPARE14_SHIFT 14
#define LBP_SPARE_SPARE14_MASK (LBP_SPARE_SPARE14_M << LBP_SPARE_SPARE14_SHIFT)
#define LBP_SPARE_SPARE15_M 0x1ULL
#define LBP_SPARE_SPARE15_SHIFT 15
#define LBP_SPARE_SPARE15_MASK (LBP_SPARE_SPARE15_M << LBP_SPARE_SPARE15_SHIFT)
#define LBP_SPARE_SPARE12_M 0x1ULL
#define LBP_SPARE_SPARE12_SHIFT 12
#define LBP_SPARE_SPARE12_MASK (LBP_SPARE_SPARE12_M << LBP_SPARE_SPARE12_SHIFT)
#define LBP_SPARE_SPARE13_M 0x1ULL
#define LBP_SPARE_SPARE13_SHIFT 13
#define LBP_SPARE_SPARE13_MASK (LBP_SPARE_SPARE13_M << LBP_SPARE_SPARE13_SHIFT)
#define LBP_SPARE_SPARE10_M 0x1ULL
#define LBP_SPARE_SPARE10_SHIFT 10
#define LBP_SPARE_SPARE10_MASK (LBP_SPARE_SPARE10_M << LBP_SPARE_SPARE10_SHIFT)
#define LBP_SPARE_SPARE11_M 0x1ULL
#define LBP_SPARE_SPARE11_SHIFT 11
#define LBP_SPARE_SPARE11_MASK (LBP_SPARE_SPARE11_M << LBP_SPARE_SPARE11_SHIFT)
#define LBP_SPARE_SPARE18_M 0x1ULL
#define LBP_SPARE_SPARE18_SHIFT 18
#define LBP_SPARE_SPARE18_MASK (LBP_SPARE_SPARE18_M << LBP_SPARE_SPARE18_SHIFT)
#define LBP_SPARE_SPARE19_M 0x1ULL
#define LBP_SPARE_SPARE19_SHIFT 19
#define LBP_SPARE_SPARE19_MASK (LBP_SPARE_SPARE19_M << LBP_SPARE_SPARE19_SHIFT)
#define LBP_SPARE_SPARE4_M 0x1ULL
#define LBP_SPARE_SPARE4_SHIFT 4
#define LBP_SPARE_SPARE4_MASK (LBP_SPARE_SPARE4_M << LBP_SPARE_SPARE4_SHIFT)
#define LBP_SPARE_SPARE5_M 0x1ULL
#define LBP_SPARE_SPARE5_SHIFT 5
#define LBP_SPARE_SPARE5_MASK (LBP_SPARE_SPARE5_M << LBP_SPARE_SPARE5_SHIFT)
#define LBP_SPARE_SPARE6_M 0x1ULL
#define LBP_SPARE_SPARE6_SHIFT 6
#define LBP_SPARE_SPARE6_MASK (LBP_SPARE_SPARE6_M << LBP_SPARE_SPARE6_SHIFT)
#define LBP_SPARE_SPARE7_M 0x1ULL
#define LBP_SPARE_SPARE7_SHIFT 7
#define LBP_SPARE_SPARE7_MASK (LBP_SPARE_SPARE7_M << LBP_SPARE_SPARE7_SHIFT)
#define LBP_SPARE_SPARE0_M 0x1ULL
#define LBP_SPARE_SPARE0_SHIFT 0
#define LBP_SPARE_SPARE0_MASK (LBP_SPARE_SPARE0_M << LBP_SPARE_SPARE0_SHIFT)
#define LBP_SPARE_SPARE1_M 0x1ULL
#define LBP_SPARE_SPARE1_SHIFT 1
#define LBP_SPARE_SPARE1_MASK (LBP_SPARE_SPARE1_M << LBP_SPARE_SPARE1_SHIFT)
#define LBP_SPARE_SPARE2_M 0x1ULL
#define LBP_SPARE_SPARE2_SHIFT 2
#define LBP_SPARE_SPARE2_MASK (LBP_SPARE_SPARE2_M << LBP_SPARE_SPARE2_SHIFT)
#define LBP_SPARE_SPARE3_M 0x1ULL
#define LBP_SPARE_SPARE3_SHIFT 3
#define LBP_SPARE_SPARE3_MASK (LBP_SPARE_SPARE3_M << LBP_SPARE_SPARE3_SHIFT)
#define LBP_SPARE_SPARE8_M 0x1ULL
#define LBP_SPARE_SPARE8_SHIFT 8
#define LBP_SPARE_SPARE8_MASK (LBP_SPARE_SPARE8_M << LBP_SPARE_SPARE8_SHIFT)
#define LBP_SPARE_SPARE9_M 0x1ULL
#define LBP_SPARE_SPARE9_SHIFT 9
#define LBP_SPARE_SPARE9_MASK (LBP_SPARE_SPARE9_M << LBP_SPARE_SPARE9_SHIFT)
#define LBP_SPARE_SPARE30_M 0x1ULL
#define LBP_SPARE_SPARE30_SHIFT 30
#define LBP_SPARE_SPARE30_MASK (LBP_SPARE_SPARE30_M << LBP_SPARE_SPARE30_SHIFT)
#define LBP_SPARE_SPARE29_M 0x1ULL
#define LBP_SPARE_SPARE29_SHIFT 29
#define LBP_SPARE_SPARE29_MASK (LBP_SPARE_SPARE29_M << LBP_SPARE_SPARE29_SHIFT)
#define LBP_SPARE_SPARE28_M 0x1ULL
#define LBP_SPARE_SPARE28_SHIFT 28
#define LBP_SPARE_SPARE28_MASK (LBP_SPARE_SPARE28_M << LBP_SPARE_SPARE28_SHIFT)
#define LBP_SPARE_SPARE27_M 0x1ULL
#define LBP_SPARE_SPARE27_SHIFT 27
#define LBP_SPARE_SPARE27_MASK (LBP_SPARE_SPARE27_M << LBP_SPARE_SPARE27_SHIFT)
#define LBP_SPARE_SPARE26_M 0x1ULL
#define LBP_SPARE_SPARE26_SHIFT 26
#define LBP_SPARE_SPARE26_MASK (LBP_SPARE_SPARE26_M << LBP_SPARE_SPARE26_SHIFT)
#define LBP_SPARE_SPARE25_M 0x1ULL
#define LBP_SPARE_SPARE25_SHIFT 25
#define LBP_SPARE_SPARE25_MASK (LBP_SPARE_SPARE25_M << LBP_SPARE_SPARE25_SHIFT)
#define LBP_SPARE_SPARE24_M 0x1ULL
#define LBP_SPARE_SPARE24_SHIFT 24
#define LBP_SPARE_SPARE24_MASK (LBP_SPARE_SPARE24_M << LBP_SPARE_SPARE24_SHIFT)
#define LBP_SPARE_SPARE23_M 0x1ULL
#define LBP_SPARE_SPARE23_SHIFT 23
#define LBP_SPARE_SPARE23_MASK (LBP_SPARE_SPARE23_M << LBP_SPARE_SPARE23_SHIFT)
#define LBP_SPARE_SPARE22_M 0x1ULL
#define LBP_SPARE_SPARE22_SHIFT 22
#define LBP_SPARE_SPARE22_MASK (LBP_SPARE_SPARE22_M << LBP_SPARE_SPARE22_SHIFT)
#define LBP_SPARE_SPARE21_M 0x1ULL
#define LBP_SPARE_SPARE21_SHIFT 21
#define LBP_SPARE_SPARE21_MASK (LBP_SPARE_SPARE21_M << LBP_SPARE_SPARE21_SHIFT)
#define LBP_SPARE_SPARE20_M 0x1ULL
#define LBP_SPARE_SPARE20_SHIFT 20
#define LBP_SPARE_SPARE20_MASK (LBP_SPARE_SPARE20_M << LBP_SPARE_SPARE20_SHIFT)
#define LBP_SPARE_SPARE31_M 0x1ULL
#define LBP_SPARE_SPARE31_SHIFT 31
#define LBP_SPARE_SPARE31_MASK (LBP_SPARE_SPARE31_M << LBP_SPARE_SPARE31_SHIFT)

/* Module : IPU_LIB_DREGFILE_STP*/
#define STP_SEL 0x0
#define STP_SEL_DEF 0xf
#define STP_SEL_STP_SEL_M 0xfULL
#define STP_SEL_STP_SEL_SHIFT 0
#define STP_SEL_STP_SEL_MASK (STP_SEL_STP_SEL_M << STP_SEL_STP_SEL_SHIFT)
#define STP_CTRL 0x8
#define STP_CTRL_DEF 0x0
#define STP_CTRL_TS_FR_M 0x1ULL
#define STP_CTRL_TS_FR_SHIFT 4
#define STP_CTRL_TS_FR_MASK (STP_CTRL_TS_FR_M << STP_CTRL_TS_FR_SHIFT)
#define STP_CTRL_ENA_M 0x1ULL
#define STP_CTRL_ENA_SHIFT 0
#define STP_CTRL_ENA_MASK (STP_CTRL_ENA_M << STP_CTRL_ENA_SHIFT)
#define STP_CTRL_RESUME_M 0x1ULL
#define STP_CTRL_RESUME_SHIFT 2
#define STP_CTRL_RESUME_MASK (STP_CTRL_RESUME_M << STP_CTRL_RESUME_SHIFT)
#define STP_CTRL_RESET_M 0x1ULL
#define STP_CTRL_RESET_SHIFT 1
#define STP_CTRL_RESET_MASK (STP_CTRL_RESET_M << STP_CTRL_RESET_SHIFT)
#define STP_CTRL_PC_FR_M 0x1ULL
#define STP_CTRL_PC_FR_SHIFT 3
#define STP_CTRL_PC_FR_MASK (STP_CTRL_PC_FR_M << STP_CTRL_PC_FR_SHIFT)
#define STP_START 0x10
#define STP_START_DEF 0x0
#define STP_START_START_INST_M 0x7ffULL
#define STP_START_START_INST_SHIFT 0
#define STP_START_START_INST_MASK (STP_START_START_INST_M << \
		STP_START_START_INST_SHIFT)
#define STP_MASK 0x18
#define STP_MASK_DEF 0xffff
#define STP_MASK_LBP_MASK_M 0xffffULL
#define STP_MASK_LBP_MASK_SHIFT 0
#define STP_MASK_LBP_MASK_MASK (STP_MASK_LBP_MASK_M << STP_MASK_LBP_MASK_SHIFT)
#define STP_STAT 0x20
#define STP_STAT_DEF 0x7ff
#define STP_STAT_PC_M 0x7ffULL
#define STP_STAT_PC_SHIFT 0
#define STP_STAT_PC_MASK (STP_STAT_PC_M << STP_STAT_PC_SHIFT)
#define STP_STAT_STALLED_M 0x1ULL
#define STP_STAT_STALLED_SHIFT 16
#define STP_STAT_STALLED_MASK (STP_STAT_STALLED_M << STP_STAT_STALLED_SHIFT)
#define STP_CAP 0x28
#define STP_CAP_DEF 0x4080040004000800
#define STP_CAP_HALO_MEM_M 0xffULL
#define STP_CAP_HALO_MEM_SHIFT 56
#define STP_CAP_HALO_MEM_MASK (STP_CAP_HALO_MEM_M << STP_CAP_HALO_MEM_SHIFT)
#define STP_CAP_SCALAR_MEM_M 0xffffULL
#define STP_CAP_SCALAR_MEM_SHIFT 16
#define STP_CAP_SCALAR_MEM_MASK (STP_CAP_SCALAR_MEM_M << \
		STP_CAP_SCALAR_MEM_SHIFT)
#define STP_CAP_CONST_MEM_M 0xffffULL
#define STP_CAP_CONST_MEM_SHIFT 32
#define STP_CAP_CONST_MEM_MASK (STP_CAP_CONST_MEM_M << STP_CAP_CONST_MEM_SHIFT)
#define STP_CAP_INST_MEM_M 0xffffULL
#define STP_CAP_INST_MEM_SHIFT 0
#define STP_CAP_INST_MEM_MASK (STP_CAP_INST_MEM_M << STP_CAP_INST_MEM_SHIFT)
#define STP_CAP_VECTOR_MEM_M 0xffULL
#define STP_CAP_VECTOR_MEM_SHIFT 48
#define STP_CAP_VECTOR_MEM_MASK (STP_CAP_VECTOR_MEM_M << \
		STP_CAP_VECTOR_MEM_SHIFT)
#define STP_ISR 0x30
#define STP_ISR_DEF 0x0
#define STP_ISR_INT_M 0x1ULL
#define STP_ISR_INT_SHIFT 0
#define STP_ISR_INT_MASK (STP_ISR_INT_M << STP_ISR_INT_SHIFT)
#define STP_ISR_ERR_M 0x1ULL
#define STP_ISR_ERR_SHIFT 1
#define STP_ISR_ERR_MASK (STP_ISR_ERR_M << STP_ISR_ERR_SHIFT)
#define STP_ITR 0x38
#define STP_ITR_DEF 0x0
#define STP_ITR_ERR_M 0x1ULL
#define STP_ITR_ERR_SHIFT 1
#define STP_ITR_ERR_MASK (STP_ITR_ERR_M << STP_ITR_ERR_SHIFT)
#define STP_ITR_INT_M 0x1ULL
#define STP_ITR_INT_SHIFT 0
#define STP_ITR_INT_MASK (STP_ITR_INT_M << STP_ITR_INT_SHIFT)
#define STP_IER 0x40
#define STP_IER_DEF 0x3
#define STP_IER_ERR_M 0x1ULL
#define STP_IER_ERR_SHIFT 1
#define STP_IER_ERR_MASK (STP_IER_ERR_M << STP_IER_ERR_SHIFT)
#define STP_IER_INT_M 0x1ULL
#define STP_IER_INT_SHIFT 0
#define STP_IER_INT_MASK (STP_IER_INT_M << STP_IER_INT_SHIFT)
#define STP_IMR 0x48
#define STP_IMR_DEF 0x0
#define STP_IMR_ERR_M 0x1ULL
#define STP_IMR_ERR_SHIFT 1
#define STP_IMR_ERR_MASK (STP_IMR_ERR_M << STP_IMR_ERR_SHIFT)
#define STP_IMR_INT_M 0x1ULL
#define STP_IMR_INT_SHIFT 0
#define STP_IMR_INT_MASK (STP_IMR_INT_M << STP_IMR_INT_SHIFT)
#define STP_ISR_OVF 0x50
#define STP_ISR_OVF_DEF 0x0
#define STP_ISR_OVF_ERR_M 0x1ULL
#define STP_ISR_OVF_ERR_SHIFT 1
#define STP_ISR_OVF_ERR_MASK (STP_ISR_OVF_ERR_M << STP_ISR_OVF_ERR_SHIFT)
#define STP_ISR_OVF_INT_M 0x1ULL
#define STP_ISR_OVF_INT_SHIFT 0
#define STP_ISR_OVF_INT_MASK (STP_ISR_OVF_INT_M << STP_ISR_OVF_INT_SHIFT)
#define STP_IRQ_LOG 0x58
#define STP_IRQ_LOG_DEF 0x0
#define STP_IRQ_LOG_CODE_M 0xffffULL
#define STP_IRQ_LOG_CODE_SHIFT 0
#define STP_IRQ_LOG_CODE_MASK (STP_IRQ_LOG_CODE_M << STP_IRQ_LOG_CODE_SHIFT)
#define STP_ERR_LOG 0x60
#define STP_ERR_LOG_DEF 0x0
#define STP_ERR_LOG_LBP_ID_M 0xfULL
#define STP_ERR_LOG_LBP_ID_SHIFT 0
#define STP_ERR_LOG_LBP_ID_MASK (STP_ERR_LOG_LBP_ID_M << \
		STP_ERR_LOG_LBP_ID_SHIFT)
#define STP_RAM_CTRL 0x68
#define STP_RAM_CTRL_DEF 0x0
#define STP_RAM_CTRL_RAM_TARG_M 0xfULL
#define STP_RAM_CTRL_RAM_TARG_SHIFT 8
#define STP_RAM_CTRL_RAM_TARG_MASK (STP_RAM_CTRL_RAM_TARG_M << \
		STP_RAM_CTRL_RAM_TARG_SHIFT)
#define STP_RAM_CTRL_WRITE_M 0x1ULL
#define STP_RAM_CTRL_WRITE_SHIFT 1
#define STP_RAM_CTRL_WRITE_MASK (STP_RAM_CTRL_WRITE_M << \
		STP_RAM_CTRL_WRITE_SHIFT)
#define STP_RAM_CTRL_RAM_ADDR_M 0xffffULL
#define STP_RAM_CTRL_RAM_ADDR_SHIFT 16
#define STP_RAM_CTRL_RAM_ADDR_MASK (STP_RAM_CTRL_RAM_ADDR_M << \
		STP_RAM_CTRL_RAM_ADDR_SHIFT)
#define STP_RAM_CTRL_RUN_M 0x1ULL
#define STP_RAM_CTRL_RUN_SHIFT 0
#define STP_RAM_CTRL_RUN_MASK (STP_RAM_CTRL_RUN_M << STP_RAM_CTRL_RUN_SHIFT)
#define STP_RAM_CTRL_PRI_M 0x1ULL
#define STP_RAM_CTRL_PRI_SHIFT 2
#define STP_RAM_CTRL_PRI_MASK (STP_RAM_CTRL_PRI_M << STP_RAM_CTRL_PRI_SHIFT)
#define STP_RAM_DATA0 0x70
#define STP_RAM_DATA0_DEF 0x0
#define STP_RAM_DATA0_VAL_M 0xffffffffffffffffULL
#define STP_RAM_DATA0_VAL_SHIFT 0
#define STP_RAM_DATA0_VAL_MASK (STP_RAM_DATA0_VAL_M << STP_RAM_DATA0_VAL_SHIFT)
#define STP_RAM_DATA1 0x78
#define STP_RAM_DATA1_DEF 0x0
#define STP_RAM_DATA1_VAL_M 0xffffffffffffffffULL
#define STP_RAM_DATA1_VAL_SHIFT 0
#define STP_RAM_DATA1_VAL_MASK (STP_RAM_DATA1_VAL_M << STP_RAM_DATA1_VAL_SHIFT)
#define STP_PMON_CFG 0x80
#define STP_PMON_CFG_DEF 0x0
#define STP_PMON_CFG_ENABLE_M 0x1ULL
#define STP_PMON_CFG_ENABLE_SHIFT 0
#define STP_PMON_CFG_ENABLE_MASK (STP_PMON_CFG_ENABLE_M << \
		STP_PMON_CFG_ENABLE_SHIFT)
#define STP_PMON_CNT_0_CFG 0x88
#define STP_PMON_CNT_0_CFG_DEF 0x0
#define STP_PMON_CNT_0_CFG_INC_MATCH_M 0xfULL
#define STP_PMON_CNT_0_CFG_INC_MATCH_SHIFT 43
#define STP_PMON_CNT_0_CFG_INC_MATCH_MASK (STP_PMON_CNT_0_CFG_INC_MATCH_M << \
		STP_PMON_CNT_0_CFG_INC_MATCH_SHIFT)
#define STP_PMON_CNT_0_CFG_INC_SEL_M 0x1fULL
#define STP_PMON_CNT_0_CFG_INC_SEL_SHIFT 32
#define STP_PMON_CNT_0_CFG_INC_SEL_MASK (STP_PMON_CNT_0_CFG_INC_SEL_M << \
		STP_PMON_CNT_0_CFG_INC_SEL_SHIFT)
#define STP_PMON_CNT_0_CFG_DEC_MATCH_M 0xfULL
#define STP_PMON_CNT_0_CFG_DEC_MATCH_SHIFT 59
#define STP_PMON_CNT_0_CFG_DEC_MATCH_MASK (STP_PMON_CNT_0_CFG_DEC_MATCH_M << \
		STP_PMON_CNT_0_CFG_DEC_MATCH_SHIFT)
#define STP_PMON_CNT_0_CFG_DEC_SEL_M 0x1fULL
#define STP_PMON_CNT_0_CFG_DEC_SEL_SHIFT 48
#define STP_PMON_CNT_0_CFG_DEC_SEL_MASK (STP_PMON_CNT_0_CFG_DEC_SEL_M << \
		STP_PMON_CNT_0_CFG_DEC_SEL_SHIFT)
#define STP_PMON_CNT_0_CFG_THRESHOLD_M 0xffULL
#define STP_PMON_CNT_0_CFG_THRESHOLD_SHIFT 3
#define STP_PMON_CNT_0_CFG_THRESHOLD_MASK (STP_PMON_CNT_0_CFG_THRESHOLD_M << \
		STP_PMON_CNT_0_CFG_THRESHOLD_SHIFT)
#define STP_PMON_CNT_0_CFG_INC_INV_M 0x1ULL
#define STP_PMON_CNT_0_CFG_INC_INV_SHIFT 47
#define STP_PMON_CNT_0_CFG_INC_INV_MASK (STP_PMON_CNT_0_CFG_INC_INV_M << \
		STP_PMON_CNT_0_CFG_INC_INV_SHIFT)
#define STP_PMON_CNT_0_CFG_DEC_MASK_M 0xfULL
#define STP_PMON_CNT_0_CFG_DEC_MASK_SHIFT 55
#define STP_PMON_CNT_0_CFG_DEC_MASK_MASK (STP_PMON_CNT_0_CFG_DEC_MASK_M << \
		STP_PMON_CNT_0_CFG_DEC_MASK_SHIFT)
#define STP_PMON_CNT_0_CFG_MODE_M 0x7ULL
#define STP_PMON_CNT_0_CFG_MODE_SHIFT 0
#define STP_PMON_CNT_0_CFG_MODE_MASK (STP_PMON_CNT_0_CFG_MODE_M << \
		STP_PMON_CNT_0_CFG_MODE_SHIFT)
#define STP_PMON_CNT_0_CFG_DEC_INV_M 0x1ULL
#define STP_PMON_CNT_0_CFG_DEC_INV_SHIFT 63
#define STP_PMON_CNT_0_CFG_DEC_INV_MASK (STP_PMON_CNT_0_CFG_DEC_INV_M << \
		STP_PMON_CNT_0_CFG_DEC_INV_SHIFT)
#define STP_PMON_CNT_0_CFG_INC_MASK_M 0xfULL
#define STP_PMON_CNT_0_CFG_INC_MASK_SHIFT 39
#define STP_PMON_CNT_0_CFG_INC_MASK_MASK (STP_PMON_CNT_0_CFG_INC_MASK_M << \
		STP_PMON_CNT_0_CFG_INC_MASK_SHIFT)
#define STP_PMON_CNT_0 0x90
#define STP_PMON_CNT_0_DEF 0x0
#define STP_PMON_CNT_0_CNT_M 0xffffffffffULL
#define STP_PMON_CNT_0_CNT_SHIFT 0
#define STP_PMON_CNT_0_CNT_MASK (STP_PMON_CNT_0_CNT_M << \
		STP_PMON_CNT_0_CNT_SHIFT)
#define STP_PMON_CNT_0_STS_ACC 0x98
#define STP_PMON_CNT_0_STS_ACC_DEF 0x0
#define STP_PMON_CNT_0_STS_ACC_VAL_M 0xffULL
#define STP_PMON_CNT_0_STS_ACC_VAL_SHIFT 0
#define STP_PMON_CNT_0_STS_ACC_VAL_MASK (STP_PMON_CNT_0_STS_ACC_VAL_M << \
		STP_PMON_CNT_0_STS_ACC_VAL_SHIFT)
#define STP_PMON_CNT_0_STS 0xa0
#define STP_PMON_CNT_0_STS_DEF 0x0
#define STP_PMON_CNT_0_STS_ACC_UF_M 0x1ULL
#define STP_PMON_CNT_0_STS_ACC_UF_SHIFT 1
#define STP_PMON_CNT_0_STS_ACC_UF_MASK (STP_PMON_CNT_0_STS_ACC_UF_M << \
		STP_PMON_CNT_0_STS_ACC_UF_SHIFT)
#define STP_PMON_CNT_0_STS_ACC_OF_M 0x1ULL
#define STP_PMON_CNT_0_STS_ACC_OF_SHIFT 0
#define STP_PMON_CNT_0_STS_ACC_OF_MASK (STP_PMON_CNT_0_STS_ACC_OF_M << \
		STP_PMON_CNT_0_STS_ACC_OF_SHIFT)
#define STP_PMON_CNT_0_STS_CNT_OF_M 0x1ULL
#define STP_PMON_CNT_0_STS_CNT_OF_SHIFT 2
#define STP_PMON_CNT_0_STS_CNT_OF_MASK (STP_PMON_CNT_0_STS_CNT_OF_M << \
		STP_PMON_CNT_0_STS_CNT_OF_SHIFT)
#define STP_PMON_CNT_1_CFG 0xa8
#define STP_PMON_CNT_1_CFG_DEF 0x0
#define STP_PMON_CNT_1_CFG_MODE_M 0x7ULL
#define STP_PMON_CNT_1_CFG_MODE_SHIFT 0
#define STP_PMON_CNT_1_CFG_MODE_MASK (STP_PMON_CNT_1_CFG_MODE_M << \
		STP_PMON_CNT_1_CFG_MODE_SHIFT)
#define STP_PMON_CNT_1_CFG_DEC_MASK_M 0xfULL
#define STP_PMON_CNT_1_CFG_DEC_MASK_SHIFT 55
#define STP_PMON_CNT_1_CFG_DEC_MASK_MASK (STP_PMON_CNT_1_CFG_DEC_MASK_M << \
		STP_PMON_CNT_1_CFG_DEC_MASK_SHIFT)
#define STP_PMON_CNT_1_CFG_INC_INV_M 0x1ULL
#define STP_PMON_CNT_1_CFG_INC_INV_SHIFT 47
#define STP_PMON_CNT_1_CFG_INC_INV_MASK (STP_PMON_CNT_1_CFG_INC_INV_M << \
		STP_PMON_CNT_1_CFG_INC_INV_SHIFT)
#define STP_PMON_CNT_1_CFG_INC_MASK_M 0xfULL
#define STP_PMON_CNT_1_CFG_INC_MASK_SHIFT 39
#define STP_PMON_CNT_1_CFG_INC_MASK_MASK (STP_PMON_CNT_1_CFG_INC_MASK_M << \
		STP_PMON_CNT_1_CFG_INC_MASK_SHIFT)
#define STP_PMON_CNT_1_CFG_INC_MATCH_M 0xfULL
#define STP_PMON_CNT_1_CFG_INC_MATCH_SHIFT 43
#define STP_PMON_CNT_1_CFG_INC_MATCH_MASK (STP_PMON_CNT_1_CFG_INC_MATCH_M << \
		STP_PMON_CNT_1_CFG_INC_MATCH_SHIFT)
#define STP_PMON_CNT_1_CFG_DEC_INV_M 0x1ULL
#define STP_PMON_CNT_1_CFG_DEC_INV_SHIFT 63
#define STP_PMON_CNT_1_CFG_DEC_INV_MASK (STP_PMON_CNT_1_CFG_DEC_INV_M << \
		STP_PMON_CNT_1_CFG_DEC_INV_SHIFT)
#define STP_PMON_CNT_1_CFG_DEC_MATCH_M 0xfULL
#define STP_PMON_CNT_1_CFG_DEC_MATCH_SHIFT 59
#define STP_PMON_CNT_1_CFG_DEC_MATCH_MASK (STP_PMON_CNT_1_CFG_DEC_MATCH_M << \
		STP_PMON_CNT_1_CFG_DEC_MATCH_SHIFT)
#define STP_PMON_CNT_1_CFG_THRESHOLD_M 0xffULL
#define STP_PMON_CNT_1_CFG_THRESHOLD_SHIFT 3
#define STP_PMON_CNT_1_CFG_THRESHOLD_MASK (STP_PMON_CNT_1_CFG_THRESHOLD_M << \
		STP_PMON_CNT_1_CFG_THRESHOLD_SHIFT)
#define STP_PMON_CNT_1_CFG_INC_SEL_M 0x1fULL
#define STP_PMON_CNT_1_CFG_INC_SEL_SHIFT 32
#define STP_PMON_CNT_1_CFG_INC_SEL_MASK (STP_PMON_CNT_1_CFG_INC_SEL_M << \
		STP_PMON_CNT_1_CFG_INC_SEL_SHIFT)
#define STP_PMON_CNT_1_CFG_DEC_SEL_M 0x1fULL
#define STP_PMON_CNT_1_CFG_DEC_SEL_SHIFT 48
#define STP_PMON_CNT_1_CFG_DEC_SEL_MASK (STP_PMON_CNT_1_CFG_DEC_SEL_M << \
		STP_PMON_CNT_1_CFG_DEC_SEL_SHIFT)
#define STP_PMON_CNT_1 0xb0
#define STP_PMON_CNT_1_DEF 0x0
#define STP_PMON_CNT_1_CNT_M 0xffffffffffULL
#define STP_PMON_CNT_1_CNT_SHIFT 0
#define STP_PMON_CNT_1_CNT_MASK (STP_PMON_CNT_1_CNT_M << \
		STP_PMON_CNT_1_CNT_SHIFT)
#define STP_PMON_CNT_1_STS_ACC 0xb8
#define STP_PMON_CNT_1_STS_ACC_DEF 0x0
#define STP_PMON_CNT_1_STS_ACC_VAL_M 0xffULL
#define STP_PMON_CNT_1_STS_ACC_VAL_SHIFT 0
#define STP_PMON_CNT_1_STS_ACC_VAL_MASK (STP_PMON_CNT_1_STS_ACC_VAL_M << \
		STP_PMON_CNT_1_STS_ACC_VAL_SHIFT)
#define STP_PMON_CNT_1_STS 0xc0
#define STP_PMON_CNT_1_STS_DEF 0x0
#define STP_PMON_CNT_1_STS_CNT_OF_M 0x1ULL
#define STP_PMON_CNT_1_STS_CNT_OF_SHIFT 2
#define STP_PMON_CNT_1_STS_CNT_OF_MASK (STP_PMON_CNT_1_STS_CNT_OF_M << \
		STP_PMON_CNT_1_STS_CNT_OF_SHIFT)
#define STP_PMON_CNT_1_STS_ACC_UF_M 0x1ULL
#define STP_PMON_CNT_1_STS_ACC_UF_SHIFT 1
#define STP_PMON_CNT_1_STS_ACC_UF_MASK (STP_PMON_CNT_1_STS_ACC_UF_M << \
		STP_PMON_CNT_1_STS_ACC_UF_SHIFT)
#define STP_PMON_CNT_1_STS_ACC_OF_M 0x1ULL
#define STP_PMON_CNT_1_STS_ACC_OF_SHIFT 0
#define STP_PMON_CNT_1_STS_ACC_OF_MASK (STP_PMON_CNT_1_STS_ACC_OF_M << \
		STP_PMON_CNT_1_STS_ACC_OF_SHIFT)

#endif /* __IPU_REGS_V2_GENERATED_H__ */