| /* |
| * Copyright (C) 2018 Samsung Electronics Co., Ltd. |
| * |
| * Authors: Shaik Ameer Basha(shaik.ameer@samsung.com) |
| * |
| * Airbrush DDR header. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| */ |
| |
| #ifndef _AIRBRUSH_DDR_INTERNAL_H_ |
| #define _AIRBRUSH_DDR_INTERNAL_H_ |
| |
| #include <linux/mfd/abc-pcie.h> |
| #include "airbrush-otp.h" |
| #include "airbrush-ddr.h" |
| |
| #define AB_DDR_CACHE_UNKNOWN 0xFFFFFFFF |
| #define PLL_LOCKTIME_PLL_PHY_MIF 0x10510008 |
| #define PLL_CON0_PLL_PHY_MIF 0x10510140 |
| #define PLL_MUX_SEL_MSK (0x1 << 4) |
| #define PLL_MUX_SEL(x) (x << 4) |
| #define PLL_MUX_SEL_OSCCLK (0x0) |
| #define PLL_MUX_SEL_PLLOUT (0x1) |
| #define DIV_S_MSK (0x7 << 0) |
| #define DIV_S(x) (((x) & 0x7) << 0) |
| #define DIV_P_MSK (0x3f << 8) |
| #define DIV_P(x) (((x) & 0x3f) << 8) |
| #define DIV_M_MSK (0x3ff << 16) |
| #define DIV_M(x) (((x) & 0x3ff) << 16) |
| #define PLL_PMS_MSK (DIV_P_MSK | DIV_M_MSK | DIV_S_MSK) |
| #define PLL_PMS(p, m, s) (DIV_P(p) | DIV_M(m) | DIV_S(s)) |
| #define PLL_STABLE (0x1 << 29) |
| #define PLL_ENABLE (0x1 << 31) |
| |
| #define CLK_CON_DIV_DFI_DIV2 0x10511800 |
| #define CLK_CON_DIV_DIV2_PLLCLK_MIF 0x10511804 |
| #define CLK_CON_DIV_DIV4_PLLCLK_MIF 0x10511808 |
| #define PHY0_INIT_CTRL_REG 0x10530400 |
| |
| #define PHY1_INIT_CTRL_REG 0x10530500 |
| #define INIT_PLL_IS_STABLE (0x1 << 0) |
| |
| #define PHY0_RST_CTRL_REG 0x10530404 |
| #define PHY1_RST_CTRL_REG 0x10530504 |
| #define RST_N (0x1 << 15) |
| #define DIV_RST_N (0x1 << 7) |
| |
| #define MIF_PLL_WRAP_CTRL_REG 0x10530510 |
| #define SEL_CLKMUX_PLL (0x1 << 1) |
| #define DDRPHY2XCLKGATE_ENABLE (0x1 << 2) |
| #define WRAP_PLL_IS_STABLE (0x1 << 3) |
| |
| #define DREX_BASE_ADDR 0x10580000 |
| #define DPHY_BASE_ADDR 0x105b0000 |
| #define DPHY2_BASE_ADDR 0x105c0000 |
| |
| #define DREX_CONCONTROL 0x10580000 |
| #define UPDATE_MODE (0x1 << 3) |
| #define AREF_EN (0x1 << 5) |
| #define DFI_INIT_START_PHY2 (0x1 << 15) |
| #define DFI_INIT_START (0x1 << 28) |
| |
| #define DREX_MEMCONTROL 0x10580004 |
| #define CLK_STOP_EN (0x1 << 0) |
| #define DPWRDN_EN (0x1 << 1) |
| #define DPWRDN_TYPE_MSK (0x3 << 2) |
| #define DPWRDN_TYPE(x) (((x) & 0x3) << 2) |
| #define ACTIVE_PRECHARGE_PD (0x0) |
| #define FORCED_PRECHARGE_PD (0x1) |
| #define PB_REF_EN (0x1 << 27) |
| #define DBI_EN (0x1 << 23) |
| |
| #define DREX_CGCONTROL 0x10580008 |
| #define PHY_CG_EN (0x1 << 4) |
| |
| #define DREX_DIRECTCMD 0x10580010 |
| #define CMD_TYPE_MRW (0x0 << 24) |
| #define CMD_TYPE_NOP (0x3 << 24) |
| #define CMD_TYPE_SREF_ENTR (0x4 << 24) |
| #define CMD_TYPE_REFA (0x5 << 24) |
| #define CMD_TYPE_CKEL (0x6 << 24) |
| #define CMD_TYPE_PD_EXIT (0x7 << 24) |
| #define CMD_TYPE_SREF_EXIT (0x8 << 24) |
| #define CMD_TYPE_MRR (0x9 << 24) |
| |
| #define MR2CMD(mr) \ |
| ((((mr) & 0x7) << 10) | ((((mr) >> 3) & 0x7) << 16) | (((mr) >> 6) & 0x3)) |
| #define OP2CMD(op) (((op) & 0xff) << 2) |
| #define MRR(mr) (CMD_TYPE_MRR | MR2CMD(mr)) |
| #define MRW(mr, op) (CMD_TYPE_MRW | MR2CMD(mr) | OP2CMD(op)) |
| |
| /* MR1 register configurations */ |
| #define MRW1_1866 (MRW(1, 0x6e)) |
| #define MRW1_1600 (MRW(1, 0x5e)) |
| #define MRW1_1200 (MRW(1, 0x4e)) |
| #define MRW1_933 (MRW(1, 0x36)) |
| #define MRW1_800 (MRW(1, 0x26)) |
| |
| /* MR2 register configurations */ |
| #define MRW2_1866 (MRW(2, 0x36)) |
| #define MRW2_1600 (MRW(2, 0x2d)) |
| #define MRW2_1200 (MRW(2, 0x24)) |
| #define MRW2_933 (MRW(2, 0x1b)) |
| #define MRW2_800 (MRW(2, 0x12)) |
| |
| /* MR3 register configurations */ |
| #define MRW3_DEFAULT (MRW(3, 0xf1)) |
| |
| /* MR11 register configurations */ |
| #define MRW11_DEFAULT (MRW(11, 0x24)) |
| |
| /* MR22 register configurations */ |
| #define MRW22_DEFAULT (MRW(22, 0x14)) |
| |
| /* MR8 register configurations */ |
| #define MRR8_READ (MRR(8)) |
| |
| /* MR13 register configurations */ |
| #define MR13_VRCG_NORMAL (0x0 << 3) |
| #define MR13_VRCG_FAST_RESP (0x1 << 3) |
| #define MR13_RRO_DISABLE (0x0 << 4) |
| #define MR13_RRO_EN_2x_4x (0x1 << 4) |
| #ifdef CONFIG_AB_DDR_MR13_RRO_ENABLE |
| #define MRW13_DEFAULT_OP (MR13_VRCG_FAST_RESP | MR13_RRO_EN_2x_4x) |
| #define MRW13_FAST_RESP_DIS_OP (MR13_VRCG_NORMAL | MR13_RRO_EN_2x_4x) |
| #else |
| #define MRW13_DEFAULT_OP (MR13_VRCG_FAST_RESP) |
| #define MRW13_FAST_RESP_DIS_OP (MR13_VRCG_NORMAL) |
| #endif |
| #define MRW13_DEFAULT (MRW(13, MRW13_DEFAULT_OP)) |
| #define MRW13_FAST_RESP_DIS (MRW(13, MRW13_FAST_RESP_DIS_OP)) |
| |
| #define DREX_PRECHCONFIG0 0x10580014 |
| #define PORT_POLICY_MSK (0xf << 16) |
| #define PORT_POLICY(x) (((x) & 0xf) << 16) |
| #define PORT_POLICY_OPEN_PAGE (0x0) |
| #define PORT_POLICY_CLOSE_PAGE (0xf) /* for all ports */ |
| #define TP_EN_MSK (0xf << 28) |
| |
| #define DREX_PHYCONTROL0 0x10580018 |
| #define FP_RESYNC (0x1 << 3) |
| #define PAUSE_NO_RELOCK (0x1 << 7) |
| |
| #define DREX_TIMINGRFCPB 0x10580020 |
| #define t_rfcpb0(x) (((x) & 0x7f) << 0) |
| #define t_rfcpb1(x) (((x) & 0x7f) << 8) |
| #define TMGPBR_1866 (t_rfcpb0(0x42) | t_rfcpb1(0x42)) |
| #define TMGPBR_1600 (t_rfcpb0(0x38) | t_rfcpb1(0x38)) |
| #define TMGPBR_1200 (t_rfcpb0(0x2b) | t_rfcpb1(0x2b)) |
| #define TMGPBR_933 (t_rfcpb0(0x21) | t_rfcpb1(0x21)) |
| #define TMGPBR_800 (t_rfcpb0(0x1c) | t_rfcpb1(0x1c)) |
| |
| #define DREX_PWRDNCONFIG 0x10580028 |
| #define PWRDNCONFIG_DEFAULT (0xffff00ff) |
| |
| #define DREX_TIMINGARE 0x10580030 |
| #define T_REFI(x) (((x) & 0xffff) << 0) |
| #define T_REFIPB(x) (((x) & 0xffff) << 16) |
| #define TIMINGARE(refi, refipb) (T_REFI(refi) | T_REFIPB(refipb)) |
| #define T_REFI_1x (0x49) |
| #define T_REFIPB_1x (0x9) |
| #define T_REFI_0_50x (0x25) |
| #define T_REFIPB_0_50x (0x4) |
| #define T_REFI_0_25x (0x12) |
| #define T_REFIPB_0_25x (0x2) |
| #ifdef CONFIG_AB_DDR_MR13_RRO_ENABLE |
| #define T_REFI_4x (0x12c) |
| #define T_REFIPB_4x (0x25) |
| #define T_REFI_2x (0x96) |
| #define T_REFIPB_2x (0x13) |
| #else |
| #define T_REFI_4x T_REFI_1x |
| #define T_REFIPB_4x T_REFIPB_1x |
| #define T_REFI_2x T_REFI_1x |
| #define T_REFIPB_2x T_REFIPB_1x |
| #endif |
| #define T_REFI_DEFAULT T_REFI_1x |
| #define T_REFIPB_DEFAULT T_REFIPB_1x |
| |
| #define DREX_TIMINGROW0 0x10580034 |
| #define t_ras(x) (((x) & 0x3f) << 0) |
| #define t_rc(x) (((x) & 0x3f) << 6) |
| #define t_rcd(x) (((x) & 0xf) << 12) |
| #define t_rp(x) (((x) & 0xf) << 16) |
| #define t_rrd(x) (((x) & 0xf) << 20) |
| #define t_rfc(x) (((x) & 0xff) << 24) |
| #define TMGROW_1866 \ |
| (t_ras(0x15) | t_rc(0x20) | t_rcd(0xa) | t_rp(0xb) | t_rrd(0x6) | t_rfc(0x83)) |
| #define TMGROW_1600 \ |
| (t_ras(0x12) | t_rc(0x1b) | t_rcd(0x8) | t_rp(0xa) | t_rrd(0x5) | t_rfc(0x70)) |
| #define TMGROW_1200 \ |
| (t_ras(0x0e) | t_rc(0x15) | t_rcd(0x6) | t_rp(0x7) | t_rrd(0x4) | t_rfc(0x55)) |
| #define TMGROW_933 \ |
| (t_ras(0x0b) | t_rc(0x10) | t_rcd(0x5) | t_rp(0x6) | t_rrd(0x3) | t_rfc(0x42)) |
| #define TMGROW_800 \ |
| (t_ras(0x09) | t_rc(0x0e) | t_rcd(0x4) | t_rp(0x5) | t_rrd(0x3) | t_rfc(0x38)) |
| |
| |
| #define DREX_TIMINGDATA0 0x10580038 |
| #define rl(x) (((x) & 0x3f) << 0) |
| #define r_to_w(x) (((x) & 0x1f) << 6) |
| #define wl(x) (((x) & 0x1f) << 11) |
| #define t_rtp(x) (((x) & 0xf) << 20) |
| #define t_wr(x) (((x) & 0xf) << 24) |
| #define t_wtr(x) (((x) & 0xf) << 28) |
| #define TMGDTA_1866 \ |
| (rl(0x24) | r_to_w(0x11) | wl(0x10) | t_rtp(0x4) | t_wr(0xa) | t_wtr(0x6)) |
| #define TMGDTA_1600 \ |
| (rl(0x20) | r_to_w(0x0e) | wl(0x0e) | t_rtp(0x3) | t_wr(0x8) | t_wtr(0x5)) |
| #define TMGDTA_1200 \ |
| (rl(0x1c) | r_to_w(0x0e) | wl(0x0c) | t_rtp(0x3) | t_wr(0x7) | t_wtr(0x4)) |
| #define TMGDTA_933 \ |
| (rl(0x16) | r_to_w(0x0b) | wl(0x0a) | t_rtp(0x2) | t_wr(0x5) | t_wtr(0x3)) |
| #define TMGDTA_800 \ |
| (rl(0x10) | r_to_w(0x0c) | wl(0x08) | t_rtp(0x2) | t_wr(0x4) | t_wtr(0x3)) |
| |
| |
| #define DREX_TIMINGPOWER0 0x1058003c |
| #define t_mrd(x) (((x) & 0xf) << 0) |
| #define t_cke(x) (((x) & 0xf) << 4) |
| #define t_xp(x) (((x) & 0xff) << 8) |
| #define t_xsr(x) (((x) & 0x3ff) << 16) |
| #define t_faw(x) (((x) & 0x3f) << 26) |
| #define TMGPWR_1866 \ |
| (t_mrd(0x1) | t_cke(0x7) | t_xp(0x4) | t_xsr(0x88) | t_faw(0x13)) |
| #define TMGPWR_1600 \ |
| (t_mrd(0x1) | t_cke(0x7) | t_xp(0x3) | t_xsr(0x74) | t_faw(0x10)) |
| #define TMGPWR_1200 \ |
| (t_mrd(0x1) | t_cke(0x7) | t_xp(0x3) | t_xsr(0x58) | t_faw(0x0d)) |
| #define TMGPWR_933 \ |
| (t_mrd(0x1) | t_cke(0x7) | t_xp(0x2) | t_xsr(0x45) | t_faw(0x0a)) |
| #define TMGPWR_800 \ |
| (t_mrd(0x1) | t_cke(0x7) | t_xp(0x2) | t_xsr(0x3b) | t_faw(0x08)) |
| |
| #define DREX_PHYSTATUS 0x10580040 |
| #define DFI_INIT_COMPLETE_ALL (0x3 << 3) |
| #define TRAIN_COMPLETE_ALL (0x3 << 14) |
| |
| #define DREX_ETCTIMING 0x10580044 |
| |
| #define DREX_CHIPSTATUS 0x10580048 |
| #define CHIP_SREF_STATE(n) (0x1 << (8 + n)) |
| #define CHIP_SREF_ENTRY(n) (0x1 << (8 + n)) |
| #define CHIP_SREF_EXIT(n) (0x0 << (8 + n)) |
| |
| #define DREX_RDFETCH0 0x1058004c |
| #define DREX_RDFETCH1 0x10580050 |
| #define DREX_MRSTATUS 0x10580054 |
| #define DREX_TIMINGSETSW 0x105800e0 |
| #define TIMING_SET_SW_CON (0x1 << 0) |
| |
| #define DREX_TIMINGROW1 0x105800e4 |
| #define DREX_TIMINGDATA1 0x105800e8 |
| #define DREX_TIMINGPOWER1 0x105800ec |
| |
| #define DREX_PPCCLKCON 0x10580130 |
| #define PEREV_CLK_EN (0x1 << 0) |
| |
| /* Performance Event Configuration Registers */ |
| #define DREX_PEREVCONFIG0 0x10580134 |
| #define DREX_PEREVCONFIG1 0x10580138 |
| #define DREX_PEREVCONFIG2 0x1058013c |
| #define DREX_PEREVCONFIG3 0x10580140 |
| #define DREX_PEREVCONFIG(x) (0x10580134 + ((x) * 4)) |
| #define PEREVx_SEL(evt) (((evt) & 0xff) << 0) |
| |
| #define DREX_ALL_INIT_INDI 0x10580400 |
| #define ALL_INIT_DONE (0x1 << 0) |
| |
| #define DREX_HWP_TRAIN_PERIOD0 0x10580420 |
| #define T_PTRAIN_PERIOD_PER_MSEC (19200000 / 1000) |
| #define T_PTRAIN_PERIOD(msec) ((msec) * T_PTRAIN_PERIOD_PER_MSEC) |
| |
| #define DREX_INIT_TRAIN_CONFIG 0x10580430 |
| #define INIT_READ_TRAIN_CHIP0 (0x1 << 1) |
| #define INIT_WRITE_TRAIN_CHIP0 (0x1 << 2) |
| |
| #define DREX_INIT_TRAIN_CONTROL 0x10580434 |
| #define INIT_TRAIN_START (0x1 << 0) |
| |
| #define DREX_HWPR_TRAIN_CONFIG0 0x10580440 |
| #define PERIODIC_WRITE_CHIP0 (0x1 << 10) |
| |
| #define DREX_HWPR_TRAIN_CONTROL0 0x10580450 |
| #define HW_PERIODIC_TRAIN_EN (0x1 << 1) |
| |
| #define DREX_WRTRA_PATTERN0 0x10580460 |
| #define DREX_WRTRA_PATTERN1 0x10580464 |
| #define DREX_WRTRA_PATTERN2 0x10580468 |
| #define DREX_EMPTY_STATE 0x10580504 |
| #define IDLE_STATE_MASK (0x7fff) |
| #define DREX_TRAIN_STATE 0x10580704 |
| #define DREX_DFIRSTCONTROL 0x10580708 |
| #define DFI_RESET_CONTROL (0x1 << 0) |
| #define PB_WA_EN (0x1 << 8) |
| |
| #define DREX_ACTIVATE_AXI_READY 0x10580714 |
| #define ACTIVATE_AXI_READY (0x1 << 0) |
| |
| #define DREX_1CHIP_MASKING 0x1058076c |
| |
| #define DREX_PMNC_PCC 0x1058E000 |
| #define PPC_ENABLE (0x1 << 0) |
| #define PPC_COUNTER_RESET (0x1 << 1) |
| #define CYCLECNT_RESET (0x1 << 2) |
| #define CYCLECNT_DIVIDER (0x1 << 3) |
| #define PPC_START_MODE_MSK (0x1 << 16) |
| #define PPC_START_MODE_SW (0x0 << 16) |
| #define PPC_START_MODE_HW (0x1 << 16) |
| |
| /* Count Enable Set Register */ |
| #define DREX_CNTENS_PCC 0x1058E010 |
| #define PPC_PMCNT_ENABLE(idx) (0x1 << (idx)) |
| #define PPC_CCNT_ENABLE (0x1 << 31) |
| |
| /* Count Enable Clear Register */ |
| #define DREX_CNTENC_PCC 0x1058E020 |
| #define PPC_PMCNT_DISABLE(idx) (0x1 << (idx)) |
| #define PPC_CCNT_DISABLE (0x1 << 31) |
| |
| /* Interrupt Enable Set Register */ |
| #define DREX_INTENS_PCC 0x1058E030 |
| #define PPC_PMCNT_INTSET(idx) (0x1 << (idx)) |
| #define PPC_CCNT_INTSET (0x1 << 31) |
| |
| /* Interrupt Enable Clear Register */ |
| #define DREX_INTENC_PCC 0x1058E040 |
| #define PPC_PMCNT_INTCLR(idx) (0x1 << (idx)) |
| #define PPC_CCNT_INTCLR (0x1 << 31) |
| |
| /* Overflow Flag Status Register */ |
| #define DREX_FLAG_PCC 0x1058E050 |
| #define PPC_PMCNT_FLAG(idx) (0x1 << (idx)) |
| #define PPC_CCNT_FLAG (0x1 << 31) |
| |
| /* Cycle Count Register */ |
| #define DREX_CCCNT_PPC 0x1058E100 |
| |
| /* Performance Monitor Count0 Register */ |
| #define DREX_PMCNT_PPC(x) (0x1058E110 + ((x) * 0x10)) |
| |
| /* configure dram base as 0x20000000 and size as 512MB */ |
| #define DREX_ASP_MEMBASECONFIG0 0x10590f00 |
| #define CHUNK_START_END (0x20009) |
| |
| #define DREX_ASP_MEMCONFIG0 0x10590f10 |
| #define DREX_ASP_CHIP0SIZECONFIG 0x10590f20 |
| #define CHIP_SIZE_512MB (0x1 << 0) |
| |
| #define DPHY_GNR_CON0 0x105b0000 |
| #define CTRL_UPD_TIME(x) (((x) & 0x3) << 30) |
| #define CTRL_UPD_RANGE(x) (((x) & 0x3) << 28) |
| #define CTRL_DFDQS (0x1 << 26) |
| #define DVFS_GATE_UPD_MODE (0x1 << 20) |
| #define CTRL_DDR_MODE(x) (((x) & 0x3) << 24) |
| #define CTRL_OTF_BL (0x1 << 14) |
| #define CTRL_BSTLEN(x) (((x) & 0x3f) << 8) |
| #define BSTLEN_16 (0x10) |
| #define BSTLEN_32 (0x20) |
| #define RL_1866 (0x24) |
| #define RL_1600 (0x20) |
| #define RL_1200 (0x1c) |
| #define RL_933 (0x16) |
| #define RL_800 (0x10) |
| #define GNRCON_INIT \ |
| (CTRL_UPD_TIME(0x1) | CTRL_DDR_MODE(3) | CTRL_OTF_BL | CTRL_BSTLEN(BSTLEN_16) |\ |
| CTRL_UPD_RANGE(0x3)) |
| #define GNRCON_INIT_1866 (GNRCON_INIT | RL_1866) |
| #define GNRCON_INIT_1600 (GNRCON_INIT | RL_1600) |
| #define GNRCON_INIT_1200 (GNRCON_INIT | RL_1200) |
| #define GNRCON_INIT_933 (GNRCON_INIT | RL_933) |
| #define GNRCON_INIT_800 (GNRCON_INIT | RL_800) |
| |
| #define DPHY_CAL_CON0 0x105b0004 |
| #define WRLVL_MODE (0x1 << 0) |
| #define GATE_CAL_MODE (0x1 << 1) |
| #define CA_CAL_MODE (0x1 << 2) |
| #define RD_CAL_MODE (0x1 << 3) |
| #define WR_CAL_MODE (0x1 << 5) |
| #define DVFS_WR_TRAIN_EN (0x1 << 26) |
| |
| #define DPHY_CAL_CON1 0x105b0008 |
| #define RDLVL_PERIODIC_INCR_ADJ_MSK (0x7f << 0) |
| #define RDLVL_PERIODIC_INCR_ADJ(x) (((x) & 0x7f) << 0) |
| #define GLVL_PERIODIC_INCR_ADJ_MSK (0x7f << 7) |
| #define GLVL_PERIODIC_INCR_ADJ(x) (((x) & 0x7f) << 7) |
| #define RDLVL_PASS_ADJ_MSK (0xf << 16) |
| #define RDLVL_PASS_ADJ(x) (((x) & 0xf) << 16) |
| |
| #define DPHY_CAL_CON2 0x105b000c |
| #define CTRL_READADJ_MSK (0xf << 12) |
| #define CTRL_READADJ(x) (((x) & 0xf) << 12) |
| #define CTRL_READDURADJ_MSK (0xf << 16) |
| #define CTRL_READDURADJ(x) (((x) & 0xf) << 16) |
| #define CTRL_GATEADJ_MSK (0xf << 20) |
| #define CTRL_GATEADJ(x) (((x) & 0xf) << 20) |
| #define CTRL_GATEDURADJ_MSK (0xf << 24) |
| #define CTRL_GATEDURADJ(x) (((x) & 0xf) << 24) |
| #define CTRL_SHGATE (0x1 << 29) |
| #define CTRL_RODT_DISABLE (0x1 << 30) |
| #define CTRL_RPRE_OPT (0x1 << 31) |
| #define CON2_FREQ_HIGH \ |
| (CTRL_GATEDURADJ(4) | CTRL_READDURADJ(7) | CTRL_RPRE_OPT) |
| #define CON2_FREQ_LOW \ |
| (CTRL_GATEDURADJ(4) | CTRL_READDURADJ(5)) |
| |
| #define DPHY_CAL_CON3 0x105b0010 |
| #define PRBS_SW_MODE (0x1 << 6) |
| #define RD_SW_MODE (0x1 << 8) |
| #define WR_SW_MODE (0x1 << 9) |
| #define AUTO_DQS_CLEAN (0x1 << 11) |
| |
| #define DPHY_CAL_CON4 0x105b0014 |
| #define GLITCH_REMOVAL_EN (0x1 << 22) |
| #define GLVL_PERIODIC_FINE_INCR_ADJ_MSK (0x7f << 24) |
| #define GLVL_PERIODIC_FINE_INCR_ADJ(x) (((x) & 0x7f) << 24) |
| |
| #define DPHY_LP_CON0 0x105b0018 |
| #define CTRL_PULLD_DQS (0x3 << 0) |
| #define MDLL_CG_EN (0x1 << 11) |
| #define PCL_PD (0x1 << 12) |
| #define DS_IO_PD (0x1 << 14) |
| #define CTRL_PULLD_DQ (0x3 << 16) |
| |
| #define DPHY_GATE_CON0 0x105b001c |
| #define GATE_CON0_DEFAULT (0xf00ffff) |
| |
| #define DPHY_OFFSETR_CON0 0x105b0020 |
| #define CTRL_OFFSETR0_MSK (0x1ff << 0) |
| #define CTRL_OFFSETR0(x) (((x) & 0x1ff) << 0) |
| #define CTRL_OFFSETR1_MSK (0x1ff << 16) |
| #define CTRL_OFFSETR1(x) (((x) & 0x1ff) << 16) |
| |
| #define DPHY_OFFSETW_CON0 0x105b0030 |
| #define CTRL_OFFSETW0_MSK (0x1ff << 0) |
| #define CTRL_OFFSETW0(x) (((x) & 0x1ff) << 0) |
| #define CTRL_OFFSETW1_MSK (0x1ff << 16) |
| #define CTRL_OFFSETW1(x) (((x) & 0x1ff) << 16) |
| |
| #define DPHY_OFFSETD_CON0 0x105b0050 |
| #define CTRL_RESYNC (0x1 << 24) |
| #define UPD_MODE (0x1 << 28) |
| |
| #define DPHY_CA_DESKEW_CON0 0x105b007c |
| #define DPHY_CA_DESKEW_CON1 0x105b0080 |
| #define DPHY_CA_DESKEW_CON2 0x105b0084 |
| |
| #define DPHY_CAL_WR_PATTERN_CON0 0x105b0098 |
| #define DPHY_CAL_WR_PATTERN_CON1 0x105b009c |
| #define DPHY_CAL_WR_PATTERN_CON2 0x105b00a0 |
| #define DPHY_CAL_WR_PATTERN_CON3 0x105b00a4 |
| #define DPHY_CAL_WR_PATTERN_CON4 0x105b00a8 |
| #define DPHY_CAL_RD_PATTERN_CON0 0x105b00ac |
| |
| #define DPHY_MDLL_CON0 0x105b00b0 |
| #define CTRL_DLL_ON (0x1 << 5) |
| #define CTRL_START (0x1 << 6) |
| #define CAL_VTC_EN (0x1 << 22) |
| #define CLKM_CG_EN_SW (0x1 << 23) |
| |
| #define DPHY_MDLL_CON1 0x105b00b4 |
| #define CTRL_LOCKED (0x1 << 18) |
| #define LOCK_VALUE_INIT_OVERRIDE (0x1 << 21) |
| #define CTRL_LOCK_VALUE_INIT_MSK (0x3ff << 22) |
| #define CTRL_LOCK_VALUE_INIT(x) (((x) & 0x3ff) << 22) |
| |
| #define DPHY_DVFS_CON 0x105b00b8 |
| #define PER_DVFS_TRAIN_DISABLE (0x1 << 13) |
| #define DVFS_CON_MSK (0xfff << 0) |
| #define DVFS_CON(x) (PER_DVFS_TRAIN_DISABLE | (((x) & 0xfff) << 0)) |
| #define DVFS_CON_1866 (DVFS_CON(1866)) |
| #define DVFS_CON_1600 (DVFS_CON(1600)) |
| #define DVFS_CON_1200 (DVFS_CON(1200)) |
| #define DVFS_CON_933 (DVFS_CON(933)) |
| #define DVFS_CON_800 (DVFS_CON(800)) |
| |
| #define DPHY_ZQ_CON0 0x105b03c8 |
| #define ZQ_MANUAL_STR (0x1 << 1) |
| #define ZQ_MANUAL_MODE_MSK (0x3 << 2) |
| #define ZQ_MANUAL_MODE(x) (((x) & 0x3) << 2) |
| #define ZQ_MANUAL_MODE_FORCE 0x0 |
| #define ZQ_MANUAL_MODE_LONG 0x1 |
| #define ZQ_MANUAL_MODE_SHORT 0x2 |
| #define ZQ_CLK_DIV_EN (0x1 << 18) |
| #define ZQ_MODE_NOTERM (0x1 << 19) |
| #define ZQ_RGDDR3 (0x1 << 20) |
| #define ZQ_MODE_TERM_MSK (0x7 << 21) |
| #define ZQ_MODE_TERM(x) (((x) & 0x7) << 21) |
| #define ZQ_MODE_TERM_60_OHM 0x4 |
| #define ZQ_MODE_TERM_120_OHM 0x2 |
| #define ZQ_MODE_TERM_240_OHM 0x1 |
| #define ZQ_CLK_EN (0x1 << 27) |
| #define ZQ_MODE_LP4 (0x1 << 31) |
| |
| #define DPHY_ZQ_CON1 0x105b03cc |
| #define ZQ_DONE (0x1 << 0) |
| |
| #define DPHY_ZQ_CON2 0x105b03d0 |
| #define CTRL_ZQ_CLK_DIV_MSK (0xffff << 0) |
| #define CTRL_ZQ_CLK_DIV(x) (((x) & 0xffff) << 0) |
| |
| #define DPHY_ZQ_CON3 0x105b03d4 |
| #define DPHY_ZQ_CON6 0x105b03e0 |
| #define ZQ_DS0_NOTERM (0x1 << 1) |
| #define ZQ_DS1_NOTERM (0x1 << 9) |
| |
| #define DPHY_ZQ_CON9 0x105b03ec |
| |
| #define DPHY_TESTIRCV_CON0 0x105b0400 |
| #define DQS0_TESTIRCV_MSK (0xf << 0) |
| #define DQS0_TESTIRCV(x) (((x) & 0xf) << 0) |
| #define DQS1_TESTIRCV_MSK (0xf << 4) |
| #define DQS1_TESTIRCV(x) (((x) & 0xf) << 4) |
| |
| #define DPHY_CBT_CON0 0x105b0608 |
| #define CBT_CA_VREF_MODE_DS0 (0x1 << 9) |
| #define CBT_CA_VREF_MODE_DS1 (0x1 << 10) |
| #define CBT_CMD_CLEAR (0x1 << 14) |
| #define CBT_CS_MSK (0x3 << 30) |
| #define CBT_CS(x) (((x) & 0x3) << 30) |
| #define CBT_CS_RANK0 (1) |
| #define CBT_CS_RANK1 (2) |
| |
| #define DPHY_PRBS_CON0 0x105b0684 |
| #define PRBS_DONE (0x1 << 0) |
| #define PRBS_READ_START (0x1 << 1) |
| #define PRBS_WRITE_START (0x1 << 2) |
| #define PRBS_CON0_INIT_PATTERN (0x5 << 16) |
| #define PRBS_CON0_DEFAULT (0x50000) |
| |
| #define DPHY_PRBS_CON1 0x105b0688 |
| #define DPHY_PRBS_CON2 0x105b068c |
| #define DPHY_PRBS_CON3 0x105b0690 |
| #define DPHY_PRBS_CON4 0x105b0694 |
| #define DPHY_PRBS_CON5 0x105b0698 |
| #define DPHY_PRBS_CON6 0x105b069c |
| #define DPHY_PRBS_CON7 0x105b06a0 |
| |
| #define DPHY_PRBS_CON8 0x105b06a4 |
| #define PRBS_DRAM_ACT_ENABLE (0x1 << 31) |
| |
| #define DPHY_MON_CON0 0x105b0700 |
| #define MDLL_MONITOR_EN (0x1 << 15) |
| |
| #define DPHY2_GNR_CON0 0x105c0000 |
| #define DPHY2_CAL_CON0 0x105c0004 |
| #define DPHY2_CAL_CON1 0x105c0008 |
| #define DPHY2_CAL_CON2 0x105c000c |
| #define DPHY2_CAL_CON3 0x105c0010 |
| #define DPHY2_CAL_CON4 0x105c0014 |
| #define DPHY2_LP_CON0 0x105c0018 |
| #define DPHY2_GATE_CON0 0x105c001c |
| #define DPHY2_OFFSETR_CON0 0x105c0020 |
| #define DPHY2_OFFSETW_CON0 0x105c0030 |
| #define DPHY2_OFFSETD_CON0 0x105c0050 |
| #define DPHY2_CA_DESKEW_CON0 0x105c007c |
| #define DPHY2_CA_DESKEW_CON1 0x105c0080 |
| #define DPHY2_CA_DESKEW_CON2 0x105c0084 |
| #define DPHY2_CAL_WR_PATTERN_CON0 0x105c0098 |
| #define DPHY2_CAL_WR_PATTERN_CON1 0x105c009c |
| #define DPHY2_CAL_WR_PATTERN_CON2 0x105c00a0 |
| #define DPHY2_CAL_WR_PATTERN_CON3 0x105c00a4 |
| #define DPHY2_CAL_WR_PATTERN_CON4 0x105c00a8 |
| #define DPHY2_CAL_RD_PATTERN_CON0 0x105c00ac |
| #define DPHY2_MDLL_CON0 0x105c00b0 |
| #define DPHY2_MDLL_CON1 0x105c00b4 |
| #define DPHY2_DVFS_CON 0x105c00b8 |
| #define DPHY2_ZQ_CON0 0x105c03c8 |
| #define DPHY2_ZQ_CON1 0x105c03cc |
| #define DPHY2_ZQ_CON2 0x105c03d0 |
| #define DPHY2_ZQ_CON3 0x105c03d4 |
| #define DPHY2_ZQ_CON6 0x105c03e0 |
| #define DPHY2_ZQ_CON9 0x105c03ec |
| #define DPHY2_TESTIRCV_CON0 0x105c0400 |
| #define DPHY2_CBT_CON0 0x105c0608 |
| #define DPHY2_PRBS_CON0 0x105c0684 |
| #define DPHY2_PRBS_CON1 0x105c0688 |
| #define DPHY2_PRBS_CON2 0x105c068c |
| #define DPHY2_PRBS_CON3 0x105c0690 |
| #define DPHY2_PRBS_CON4 0x105c0694 |
| #define DPHY2_PRBS_CON5 0x105c0698 |
| #define DPHY2_PRBS_CON6 0x105c069c |
| #define DPHY2_PRBS_CON7 0x105c06a0 |
| #define DPHY2_PRBS_CON8 0x105c06a4 |
| #define DPHY2_MON_CON0 0x105c0700 |
| |
| /* DDR training save and restore registers */ |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON_DM 0x105b018c |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON0 0x105b0190 |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON1 0x105b019c |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON2 0x105b01a8 |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON3 0x105b01b4 |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON4 0x105b01c0 |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON5 0x105b01cc |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON6 0x105b01d8 |
| #define DPHY_RD_DESKEW_CENTER_CS0_CON7 0x105b01e4 |
| #define DPHY_WR_DESKEWC_CS0_CON0 0x105b01f0 |
| #define DPHY_WR_DESKEWC_CS0_CON1 0x105b01fc |
| #define DPHY_WR_DESKEWC_CS0_CON2 0x105b0208 |
| #define DPHY_WR_DESKEWC_CS0_CON3 0x105b0214 |
| #define DPHY_WR_DESKEWC_CS0_CON4 0x105b0220 |
| #define DPHY_WR_DESKEWC_CS0_CON5 0x105b022c |
| #define DPHY_WR_DESKEWC_CS0_CON6 0x105b0238 |
| #define DPHY_WR_DESKEWC_CS0_CON7 0x105b0244 |
| #define DPHY_DM_DESKEWC_CS0_CON0 0x105b0250 |
| #define DPHY_WR_DESKEWC_CS1_CON0 0x105b0410 |
| #define DPHY_WR_DESKEWC_CS1_CON1 0x105b041c |
| #define DPHY_WR_DESKEWC_CS1_CON2 0x105b0428 |
| #define DPHY_WR_DESKEWC_CS1_CON3 0x105b0434 |
| #define DPHY_WR_DESKEWC_CS1_CON4 0x105b0440 |
| #define DPHY_WR_DESKEWC_CS1_CON5 0x105b044c |
| #define DPHY_WR_DESKEWC_CS1_CON6 0x105b0458 |
| #define DPHY_WR_DESKEWC_CS1_CON7 0x105b0464 |
| #define DPHY_DM_DESKEWC_CS1_CON0 0x105b0470 |
| #define DPHY_WR_DESKEWL_CS0_CON0 0x105b0490 |
| #define DPHY_WR_DESKEWL_CS0_CON1 0x105b049c |
| #define DPHY_WR_DESKEWL_CS0_CON2 0x105b04a8 |
| #define DPHY_WR_DESKEWL_CS0_CON3 0x105b04b4 |
| #define DPHY_WR_DESKEWL_CS0_CON4 0x105b04c0 |
| #define DPHY_WR_DESKEWL_CS0_CON5 0x105b04cc |
| #define DPHY_WR_DESKEWL_CS0_CON6 0x105b04d8 |
| #define DPHY_WR_DESKEWL_CS0_CON7 0x105b04e4 |
| #define DPHY_DM_DESKEWL_CS0_CON0 0x105b04f0 |
| #define DPHY_WR_DESKEWL_CS1_CON0 0x105b0500 |
| #define DPHY_WR_DESKEWL_CS1_CON1 0x105b050c |
| #define DPHY_WR_DESKEWL_CS1_CON2 0x105b0518 |
| #define DPHY_WR_DESKEWL_CS1_CON3 0x105b0524 |
| #define DPHY_WR_DESKEWL_CS1_CON4 0x105b0530 |
| #define DPHY_WR_DESKEWL_CS1_CON5 0x105b053c |
| #define DPHY_WR_DESKEWL_CS1_CON6 0x105b0548 |
| #define DPHY_WR_DESKEWL_CS1_CON7 0x105b0554 |
| #define DPHY_DM_DESKEWL_CS1_CON0 0x105b0560 |
| #define DPHY_RD_DQS_VWML_CS0_CON0 0x105b0574 |
| #define DPHY_RD_DQS_VWMC_CS0_CON0 0x105b0580 |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON_DM 0x105b0610 |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON0 0x105b0614 |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON1 0x105b0620 |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON2 0x105b062c |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON3 0x105b0638 |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON4 0x105b0644 |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON5 0x105b0650 |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON6 0x105b065c |
| #define DPHY_RD_DESKEW_LEFT_CS0_CON7 0x105b0668 |
| #define DPHY_RD_DQS_VWML_CS1_CON0 0x105b0764 |
| #define DPHY_RD_DQS_VWMC_CS1_CON0 0x105b0768 |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON_DM 0x105b076c |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON0 0x105b0770 |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON1 0x105b0774 |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON2 0x105b0778 |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON3 0x105b077c |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON4 0x105b0780 |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON5 0x105b0784 |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON6 0x105b0788 |
| #define DPHY_RD_DESKEW_CENTER_CS1_CON7 0x105b078c |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON_DM 0x105b0790 |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON0 0x105b0794 |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON1 0x105b0798 |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON2 0x105b079c |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON3 0x105b07a0 |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON4 0x105b07a4 |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON5 0x105b07a8 |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON6 0x105b07ac |
| #define DPHY_RD_DESKEW_LEFT_CS1_CON7 0x105b07b0 |
| #define DPHY_SW_RD_DQS_VWML_CS0_CON0 0x105b07c0 |
| #define DPHY_SW_RD_DQS_VWMC_CS0_CON0 0x105b07c4 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON_DM 0x105b07c8 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON0 0x105b07cc |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON1 0x105b07d0 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON2 0x105b07d4 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON3 0x105b07d8 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON4 0x105b07dc |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON5 0x105b07e0 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON6 0x105b07e4 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS0_CON7 0x105b07e8 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON_DM 0x105b07f0 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON0 0x105b07f4 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON1 0x105b07f8 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON2 0x105b07fc |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON3 0x105b0800 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON4 0x105b0804 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON5 0x105b0808 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON6 0x105b080c |
| #define DPHY_SW_RD_DESKEW_LEFT_CS0_CON7 0x105b0810 |
| #define DPHY_SW_RD_DQS_VWML_CS1_CON0 0x105b0814 |
| #define DPHY_SW_RD_DQS_VWMC_CS1_CON0 0x105b0818 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON_DM 0x105b0820 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON0 0x105b0824 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON1 0x105b0828 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON2 0x105b082c |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON3 0x105b0830 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON4 0x105b0834 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON5 0x105b0838 |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON6 0x105b083c |
| #define DPHY_SW_RD_DESKEW_CENTER_CS1_CON7 0x105b0840 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON_DM 0x105b0850 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON0 0x105b0854 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON1 0x105b0858 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON2 0x105b085c |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON3 0x105b0860 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON4 0x105b0864 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON5 0x105b0868 |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON6 0x105b086c |
| #define DPHY_SW_RD_DESKEW_LEFT_CS1_CON7 0x105b0870 |
| #define DPHY_SW_WR_DESKEWC_CS0_CON0 0x105b0880 |
| #define DPHY_SW_WR_DESKEWC_CS0_CON1 0x105b0884 |
| #define DPHY_SW_WR_DESKEWC_CS0_CON2 0x105b0888 |
| #define DPHY_SW_WR_DESKEWC_CS0_CON3 0x105b088c |
| #define DPHY_SW_WR_DESKEWC_CS0_CON4 0x105b0890 |
| #define DPHY_SW_WR_DESKEWC_CS0_CON5 0x105b0894 |
| #define DPHY_SW_WR_DESKEWC_CS0_CON6 0x105b0898 |
| #define DPHY_SW_WR_DESKEWC_CS0_CON7 0x105b089c |
| #define DPHY_SW_DM_DESKEWC_CS0_CON0 0x105b08a0 |
| #define DPHY_SW_WR_DESKEWL_CS0_CON0 0x105b08b0 |
| #define DPHY_SW_WR_DESKEWL_CS0_CON1 0x105b08b4 |
| #define DPHY_SW_WR_DESKEWL_CS0_CON2 0x105b08b8 |
| #define DPHY_SW_WR_DESKEWL_CS0_CON3 0x105b08bc |
| #define DPHY_SW_WR_DESKEWL_CS0_CON4 0x105b08c0 |
| #define DPHY_SW_WR_DESKEWL_CS0_CON5 0x105b08c4 |
| #define DPHY_SW_WR_DESKEWL_CS0_CON6 0x105b08c8 |
| #define DPHY_SW_WR_DESKEWL_CS0_CON7 0x105b08cc |
| #define DPHY_SW_DM_DESKEWL_CS0_CON0 0x105b08d0 |
| #define DPHY_SW_WR_DESKEWC_CS1_CON0 0x105b08e0 |
| #define DPHY_SW_WR_DESKEWC_CS1_CON1 0x105b08e4 |
| #define DPHY_SW_WR_DESKEWC_CS1_CON2 0x105b08e8 |
| #define DPHY_SW_WR_DESKEWC_CS1_CON3 0x105b08ec |
| #define DPHY_SW_WR_DESKEWC_CS1_CON4 0x105b08f0 |
| #define DPHY_SW_WR_DESKEWC_CS1_CON5 0x105b08f4 |
| #define DPHY_SW_WR_DESKEWC_CS1_CON6 0x105b08f8 |
| #define DPHY_SW_WR_DESKEWC_CS1_CON7 0x105b08fc |
| #define DPHY_SW_DM_DESKEWC_CS1_CON0 0x105b0900 |
| #define DPHY_SW_WR_DESKEWL_CS1_CON0 0x105b0910 |
| #define DPHY_SW_WR_DESKEWL_CS1_CON1 0x105b0914 |
| #define DPHY_SW_WR_DESKEWL_CS1_CON2 0x105b0918 |
| #define DPHY_SW_WR_DESKEWL_CS1_CON3 0x105b091c |
| #define DPHY_SW_WR_DESKEWL_CS1_CON4 0x105b0920 |
| #define DPHY_SW_WR_DESKEWL_CS1_CON5 0x105b0924 |
| #define DPHY_SW_WR_DESKEWL_CS1_CON6 0x105b0928 |
| #define DPHY_SW_WR_DESKEWL_CS1_CON7 0x105b092c |
| #define DPHY_SW_DM_DESKEWL_CS1_CON0 0x105b0930 |
| |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON_DM 0x105c018c |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON0 0x105c0190 |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON1 0x105c019c |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON2 0x105c01a8 |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON3 0x105c01b4 |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON4 0x105c01c0 |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON5 0x105c01cc |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON6 0x105c01d8 |
| #define DPHY2_RD_DESKEW_CENTER_CS0_CON7 0x105c01e4 |
| #define DPHY2_WR_DESKEWC_CS0_CON0 0x105c01f0 |
| #define DPHY2_WR_DESKEWC_CS0_CON1 0x105c01fc |
| #define DPHY2_WR_DESKEWC_CS0_CON2 0x105c0208 |
| #define DPHY2_WR_DESKEWC_CS0_CON3 0x105c0214 |
| #define DPHY2_WR_DESKEWC_CS0_CON4 0x105c0220 |
| #define DPHY2_WR_DESKEWC_CS0_CON5 0x105c022c |
| #define DPHY2_WR_DESKEWC_CS0_CON6 0x105c0238 |
| #define DPHY2_WR_DESKEWC_CS0_CON7 0x105c0244 |
| #define DPHY2_DM_DESKEWC_CS0_CON0 0x105c0250 |
| #define DPHY2_WR_DESKEWC_CS1_CON0 0x105c0410 |
| #define DPHY2_WR_DESKEWC_CS1_CON1 0x105c041c |
| #define DPHY2_WR_DESKEWC_CS1_CON2 0x105c0428 |
| #define DPHY2_WR_DESKEWC_CS1_CON3 0x105c0434 |
| #define DPHY2_WR_DESKEWC_CS1_CON4 0x105c0440 |
| #define DPHY2_WR_DESKEWC_CS1_CON5 0x105c044c |
| #define DPHY2_WR_DESKEWC_CS1_CON6 0x105c0458 |
| #define DPHY2_WR_DESKEWC_CS1_CON7 0x105c0464 |
| #define DPHY2_DM_DESKEWC_CS1_CON0 0x105c0470 |
| #define DPHY2_WR_DESKEWL_CS0_CON0 0x105c0490 |
| #define DPHY2_WR_DESKEWL_CS0_CON1 0x105c049c |
| #define DPHY2_WR_DESKEWL_CS0_CON2 0x105c04a8 |
| #define DPHY2_WR_DESKEWL_CS0_CON3 0x105c04b4 |
| #define DPHY2_WR_DESKEWL_CS0_CON4 0x105c04c0 |
| #define DPHY2_WR_DESKEWL_CS0_CON5 0x105c04cc |
| #define DPHY2_WR_DESKEWL_CS0_CON6 0x105c04d8 |
| #define DPHY2_WR_DESKEWL_CS0_CON7 0x105c04e4 |
| #define DPHY2_DM_DESKEWL_CS0_CON0 0x105c04f0 |
| #define DPHY2_WR_DESKEWL_CS1_CON0 0x105c0500 |
| #define DPHY2_WR_DESKEWL_CS1_CON1 0x105c050c |
| #define DPHY2_WR_DESKEWL_CS1_CON2 0x105c0518 |
| #define DPHY2_WR_DESKEWL_CS1_CON3 0x105c0524 |
| #define DPHY2_WR_DESKEWL_CS1_CON4 0x105c0530 |
| #define DPHY2_WR_DESKEWL_CS1_CON5 0x105c053c |
| #define DPHY2_WR_DESKEWL_CS1_CON6 0x105c0548 |
| #define DPHY2_WR_DESKEWL_CS1_CON7 0x105c0554 |
| #define DPHY2_DM_DESKEWL_CS1_CON0 0x105c0560 |
| #define DPHY2_RD_DQS_VWML_CS0_CON0 0x105c0574 |
| #define DPHY2_RD_DQS_VWMC_CS0_CON0 0x105c0580 |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON_DM 0x105c0610 |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON0 0x105c0614 |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON1 0x105c0620 |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON2 0x105c062c |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON3 0x105c0638 |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON4 0x105c0644 |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON5 0x105c0650 |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON6 0x105c065c |
| #define DPHY2_RD_DESKEW_LEFT_CS0_CON7 0x105c0668 |
| #define DPHY2_RD_DQS_VWML_CS1_CON0 0x105c0764 |
| #define DPHY2_RD_DQS_VWMC_CS1_CON0 0x105c0768 |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON_DM 0x105c076c |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON0 0x105c0770 |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON1 0x105c0774 |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON2 0x105c0778 |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON3 0x105c077c |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON4 0x105c0780 |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON5 0x105c0784 |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON6 0x105c0788 |
| #define DPHY2_RD_DESKEW_CENTER_CS1_CON7 0x105c078c |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON_DM 0x105c0790 |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON0 0x105c0794 |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON1 0x105c0798 |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON2 0x105c079c |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON3 0x105c07a0 |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON4 0x105c07a4 |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON5 0x105c07a8 |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON6 0x105c07ac |
| #define DPHY2_RD_DESKEW_LEFT_CS1_CON7 0x105c07b0 |
| #define DPHY2_SW_RD_DQS_VWML_CS0_CON0 0x105c07c0 |
| #define DPHY2_SW_RD_DQS_VWMC_CS0_CON0 0x105c07c4 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON_DM 0x105c07c8 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON0 0x105c07cc |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON1 0x105c07d0 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON2 0x105c07d4 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON3 0x105c07d8 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON4 0x105c07dc |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON5 0x105c07e0 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON6 0x105c07e4 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS0_CON7 0x105c07e8 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON_DM 0x105c07f0 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON0 0x105c07f4 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON1 0x105c07f8 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON2 0x105c07fc |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON3 0x105c0800 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON4 0x105c0804 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON5 0x105c0808 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON6 0x105c080c |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS0_CON7 0x105c0810 |
| #define DPHY2_SW_RD_DQS_VWML_CS1_CON0 0x105c0814 |
| #define DPHY2_SW_RD_DQS_VWMC_CS1_CON0 0x105c0818 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON_DM 0x105c0820 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON0 0x105c0824 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON1 0x105c0828 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON2 0x105c082c |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON3 0x105c0830 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON4 0x105c0834 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON5 0x105c0838 |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON6 0x105c083c |
| #define DPHY2_SW_RD_DESKEW_CENTER_CS1_CON7 0x105c0840 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON_DM 0x105c0850 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON0 0x105c0854 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON1 0x105c0858 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON2 0x105c085c |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON3 0x105c0860 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON4 0x105c0864 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON5 0x105c0868 |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON6 0x105c086c |
| #define DPHY2_SW_RD_DESKEW_LEFT_CS1_CON7 0x105c0870 |
| #define DPHY2_SW_WR_DESKEWC_CS0_CON0 0x105c0880 |
| #define DPHY2_SW_WR_DESKEWC_CS0_CON1 0x105c0884 |
| #define DPHY2_SW_WR_DESKEWC_CS0_CON2 0x105c0888 |
| #define DPHY2_SW_WR_DESKEWC_CS0_CON3 0x105c088c |
| #define DPHY2_SW_WR_DESKEWC_CS0_CON4 0x105c0890 |
| #define DPHY2_SW_WR_DESKEWC_CS0_CON5 0x105c0894 |
| #define DPHY2_SW_WR_DESKEWC_CS0_CON6 0x105c0898 |
| #define DPHY2_SW_WR_DESKEWC_CS0_CON7 0x105c089c |
| #define DPHY2_SW_DM_DESKEWC_CS0_CON0 0x105c08a0 |
| #define DPHY2_SW_WR_DESKEWL_CS0_CON0 0x105c08b0 |
| #define DPHY2_SW_WR_DESKEWL_CS0_CON1 0x105c08b4 |
| #define DPHY2_SW_WR_DESKEWL_CS0_CON2 0x105c08b8 |
| #define DPHY2_SW_WR_DESKEWL_CS0_CON3 0x105c08bc |
| #define DPHY2_SW_WR_DESKEWL_CS0_CON4 0x105c08c0 |
| #define DPHY2_SW_WR_DESKEWL_CS0_CON5 0x105c08c4 |
| #define DPHY2_SW_WR_DESKEWL_CS0_CON6 0x105c08c8 |
| #define DPHY2_SW_WR_DESKEWL_CS0_CON7 0x105c08cc |
| #define DPHY2_SW_DM_DESKEWL_CS0_CON0 0x105c08d0 |
| #define DPHY2_SW_WR_DESKEWC_CS1_CON0 0x105c08e0 |
| #define DPHY2_SW_WR_DESKEWC_CS1_CON1 0x105c08e4 |
| #define DPHY2_SW_WR_DESKEWC_CS1_CON2 0x105c08e8 |
| #define DPHY2_SW_WR_DESKEWC_CS1_CON3 0x105c08ec |
| #define DPHY2_SW_WR_DESKEWC_CS1_CON4 0x105c08f0 |
| #define DPHY2_SW_WR_DESKEWC_CS1_CON5 0x105c08f4 |
| #define DPHY2_SW_WR_DESKEWC_CS1_CON6 0x105c08f8 |
| #define DPHY2_SW_WR_DESKEWC_CS1_CON7 0x105c08fc |
| #define DPHY2_SW_DM_DESKEWC_CS1_CON0 0x105c0900 |
| #define DPHY2_SW_WR_DESKEWL_CS1_CON0 0x105c0910 |
| #define DPHY2_SW_WR_DESKEWL_CS1_CON1 0x105c0914 |
| #define DPHY2_SW_WR_DESKEWL_CS1_CON2 0x105c0918 |
| #define DPHY2_SW_WR_DESKEWL_CS1_CON3 0x105c091c |
| #define DPHY2_SW_WR_DESKEWL_CS1_CON4 0x105c0920 |
| #define DPHY2_SW_WR_DESKEWL_CS1_CON5 0x105c0924 |
| #define DPHY2_SW_WR_DESKEWL_CS1_CON6 0x105c0928 |
| #define DPHY2_SW_WR_DESKEWL_CS1_CON7 0x105c092c |
| #define DPHY2_SW_DM_DESKEWL_CS1_CON0 0x105c0930 |
| |
| /* Register offsets used during PRBS training */ |
| #define DPHY_OFFSET_PRBS_CON6 0x69c |
| #define DPHY_OFFSET_PRBS_CON7 0x6a0 |
| |
| #define PATTERN_55AA55AA 0x55aa55aa |
| #define PATTERN_AA55AA55 0xaa55aa55 |
| #define PATTERN_5555 0x5555 |
| |
| #define pll_locktime_pll_aon 0x10b10000 |
| #define pll_con0_pll_aon 0x10b10100 |
| #define clk_con_div_div4_pllclk 0x10b11800 |
| #define clk_con_div_div_otp 0x10b11804 |
| #define clk_con_div_div_tmu 0x10b11808 |
| #define clk_con_div_pll_aon_clk 0x10b1180c |
| #define clk_con_div_shared_div_aon_pll 0x10b11810 |
| #define clk_con_div_shared_div_mif 0x10b11814 |
| |
| #define POLL_TIMEOUT_USEC 10000 |
| #define DDR_POLL_USLEEP_MIN 100 |
| #define DDR_CLK_IN_SENSE_TIMEOUT 5000 |
| #define DDR_AXI_BLOCK_TIMEOUT 5000 |
| /* Minimum RESET_n LOW time after completion of voltage ramp */ |
| #define DDR_INIT_TIMING_tINIT1_USEC 400 |
| /* Minimum CKE low time after RESET_n high */ |
| #define DDR_INIT_TIMING_tINIT3_USEC 2000 |
| /* CKE High to CS delay */ |
| #define DDR_INIT_CKE2CS_DELAY_USEC 100 |
| #define DDR_DLL_CTRL_OFF_ON_UDELAY 10 |
| |
| #define ddr_usleep(usec) (usleep_range(usec, usec + 1)) |
| |
| #define VREF_REF_NUM 0x05 |
| #define PHY_VREF_LEVELS 64 |
| #define DRAM_VREF_LEVELS 81 |
| #define VREF_FROM 0x0 |
| #define VREF_STEP 0x1 |
| #define VREF_PRBS_TIMEOUT_USEC 10000 |
| |
| #define MAX_RW_OFFSETS (512) |
| #define MR_READ_DELAY_USEC (100) |
| #define DDR_HW_P_W_TRAIN_INTERVAL_MSEC (32) |
| |
| /* These macros are used to control refresh control setting during self-refresh |
| * entry and exit. |
| */ |
| #define REF_CTRL_DISABLE (0) |
| #define REF_CTRL_ENABLE (1) |
| |
| /* |
| * Polling interval for refresh rate control; |
| * may be decreased pending HW data. |
| */ |
| #define DDR_REFCTRL_POLL_TIME_MSEC (512) |
| |
| enum ddr_freq_index { |
| f_DPHY_DVFS_CON, |
| f_DPHY_CAL_CON2, |
| f_DPHY_GNR_CON0, |
| f_DREX_TIMINGRFCPB, |
| f_DREX_TIMINGROW, |
| f_DREX_TIMINGDATA, |
| f_DREX_TIMINGPOWER, |
| f_reg_max |
| }; |
| |
| enum ddr_poll_index { |
| p_pll_con0_pll_phy_mif, |
| p_DPHY_ZQ_CON1, |
| p_DPHY_MDLL_CON1, |
| p_DREX_PHYSTATUS_dfi, |
| p_DREX_PHYSTATUS_train, |
| p_DREX_CHIPSTATUS_sr_enter, |
| p_DREX_CHIPSTATUS_sr_exit, |
| p_DPHY_PRBS_CON0_prbs_done, |
| p_DPHY_PRBS_CON0_prbs_disable, |
| }; |
| |
| enum ddr_train_save_index { |
| s_DPHY_MDLL_CON1, |
| s_DPHY2_MDLL_CON1, |
| s_DPHY_CA_DESKEW_CON0, |
| s_DPHY_CA_DESKEW_CON1, |
| s_DPHY_CA_DESKEW_CON2, |
| s_DPHY2_CA_DESKEW_CON0, |
| s_DPHY2_CA_DESKEW_CON1, |
| s_DPHY2_CA_DESKEW_CON2, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON_DM, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON0, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON1, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON2, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON3, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON4, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON5, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON6, |
| s_DPHY_RD_DESKEW_CENTER_CS0_CON7, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON_DM, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON0, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON1, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON2, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON3, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON4, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON5, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON6, |
| s_DPHY_RD_DESKEW_CENTER_CS1_CON7, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON_DM, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON0, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON1, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON2, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON3, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON4, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON5, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON6, |
| s_DPHY_RD_DESKEW_LEFT_CS0_CON7, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON_DM, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON0, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON1, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON2, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON3, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON4, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON5, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON6, |
| s_DPHY_RD_DESKEW_LEFT_CS1_CON7, |
| s_DPHY_RD_DQS_VWMC_CS0_CON0, |
| s_DPHY_RD_DQS_VWMC_CS1_CON0, |
| s_DPHY_RD_DQS_VWML_CS0_CON0, |
| s_DPHY_RD_DQS_VWML_CS1_CON0, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON_DM, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON0, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON1, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON2, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON3, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON4, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON5, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON6, |
| s_DPHY2_RD_DESKEW_CENTER_CS0_CON7, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON_DM, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON0, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON1, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON2, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON3, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON4, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON5, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON6, |
| s_DPHY2_RD_DESKEW_CENTER_CS1_CON7, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON_DM, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON0, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON1, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON2, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON3, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON4, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON5, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON6, |
| s_DPHY2_RD_DESKEW_LEFT_CS0_CON7, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON_DM, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON0, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON1, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON2, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON3, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON4, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON5, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON6, |
| s_DPHY2_RD_DESKEW_LEFT_CS1_CON7, |
| s_DPHY2_RD_DQS_VWMC_CS0_CON0, |
| s_DPHY2_RD_DQS_VWMC_CS1_CON0, |
| s_DPHY2_RD_DQS_VWML_CS0_CON0, |
| s_DPHY2_RD_DQS_VWML_CS1_CON0, |
| s_DPHY_WR_DESKEWC_CS0_CON0, |
| s_DPHY_WR_DESKEWC_CS0_CON1, |
| s_DPHY_WR_DESKEWC_CS0_CON2, |
| s_DPHY_WR_DESKEWC_CS0_CON3, |
| s_DPHY_WR_DESKEWC_CS0_CON4, |
| s_DPHY_WR_DESKEWC_CS0_CON5, |
| s_DPHY_WR_DESKEWC_CS0_CON6, |
| s_DPHY_WR_DESKEWC_CS0_CON7, |
| s_DPHY_DM_DESKEWC_CS0_CON0, |
| s_DPHY_WR_DESKEWC_CS1_CON0, |
| s_DPHY_WR_DESKEWC_CS1_CON1, |
| s_DPHY_WR_DESKEWC_CS1_CON2, |
| s_DPHY_WR_DESKEWC_CS1_CON3, |
| s_DPHY_WR_DESKEWC_CS1_CON4, |
| s_DPHY_WR_DESKEWC_CS1_CON5, |
| s_DPHY_WR_DESKEWC_CS1_CON6, |
| s_DPHY_WR_DESKEWC_CS1_CON7, |
| s_DPHY_DM_DESKEWC_CS1_CON0, |
| s_DPHY_WR_DESKEWL_CS0_CON0, |
| s_DPHY_WR_DESKEWL_CS0_CON1, |
| s_DPHY_WR_DESKEWL_CS0_CON2, |
| s_DPHY_WR_DESKEWL_CS0_CON3, |
| s_DPHY_WR_DESKEWL_CS0_CON4, |
| s_DPHY_WR_DESKEWL_CS0_CON5, |
| s_DPHY_WR_DESKEWL_CS0_CON6, |
| s_DPHY_WR_DESKEWL_CS0_CON7, |
| s_DPHY_DM_DESKEWL_CS0_CON0, |
| s_DPHY_WR_DESKEWL_CS1_CON0, |
| s_DPHY_WR_DESKEWL_CS1_CON1, |
| s_DPHY_WR_DESKEWL_CS1_CON2, |
| s_DPHY_WR_DESKEWL_CS1_CON3, |
| s_DPHY_WR_DESKEWL_CS1_CON4, |
| s_DPHY_WR_DESKEWL_CS1_CON5, |
| s_DPHY_WR_DESKEWL_CS1_CON6, |
| s_DPHY_WR_DESKEWL_CS1_CON7, |
| s_DPHY_DM_DESKEWL_CS1_CON0, |
| s_DPHY2_WR_DESKEWC_CS0_CON0, |
| s_DPHY2_WR_DESKEWC_CS0_CON1, |
| s_DPHY2_WR_DESKEWC_CS0_CON2, |
| s_DPHY2_WR_DESKEWC_CS0_CON3, |
| s_DPHY2_WR_DESKEWC_CS0_CON4, |
| s_DPHY2_WR_DESKEWC_CS0_CON5, |
| s_DPHY2_WR_DESKEWC_CS0_CON6, |
| s_DPHY2_WR_DESKEWC_CS0_CON7, |
| s_DPHY2_DM_DESKEWC_CS0_CON0, |
| s_DPHY2_WR_DESKEWC_CS1_CON0, |
| s_DPHY2_WR_DESKEWC_CS1_CON1, |
| s_DPHY2_WR_DESKEWC_CS1_CON2, |
| s_DPHY2_WR_DESKEWC_CS1_CON3, |
| s_DPHY2_WR_DESKEWC_CS1_CON4, |
| s_DPHY2_WR_DESKEWC_CS1_CON5, |
| s_DPHY2_WR_DESKEWC_CS1_CON6, |
| s_DPHY2_WR_DESKEWC_CS1_CON7, |
| s_DPHY2_DM_DESKEWC_CS1_CON0, |
| s_DPHY2_WR_DESKEWL_CS0_CON0, |
| s_DPHY2_WR_DESKEWL_CS0_CON1, |
| s_DPHY2_WR_DESKEWL_CS0_CON2, |
| s_DPHY2_WR_DESKEWL_CS0_CON3, |
| s_DPHY2_WR_DESKEWL_CS0_CON4, |
| s_DPHY2_WR_DESKEWL_CS0_CON5, |
| s_DPHY2_WR_DESKEWL_CS0_CON6, |
| s_DPHY2_WR_DESKEWL_CS0_CON7, |
| s_DPHY2_DM_DESKEWL_CS0_CON0, |
| s_DPHY2_WR_DESKEWL_CS1_CON0, |
| s_DPHY2_WR_DESKEWL_CS1_CON1, |
| s_DPHY2_WR_DESKEWL_CS1_CON2, |
| s_DPHY2_WR_DESKEWL_CS1_CON3, |
| s_DPHY2_WR_DESKEWL_CS1_CON4, |
| s_DPHY2_WR_DESKEWL_CS1_CON5, |
| s_DPHY2_WR_DESKEWL_CS1_CON6, |
| s_DPHY2_WR_DESKEWL_CS1_CON7, |
| s_DPHY2_DM_DESKEWL_CS1_CON0, |
| s_DPHY_PRBS_CON2, |
| s_DPHY_PRBS_CON3, |
| s_DPHY2_PRBS_CON2, |
| s_DPHY2_PRBS_CON3, |
| s_DPHY_ZQ_CON9, |
| s_DPHY2_ZQ_CON9, |
| s_train_max_index, |
| }; |
| |
| enum ddr_freq_t { |
| AB_DRAM_FREQ_MHZ_1866, |
| AB_DRAM_FREQ_MHZ_1600, |
| AB_DRAM_FREQ_MHZ_1200, |
| AB_DRAM_FREQ_MHZ_933, |
| AB_DRAM_FREQ_MHZ_800, |
| AB_DRAM_FREQ_MAX |
| }; |
| |
| /* returns true for all frequencies less than or equal to 933Mhz */ |
| #define is_low_freq(x) ((x >= AB_DRAM_FREQ_MHZ_933) ? 1 : 0) |
| |
| enum ddr_restore_mode_t { |
| AB_RESTORE_FULL, |
| AB_RESTORE_DVFS, |
| }; |
| |
| enum ddr_ref_rate_t { |
| RR_LT = 0, |
| RR_4x, |
| RR_2x, |
| RR_1x, |
| RR_0_5x, |
| RR_0_25x, |
| RR_0_25xd, |
| RR_HT, |
| RR_MAX |
| }; |
| |
| enum vref_operation_t { |
| VREF_READ = 0, |
| VREF_WRITE |
| }; |
| |
| enum vref_byte_t { |
| VREF_BYTE0 = 0, |
| VREF_BYTE1, |
| VREF_BYTE_ALL |
| }; |
| |
| enum vref_error_t { |
| VREF_ERROR = DDR_FAIL, |
| VREF_SUCCESS = DDR_SUCCESS, |
| VREF_TIMEOUT |
| }; |
| |
| enum vref_prbs_t { |
| VREF_PRBS_SUCCESS = 0, |
| VREF_PRBS_TIMEOUT |
| }; |
| |
| enum phy_type_t { |
| PHY0 = 0, |
| PHY1 |
| }; |
| |
| /* Little Endian representation of the register fields */ |
| union dphy_cal_con0_t { |
| uint32_t n; |
| struct { |
| uint32_t wrlvl_mode : (0 - 0 + 1); |
| uint32_t gate_cal_mode : (1 - 1 + 1); |
| uint32_t ca_cal_mode : (2 - 2 + 1); |
| uint32_t rd_cal_mode : (3 - 3 + 1); |
| uint32_t lock_average_en : (4 - 4 + 1); |
| uint32_t wr_cal_mode : (5 - 5 + 1); |
| uint32_t rdlvl_dqs_edge_en : (7 - 6 + 1); |
| uint32_t wrlvl_start : (8 - 8 + 1); |
| uint32_t wrtrn_dqs_edge_en : (10 - 9 + 1); |
| uint32_t lock_sample_condition : (12 - 11 + 1); |
| uint32_t ctrl_upd_interval : (14 - 13 + 1); |
| uint32_t reserved_15_15 : (15 - 15 + 1); |
| uint32_t wrlvl_resp : (16 - 16 + 1); |
| uint32_t reserved_17_17 : (17 - 17 + 1); |
| uint32_t wr_per_rank_en : (19 - 18 + 1); |
| uint32_t byte_rdlvl_en : (20 - 20 + 1); |
| uint32_t ca_swap_mode : (21 - 21 + 1); |
| uint32_t cal_vtc_en : (22 - 22 + 1); |
| uint32_t freq_offset_en : (23 - 23 + 1); |
| uint32_t avg_window_size : (25 - 24 + 1); |
| uint32_t dvfs_wr_train_en : (26 - 26 + 1); |
| uint32_t gate_rdchk_en : (27 - 27 + 1); |
| uint32_t cs_default : (31 - 28 + 1); |
| } bits; |
| }; |
| |
| union dphy_zq_con9_t { |
| uint32_t n; |
| struct { |
| uint32_t zq_ds0_vref : (5 - 0 + 1); |
| uint32_t zq_ds0_vref_fsbst : (6 - 6 + 1); |
| uint32_t zq_ds0_vref_pd : (7 - 7 + 1); |
| uint32_t zq_ds1_vref : (13 - 8 + 1); |
| uint32_t zq_ds1_vref_fsbst : (14 - 14 + 1); |
| uint32_t zq_ds1_vref_pd : (15 - 15 + 1); |
| uint32_t reserved_16_31 : (31 - 16 + 1); |
| } bits; |
| }; |
| |
| union dphy_prbs_con0_t { |
| uint32_t n; |
| struct { |
| uint32_t prbs_done : (0 - 0 + 1); |
| uint32_t prbs_read_start : (1 - 1 + 1); |
| uint32_t prbs_write_start : (2 - 2 + 1); |
| uint32_t reserved_3_15 : (15 - 3 + 1); |
| uint32_t prbs_pattern : (31 - 16 + 1); |
| } bits; |
| }; |
| |
| union dphy_prbs_con1_t { |
| uint32_t n; |
| struct { |
| uint32_t prbs_tresync : (4 - 0 + 1); |
| uint32_t prbs_trddata_en_adj : (8 - 5 + 1); |
| uint32_t reserved_9_12 : (12 - 9 + 1); |
| uint32_t prbs_twr2rd : (17 - 13 + 1); |
| uint32_t prbs_wrlat : (23 - 18 + 1); |
| uint32_t reserved_24_25 : (25 - 24 + 1); |
| uint32_t prbs_dbi_en : (26 - 26 + 1); |
| uint32_t reserved_27_27 : (27 - 27 + 1); |
| uint32_t prbs_cs : (31 - 28 + 1); |
| } bits; |
| }; |
| |
| union dphy_prbs_con6_t { |
| uint32_t n; |
| struct { |
| uint32_t prbs_offset_left0 : (8 - 0 + 1); |
| uint32_t reserved_9_15 : (15 - 9 + 1); |
| uint32_t prbs_offset_left1 : (24 - 16 + 1); |
| uint32_t reserved_31_25 : (31 - 25 + 1); |
| } bits; |
| }; |
| |
| union dphy_prbs_con7_t { |
| uint32_t n; |
| struct { |
| uint32_t prbs_offset_right0 : (8 - 0 + 1); |
| uint32_t reserved_9_15 : (15 - 9 + 1); |
| uint32_t prbs_offset_right1 : (24 - 16 + 1); |
| uint32_t reserved_31_25 : (31 - 25 + 1); |
| } bits; |
| }; |
| |
| struct airbrush_ddr_pll_t { |
| unsigned int p; |
| unsigned int m; |
| unsigned int s; |
| }; |
| |
| struct airbrush_ddr_mrw_set_t { |
| unsigned int mr1; |
| unsigned int mr2; |
| unsigned int mr3; |
| unsigned int mr11; |
| unsigned int mr13; |
| unsigned int mr22; |
| unsigned int mr8; |
| }; |
| |
| struct ddr_refresh_info_t { |
| unsigned int t_refi; |
| unsigned int t_refipb; |
| }; |
| |
| struct ddr_reg_poll_t { |
| uint32_t mask; |
| uint32_t val; |
| uint32_t usec_timeout; |
| }; |
| |
| struct ddr_train_save_restore_t { |
| uint32_t reg_save; |
| uint32_t reg_restore; |
| }; |
| |
| struct ddr_ppc_overflow_info { |
| uint32_t overflow_count_cycle_cnt; |
| uint32_t overflow_count_cnt[PPC_COUNTER_MAX]; |
| }; |
| |
| struct ddr_eyemargin_data { |
| /* time taken by memtester for r/w eyemargin test at each offset */ |
| ktime_t read_eye_time[PHY_VREF_LEVELS][MAX_RW_OFFSETS]; |
| ktime_t write_eye_time[DRAM_VREF_LEVELS][MAX_RW_OFFSETS]; |
| |
| /* memtester result for r/w eyemargin test for each offset */ |
| char read_eye[PHY_VREF_LEVELS][MAX_RW_OFFSETS]; |
| char write_eye[DRAM_VREF_LEVELS][MAX_RW_OFFSETS]; |
| |
| /* Number of offset samples used to plot eyemargin diagram */ |
| unsigned int num_samples_read; |
| unsigned int num_samples_write; |
| }; |
| |
| struct ab_ddr_context { |
| struct device *dev; |
| unsigned int is_setup_done; |
| |
| struct mutex ddr_lock; |
| |
| struct ab_state_context *ab_state_ctx; |
| enum ddr_state ddr_state; /* keeps track of current ddr state */ |
| enum ddr_state prev_ddr_state; /* keeps track of previous ddr state */ |
| |
| enum ddr_freq_t cur_freq; /* current frequency */ |
| |
| /* Array to store ddr train results for various frequencies. */ |
| unsigned int ddr_train_save_value[AB_DRAM_FREQ_MAX][s_train_max_index]; |
| |
| /* Flag to indicate whether the training results for a given frequency |
| * is valid or not. |
| */ |
| unsigned int ddr_train_completed[AB_DRAM_FREQ_MAX]; |
| |
| /* When M0 performs the ddr initialization and training, training |
| * results are stored in SRAM. During ddr_setup() read this address |
| * information and update here. |
| */ |
| unsigned int ddr_train_sram_location; |
| |
| uint32_t drex_memcontrol_cache; |
| uint32_t drex_cgcontrol_cache; |
| uint32_t drex_dfirstcontrol_cache; |
| uint32_t drex_concontrol_cache; |
| uint32_t mif_pll_wrap_ctrl_reg_cache; |
| uint32_t pll_con0_pll_phy_mif_cache; |
| uint32_t dphy_lp_con0_cache; |
| uint32_t dphy2_lp_con0_cache; |
| uint32_t dphy_gate_con0_cache; |
| uint32_t dphy2_gate_con0_cache; |
| uint32_t dphy_mdll_con0_cache; |
| uint32_t dphy2_mdll_con0_cache; |
| uint32_t drex_activate_axi_ready_cache; |
| |
| int32_t poll_multiplier; |
| |
| /* ddr refresh rate control work queue */ |
| struct delayed_work ddr_ref_control_work; |
| struct ddr_refresh_info_t ref_info; |
| unsigned int ref_rate; |
| |
| /* pcie link notifier registration */ |
| bool pcie_link_ready; /* Guarded by ddr_lock */ |
| struct notifier_block pcie_link_blocking_nb; |
| |
| #ifdef CONFIG_AB_DDR_RW_TEST |
| /* read/write test data */ |
| ktime_t st_read, et_read; |
| ktime_t st_write, et_write; |
| #endif |
| |
| #ifdef CONFIG_AB_DDR_EYE_MARGIN |
| struct ddr_eyemargin_data *eye_data; |
| #endif |
| |
| #ifdef CONFIG_AB_DDR_PPC |
| int ddr_ppc_events[PPC_COUNTER_MAX]; |
| struct ddr_ppc_overflow_info ddr_ppc_info; |
| #endif |
| }; |
| |
| static inline uint32_t ddr_reg_rd(struct ab_ddr_context *ddr_ctx, |
| uint32_t addr) |
| { |
| uint32_t data = 0xffffffff; |
| int ret; |
| |
| ret = abc_pcie_config_read(addr & 0xFFFFFF, 0x4, &data); |
| WARN_ON(ret); |
| |
| if (ret) |
| return data; |
| |
| switch (addr) { |
| case DREX_MEMCONTROL: |
| ddr_ctx->drex_memcontrol_cache = data; |
| break; |
| case DREX_CGCONTROL: |
| ddr_ctx->drex_cgcontrol_cache = data; |
| break; |
| case DREX_DFIRSTCONTROL: |
| ddr_ctx->drex_dfirstcontrol_cache = data; |
| break; |
| case DREX_CONCONTROL: |
| ddr_ctx->drex_concontrol_cache = data; |
| break; |
| case MIF_PLL_WRAP_CTRL_REG: |
| ddr_ctx->mif_pll_wrap_ctrl_reg_cache = data; |
| break; |
| case PLL_CON0_PLL_PHY_MIF: |
| ddr_ctx->pll_con0_pll_phy_mif_cache = data; |
| break; |
| case DPHY_LP_CON0: |
| ddr_ctx->dphy_lp_con0_cache = data; |
| break; |
| case DPHY2_LP_CON0: |
| ddr_ctx->dphy2_lp_con0_cache = data; |
| break; |
| case DPHY_GATE_CON0: |
| ddr_ctx->dphy_gate_con0_cache = data; |
| break; |
| case DPHY2_GATE_CON0: |
| ddr_ctx->dphy2_gate_con0_cache = data; |
| break; |
| case DPHY_MDLL_CON0: |
| ddr_ctx->dphy_mdll_con0_cache = data; |
| break; |
| case DPHY2_MDLL_CON0: |
| ddr_ctx->dphy2_mdll_con0_cache = data; |
| break; |
| case DREX_ACTIVATE_AXI_READY: |
| ddr_ctx->drex_activate_axi_ready_cache = data; |
| break; |
| default: |
| break; |
| } |
| |
| return data; |
| } |
| |
| static inline void ab_ddr_clear_cache(struct ab_ddr_context *ddr_ctx) |
| { |
| ddr_ctx->drex_memcontrol_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->drex_cgcontrol_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->drex_dfirstcontrol_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->drex_concontrol_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->mif_pll_wrap_ctrl_reg_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->pll_con0_pll_phy_mif_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->dphy_lp_con0_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->dphy2_lp_con0_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->dphy_gate_con0_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->dphy2_gate_con0_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->dphy_mdll_con0_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->dphy2_mdll_con0_cache = AB_DDR_CACHE_UNKNOWN; |
| ddr_ctx->drex_activate_axi_ready_cache = AB_DDR_CACHE_UNKNOWN; |
| } |
| |
| static inline uint32_t ddr_reg_rd_cache(struct ab_ddr_context *ddr_ctx, |
| uint32_t addr) |
| { |
| uint32_t *cache = 0; |
| uint32_t def_val = AB_DDR_CACHE_UNKNOWN; |
| |
| switch (addr) { |
| case DREX_MEMCONTROL: |
| cache = &ddr_ctx->drex_memcontrol_cache; |
| break; |
| case DREX_CGCONTROL: |
| cache = &ddr_ctx->drex_cgcontrol_cache; |
| break; |
| case DREX_DFIRSTCONTROL: |
| cache = &ddr_ctx->drex_dfirstcontrol_cache; |
| break; |
| case DREX_CONCONTROL: |
| cache = &ddr_ctx->drex_concontrol_cache; |
| break; |
| case MIF_PLL_WRAP_CTRL_REG: |
| cache = &ddr_ctx->mif_pll_wrap_ctrl_reg_cache; |
| break; |
| case PLL_CON0_PLL_PHY_MIF: |
| cache = &ddr_ctx->pll_con0_pll_phy_mif_cache; |
| break; |
| case DPHY_LP_CON0: |
| cache = &ddr_ctx->dphy_lp_con0_cache; |
| break; |
| case DPHY2_LP_CON0: |
| cache = &ddr_ctx->dphy2_lp_con0_cache; |
| break; |
| case DPHY_GATE_CON0: |
| cache = &ddr_ctx->dphy_gate_con0_cache; |
| break; |
| case DPHY2_GATE_CON0: |
| cache = &ddr_ctx->dphy2_gate_con0_cache; |
| break; |
| case DPHY_MDLL_CON0: |
| cache = &ddr_ctx->dphy_mdll_con0_cache; |
| break; |
| case DPHY2_MDLL_CON0: |
| cache = &ddr_ctx->dphy2_mdll_con0_cache; |
| break; |
| case DREX_ACTIVATE_AXI_READY: |
| cache = &ddr_ctx->drex_activate_axi_ready_cache; |
| break; |
| default: |
| cache = &def_val; |
| break; |
| } |
| |
| if (*cache == AB_DDR_CACHE_UNKNOWN) |
| WARN_ON(abc_pcie_config_read(addr & 0xFFFFFF, 0x4, cache)); |
| |
| return *cache; |
| } |
| |
| static inline void ddr_reg_wr(struct ab_ddr_context *ddr_ctx, |
| uint32_t addr, uint32_t data) |
| { |
| int ret; |
| |
| ret = abc_pcie_config_write(addr & 0xFFFFFF, 0x4, data); |
| WARN_ON(ret); |
| |
| if (ret) |
| return; |
| |
| switch (addr) { |
| case DREX_MEMCONTROL: |
| ddr_ctx->drex_memcontrol_cache = data; |
| break; |
| case DREX_CGCONTROL: |
| ddr_ctx->drex_cgcontrol_cache = data; |
| break; |
| case DREX_DFIRSTCONTROL: |
| ddr_ctx->drex_dfirstcontrol_cache = data; |
| break; |
| case DREX_CONCONTROL: |
| ddr_ctx->drex_concontrol_cache = data; |
| break; |
| case MIF_PLL_WRAP_CTRL_REG: |
| ddr_ctx->mif_pll_wrap_ctrl_reg_cache = data; |
| break; |
| case PLL_CON0_PLL_PHY_MIF: |
| ddr_ctx->pll_con0_pll_phy_mif_cache = data; |
| break; |
| case DPHY_LP_CON0: |
| ddr_ctx->dphy_lp_con0_cache = data; |
| break; |
| case DPHY2_LP_CON0: |
| ddr_ctx->dphy2_lp_con0_cache = data; |
| break; |
| case DPHY_GATE_CON0: |
| ddr_ctx->dphy_gate_con0_cache = data; |
| break; |
| case DPHY2_GATE_CON0: |
| ddr_ctx->dphy2_gate_con0_cache = data; |
| break; |
| case DPHY_MDLL_CON0: |
| ddr_ctx->dphy_mdll_con0_cache = data; |
| break; |
| case DPHY2_MDLL_CON0: |
| ddr_ctx->dphy2_mdll_con0_cache = data; |
| break; |
| case DREX_ACTIVATE_AXI_READY: |
| ddr_ctx->drex_activate_axi_ready_cache = data; |
| break; |
| default: |
| break; |
| } |
| } |
| |
| static inline void ddr_reg_set(struct ab_ddr_context *ddr_ctx, |
| uint32_t addr, uint32_t mask) |
| { |
| ddr_reg_wr(ddr_ctx, addr, ddr_reg_rd_cache(ddr_ctx, addr) | mask); |
| } |
| |
| static inline void ddr_reg_clr(struct ab_ddr_context *ddr_ctx, |
| uint32_t addr, uint32_t mask) |
| { |
| ddr_reg_wr(ddr_ctx, addr, ddr_reg_rd_cache(ddr_ctx, addr) & (~mask)); |
| } |
| |
| static inline void ddr_reg_clr_set(struct ab_ddr_context *ddr_ctx, |
| uint32_t addr, uint32_t clr_mask, uint32_t set_mask) |
| { |
| ddr_reg_wr(ddr_ctx, addr, |
| (ddr_reg_rd_cache(ddr_ctx, addr) & (~clr_mask)) | set_mask); |
| } |
| |
| static inline uint32_t ddr_mem_rd(uint32_t addr) |
| { |
| uint32_t data = 0xffffffff; |
| |
| WARN_ON(memory_config_read(addr, 0x4, &data)); |
| |
| return data; |
| } |
| |
| static inline void ddr_mem_wr(uint32_t addr, uint32_t data) |
| { |
| WARN_ON(memory_config_write(addr, 0x4, data)); |
| } |
| |
| static inline int ddr_read_mr_reg(struct ab_ddr_context *ddr_ctx, |
| int32_t mr_num) |
| { |
| ddr_reg_wr(ddr_ctx, DREX_DIRECTCMD, MRR(mr_num)); |
| |
| /* Read the DREX_DIRECTCMD back to make sure the previous write is |
| * reflected before continuing. |
| */ |
| ddr_reg_rd(ddr_ctx, DREX_DIRECTCMD); |
| |
| /* This function is called after the MR read command is sent to the |
| * DRAM device. As the response from DRAM device may take some time, |
| * please wait for "MR_READ_DELAY_USEC" time before continuing to |
| * read the MR read response from DREX_MRSTATUS register. |
| */ |
| ddr_usleep(MR_READ_DELAY_USEC); |
| |
| return ddr_reg_rd(ddr_ctx, DREX_MRSTATUS); |
| } |
| |
| void ddr_prbs_training_init(struct ab_ddr_context *ddr_ctx); |
| int32_t ddrphy_run_vref_training(struct ab_ddr_context *ctx); |
| void ddrphy_set_write_vref(struct ab_ddr_context *ddr_ctx, |
| uint32_t vref, enum vref_byte_t byte); |
| void ddrphy_set_read_vref(struct ab_ddr_context *ddr_ctx, |
| uint32_t vref_phy0, uint32_t vref_phy1, enum vref_byte_t byte); |
| uint32_t ddr_get_phy_vref(uint32_t idx); |
| uint32_t ddr_get_dram_vref(uint32_t idx); |
| int ddr_enter_self_refresh_mode(struct ab_ddr_context *ddr_ctx, int ref_ctrl); |
| int ddr_exit_self_refresh_mode(struct ab_ddr_context *ddr_ctx, int ref_ctrl); |
| |
| #ifdef CONFIG_AB_DDR_RW_TEST |
| int __ab_ddr_read_write_test(void *ctx, unsigned int read_write); |
| int ab_ddr_read_write_test(void *ctx, unsigned int read_write); |
| #endif |
| |
| #ifdef CONFIG_AB_DDR_EYE_MARGIN |
| int ab_ddr_eye_margin(void *ctx, unsigned int test_data); |
| int ab_ddr_eye_margin_plot(void *ctx); |
| #endif |
| |
| #ifdef CONFIG_AB_DDR_PPC |
| void ab_ddr_ppc_ctrl(void *ctx, int ppc_start); |
| int ab_ddr_ppc_set_event(void *ctx, unsigned int counter_idx, |
| unsigned int event); |
| #endif |
| |
| #endif /* _AIRBRUSH_DDR_INTERNAL_H_ */ |
