| /* Copyright (c) 2019, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/clock/mdss-14nm-pll-clk.h> |
| |
| &soc { |
| mdss_mdp: qcom,mdss_mdp@5e00000 { |
| compatible = "qcom,sde-kms"; |
| reg = <0x5e00000 0x84208>, |
| <0x5eb0000 0x2008>, |
| <0x5eac000 0x214>; |
| reg-names = "mdp_phys", |
| "vbif_phys", |
| "regdma_phys"; |
| |
| clocks = |
| <&clock_gcc GCC_DISP_AHB_CLK>, |
| <&clock_gcc GCC_DISP_HF_AXI_CLK>, |
| <&clock_gcc GCC_DISP_THROTTLE_CORE_CLK>, |
| <&clock_gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, |
| <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; |
| clock-names = "gcc_iface", "gcc_bus", "throttle_clk", "div_clk", |
| "iface_clk", "core_clk", "vsync_clk", |
| "lut_clk", "rot_clk"; |
| clock-rate = <0 0 0 0 0 256000000 19200000 192000000 |
| 192000000>; |
| clock-max-rate = <0 0 0 0 0 400000000 19200000 400000000 |
| 307200000>; |
| qcom,dss-cx-ipeak = <&cx_ipeak_lm 1>; |
| |
| sde-vdd-supply = <&mdss_core_gdsc>; |
| |
| /* interrupt config */ |
| interrupts = <0 186 0>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| iommus = <&apps_smmu 0x400 0x0>; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| #power-domain-cells = <0>; |
| |
| #list-cells = <1>; |
| |
| /* hw blocks */ |
| qcom,sde-off = <0x1000>; |
| qcom,sde-len = <0x45c>; |
| |
| qcom,sde-ctl-off = <0x2000 0x2200 0x2400 |
| 0x2600 0x2800 0x2a00>; |
| qcom,sde-ctl-size = <0x1e0>; |
| qcom,sde-ctl-display-pref = "primary", "none", "none", |
| "none", "none"; |
| |
| qcom,sde-mixer-off = <0x45000 0x46000 0x0 |
| 0x0 0x0 0x0>; |
| qcom,sde-mixer-size = <0x320>; |
| qcom,sde-mixer-display-pref = "primary", "none", "none", |
| "none", "none", "none"; |
| |
| qcom,sde-mixer-cwb-pref = "none", "cwb", "none", |
| "none", "none", "none"; |
| qcom,sde-mixer-stage-base-layer; |
| |
| qcom,sde-dspp-top-off = <0x1300>; |
| qcom,sde-dspp-top-size = <0x80>; |
| qcom,sde-dspp-off = <0x55000>; |
| qcom,sde-dspp-size = <0x1800>; |
| |
| |
| qcom,sde-wb-off = <0x66000>; |
| qcom,sde-wb-size = <0x2c8>; |
| qcom,sde-wb-xin-id = <6>; |
| qcom,sde-wb-id = <2>; |
| qcom,sde-wb-clk-ctrl = <0x3b8 24>; |
| |
| qcom,sde-intf-off = <0x6b000 0x6b800>; |
| qcom,sde-intf-size = <0x2b8>; |
| qcom,sde-intf-type = "dp", "dsi"; |
| |
| qcom,sde-pp-off = <0x71000 0x71800>; |
| qcom,sde-pp-slave = <0x0 0x0>; |
| qcom,sde-pp-size = <0xd4>; |
| |
| qcom,sde-cdm-off = <0x7a200>; |
| qcom,sde-cdm-size = <0x224>; |
| |
| qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0 0x30e0>; |
| qcom,sde-dither-version = <0x00010000>; |
| qcom,sde-dither-size = <0x20>; |
| |
| qcom,sde-sspp-type = "vig", "dma", "dma"; |
| |
| qcom,sde-sspp-off = <0x5000 0x25000 0x27000>; |
| qcom,sde-sspp-src-size = <0x1f0>; |
| |
| qcom,sde-sspp-xin-id = <0 1 5>; |
| qcom,sde-sspp-excl-rect = <1 1 1>; |
| qcom,sde-sspp-smart-dma-priority = <3 1 2>; |
| qcom,sde-smart-dma-rev = "smart_dma_v2p5"; |
| |
| qcom,sde-mixer-pair-mask = <2 1 0 0 0 0>; |
| |
| qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98 |
| 0xb0 0xc8 0xe0 0xf8 0x110>; |
| |
| qcom,sde-max-per-pipe-bw-kbps = <4500000 4500000 4500000>; |
| |
| /* offsets are relative to "mdp_phys + qcom,sde-off */ |
| qcom,sde-sspp-clk-ctrl = |
| <0x2ac 0>, <0x2ac 8>, <0x2b4 8>; |
| qcom,sde-sspp-csc-off = <0x1a00>; |
| qcom,sde-csc-type = "csc-10bit"; |
| qcom,sde-qseed-type = "qseedv3lite"; |
| qcom,sde-sspp-qseed-off = <0xa00>; |
| qcom,sde-mixer-linewidth = <2560>; |
| qcom,sde-sspp-linewidth = <2160>; |
| qcom,sde-wb-linewidth = <2160>; |
| qcom,sde-mixer-blendstages = <0x6>; |
| qcom,sde-highest-bank-bit = <0x1>; |
| qcom,sde-ubwc-version = <0x100>; |
| qcom,sde-ubwc-swizzle = <1>; |
| qcom,sde-panic-per-pipe; |
| qcom,sde-has-cdp; |
| |
| qcom,sde-has-dim-layer; |
| qcom,sde-has-idle-pc; |
| |
| qcom,sde-max-bw-low-kbps = <4100000>; |
| qcom,sde-max-bw-high-kbps = <4100000>; |
| qcom,sde-min-core-ib-kbps = <2400000>; |
| qcom,sde-min-llcc-ib-kbps = <800000>; |
| qcom,sde-min-dram-ib-kbps = <800000>; |
| qcom,sde-dram-channels = <2>; |
| qcom,sde-num-nrt-paths = <0>; |
| |
| |
| qcom,sde-vbif-off = <0>; |
| qcom,sde-vbif-size = <0x1040>; |
| qcom,sde-vbif-id = <0>; |
| qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>; |
| qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>; |
| |
| qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>; |
| qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>; |
| |
| /* macrotile & macrotile-qseed has the same configs */ |
| qcom,sde-danger-lut = <0x0000000f 0x0000ffff |
| 0x00000000 0x00000000 0x0000ffff>; |
| |
| qcom,sde-safe-lut-linear = <0 0xfff8>; |
| qcom,sde-safe-lut-macrotile = <0 0xf000>; |
| /* same as safe-lut-macrotile */ |
| qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>; |
| qcom,sde-safe-lut-nrt = <0 0xffff>; |
| qcom,sde-safe-lut-cwb = <0 0xffff>; |
| |
| qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>; |
| qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>; |
| qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>; |
| qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>; |
| qcom,sde-qos-lut-cwb = <0 0x75300000 0x00000000>; |
| |
| qcom,sde-cdp-setting = <1 1>, <1 0>; |
| |
| qcom,sde-qos-cpu-mask = <0x3>; |
| qcom,sde-qos-cpu-dma-latency = <300>; |
| |
| /* offsets are relative to "mdp_phys + qcom,sde-off */ |
| |
| qcom,sde-reg-dma-off = <0>; |
| qcom,sde-reg-dma-version = <0x00010001>; |
| qcom,sde-reg-dma-trigger-off = <0x119c>; |
| |
| qcom,sde-secure-sid-mask = <0x0000401>; |
| qcom,sde-num-mnoc-ports = <1>; |
| qcom,sde-axi-bus-width = <16>; |
| |
| qcom,sde-sspp-vig-blocks { |
| qcom,sde-vig-csc-off = <0x1a00>; |
| qcom,sde-vig-qseed-off = <0xa00>; |
| qcom,sde-vig-qseed-size = <0xa0>; |
| qcom,sde-vig-inverse-pma; |
| }; |
| |
| |
| qcom,sde-dspp-blocks { |
| qcom,sde-dspp-igc = <0x0 0x00030001>; |
| qcom,sde-dspp-hsic = <0x800 0x00010007>; |
| qcom,sde-dspp-memcolor = <0x880 0x00010007>; |
| qcom,sde-dspp-hist = <0x800 0x00010007>; |
| qcom,sde-dspp-sixzone= <0x900 0x00010007>; |
| qcom,sde-dspp-vlut = <0xa00 0x00010008>; |
| qcom,sde-dspp-pcc = <0x1700 0x00040000>; |
| qcom,sde-dspp-gc = <0x17c0 0x00010008>; |
| qcom,sde-dspp-dither = <0x82c 0x00010007>; |
| }; |
| |
| qcom,platform-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,platform-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "sde-vdd"; |
| qcom,supply-min-voltage = <0>; |
| qcom,supply-max-voltage = <0>; |
| qcom,supply-enable-load = <0>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| |
| smmu_sde_sec: qcom,smmu_sde_sec_cb { |
| compatible = "qcom,smmu_sde_sec"; |
| iommus = <&apps_smmu 0x401 0x0>; |
| }; |
| |
| /* data and reg bus scale settings */ |
| qcom,sde-data-bus { |
| qcom,msm-bus,name = "mdss_sde"; |
| qcom,msm-bus,num-cases = <3>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <22 512 0 0>, |
| <22 512 0 4800000>, |
| <22 512 0 4800000>; |
| }; |
| |
| qcom,sde-reg-bus { |
| qcom,msm-bus,name = "mdss_reg"; |
| qcom,msm-bus,num-cases = <4>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <1 700 0 0>, |
| <1 700 0 76800>, |
| <1 700 0 150000>, |
| <1 700 0 300000>; |
| }; |
| }; |
| |
| mdss_rotator: qcom,mdss_rotator@5e00000 { |
| compatible = "qcom,sde_rotator"; |
| reg = <0x5e00000 0xac000>, |
| <0x5eb0000 0x2008>; |
| reg-names = "mdp_phys", |
| "rot_vbif_phys"; |
| |
| #list-cells = <1>; |
| |
| qcom,mdss-rot-mode = <1>; |
| qcom,mdss-highest-bank-bit = <0x1>; |
| qcom,sde-ubwc-malsize = <0x1>; |
| qcom,sde-ubwc_swizzle = <0x1>; |
| |
| /* Bus Scale Settings */ |
| qcom,msm-bus,name = "mdss_rotator"; |
| qcom,msm-bus,num-cases = <3>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <22 512 0 0>, |
| <22 512 0 6400000>, |
| <22 512 0 6400000>; |
| |
| rot-vdd-supply = <&mdss_core_gdsc>; |
| qcom,supply-names = "rot-vdd"; |
| |
| clocks = |
| <&clock_gcc GCC_DISP_AHB_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; |
| clock-names = "gcc_iface", |
| "iface_clk", "rot_clk"; |
| |
| interrupt-parent = <&mdss_mdp>; |
| interrupts = <2 0>; |
| |
| power-domains = <&mdss_mdp>; |
| |
| /*Offline rotator RT setting */ |
| qcom,mdss-rot-parent = <&mdss_mdp 0>; |
| qcom,mdss-rot-xin-id = <10 11>; |
| |
| /* Offline rotator QoS setting */ |
| qcom,mdss-rot-vbif-qos-setting = <3 3 4 4 5 5 6 6>; |
| qcom,mdss-rot-cdp-setting = <1 1>; |
| qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>; |
| qcom,mdss-rot-danger-lut = <0x0 0x0>; |
| qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>; |
| |
| qcom,mdss-default-ot-rd-limit = <32>; |
| qcom,mdss-default-ot-wr-limit = <32>; |
| |
| qcom,mdss-sbuf-headroom = <20>; |
| |
| /* reg bus scale settings */ |
| rot_reg: qcom,rot-reg-bus { |
| qcom,msm-bus,name = "mdss_rot_reg"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <1 700 0 0>, |
| <1 700 0 76800>; |
| }; |
| |
| smmu_rot_unsec: qcom,smmu_rot_unsec_cb { |
| compatible = "qcom,smmu_sde_rot_unsec"; |
| iommus = <&apps_smmu 0x402 0x0>; |
| }; |
| |
| smmu_rot_sec: qcom,smmu_rot_sec_cb { |
| compatible = "qcom,smmu_sde_rot_sec"; |
| iommus = <&apps_smmu 0x403 0x0>; |
| }; |
| }; |
| |
| mdss_dsi0: qcom,mdss_dsi_ctrl0@5e94000 { |
| compatible = "qcom,dsi-ctrl-hw-v2.3"; |
| label = "dsi-ctrl-0"; |
| cell-index = <0>; |
| reg = <0x5e94000 0x400>, |
| <0x5f08000 0x4>; |
| reg-names = "dsi_ctrl", "disp_cc_base"; |
| interrupt-parent = <&mdss_mdp>; |
| interrupts = <4 0>; |
| vdda-1p2-supply = <&L18A>; |
| clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, |
| <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>, |
| <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>; |
| clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk", |
| "pixel_clk", "pixel_clk_rcg", |
| "esc_clk"; |
| |
| qcom,ctrl-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,ctrl-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vdda-1p2"; |
| qcom,supply-min-voltage = <1232000>; |
| qcom,supply-max-voltage = <1232000>; |
| qcom,supply-enable-load = <21800>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| qcom,core-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,core-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "refgen"; |
| qcom,supply-min-voltage = <0>; |
| qcom,supply-max-voltage = <0>; |
| qcom,supply-enable-load = <0>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| }; |
| |
| mdss_dsi_phy0: qcom,mdss_dsi_phy0@5e94400 { |
| compatible = "qcom,dsi-phy-v2.0"; |
| label = "dsi-phy-0"; |
| cell-index = <0>; |
| reg = <0x5e94400 0x588>, |
| <0x5e01400 0x100>, |
| <0x5e94200 0x100>; |
| reg-names = "dsi_phy", "phy_clamp_base", |
| "dyn_refresh_base"; |
| vdda-0p9-supply = <&VDD_MX_LEVEL>; |
| qcom,platform-strength-ctrl = [ff 06 |
| ff 06 |
| ff 06 |
| ff 06 |
| ff 00]; |
| qcom,platform-lane-config = [00 00 10 0f |
| 00 00 10 0f |
| 00 00 10 0f |
| 00 00 10 0f |
| 00 00 10 8f]; |
| qcom,platform-regulator-settings = [1d 1d 1d 1d 1d]; |
| qcom,panel-allow-phy-poweroff; |
| qcom,phy-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| qcom,phy-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vdda-0p9"; |
| qcom,supply-min-voltage = |
| <RPM_SMD_REGULATOR_LEVEL_NOM>; |
| qcom,supply-max-voltage = |
| <RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>; |
| qcom,supply-off-min-voltage = |
| <RPM_SMD_REGULATOR_LEVEL_RETENTION>; |
| qcom,supply-enable-load = <0>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| }; |
| |
| ext_disp: qcom,msm-ext-disp { |
| compatible = "qcom,msm-ext-disp"; |
| |
| ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { |
| compatible = "qcom,msm-ext-disp-audio-codec-rx"; |
| }; |
| }; |
| |
| sde_dp: qcom,dp_display@0{ |
| status = "disabled"; |
| cell-index = <0>; |
| compatible = "qcom,dp-display"; |
| |
| vdda-1p8-supply = <&pm6125_l10>; |
| vdda-0p9-supply = <&pm6125_l7>; |
| vdda-3p1-supply = <&pm6125_l15>; |
| hpd-pwr-supply = <&pm6125_l9>; |
| |
| reg = <0x05e90000 0xf4>, |
| <0x05e90200 0xc0>, |
| <0x05e90400 0x600>, |
| <0x05e90a00 0x98>, |
| <0x01616000 0x17c>, |
| <0x01616400 0x10c>, |
| <0x01616800 0x10c>, |
| <0x05f0212c 0x8>, |
| <0x01b40000 0x7000>, |
| <0x01616c30 0x10>, |
| <0x05ee1000 0x2c>, |
| <0x003cb248 0x4>; |
| reg-names = "dp_ahb", "dp_aux", "dp_link", "dp_p0", |
| "dp_phy", "dp_ln_tx0", "dp_ln_tx1", |
| "dp_pixel_mn", "qfprom_physical", "dp_pll", |
| "hdcp_physical", "dp_tcsr"; |
| |
| interrupt-parent = <&mdss_mdp>; |
| interrupts = <12 0>; |
| |
| clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>, |
| <&clock_gcc GCC_AHB2PHY_USB_CLK>, |
| <&clock_rpmcc CXO_SMD_OTG_CLK>, |
| <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>, |
| <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, |
| <&mdss_dp_pll DP_PHY_PLL_VCO_DIV_CLK>, |
| <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; |
| |
| clock-names = "core_aux_clk", "core_usb_ahb_clk", |
| "core_usb_ref_clk_src", |
| "core_usb_ref_clk", |
| "core_usb_pipe_clk", "link_clk", "link_iface_clk", |
| "crypto_clk", "pixel_clk_rcg", "pixel_parent", |
| "strm0_pixel_clk"; |
| |
| qcom,phy-version = <0x200>; |
| qcom,aux-cfg0-settings = [20 00]; |
| qcom,aux-cfg1-settings = [24 13 23 1d]; |
| qcom,aux-cfg2-settings = [28 24]; |
| qcom,aux-cfg3-settings = [2c 00]; |
| qcom,aux-cfg4-settings = [30 0a]; |
| qcom,aux-cfg5-settings = [34 26]; |
| qcom,aux-cfg6-settings = [38 0a]; |
| qcom,aux-cfg7-settings = [3c 03]; |
| qcom,aux-cfg8-settings = [40 bb]; |
| qcom,aux-cfg9-settings = [44 03]; |
| |
| qcom,logical2physical-lane-map = [00 01 02 03]; |
| |
| qcom,max-lclk-frequency-khz = <540000>; |
| qcom,max-pclk-frequency-khz = <200000>; |
| |
| qcom,ext-disp = <&ext_disp>; |
| |
| qcom,usbplug-cc-gpio = <&tlmm 102 0>; |
| |
| pinctrl-names = "mdss_dp_active", "mdss_dp_sleep", |
| "mdss_dp_hpd_active", "mdss_dp_hpd_tlmm", |
| "mdss_dp_hpd_ctrl"; |
| pinctrl-0 = <&sde_dp_usbplug_cc_active>; |
| pinctrl-1 = <&sde_dp_usbplug_cc_suspend>; |
| pinctrl-2 = <&sde_dp_hotplug_tlmm>; |
| pinctrl-3 = <&sde_dp_hotplug_tlmm>; |
| pinctrl-4 = <&sde_dp_hotplug_ctrl>; |
| |
| qcom,ctrl-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,ctrl-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vdda-1p8"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1896000>; |
| qcom,supply-enable-load = <20000>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| |
| qcom,phy-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,phy-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vdda-0p9"; |
| qcom,supply-min-voltage = <872000>; |
| qcom,supply-max-voltage = <976000>; |
| qcom,supply-enable-load = <50000>; |
| qcom,supply-disable-load = <0>; |
| }; |
| qcom,phy-supply-entry@1 { |
| reg = <1>; |
| qcom,supply-name = "vdda-3p1"; |
| qcom,supply-min-voltage = <3104000>; |
| qcom,supply-max-voltage = <3232000>; |
| qcom,supply-enable-load = <5250>; |
| qcom,supply-disable-load = <0>; |
| }; |
| qcom,phy-supply-entry@2 { |
| reg = <2>; |
| qcom,supply-name = "hpd-pwr"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1896000>; |
| qcom,supply-enable-load = <10000>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| |
| qcom,core-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,core-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "refgen"; |
| qcom,supply-min-voltage = <0>; |
| qcom,supply-max-voltage = <0>; |
| qcom,supply-enable-load = <0>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| }; |
| }; |
