arch/arm64/boot/dts/qcom/sdmmagpie-npu.dtsi

/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 */

&soc {
	msm_npu: qcom,msm_npu@9800000 {
		compatible = "qcom,msm-npu";
		reg = <0x9800000 0x40000>,
			<0x9900000 0x10000>,
			<0x9960200 0x600>,
			<0x780000 0x7000>;
		reg-names = "tcm", "core", "bwmon", "qfprom_physical";
		interrupts = <GIC_SPI 583 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 587 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq";
		iommus = <&apps_smmu 0x1461 0x0>;
		cache-slice-names = "npu";
		cache-slices = <&llcc 23>;

		clocks = <&clock_aop QDSS_CLK>,
			<&clock_npucc NPU_CC_ARMWIC_CORE_CLK>,
			<&clock_npucc NPU_CC_CAL_DP_CLK>,
			<&clock_npucc NPU_CC_CAL_DP_CDC_CLK>,
			<&clock_npucc NPU_CC_CONF_NOC_AHB_CLK>,
			<&clock_npucc NPU_CC_COMP_NOC_AXI_CLK>,
			<&clock_npucc NPU_CC_NPU_CORE_CLK>,
			<&clock_npucc NPU_CC_NPU_CORE_CTI_CLK>,
			<&clock_npucc NPU_CC_NPU_CORE_APB_CLK>,
			<&clock_npucc NPU_CC_NPU_CORE_ATB_CLK>,
			<&clock_npucc NPU_CC_NPU_CPC_CLK>,
			<&clock_npucc NPU_CC_NPU_CPC_TIMER_CLK>,
			<&clock_npucc NPU_CC_QTIMER_CORE_CLK>,
			<&clock_npucc NPU_CC_SLEEP_CLK>,
			<&clock_npucc NPU_CC_BWMON_CLK>,
			<&clock_npucc NPU_CC_PERF_CNT_CLK>,
			<&clock_npucc NPU_CC_BTO_CORE_CLK>,
			<&clock_npucc NPU_CC_XO_CLK>;
		clock-names = "qdss_clk",
			"armwic_core_clk",
			"cal_dp_clk",
			"cal_dp_cdc_clk",
			"conf_noc_ahb_clk",
			"comp_noc_axi_clk",
			"npu_core_clk",
			"npu_core_cti_clk",
			"npu_core_apb_clk",
			"npu_core_atb_clk",
			"npu_cpc_clk",
			"npu_cpc_timer_clk",
			"qtimer_core_clk",
			"sleep_clk",
			"bwmon_clk",
			"perf_cnt_clk",
			"bto_core_clk",
			"xo_clk";
		vdd-supply = <&npu_core_gdsc>;
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		qcom,proxy-reg-names ="vdd", "vdd_cx";
		qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mboxes = <&qmp_npu0 0>, <&qmp_npu1 0>;
		mbox-names = "npu_low", "npu_high";
		#cooling-cells = <2>;
		qcom,npubw-dev = <&npu_npu_ddr_bw>;
		qcom,npu-cxlimit-enable;
		qcom,npu-pwrlevels {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "qcom,npu-pwrlevels";
			initial-pwrlevel = <4>;
			qcom,npu-pwrlevel@0 {
				reg = <0>;
				vreg = <1>;
				clk-freq = <0
					100000000
					300000000
					300000000
					30000000
					150000000
					100000000
					37500000
					19200000
					60000000
					100000000
					19200000
					19200000
					0
					19200000
					300000000
					19200000
					19200000>;
			};
			qcom,npu-pwrlevel@1 {
				reg = <1>;
				vreg = <2>;
				clk-freq = <0
					150000000
					400000000
					400000000
					37500000
					200000000
					150000000
					75000000
					19200000
					120000000
					150000000
					19200000
					19200000
					0
					19200000
					400000000
					19200000
					19200000>;
			};
			qcom,npu-pwrlevel@2 {
				reg = <2>;
				vreg = <3>;
				clk-freq = <0
					200000000
					466500000
					466500000
					37500000
					300000000
					200000000
					75000000
					19200000
					120000000
					200000000
					19200000
					19200000
					0
					19200000
					466500000
					19200000
					19200000>;
			};
			qcom,npu-pwrlevel@3 {
				reg = <3>;
				vreg = <4>;
				clk-freq = <0
					300000000
					600000000
					600000000
					75000000
					403000000
					300000000
					150000000
					19200000
					240000000
					300000000
					19200000
					19200000
					0
					19200000
					600000000
					19200000
					19200000>;
			};
			qcom,npu-pwrlevel@4 {
				reg = <4>;
				vreg = <6>;
				clk-freq = <0
					400000000
					700000000
					700000000
					75000000
					533000000
					400000000
					150000000
					19200000
					300000000
					400000000
					19200000
					19200000
					0
					19200000
					700000000
					19200000
					19200000>;
			};
		};
	};
};