| /* |
| * Copyright (c) 2019, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/clock/qcom,gcc-sm8150.h> |
| |
| &soc { |
| pcie0: qcom,pcie@1c00000 { |
| compatible = "qcom,pci-msm"; |
| cell-index = <0>; |
| |
| reg = <0x1c00000 0x4000>, |
| <0x1c06000 0x1000>, |
| <0x60000000 0xf1d>, |
| <0x60000f20 0xa8>, |
| <0x60001000 0x1000>, |
| <0x60100000 0x100000>, |
| <0x60200000 0x100000>, |
| <0x60300000 0x3d00000>; |
| |
| reg-names = "parf", "phy", "dm_core", "elbi", |
| "iatu", "conf", "io", "bars"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>, |
| <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>; |
| interrupt-parent = <&pcie0>; |
| interrupts = <0 1 2 3 4>; |
| interrupt-names = "int_global_int", "int_a", "int_b", "int_c", |
| "int_d"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0xffffffff>; |
| interrupt-map = < 0 0 0 0 &intc 0 140 0 |
| 0 0 0 1 &intc 0 149 0 |
| 0 0 0 2 &intc 0 150 0 |
| 0 0 0 3 &intc 0 151 0 |
| 0 0 0 4 &intc 0 152 0>; |
| |
| qcom,phy-sequence = <0x0840 0x03 0x0 |
| 0x0094 0x08 0x0 |
| 0x0154 0x34 0x0 |
| 0x016c 0x08 0x0 |
| 0x0058 0x0f 0x0 |
| 0x00a4 0x42 0x0 |
| 0x0110 0x24 0x0 |
| 0x011c 0x03 0x0 |
| 0x0118 0xb4 0x0 |
| 0x010c 0x02 0x0 |
| 0x01bc 0x11 0x0 |
| 0x00bc 0x82 0x0 |
| 0x00d4 0x03 0x0 |
| 0x00d0 0x55 0x0 |
| 0x00cc 0x55 0x0 |
| 0x00b0 0x1a 0x0 |
| 0x00ac 0x0a 0x0 |
| 0x00c4 0x68 0x0 |
| 0x00e0 0x02 0x0 |
| 0x00dc 0xaa 0x0 |
| 0x00d8 0xab 0x0 |
| 0x00b8 0x34 0x0 |
| 0x00b4 0x14 0x0 |
| 0x0158 0x01 0x0 |
| 0x0074 0x06 0x0 |
| 0x007c 0x16 0x0 |
| 0x0084 0x36 0x0 |
| 0x0078 0x06 0x0 |
| 0x0080 0x16 0x0 |
| 0x0088 0x36 0x0 |
| 0x01b0 0x1e 0x0 |
| 0x01ac 0xb9 0x0 |
| 0x01b8 0x18 0x0 |
| 0x01b4 0x94 0x0 |
| 0x0050 0x07 0x0 |
| 0x0010 0x00 0x0 |
| 0x001c 0x31 0x0 |
| 0x0020 0x01 0x0 |
| 0x0024 0xde 0x0 |
| 0x0028 0x07 0x0 |
| 0x0030 0x4c 0x0 |
| 0x0034 0x06 0x0 |
| 0x029c 0x12 0x0 |
| 0x0284 0x35 0x0 |
| 0x023c 0x11 0x0 |
| 0x051c 0x03 0x0 |
| 0x0518 0x1c 0x0 |
| 0x0524 0x1e 0x0 |
| 0x04e8 0x00 0x0 |
| 0x04ec 0x0e 0x0 |
| 0x04f0 0x4a 0x0 |
| 0x04f4 0x0f 0x0 |
| 0x05b4 0x04 0x0 |
| 0x0434 0x7f 0x0 |
| 0x0444 0x70 0x0 |
| 0x0510 0x17 0x0 |
| 0x04d4 0x54 0x0 |
| 0x04d8 0x07 0x0 |
| 0x0598 0xd4 0x0 |
| 0x059c 0x54 0x0 |
| 0x05a0 0xdb 0x0 |
| 0x05a4 0x3b 0x0 |
| 0x05a8 0x31 0x0 |
| 0x0584 0x24 0x0 |
| 0x0588 0xe4 0x0 |
| 0x058c 0xec 0x0 |
| 0x0590 0x3b 0x0 |
| 0x0594 0x36 0x0 |
| 0x0570 0xff 0x0 |
| 0x0574 0xff 0x0 |
| 0x0578 0xff 0x0 |
| 0x057c 0x7f 0x0 |
| 0x0580 0x66 0x0 |
| 0x04fc 0x00 0x0 |
| 0x04f8 0xc0 0x0 |
| 0x0460 0x30 0x0 |
| 0x0464 0xc0 0x0 |
| 0x05bc 0x0c 0x0 |
| 0x04dc 0x0d 0x0 |
| 0x0408 0x0c 0x0 |
| 0x0414 0x03 0x0 |
| 0x09a4 0x01 0x0 |
| 0x0c90 0x00 0x0 |
| 0x0c40 0x01 0x0 |
| 0x0c48 0x01 0x0 |
| 0x0c50 0x00 0x0 |
| 0x0cbc 0x00 0x0 |
| 0x0ce0 0x58 0x0 |
| 0x0048 0x90 0x0 |
| 0x0c1c 0xc1 0x0 |
| 0x0988 0x88 0x0 |
| 0x0998 0x0b 0x0 |
| 0x08dc 0x0d 0x0 |
| 0x09ec 0x01 0x0 |
| 0x0800 0x00 0x0 |
| 0x0844 0x03 0x0>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pcie0_clkreq_default |
| &pcie0_perst_default |
| &pcie0_wake_default>; |
| |
| perst-gpio = <&tlmm 35 0>; |
| wake-gpio = <&tlmm 37 0>; |
| |
| gdsc-vdd-supply = <&pcie_0_gdsc>; |
| vreg-1.8-supply = <&pm8150_2_l8>; |
| vreg-0.9-supply = <&pm8150_2_l18>; |
| vreg-cx-supply = <&VDD_CX_LEVEL>; |
| |
| qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>; |
| qcom,vreg-0.9-voltage-level = <880000 880000 24000>; |
| qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX |
| RPMH_REGULATOR_LEVEL_NOM 0>; |
| |
| msi-parent = <&pcie0_msi>; |
| |
| qcom,no-l0s-supported; |
| qcom,no-l1-supported; |
| qcom,no-l1ss-supported; |
| qcom,no-aux-clk-sync; |
| |
| qcom,ep-latency = <10>; |
| |
| qcom,slv-addr-space-size = <0x4000000>; |
| |
| qcom,phy-status-offset = <0x814>; |
| qcom,phy-status-bit = <6>; |
| qcom,phy-power-down-offset = <0x840>; |
| |
| qcom,boot-option = <0x1>; |
| |
| linux,pci-domain = <0>; |
| |
| qcom,pcie-phy-ver = <2110>; |
| qcom,use-19p2mhz-aux-clk; |
| |
| qcom,smmu-sid-base = <0x1d80>; |
| |
| iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, |
| <0x100 &apps_smmu 0x1d81 0x1>, |
| <0x200 &apps_smmu 0x1d82 0x1>, |
| <0x300 &apps_smmu 0x1d83 0x1>, |
| <0x400 &apps_smmu 0x1d84 0x1>, |
| <0x500 &apps_smmu 0x1d85 0x1>, |
| <0x600 &apps_smmu 0x1d86 0x1>, |
| <0x700 &apps_smmu 0x1d87 0x1>, |
| <0x800 &apps_smmu 0x1d88 0x1>, |
| <0x900 &apps_smmu 0x1d89 0x1>, |
| <0xa00 &apps_smmu 0x1d8a 0x1>, |
| <0xb00 &apps_smmu 0x1d8b 0x1>, |
| <0xc00 &apps_smmu 0x1d8c 0x1>, |
| <0xd00 &apps_smmu 0x1d8d 0x1>, |
| <0xe00 &apps_smmu 0x1d8e 0x1>, |
| <0xf00 &apps_smmu 0x1d8f 0x1>; |
| |
| qcom,msm-bus,name = "pcie0"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <45 512 0 0>, |
| <45 512 500 800>; |
| |
| clocks = <&clock_virt GCC_PCIE_0_PIPE_CLK>, |
| <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_virt GCC_PCIE_0_AUX_CLK>, |
| <&clock_virt GCC_PCIE_0_CFG_AHB_CLK>, |
| <&clock_virt GCC_PCIE_0_MSTR_AXI_CLK>, |
| <&clock_virt GCC_PCIE_0_SLV_AXI_CLK>, |
| <&clock_virt GCC_PCIE_0_CLKREF_CLK>, |
| <&clock_virt GCC_PCIE_0_SLV_Q2A_AXI_CLK>, |
| <&clock_virt GCC_AGGRE_NOC_PCIE_TBU_CLK>, |
| <&clock_virt GCC_PCIE0_PHY_REFGEN_CLK>, |
| <&clock_virt GCC_PCIE_PHY_AUX_CLK>; |
| |
| clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", |
| "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", |
| "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", |
| "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", |
| "pcie_tbu_clk", "pcie_phy_refgen_clk", |
| "pcie_phy_aux_clk"; |
| |
| max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>, |
| <0>, <0>, <0>, <0>, <100000000>, <0>; |
| |
| resets = <&clock_virt GCC_PCIE_0_BCR>, |
| <&clock_virt GCC_PCIE_0_PHY_BCR>; |
| |
| reset-names = "pcie_0_core_reset", |
| "pcie_0_phy_reset"; |
| |
| status = "disabled"; |
| |
| pcie_rc0: pcie_rc0 { |
| reg = <0 0 0 0 0>; |
| }; |
| }; |
| |
| pcie0_msi: qcom,pcie0_msi@17a00040 { |
| compatible = "qcom,pci-msi"; |
| msi-controller; |
| reg = <0x17a00040 0x0>; |
| interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; |
| |
| status = "disabled"; |
| }; |
| }; |