drivers/clk/qcom/gpucc-lagoon.c - kernel/msm.git - Git at Google

 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  */

 #define pr_fmt(fmt) "clk: %s: " fmt, __func__

 #include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/regmap.h>

 #include <dt-bindings/clock/qcom,gpucc-lagoon.h>

 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
 #include "clk-rcg.h"
 #include "common.h"
 #include "clk-regmap-mux.h"
 #include "vdd-level-lagoon.h"

 static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
 static DEFINE_VDD_REGULATORS(vdd_gx, VDD_GX_NUM, 1, vdd_corner);
 static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_gx_corner);

 #define CX_GMU_CBCR_SLEEP_MASK		0xF
 #define CX_GMU_CBCR_SLEEP_SHIFT		4
 #define CX_GMU_CBCR_WAKE_MASK		0xF
 #define CX_GMU_CBCR_WAKE_SHIFT		8

 enum {
 	P_BI_TCXO,
 	P_CORE_BI_PLL_TEST_SE,
 	P_GPLL0_OUT_MAIN,
 	P_GPLL0_OUT_MAIN_DIV,
 	P_GPU_CC_PLL0_OUT_EVEN,
 	P_GPU_CC_PLL0_OUT_MAIN,
 	P_GPU_CC_PLL0_OUT_ODD,
 	P_GPU_CC_PLL1_OUT_EVEN,
 	P_GPU_CC_PLL1_OUT_MAIN,
 	P_GPU_CC_PLL1_OUT_ODD,
 	P_CRC_DIV,
 };

 static const struct parent_map gpu_cc_parent_map_0[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
 	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
 	{ P_GPLL0_OUT_MAIN, 5 },
 	{ P_GPLL0_OUT_MAIN_DIV, 6 },
 	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };

 static const char * const gpu_cc_parent_names_0[] = {
 	"bi_tcxo",
 	"gpu_cc_pll0",
 	"gpu_cc_pll1",
 	"gcc_gpu_gpll0_clk",
 	"gcc_gpu_gpll0_div_clk",
 	"core_bi_pll_test_se",
 };

 static const struct parent_map gpu_cc_parent_map_1[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_CRC_DIV, 1 },
 	{ P_GPU_CC_PLL0_OUT_ODD, 2 },
 	{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
 	{ P_GPU_CC_PLL1_OUT_ODD, 4 },
 	{ P_GPLL0_OUT_MAIN, 5 },
 	{ P_CORE_BI_PLL_TEST_SE, 7 },
 };

 static const char * const gpu_cc_parent_names_1[] = {
 	"bi_tcxo",
 	"crc_div",
 	"gpu_cc_pll0",
 	"gpu_cc_pll1",
 	"gpu_cc_pll1",
 	"gcc_gpu_gpll0_clk",
 	"core_bi_pll_test_se",
 };

 static const struct pll_vco fabia_vco[] = {
 	{ 249600000, 2000000000, 0 },
 };

 /* 506MHz Configuration*/
 static const struct alpha_pll_config gpu_cc_pll0_config = {
 	.l = 0x1A,
 	.cal_l = 0x3F,
 	.alpha = 0x5AAA,
 	.config_ctl_val = 0x20485699,
 	.config_ctl_hi_val = 0x00002067,
 	.test_ctl_val = 0x40000000,
 	.test_ctl_hi_val = 0x00000002,
 	.user_ctl_val = 0x00000001,
 	.user_ctl_hi_val = 0x00004805,
 };

 static struct clk_alpha_pll gpu_cc_pll0 = {
 	.offset = 0x0,
 	.vco_table = fabia_vco,
 	.num_vco = ARRAY_SIZE(fabia_vco),
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_pll0",
 			.parent_names = (const char *[]){ "bi_tcxo" },
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fabia_ops,
 			.vdd_class = &vdd_mx,
 			.num_rate_max = VDD_NUM,
 			.rate_max = (unsigned long[VDD_NUM]) {
 				[VDD_MIN] = 615000000,
 				[VDD_LOW] = 1066000000,
 				[VDD_LOW_L1] = 1600000000,
 				[VDD_NOMINAL] = 2000000000},
 		},
 	},
 };

 static struct clk_fixed_factor crc_div = {
 	.mult = 1,
 	.div = 2,
 	.hw.init = &(struct clk_init_data){
 		.name = "crc_div",
 		.parent_names = (const char *[]){ "gpu_cc_pll0" },
 		.num_parents = 1,
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
 	},
 };

 /* 514MHz Configuration*/
 static const struct alpha_pll_config gpu_cc_pll1_config = {
 	.l = 0x1A,
 	.cal_l = 0x3F,
 	.alpha = 0xC555,
 	.config_ctl_val = 0x20485699,
 	.config_ctl_hi_val = 0x00002067,
 	.test_ctl_val = 0x40000000,
 	.test_ctl_hi_val = 0x00000002,
 	.user_ctl_val = 0x00000001,
 	.user_ctl_hi_val = 0x00004805,
 };

 static struct clk_alpha_pll gpu_cc_pll1 = {
 	.offset = 0x100,
 	.vco_table = fabia_vco,
 	.num_vco = ARRAY_SIZE(fabia_vco),
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
 	.clkr = {
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_pll1",
 			.parent_names = (const char *[]){ "bi_tcxo" },
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fabia_ops,
 			.vdd_class = &vdd_mx,
 			.num_rate_max = VDD_NUM,
 			.rate_max = (unsigned long[VDD_NUM]) {
 				[VDD_MIN] = 615000000,
 				[VDD_LOW] = 1066000000,
 				[VDD_LOW_L1] = 1600000000,
 				[VDD_NOMINAL] = 2000000000},
 		},
 	},
 };

 static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
 	{ }
 };

 static struct clk_rcg2 gpu_cc_gmu_clk_src = {
 	.cmd_rcgr = 0x1120,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = gpu_cc_parent_map_0,
 	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpu_cc_gmu_clk_src",
 		.parent_names = gpu_cc_parent_names_0,
 		.num_parents = 6,
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 		.vdd_class = &vdd_cx,
 		.num_rate_max = VDD_NUM,
 		.rate_max = (unsigned long[VDD_NUM]) {
 			[VDD_LOWER] = 200000000},
 	},
 };

 static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
 	F(253000000, P_CRC_DIV, 1, 0, 0),
 	F(355000000, P_CRC_DIV, 1, 0, 0),
 	F(430000000, P_CRC_DIV, 1, 0, 0),
 	F(565000000, P_CRC_DIV, 1, 0, 0),
 	F(650000000, P_CRC_DIV, 1, 0, 0),
 	F(800000000, P_CRC_DIV, 1, 0, 0),
 	F(825000000, P_CRC_DIV, 1, 0, 0),
 	F(850000000, P_CRC_DIV, 1, 0, 0),
 	{ }
 };

 static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
 	.cmd_rcgr = 0x101c,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = gpu_cc_parent_map_1,
 	.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpu_cc_gx_gfx3d_clk_src",
 		.parent_names = gpu_cc_parent_names_1,
 		.num_parents = 7,
 		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_rcg2_ops,
 		.vdd_class = &vdd_gx,
 		.num_rate_max = VDD_NUM,
 		.rate_max = (unsigned long[VDD_GX_NUM]) {
 			[VDD_GX_LOWER] = 253000000,
 			[VDD_GX_LOW] = 355000000,
 			[VDD_GX_LOW_L1] = 430000000,
 			[VDD_GX_NOMINAL] = 565000000,
 			[VDD_GX_NOMINAL_L1] = 650000000,
 			[VDD_GX_HIGH] = 800000000,
 			[VDD_GX_HIGH_L1] = 850000000},
 	},
 };

 static struct clk_branch gpu_cc_acd_ahb_clk = {
 	.halt_reg = 0x1168,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x1168,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_acd_ahb_clk",
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_acd_cxo_clk = {
 	.halt_reg = 0x1164,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x1164,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_acd_cxo_clk",
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_ahb_clk = {
 	.halt_reg = 0x1078,
 	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x1078,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_ahb_clk",
 			.flags = CLK_IS_CRITICAL,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_crc_ahb_clk = {
 	.halt_reg = 0x107c,
 	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x107c,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_crc_ahb_clk",
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_cx_gfx3d_clk = {
 	.halt_reg = 0x10a4,
 	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x10a4,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_cx_gfx3d_clk",
 			.parent_names = (const char *[]){
 				"gpu_cc_gx_gfx3d_clk_src",
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
 	.halt_reg = 0x10a8,
 	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x10a8,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_cx_gfx3d_slv_clk",
 			.parent_names = (const char *[]){
 				"gpu_cc_gx_gfx3d_clk_src",
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_cx_gmu_clk = {
 	.halt_reg = 0x1098,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x1098,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_cx_gmu_clk",
 			.parent_names = (const char *[]){
 				"gpu_cc_gmu_clk_src",
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
 	.halt_reg = 0x108c,
 	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x108c,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_cx_snoc_dvm_clk",
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_cxo_aon_clk = {
 	.halt_reg = 0x1004,
 	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x1004,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_cxo_aon_clk",
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_cxo_clk = {
 	.halt_reg = 0x109c,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x109c,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_cxo_clk",
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_gx_cxo_clk = {
 	.halt_reg = 0x1060,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x1060,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_gx_cxo_clk",
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_gx_gfx3d_clk = {
 	.halt_reg = 0x1054,
 	.halt_check = BRANCH_HALT_SKIP,
 	.clkr = {
 		.enable_reg = 0x1054,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_gx_gfx3d_clk",
 			.parent_names = (const char *[]){
 				"gpu_cc_gx_gfx3d_clk_src",
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_gx_gmu_clk = {
 	.halt_reg = 0x1064,
 	.halt_check = BRANCH_HALT,
 	.clkr = {
 		.enable_reg = 0x1064,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_gx_gmu_clk",
 			.parent_names = (const char *[]){
 				"gpu_cc_gmu_clk_src",
 			},
 			.num_parents = 1,
 			.flags = CLK_SET_RATE_PARENT,
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_branch gpu_cc_gx_vsense_clk = {
 	.halt_reg = 0x1058,
 	.halt_check = BRANCH_HALT_DELAY,
 	.clkr = {
 		.enable_reg = 0x1058,
 		.enable_mask = BIT(0),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpu_cc_gx_vsense_clk",
 			.ops = &clk_branch2_ops,
 		},
 	},
 };

 static struct clk_regmap *gpu_cc_lagoon_clocks[] = {
 	[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
 	[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
 	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
 	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
 	[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
 	[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
 	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
 	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
 	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
 	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
 	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
 	[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
 	[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
 	[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
 	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
 	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
 	[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
 	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
 };

 static const struct regmap_config gpu_cc_lagoon_regmap_config = {
 	.reg_bits = 32,
 	.reg_stride = 4,
 	.val_bits = 32,
 	.max_register = 0x8008,
 	.fast_io = true,
 };

 static const struct qcom_cc_desc gpu_cc_lagoon_desc = {
 	.config = &gpu_cc_lagoon_regmap_config,
 	.clks = gpu_cc_lagoon_clocks,
 	.num_clks = ARRAY_SIZE(gpu_cc_lagoon_clocks),
 };

 static const struct of_device_id gpu_cc_lagoon_match_table[] = {
 	{ .compatible = "qcom,lagoon-gpucc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, gpu_cc_lagoon_match_table);

 static int gpu_cc_lagoon_probe(struct platform_device *pdev)
 {
 	struct regmap *regmap;
 	unsigned int value, mask;
 	int ret;

 	regmap = qcom_cc_map(pdev, &gpu_cc_lagoon_desc);
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);

 	vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
 	if (IS_ERR(vdd_cx.regulator[0])) {
 		if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
 			dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
 		return PTR_ERR(vdd_cx.regulator[0]);
 	}

 	vdd_gx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gx");
 	if (IS_ERR(vdd_gx.regulator[0])) {
 		if (!(PTR_ERR(vdd_gx.regulator[0]) == -EPROBE_DEFER))
 			dev_err(&pdev->dev, "Unable to get vdd_gx regulator\n");
 		return PTR_ERR(vdd_gx.regulator[0]);
 	}

 	vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
 	if (IS_ERR(vdd_mx.regulator[0])) {
 		if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER))
 			dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");
 		return PTR_ERR(vdd_mx.regulator[0]);
 	}

 	/* Register clock fixed factor for CRC divide. */
 	ret = devm_clk_hw_register(&pdev->dev, &crc_div.hw);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register hardware clock\n");
 		return ret;
 	}

 	clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
 	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);

 	ret = qcom_cc_really_probe(pdev, &gpu_cc_lagoon_desc, regmap);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
 		return ret;
 	}

 	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
 	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
 	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
 	value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
 	regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,
 								mask, value);

 	dev_info(&pdev->dev, "Registered GPU CC clocks\n");
 	return 0;
 }

 static struct platform_driver gpu_cc_lagoon_driver = {
 	.probe = gpu_cc_lagoon_probe,
 	.driver = {
 		.name = "lagoon-gpucc",
 		.of_match_table = gpu_cc_lagoon_match_table,
 	},
 };

 static int __init gpu_cc_lagoon_init(void)
 {
 	return platform_driver_register(&gpu_cc_lagoon_driver);
 }
 core_initcall(gpu_cc_lagoon_init);

 static void __exit gpu_cc_lagoon_exit(void)
 {
 	platform_driver_unregister(&gpu_cc_lagoon_driver);
 }
 module_exit(gpu_cc_lagoon_exit);

 MODULE_DESCRIPTION("QTI GPU_CC LAGOON Driver");
 MODULE_LICENSE("GPL v2");
	// SPDX-License-Identifier: GPL-2.0-only
	/*
	* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
	*/

	#define pr_fmt(fmt) "clk: %s: " fmt, __func__

	#include <linux/clk.h>
	#include <linux/clk-provider.h>
	#include <linux/module.h>
	#include <linux/of_device.h>
	#include <linux/regmap.h>

	#include <dt-bindings/clock/qcom,gpucc-lagoon.h>

	#include "clk-alpha-pll.h"
	#include "clk-branch.h"
	#include "clk-rcg.h"
	#include "common.h"
	#include "clk-regmap-mux.h"
	#include "vdd-level-lagoon.h"

	static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner);
	static DEFINE_VDD_REGULATORS(vdd_gx, VDD_GX_NUM, 1, vdd_corner);
	static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_gx_corner);

	#define CX_GMU_CBCR_SLEEP_MASK 0xF
	#define CX_GMU_CBCR_SLEEP_SHIFT 4
	#define CX_GMU_CBCR_WAKE_MASK 0xF
	#define CX_GMU_CBCR_WAKE_SHIFT 8

	enum {
	P_BI_TCXO,
	P_CORE_BI_PLL_TEST_SE,
	P_GPLL0_OUT_MAIN,
	P_GPLL0_OUT_MAIN_DIV,
	P_GPU_CC_PLL0_OUT_EVEN,
	P_GPU_CC_PLL0_OUT_MAIN,
	P_GPU_CC_PLL0_OUT_ODD,
	P_GPU_CC_PLL1_OUT_EVEN,
	P_GPU_CC_PLL1_OUT_MAIN,
	P_GPU_CC_PLL1_OUT_ODD,
	P_CRC_DIV,
	};

	static const struct parent_map gpu_cc_parent_map_0[] = {
	{ P_BI_TCXO, 0 },
	{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
	{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
	{ P_GPLL0_OUT_MAIN, 5 },
	{ P_GPLL0_OUT_MAIN_DIV, 6 },
	{ P_CORE_BI_PLL_TEST_SE, 7 },
	};

	static const char * const gpu_cc_parent_names_0[] = {
	"bi_tcxo",
	"gpu_cc_pll0",
	"gpu_cc_pll1",
	"gcc_gpu_gpll0_clk",
	"gcc_gpu_gpll0_div_clk",
	"core_bi_pll_test_se",
	};

	static const struct parent_map gpu_cc_parent_map_1[] = {
	{ P_BI_TCXO, 0 },
	{ P_CRC_DIV, 1 },
	{ P_GPU_CC_PLL0_OUT_ODD, 2 },
	{ P_GPU_CC_PLL1_OUT_EVEN, 3 },
	{ P_GPU_CC_PLL1_OUT_ODD, 4 },
	{ P_GPLL0_OUT_MAIN, 5 },
	{ P_CORE_BI_PLL_TEST_SE, 7 },
	};

	static const char * const gpu_cc_parent_names_1[] = {
	"bi_tcxo",
	"crc_div",
	"gpu_cc_pll0",
	"gpu_cc_pll1",
	"gpu_cc_pll1",
	"gcc_gpu_gpll0_clk",
	"core_bi_pll_test_se",
	};

	static const struct pll_vco fabia_vco[] = {
	{ 249600000, 2000000000, 0 },
	};

	/* 506MHz Configuration*/
	static const struct alpha_pll_config gpu_cc_pll0_config = {
	.l = 0x1A,
	.cal_l = 0x3F,
	.alpha = 0x5AAA,
	.config_ctl_val = 0x20485699,
	.config_ctl_hi_val = 0x00002067,
	.test_ctl_val = 0x40000000,
	.test_ctl_hi_val = 0x00000002,
	.user_ctl_val = 0x00000001,
	.user_ctl_hi_val = 0x00004805,
	};

	static struct clk_alpha_pll gpu_cc_pll0 = {
	.offset = 0x0,
	.vco_table = fabia_vco,
	.num_vco = ARRAY_SIZE(fabia_vco),
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
	.clkr = {
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_pll0",
	.parent_names = (const char *[]){ "bi_tcxo" },
	.num_parents = 1,
	.ops = &clk_alpha_pll_fabia_ops,
	.vdd_class = &vdd_mx,
	.num_rate_max = VDD_NUM,
	.rate_max = (unsigned long[VDD_NUM]) {
	[VDD_MIN] = 615000000,
	[VDD_LOW] = 1066000000,
	[VDD_LOW_L1] = 1600000000,
	[VDD_NOMINAL] = 2000000000},
	},
	},
	};

	static struct clk_fixed_factor crc_div = {
	.mult = 1,
	.div = 2,
	.hw.init = &(struct clk_init_data){
	.name = "crc_div",
	.parent_names = (const char *[]){ "gpu_cc_pll0" },
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_fixed_factor_ops,
	},
	};

	/* 514MHz Configuration*/
	static const struct alpha_pll_config gpu_cc_pll1_config = {
	.l = 0x1A,
	.cal_l = 0x3F,
	.alpha = 0xC555,
	.config_ctl_val = 0x20485699,
	.config_ctl_hi_val = 0x00002067,
	.test_ctl_val = 0x40000000,
	.test_ctl_hi_val = 0x00000002,
	.user_ctl_val = 0x00000001,
	.user_ctl_hi_val = 0x00004805,
	};

	static struct clk_alpha_pll gpu_cc_pll1 = {
	.offset = 0x100,
	.vco_table = fabia_vco,
	.num_vco = ARRAY_SIZE(fabia_vco),
	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
	.clkr = {
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_pll1",
	.parent_names = (const char *[]){ "bi_tcxo" },
	.num_parents = 1,
	.ops = &clk_alpha_pll_fabia_ops,
	.vdd_class = &vdd_mx,
	.num_rate_max = VDD_NUM,
	.rate_max = (unsigned long[VDD_NUM]) {
	[VDD_MIN] = 615000000,
	[VDD_LOW] = 1066000000,
	[VDD_LOW_L1] = 1600000000,
	[VDD_NOMINAL] = 2000000000},
	},
	},
	};

	static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
	{ }
	};

	static struct clk_rcg2 gpu_cc_gmu_clk_src = {
	.cmd_rcgr = 0x1120,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = gpu_cc_parent_map_0,
	.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_gmu_clk_src",
	.parent_names = gpu_cc_parent_names_0,
	.num_parents = 6,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_rcg2_ops,
	.vdd_class = &vdd_cx,
	.num_rate_max = VDD_NUM,
	.rate_max = (unsigned long[VDD_NUM]) {
	[VDD_LOWER] = 200000000},
	},
	};

	static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
	F(253000000, P_CRC_DIV, 1, 0, 0),
	F(355000000, P_CRC_DIV, 1, 0, 0),
	F(430000000, P_CRC_DIV, 1, 0, 0),
	F(565000000, P_CRC_DIV, 1, 0, 0),
	F(650000000, P_CRC_DIV, 1, 0, 0),
	F(800000000, P_CRC_DIV, 1, 0, 0),
	F(825000000, P_CRC_DIV, 1, 0, 0),
	F(850000000, P_CRC_DIV, 1, 0, 0),
	{ }
	};

	static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
	.cmd_rcgr = 0x101c,
	.mnd_width = 0,
	.hid_width = 5,
	.parent_map = gpu_cc_parent_map_1,
	.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
	.clkr.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_gx_gfx3d_clk_src",
	.parent_names = gpu_cc_parent_names_1,
	.num_parents = 7,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_rcg2_ops,
	.vdd_class = &vdd_gx,
	.num_rate_max = VDD_NUM,
	.rate_max = (unsigned long[VDD_GX_NUM]) {
	[VDD_GX_LOWER] = 253000000,
	[VDD_GX_LOW] = 355000000,
	[VDD_GX_LOW_L1] = 430000000,
	[VDD_GX_NOMINAL] = 565000000,
	[VDD_GX_NOMINAL_L1] = 650000000,
	[VDD_GX_HIGH] = 800000000,
	[VDD_GX_HIGH_L1] = 850000000},
	},
	};

	static struct clk_branch gpu_cc_acd_ahb_clk = {
	.halt_reg = 0x1168,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x1168,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_acd_ahb_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_acd_cxo_clk = {
	.halt_reg = 0x1164,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x1164,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_acd_cxo_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_ahb_clk = {
	.halt_reg = 0x1078,
	.halt_check = BRANCH_HALT_DELAY,
	.clkr = {
	.enable_reg = 0x1078,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_ahb_clk",
	.flags = CLK_IS_CRITICAL,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_crc_ahb_clk = {
	.halt_reg = 0x107c,
	.halt_check = BRANCH_HALT_DELAY,
	.clkr = {
	.enable_reg = 0x107c,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_crc_ahb_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_cx_gfx3d_clk = {
	.halt_reg = 0x10a4,
	.halt_check = BRANCH_HALT_DELAY,
	.clkr = {
	.enable_reg = 0x10a4,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_cx_gfx3d_clk",
	.parent_names = (const char *[]){
	"gpu_cc_gx_gfx3d_clk_src",
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_cx_gfx3d_slv_clk = {
	.halt_reg = 0x10a8,
	.halt_check = BRANCH_HALT_DELAY,
	.clkr = {
	.enable_reg = 0x10a8,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_cx_gfx3d_slv_clk",
	.parent_names = (const char *[]){
	"gpu_cc_gx_gfx3d_clk_src",
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_cx_gmu_clk = {
	.halt_reg = 0x1098,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x1098,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_cx_gmu_clk",
	.parent_names = (const char *[]){
	"gpu_cc_gmu_clk_src",
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
	.halt_reg = 0x108c,
	.halt_check = BRANCH_HALT_DELAY,
	.clkr = {
	.enable_reg = 0x108c,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_cx_snoc_dvm_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_cxo_aon_clk = {
	.halt_reg = 0x1004,
	.halt_check = BRANCH_HALT_DELAY,
	.clkr = {
	.enable_reg = 0x1004,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_cxo_aon_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_cxo_clk = {
	.halt_reg = 0x109c,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x109c,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_cxo_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_gx_cxo_clk = {
	.halt_reg = 0x1060,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x1060,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_gx_cxo_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_gx_gfx3d_clk = {
	.halt_reg = 0x1054,
	.halt_check = BRANCH_HALT_SKIP,
	.clkr = {
	.enable_reg = 0x1054,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_gx_gfx3d_clk",
	.parent_names = (const char *[]){
	"gpu_cc_gx_gfx3d_clk_src",
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_gx_gmu_clk = {
	.halt_reg = 0x1064,
	.halt_check = BRANCH_HALT,
	.clkr = {
	.enable_reg = 0x1064,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_gx_gmu_clk",
	.parent_names = (const char *[]){
	"gpu_cc_gmu_clk_src",
	},
	.num_parents = 1,
	.flags = CLK_SET_RATE_PARENT,
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_branch gpu_cc_gx_vsense_clk = {
	.halt_reg = 0x1058,
	.halt_check = BRANCH_HALT_DELAY,
	.clkr = {
	.enable_reg = 0x1058,
	.enable_mask = BIT(0),
	.hw.init = &(struct clk_init_data){
	.name = "gpu_cc_gx_vsense_clk",
	.ops = &clk_branch2_ops,
	},
	},
	};

	static struct clk_regmap *gpu_cc_lagoon_clocks[] = {
	[GPU_CC_ACD_AHB_CLK] = &gpu_cc_acd_ahb_clk.clkr,
	[GPU_CC_ACD_CXO_CLK] = &gpu_cc_acd_cxo_clk.clkr,
	[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
	[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
	[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
	[GPU_CC_CX_GFX3D_SLV_CLK] = &gpu_cc_cx_gfx3d_slv_clk.clkr,
	[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
	[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
	[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
	[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
	[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
	[GPU_CC_GX_CXO_CLK] = &gpu_cc_gx_cxo_clk.clkr,
	[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
	[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
	[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
	[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
	[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
	[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
	};

	static const struct regmap_config gpu_cc_lagoon_regmap_config = {
	.reg_bits = 32,
	.reg_stride = 4,
	.val_bits = 32,
	.max_register = 0x8008,
	.fast_io = true,
	};

	static const struct qcom_cc_desc gpu_cc_lagoon_desc = {
	.config = &gpu_cc_lagoon_regmap_config,
	.clks = gpu_cc_lagoon_clocks,
	.num_clks = ARRAY_SIZE(gpu_cc_lagoon_clocks),
	};

	static const struct of_device_id gpu_cc_lagoon_match_table[] = {
	{ .compatible = "qcom,lagoon-gpucc" },
	{ }
	};
	MODULE_DEVICE_TABLE(of, gpu_cc_lagoon_match_table);

	static int gpu_cc_lagoon_probe(struct platform_device *pdev)
	{
	struct regmap *regmap;
	unsigned int value, mask;
	int ret;

	regmap = qcom_cc_map(pdev, &gpu_cc_lagoon_desc);
	if (IS_ERR(regmap))
	return PTR_ERR(regmap);

	vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx");
	if (IS_ERR(vdd_cx.regulator[0])) {
	if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER))
	dev_err(&pdev->dev, "Unable to get vdd_cx regulator\n");
	return PTR_ERR(vdd_cx.regulator[0]);
	}

	vdd_gx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gx");
	if (IS_ERR(vdd_gx.regulator[0])) {
	if (!(PTR_ERR(vdd_gx.regulator[0]) == -EPROBE_DEFER))
	dev_err(&pdev->dev, "Unable to get vdd_gx regulator\n");
	return PTR_ERR(vdd_gx.regulator[0]);
	}

	vdd_mx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_mx");
	if (IS_ERR(vdd_mx.regulator[0])) {
	if (!(PTR_ERR(vdd_mx.regulator[0]) == -EPROBE_DEFER))
	dev_err(&pdev->dev, "Unable to get vdd_mx regulator\n");
	return PTR_ERR(vdd_mx.regulator[0]);
	}

	/* Register clock fixed factor for CRC divide. */
	ret = devm_clk_hw_register(&pdev->dev, &crc_div.hw);
	if (ret) {
	dev_err(&pdev->dev, "Failed to register hardware clock\n");
	return ret;
	}

	clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
	clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);

	ret = qcom_cc_really_probe(pdev, &gpu_cc_lagoon_desc, regmap);
	if (ret) {
	dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
	return ret;
	}

	/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
	mask \|= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
	value = 0xF << CX_GMU_CBCR_WAKE_SHIFT \| 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
	regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg,
	mask, value);

	dev_info(&pdev->dev, "Registered GPU CC clocks\n");
	return 0;
	}

	static struct platform_driver gpu_cc_lagoon_driver = {
	.probe = gpu_cc_lagoon_probe,
	.driver = {
	.name = "lagoon-gpucc",
	.of_match_table = gpu_cc_lagoon_match_table,
	},
	};

	static int __init gpu_cc_lagoon_init(void)
	{
	return platform_driver_register(&gpu_cc_lagoon_driver);
	}
	core_initcall(gpu_cc_lagoon_init);

	static void __exit gpu_cc_lagoon_exit(void)
	{
	platform_driver_unregister(&gpu_cc_lagoon_driver);
	}
	module_exit(gpu_cc_lagoon_exit);

	MODULE_DESCRIPTION("QTI GPU_CC LAGOON Driver");
	MODULE_LICENSE("GPL v2");