Documentation/devicetree/bindings/pci/msm_pcie.txt

MSM PCIe

MSM PCI express root complex

Required properties:
  - compatible: should be "qcom,msm-pcie"
  - cell-index: defines root complex ID.
  - qcom,ctrl-amt: Number of controllers.
  - #address-cells: Should provide a value of 0.
  - reg: should contain PCIe register maps.
  - reg-names: indicates various resources passed to driver by name.
		Should be "parf", "phy", "dm_core", "elbi", "conf", "io", "bars".
		These correspond to different modules within the PCIe core.
  - interrupts: Should be in the format <0 1 2> and it is an index to the
		interrupt-map that contains PCIe related interrupts.
  - #interrupt-cells: Should provide a value of 1.
  - #interrupt-map-mask: should provide a value of 0xffffffff.
  - interrupt-map:  Must create mapping for the number of interrupts
		    that are defined in above interrupts property.
		    For PCIe device node, it should define 13 mappings for
		    the corresponding PCIe interrupts supporting the specification.
  - interrupt-names: indicates interrupts passed to driver by name.
		     Should be "int_msi", "int_a", "int_b", "int_c", "int_d",
		     "int_pls_pme", "int_pme_legacy", "int_pls_err",
		     "int_aer_legacy", "int_pls_link_up",
		     "int_pls_link_down", "int_bridge_flush_n", "int_wake"
		     These correspond to the standard PCIe specification to support
		     MSIs, virtual IRQ's (INT#), link state notifications.
  - perst-gpio: PERST GPIO specified by PCIe spec.
  - wake-gpio: WAKE GPIO specified by PCIe spec.
  - clkreq-gpio: CLKREQ GPIO specified by PCIe spec.
  - <supply-name>-supply: phandle to the regulator device tree node.
    Refer to the schematics for the corresponding voltage regulators.
    vreg-1.8-supply: phandle to the analog supply for the PCIe controller.
    vreg-3.3-supply: phandle to the analog supply for the PCIe controller.
    vreg-0.9-supply: phandle to the analog supply for the PCIe controller.

Optional Properties:
  - qcom,<supply-name>-voltage-level: specifies voltage levels for supply.
    Should be specified in pairs (max, min, optimal), units uV.
  - clock-names: list of names of clock inputs.
		     Should be "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
				"pcie_0_ldo";
  - max-clock-frequency-hz: list of the maximum operating frequencies stored
				in the same order of clock names;
  - qcom,l1ss-supported: L1 sub-states (L1ss) is supported.
  - qcom,aux-clk-sync: The AUX clock is synchronous to the Core clock to
    support L1ss.
  - qcom,n-fts: The number of fast training sequences sent when the link state
    is changed from L0s to L0.
  - qcom,ep-wakeirq: The endpoint will issue wake signal when it is up, and the
    root complex has the capability to enumerate the endpoint for this case.
  - qcom,msi-gicm-addr: MSI address for GICv2m.
  - qcom,msi-gicm-base: MSI IRQ base for GICv2m.
  - qcom,ep-latency: The time (unit: ms) to wait for the PCIe endpoint to become
    stable after power on, before de-assert the PERST to the endpoint.

Example:

	pcie0: qcom,pcie@fc520000 {
		compatible = "qcom,msm_pcie";
		cell-index = <0>;
		qcom,ctrl-amt = <1>;
		#address-cells = <0>;
		reg = <0xfc520000 0x2000>,
		      <0xfc526000 0x1000>,
		      <0xff000000 0x1000>,
		      <0xff001000 0x1000>,
		      <0xff100000 0x1000>,
		      <0xff200000 0x100000>,
		      <0xff300000 0xd00000>;
		reg-names = "parf", "dm_core", "elbi",
				"conf", "io", "bars";
		interrupt-parent = <&pcie0>;
		interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0xffffffff>;
		interrupt-map = <0 &intc 0 243 0
				1 &intc 0 244 0
				2 &intc 0 245 0
				3 &intc 0 247 0
				4 &intc 0 248 0
				5 &intc 0 249 0
				6 &intc 0 250 0
				7 &intc 0 251 0
				8 &intc 0 252 0
				9 &intc 0 253 0
				10 &intc 0 254 0
				11 &intc 0 255 0
				12 &msmgpio 69 0x2>;
		interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
				"int_pls_pme", "int_pme_legacy", "int_pls_err",
				"int_aer_legacy", "int_pls_link_up",
				"int_pls_link_down", "int_bridge_flush_n",
				"int_wake";
		perst-gpio = <&msmgpio 70 0>;
		wake-gpio = <&msmgpio 69 0>;
		clkreq-gpio = <&msmgpio 68 0>;

		gdsc-vdd-supply = <&gdsc_pcie_0>;
		vreg-1.8-supply = <&pma8084_l12>;
		vreg-0.9-supply = <&pma8084_l4>;
		vreg-3.3-supply = <&wlan_vreg>;

		qcom,vreg-1.8-voltage-level = <1800000 1800000 1000>;
		qcom,vreg-0.9-voltage-level = <950000 950000 24000>;

		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
				"pcie_0_ldo";
		max-clock-frequency-hz = <125000000>, <0>, <1000000>,
						<0>, <0>, <0>, <0>;
		qcom,l1ss-supported;
		qcom,aux-clk-sync;
		qcom,n-fts = <0x50>;
		qcom,ep-wakeirq;
		qcom,msi-gicm-addr = <0xf9040040>;
		qcom,msi-gicm-base = <0x160>;
		qcom,ep-latency = <100>;
	};