| /* |
| * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <dt-bindings/clock/qcom,gcc-sdxprairie.h> |
| |
| &soc { |
| pcie0: qcom,pcie@1c00000 { |
| compatible = "qcom,pci-msm"; |
| cell-index = <0>; |
| |
| reg = <0x1c00000 0x4000>, |
| <0x1c06000 0x2000>, |
| <0x40000000 0xf1d>, |
| <0x40000f20 0xa8>, |
| <0x40001000 0x1000>, |
| <0x40100000 0x100000>; |
| |
| reg-names = "parf", "phy", "dm_core", "elbi", |
| "iatu", "conf"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>, |
| <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>; |
| interrupt-parent = <&pcie0>; |
| interrupts = <0 1 2 3 4>; |
| interrupt-names = "int_global_int", "int_a", "int_b", "int_c", |
| "int_d"; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0xffffffff>; |
| interrupt-map = <0 0 0 0 &intc 0 140 0 |
| 0 0 0 1 &intc 0 141 0 |
| 0 0 0 2 &intc 0 142 0 |
| 0 0 0 3 &intc 0 143 0 |
| 0 0 0 4 &intc 0 144 0>; |
| |
| qcom,phy-sequence = <0x1240 0x03 0x0 |
| 0x1010 0x00 0x0 |
| 0x101c 0x31 0x0 |
| 0x1020 0x01 0x0 |
| 0x1024 0xce 0x0 |
| 0x1028 0x0b 0x0 |
| 0x1030 0x97 0x0 |
| 0x1034 0x0c 0x0 |
| 0x1044 0x18 0x0 |
| 0x1048 0x90 0x0 |
| 0x1058 0x0f 0x0 |
| 0x1074 0x06 0x0 |
| 0x1078 0x06 0x0 |
| 0x107c 0x16 0x0 |
| 0x1080 0x16 0x0 |
| 0x1084 0x36 0x0 |
| 0x1088 0x36 0x0 |
| 0x1094 0x08 0x0 |
| 0x10a4 0x46 0x0 |
| 0x10a8 0x04 0x0 |
| 0x10ac 0x04 0x0 |
| 0x10b0 0x0d 0x0 |
| 0x10b4 0x0a 0x0 |
| 0x10b8 0x1a 0x0 |
| 0x10bc 0xc3 0x0 |
| 0x10c4 0xd0 0x0 |
| 0x10d4 0x05 0x0 |
| 0x10d8 0x55 0x0 |
| 0x10dc 0x55 0x0 |
| 0x10e0 0x05 0x0 |
| 0x110c 0x02 0x0 |
| 0x1154 0x34 0x0 |
| 0x1158 0x12 0x0 |
| 0x115c 0x00 0x0 |
| 0x1168 0x05 0x0 |
| 0x116c 0x04 0x0 |
| 0x119c 0x88 0x0 |
| 0x11a0 0x03 0x0 |
| 0x11ac 0xca 0x0 |
| 0x11b0 0x1e 0x0 |
| 0x11b4 0xd8 0x0 |
| 0x11b8 0x20 0x0 |
| 0x11bc 0x22 0x0 |
| 0x106c 0x0a 0x0 |
| 0x1070 0x10 0x0 |
| 0x11a4 0x05 0x0 |
| 0x11a8 0x0f 0x0 |
| 0x008c 0x06 0x0 |
| 0x00e0 0x01 0x0 |
| 0x00c4 0x01 0x0 |
| 0x0258 0x16 0x0 |
| 0x0378 0x83 0x0 |
| 0x0360 0xe2 0x0 |
| 0x0364 0x04 0x0 |
| 0x0368 0x30 0x0 |
| 0x0370 0xff 0x0 |
| 0x03cc 0x42 0x0 |
| 0x03d0 0x0d 0x0 |
| 0x03d4 0x77 0x0 |
| 0x03d8 0x2d 0x0 |
| 0x03dc 0x39 0x0 |
| 0x03e0 0x9f 0x0 |
| 0x03e4 0x0f 0x0 |
| 0x03e8 0x63 0x0 |
| 0x03ec 0xbf 0x0 |
| 0x03f0 0x79 0x0 |
| 0x03f4 0x4f 0x0 |
| 0x03f8 0x0f 0x0 |
| 0x03fc 0xd5 0x0 |
| 0x02ac 0x7f 0x0 |
| 0x0310 0x55 0x0 |
| 0x0334 0x0c 0x0 |
| 0x0338 0x00 0x0 |
| 0x0350 0x0f 0x0 |
| 0x088c 0x06 0x0 |
| 0x08e0 0x01 0x0 |
| 0x08c4 0x01 0x0 |
| 0x0a58 0x16 0x0 |
| 0x0b78 0x83 0x0 |
| 0x0b60 0xe2 0x0 |
| 0x0b64 0x04 0x0 |
| 0x0b68 0x30 0x0 |
| 0x0b70 0xff 0x0 |
| 0x0bcc 0x42 0x0 |
| 0x0bd0 0x0d 0x0 |
| 0x0bd4 0x77 0x0 |
| 0x0bd8 0x2d 0x0 |
| 0x0bdc 0x39 0x0 |
| 0x0be0 0x9f 0x0 |
| 0x0be4 0x0f 0x0 |
| 0x0be8 0x63 0x0 |
| 0x0bec 0xbf 0x0 |
| 0x0bf0 0x79 0x0 |
| 0x0bf4 0x4f 0x0 |
| 0x0bf8 0x0f 0x0 |
| 0x0bfc 0xd5 0x0 |
| 0x0aac 0x7f 0x0 |
| 0x0b10 0x55 0x0 |
| 0x0b34 0x0c 0x0 |
| 0x0b38 0x00 0x0 |
| 0x0b50 0x0f 0x0 |
| 0x161c 0xc1 0x0 |
| 0x1690 0x00 0x0 |
| 0x13e4 0x03 0x0 |
| 0x1708 0x03 0x0 |
| 0x16a0 0x16 0x0 |
| 0x13e0 0x16 0x0 |
| 0x13d8 0x01 0x0 |
| 0x16fc 0x01 0x0 |
| 0x13dc 0x00 0x0 |
| 0x1700 0x00 0x0 |
| 0x1828 0x50 0x0 |
| 0x1c28 0x50 0x0 |
| 0x1200 0x00 0x0 |
| 0x1244 0x03 0x0>; |
| |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pcie0_clkreq_default |
| &pcie0_perst_default |
| &pcie0_wake_default>; |
| pinctrl-1 = <&pcie0_clkreq_sleep |
| &pcie0_perst_default |
| &pcie0_wake_default>; |
| |
| perst-gpio = <&tlmm 57 0>; |
| wake-gpio = <&tlmm 53 0>; |
| |
| gdsc-vdd-supply = <&gdsc_pcie>; |
| vreg-1.8-supply = <&pmxprairie_l1>; |
| vreg-0.9-supply = <&pmxprairie_l4>; |
| vreg-cx-supply = <&VDD_CX_LEVEL>; |
| |
| qcom,vreg-1.8-voltage-level = <1200000 1200000 15000>; |
| qcom,vreg-0.9-voltage-level = <872000 872000 47900>; |
| qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX |
| RPMH_REGULATOR_LEVEL_NOM 0>; |
| |
| msi-parent = <&pcie0_msi>; |
| |
| qcom,no-l0s-supported; |
| |
| qcom,ep-latency = <10>; |
| |
| qcom,slv-addr-space-size = <0x40000000>; |
| |
| qcom,pcie-phy-ver = <0x1096>; |
| qcom,use-19p2mhz-aux-clk; |
| qcom,phy-status-offset = <0x1214>; |
| qcom,phy-status-bit = <7>; |
| qcom,phy-power-down-offset = <0x1240>; |
| |
| qcom,boot-option = <0x1>; |
| |
| linux,pci-domain = <0>; |
| |
| qcom,smmu-sid-base = <0x0200>; |
| iommu-map = <0x0 &apps_smmu 0x0200 0x1>, |
| <0x100 &apps_smmu 0x0201 0x1>, |
| <0x200 &apps_smmu 0x0202 0x1>, |
| <0x300 &apps_smmu 0x0203 0x1>, |
| <0x400 &apps_smmu 0x0204 0x1>; |
| |
| qcom,msm-bus,name = "pcie0"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <45 512 0 0>, |
| <45 512 500 800>; |
| |
| clocks = <&clock_gcc GCC_PCIE_PIPE_CLK>, |
| <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_PCIE_AUX_CLK>, |
| <&clock_gcc GCC_PCIE_CFG_AHB_CLK>, |
| <&clock_gcc GCC_PCIE_MSTR_AXI_CLK>, |
| <&clock_gcc GCC_PCIE_SLV_AXI_CLK>, |
| <&clock_gcc GCC_PCIE_0_CLKREF_CLK>, |
| <&clock_gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, |
| <&clock_gcc GCC_PCIE_SLEEP_CLK>, |
| <&clock_gcc GCC_PCIE_RCHNG_PHY_CLK>; |
| |
| clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", |
| "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", |
| "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk", |
| "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk", |
| "pcie_0_sleep_clk", "pcie_phy_refgen_clk"; |
| |
| max-clock-frequency-hz = <0>, <0>, <0>, <0>, <0>, <0>, |
| <0>, <0>, <0>, <0>, <100000000>; |
| |
| resets = <&clock_gcc GCC_PCIE_BCR>, |
| <&clock_gcc GCC_PCIE_PHY_BCR>; |
| |
| reset-names = "pcie_0_core_reset", |
| "pcie_0_phy_reset"; |
| |
| pcie0_rp: pcie0_rp { |
| reg = <0 0 0 0 0>; |
| pci-ids = "17cb:010c"; |
| |
| /* BDF 1.0.0 */ |
| pcie0_bus1_dev0_fn0: pcie0_bus1_dev0_fn0 { |
| reg = <0 0 0 0 0>; |
| pci-ids = "12d8:b304"; |
| |
| /* BDF 2.1.0 */ |
| pcie0_bus2_dev1_fn0: pcie0_bus2_dev1_fn0 { |
| reg = <0x800 0 0 0 0>; |
| pci-ids = "12d8:b304"; |
| }; |
| |
| /* BDF 2.2.0 */ |
| pcie0_bus2_dev2_fn0: pcie0_bus2_dev2_fn0 { |
| reg = <0x1000 0 0 0 0>; |
| pci-ids = "12d8:b304"; |
| }; |
| }; |
| }; |
| }; |
| |
| pcie0_msi: qcom,pcie0_msi@a0000000 { |
| compatible = "qcom,pci-msi"; |
| msi-controller; |
| reg = <0xa0000000 0x0>; |
| interrupt-parent = <&intc>; |
| interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,snps; |
| }; |
| }; |
