| /* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "skeleton64.dtsi" |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/clock/qcom,gcc-sdmshrike.h> |
| #include <dt-bindings/clock/qcom,npucc-sm8150.h> |
| #include <dt-bindings/clock/qcom,dispcc-sm8150.h> |
| #include <dt-bindings/clock/qcom,scc-sm8150.h> |
| #include <dt-bindings/clock/qcom,cpucc-sm8150.h> |
| #include <dt-bindings/clock/qcom,gpucc-sm8150.h> |
| #include <dt-bindings/clock/qcom,videocc-sm8150.h> |
| #include <dt-bindings/clock/qcom,camcc-sdmshrike.h> |
| #include <dt-bindings/clock/qcom,aop-qmp.h> |
| #include <dt-bindings/regulator/qcom,rpmh-regulator.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/soc/qcom,tcs-mbox.h> |
| #include <dt-bindings/soc/qcom,dcc_v2.h> |
| #include <dt-bindings/msm/msm-bus-ids.h> |
| #include <dt-bindings/spmi/spmi.h> |
| |
| #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) |
| #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;} |
| |
| / { |
| model = "Qualcomm Technologies, Inc. SDMSHRIKE"; |
| compatible = "qcom,sdmshrike"; |
| qcom,msm-name = "SDMSHRIKE"; |
| qcom,msm-id = <340 0x10000>; |
| interrupt-parent = <&pdc>; |
| |
| aliases { |
| ufshc1 = &ufshc_mem; /* Embedded UFS slot */ |
| sdhc2 = &sdhc_2; /* SDC2 SD Card slot */ |
| serial0 = &qupv3_se12_2uart; |
| hsuart0 = &qupv3_se13_4uart; |
| spi0 = &qupv3_se3_spi; |
| i2c0 = &qupv3_se4_i2c; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_0>; |
| sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; |
| qcom,lmh-dcvs = <&lmh_dcvs0>; |
| #cooling-cells = <2>; |
| L2_0: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| |
| L3_0: l3-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x400000>; |
| cache-level = <3>; |
| }; |
| }; |
| |
| L1_I_0: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0xa000>; |
| }; |
| |
| L1_D_0: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0xa000>; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_1>; |
| sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; |
| qcom,lmh-dcvs = <&lmh_dcvs0>; |
| #cooling-cells = <2>; |
| L2_1: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_100: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0xa000>; |
| }; |
| |
| L1_D_100: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0xa000>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_2>; |
| sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; |
| qcom,lmh-dcvs = <&lmh_dcvs0>; |
| #cooling-cells = <2>; |
| L2_2: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_200: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0xa000>; |
| }; |
| |
| L1_D_200: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0xa000>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_3>; |
| sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>; |
| qcom,lmh-dcvs = <&lmh_dcvs0>; |
| #cooling-cells = <2>; |
| L2_3: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x20000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_300: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0xa000>; |
| }; |
| |
| L1_D_300: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0xa000>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1740>; |
| cache-size = <0x20000>; |
| next-level-cache = <&L2_4>; |
| sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; |
| qcom,lmh-dcvs = <&lmh_dcvs1>; |
| #cooling-cells = <2>; |
| L2_4: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x80000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_400: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x14000>; |
| }; |
| |
| L1_D_400: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x14000>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1740>; |
| cache-size = <0x20000>; |
| next-level-cache = <&L2_5>; |
| sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; |
| qcom,lmh-dcvs = <&lmh_dcvs1>; |
| #cooling-cells = <2>; |
| L2_5: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x80000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_500: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x14000>; |
| }; |
| |
| L1_D_500: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x14000>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1740>; |
| cache-size = <0x20000>; |
| next-level-cache = <&L2_6>; |
| sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; |
| qcom,lmh-dcvs = <&lmh_dcvs1>; |
| #cooling-cells = <2>; |
| L2_6: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x80000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_600: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x14000>; |
| }; |
| |
| L1_D_600: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x14000>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1740>; |
| cache-size = <0x20000>; |
| next-level-cache = <&L2_7>; |
| sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>; |
| qcom,lmh-dcvs = <&lmh_dcvs1>; |
| #cooling-cells = <2>; |
| L2_7: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x80000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_700: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x14000>; |
| }; |
| |
| L1_D_700: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x14000>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&CPU4>; |
| }; |
| |
| core1 { |
| cpu = <&CPU5>; |
| }; |
| |
| core2 { |
| cpu = <&CPU6>; |
| }; |
| |
| core3 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| }; |
| |
| energy_costs: energy-costs { |
| compatible = "sched-energy"; |
| |
| CPU_COST_0: core-cost0 { |
| busy-cost-data = < |
| 300000 24 |
| 403200 25 |
| 499200 27 |
| 576000 29 |
| 672000 33 |
| 768000 37 |
| 844800 42 |
| 940800 47 |
| 1036800 54 |
| 1113600 59 |
| 1209600 66 |
| 1305600 73 |
| 1382400 79 |
| 1478400 88 |
| 1555200 96 |
| 1632000 105 |
| 1708800 115 |
| 1785600 128 |
| >; |
| idle-cost-data = < |
| 18 14 12 |
| >; |
| }; |
| |
| CPU_COST_1: core-cost1 { |
| busy-cost-data = < |
| 825600 227 |
| 940800 262 |
| 1056000 302 |
| 1171200 348 |
| 1286400 398 |
| 1401600 451 |
| 1497600 498 |
| 1612800 556 |
| 1708800 606 |
| 1804800 655 |
| 1920000 716 |
| 2016000 766 |
| 2131200 826 |
| 2227200 878 |
| 2323200 933 |
| 2419200 992 |
| 2534400 1075 |
| 2649600 1179 |
| 2745600 1288 |
| 2841600 1427 |
| 2956800 1670 |
| >; |
| idle-cost-data = < |
| 110 90 70 |
| >; |
| }; |
| |
| CLUSTER_COST_0: cluster-cost0 { |
| busy-cost-data = < |
| 300000 3 |
| 403200 4 |
| 499200 4 |
| 576000 4 |
| 672000 5 |
| 768000 5 |
| 844800 6 |
| 940800 7 |
| 1036800 8 |
| 1113600 9 |
| 1209600 10 |
| 1305600 11 |
| 1382400 12 |
| 1478400 13 |
| 1555200 14 |
| 1632000 15 |
| 1708800 16 |
| 1785600 17 |
| >; |
| idle-cost-data = < |
| 3 2 1 |
| >; |
| }; |
| |
| CLUSTER_COST_1: cluster-cost1 { |
| busy-cost-data = < |
| 825600 30 |
| 940800 33 |
| 1056000 36 |
| 1171200 39 |
| 1286400 42 |
| 1401600 46 |
| 1497600 49 |
| 1612800 55 |
| 1708800 67 |
| 1804800 77 |
| 1920000 87 |
| 2016000 100 |
| 2131200 110 |
| 2227200 120 |
| 2323200 128 |
| 2419200 135 |
| 2534400 140 |
| 2649600 147 |
| 2745600 160 |
| 2841600 180 |
| 2956800 197 |
| >; |
| idle-cost-data = < |
| 3 2 1 |
| >; |
| }; |
| }; /* energy-costs */ |
| |
| chosen { |
| bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 cgroup.memory=nokmem,nosocket"; |
| }; |
| |
| cpuss_dump { |
| compatible = "qcom,cpuss-dump"; |
| |
| qcom,l1_i_cache0 { |
| qcom,dump-node = <&L1_I_0>; |
| qcom,dump-id = <0x60>; |
| }; |
| |
| qcom,l1_i_cache1 { |
| qcom,dump-node = <&L1_I_100>; |
| qcom,dump-id = <0x61>; |
| }; |
| |
| qcom,l1_i_cache2 { |
| qcom,dump-node = <&L1_I_200>; |
| qcom,dump-id = <0x62>; |
| }; |
| |
| qcom,l1_i_cache3 { |
| qcom,dump-node = <&L1_I_300>; |
| qcom,dump-id = <0x63>; |
| }; |
| |
| qcom,l1_i_cache100 { |
| qcom,dump-node = <&L1_I_400>; |
| qcom,dump-id = <0x64>; |
| }; |
| |
| qcom,l1_i_cache101 { |
| qcom,dump-node = <&L1_I_500>; |
| qcom,dump-id = <0x65>; |
| }; |
| |
| qcom,l1_i_cache102 { |
| qcom,dump-node = <&L1_I_600>; |
| qcom,dump-id = <0x66>; |
| }; |
| |
| qcom,l1_i_cache103 { |
| qcom,dump-node = <&L1_I_700>; |
| qcom,dump-id = <0x67>; |
| }; |
| |
| qcom,l1_d_cache0 { |
| qcom,dump-node = <&L1_D_0>; |
| qcom,dump-id = <0x80>; |
| }; |
| |
| qcom,l1_d_cache1 { |
| qcom,dump-node = <&L1_D_100>; |
| qcom,dump-id = <0x81>; |
| }; |
| |
| qcom,l1_d_cache2 { |
| qcom,dump-node = <&L1_D_200>; |
| qcom,dump-id = <0x82>; |
| }; |
| |
| qcom,l1_d_cache3 { |
| qcom,dump-node = <&L1_D_300>; |
| qcom,dump-id = <0x83>; |
| }; |
| |
| qcom,l1_d_cache100 { |
| qcom,dump-node = <&L1_D_400>; |
| qcom,dump-id = <0x84>; |
| }; |
| |
| qcom,l1_d_cache101 { |
| qcom,dump-node = <&L1_D_500>; |
| qcom,dump-id = <0x85>; |
| }; |
| |
| qcom,l1_d_cache102 { |
| qcom,dump-node = <&L1_D_600>; |
| qcom,dump-id = <0x86>; |
| }; |
| |
| qcom,l1_d_cache103 { |
| qcom,dump-node = <&L1_D_700>; |
| qcom,dump-id = <0x87>; |
| }; |
| }; |
| |
| firmware: firmware { |
| android { |
| compatible = "android,firmware"; |
| vbmeta { |
| compatible = "android,vbmeta"; |
| parts = "vbmeta,boot,system,vendor,dtbo"; |
| }; |
| fstab { |
| compatible = "android,fstab"; |
| vendor { |
| compatible = "android,vendor"; |
| dev = "/dev/block/platform/soc/8804000.sdhci/by-name/vendor"; |
| type = "ext4"; |
| mnt_flags = "ro,barrier=1,discard"; |
| fsmgr_flags = "wait,slotselect,avb"; |
| status = "ok"; |
| }; |
| }; |
| }; |
| }; |
| |
| reserved_memory: reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| hyp_mem: hyp_mem@85700000 { |
| no-map; |
| reg = <0x0 0x85700000 0x0 0x600000>; |
| }; |
| |
| xbl_aop_mem: xbl_aop_mem@85e00000 { |
| no-map; |
| reg = <0x0 0x85e00000 0x0 0x140000>; |
| }; |
| |
| flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 { |
| no-map; |
| reg = <0x0 0x85ffd000 0x0 0x3000>; |
| }; |
| |
| smem_region: smem@86000000 { |
| no-map; |
| reg = <0x0 0x86000000 0x0 0x200000>; |
| }; |
| |
| removed_regions: removed_regions@86200000 { |
| no-map; |
| reg = <0x0 0x86200000 0x0 0x5500000>; |
| }; |
| |
| pil_camera_mem: camera_region@8b700000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x8b700000 0x0 0x500000>; |
| }; |
| |
| pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x8bc00000 0x0 0x180000>; |
| }; |
| |
| pil_npu_mem: pil_npu_region@0x8bd80000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x8bd80000 0x0 0x80000>; |
| }; |
| |
| pil_adsp_mem: pil_adsp_region@0x8be00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x8be00000 0x0 0x1a00000>; |
| }; |
| |
| pil_modem_mem: modem_region@0x8d800000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x8d800000 0x0 0x9600000>; |
| }; |
| |
| pil_video_mem: pil_video_region@0x96e00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x96e00000 0x0 0x500000>; |
| }; |
| |
| pil_slpi_mem: pil_slpi_region@0x97300000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x97300000 0x0 0x1400000>; |
| }; |
| |
| pil_ipa_fw_mem: pil_ipa_fw_region@0x98700000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x98700000 0x0 0x10000>; |
| }; |
| |
| pil_ipa_gsi_mem: pil_ipa_gsi_region@0x98710000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x98710000 0x0 0x5000>; |
| }; |
| |
| pil_gpu_mem: pil_gpu_region@0x98715000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x98715000 0x0 0x2000>; |
| }; |
| |
| pil_spss_mem: pil_spss_region@0x98800000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x98800000 0x0 0x100000>; |
| }; |
| |
| pil_cdsp_mem: cdsp_regions@0x98900000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x98900000 0x0 0x1400000>; |
| }; |
| |
| qseecom_mem: qseecom_region@0x9e400000 { |
| compatible = "shared-dma-pool"; |
| no-map; |
| reg = <0x0 0x9e400000 0x0 0x1400000>; |
| }; |
| |
| |
| cont_splash_memory: cont_splash_region@0x9c000000 { |
| reg = <0x0 0x9c000000 0x0 0x02400000>; |
| label = "cont_splash_region"; |
| }; |
| |
| disp_rdump_memory: disp_rdump_region@0x9c000000 { |
| reg = <0x0 0x9c000000 0x0 0x02400000>; |
| label = "disp_rdump_region"; |
| }; |
| |
| adsp_mem: adsp_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x1000000>; |
| }; |
| |
| cdsp_mem: cdsp_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x400000>; |
| }; |
| |
| user_contig_mem: user_contig_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x1000000>; |
| }; |
| |
| qseecom_ta_mem: qseecom_ta_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x1000000>; |
| }; |
| |
| sp_mem: sp_region { /* SPSS-HLOS ION shared mem */ |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x800000>; |
| }; |
| |
| secure_display_memory: secure_display_region { /* Secure UI */ |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0xA000000>; |
| }; |
| |
| dump_mem: mem_dump_region { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0 0x2400000>; |
| }; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x2800000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| vendor: vendor { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| }; |
| |
| soc: soc { }; |
| |
| }; |
| |
| #include "sdmshrike-gdsc.dtsi" |
| #include "sdmshrike-sde-pll.dtsi" |
| #include "sdmshrike-sde.dtsi" |
| |
| &soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| reg = <0x17a00000 0x10000>, /* GICD */ |
| <0x17a60000 0x100000>; /* GICR * 8 */ |
| interrupts = <1 9 4>; |
| interrupt-parent = <&intc>; |
| }; |
| |
| spss_utils: qcom,spss_utils { |
| compatible = "qcom,spss-utils"; |
| /* spss fuses physical address */ |
| qcom,spss-fuse1-addr = <0x007841c4>; |
| qcom,spss-fuse1-bit = <27>; |
| qcom,spss-fuse2-addr = <0x007841c4>; |
| qcom,spss-fuse2-bit = <26>; |
| qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */ |
| qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */ |
| qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */ |
| qcom,spss-debug-reg-addr = <0x01886020>; |
| qcom,spss-emul-type-reg-addr = <0x01fc8004>; |
| status = "ok"; |
| }; |
| |
| qcom,spcom { |
| compatible = "qcom,spcom"; |
| |
| /* predefined channels, remote side is server */ |
| qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; |
| status = "ok"; |
| }; |
| |
| sdhc_2: sdhci@8804000 { |
| compatible = "qcom,sdhci-msm-v5"; |
| reg = <0x8804000 0x1000>; |
| reg-names = "hc_mem"; |
| |
| interrupts = <0 204 0>, <0 222 0>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| qcom,bus-width = <4>; |
| qcom,large-address-bus; |
| |
| qcom,clk-rates = <400000 20000000 25000000 |
| 50000000 100000000 200000000>; |
| qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", |
| "SDR104"; |
| |
| qcom,devfreq,freq-table = <50000000 200000000>; |
| |
| qcom,msm-bus,name = "sdhc2"; |
| qcom,msm-bus,num-cases = <8>; |
| qcom,msm-bus,num-paths = <2>; |
| qcom,msm-bus,vectors-KBps = |
| /* No vote */ |
| <81 512 0 0>, <1 608 0 0>, |
| /* 400 KB/s*/ |
| <81 512 1046 1600>, |
| <1 608 1600 1600>, |
| /* 20 MB/s */ |
| <81 512 52286 80000>, |
| <1 608 80000 80000>, |
| /* 25 MB/s */ |
| <81 512 65360 100000>, |
| <1 608 100000 100000>, |
| /* 50 MB/s */ |
| <81 512 130718 200000>, |
| <1 608 100000 100000>, |
| /* 100 MB/s */ |
| <81 512 261438 200000>, |
| <1 608 130000 130000>, |
| /* 200 MB/s */ |
| <81 512 261438 400000>, |
| <1 608 300000 300000>, |
| /* Max. bandwidth */ |
| <81 512 1338562 4096000>, |
| <1 608 1338562 4096000>; |
| qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 100000000 200000000 4294967295>; |
| |
| qcom,restore-after-cx-collapse; |
| |
| /* PM QoS */ |
| qcom,pm-qos-irq-type = "affine_irq"; |
| qcom,pm-qos-irq-latency = <70 70>; |
| qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| qcom,pm-qos-legacy-latency-us = <70 70>, <70 70>; |
| |
| clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, |
| <&clock_gcc GCC_SDCC2_APPS_CLK>; |
| clock-names = "iface_clk", "core_clk"; |
| |
| status = "disabled"; |
| }; |
| |
| pdc: interrupt-controller@0xb220000{ |
| compatible = "qcom,pdc-sm8150"; |
| reg = <0xb220000 0x400>; |
| #interrupt-cells = <3>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 1 0xf08>, |
| <1 2 0xf08>, |
| <1 3 0xf08>, |
| <1 0 0xf08>; |
| clock-frequency = <19200000>; |
| }; |
| |
| timer@0x17c20000{ |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x17c20000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@0x17c21000 { |
| frame-number = <0>; |
| interrupts = <0 7 0x4>, |
| <0 6 0x4>; |
| reg = <0x17c21000 0x1000>, |
| <0x17c22000 0x1000>; |
| }; |
| |
| frame@17c23000 { |
| frame-number = <1>; |
| interrupts = <0 8 0x4>; |
| reg = <0x17c23000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c25000 { |
| frame-number = <2>; |
| interrupts = <0 9 0x4>; |
| reg = <0x17c25000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c27000 { |
| frame-number = <3>; |
| interrupts = <0 10 0x4>; |
| reg = <0x17c26000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c29000 { |
| frame-number = <4>; |
| interrupts = <0 11 0x4>; |
| reg = <0x17c29000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c2b000 { |
| frame-number = <5>; |
| interrupts = <0 12 0x4>; |
| reg = <0x17c2b000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c2d000 { |
| frame-number = <6>; |
| interrupts = <0 13 0x4>; |
| reg = <0x17c2d000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| llcc_pmu: llcc-pmu@90cc000 { |
| compatible = "qcom,qcom-llcc-pmu"; |
| reg = <0x090cc000 0x300>, <0x09648000 0x200>; |
| reg-names = "lagg-base", "beac-base"; |
| }; |
| |
| llcc_bw_opp_table: llcc-bw-opp-table { |
| compatible = "operating-points-v2"; |
| BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */ |
| BW_OPP_ENTRY( 200, 16); /* 3051 MB/s */ |
| BW_OPP_ENTRY( 403, 16); /* 6149 MB/s */ |
| BW_OPP_ENTRY( 533, 16); /* 8132 MB/s */ |
| BW_OPP_ENTRY( 666, 16); /* 10162 MB/s */ |
| BW_OPP_ENTRY( 777, 16); /* 11856 MB/s */ |
| }; |
| |
| cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw { |
| compatible = "qcom,devbw"; |
| governor = "performance"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>; |
| qcom,active-only; |
| operating-points-v2 = <&llcc_bw_opp_table>; |
| }; |
| |
| cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 { |
| compatible = "qcom,bimc-bwmon4"; |
| reg = <0x90b6400 0x300>, <0x90b6300 0x200>; |
| reg-names = "base", "global_base"; |
| interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,mport = <0>; |
| qcom,hw-timer-hz = <19200000>; |
| qcom,target-dev = <&cpu_cpu_llcc_bw>; |
| qcom,count-unit = <0x10000>; |
| }; |
| |
| ddr_bw_opp_table: ddr-bw-opp-table { |
| compatible = "operating-points-v2"; |
| BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ |
| BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ |
| BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */ |
| BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ |
| BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ |
| BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ |
| BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ |
| BW_OPP_ENTRY(1296, 4); /* 4943 MB/s */ |
| BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ |
| BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ |
| BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */ |
| }; |
| |
| cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw { |
| compatible = "qcom,devbw"; |
| governor = "performance"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&ddr_bw_opp_table>; |
| }; |
| |
| cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 { |
| compatible = "qcom,bimc-bwmon5"; |
| reg = <0x90cd000 0x1000>; |
| reg-names = "base"; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,hw-timer-hz = <19200000>; |
| qcom,target-dev = <&cpu_llcc_ddr_bw>; |
| qcom,count-unit = <0x10000>; |
| }; |
| |
| cdsp_cdsp_l3_lat: qcom,cdsp-cdsp-l3-lat { |
| compatible = "devfreq-simple-dev"; |
| clock-names = "devfreq_clk"; |
| clocks = <&clock_cpucc L3_MISC_VOTE_CLK>; |
| governor = "powersave"; |
| }; |
| |
| cpu0_cpu_l3_lat: qcom,cpu0-cpu-l3-lat { |
| compatible = "devfreq-simple-dev"; |
| clock-names = "devfreq_clk"; |
| clocks = <&clock_cpucc L3_CLUSTER0_VOTE_CLK>; |
| governor = "performance"; |
| }; |
| |
| cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon { |
| compatible = "qcom,arm-memlat-mon"; |
| qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| qcom,target-dev = <&cpu0_cpu_l3_lat>; |
| qcom,cachemiss-ev = <0x17>; |
| qcom,core-dev-table = |
| < 300000 300000000 >, |
| < 576000 576000000 >, |
| < 672000 768000000 >, |
| < 864000 960000000 >, |
| < 1171200 1228800000 >, |
| < 1267200 1344000000 >; |
| }; |
| |
| cpu4_cpu_l3_lat: qcom,cpu4-cpu-l3-lat { |
| compatible = "devfreq-simple-dev"; |
| clock-names = "devfreq_clk"; |
| clocks = <&clock_cpucc L3_CLUSTER1_VOTE_CLK>; |
| governor = "performance"; |
| }; |
| |
| cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon { |
| compatible = "qcom,arm-memlat-mon"; |
| qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| qcom,target-dev = <&cpu4_cpu_l3_lat>; |
| qcom,cachemiss-ev = <0x17>; |
| qcom,core-dev-table = |
| < 300000 300000000 >, |
| < 576000 576000000 >, |
| < 768000 768000000 >, |
| < 960000 960000000 >, |
| < 1248000 1228800000 >, |
| < 1593600 1344000000 >; |
| }; |
| |
| cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat { |
| compatible = "qcom,devbw"; |
| governor = "performance"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>; |
| qcom,active-only; |
| operating-points-v2 = <&llcc_bw_opp_table>; |
| }; |
| |
| cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon { |
| compatible = "qcom,arm-memlat-mon"; |
| qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| qcom,target-dev = <&cpu0_cpu_llcc_lat>; |
| qcom,cachemiss-ev = <0x2A>; |
| qcom,core-dev-table = |
| < 300000 MHZ_TO_MBPS(150, 16) >, |
| < 576000 MHZ_TO_MBPS(200, 16) >, |
| < 672000 MHZ_TO_MBPS(403, 16) >, |
| < 864000 MHZ_TO_MBPS(533, 16) >, |
| < 1171200 MHZ_TO_MBPS(666, 16) >, |
| < 1267200 MHZ_TO_MBPS(777, 16) >; |
| }; |
| |
| cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat { |
| compatible = "qcom,devbw"; |
| governor = "performance"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>; |
| qcom,active-only; |
| operating-points-v2 = <&llcc_bw_opp_table>; |
| }; |
| |
| cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon { |
| compatible = "qcom,arm-memlat-mon"; |
| qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| qcom,target-dev = <&cpu4_cpu_llcc_lat>; |
| qcom,cachemiss-ev = <0x2A>; |
| qcom,core-dev-table = |
| < 300000 MHZ_TO_MBPS(150, 16) >, |
| < 576000 MHZ_TO_MBPS(200, 16) >, |
| < 768000 MHZ_TO_MBPS(403, 16) >, |
| < 960000 MHZ_TO_MBPS(533, 16) >, |
| < 1248000 MHZ_TO_MBPS(666, 16) >, |
| < 1593600 MHZ_TO_MBPS(777, 16) >; |
| }; |
| |
| cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat { |
| compatible = "qcom,devbw"; |
| governor = "performance"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&ddr_bw_opp_table>; |
| }; |
| |
| cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon { |
| compatible = "qcom,arm-memlat-mon"; |
| qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| qcom,target-dev = <&cpu0_llcc_ddr_lat>; |
| qcom,cachemiss-ev = <0x1000>; |
| qcom,core-dev-table = |
| < 300000 MHZ_TO_MBPS( 200, 4) >, |
| < 576000 MHZ_TO_MBPS( 451, 4) >, |
| < 672000 MHZ_TO_MBPS( 768, 4) >, |
| < 864000 MHZ_TO_MBPS(1017, 4) >, |
| < 1171200 MHZ_TO_MBPS(1555, 4) >, |
| < 1267200 MHZ_TO_MBPS(1804, 4) >; |
| }; |
| |
| cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat { |
| compatible = "qcom,devbw"; |
| governor = "performance"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&ddr_bw_opp_table>; |
| }; |
| |
| cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { |
| compatible = "qcom,arm-memlat-mon"; |
| qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| qcom,target-dev = <&cpu4_llcc_ddr_lat>; |
| qcom,cachemiss-ev = <0x1000>; |
| qcom,core-dev-table = |
| < 300000 MHZ_TO_MBPS( 200, 4) >, |
| < 576000 MHZ_TO_MBPS( 451, 4) >, |
| < 768000 MHZ_TO_MBPS( 768, 4) >, |
| < 960000 MHZ_TO_MBPS(1017, 4) >, |
| < 1248000 MHZ_TO_MBPS(1555, 4) >, |
| < 1593600 MHZ_TO_MBPS(1804, 4) >, |
| < 1689600 MHZ_TO_MBPS(2092, 4) >; |
| }; |
| |
| cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { |
| compatible = "qcom,devbw"; |
| governor = "performance"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&ddr_bw_opp_table>; |
| }; |
| |
| cpu4_computemon: qcom,cpu4-computemon { |
| compatible = "qcom,arm-cpu-mon"; |
| qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; |
| qcom,core-dev-table = |
| < 1593600 MHZ_TO_MBPS( 200, 4) >, |
| < 2016000 MHZ_TO_MBPS(1017, 4) >, |
| < 2054400 MHZ_TO_MBPS(2092, 4) >; |
| }; |
| |
| cpu_pmu: cpu-pmu { |
| compatible = "arm,armv8-pmuv3"; |
| qcom,irq-is-percpu; |
| interrupts = <1 5 4>; |
| }; |
| |
| qcom,chd_silver { |
| compatible = "qcom,core-hang-detect"; |
| label = "silver"; |
| qcom,threshold-arr = <0x18000058 0x18010058 |
| 0x18020058 0x18030058>; |
| qcom,config-arr = <0x18000060 0x18010060 |
| 0x18020060 0x18030060>; |
| }; |
| |
| qcom,chd_gold { |
| compatible = "qcom,core-hang-detect"; |
| label = "gold"; |
| qcom,threshold-arr = <0x18040058 0x18050058 |
| 0x18060058 0x18070058>; |
| qcom,config-arr = <0x18040060 0x18050060 |
| 0x18060060 0x18070060>; |
| }; |
| |
| qcom,ghd { |
| compatible = "qcom,gladiator-hang-detect-v3"; |
| qcom,threshold-arr = <0x17e0041C>; |
| qcom,config-reg = <0x17e00434>; |
| }; |
| |
| kryo-erp { |
| compatible = "arm,arm64-kryo-cpu-erp"; |
| interrupts = <1 6 4>, |
| <1 7 4>, |
| <0 34 4>, |
| <0 35 4>; |
| |
| interrupt-names = "l1-l2-faultirq", |
| "l1-l2-errirq", |
| "l3-scu-errirq", |
| "l3-scu-faultirq"; |
| }; |
| |
| qcom,llcc@9200000 { |
| compatible = "qcom,llcc-core", "syscon", "simple-mfd"; |
| reg = <0x9200000 0x450000>; |
| reg-names = "llcc_base"; |
| qcom,llcc-banks-off = <0x0 0x80000 0x100000 0x180000 |
| 0x200000 0x280000 0x300000 0x380000>; |
| qcom,llcc-broadcast-off = <0x400000>; |
| |
| llcc: qcom,sdmshrike-llcc { |
| compatible = "qcom,sdmshrike-llcc"; |
| #cache-cells = <1>; |
| max-slices = <32>; |
| }; |
| |
| qcom,llcc-erp { |
| compatible = "qcom,llcc-erp"; |
| }; |
| |
| qcom,llcc-amon { |
| compatible = "qcom,llcc-amon"; |
| }; |
| }; |
| |
| qmp_aop: qcom,qmp-aop@c300000 { |
| compatible = "qcom,qmp-mbox"; |
| reg = <0xc300000 0x1000>, <0x17c0000C 0x4>; |
| reg-names = "msgram", "irq-reg-base"; |
| qcom,irq-mask = <0x1>; |
| interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "aop"; |
| qcom,early-boot; |
| priority = <0>; |
| mbox-desc-offset = <0x0>; |
| #mbox-cells = <1>; |
| }; |
| |
| tcsr_mutex_block: syscon@1f40000 { |
| compatible = "syscon"; |
| reg = <0x1f40000 0x20000>; |
| }; |
| |
| tcsr_mutex: qcom,hwlock { |
| compatible = "qcom,tcsr-mutex"; |
| syscon = <&tcsr_mutex_block 0 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| smem: qcom,smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_region>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| apcs: syscon@17c0000c { |
| compatible = "syscon"; |
| reg = <0x17c0000c 0x4>; |
| }; |
| |
| apcs_glb: mailbox@17c00000 { |
| compatible = "qcom,sm8150-apcs-hmss-global"; |
| reg = <0x17c00000 0x1000>; |
| |
| #mbox-cells = <1>; |
| }; |
| |
| sp_scsr: mailbox@188501c { |
| compatible = "qcom,sm8150-spcs-global"; |
| reg = <0x188501c 0x4>; |
| |
| #mbox-cells = <1>; |
| }; |
| |
| sp_scsr_block: syscon@1880000 { |
| compatible = "syscon"; |
| reg = <0x1880000 0x10000>; |
| }; |
| |
| intsp: qcom,qsee_irq { |
| compatible = "qcom,sm8150-qsee-irq"; |
| |
| syscon = <&sp_scsr_block>; |
| interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, |
| <0 349 IRQ_TYPE_LEVEL_HIGH>; |
| |
| interrupt-names = "sp_ipc0", |
| "sp_ipc1"; |
| |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| }; |
| |
| qcom,qsee_irq_bridge { |
| compatible = "qcom,qsee-ipc-irq-bridge"; |
| |
| qcom,qsee-ipc-irq-spss { |
| qcom,dev-name = "qsee_ipc_irq_spss"; |
| label = "spss"; |
| interrupt-parent = <&intsp>; |
| interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| qcom,glink { |
| compatible = "qcom,glink"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| glink_modem: modem { |
| qcom,remote-pid = <1>; |
| transport = "smem"; |
| mboxes = <&apcs_glb 12>; |
| mbox-names = "mpss_smem"; |
| interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "modem"; |
| qcom,glink-label = "mpss"; |
| |
| qcom,modem_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,msm_fastrpc_rpmsg { |
| compatible = "qcom,msm-fastrpc-rpmsg"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| qcom,intents = <0x64 64>; |
| }; |
| }; |
| |
| glink_adsp: adsp { |
| qcom,remote-pid = <2>; |
| transport = "smem"; |
| mboxes = <&apcs_glb 8>; |
| mbox-names = "adsp_smem"; |
| interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "adsp"; |
| qcom,glink-label = "lpass"; |
| |
| qcom,adsp_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,apr_tal_rpmsg { |
| qcom,glink-channels = "apr_audio_svc"; |
| qcom,intents = <0x200 20>; |
| }; |
| |
| qcom,msm_fastrpc_rpmsg { |
| compatible = "qcom,msm-fastrpc-rpmsg"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| qcom,intents = <0x64 64>; |
| }; |
| }; |
| |
| glink_slpi: dsps { |
| qcom,remote-pid = <3>; |
| transport = "smem"; |
| mboxes = <&apcs_glb 24>; |
| mbox-names = "dsps_smem"; |
| interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "slpi"; |
| qcom,glink-label = "dsps"; |
| |
| qcom,slpi_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,msm_fastrpc_rpmsg { |
| compatible = "qcom,msm-fastrpc-rpmsg"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| qcom,intents = <0x64 64>; |
| }; |
| }; |
| |
| glink_cdsp: cdsp { |
| qcom,remote-pid = <5>; |
| transport = "smem"; |
| mboxes = <&apcs_glb 4>; |
| mbox-names = "cdsp_smem"; |
| interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "cdsp"; |
| qcom,glink-label = "cdsp"; |
| |
| qcom,cdsp_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,msm_fastrpc_rpmsg { |
| compatible = "qcom,msm-fastrpc-rpmsg"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| qcom,intents = <0x64 64>; |
| }; |
| }; |
| |
| glink_spss: spss { |
| qcom,remote-pid = <8>; |
| transport = "spss"; |
| mboxes = <&sp_scsr 0>; |
| mbox-names = "spss_spss"; |
| interrupt-parent = <&intsp>; |
| interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; |
| |
| reg = <0x1885008 0x8>, |
| <0x1885010 0x4>; |
| reg-names = "qcom,spss-addr", |
| "qcom,spss-size"; |
| |
| label = "spss"; |
| qcom,glink-label = "spss"; |
| |
| qcom,spss_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_modem>; |
| }; |
| }; |
| |
| glink_spi_xprt_wdsp: wdsp { |
| qcom,remote-pid = <10>; |
| transport = "spi"; |
| tx-descriptors = <0x12000 0x12004>; |
| rx-descriptors = <0x1200c 0x12010>; |
| |
| label = "wdsp"; |
| qcom,glink-label = "wdsp"; |
| }; |
| }; |
| |
| qcom,glinkpkt { |
| compatible = "qcom,glinkpkt"; |
| |
| qcom,glinkpkt-at-mdm0 { |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DS"; |
| qcom,glinkpkt-dev-name = "at_mdm0"; |
| }; |
| |
| qcom,glinkpkt-apr-apps2 { |
| qcom,glinkpkt-edge = "adsp"; |
| qcom,glinkpkt-ch-name = "apr_apps2"; |
| qcom,glinkpkt-dev-name = "apr_apps2"; |
| }; |
| |
| qcom,glinkpkt-data40-cntl { |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA40_CNTL"; |
| qcom,glinkpkt-dev-name = "smdcntl8"; |
| }; |
| |
| qcom,glinkpkt-data1 { |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA1"; |
| qcom,glinkpkt-dev-name = "smd7"; |
| }; |
| |
| qcom,glinkpkt-data4 { |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA4"; |
| qcom,glinkpkt-dev-name = "smd8"; |
| }; |
| |
| qcom,glinkpkt-data11 { |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA11"; |
| qcom,glinkpkt-dev-name = "smd11"; |
| }; |
| }; |
| |
| slim_aud: slim@171c0000 { |
| cell-index = <1>; |
| compatible = "qcom,slim-ngd"; |
| reg = <0x171c0000 0x2c000>, |
| <0x17184000 0x2c000>; |
| reg-names = "slimbus_physical", "slimbus_bam_physical"; |
| interrupts = <0 163 0>, <0 164 0>; |
| interrupt-names = "slimbus_irq", "slimbus_bam_irq"; |
| qcom,apps-ch-pipes = <0x780000>; |
| qcom,ea-pc = <0x2b0>; |
| qcom,iommu-s1-bypass; |
| |
| iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb { |
| compatible = "qcom,iommu-slim-ctrl-cb"; |
| iommus = <&apps_smmu 0x1b46 0x8>, |
| <&apps_smmu 0x1b4d 0x2>, |
| <&apps_smmu 0x1b50 0x1>; |
| }; |
| }; |
| |
| spmi_bus: qcom,spmi@c440000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0xc440000 0x1100>, |
| <0xc600000 0x2000000>, |
| <0xe600000 0x100000>, |
| <0xe700000 0xa0000>, |
| <0xc40a000 0x26000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| cell-index = <0>; |
| }; |
| |
| thermal_zones: thermal-zones { |
| }; |
| |
| cmd_db: qcom,cmd-db@c3f000c { |
| compatible = "qcom,cmd-db"; |
| reg = <0xc3f000c 8>; |
| }; |
| |
| apps_rsc: mailbox@18220000 { |
| compatible = "qcom,tcs-drv"; |
| label = "apps_rsc"; |
| reg = <0x18220000 0x100>, <0x18220d00 0x3000>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <1>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, |
| <SLEEP_TCS 3>, |
| <WAKE_TCS 3>, |
| <CONTROL_TCS 1>; |
| }; |
| |
| disp_rsc: mailbox@af20000 { |
| status = "disabled"; |
| compatible = "qcom,tcs-drv"; |
| label = "display_rsc"; |
| reg = <0xaf20000 0x100>, <0xaf21c00 0x3000>; |
| interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; |
| #mbox-cells = <1>; |
| qcom,drv-id = <0>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, |
| <SLEEP_TCS 1>, |
| <WAKE_TCS 1>, |
| <CONTROL_TCS 0>; |
| }; |
| |
| keepalive_opp_table: keepalive-opp-table { |
| compatible = "operating-points-v2"; |
| opp-1 { |
| opp-hz = /bits/ 64 < 1 >; |
| }; |
| }; |
| |
| snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive { |
| compatible = "qcom,devbw"; |
| governor = "powersave"; |
| qcom,src-dst-ports = <1 627>; |
| qcom,active-only; |
| status = "ok"; |
| operating-points-v2 = <&keepalive_opp_table>; |
| }; |
| |
| cdsp_keepalive: qcom,cdsp_keepalive { |
| compatible = "qcom,devbw"; |
| governor = "powersave"; |
| qcom,src-dst-ports = <154 10070>; |
| qcom,active-only; |
| status = "ok"; |
| operating-points-v2 = <&keepalive_opp_table>; |
| }; |
| |
| clock_rpmh: qcom,rpmhclk { |
| compatible = "qcom,rpmh-clk-sdmshrike"; |
| mboxes = <&apps_rsc 0>; |
| mbox-names = "apps"; |
| #clock-cells = <1>; |
| }; |
| |
| clock_gcc: qcom,gcc@100000 { |
| compatible = "qcom,gcc-sdmshrike", "syscon"; |
| reg = <0x100000 0x1f0000>; |
| reg-names = "cc_base"; |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; |
| vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_videocc: qcom,videocc@ab00000 { |
| compatible = "qcom,videocc-sm8150-v2", "syscon"; |
| reg = <0xab00000 0x10000>; |
| reg-names = "cc_base"; |
| vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| clock-names = "cfg_ahb_clk"; |
| clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_npucc: qcom,npucc@9910000 { |
| compatible = "qcom,npucc-sm8150"; |
| reg = <0x9910000 0x10000>; |
| reg-names = "cc_base"; |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| vdd_gdsc-supply = <&npu_core_gdsc>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_dispcc: qcom,dispcc@af00000 { |
| compatible = "qcom,dispcc-sm8150", "syscon"; |
| reg = <0xaf00000 0x20000>; |
| reg-names = "cc_base"; |
| vdd_mm-supply = <&VDD_MMCX_LEVEL>; |
| clock-names = "cfg_ahb_clk"; |
| clocks = <&clock_gcc GCC_DISP_AHB_CLK>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_camcc: qcom,camcc@ad00000 { |
| compatible = "qcom,camcc-sdmshrike", "syscon"; |
| reg = <0xad00000 0x20000>; |
| reg-names = "cc_base"; |
| vdd_mx-supply = <&pm8150c_s3_level>; |
| vdd_mm-supply = <&pm8150c_s1_level>; |
| clock-names = "cfg_ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| #clock-cells = <1>; |
| }; |
| |
| clock_cpucc: qcom,cpucc@18321000 { |
| compatible = "qcom,clk-cpu-osm-sdmshrike"; |
| reg = <0x18321000 0x1400>, |
| <0x18323000 0x1400>, |
| <0x18325800 0x1400>; |
| reg-names = "osm_l3_base", "osm_pwrcl_base", |
| "osm_perfcl_base"; |
| l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat>; |
| #clock-cells = <1>; |
| }; |
| |
| clock_gpucc: qcom,gpucc@2c90000 { |
| compatible = "qcom,gpucc-sdmshrike", "syscon"; |
| reg = <0x2c90000 0x9000>; |
| reg-names = "cc_base"; |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| vdd_mx-supply = <&VDD_MX_LEVEL>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_scc: qcom,scc@2b10000 { |
| compatible = "qcom,scc-sm8150-v2"; |
| reg = <0x2b10000 0x30000>; |
| #clock-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| cpucc_debug: syscon@182a0018 { |
| compatible = "syscon"; |
| reg = <0x182a0018 0x4>; |
| }; |
| |
| mccc_debug: syscon@90b0000 { |
| compatible = "syscon"; |
| reg = <0x90b0000 0x1000>; |
| }; |
| |
| clock_debugcc: qcom,cc-debug { |
| compatible = "qcom,debugcc-sdmshrike"; |
| qcom,gcc = <&clock_gcc>; |
| qcom,videocc = <&clock_videocc>; |
| qcom,camcc = <&clock_camcc>; |
| qcom,dispcc = <&clock_dispcc>; |
| qcom,gpucc = <&clock_gpucc>; |
| qcom,cpucc = <&cpucc_debug>; |
| qcom,npucc = <&clock_npucc>; |
| qcom,mccc = <&mccc_debug>; |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "cxo"; |
| #clock-cells = <1>; |
| }; |
| |
| tsens0: tsens@c222000 { |
| compatible = "qcom,tsens24xx"; |
| reg = <0xc222000 0x4>, |
| <0xc263000 0x1ff>; |
| reg-names = "tsens_srot_physical", |
| "tsens_tm_physical"; |
| interrupts = <0 506 0>, <0 508 0>; |
| interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| tsens1: tsens@c223000 { |
| compatible = "qcom,tsens24xx"; |
| reg = <0xc223000 0x4>, |
| <0xc265000 0x1ff>; |
| reg-names = "tsens_srot_physical", |
| "tsens_tm_physical"; |
| interrupts = <0 507 0>, <0 509 0>; |
| interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| clock_aop: qcom,aopclk { |
| compatible = "qcom,aop-qmp-clk"; |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "qdss_clk"; |
| #clock-cells = <1>; |
| }; |
| |
| qcom,rmtfs_sharedmem@0 { |
| compatible = "qcom,sharedmem-uio"; |
| reg = <0x0 0x200000>; |
| reg-names = "rmtfs"; |
| qcom,client-id = <0x00000001>; |
| }; |
| |
| pil_lpass: qcom,lpass@17300000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x17300000 0x00100>; |
| |
| vdd_cx-supply = <&pm8150_2_s3_level>; |
| qcom,proxy-reg-names = "vdd_cx"; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <1>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <423>; |
| qcom,sysmon-id = <1>; |
| qcom,ssctl-instance-id = <0x14>; |
| qcom,firmware-name = "adsp"; |
| memory-region = <&pil_adsp_mem>; |
| |
| /* Inputs from lpass */ |
| interrupts-extended = <&pdc 0 162 1>, |
| <&adsp_smp2p_in 0 0>, |
| <&adsp_smp2p_in 2 0>, |
| <&adsp_smp2p_in 1 0>, |
| <&adsp_smp2p_in 3 0>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,proxy-unvote", |
| "qcom,err-ready", |
| "qcom,stop-ack"; |
| |
| /* Outputs to lpass */ |
| qcom,smem-states = <&adsp_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "adsp-pil"; |
| }; |
| |
| pil_ssc: qcom,ssc@5c00000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x5c00000 0x4000>; |
| |
| vdd_cx-supply = <&L8E_LEVEL>; |
| vdd_mx-supply = <&L4E_LEVEL>; |
| |
| qcom,proxy-reg-names = "vdd_cx", "vdd_mx"; |
| qcom,keep-proxy-regs-on; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <12>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <424>; |
| qcom,sysmon-id = <3>; |
| qcom,ssctl-instance-id = <0x16>; |
| qcom,firmware-name = "slpi"; |
| status = "ok"; |
| memory-region = <&pil_slpi_mem>; |
| |
| /* Inputs from ssc */ |
| interrupts-extended = <&pdc 0 494 1>, |
| <&dsps_smp2p_in 0 0>, |
| <&dsps_smp2p_in 2 0>, |
| <&dsps_smp2p_in 1 0>, |
| <&dsps_smp2p_in 3 0>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,proxy-unvote", |
| "qcom,err-ready", |
| "qcom,stop-ack"; |
| |
| /* Outputs to ssc */ |
| qcom,smem-states = <&dsps_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "slpi-pil"; |
| }; |
| |
| pil_spss: qcom,spss@1880000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x188101c 0x4>, |
| <0x1881024 0x4>, |
| <0x1881028 0x4>, |
| <0x188103c 0x4>, |
| <0x1882014 0x4>; |
| reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", |
| "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; |
| interrupts = <0 352 1>; |
| |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| qcom,proxy-reg-names = "vdd_cx"; |
| vdd_mx-supply = <&VDD_MX_LEVEL>; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| qcom,pil-generic-irq-handler; |
| status = "ok"; |
| qcom,signal-aop; |
| qcom,complete-ramdump; |
| |
| qcom,pas-id = <14>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,firmware-name = "spss"; |
| memory-region = <&pil_spss_mem>; |
| qcom,spss-scsr-bits = <24 25>; |
| |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "spss-pil"; |
| }; |
| |
| pil_npu: qcom,npu@0x9800000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x9800000 0x800000>; |
| |
| status = "ok"; |
| qcom,pas-id = <23>; |
| qcom,firmware-name = "npu"; |
| |
| memory-region = <&pil_npu_mem>; |
| }; |
| |
| pil_turing: qcom,turing@8300000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x8300000 0x100000>; |
| |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| qcom,proxy-reg-names = "vdd_cx"; |
| |
| clocks = <&clock_rpmh RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <18>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <601>; |
| qcom,sysmon-id = <7>; |
| qcom,ssctl-instance-id = <0x17>; |
| qcom,firmware-name = "cdsp"; |
| memory-region = <&pil_cdsp_mem>; |
| qcom,signal-aop; |
| qcom,complete-ramdump; |
| |
| qcom,msm-bus,name = "pil-cdsp"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <154 10070 0 0>, |
| <154 10070 0 1>; |
| |
| /* Inputs from turing */ |
| interrupts-extended = <&pdc 0 578 1>, |
| <&cdsp_smp2p_in 0 0>, |
| <&cdsp_smp2p_in 2 0>, |
| <&cdsp_smp2p_in 1 0>, |
| <&cdsp_smp2p_in 3 0>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,proxy-unvote", |
| "qcom,err-ready", |
| "qcom,stop-ack"; |
| |
| /* Outputs to turing */ |
| qcom,smem-states = <&cdsp_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "cdsp-pil"; |
| }; |
| |
| pil_venus: qcom,venus@aae0000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0xaae0000 0x4000>; |
| |
| vdd-supply = <&mvsc_gdsc>; |
| qcom,proxy-reg-names = "vdd"; |
| qcom,complete-ramdump; |
| |
| clocks = <&clock_videocc VIDEO_CC_XO_CLK>, |
| <&clock_videocc VIDEO_CC_MVSC_CORE_CLK>, |
| <&clock_videocc VIDEO_CC_IRIS_AHB_CLK>; |
| clock-names = "xo", "core", "ahb"; |
| qcom,proxy-clock-names = "xo", "core", "ahb"; |
| |
| qcom,core-freq = <200000000>; |
| qcom,ahb-freq = <200000000>; |
| |
| qcom,pas-id = <9>; |
| qcom,msm-bus,name = "pil-venus"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <63 512 0 0>, |
| <63 512 0 304000>; |
| qcom,proxy-timeout-ms = <100>; |
| qcom,firmware-name = "venus"; |
| memory-region = <&pil_video_mem>; |
| }; |
| |
| ssc_sensors: qcom,msm-ssc-sensors { |
| compatible = "qcom,msm-ssc-sensors"; |
| qcom,firmware-name = "slpi"; |
| status = "disabled"; |
| }; |
| |
| wdog: qcom,wdt@17c10000 { |
| compatible = "qcom,msm-watchdog"; |
| reg = <0x17c10000 0x1000>; |
| reg-names = "wdt-base"; |
| interrupts = <0 0 0>, <0 1 0>; |
| qcom,bark-time = <11000>; |
| qcom,pet-time = <9360>; |
| qcom,ipi-ping; |
| qcom,wakeup-enable; |
| }; |
| |
| qcom,msm-imem@146bf000 { |
| compatible = "qcom,msm-imem"; |
| reg = <0x146bf000 0x1000>; |
| ranges = <0x0 0x146bf000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mem_dump_table@10 { |
| compatible = "qcom,msm-imem-mem_dump_table"; |
| reg = <0x10 8>; |
| }; |
| |
| restart_reason@65c { |
| compatible = "qcom,msm-imem-restart_reason"; |
| reg = <0x65c 4>; |
| }; |
| |
| dload_type@1c { |
| compatible = "qcom,msm-imem-dload-type"; |
| reg = <0x1c 0x4>; |
| }; |
| |
| boot_stats@6b0 { |
| compatible = "qcom,msm-imem-boot_stats"; |
| reg = <0x6b0 32>; |
| }; |
| |
| kaslr_offset@6d0 { |
| compatible = "qcom,msm-imem-kaslr_offset"; |
| reg = <0x6d0 12>; |
| }; |
| |
| pil@94c { |
| compatible = "qcom,msm-imem-pil"; |
| reg = <0x94c 200>; |
| }; |
| |
| diag_dload@c8 { |
| compatible = "qcom,msm-imem-diag-dload"; |
| reg = <0xc8 200>; |
| }; |
| }; |
| |
| restart@c264000 { |
| compatible = "qcom,pshold"; |
| reg = <0xc264000 0x4>, |
| <0x1fd3000 0x4>; |
| reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| }; |
| |
| qcom,mpm2-sleep-counter@c221000 { |
| compatible = "qcom,mpm2-sleep-counter"; |
| reg = <0xc221000 0x1000>; |
| clock-frequency = <32768>; |
| }; |
| |
| ufs_ice: ufsice@1d90000 { |
| compatible = "qcom,ice"; |
| reg = <0x1d90000 0x8000>; |
| qcom,enable-ice-clk; |
| clock-names = "ufs_core_clk", |
| "iface_clk", "ice_core_clk"; |
| clocks = <&clock_gcc GCC_UFS_PHY_AXI_CLK>, |
| <&clock_gcc GCC_UFS_PHY_AHB_CLK>, |
| <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>; |
| qcom,op-freq-hz = <0>, <0>, <0>, <300000000>; |
| vdd-hba-supply = <&ufs_phy_gdsc>; |
| qcom,msm-bus,name = "ufs_ice_noc"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <1 650 0 0>, /* No vote */ |
| <1 650 1000 0>; /* Max. bandwidth */ |
| qcom,bus-vector-names = "MIN", |
| "MAX"; |
| qcom,instance-type = "ufs"; |
| }; |
| |
| ufsphy_mem: ufsphy_mem@1d87000 { |
| reg = <0x1d87000 0xda8>; /* PHY regs */ |
| reg-names = "phy_mem"; |
| #phy-cells = <0>; |
| ufs-qcom-crypto = <&ufs_ice>; |
| |
| lanes-per-direction = <2>; |
| |
| clock-names = "ref_clk_src", |
| "ref_aux_clk"; |
| clocks = <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
| |
| status = "disabled"; |
| }; |
| |
| ufshc_mem: ufshc@1d84000 { |
| compatible = "qcom,ufshc"; |
| reg = <0x1d84000 0x2500>; |
| interrupts = <0 265 0>; |
| phys = <&ufsphy_mem>; |
| phy-names = "ufsphy"; |
| ufs-qcom-crypto = <&ufs_ice>; |
| spm-level = <5>; |
| |
| lanes-per-direction = <2>; |
| dev-ref-clk-freq = <0>; /* 19.2 MHz */ |
| |
| clock-names = |
| "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "core_clk_ice", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk", |
| "rx_lane1_sync_clk"; |
| clocks = |
| <&clock_gcc GCC_UFS_PHY_AXI_CLK>, |
| <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| <&clock_gcc GCC_UFS_PHY_AHB_CLK>, |
| <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
| <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>, |
| <&clock_rpmh RPMH_CXO_CLK>, |
| <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
| freq-table-hz = |
| <37500000 300000000>, |
| <0 0>, |
| <0 0>, |
| <37500000 300000000>, |
| <37500000 300000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| |
| qcom,msm-bus,name = "ufshc_mem"; |
| qcom,msm-bus,num-cases = <26>; |
| qcom,msm-bus,num-paths = <2>; |
| qcom,msm-bus,vectors-KBps = |
| /* |
| * During HS G3 UFS runs at nominal voltage corner, vote |
| * higher bandwidth to push other buses in the data path |
| * to run at nominal to achieve max throughput. |
| * 4GBps pushes BIMC to run at nominal. |
| * 200MBps pushes CNOC to run at nominal. |
| * Vote for half of this bandwidth for HS G3 1-lane. |
| * For max bandwidth, vote high enough to push the buses |
| * to run in turbo voltage corner. |
| */ |
| <123 512 0 0>, <1 797 0 0>, /* No vote */ |
| <123 512 922 0>, <1 797 1000 0>, /* PWM G1 */ |
| <123 512 1844 0>, <1 797 1000 0>, /* PWM G2 */ |
| <123 512 3688 0>, <1 797 1000 0>, /* PWM G3 */ |
| <123 512 7376 0>, <1 797 1000 0>, /* PWM G4 */ |
| <123 512 1844 0>, <1 797 1000 0>, /* PWM G1 L2 */ |
| <123 512 3688 0>, <1 797 1000 0>, /* PWM G2 L2 */ |
| <123 512 7376 0>, <1 797 1000 0>, /* PWM G3 L2 */ |
| <123 512 14752 0>, <1 797 1000 0>, /* PWM G4 L2 */ |
| <123 512 127796 0>, <1 797 1000 0>, /* HS G1 RA */ |
| <123 512 255591 0>, <1 797 1000 0>, /* HS G2 RA */ |
| <123 512 2097152 0>, <1 797 102400 0>, /* HS G3 RA */ |
| <123 512 4194304 0>, <1 797 204800 0>, /* HS G4 RA */ |
| <123 512 255591 0>, <1 797 1000 0>, /* HS G1 RA L2 */ |
| <123 512 511181 0>, <1 797 1000 0>, /* HS G2 RA L2 */ |
| <123 512 4194304 0>, <1 797 204800 0>, /* HS G3 RA L2 */ |
| <123 512 8388608 0>, <1 797 409600 0>, /* HS G4 RA L2 */ |
| <123 512 149422 0>, <1 797 1000 0>, /* HS G1 RB */ |
| <123 512 298189 0>, <1 797 1000 0>, /* HS G2 RB */ |
| <123 512 2097152 0>, <1 797 102400 0>, /* HS G3 RB */ |
| <123 512 4194304 0>, <1 797 204800 0>, /* HS G4 RB */ |
| <123 512 298189 0>, <1 797 1000 0>, /* HS G1 RB L2 */ |
| <123 512 596378 0>, <1 797 1000 0>, /* HS G2 RB L2 */ |
| /* As UFS working in HS G3 RB L2 mode, aggregated |
| * bandwidth (AB) should take care of providing |
| * optimum throughput requested. However, as tested, |
| * in order to scale up CNOC clock, instantaneous |
| * bindwidth (IB) needs to be given a proper value too. |
| */ |
| <123 512 4194304 0>, <1 797 204800 409600>, /* HS G3 RB L2 */ |
| <123 512 8388608 0>, <1 797 409600 409600>, /* HS G4 RB L2 */ |
| <123 512 7643136 0>, <1 797 307200 0>; /* Max. bandwidth */ |
| |
| qcom,bus-vector-names = "MIN", |
| "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", |
| "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", |
| "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", |
| "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", |
| "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", |
| "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", |
| "MAX"; |
| |
| /* PM QoS */ |
| qcom,pm-qos-cpu-groups = <0x0f 0xf0>; |
| qcom,pm-qos-cpu-group-latency-us = <44 44>; |
| qcom,pm-qos-default-cpu = <0>; |
| |
| pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; |
| pinctrl-0 = <&ufs_dev_reset_assert>; |
| pinctrl-1 = <&ufs_dev_reset_deassert>; |
| |
| resets = <&clock_gcc GCC_UFS_PHY_BCR>; |
| reset-names = "core_reset"; |
| |
| status = "disabled"; |
| }; |
| |
| qcom,msm-cdsp-loader { |
| compatible = "qcom,cdsp-loader"; |
| qcom,proc-img-to-load = "cdsp"; |
| }; |
| |
| qcom,msm-adsprpc-mem { |
| compatible = "qcom,msm-adsprpc-mem-region"; |
| memory-region = <&adsp_mem>; |
| }; |
| |
| msm_fastrpc: qcom,msm_fastrpc { |
| compatible = "qcom,msm-fastrpc-compute"; |
| qcom,fastrpc-adsp-audio-pdr; |
| qcom,rpc-latency-us = <235>; |
| |
| qcom,msm_fastrpc_compute_cb1 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x1401 0x2040>, |
| <&apps_smmu 0x1421 0x0>, |
| <&apps_smmu 0x2001 0x420>, |
| <&apps_smmu 0x2041 0x0>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb4 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x4 0x3440>, |
| <&apps_smmu 0x24 0x3400>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb5 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x5 0x3440>, |
| <&apps_smmu 0x25 0x3400>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb6 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x6 0x3460>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb7 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x7 0x3460>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb8 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x8 0x3460>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb2 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x2 0x3440>, |
| <&apps_smmu 0x22 0x3400>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb3 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&apps_smmu 0x3 0x3440>, |
| <&apps_smmu 0x1423 0x0>, |
| <&apps_smmu 0x2023 0x0>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb9 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| qcom,secure-context-bank; |
| iommus = <&apps_smmu 0x9 0x3460>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb10 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&apps_smmu 0x1b23 0x0>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb11 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&apps_smmu 0x1b24 0x0>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb12 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&apps_smmu 0x1b25 0x0>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb13 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "sdsprpc-smd"; |
| iommus = <&apps_smmu 0x5a1 0x0>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb14 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "sdsprpc-smd"; |
| iommus = <&apps_smmu 0x5a2 0x0>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb15 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "sdsprpc-smd"; |
| iommus = <&apps_smmu 0x5a3 0x0>; |
| shared-cb = <4>; |
| dma-coherent; |
| }; |
| }; |
| |
| system_pm { |
| compatible = "qcom,system-pm"; |
| mboxes = <&apps_rsc 0>; |
| }; |
| |
| qcom_seecom: qseecom@87900000 { |
| compatible = "qcom,qseecom"; |
| reg = <0x87900000 0x2200000>; |
| reg-names = "secapp-region"; |
| memory-region = <&qseecom_mem>; |
| qcom,hlos-num-ce-hw-instances = <1>; |
| qcom,hlos-ce-hw-instance = <0>; |
| qcom,qsee-ce-hw-instance = <0>; |
| qcom,disk-encrypt-pipe-pair = <2>; |
| qcom,support-fde; |
| qcom,no-clock-support; |
| qcom,fde-key-size; |
| qcom,appsbl-qseecom-support; |
| qcom,commonlib64-loaded-by-uefi; |
| qcom,qsee-reentrancy-support = <2>; |
| }; |
| |
| qcom_smcinvoke: smcinvoke@87900000 { |
| compatible = "qcom,smcinvoke"; |
| reg = <0x87900000 0x2200000>; |
| reg-names = "secapp-region"; |
| }; |
| |
| qcom_rng: qrng@793000 { |
| compatible = "qcom,msm-rng"; |
| reg = <0x793000 0x1000>; |
| qcom,msm-rng-iface-clk; |
| qcom,no-qrng-config; |
| qcom,msm-bus,name = "msm-rng-noc"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <1 618 0 0>, /* No vote */ |
| <1 618 0 300000>; /* 75 MHz */ |
| clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "iface_clk"; |
| }; |
| |
| qcom_msmhdcp: qcom,msm_hdcp { |
| compatible = "qcom,msm-hdcp"; |
| }; |
| |
| mem_dump { |
| compatible = "qcom,mem-dump"; |
| memory-region = <&dump_mem>; |
| |
| rpmh { |
| qcom,dump-size = <0x2000000>; |
| qcom,dump-id = <0xec>; |
| }; |
| |
| rpm_sw { |
| qcom,dump-size = <0x28000>; |
| qcom,dump-id = <0xea>; |
| }; |
| |
| pmic { |
| qcom,dump-size = <0x10000>; |
| qcom,dump-id = <0xe4>; |
| }; |
| |
| fcm { |
| qcom,dump-size = <0x8400>; |
| qcom,dump-id = <0xee>; |
| }; |
| |
| tmc_etf { |
| qcom,dump-size = <0x8000>; |
| qcom,dump-id = <0xf0>; |
| }; |
| |
| etf_swao { |
| qcom,dump-size = <0x8000>; |
| qcom,dump-id = <0xf1>; |
| }; |
| |
| etr_reg { |
| qcom,dump-size = <0x1000>; |
| qcom,dump-id = <0x100>; |
| }; |
| |
| etf_reg { |
| qcom,dump-size = <0x1000>; |
| qcom,dump-id = <0x101>; |
| }; |
| |
| etfswao_reg { |
| qcom,dump-size = <0x1000>; |
| qcom,dump-id = <0x102>; |
| }; |
| |
| misc_data { |
| qcom,dump-size = <0x1000>; |
| qcom,dump-id = <0xe8>; |
| }; |
| }; |
| |
| aop-msg-client { |
| compatible = "qcom,debugfs-qmp-client"; |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "aop"; |
| }; |
| }; |
| |
| &emac_gdsc { |
| status = "ok"; |
| }; |
| |
| &pcie_0_gdsc { |
| status = "ok"; |
| }; |
| |
| &pcie_1_gdsc { |
| status = "ok"; |
| }; |
| |
| &pcie_2_gdsc { |
| status = "ok"; |
| }; |
| |
| &pcie_3_gdsc { |
| status = "ok"; |
| }; |
| |
| &ufs_card_gdsc { |
| status = "ok"; |
| }; |
| |
| &ufs_card_2_gdsc { |
| status = "ok"; |
| }; |
| |
| &ufs_phy_gdsc { |
| status = "ok"; |
| }; |
| |
| &usb30_prim_gdsc { |
| status = "ok"; |
| }; |
| |
| &usb30_sec_gdsc { |
| status = "ok"; |
| }; |
| |
| &usb30_mp_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_tbu1_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_tbu2_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_sf_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_turing_mmu_tbu0_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_turing_mmu_tbu1_gdsc { |
| status = "ok"; |
| }; |
| |
| &bps_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &ipe_0_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &ipe_1_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &ife_0_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &ife_1_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &ife_2_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &ife_3_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &titan_top_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &mdss_core_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_DISP_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| qcom,msm-bus,name = "mdss_core_gdsc_ahb"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_DISPLAY_CFG 0 0>, |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_DISPLAY_CFG 0 1>; |
| status = "ok"; |
| }; |
| |
| &gpu_cx_gdsc { |
| status = "ok"; |
| }; |
| |
| &gpu_gx_gdsc { |
| parent-supply = <&pm8150_1_s10_level>; |
| vdd_parent-supply = <&pm8150_1_s10_level>; |
| status = "ok"; |
| }; |
| |
| &mvsc_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &mvs0_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &mvs1_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; |
| parent-supply = <&VDD_MMCX_LEVEL>; |
| vdd_parent-supply = <&VDD_MMCX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &npu_core_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>; |
| status = "ok"; |
| }; |
| |
| #include "sdmshrike-smp2p.dtsi" |
| #include "sdmshrike-pinctrl.dtsi" |
| #include "sm8150-slpi-pinctrl.dtsi" |
| #include "sdmshrike-regulators.dtsi" |
| #include "sdmshrike-ion.dtsi" |
| #include "sdmshrike-bus.dtsi" |
| #include "msm-arm-smmu-sdmshrike.dtsi" |
| #include "sdmshrike-usb.dtsi" |
| #include "sdmshrike-qupv3.dtsi" |
| #include "sm8150-audio.dtsi" |
| #include "sdmshrike-vidc.dtsi" |
| #include "sdmshrike-pm.dtsi" |
| #include "sdmshrike-gpu.dtsi" |
| #include "sdmshrike-thermal.dtsi" |
