| /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "sm8150-v2.dtsi" |
| #include "sa8155.dtsi" |
| |
| / { |
| model = "Qualcomm Technologies, Inc. SA8155 V2"; |
| qcom,msm-name = "SA8155 V2"; |
| qcom,msm-id = <362 0x20000>; |
| }; |
| |
| &emac_hw { |
| emac-core-version = <4>; |
| early-ethernet-en; |
| }; |
| |
| &ufsphy_mem { |
| vdda-phy-supply = <&pm8150_1_l5>; |
| }; |
| |
| /* GPU frequency overrides */ |
| &soc { |
| gpu_opp_table_v2: gpu_opp_table_v2 { |
| compatible = "operating-points-v2"; |
| |
| opp-700000000 { |
| opp-hz = /bits/ 64 <700000000>; |
| opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>; |
| }; |
| |
| opp-675000000 { |
| opp-hz = /bits/ 64 <675000000>; |
| opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| }; |
| |
| opp-585000000 { |
| opp-hz = /bits/ 64 <585000000>; |
| opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>; |
| }; |
| |
| opp-500000000 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>; |
| }; |
| |
| opp-427000000 { |
| opp-hz = /bits/ 64 <427000000>; |
| opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| }; |
| }; |
| }; |
| |
| /* GPU power level overrides */ |
| &msm_gpu { |
| qcom,initial-pwrlevel = <4>; |
| /delete-node/qcom,gpu-pwrlevel-bins; |
| qcom,gpu-pwrlevels { |
| compatible = "qcom,gpu-pwrlevels"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <700000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <675000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <585000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <11>; |
| }; |
| |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <500000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <6>; |
| qcom,bus-max = <11>; |
| }; |
| |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <427000000>; |
| qcom,bus-freq = <6>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <9>; |
| }; |
| |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| }; |
| |
| &clock_scc { |
| compatible = "qcom,scc-sa8155-v2"; |
| }; |
| |
| &clock_gcc { |
| compatible = "qcom,gcc-sa8155-v2", "syscon"; |
| }; |
| |
| &clock_videocc { |
| compatible = "qcom,videocc-sa8155-v2", "syscon"; |
| }; |
| |
| &clock_npucc { |
| compatible = "qcom,npucc-sa8155-v2", "syscon"; |
| }; |
| |
| &clock_camcc { |
| compatible = "qcom,camcc-sa8155-v2", "syscon"; |
| }; |