| /* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "sm6150.dtsi" |
| #include "sa6155-pmic.dtsi" |
| #include "sa6155-display.dtsi" |
| #include "sm6150-camera-sensor-adp.dtsi" |
| |
| / { |
| model = "Qualcomm Technologies, Inc. SA6155P"; |
| qcom,msm-name = "SA6155P"; |
| qcom,msm-id = <377 0>, <380 0>; |
| |
| aliases { |
| pci-domain0 = &pcie0; /* PCIe0 domain */ |
| }; |
| }; |
| |
| /* Delete second instance of pm6155 definitions for APQ version */ |
| &spmi_bus { |
| /delete-node/ qcom,pm6155@4; |
| /delete-node/ qcom,pm6155@5; |
| }; |
| |
| &soc { |
| /delete-node/ rpmh-regulator-modemlvl; |
| /delete-node/ rpmh-regulator-ldoc2; |
| /delete-node/ rpmh-regulator-ldoc3; |
| /delete-node/ rpmh-regulator-ldoc4; |
| /delete-node/ rpmh-regulator-ldoc13; |
| /delete-node/ rpmh-regulator-ldoc14; |
| /delete-node/ rpmh-regulator-ldoc16; |
| /delete-node/ rpmh-regulator-ldoc17; |
| /delete-node/ rpmh-regulator-ldoc18; |
| /delete-node/ bt_wcn3990; |
| |
| qcom,rmnet-ipa { |
| status="disabled"; |
| }; |
| qfprom: qfprom@780130 { |
| compatible = "qcom,qfprom"; |
| reg = <0x00780130 0x4>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| read-only; |
| ranges; |
| }; |
| }; |
| |
| &ipa_hw { |
| status="disabled"; |
| }; |
| |
| &pil_modem { |
| /delete-property/ vdd_mss-supply; |
| }; |
| |
| &qusb_phy0 { |
| reg = <0x88e2000 0x180>, |
| <0x007801f8 0x4>, |
| <0x01fcb3e4 0x4>; |
| reg-names = "qusb_phy_base", |
| "tune2_efuse_addr", |
| "tcsr_conn_box_spare_0"; |
| vdd-supply = <&L5A>; |
| vdda18-supply = <&L12A>; |
| vdda33-supply = <&L13A>; |
| }; |
| |
| &tpdm_west { |
| status = "disabled"; |
| }; |
| |
| &usb_qmp_phy { |
| vdd-supply = <&L5A>; |
| core-supply = <&L12A>; |
| }; |
| |
| &qusb_phy1 { |
| vdd-supply = <&L5A>; |
| vdda18-supply = <&L12A>; |
| vdda33-supply = <&L13A>; |
| }; |
| |
| &mdss_dsi0_pll { |
| /delete-property/ qcom,dsi-pll-ssc-en; |
| }; |
| |
| &slpi_tlmm { |
| status = "ok"; |
| }; |
| |
| &msm_vidc { |
| compatible = "qcom,msm-vidc", "qcom,sm6150-vidc", "qcom,sa6155p-vidc"; |
| qcom,allowed-clock-rates = <133330000 240000000 300000000 |
| 380000000 410000000 460000000>; |
| }; |
| |
| &clock_gcc { |
| compatible = "qcom,gcc-sa6155", "syscon"; |
| /delete-property/ protected-clocks; |
| }; |
| |
| &clock_videocc { |
| compatible = "qcom,videocc-sa6155", "syscon"; |
| }; |
| |
| &clock_dispcc { |
| compatible = "qcom,dispcc-sa6155", "syscon"; |
| }; |
| |
| &clock_scc { |
| compatible = "qcom,scc-sa6155", "syscon"; |
| vdd_scc_cx-supply = <&VDD_CX_LEVEL>; |
| status = "ok"; |
| }; |
| |
| &clock_camcc { |
| compatible = "qcom,camcc-sa6155", "syscon"; |
| vdd_mx-supply = <&VDD_CX_LEVEL>; |
| }; |
| |
| &clock_gpucc { |
| compatible = "qcom,gpucc-sa6155", "syscon"; |
| vdd_mx-supply = <&VDD_CX_LEVEL>; |
| }; |
| |
| &thermal_zones { |
| lmh-dcvs-00 { |
| trips { |
| active-config { |
| temperature = <105000>; |
| hysteresis = <40000>; |
| }; |
| }; |
| }; |
| |
| lmh-dcvs-01 { |
| trips { |
| active-config { |
| temperature = <105000>; |
| hysteresis = <40000>; |
| }; |
| }; |
| }; |
| |
| cpuss-0-step { |
| trips { |
| cpu45-config { |
| temperature = <115000>; |
| }; |
| }; |
| }; |
| |
| cpuss-1-step { |
| trips { |
| cpu23-config { |
| temperature = <115000>; |
| }; |
| }; |
| }; |
| |
| cpuss-2-step { |
| trips { |
| cpu01-config { |
| temperature = <115000>; |
| }; |
| }; |
| }; |
| |
| cpu-1-0-step { |
| trips { |
| cpu6-0-config { |
| temperature = <115000>; |
| }; |
| }; |
| }; |
| |
| cpu-1-1-step { |
| trips { |
| cpu6-1-config { |
| temperature = <115000>; |
| }; |
| }; |
| }; |
| |
| cpu-1-2-step { |
| trips { |
| cpu7-0-config { |
| temperature = <115000>; |
| }; |
| }; |
| }; |
| |
| cpu-1-3-step { |
| trips { |
| cpu7-1-config { |
| temperature = <115000>; |
| }; |
| }; |
| }; |
| |
| gpu-step { |
| trips { |
| gpu-trip { |
| temperature = <105000>; |
| }; |
| |
| gpu-cx-mon { |
| temperature = <110000>; |
| }; |
| }; |
| }; |
| |
| q6-hvx-step { |
| trips { |
| q6-hvx-config { |
| temperature = <105000>; |
| }; |
| |
| q6-hvx-trip1 { |
| temperature = <105000>; |
| }; |
| |
| q6-hvx-cx-mon { |
| temperature = <110000>; |
| }; |
| }; |
| }; |
| |
| mdm-core-step { |
| trips { |
| mdm-core-cx-mon { |
| temperature = <110000>; |
| }; |
| }; |
| }; |
| |
| camera-step { |
| trips { |
| camera-cx-mon { |
| temperature = <110000>; |
| }; |
| }; |
| }; |
| |
| wlan-step { |
| trips { |
| wlan-cx-mon { |
| temperature = <110000>; |
| }; |
| }; |
| }; |
| |
| display-step { |
| trips { |
| display-cx-mon { |
| temperature = <110000>; |
| }; |
| }; |
| }; |
| |
| video-step { |
| trips { |
| video-cx-mon { |
| temperature = <110000>; |
| }; |
| }; |
| }; |
| |
| quiet-therm-step { |
| status = "disabled"; |
| }; |
| }; |
| |
| /* GPU power level overrides */ |
| &msm_gpu { |
| /* |
| * Speed-bin zero is default speed bin. |
| * For rest of the speed bins, speed-bin value |
| * is calulated as FMAX/4.8 MHz round up to zero |
| * decimal places. |
| */ |
| |
| /delete-node/qcom,gpu-pwrlevel-bins; |
| qcom,gpu-pwrlevel-bins { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compatible="qcom,gpu-pwrlevel-bins"; |
| |
| qcom,gpu-pwrlevels-0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <0>; |
| |
| qcom,initial-pwrlevel = <4>; |
| qcom,ca-target-pwrlevel = <3>; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <845000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <745000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <650000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <500000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <435000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <177>; |
| |
| qcom,initial-pwrlevel = <4>; |
| qcom,ca-target-pwrlevel = <3>; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <845000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <745000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <650000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <500000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <435000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <156>; |
| |
| qcom,initial-pwrlevel = <3>; |
| qcom,ca-target-pwrlevel = <2>; |
| |
| /* NOM L1 */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <745000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <650000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <500000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <435000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <136>; |
| |
| qcom,initial-pwrlevel = <2>; |
| qcom,ca-target-pwrlevel = <1>; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <650000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <500000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <435000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-4 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <105>; |
| |
| qcom,initial-pwrlevel = <1>; |
| qcom,ca-target-pwrlevel = <0>; |
| |
| /* SVS L1 */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <500000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <9>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <435000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-5 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <73>; |
| |
| qcom,initial-pwrlevel = <0>; |
| qcom,ca-target-pwrlevel = <0>; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <350000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| }; |
| }; |
| |
| /* Audio device tree */ |
| #include "sa6155-audio.dtsi" |
| #include "sa6155-pcie.dtsi" |
