arch/arm64/boot/dts/qcom/pms405.dtsi

/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/iio/qcom,spmi-vadc.h>

&spmi_bus {
	qcom,pms405@0 {
		compatible ="qcom,spmi-pmic";
		reg = <0x0 SPMI_USID>;
		#address-cells = <1>;
		#size-cells = <1>;

		qcom,revid@100 {
			compatible = "qcom,qpnp-revid";
			reg = <0x100 0x100>;
		};

		pms405_vadc: vadc@3100 {
			compatible = "qcom,spmi-adc-rev2";
			reg = <0x3100 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "eoc-int-en-set";
			qcom,adc-vdd-reference = <1875>;
			#io-channel-cells = <1>;
			io-channel-ranges;

			ref_gnd {
				label = "ref_gnd";
				reg = <ADC_REF_GND>;
				qcom,pre-scaling = <1 1>;
			};

			vref_1p25 {
				label = "vref_1p25";
				reg = <ADC_1P25VREF>;
				qcom,pre-scaling = <1 1>;
			};

			die_temp {
				label = "die_temp";
				reg = <ADC_DIE_TEMP>;
				qcom,pre-scaling = <1 1>;
			};

			vph_pwr {
				label = "vph_pwr";
				reg = <ADC_VPH_PWR>;
				qcom,pre-scaling = <1 3>;
			};

			xo_therm {
				label = "xo_therm";
				reg = <ADC_XO_THERM_PU2>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
				qcom,pre-scaling = <1 1>;
			};

			pa_therm1 {
				label = "pa_therm1";
				reg = <ADC_AMUX_THM1_PU2>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
				qcom,pre-scaling = <1 1>;
			};

			pa_therm3 {
				label = "pa_therm3";
				reg = <ADC_AMUX_THM3_PU2>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
				qcom,pre-scaling = <1 1>;
			};
		};

		pms405_adc_tm_iio: adc_tm@3500 {
			compatible = "qcom,adc-tm5-iio";
			reg = <0x3500 0x100>;
			#thermal-sensor-cells = <1>;
			io-channels = <&pms405_vadc ADC_XO_THERM_PU2>,
					<&pms405_vadc ADC_AMUX_THM1_PU2>,
					<&pms405_vadc ADC_AMUX_THM3_PU2>;

			xo_therm {
				reg = <ADC_XO_THERM_PU2>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};

			pa_therm1 {
				reg = <ADC_AMUX_THM1_PU2>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};

			pa_therm3 {
				reg = <ADC_AMUX_THM3_PU2>;
				qcom,ratiometric;
				qcom,hw-settle-time = <200>;
			};
		};

		pms405_pon: qcom,power-on@800 {
			compatible = "qcom,qpnp-power-on";
			reg = <0x800 0x100>;
			interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>;
			interrupt-names = "kpdpwr";
			qcom,pon-dbc-delay = <15625>;
			qcom,system-reset;
			qcom,store-hard-reset-reason;

			qcom,pon_1 {
				qcom,pon-type = <0>;
				qcom,pull-up;
				linux,code = <KEY_POWER>;
			};
		};

		pms405_misc: qcom,misc@900 {
			compatible = "qcom,qpnp-misc";
			reg = <0x900 0x100>;
		};

		pms405_clkdiv: clock-controller@5b00 {
			compatible = "qcom,spmi-clkdiv";
			reg = <0x5b00 0x100>;
			#clock-cells = <1>;
			qcom,num-clkdivs = <1>;
			clock-output-names = "pms405_div_clk1";
			clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>;
			clock-names = "xo";

			assigned-clocks = <&pms405_clkdiv 1>;
			assigned-clock-rates = <9600000>;
		};

		/* QCS405 + PMS405 GPIO configuration */
		pms405_gpios: pinctrl@c000 {
			compatible = "qcom,spmi-gpio";
			reg = <0xc000 0xc00>;
			interrupts = <0x0 0xc1 0 IRQ_TYPE_NONE>,
				     <0x0 0xc2 0 IRQ_TYPE_NONE>,
				     <0x0 0xc3 0 IRQ_TYPE_NONE>,
				     <0x0 0xc4 0 IRQ_TYPE_NONE>,
				     <0x0 0xc5 0 IRQ_TYPE_NONE>,
				     <0x0 0xc6 0 IRQ_TYPE_NONE>,
				     <0x0 0xc7 0 IRQ_TYPE_NONE>,
				     <0x0 0xca 0 IRQ_TYPE_NONE>,
				     <0x0 0xcb 0 IRQ_TYPE_NONE>;
			interrupt-names = "pms405_gpio2",  "pms405_gpio3",
					  "pms405_gpio4",  "pms405_gpio5",
					  "pms405_gpio6",  "pms405_gpio7",
					  "pms405_gpio8",  "pms405_gpio11",
					  "pms405_gpio12";
			gpio-controller;
			#gpio-cells = <2>;
			#address-cells = <1>;
			#size-cells = <1>;
			qcom,gpios-disallowed = <1 9 10>;
		};

		qcom,pms405_rtc {
			compatible = "qcom,qpnp-rtc";
			#address-cells = <1>;
			#size-cells = <1>;
			qcom,qpnp-rtc-write = <0>;
			qcom,qpnp-rtc-alarm-pwrup = <0>;

			qcom,pms405_rtc_rw@6000 {
				reg = <0x6000 0x100>;
			};

			qcom,pms405_rtc_alarm@6100 {
				reg = <0x6100 0x100>;
				interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
			};
		};
	};

	qcom,pms405@1 {
		compatible = "qcom,spmi-pmic";
		reg = <0x1 SPMI_USID>;
		#address-cells = <1>;
		#size-cells = <1>;

		pms405_pwm: qcom,pwms@bc00 {
			compatible = "qcom,pwm-lpg";
			reg = <0xbc00 0x200>;
			reg-names = "lpg-base";
			#pwm-cells = <2>;
			qcom,num-lpg-channels = <2>;
		};
	};
};