| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include "skeleton64.dtsi" |
| |
| #include <dt-bindings/clock/qcom,aop-qmp.h> |
| #include <dt-bindings/clock/qcom,camcc-lito.h> |
| #include <dt-bindings/clock/qcom,dispcc-lito.h> |
| #include <dt-bindings/clock/qcom,gcc-lito.h> |
| #include <dt-bindings/clock/qcom,gpucc-lito.h> |
| #include <dt-bindings/clock/qcom,npucc-lito.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/clock/qcom,videocc-lito.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h> |
| #include <dt-bindings/soc/qcom,ipcc.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| |
| / { |
| model = "Qualcomm Technologies, Inc. Lito"; |
| compatible = "qcom,lito"; |
| qcom,msm-id = <400 0x10000>; |
| interrupt-parent = <&intc>; |
| |
| aliases { |
| serial0 = &qupv3_se2_2uart; /*RUMI*/ |
| ufshc1 = &ufshc_mem; /* Embedded UFS slot */ |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x10000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| |
| L3_0: l3-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x200000>; |
| cache-level = <3>; |
| }; |
| }; |
| |
| L1_I_0: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x8800>; |
| }; |
| |
| L1_D_0: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| |
| L2_TLB_0: l2-tlb { |
| qcom,dump-size = <0x5000>; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_100>; |
| L2_100: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x10000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_100: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x8800>; |
| }; |
| |
| L1_D_100: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| |
| L2_TLB_100: l2-tlb { |
| qcom,dump-size = <0x5000>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_200>; |
| L2_200: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x10000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_200: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x8800>; |
| }; |
| |
| L1_D_200: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| |
| L2_TLB_200: l2-tlb { |
| qcom,dump-size = <0x5000>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_300>; |
| L2_300: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x10000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_300: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x8800>; |
| }; |
| |
| L1_D_300: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| |
| L2_TLB_300: l2-tlb { |
| qcom,dump-size = <0x5000>; |
| }; |
| |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_400>; |
| L2_400: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x10000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_400: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x8800>; |
| }; |
| |
| L1_D_400: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| |
| L2_TLB_400: l2-tlb { |
| qcom,dump-size = <0x5000>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| cache-size = <0x8000>; |
| next-level-cache = <&L2_500>; |
| L2_500: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x10000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| }; |
| |
| L1_I_500: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x8800>; |
| }; |
| |
| L1_D_500: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x9000>; |
| }; |
| |
| L2_TLB_500: l2-tlb { |
| qcom,dump-size = <0x5000>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| cache-size = <0x10000>; |
| next-level-cache = <&L2_600>; |
| L2_600: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x40000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| qcom,dump-size = <0x48000>; |
| }; |
| |
| L1_I_600: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x11000>; |
| }; |
| |
| L1_D_600: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| |
| L1_ITLB_600: l1-itlb { |
| qcom,dump-size = <0x300>; |
| }; |
| |
| L1_DTLB_600: l1-dtlb { |
| qcom,dump-size = <0x480>; |
| }; |
| |
| L2_TLB_600: l2-tlb { |
| qcom,dump-size = <0x7800>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| cache-size = <0x10000>; |
| next-level-cache = <&L2_700>; |
| L2_700: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-size = <0x40000>; |
| cache-level = <2>; |
| next-level-cache = <&L3_0>; |
| qcom,dump-size = <0x48000>; |
| }; |
| |
| L1_I_700: l1-icache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x11000>; |
| }; |
| |
| L1_D_700: l1-dcache { |
| compatible = "arm,arch-cache"; |
| qcom,dump-size = <0x12000>; |
| }; |
| |
| L1_ITLB_700: l1-itlb { |
| qcom,dump-size = <0x300>; |
| }; |
| |
| L1_DTLB_700: l1-dtlb { |
| qcom,dump-size = <0x480>; |
| }; |
| |
| L2_TLB_700: l2-tlb { |
| qcom,dump-size = <0x7800>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&CPU6>; |
| }; |
| }; |
| |
| cluster2 { |
| core0 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| }; |
| |
| firmware: firmware { |
| android { |
| compatible = "android,firmware"; |
| fstab { |
| compatible = "android,fstab"; |
| vendor { |
| compatible = "android,vendor"; |
| dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; |
| type = "ext4"; |
| mnt_flags = "ro,barrier=1,discard"; |
| fsmgr_flags = "wait,slotselect,avb"; |
| status = "ok"; |
| }; |
| }; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| hyp_mem: hyp_region@80000000 { |
| no-map; |
| reg = <0x0 0x80000000 0x0 0x600000>; |
| }; |
| |
| xbl_aop_mem: xbl_aop_region@80700000 { |
| no-map; |
| reg = <0x0 0x80700000 0x0 0x120000>; |
| }; |
| |
| cmd_db: reserved-memory@80820000 { |
| reg = <0x0 0x80820000 0x0 0x20000>; |
| compatible = "qcom,cmd-db"; |
| no-map; |
| }; |
| |
| sec_apps_mem: sec_apps_region@808ff000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x808ff000 0x0 0x1000>; |
| }; |
| |
| smem_mem: smem_region@80900000 { |
| no-map; |
| reg = <0x0 0x80900000 0x0 0x200000>; |
| }; |
| |
| removed_mem: removed_region@80b00000 { |
| no-map; |
| reg = <0x0 0x80b00000 0x0 0x1300000>; |
| }; |
| |
| qtee_apps_mem: qtee_apps_region@81e00000 { |
| no-map; |
| reg = <0x0 0x81e00000 0x0 0x2600000>; |
| }; |
| |
| modem_wlan_mem: modem_wlan_region@86000000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x86000000 0x0 0xbe00000>; |
| }; |
| |
| pil_camera_mem: pil_camera_region@91e00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x91e00000 0x0 0x500000>; |
| }; |
| |
| pil_npu_mem: pil_npu_region@92300000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x92300000 0x0 0x500000>; |
| }; |
| |
| pil_video_mem: pil_video_region@92800000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x92800000 0x0 0x500000>; |
| }; |
| |
| pil_cvp_mem: pil_cvp_region@92d00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x92d00000 0x0 0x500000>; |
| }; |
| |
| pil_cdsp_mem: pil_cdsp_region@93200000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x93200000 0x0 0x1e00000>; |
| }; |
| |
| pil_adsp_mem: pil_adsp_region@95000000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x95000000 0x0 0x2800000>; |
| }; |
| |
| pil_wlan_fw_mem: pil_wlan_fw_region@97800000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x97800000 0x0 0x200000>; |
| }; |
| |
| pil_ipa_fw_mem: pil_ipa_fw_region@97a00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x97a00000 0x0 0x10000>; |
| }; |
| |
| pil_ipa_gsi_mem: pil_ipa_gsi_region@97a10000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x97a10000 0x0 0x5000>; |
| }; |
| |
| pil_gpu_mem: pil_gpu_region@97a15000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x97a15000 0x0 0x2000>; |
| }; |
| |
| qseecom_mem: qseecom_mem_region@9e000000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x9e000000 0x0 0x1400000>; |
| }; |
| |
| cdsp_sec_mem: cdsp_sec_regions@9f400000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x9f400000 0x0 0xc00000>; |
| }; |
| cdsp_mem: cdsp_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x400000>; |
| }; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x2000000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| chosen { |
| bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; |
| }; |
| |
| soc: soc { }; |
| }; |
| |
| &soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| reg = <0x17a00000 0x10000>, /* GICD */ |
| <0x17a60000 0x100000>; /* GICR * 8 */ |
| interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&intc>; |
| }; |
| |
| pdc: interrupt-controller@b220000 { |
| compatible = "qcom,lito-pdc"; |
| reg = <0xb220000 0x30000>; |
| qcom,pdc-ranges = <0 480 42>, <42 612 28>, <70 63 1>, |
| <71 640 15>, <86 522 52>; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&intc>; |
| interrupt-controller; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| clock-frequency = <19200000>; |
| }; |
| |
| timer@17c20000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x17c20000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@17c21000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c21000 0x1000>, |
| <0x17c22000 0x1000>; |
| }; |
| |
| frame@17c23000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c23000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c25000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c25000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c27000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c27000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c29000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c29000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c2b000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c2b000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17c2d000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0x17c2d000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qcom,msm-imem@146ab000 { |
| compatible = "qcom,msm-imem"; |
| reg = <0x146ab000 0x1000>; |
| ranges = <0x0 0x146ab000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mem_dump_table@10 { |
| compatible = "qcom,msm-imem-mem_dump_table"; |
| reg = <0x10 0x8>; |
| }; |
| |
| restart_reason@65c { |
| compatible = "qcom,msm-imem-restart_reason"; |
| reg = <0x65c 0x4>; |
| }; |
| |
| dload_type@1c { |
| compatible = "qcom,msm-imem-dload-type"; |
| reg = <0x1c 0x4>; |
| }; |
| |
| boot_stats@6b0 { |
| compatible = "qcom,msm-imem-boot_stats"; |
| reg = <0x6b0 0x20>; |
| }; |
| |
| kaslr_offset@6d0 { |
| compatible = "qcom,msm-imem-kaslr_offset"; |
| reg = <0x6d0 0xc>; |
| }; |
| |
| pil@94c { |
| compatible = "qcom,msm-imem-pil"; |
| reg = <0x94c 0xc8>; |
| }; |
| |
| diag_dload@c8 { |
| compatible = "qcom,msm-imem-diag-dload"; |
| reg = <0xc8 0xc8>; |
| }; |
| }; |
| |
| restart@c264000 { |
| compatible = "qcom,pshold"; |
| reg = <0xc264000 0x4>, |
| <0x1fd3000 0x4>; |
| reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| }; |
| |
| qcom,mpm2-sleep-counter@0xc221000 { |
| compatible = "qcom,mpm2-sleep-counter"; |
| reg = <0xc221000 0x1000>; |
| clock-frequency = <32768>; |
| }; |
| |
| qcom,msm-rtb { |
| compatible = "qcom,msm-rtb"; |
| qcom,rtb-size = <0x100000>; |
| }; |
| |
| wdog: qcom,wdt@17c10000 { |
| compatible = "qcom,msm-watchdog"; |
| reg = <0x17c10000 0x1000>; |
| reg-names = "wdt-base"; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,bark-time = <11000>; |
| qcom,pet-time = <9360>; |
| qcom,ipi-ping; |
| qcom,wakeup-enable; |
| qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100 |
| 0x10100 0x10100 0x25900 0x25900>; |
| }; |
| |
| cpuss_dump { |
| compatible = "qcom,cpuss-dump"; |
| |
| qcom,l1_i_cache0 { |
| qcom,dump-node = <&L1_I_0>; |
| qcom,dump-id = <0x60>; |
| }; |
| |
| qcom,l1_i_cache100 { |
| qcom,dump-node = <&L1_I_100>; |
| qcom,dump-id = <0x61>; |
| }; |
| |
| qcom,l1_i_cache200 { |
| qcom,dump-node = <&L1_I_200>; |
| qcom,dump-id = <0x62>; |
| }; |
| |
| qcom,l1_i_cache300 { |
| qcom,dump-node = <&L1_I_300>; |
| qcom,dump-id = <0x63>; |
| }; |
| |
| qcom,l1_i_cache400 { |
| qcom,dump-node = <&L1_I_400>; |
| qcom,dump-id = <0x64>; |
| }; |
| |
| qcom,l1_i_cache500 { |
| qcom,dump-node = <&L1_I_500>; |
| qcom,dump-id = <0x65>; |
| }; |
| |
| qcom,l1_i_cache600 { |
| qcom,dump-node = <&L1_I_600>; |
| qcom,dump-id = <0x66>; |
| }; |
| |
| qcom,l1_i_cache700 { |
| qcom,dump-node = <&L1_I_700>; |
| qcom,dump-id = <0x67>; |
| }; |
| |
| qcom,l1_d_cache0 { |
| qcom,dump-node = <&L1_D_0>; |
| qcom,dump-id = <0x80>; |
| }; |
| |
| qcom,l1_d_cache100 { |
| qcom,dump-node = <&L1_D_100>; |
| qcom,dump-id = <0x81>; |
| }; |
| |
| qcom,l1_d_cache200 { |
| qcom,dump-node = <&L1_D_200>; |
| qcom,dump-id = <0x82>; |
| }; |
| |
| qcom,l1_d_cache300 { |
| qcom,dump-node = <&L1_D_300>; |
| qcom,dump-id = <0x83>; |
| }; |
| |
| qcom,l1_d_cache400 { |
| qcom,dump-node = <&L1_D_400>; |
| qcom,dump-id = <0x84>; |
| }; |
| |
| qcom,l1_d_cache500 { |
| qcom,dump-node = <&L1_D_500>; |
| qcom,dump-id = <0x85>; |
| }; |
| |
| qcom,l1_d_cache600 { |
| qcom,dump-node = <&L1_D_600>; |
| qcom,dump-id = <0x86>; |
| }; |
| |
| qcom,l1_d_cache700 { |
| qcom,dump-node = <&L1_D_700>; |
| qcom,dump-id = <0x87>; |
| }; |
| |
| qcom,l1_i_tlb_dump600 { |
| qcom,dump-node = <&L1_ITLB_600>; |
| qcom,dump-id = <0x26>; |
| }; |
| |
| qcom,l1_i_tlb_dump700 { |
| qcom,dump-node = <&L1_ITLB_700>; |
| qcom,dump-id = <0x27>; |
| }; |
| |
| qcom,l1_d_tlb_dump600 { |
| qcom,dump-node = <&L1_DTLB_600>; |
| qcom,dump-id = <0x46>; |
| }; |
| |
| qcom,l1_d_tlb_dump700 { |
| qcom,dump-node = <&L1_DTLB_700>; |
| qcom,dump-id = <0x47>; |
| }; |
| |
| qcom,l2_cache_dump600 { |
| qcom,dump-node = <&L2_600>; |
| qcom,dump-id = <0xc6>; |
| }; |
| |
| qcom,l2_cache_dump700 { |
| qcom,dump-node = <&L2_700>; |
| qcom,dump-id = <0xc7>; |
| }; |
| |
| qcom,l2_tlb_dump0 { |
| qcom,dump-node = <&L2_TLB_0>; |
| qcom,dump-id = <0x120>; |
| }; |
| |
| qcom,l2_tlb_dump100 { |
| qcom,dump-node = <&L2_TLB_100>; |
| qcom,dump-id = <0x121>; |
| }; |
| |
| qcom,l2_tlb_dump200 { |
| qcom,dump-node = <&L2_TLB_200>; |
| qcom,dump-id = <0x122>; |
| }; |
| |
| qcom,l2_tlb_dump300 { |
| qcom,dump-node = <&L2_TLB_300>; |
| qcom,dump-id = <0x123>; |
| }; |
| |
| qcom,l2_tlb_dump400 { |
| qcom,dump-node = <&L2_TLB_400>; |
| qcom,dump-id = <0x124>; |
| }; |
| |
| qcom,l2_tlb_dump500 { |
| qcom,dump-node = <&L2_TLB_500>; |
| qcom,dump-id = <0x125>; |
| }; |
| |
| qcom,l2_tlb_dump600 { |
| qcom,dump-node = <&L2_TLB_600>; |
| qcom,dump-id = <0x126>; |
| }; |
| |
| qcom,l2_tlb_dump700 { |
| qcom,dump-node = <&L2_TLB_700>; |
| qcom,dump-id = <0x127>; |
| }; |
| }; |
| |
| qcom,sps { |
| compatible = "qcom,msm-sps-4k"; |
| qcom,pipe-attr-ee; |
| }; |
| |
| qcom,ghd { |
| compatible = "qcom,gladiator-hang-detect-v3"; |
| qcom,threshold-arr = <0x17e0041c>; |
| qcom,config-reg = <0x17e00434>; |
| }; |
| |
| clocks { |
| xo_board: xo-board { |
| compatible = "fixed-clock"; |
| clock-frequency = <38400000>; |
| clock-output-names = "xo_board"; |
| #clock-cells = <0>; |
| }; |
| |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| clock-output-names = "chip_sleep_clk"; |
| clock-frequency = <32000>; |
| #clock-cells = <0>; |
| }; |
| }; |
| |
| cxo: bi_tcxo { |
| compatible = "fixed-factor-clock"; |
| clocks = <&xo_board>; |
| clock-mult = <1>; |
| clock-div = <2>; |
| #clock-cells = <0>; |
| }; |
| |
| cxo_a: bi_tcxo_ao { |
| compatible = "fixed-factor-clock"; |
| clocks = <&xo_board>; |
| clock-mult = <1>; |
| clock-div = <2>; |
| #clock-cells = <0>; |
| }; |
| |
| rpmhcc: qcom,rpmhclk { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "rpmh_clocks"; |
| #clock-cells = <1>; |
| }; |
| |
| aopcc: qcom,aopclk { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "qdss_clocks"; |
| #clock-cells = <1>; |
| }; |
| |
| gcc: qcom,gcc@100000 { |
| compatible = "qcom,gcc-lito", "syscon"; |
| reg = <0x100000 0x1f0000>; |
| reg-names = "cc_base"; |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| camcc: qcom,camcc@ad00000 { |
| compatible = "qcom,lito-camcc", "syscon"; |
| reg = <0xad00000 0x10000>; |
| reg-names = "cc_base"; |
| vdd_mx-supply = <&VDD_MX_LEVEL>; |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| clock-names = "cfg_ahb_clk"; |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| videocc: qcom,videocc { |
| compatible = "qcom,lito-videocc", "syscon"; |
| reg = <0x0ab00000 0x10000>; |
| reg-names = "cc_base"; |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| clock-names = "cfg_ahb_clk"; |
| clocks = <&gcc GCC_VIDEO_AHB_CLK>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| dispcc: qcom,dispcc { |
| compatible = "qcom,lito-dispcc"; |
| reg = <0xaf00000 0x20000>; |
| reg-names = "cc_base"; |
| clock-names = "cfg_ahb_clk"; |
| clocks = <&gcc GCC_DISP_AHB_CLK>; |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| ufsphy_mem: ufsphy_mem@1d87000 { |
| reg = <0x1d87000 0xe00>; /* PHY regs */ |
| reg-names = "phy_mem"; |
| #phy-cells = <0>; |
| |
| lanes-per-direction = <2>; |
| |
| clock-names = "ref_clk_src", |
| "ref_clk", |
| "ref_aux_clk"; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_UFS_1X_CLKREF_CLK>, |
| <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
| |
| status = "disabled"; |
| }; |
| |
| ufshc_mem: ufshc@1d84000 { |
| compatible = "qcom,ufshc"; |
| reg = <0x1d84000 0x3000>; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&ufsphy_mem>; |
| phy-names = "ufsphy"; |
| |
| lanes-per-direction = <2>; |
| dev-ref-clk-freq = <0>; /* 19.2 MHz */ |
| |
| clock-names = |
| "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "core_clk_ice", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk", |
| "rx_lane1_sync_clk"; |
| clocks = |
| <&gcc GCC_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_UFS_PHY_AHB_CLK>, |
| <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
| <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
| freq-table-hz = |
| <37500000 300000000>, |
| <0 0>, |
| <0 0>, |
| <37500000 150000000>, |
| <75000000 300000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| |
| qcom,msm-bus,name = "ufshc_mem"; |
| qcom,msm-bus,num-cases = <22>; |
| qcom,msm-bus,num-paths = <2>; |
| qcom,msm-bus,vectors-KBps = |
| /* |
| * During HS G3 UFS runs at nominal voltage corner, vote |
| * higher bandwidth to push other buses in the data path |
| * to run at nominal to achieve max throughput. |
| * 4GBps pushes BIMC to run at nominal. |
| * 200MBps pushes CNOC to run at nominal. |
| * Vote for half of this bandwidth for HS G3 1-lane. |
| * For max bandwidth, vote high enough to push the buses |
| * to run in turbo voltage corner. |
| */ |
| <123 512 0 0>, <1 757 0 0>, /* No vote */ |
| <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */ |
| <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */ |
| <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */ |
| <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */ |
| <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */ |
| <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */ |
| <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */ |
| <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */ |
| <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */ |
| <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */ |
| <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */ |
| <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */ |
| <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */ |
| <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */ |
| <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */ |
| <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */ |
| <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */ |
| <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */ |
| <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */ |
| /* As UFS working in HS G3 RB L2 mode, aggregated |
| * bandwidth (AB) should take care of providing |
| * optimum throughput requested. However, as tested, |
| * in order to scale up CNOC clock, instantaneous |
| * bindwidth (IB) needs to be given a proper value too. |
| */ |
| <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */ |
| <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */ |
| |
| qcom,bus-vector-names = "MIN", |
| "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", |
| "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", |
| "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", |
| "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", |
| "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", |
| "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", |
| "MAX"; |
| |
| /* PM QoS */ |
| qcom,pm-qos-cpu-groups = <0x3f 0xc0>; |
| qcom,pm-qos-cpu-group-latency-us = <67 67>; |
| qcom,pm-qos-default-cpu = <0>; |
| |
| pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; |
| pinctrl-0 = <&ufs_dev_reset_assert>; |
| pinctrl-1 = <&ufs_dev_reset_deassert>; |
| |
| resets = <&gcc GCC_UFS_PHY_BCR>; |
| reset-names = "core_reset"; |
| non-removable; |
| |
| status = "disabled"; |
| }; |
| |
| npucc: qcom,npucc { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "npucc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| gpucc: qcom,gpucc { |
| compatible = "qcom,dummycc"; |
| clock-output-names = "gpucc_clocks"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| apps_rsc: rsc@18200000 { |
| label = "apps_rsc"; |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0x18200000 0x10000>, |
| <0x18210000 0x10000>, |
| <0x18220000 0x10000>; |
| reg-names = "drv-0", "drv-1", "drv-2"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,tcs-offset = <0xd00>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, |
| <SLEEP_TCS 3>, |
| <WAKE_TCS 3>, |
| <CONTROL_TCS 1>; |
| |
| system_pm { |
| compatible = "qcom,system-pm"; |
| }; |
| }; |
| |
| disp_rsc: rsc@af20000 { |
| label = "disp_rsc"; |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0xaf20000 0x10000>; |
| reg-names = "drv-0"; |
| interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,tcs-offset = <0x1c00>; |
| qcom,drv-id = <0>; |
| qcom,tcs-config = <ACTIVE_TCS 0>, |
| <SLEEP_TCS 1>, |
| <WAKE_TCS 1>, |
| <CONTROL_TCS 0>; |
| }; |
| |
| qcom,rmtfs_sharedmem@0 { |
| compatible = "qcom,sharedmem-uio"; |
| reg = <0x0 0x200000>; |
| reg-names = "rmtfs"; |
| qcom,client-id = <0x00000001>; |
| }; |
| |
| ipcc_mproc: qcom,ipcc@408000 { |
| compatible = "qcom,ipcc"; |
| reg = <0x408000 0x1000>; |
| interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| #mbox-cells = <2>; |
| }; |
| |
| ipcc_self_ping: ipcc-self-ping { |
| compatible = "qcom,ipcc-self-ping"; |
| interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS |
| IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>; |
| mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>; |
| }; |
| |
| cache-controller@9200000 { |
| compatible = "qcom,llcc-v1"; |
| reg = <0x9200000 0xd0000> , <0x9600000 0x50000>; |
| reg-names = "llcc_base", "llcc_broadcast_base"; |
| interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
| cap-based-alloc-and-pwr-collapse; |
| }; |
| |
| cpu_pmu: cpu-pmu { |
| compatible = "arm,armv8-pmuv3"; |
| qcom,irq-is-percpu; |
| interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| qcom,chd_silver { |
| compatible = "qcom,core-hang-detect"; |
| label = "silver"; |
| qcom,threshold-arr = <0x18000058 0x18010058 |
| 0x18020058 0x18030058 |
| 0x18040058 0x18050058>; |
| qcom,config-arr = <0x18000060 0x18010060 |
| 0x18020060 0x18030060 |
| 0x18040060 0x18050060>; |
| }; |
| |
| qcom,chd_gold { |
| compatible = "qcom,core-hang-detect"; |
| label = "gold"; |
| qcom,threshold-arr = <0x18060058 0x18070058>; |
| qcom,config-arr = <0x18060060 0x18070060>; |
| }; |
| |
| kryo-erp { |
| compatible = "arm,arm64-kryo-cpu-erp"; |
| interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "l1-l2-faultirq", |
| "l3-scu-faultirq"; |
| }; |
| |
| tcsr_mutex_block: syscon@1f40000 { |
| compatible = "syscon"; |
| reg = <0x1f40000 0x20000>; |
| }; |
| |
| tcsr_mutex: hwlock { |
| compatible = "qcom,tcsr-mutex"; |
| syscon = <&tcsr_mutex_block 0 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| smem: qcom,smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_mem>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| qcom,glink { |
| compatible = "qcom,glink"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| glink_modem: modem { |
| qcom,remote-pid = <1>; |
| transport = "smem"; |
| mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| mbox-names = "modem_smem"; |
| interrupt-parent = <&ipcc_mproc>; |
| interrupts = <IPCC_CLIENT_MPSS |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| label = "modem"; |
| qcom,glink-label = "mpss"; |
| |
| qcom,modem_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,modem_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_adsp>, |
| <&glink_cdsp>; |
| }; |
| |
| qcom,msm_fastrpc_rpmsg { |
| compatible = "qcom,msm-fastrpc-rpmsg"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| qcom,intents = <0x64 64>; |
| }; |
| |
| qcom,modem_ds { |
| qcom,glink-channels = "DS"; |
| qcom,intents = <0x4000 0x2>; |
| }; |
| }; |
| |
| glink_adsp: adsp { |
| qcom,remote-pid = <2>; |
| transport = "smem"; |
| mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| mbox-names = "adsp_smem"; |
| interrupt-parent = <&ipcc_mproc>; |
| interrupts = <IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| label = "adsp"; |
| qcom,glink-label = "lpass"; |
| |
| qcom,adsp_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,adsp_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_modem>, |
| <&glink_cdsp>; |
| }; |
| }; |
| |
| glink_cdsp: cdsp { |
| qcom,remote-pid = <5>; |
| transport = "smem"; |
| mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| mbox-names = "dsps_smem"; |
| interrupt-parent = <&ipcc_mproc>; |
| interrupts = <IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| label = "cdsp"; |
| qcom,glink-label = "cdsp"; |
| |
| qcom,cdsp_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,cdsp_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_modem>, |
| <&glink_adsp>, |
| <&glink_npu>; |
| }; |
| }; |
| |
| glink_npu: npu { |
| qcom,remote-pid = <10>; |
| transport = "smem"; |
| mboxes = <&ipcc_mproc IPCC_CLIENT_NPU |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| mbox-names = "npu_smem"; |
| interrupt-parent = <&ipcc_mproc>; |
| interrupts = <IPCC_CLIENT_NPU |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| label = "npu"; |
| qcom,glink-label = "npu"; |
| |
| qcom,npu_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,npu_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_modem>, |
| <&glink_adsp>, |
| <&glink_cdsp>; |
| }; |
| }; |
| }; |
| |
| qmp_aop: qcom,qmp-aop@c300000 { |
| compatible = "qcom,qmp-mbox"; |
| reg = <0xc300000 0x1000>; |
| reg-names = "msgram"; |
| mboxes = <&ipcc_mproc IPCC_CLIENT_AOP |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| mbox-names = "aop_qmp"; |
| interrupt-parent = <&ipcc_mproc>; |
| interrupts = <IPCC_CLIENT_AOP |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| |
| label = "aop"; |
| qcom,early-boot; |
| priority = <0>; |
| mbox-desc-offset = <0x0>; |
| #mbox-cells = <1>; |
| }; |
| |
| aop-msg-client { |
| compatible = "qcom,debugfs-qmp-client"; |
| mboxes = <&qmp_aop 0>; |
| mbox-names = "aop"; |
| }; |
| |
| pil_modem: qcom,mss@4080000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x4080000 0x100>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| vdd_mss-supply = <&VDD_MSS_LEVEL>; |
| qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; |
| |
| qcom,firmware-name = "modem"; |
| memory-region = <&modem_wlan_mem>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,sysmon-id = <0>; |
| qcom,ssctl-instance-id = <0x12>; |
| qcom,pas-id = <4>; |
| qcom,smem-id = <421>; |
| qcom,minidump-id = <3>; |
| qcom,complete-ramdump; |
| |
| /* Inputs from mss */ |
| interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, |
| <&mpss_smp2p_in 0 IRQ_TYPE_NONE>, |
| <&mpss_smp2p_in 1 IRQ_TYPE_NONE>, |
| <&mpss_smp2p_in 2 IRQ_TYPE_NONE>, |
| <&mpss_smp2p_in 3 IRQ_TYPE_NONE>, |
| <&mpss_smp2p_in 7 IRQ_TYPE_NONE>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,err-ready", |
| "qcom,proxy-unvote", |
| "qcom,stop-ack", |
| "qcom,shutdown-ack"; |
| |
| /* Outputs to mss */ |
| qcom,smem-states = <&mpss_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| |
| mbox-names = "mss-pil"; |
| }; |
| |
| qcom,lpass@3000000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x3000000 0x00100>; |
| |
| vdd_lpi_cx-supply = <&L8A_LEVEL>; |
| qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| vdd_lpi_mx-supply = <&L4A_LEVEL>; |
| qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>; |
| qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <1>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <423>; |
| qcom,sysmon-id = <1>; |
| qcom,ssctl-instance-id = <0x14>; |
| qcom,firmware-name = "adsp"; |
| memory-region = <&pil_adsp_mem>; |
| qcom,complete-ramdump; |
| |
| /* Inputs from lpass */ |
| interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, |
| <&adsp_smp2p_in 0 0>, |
| <&adsp_smp2p_in 1 0>, |
| <&adsp_smp2p_in 2 0>, |
| <&adsp_smp2p_in 3 0>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,err-ready", |
| "qcom,proxy-unvote", |
| "qcom,stop-ack"; |
| |
| /* Outputs to lpass */ |
| qcom,smem-states = <&adsp_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| |
| mbox-names = "adsp-pil"; |
| }; |
| |
| qcom,turing@8300000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x8300000 0x100000>; |
| |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| qcom,proxy-reg-names = "vdd_cx"; |
| qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <18>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <601>; |
| qcom,sysmon-id = <7>; |
| qcom,ssctl-instance-id = <0x17>; |
| qcom,firmware-name = "cdsp"; |
| memory-region = <&pil_cdsp_mem>; |
| qcom,complete-ramdump; |
| |
| /* Inputs from turing */ |
| interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, |
| <&cdsp_smp2p_in 0 0>, |
| <&cdsp_smp2p_in 2 0>, |
| <&cdsp_smp2p_in 1 0>, |
| <&cdsp_smp2p_in 3 0>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,proxy-unvote", |
| "qcom,err-ready", |
| "qcom,stop-ack"; |
| |
| /* Outputs to turing */ |
| qcom,smem-states = <&cdsp_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| |
| mbox-names = "cdsp-pil"; |
| }; |
| }; |
| |
| #include "lito-pinctrl.dtsi" |
| #include "lito-pm.dtsi" |
| #include "lito-gdsc.dtsi" |
| #include "msm-arm-smmu-lito.dtsi" |
| #include "lito-regulators.dtsi" |
| #include "lito-smp2p.dtsi" |
| #include "lito-usb.dtsi" |
| |
| &ufs_phy_gdsc { |
| status = "ok"; |
| }; |
| |
| &usb30_prim_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc { |
| status = "ok"; |
| }; |
| |
| &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc { |
| status = "ok"; |
| }; |
| |
| &bps_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>; |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &ipe_0_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>; |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &ipe_1_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>; |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &ife_0_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>; |
| status = "ok"; |
| }; |
| |
| &ife_1_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>; |
| status = "ok"; |
| }; |
| |
| &titan_top_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_CAMERA_AHB_CLK>; |
| status = "ok"; |
| }; |
| |
| &mdss_core_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_DISP_AHB_CLK>; |
| status = "ok"; |
| }; |
| |
| &gpu_cx_gdsc { |
| status = "ok"; |
| }; |
| |
| &gpu_gx_gdsc { |
| status = "ok"; |
| }; |
| |
| &npu_core_gdsc { |
| status = "ok"; |
| }; |
| |
| &mvsc_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_VIDEO_AHB_CLK>; |
| status = "ok"; |
| }; |
| |
| &mvs0_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_VIDEO_AHB_CLK>; |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &mvs1_gdsc { |
| clock-names = "ahb_clk"; |
| clocks = <&gcc GCC_VIDEO_AHB_CLK>; |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| #include "lito-qupv3.dtsi" |
