Merge branch 'LA.UM.9.12.R2.10.00.00.685.021' into qcom-msm-4.19-7250-wlan-api.lnx.1.0.r46
Change-Id: I66ba02e391ebc982aab3ae8d5d3a0a0713b97b4a
diff --git a/fw/htt_ppdu_stats.h b/fw/htt_ppdu_stats.h
index a02e7ad..1f70b5a 100644
--- a/fw/htt_ppdu_stats.h
+++ b/fw/htt_ppdu_stats.h
@@ -714,13 +714,22 @@
* of the BSS and is used to assist a receiving STA in
* identifying the BSS from which a PPDU originates.
* Value in the range 0 to 63
- * BIT [31 : 6] -reserved
+ * BIT [6 : 6] - PPDU transmitted using Non-SRG opportunity
+ * BIT [7 : 7] - PPDU transmitted using SRG opportunity
+ * BIT [15: 8] - RSSI of the aborted OBSS frame (in dB w.r.t. noise floor)
+ * by which SRG/Non-SRG based spatial reuse opportunity
+ * was created.
+ * BIT [31:16] - reserved
*/
union {
+ A_UINT32 reserved__aborted_obss_rssi__srg_tx__non_srg_tx___bss_color_id;
A_UINT32 reserved__bss_color_id;
struct {
- A_UINT32 bss_color_id: 6,
- reserved2: 26;
+ A_UINT32 bss_color_id: 6,
+ non_srg_tx: 1,
+ srg_tx: 1,
+ aborted_obss_rssi: 8,
+ reserved2: 16;
};
};
} htt_ppdu_stats_common_tlv;
diff --git a/fw/wmi_services.h b/fw/wmi_services.h
index b2b02cb..92cecb5 100644
--- a/fw/wmi_services.h
+++ b/fw/wmi_services.h
@@ -443,6 +443,7 @@
WMI_SERVICE_MU_PREAMBLE_PUNCTURE_SUPPORT = 248, /* Indicates FW supports MU preamble puncture */
WMI_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, /* Support for SRG, SRP based spatial reuse support */
WMI_REQUEST_CTRL_PATH_STATS_REQUEST = 250, /* FW supports control path stats */
+ WMI_SERVICE_TPC_STATS_EVENT = 251, /* FW support to dump the TPC tables */
/******* ADD NEW SERVICES UP TO 256 HERE *******/
diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h
index c9bdc6f..f7de494 100644
--- a/fw/wmi_tlv_defs.h
+++ b/fw/wmi_tlv_defs.h
@@ -199,6 +199,7 @@
WMITLV_TAG_ARRAY_BYTE,
WMITLV_TAG_ARRAY_STRUC,
WMITLV_TAG_ARRAY_FIXED_STRUC,
+ WMITLV_TAG_ARRAY_INT16,
WMITLV_TAG_LAST_ARRAY_ENUM = 31, /* Last entry of ARRAY type tags */
WMITLV_TAG_STRUC_wmi_service_ready_event_fixed_param,
WMITLV_TAG_STRUC_HAL_REG_CAPABILITIES,
@@ -1081,6 +1082,13 @@
WMITLV_TAG_STRUC_wmi_request_ctrl_path_stats_cmd_fixed_param,
WMITLV_TAG_STRUC_wmi_ctrl_path_stats_event_fixed_param,
WMITLV_TAG_STRUC_wmi_ctrl_path_pdev_stats_struct,
+ WMITLV_TAG_STRUC_wmi_pdev_get_tpc_stats_cmd_fixed_param,
+ WMITLV_TAG_STRUC_wmi_pdev_get_tpc_stats_event_fixed_param,
+ WMITLV_TAG_STRUC_wmi_tpc_configs,
+ WMITLV_TAG_STRUC_wmi_max_reg_power_allowed,
+ WMITLV_TAG_STRUC_wmi_tpc_rates_array,
+ WMITLV_TAG_STRUC_wmi_tpc_ctl_pwr_table,
+ WMITLV_TAG_STRUC_wmi_vdev_bcn_latency_fixed_param,
} WMITLV_TAG_ID;
/*
@@ -1526,6 +1534,7 @@
OP(WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID) \
OP(WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID) \
OP(WMI_REQUEST_CTRL_PATH_STATS_CMDID) \
+ OP(WMI_PDEV_GET_TPC_STATS_CMDID) \
/* add new CMD_LIST elements above this line */
@@ -1777,6 +1786,8 @@
OP(WMI_PDEV_SSCAN_FW_PARAM_EVENTID) \
OP(WMI_ROAM_CAPABILITY_REPORT_EVENTID) \
OP(WMI_CTRL_PATH_STATS_EVENTID) \
+ OP(WMI_PDEV_GET_TPC_STATS_EVENTID) \
+ OP(WMI_VDEV_BCN_LATENCY_EVENTID) \
/* add new EVT_LIST elements above this line */
@@ -4428,6 +4439,11 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_non_srg_obss_bssid_enable_bitmap_cmd_fixed_param, wmi_pdev_non_srg_obss_bssid_enable_bitmap_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID);
+/* PDEV Get TPC STATS Cmd */
+#define WMITLV_TABLE_WMI_PDEV_GET_TPC_STATS_CMDID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_tpc_stats_cmd_fixed_param, wmi_pdev_get_tpc_stats_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_STATS_CMDID);
+
/************************** TLV definitions of WMI events *******************************/
@@ -5963,6 +5979,22 @@
WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_capability_report_event_fixed_param, wmi_roam_capability_report_event_fixed_param, fixed_param, WMITLV_SIZE_FIX)
WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_CAPABILITY_REPORT_EVENTID);
+/* PDEV TPC STATS Event */
+#define WMITLV_TABLE_WMI_PDEV_GET_TPC_STATS_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_get_tpc_stats_event_fixed_param, wmi_pdev_get_tpc_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tpc_configs, tpc_configs, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_max_reg_power_allowed, regulatory_power, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_INT16, A_INT16, reg_buf, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tpc_rates_array, tpc_rates, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_INT16, A_UINT16, rates_buf, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_tpc_ctl_pwr_table, ctl_power, WMITLV_SIZE_VAR) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_INT8, ctl_buf, WMITLV_SIZE_VAR)
+WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_GET_TPC_STATS_EVENTID);
+
+/* Send Bcn Latency ie related params to host */
+#define WMITLV_TABLE_WMI_VDEV_BCN_LATENCY_EVENTID(id,op,buf,len) \
+ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_bcn_latency_fixed_param, wmi_vdev_bcn_latency_fixed_param, fixed_param, WMITLV_SIZE_FIX)
+WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_BCN_LATENCY_EVENTID);
#ifdef __cplusplus
}
diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h
index 2b9c082..cd56e2f 100644
--- a/fw/wmi_unified.h
+++ b/fw/wmi_unified.h
@@ -434,6 +434,8 @@
WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID,
/** OBSS BSSID enable bitmap for NON_SRG based spatial reuse feature */
WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID,
+ /** TPC stats display command */
+ WMI_PDEV_GET_TPC_STATS_CMDID,
/* VDEV (virtual device) specific commands */
/** vdev create */
@@ -1446,6 +1448,10 @@
*/
WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID,
+ /** WMI event in response to TPC STATS command */
+ WMI_PDEV_GET_TPC_STATS_EVENTID,
+
+
/* VDEV specific events */
/** VDEV started event in response to VDEV_START request */
WMI_VDEV_START_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VDEV),
@@ -1510,6 +1516,8 @@
WMI_VDEV_SEND_BIG_DATA_EVENTID,
/** send BIG DATA stats to host phase 2 */
WMI_VDEV_SEND_BIG_DATA_P2_EVENTID,
+ /** Latency related information received from beacon IE */
+ WMI_VDEV_BCN_LATENCY_EVENTID,
/* peer specific events */
@@ -3657,6 +3665,7 @@
* (maximum number of beacons after which VAP profiles repeat)
* for any EMA VAP on any pdev.
*/
+
A_UINT32 ema_max_profile_period;
/** @brief max_ndp_sessions
* This is the max ndp sessions sent by the host which is the minimum
@@ -3665,6 +3674,12 @@
* SERVICE_READY_EXT2_EVENT message).
*/
A_UINT32 max_ndp_sessions;
+
+ /** @brief max_ndi_supported
+ * This is the max ndi interfaces sent by the host based on the value
+ * specified by the host's ini configuration.
+ */
+ A_UINT32 max_ndi_interfaces;
} wmi_resource_config;
#define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \
@@ -6793,6 +6808,16 @@
/* Parameter used to enable/disable SR prohibit feature */
WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT,
+ /*
+ * Parameter used to enable/disable UL OFDMA mBSSID support for
+ * trigger frames. It is disabled by default.
+ * bit | config_mode
+ * -----------------
+ * 0 | Enable/Disable mBSSID trigger support for basic triggers.
+ * 1 | Enable/Disable mBSSID trigger support for BSR triggers.
+ */
+ WMI_PDEV_PARAM_ENABLE_MBSSID_CTRL_FRAME,
+
} WMI_PDEV_PARAM;
#define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1)
@@ -6930,6 +6955,151 @@
wmi_mac_addr macaddr;
} wmi_pdev_div_get_rssi_antid_fixed_param;
+typedef enum {
+ WMI_TPC_STATS_EVENT_SEND_REG = 0x00000001,
+ WMI_TPC_STATS_EVENT_SEND_RATE = 0x00000002,
+ WMI_TPC_STATS_EVENT_SEND_CTL = 0x00000004,
+ WMI_TPC_STATS_EVENT_SEND_REG_RATE_CTL = 0x00000007, /* REG | RATE | CTL */
+} WMI_PDEV_TPC_STATS_PARAMS;
+
+typedef struct {
+ A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_tpc_stats_cmd_fixed_param */
+ /** pdev_id for identifying the MAC
+ * See macros starting with WMI_PDEV_ID_ for values.
+ */
+ A_UINT32 pdev_id;
+ /** parameter -
+ * This is to specify whether we want only the target power
+ * information (rates array) or the CTL power or the regulatory
+ * power information. At present, we send all of them.
+ */
+ A_UINT32 param; /* Currently expect WMI_TPC_STATS_EVENT_SEND_REG_RATE_CTL
+ * as a host specification that rates array, regulatory
+ * power array, and ctl power array are all to be sent.
+ * See WMI_PDEV_TPC_STATS_PARAMS.
+ */
+} wmi_pdev_get_tpc_stats_cmd_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_pdev_get_tpc_stats_event_fixed_param */
+ A_UINT32 pdev_id; /* pdev_id for identifying the MAC. See macros starting with WMI_PDEV_ID_ for values */
+ A_UINT32 end_of_event; /* The total response to the WMI command will be split into multiple event chunks to fit into the WMI svc msg size limit: 0 indicates more events to follow: 1 indicates end of event */
+ A_UINT32 event_count; /* Incremented for every event chunk for Host to know the sequence */
+ /* wmi_tpc_configs TLV to optionally follow */
+ /* wmi_max_reg_power_allowed TLVs to optionally follow */
+ /* wmi_tpc_rates_array TLVs to optionally follow */
+ /* wmi_tpc_ctl_pwr_table TLVs to optionally follow */
+} wmi_pdev_get_tpc_stats_event_fixed_param;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tpc_configs */
+ A_UINT32 regDomain;
+ A_UINT32 chanFreq; /* current channel in MHz */
+ A_UINT32 phyMode; /* current phy mode - See WLAN_PHY_MODE for the different phy modes */
+ A_UINT32 maxAntennaGain; /* Maximum antenna gain for the current regulatory in 0.25 dBm steps */
+ A_UINT32 twiceMaxRDPower; /* Maximum transmit power allowed in the regulatory domain in 0.25 dBm steps */
+ A_INT32 userAntennaGain; /* User specified antenna gain in 0.25 dBm steps */
+ A_UINT32 powerLimit; /* The overall power limit in 0.25 dBm steps */
+ A_UINT32 rateMax; /* The total number of rates supported */
+ A_UINT32 numTxChain; /* The total number of active chains */
+ A_UINT32 ctl; /* See CONFORMANCE_TEST_LIMITS enumeration */
+ A_UINT32 flags; /* See WMI_TPC_CONFIG_EVENT_FLAG */
+} wmi_tpc_configs;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_max_reg_power_allowed */
+ A_UINT32 reg_power_type; /* 0: maxRegAllowedPower (1D array),
+ * 1: maxRegAllowedPowerAGCDD (2D array),
+ * 2: maxRegAllowedPowerAGSTBC (2D array),
+ * 3: maxRegAllowedPowerAGTXBF (2D array)
+ */
+ A_UINT32 reg_power_array_len; /* Length of the regulatory power array being sent in bytes */
+ A_UINT32 d1; /* the length of 1st (innermost) dimension array */
+ A_UINT32 d2; /* the length of 2nd dimension array */
+ A_UINT32 d3; /* the length of 3rd dimension array (for future use) */
+ A_UINT32 d4; /* the length of 4th dimension array (for future use) */
+ /*
+ * This TLV is followed by an A_INT16 TLV-array that will carry
+ * one of the four types of regulatory power arrays.
+ *
+ * The multi-dimensional regulatory power array will be communicated
+ * as a flat array: Host to stitch it back as 2D array.
+ * For an array[a][b][c][d], d1 = d, d2 = c, d3 = b, d4 = a
+ * For a 2D array, array[a][b], d1 = b, d2 = a, d3 = 1, d4 = 1
+ * The possible types of following A_INT16 TLV arrays are
+ * 1. A_INT16 maxRegAllowedPower[WHAL_TPC_TX_NUM_CHAIN];
+ * 2. A_INT16 maxRegAllowedPowerAGCDD[WHAL_TPC_TX_NUM_CHAIN - 1][WHAL_TPC_TX_NUM_CHAIN - 1];
+ * 3. A_INT16 maxRegAllowedPowerAGSTBC[WHAL_TPC_TX_NUM_CHAIN - 1][WHAL_TPC_TX_NUM_CHAIN - 1];
+ * 4. A_INT16 maxRegAllowedPowerAGTXBF[WHAL_TPC_TX_NUM_CHAIN - 1][WHAL_TPC_TX_NUM_CHAIN - 1];
+ * where WHAL_TPC_TX_NUM_CHAIN=2 for CYP and 8 for HK.
+ */
+} wmi_max_reg_power_allowed;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tpc_rates_array */
+ A_UINT32 rate_array_type; /* 0: ratesArray,
+ * 1: ratesArray2 (for chain > 4),
+ * 2: dl_ofdma rate array
+ */
+ A_UINT32 rate_array_len;
+ /* This TLV will be followed by an A_UINT16 TLV array that will
+ * carry one of the types of TPC rate arrays.
+ * All the rates arrays are 1D arrays.
+ * The possible types of following A_UINT16 TLV arrays are
+ * 1. A_UINT16 ratesArray[WHAL_TPC_RATE_MAX];
+ * This array has to be referred when number of active chains is < 4
+ * 2. A_UINT16 ratesArray2[WHAL_TPC_RATE_MAX];
+ * This array has to be referred when number of active chains is > 4
+ * 3. A_UINT16 ratesArray_DL_OFDMA[72];
+ * WHAL_TPC_RATE_MAX is 748 for HK (considering PHY A0 8x8)
+ * WHAL_TPC_RATE_MAX is 188 for CYP (considering PHY A0 2x2)
+ * Each 16 bit value in the rates array carries both SU and MU
+ * target power information.
+ * Bits 0:7 contained the SU target power (signed value, 0.25 dBm units),
+ * bits 8:15 denote the MU target power (signed value, 0.25 dBm units).
+ */
+} wmi_tpc_rates_array;
+
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tpc_ctl_pwr_table */
+ A_UINT32 ctl_array_type; /* 0: ctl_array,
+ * 1: ctl_160 array,
+ * 2: ctl_dlOfdma array,
+ * 3: ctl_ulOfdma array
+ */
+ A_UINT32 ctl_array_len; /* Length of the CTL array being sent in bytes */
+ A_UINT32 end_of_ctl_pwr; /* Message MAY be split into smaller chunks
+ * to fit in the WMI svc msg size limit:
+ * 0 indicates more chunks of CTL info to follow,
+ * 1 indicates end of CTL info.
+ */
+ A_UINT32 ctl_pwr_count; /* Incremented for every CTL info chunk
+ * for Host to know the sequence.
+ */
+ A_UINT32 d1; /* the length of 1st (innermost) dimension array */
+ A_UINT32 d2; /* the length of 2nd dimension array */
+ A_UINT32 d3; /* the length of 3rd dimension array */
+ A_UINT32 d4; /* the length of 4th dimension array */
+ /* This TLV will be followed by an A_INT8 TLV-array that will
+ * carry one the types of CTL power arrays.
+ * The CTL array will be multi-dimensional, but will be communicated as
+ * a flat array; the host has to stitch it back into a 4D array.
+ * The possible types of following A_INT8 arrays are
+ * 1. A_INT8 ctlEdgePwrBF[WHAL_MAX_NUM_CHAINS][2][10][8];
+ * 2. A_INT8 ctlEdgePwr160[WHAL_MAX_NUM_CHAINS/2][2][2][4];
+ * 3. A_INT8 ctlEdgePwrBF_dlOFDMA[WHAL_MAX_NUM_CHAINS][2][3][8];
+ * For e.g., in ctlEdgePwrBF
+ * D4 = WHAL_MAX_NUM_CHAINS = 8 for HK, 2 for CYP, 4 for Pine
+ * D3 = BF on/off = 2
+ * D2 = 10 which the number of different tx modes,
+ * like cck, legacy, HT20, HT40, VHT80, etc.
+ * D1 = NSS = 8, number of spatial streams
+ * Total number of elements = D4*D3*D2*D1
+ * The same will apply for ctl_dlOfdma array, except that the values
+ * of d1,d2,d3,d4 will be different.
+ */
+} wmi_tpc_ctl_pwr_table;
+
typedef struct {
A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_pdev_bss_chan_info_request_fixed_param */
A_UINT32 param; /* 1 = read only, 2= read and clear */
@@ -14340,6 +14510,20 @@
(((roam_reason) & WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE_MASK) >> \
WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE_SHIFT)
+/* Bits 0-3: stores 4 LSbs of trigger reason.
+ * Old host will get trigger reasons <= 15 from this bitfield.
+ * Bit 7 will be 1 always to indicate that bits 8-15 are valid.
+ * Bits 8-15: full trigger_reason, including values > 15.
+ * New host will gett full trigger_reason from this bitfield.
+ * Bits 8-11 and bits 0-3 store matching values.
+ */
+#define WMI_SET_ROAM_EXT_TRIGGER_REASON(roam_reason, trigger_reason) \
+ do { \
+ (roam_reason) |= (trigger_reason & 0xf); \
+ (roam_reason) |= 0x80; \
+ (roam_reason) |= ((trigger_reason & 0xff) << 8); \
+ } while (0)
+
/* roaming notification */
#define WMI_ROAM_NOTIF_INVALID 0x0 /** invalid notification. Do not interpret notif field */
#define WMI_ROAM_NOTIF_ROAM_START 0x1 /** indicate that roaming is started. sent only in non WOW state */
@@ -19927,10 +20111,13 @@
/** auth_status: connected or authorized */
A_UINT32 auth_status;
/** roam_reason:
- * bits 0-3 for roam reason see WMI_ROAM_REASON_XXX
- * bits 4-5 for subnet status see WMI_ROAM_SUBNET_CHANGE_STATUS_XXX.
- * bit 6 for HW mode status, set 1 to indicate host to schedule
- * HW mode change, see WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE.
+ * bits 0-3 roam trigger reason LSbs - see WMI_ROAM_TRIGGER_REASON_XXX
+ * bits 4-5 subnet status - see WMI_ROAM_SUBNET_CHANGE_STATUS_XXX.
+ * bit 6 HW mode status, set 1 to indicate host to schedule
+ * HW mode change, see WMI_ROAM_REQUEST_HOST_HW_MODE_CHANGE.
+ * bit 7 0x1 to show bits 8-15 are valid
+ * bits 8-15 full WMI_ROAM_TRIGGER_REASON_ID/WMI_ROAM_TRIGGER_EXT_REASON_ID
+ * since 4 bits are not enough.
*/
A_UINT32 roam_reason;
/** associated AP's rssi calculated by FW when reason code is WMI_ROAM_REASON_LOW_RSSI. not valid if roam_reason is BMISS */
@@ -21434,6 +21621,29 @@
A_UINT32 bss_color_bitmap_bit32to63; /* Bit set indicating BSS color present */
} wmi_obss_color_collision_evt_fixed_param;
+/*
+ * WMI event to notify host if latency_flags/latency_level got changed
+ * or if latency got enabled/disabled.
+ * When latency disable is received in the beacon vendor IE and wlm
+ * parameters are restored, latency_enable will be zero.
+ * latency level and latency flags will be those of wlm params.
+ * Lay out of latency flags is as follows. The field is same as flags
+ * in wmi_wlm_config_cmd_fixed_param.
+ *
+ * |31 19| 18 | 17|16 14| 13 | 12| 11 | 10 | 9 | 8 |7 6|5 4|3 2| 1 | 0 |
+ * +-----+-----+---+-----+----+---+----+----+-----+----+----+----+----+---+---+
+ * | RSVD|SRATE|RTS| NSS |EDCA|TRY|SSLP|CSLP|DBMPS|RSVD|Roam|RSVD|DWLT|DFS|SUP|
+ * +------------------------------+---------------+---------+-----------------+
+ * | WAL | PS | Roam | Scan |
+ */
+typedef struct {
+ A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_bcn_latency_fixed_param */
+ A_UINT32 vdev_id;
+ A_UINT32 latency_enable;
+ A_UINT32 latency_level;
+ A_UINT32 latency_flags;
+} wmi_vdev_bcn_latency_fixed_param;
+
/**
* OCB DCC types and structures.
*/
@@ -26314,6 +26524,7 @@
WMI_RETURN_STRING(WMI_SIMULATION_TEST_CMDID);
WMI_RETURN_STRING(WMI_AUDIO_AGGR_SET_RTSCTS_CONFIG_CMDID);
WMI_RETURN_STRING(WMI_REQUEST_CTRL_PATH_STATS_CMDID);
+ WMI_RETURN_STRING(WMI_PDEV_GET_TPC_STATS_CMDID);
}
return "Invalid WMI cmd";
diff --git a/fw/wmi_version.h b/fw/wmi_version.h
index 3204313..5adc744 100644
--- a/fw/wmi_version.h
+++ b/fw/wmi_version.h
@@ -36,7 +36,7 @@
#define __WMI_VER_MINOR_ 0
/** WMI revision number has to be incremented when there is a
* change that may or may not break compatibility. */
-#define __WMI_REVISION_ 843
+#define __WMI_REVISION_ 848
/** The Version Namespace should not be normally changed. Only
* host and firmware of the same WMI namespace will work
diff --git a/hw/qca5018/HALcomdef.h b/hw/qca5018/HALcomdef.h
new file mode 100644
index 0000000..e536d2e
--- /dev/null
+++ b/hw/qca5018/HALcomdef.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+/*
+==============================================================================
+
+FILE: HALcomdef.h
+
+DESCRIPTION:
+
+==============================================================================
+
+ Edit History
+
+$Header: //depot/prj/qca/lithium3/wcss/maple_verif/native/register/include/HALcomdef.h#1 $
+
+when who what, where, why
+-------- --- -----------------------------------------------------------
+06/17/10 sc Included com_dtypes.h and cleaned up typedefs
+05/15/08 gfr Added HAL_ENUM_32BITS macro.
+02/14/08 gfr Added bool32 type.
+11/13/07 gfr Removed dependency on comdef.h
+01/08/07 hxw Created
+
+==============================================================================
+*/
+
+
+/*
+ * Assembly wrapper
+ */
+#ifndef _ARM_ASM_
+
+/*
+ * C++ wrapper
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+/* -----------------------------------------------------------------------
+** Types
+** ----------------------------------------------------------------------- */
+
+/*
+ * Standard integer types.
+ *
+ * bool32 - boolean, 32 bit (TRUE or FALSE)
+ */
+#ifndef _BOOL32_DEFINED
+typedef unsigned long int bool32;
+#define _BOOL32_DEFINED
+#endif
+
+/*
+ * Macro to allow forcing an enum to 32 bits. The argument should be
+ * an identifier in the namespace of the enumeration in question, i.e.
+ * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
+ */
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+/*===========================================================================
+
+FUNCTION inp, outp, inpw, outpw, inpdw, outpdw
+
+DESCRIPTION
+ IN/OUT port macros for byte and word ports, typically inlined by compilers
+ which support these routines
+
+PARAMETERS
+ inp( xx_addr )
+ inpw( xx_addr )
+ inpdw( xx_addr )
+ outp( xx_addr, xx_byte_val )
+ outpw( xx_addr, xx_word_val )
+ outpdw( xx_addr, xx_dword_val )
+ xx_addr - Address of port to read or write (may be memory mapped)
+ xx_byte_val - 8 bit value to write
+ xx_word_val - 16 bit value to write
+ xx_dword_val - 32 bit value to write
+
+DEPENDENCIES
+ None
+
+RETURN VALUE
+ inp/inpw/inpdw: the byte, word or dword read from the given address
+ outp/outpw/outpdw: the byte, word or dword written to the given address
+
+SIDE EFFECTS
+ None.
+
+===========================================================================*/
+
+ /* ARM based targets use memory mapped i/o, so the inp/outp calls are
+ ** macroized to access memory directly
+ */
+
+#if defined(VV_FEATURE_COMPILING_64BIT)
+ #define inp(port) (*((volatile dword *) (port)))
+ #define inpw(port) (*((volatile word *) (port)))
+ #define inpdw(port) (*((volatile dword *)(port)))
+
+ #define outp(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+ #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val)))
+ #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ARM_ASM_ */
+
+#endif /* HAL_COMDEF_H */
+
diff --git a/hw/qca5018/HALhwio.h b/hw/qca5018/HALhwio.h
new file mode 100644
index 0000000..512a924
--- /dev/null
+++ b/hw/qca5018/HALhwio.h
@@ -0,0 +1,490 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+/*
+===========================================================================
+*/
+/**
+ @file HALhwio.h
+
+ Public interface include file for accessing the HWIO HAL definitions.
+
+ The HALhwio.h file is the public API interface to the HW I/O (HWIO)
+ register access definitions.
+*/
+
+/*=========================================================================
+ Include Files
+==========================================================================*/
+
+
+/*
+ * Common types.
+ */
+#include "HALcomdef.h"
+
+
+
+/* -----------------------------------------------------------------------
+** Macros
+** ----------------------------------------------------------------------- */
+
+#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET
+#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET
+/**
+ @addtogroup macros
+ @{
+*/
+
+/**
+ * Map a base name to the pointer to access the base.
+ *
+ * This macro maps a base name to the pointer to access the base.
+ * This is generally just used internally.
+ *
+ */
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+
+/**
+ * Declare a HWIO base pointer.
+ *
+ * This macro will declare a HWIO base pointer data structure. The pointer
+ * will always be declared as a weak symbol so multiple declarations will
+ * resolve correctly to the same data at link-time.
+ */
+#ifdef __ARMCC_VERSION
+ #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+ #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+/**
+ @}
+*/
+
+
+/**
+ @addtogroup hwio_macros
+ @{
+*/
+
+/**
+ * @name Address Macros
+ *
+ * Macros for getting register addresses.
+ * These macros are used for retrieving the address of a register.
+ * HWIO_ADDR* will return the directly accessible address (virtual or physical based
+ * on environment), HWIO_PHYS* will always return the physical address.
+ * The offset from the base region can be retrieved using HWIO_OFFS*.
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ *
+ * @{
+ */
+#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3)
+/** @} */
+
+/**
+ * @name Input Macros
+ *
+ * These macros are used for reading from a named hardware register. Register
+ * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
+ * indicates that the input will be masked with the supplied mask. The HWIO_INF*
+ * macros take a field name and will do the appropriate masking and shifting
+ * to return just the value of that field.
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ *
+ * Generally you want to use either HWIO_IN or HWIO_INF (with required indexing).
+ *
+ * @{
+ */
+#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+/** @} */
+
+/**
+ * @name Output Macros
+ *
+ * These macros are used for writing to a named hardware register. Register
+ * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix
+ * indicates that the output will be masked with the supplied mask (meaning these
+ * macros do a read first, mask in the supplied data, then write it back).
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ * The HWIO_OUTF* macros take a field name and will do the appropriate masking
+ * and shifting to output just the value of that field.
+ * HWIO_OUTV* registers take a named value instead of a numeric value and
+ * do the same masking/shifting as HWIO_OUTF.
+ *
+ * Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing).
+ *
+ * @{
+ */
+#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+/** @} */
+
+/**
+ * @name Shift and Mask Macros
+ *
+ * Macros for getting shift and mask values for fields and registers.
+ * HWIO_RMSK: The mask value for accessing an entire register. For example:
+ * @code
+ * HWIO_RMSK(REG) -> 0xFFFFFFFF
+ * @endcode
+ * HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n
+ * HWIO_SHFT: The right-shift value for accessing a field in a register. For example:
+ * @code
+ * HWIO_SHFT(REG, FLD) -> 8
+ * @endcode
+ * HWIO_FMSK: The mask value for accessing a field in a register. For example:
+ * @code
+ * HWIO_FMSK(REG, FLD) -> 0xFF00
+ * @endcode
+ * HWIO_VAL: The value for a field in a register. For example:
+ * @code
+ * HWIO_VAL(REG, FLD, ON) -> 0x1
+ * @endcode
+ * HWIO_FVAL: This macro takes a numerical value and will shift and mask it into
+ * the given field position. For example:
+ * @code
+ * HWIO_FVAL(REG, FLD, 0x1) -> 0x100
+ * @endcode
+ * HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it
+ * into the given field position. For example:
+ * @code
+ * HWIO_FVALV(REG, FLD, ON) -> 0x100
+ * @endcode
+ *
+ * @{
+ */
+#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+/** @} */
+
+/**
+ * @name Shadow Register Macros
+ *
+ * These macros are used for directly reading the value stored in a
+ * shadow register.
+ * Shadow registers are defined for write-only registers. Generally these
+ * macros should not be necessary as HWIO_OUTM* macros will automatically use
+ * the shadow values internally.
+ *
+ * @{
+ */
+#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index)
+/** @} */
+
+/**
+ @}
+*/ /* end_group */
+
+
+/** @cond */
+
+/*
+ * Map to final symbols. This remapping is done to allow register
+ * redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN
+ * then remappings like "#define xreg xregnew" do not work as expected.
+ */
+#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS
+#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \
+ HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+ HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+ }
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \
+ HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+ HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+ HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+ }
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+ HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+ HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+ HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+ HWIO_##hwiosym##_OUTM(base, mask4, val4); \
+ }
+
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+
+/*
+ * HWIO_INTLOCK
+ *
+ * Macro used by autogenerated code for mutual exclusion around
+ * read-mask-write operations. This is not supported in HAL
+ * code but can be overridden by non-HAL code.
+ */
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+
+/*
+ * Input/output port macros for memory mapped IO.
+ */
+#define __inp(port) (*((volatile uint8 *) (port)))
+#define __inpw(port) (*((volatile uint16 *) (port)))
+#define __inpdw(port) (*((volatile uint32 *) (port)))
+#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+
+#ifdef HAL_HWIO_EXTERNAL
+
+/*
+ * Replace macros with externally supplied functions.
+ */
+#undef __inp
+#undef __inpw
+#undef __inpdw
+#undef __outp
+#undef __outpw
+#undef __outpdw
+
+#define __inp(port) __inp_extern(port)
+#define __inpw(port) __inpw_extern(port)
+#define __inpdw(port) __inpdw_extern(port)
+#define __outp(port, val) __outp_extern(port, val)
+#define __outpw(port, val) __outpw_extern(port, val)
+#define __outpdw(port, val) __outpdw_extern(port, val)
+
+extern uint8 __inp_extern ( uint32 nAddr );
+extern uint16 __inpw_extern ( uint32 nAddr );
+extern uint32 __inpdw_extern ( uint32 nAddr );
+extern void __outp_extern ( uint32 nAddr, uint8 nData );
+extern void __outpw_extern ( uint32 nAddr, uint16 nData );
+extern void __outpdw_extern ( uint32 nAddr, uint32 nData );
+
+#endif /* HAL_HWIO_EXTERNAL */
+
+
+/*
+ * Base 8-bit byte accessing macros.
+ */
+#define in_byte(addr) (__inp(addr))
+#define in_byte_masked(addr, mask) (__inp(addr) & (mask))
+#define out_byte(addr, val) __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK(); \
+ out_byte( io, shadow); \
+ shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+ HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content) \
+ out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+ ((uint16)((val) & (mask)))) )
+
+
+/*
+ * Base 16-bit word accessing macros.
+ */
+#define in_word(addr) (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val) __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK( ); \
+ shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+ out_word( io, shadow); \
+ HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content) \
+ out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+ ((uint16)((val) & (mask)))) )
+
+
+/*
+ * Base 32-bit double-word accessing macros.
+ */
+#define in_dword(addr) (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val) __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow) \
+ HWIO_INTLOCK(); \
+ shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+ out_dword( io, shadow); \
+ HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+ out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+ ((uint32)((val) & (mask)))) )
+
+/** @endcond */
+
+#endif /* HAL_HWIO_H */
+
diff --git a/hw/qca5018/buffer_addr_info.h b/hw/qca5018/buffer_addr_info.h
new file mode 100644
index 0000000..275f8c9
--- /dev/null
+++ b/hw/qca5018/buffer_addr_info.h
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 buffer_addr_31_0[31:0]
+// 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+ uint32_t buffer_addr_31_0 : 32; //[31:0]
+ uint32_t buffer_addr_39_32 : 8, //[7:0]
+ return_buffer_manager : 3, //[10:8]
+ sw_buffer_cookie : 21; //[31:11]
+};
+
+/*
+
+buffer_addr_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+
+buffer_addr_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+
+return_buffer_manager
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+
+sw_buffer_cookie
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+
+
+/* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+
+#endif // _BUFFER_ADDR_INFO_H_
diff --git a/hw/qca5018/ce_src_desc.h b/hw/qca5018/ce_src_desc.h
new file mode 100644
index 0000000..cc107b1
--- /dev/null
+++ b/hw/qca5018/ce_src_desc.h
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 src_buffer_low[31:0]
+// 1 src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16]
+// 2 fw_metadata[15:0], ce_res_1[31:16]
+// 3 ce_res_2[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+ uint32_t src_buffer_low : 32; //[31:0]
+ uint32_t src_buffer_high : 8, //[7:0]
+ toeplitz_en : 1, //[8]
+ src_swap : 1, //[9]
+ dest_swap : 1, //[10]
+ gather : 1, //[11]
+ ce_res_0 : 4, //[15:12]
+ length : 16; //[31:16]
+ uint32_t fw_metadata : 16, //[15:0]
+ ce_res_1 : 16; //[31:16]
+ uint32_t ce_res_2 : 20, //[19:0]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+src_buffer_low
+
+ LSB 32 bits of the 40 Bit Pointer to the source buffer
+
+ <legal all>
+
+src_buffer_high
+
+ MSB 8 bits of the 40 Bit Pointer to the source buffer
+
+ <legal all>
+
+toeplitz_en
+
+ Enable generation of 32-bit Toeplitz-LFSR hash for the
+ data transfer
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+
+src_swap
+
+ Treats source memory organization as big-endian. For
+ each dword read (4 bytes), the byte 0 is swapped with byte 3
+ and byte 1 is swapped with byte 2.
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+
+dest_swap
+
+ Treats destination memory organization as big-endian.
+ For each dword write (4 bytes), the byte 0 is swapped with
+ byte 3 and byte 1 is swapped with byte 2.
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+
+gather
+
+ Enables gather of multiple copy engine source
+ descriptors to one destination.
+
+ <legal all>
+
+ce_res_0
+
+ Reserved
+
+ <legal all>
+
+length
+
+ Length of the buffer in units of octets of the current
+ descriptor
+
+ <legal all>
+
+fw_metadata
+
+ Meta data used by FW
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+
+ce_res_1
+
+ Reserved
+
+ <legal all>
+
+ce_res_2
+
+ Reserved
+
+ <legal all>
+
+ring_id
+
+ The buffer pointer ring ID.
+
+ 0 refers to the IDLE ring
+
+ 1 - N refers to other rings
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+/* Description CE_SRC_DESC_0_SRC_BUFFER_LOW
+
+ LSB 32 bits of the 40 Bit Pointer to the source buffer
+
+ <legal all>
+*/
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff
+
+/* Description CE_SRC_DESC_1_SRC_BUFFER_HIGH
+
+ MSB 8 bits of the 40 Bit Pointer to the source buffer
+
+ <legal all>
+*/
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff
+
+/* Description CE_SRC_DESC_1_TOEPLITZ_EN
+
+ Enable generation of 32-bit Toeplitz-LFSR hash for the
+ data transfer
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+*/
+#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004
+#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8
+#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100
+
+/* Description CE_SRC_DESC_1_SRC_SWAP
+
+ Treats source memory organization as big-endian. For
+ each dword read (4 bytes), the byte 0 is swapped with byte 3
+ and byte 1 is swapped with byte 2.
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+*/
+#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004
+#define CE_SRC_DESC_1_SRC_SWAP_LSB 9
+#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200
+
+/* Description CE_SRC_DESC_1_DEST_SWAP
+
+ Treats destination memory organization as big-endian.
+ For each dword write (4 bytes), the byte 0 is swapped with
+ byte 3 and byte 1 is swapped with byte 2.
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+*/
+#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004
+#define CE_SRC_DESC_1_DEST_SWAP_LSB 10
+#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400
+
+/* Description CE_SRC_DESC_1_GATHER
+
+ Enables gather of multiple copy engine source
+ descriptors to one destination.
+
+ <legal all>
+*/
+#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004
+#define CE_SRC_DESC_1_GATHER_LSB 11
+#define CE_SRC_DESC_1_GATHER_MASK 0x00000800
+
+/* Description CE_SRC_DESC_1_CE_RES_0
+
+ Reserved
+
+ <legal all>
+*/
+#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004
+#define CE_SRC_DESC_1_CE_RES_0_LSB 12
+#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000
+
+/* Description CE_SRC_DESC_1_LENGTH
+
+ Length of the buffer in units of octets of the current
+ descriptor
+
+ <legal all>
+*/
+#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004
+#define CE_SRC_DESC_1_LENGTH_LSB 16
+#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000
+
+/* Description CE_SRC_DESC_2_FW_METADATA
+
+ Meta data used by FW
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+*/
+#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008
+#define CE_SRC_DESC_2_FW_METADATA_LSB 0
+#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff
+
+/* Description CE_SRC_DESC_2_CE_RES_1
+
+ Reserved
+
+ <legal all>
+*/
+#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008
+#define CE_SRC_DESC_2_CE_RES_1_LSB 16
+#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000
+
+/* Description CE_SRC_DESC_3_CE_RES_2
+
+ Reserved
+
+ <legal all>
+*/
+#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c
+#define CE_SRC_DESC_3_CE_RES_2_LSB 0
+#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff
+
+/* Description CE_SRC_DESC_3_RING_ID
+
+ The buffer pointer ring ID.
+
+ 0 refers to the IDLE ring
+
+ 1 - N refers to other rings
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+*/
+#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c
+#define CE_SRC_DESC_3_RING_ID_LSB 20
+#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000
+
+/* Description CE_SRC_DESC_3_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
+#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28
+#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _CE_SRC_DESC_H_
diff --git a/hw/qca5018/ce_stat_desc.h b/hw/qca5018/ce_stat_desc.h
new file mode 100644
index 0000000..b06ffe4
--- /dev/null
+++ b/hw/qca5018/ce_stat_desc.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16]
+// 1 toeplitz_hash_0[31:0]
+// 2 toeplitz_hash_1[31:0]
+// 3 fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+ uint32_t ce_res_5 : 8, //[7:0]
+ toeplitz_en : 1, //[8]
+ src_swap : 1, //[9]
+ dest_swap : 1, //[10]
+ gather : 1, //[11]
+ ce_res_6 : 4, //[15:12]
+ length : 16; //[31:16]
+ uint32_t toeplitz_hash_0 : 32; //[31:0]
+ uint32_t toeplitz_hash_1 : 32; //[31:0]
+ uint32_t fw_metadata : 16, //[15:0]
+ ce_res_7 : 4, //[19:16]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+ce_res_5
+
+ Reserved
+
+ <legal all>
+
+toeplitz_en
+
+
+ <legal all>
+
+src_swap
+
+ Source memory buffer swapped
+
+ <legal all>
+
+dest_swap
+
+ Destination memory buffer swapped
+
+ <legal all>
+
+gather
+
+ Gather of multiple copy engine source descriptors to one
+ destination enabled
+
+ <legal all>
+
+ce_res_6
+
+ Reserved
+
+ <legal all>
+
+length
+
+ Sum of all the Lengths of the source descriptor in the
+ gather chain
+
+ <legal all>
+
+toeplitz_hash_0
+
+ 32 LS bits of 64 bit Toeplitz LFSR hash result
+
+ <legal all>
+
+toeplitz_hash_1
+
+ 32 MS bits of 64 bit Toeplitz LFSR hash result
+
+ <legal all>
+
+fw_metadata
+
+ Meta data used by FW
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+
+ce_res_7
+
+ Reserved
+
+ <legal all>
+
+ring_id
+
+ The buffer pointer ring ID.
+
+ 0 refers to the IDLE ring
+
+ 1 - N refers to other rings
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+/* Description CE_STAT_DESC_0_CE_RES_5
+
+ Reserved
+
+ <legal all>
+*/
+#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000
+#define CE_STAT_DESC_0_CE_RES_5_LSB 0
+#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff
+
+/* Description CE_STAT_DESC_0_TOEPLITZ_EN
+
+
+ <legal all>
+*/
+#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000
+#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8
+#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100
+
+/* Description CE_STAT_DESC_0_SRC_SWAP
+
+ Source memory buffer swapped
+
+ <legal all>
+*/
+#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000
+#define CE_STAT_DESC_0_SRC_SWAP_LSB 9
+#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200
+
+/* Description CE_STAT_DESC_0_DEST_SWAP
+
+ Destination memory buffer swapped
+
+ <legal all>
+*/
+#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000
+#define CE_STAT_DESC_0_DEST_SWAP_LSB 10
+#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400
+
+/* Description CE_STAT_DESC_0_GATHER
+
+ Gather of multiple copy engine source descriptors to one
+ destination enabled
+
+ <legal all>
+*/
+#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000
+#define CE_STAT_DESC_0_GATHER_LSB 11
+#define CE_STAT_DESC_0_GATHER_MASK 0x00000800
+
+/* Description CE_STAT_DESC_0_CE_RES_6
+
+ Reserved
+
+ <legal all>
+*/
+#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000
+#define CE_STAT_DESC_0_CE_RES_6_LSB 12
+#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000
+
+/* Description CE_STAT_DESC_0_LENGTH
+
+ Sum of all the Lengths of the source descriptor in the
+ gather chain
+
+ <legal all>
+*/
+#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000
+#define CE_STAT_DESC_0_LENGTH_LSB 16
+#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000
+
+/* Description CE_STAT_DESC_1_TOEPLITZ_HASH_0
+
+ 32 LS bits of 64 bit Toeplitz LFSR hash result
+
+ <legal all>
+*/
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff
+
+/* Description CE_STAT_DESC_2_TOEPLITZ_HASH_1
+
+ 32 MS bits of 64 bit Toeplitz LFSR hash result
+
+ <legal all>
+*/
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff
+
+/* Description CE_STAT_DESC_3_FW_METADATA
+
+ Meta data used by FW
+
+ In case of gather field in first source ring entry of
+ the gather copy cycle in taken into account.
+
+ <legal all>
+*/
+#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c
+#define CE_STAT_DESC_3_FW_METADATA_LSB 0
+#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff
+
+/* Description CE_STAT_DESC_3_CE_RES_7
+
+ Reserved
+
+ <legal all>
+*/
+#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c
+#define CE_STAT_DESC_3_CE_RES_7_LSB 16
+#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000
+
+/* Description CE_STAT_DESC_3_RING_ID
+
+ The buffer pointer ring ID.
+
+ 0 refers to the IDLE ring
+
+ 1 - N refers to other rings
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+*/
+#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c
+#define CE_STAT_DESC_3_RING_ID_LSB 20
+#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000
+
+/* Description CE_STAT_DESC_3_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
+#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28
+#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _CE_STAT_DESC_H_
diff --git a/hw/qca5018/com_dtypes.h b/hw/qca5018/com_dtypes.h
new file mode 100644
index 0000000..9e0c577
--- /dev/null
+++ b/hw/qca5018/com_dtypes.h
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+/**
+ @file com_dtypes.h
+ @brief This header file contains general data types that are of use to all
+ modules.
+
+*/
+/*===========================================================================
+NOTE: The @brief description and any detailed descriptions above do not appear
+ in the PDF.
+
+ The Utility_Services_API_mainpage.dox file contains all file/group
+ descriptions that are in the output PDF generated using Doxygen and
+ Latex. To edit or update any of the file/group text in the PDF, edit
+ the Utility_Services_API_mainpage.dox file or contact Tech Pubs.
+
+ The above description for this file is part of the "utils_services"
+ group description in the Utility_Services_API_mainpage.dox file.
+===========================================================================*/
+/*===========================================================================
+
+ S T A N D A R D D E C L A R A T I O N S
+
+DESCRIPTION
+ This header file contains general data types that are of use to all modules.
+ The values or definitions are dependent on the specified
+ target. T_WINNT specifies Windows NT based targets, otherwise the
+ default is for ARM targets.
+
+ T_WINNT Software is hosted on an NT platforn, triggers macro and
+ type definitions, unlike definition above which triggers
+ actual OS calls
+===========================================================================*/
+
+
+/*===========================================================================
+
+ EDIT HISTORY FOR FILE
+
+This section contains comments describing changes made to this file.
+Notice that changes are listed in reverse chronological order.
+
+$Header: //depot/prj/qca/lithium3/wcss/maple_verif/native/register/include/com_dtypes.h#1 $
+
+when who what, where, why
+-------- --- ----------------------------------------------------------
+03/21/11 llg (Tech Pubs) Edited/added Doxygen comments and markup.
+11/09/10 EBR Doxygenated file.
+09/15/09 pc Created file.
+===========================================================================*/
+
+
+/*===========================================================================
+
+ Data Declarations
+
+===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* For NT apps we want to use the Win32 definitions and/or those
+ supplied by the Win32 compiler for things like NULL, MAX, MIN
+ abs, labs, etc.
+*/
+#ifdef T_WINNT
+ #ifndef WIN32
+ #define WIN32
+ #endif
+ #include <stdlib.h>
+#endif
+
+/* ------------------------------------------------------------------------
+** Constants
+** ------------------------------------------------------------------------ */
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+/** @addtogroup utils_services
+@{ */
+
+/** @name Macros for Common Data Types
+@{ */
+#define TRUE 1 /**< Boolean TRUE value. */
+#define FALSE 0 /**< Boolean FALSE value. */
+
+#define ON 1 /**< ON value. */
+#define OFF 0 /**< OFF value. */
+
+#ifndef NULL
+ #define NULL 0 /**< NULL value. */
+#endif
+/** @} */ /* end_name_group Macros for Common Data Types */
+
+/* -----------------------------------------------------------------------
+** Standard Types
+** ----------------------------------------------------------------------- */
+
+/** @} */ /* end_addtogroup utils_services */
+
+/* The following definitions are the same across platforms. This first
+ group are the sanctioned types.
+*/
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+/** @addtogroup utils_services
+@{ */
+/** Boolean value type.
+*/
+typedef unsigned char boolean;
+#define _BOOLEAN_DEFINED
+#endif
+
+/** @cond
+*/
+#if defined(DALSTDDEF_H) /* guards against a known re-definer */
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif /* #if !defined(DALSTDDEF_H) */
+/** @endcond */
+
+#ifndef _UINT32_DEFINED
+/** Unsigned 32-bit value.
+*/
+typedef unsigned long int uint32;
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+/** Unsigned 16-bit value.
+*/
+typedef unsigned short uint16;
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+/** Unsigned 8-bit value.
+*/
+typedef unsigned char uint8;
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+/** Signed 32-bit value.
+*/
+typedef signed long int int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+/** Signed 16-bit value.
+*/
+typedef signed short int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+/** Signed 8-bit value.
+*/
+typedef signed char int8;
+#define _INT8_DEFINED
+#endif
+
+/** @cond
+*/
+/* This group are the deprecated types. Their use should be
+** discontinued and new code should use the types above
+*/
+#ifndef _BYTE_DEFINED
+/** DEPRECATED: Unsigned 8 bit value type.
+*/
+typedef unsigned char byte;
+#define _BYTE_DEFINED
+#endif
+
+/** DEPRECATED: Unsinged 16 bit value type.
+*/
+typedef unsigned short word;
+/** DEPRECATED: Unsigned 32 bit value type.
+*/
+typedef unsigned long dword;
+
+/** DEPRECATED: Unsigned 8 bit value type.
+*/
+typedef unsigned char uint1;
+/** DEPRECATED: Unsigned 16 bit value type.
+*/
+typedef unsigned short uint2;
+/** DEPRECATED: Unsigned 32 bit value type.
+*/
+typedef unsigned long uint4;
+
+/** DEPRECATED: Signed 8 bit value type.
+*/
+typedef signed char int1;
+/** DEPRECATED: Signed 16 bit value type.
+*/
+typedef signed short int2;
+/** DEPRECATED: Signed 32 bit value type.
+*/
+typedef long int int4;
+
+/** DEPRECATED: Signed 32 bit value.
+*/
+typedef signed long sint31;
+/** DEPRECATED: Signed 16 bit value.
+*/
+typedef signed short sint15;
+/** DEPRECATED: Signed 8 bit value.
+*/
+typedef signed char sint7;
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32 Word32 ;
+typedef int16 Word16 ;
+typedef uint8 UWord8 ;
+typedef int8 Word8 ;
+typedef int32 Vect32 ;
+/** @endcond */
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+ /* Non WinNT Targets */
+ #ifndef _INT64_DEFINED
+ /** Signed 64-bit value.
+ */
+ typedef long long int64;
+ #define _INT64_DEFINED
+ #endif
+ #ifndef _UINT64_DEFINED
+ /** Unsigned 64-bit value.
+ */
+ typedef unsigned long long uint64;
+ #define _UINT64_DEFINED
+ #endif
+#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */
+ /* WINNT or SOLARIS based targets */
+ #if (defined __GNUC__)
+ #ifndef _INT64_DEFINED
+ typedef long long int64;
+ #define _INT64_DEFINED
+ #endif
+ #ifndef _UINT64_DEFINED
+ typedef unsigned long long uint64;
+ #define _UINT64_DEFINED
+ #endif
+ #else
+ typedef __int64 int64; /* Signed 64-bit value */
+ #ifndef _UINT64_DEFINED
+ typedef unsigned __int64 uint64; /* Unsigned 64-bit value */
+ #define _UINT64_DEFINED
+ #endif
+ #endif
+#endif /* T_WINNT */
+
+#endif /* _ARM_ASM_ */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */ /* end_addtogroup utils_services */
+#endif /* COM_DTYPES_H */
diff --git a/hw/qca5018/he_sig_a_mu_dl_info.h b/hw/qca5018/he_sig_a_mu_dl_info.h
new file mode 100644
index 0000000..51bfbfa
--- /dev/null
+++ b/hw/qca5018/he_sig_a_mu_dl_info.h
@@ -0,0 +1,686 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HE_SIG_A_MU_DL_INFO_H_
+#define _HE_SIG_A_MU_DL_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 dl_ul_flag[0], mcs_of_sig_b[3:1], dcm_of_sig_b[4], bss_color_id[10:5], spatial_reuse[14:11], transmit_bw[17:15], num_sig_b_symbols[21:18], comp_mode_sig_b[22], cp_ltf_size[24:23], doppler_indication[25], reserved_0a[31:26]
+// 1 txop_duration[6:0], reserved_1a[7], num_ltf_symbols[10:8], ldpc_extra_symbol[11], stbc[12], packet_extension_a_factor[14:13], packet_extension_pe_disambiguity[15], crc[19:16], tail[25:20], reserved_1b[31:26]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2
+
+struct he_sig_a_mu_dl_info {
+ uint32_t dl_ul_flag : 1, //[0]
+ mcs_of_sig_b : 3, //[3:1]
+ dcm_of_sig_b : 1, //[4]
+ bss_color_id : 6, //[10:5]
+ spatial_reuse : 4, //[14:11]
+ transmit_bw : 3, //[17:15]
+ num_sig_b_symbols : 4, //[21:18]
+ comp_mode_sig_b : 1, //[22]
+ cp_ltf_size : 2, //[24:23]
+ doppler_indication : 1, //[25]
+ reserved_0a : 6; //[31:26]
+ uint32_t txop_duration : 7, //[6:0]
+ reserved_1a : 1, //[7]
+ num_ltf_symbols : 3, //[10:8]
+ ldpc_extra_symbol : 1, //[11]
+ stbc : 1, //[12]
+ packet_extension_a_factor : 2, //[14:13]
+ packet_extension_pe_disambiguity: 1, //[15]
+ crc : 4, //[19:16]
+ tail : 6, //[25:20]
+ reserved_1b : 6; //[31:26]
+};
+
+/*
+
+dl_ul_flag
+
+ Differentiates between DL and UL transmission
+
+
+
+ <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
+
+ <enum 1 DL_UL_FLAG_IS_UL>
+
+ NOTE: This is unsupported for HE MU format (including
+ MU_SU) Tx in Napier and Hastings80.
+
+ <legal all>
+
+mcs_of_sig_b
+
+ Indicates the MCS of HE-SIG-B
+
+ <legal 0-5>
+
+dcm_of_sig_b
+
+ Indicates whether dual sub-carrier modulation is applied
+ to HE-SIG-B
+
+
+
+ 0: No DCM for HE_SIG_B
+
+ 1: DCM for HE_SIG_B
+
+ <legal all>
+
+bss_color_id
+
+ BSS color ID
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+
+spatial_reuse
+
+ Spatial reuse
+
+
+
+ For 20MHz one SR field corresponding to entire 20MHz
+ (other 3 fields indicate identical values)
+
+ For 40MHz two SR fields for each 20MHz (other 2 fields
+ indicate identical values)
+
+ For 80MHz four SR fields for each 20MHz
+
+ For 160MHz four SR fields for each 40MHz
+
+ <legal all>
+
+transmit_bw
+
+ Bandwidth of the PPDU.
+
+
+
+ <enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble
+ puncturing mode
+
+ <enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz
+ non-preamble puncturing mode
+
+ <enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble
+ puncturing in 80 MHz, where in the preamble only the
+ secondary 20 MHz is punctured
+
+ <enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for
+ preamble puncturing in 80 MHz, where in the preamble only
+ one of the two 20 MHz sub-channels in secondary 40 MHz is
+ punctured.
+
+ <enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble
+ puncturing in 160 MHz or 80+80 MHz, where in the primary 80
+ MHz of the preamble only the secondary 20 MHz is punctured.
+
+ <enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for
+ preamble puncturing in 160 MHz or 80+80 MHz, where in the
+ primary 80 MHz of the preamble the primary 40 MHz is
+ present.
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal 0-7>
+
+num_sig_b_symbols
+
+ Number of symbols
+
+
+
+ For OFDMA, the actual number of symbols is 1 larger then
+ indicated in this field.
+
+
+
+ For MU-MIMO this is equal to the number of users - 1:
+ the following encoding is used:
+
+ 1 => 2 users
+
+ 2 => 3 users
+
+ Etc.
+
+
+
+ <legal all>
+
+comp_mode_sig_b
+
+ Indicates the compression mode of HE-SIG-B
+
+
+
+ 0: Regular [uncomp mode]
+
+ 1: compressed mode (full-BW MU-MIMO only)
+
+ <legal all>
+
+cp_ltf_size
+
+ Indicates the CP and HE-LTF type
+
+
+
+ <enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
+
+ <enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
+
+ <enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
+
+ <enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
+
+
+
+
+
+ <legal all>
+
+doppler_indication
+
+ 0: No Doppler support
+
+ 1: Doppler support
+
+ <legal all>
+
+reserved_0a
+
+ <legal 0>
+
+txop_duration
+
+ Indicates the remaining time in the current TXOP
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+
+reserved_1a
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+
+num_ltf_symbols
+
+ Indicates the number of HE-LTF symbols
+
+
+
+ 0: 1 LTF
+
+ 1: 2 LTFs
+
+ 2: 4 LTFs
+
+ 3: 6 LTFs
+
+ 4: 8 LTFs
+
+
+
+ <legal all>
+
+ldpc_extra_symbol
+
+ If LDPC,
+
+ 0: LDPC extra symbol not present
+
+ 1: LDPC extra symbol present
+
+ Else
+
+ Set to 1
+
+ <legal all>
+
+stbc
+
+ Indicates whether STBC is applied
+
+ 0: No STBC
+
+ 1: STBC
+
+ <legal all>
+
+packet_extension_a_factor
+
+ the packet extension duration of the trigger-based PPDU
+ response with these two bits indicating the a-factor
+
+
+
+ <enum 0 a_factor_4>
+
+ <enum 1 a_factor_1>
+
+ <enum 2 a_factor_2>
+
+ <enum 3 a_factor_3>
+
+
+
+ <legal all>
+
+packet_extension_pe_disambiguity
+
+ the packet extension duration of the trigger-based PPDU
+ response with this bit indicating the PE-Disambiguity
+
+ <legal all>
+
+crc
+
+ CRC for HE-SIG-A contents.
+
+ <legal all>
+
+tail
+
+ <legal 0>
+
+reserved_1b
+
+ <legal 0>
+*/
+
+
+/* Description HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG
+
+ Differentiates between DL and UL transmission
+
+
+
+ <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
+
+ <enum 1 DL_UL_FLAG_IS_UL>
+
+ NOTE: This is unsupported for HE MU format (including
+ MU_SU) Tx in Napier and Hastings80.
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_LSB 0
+#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_MASK 0x00000001
+
+/* Description HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B
+
+ Indicates the MCS of HE-SIG-B
+
+ <legal 0-5>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_LSB 1
+#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_MASK 0x0000000e
+
+/* Description HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B
+
+ Indicates whether dual sub-carrier modulation is applied
+ to HE-SIG-B
+
+
+
+ 0: No DCM for HE_SIG_B
+
+ 1: DCM for HE_SIG_B
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_LSB 4
+#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_MASK 0x00000010
+
+/* Description HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID
+
+ BSS color ID
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_LSB 5
+#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_MASK 0x000007e0
+
+/* Description HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE
+
+ Spatial reuse
+
+
+
+ For 20MHz one SR field corresponding to entire 20MHz
+ (other 3 fields indicate identical values)
+
+ For 40MHz two SR fields for each 20MHz (other 2 fields
+ indicate identical values)
+
+ For 80MHz four SR fields for each 20MHz
+
+ For 160MHz four SR fields for each 40MHz
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_LSB 11
+#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_MASK 0x00007800
+
+/* Description HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW
+
+ Bandwidth of the PPDU.
+
+
+
+ <enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble
+ puncturing mode
+
+ <enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz
+ non-preamble puncturing mode
+
+ <enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble
+ puncturing in 80 MHz, where in the preamble only the
+ secondary 20 MHz is punctured
+
+ <enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for
+ preamble puncturing in 80 MHz, where in the preamble only
+ one of the two 20 MHz sub-channels in secondary 40 MHz is
+ punctured.
+
+ <enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble
+ puncturing in 160 MHz or 80+80 MHz, where in the primary 80
+ MHz of the preamble only the secondary 20 MHz is punctured.
+
+ <enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for
+ preamble puncturing in 160 MHz or 80+80 MHz, where in the
+ primary 80 MHz of the preamble the primary 40 MHz is
+ present.
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal 0-7>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_LSB 15
+#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_MASK 0x00038000
+
+/* Description HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS
+
+ Number of symbols
+
+
+
+ For OFDMA, the actual number of symbols is 1 larger then
+ indicated in this field.
+
+
+
+ For MU-MIMO this is equal to the number of users - 1:
+ the following encoding is used:
+
+ 1 => 2 users
+
+ 2 => 3 users
+
+ Etc.
+
+
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_LSB 18
+#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+/* Description HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B
+
+ Indicates the compression mode of HE-SIG-B
+
+
+
+ 0: Regular [uncomp mode]
+
+ 1: compressed mode (full-BW MU-MIMO only)
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_LSB 22
+#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_MASK 0x00400000
+
+/* Description HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE
+
+ Indicates the CP and HE-LTF type
+
+
+
+ <enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
+
+ <enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
+
+ <enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
+
+ <enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
+
+
+
+
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_LSB 23
+#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_MASK 0x01800000
+
+/* Description HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION
+
+ 0: No Doppler support
+
+ 1: Doppler support
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_LSB 25
+#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_MASK 0x02000000
+
+/* Description HE_SIG_A_MU_DL_INFO_0_RESERVED_0A
+
+ <legal 0>
+*/
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_LSB 26
+#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_MASK 0xfc000000
+
+/* Description HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION
+
+ Indicates the remaining time in the current TXOP
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_LSB 0
+#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_MASK 0x0000007f
+
+/* Description HE_SIG_A_MU_DL_INFO_1_RESERVED_1A
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_LSB 7
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_MASK 0x00000080
+
+/* Description HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS
+
+ Indicates the number of HE-LTF symbols
+
+
+
+ 0: 1 LTF
+
+ 1: 2 LTFs
+
+ 2: 4 LTFs
+
+ 3: 6 LTFs
+
+ 4: 8 LTFs
+
+
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_LSB 8
+#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+/* Description HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL
+
+ If LDPC,
+
+ 0: LDPC extra symbol not present
+
+ 1: LDPC extra symbol present
+
+ Else
+
+ Set to 1
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_LSB 11
+#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+/* Description HE_SIG_A_MU_DL_INFO_1_STBC
+
+ Indicates whether STBC is applied
+
+ 0: No STBC
+
+ 1: STBC
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_STBC_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_STBC_LSB 12
+#define HE_SIG_A_MU_DL_INFO_1_STBC_MASK 0x00001000
+
+/* Description HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR
+
+ the packet extension duration of the trigger-based PPDU
+ response with these two bits indicating the a-factor
+
+
+
+ <enum 0 a_factor_4>
+
+ <enum 1 a_factor_1>
+
+ <enum 2 a_factor_2>
+
+ <enum 3 a_factor_3>
+
+
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+/* Description HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY
+
+ the packet extension duration of the trigger-based PPDU
+ response with this bit indicating the PE-Disambiguity
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+/* Description HE_SIG_A_MU_DL_INFO_1_CRC
+
+ CRC for HE-SIG-A contents.
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_CRC_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_CRC_LSB 16
+#define HE_SIG_A_MU_DL_INFO_1_CRC_MASK 0x000f0000
+
+/* Description HE_SIG_A_MU_DL_INFO_1_TAIL
+
+ <legal 0>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_LSB 20
+#define HE_SIG_A_MU_DL_INFO_1_TAIL_MASK 0x03f00000
+
+/* Description HE_SIG_A_MU_DL_INFO_1_RESERVED_1B
+
+ <legal 0>
+*/
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_OFFSET 0x00000004
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_LSB 26
+#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_MASK 0xfc000000
+
+
+#endif // _HE_SIG_A_MU_DL_INFO_H_
diff --git a/hw/qca5018/he_sig_a_mu_ul_info.h b/hw/qca5018/he_sig_a_mu_ul_info.h
new file mode 100644
index 0000000..bf9888a
--- /dev/null
+++ b/hw/qca5018/he_sig_a_mu_ul_info.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HE_SIG_A_MU_UL_INFO_H_
+#define _HE_SIG_A_MU_UL_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 format_indication[0], bss_color_id[6:1], spatial_reuse[22:7], reserved_0a[23], transmit_bw[25:24], reserved_0b[31:26]
+// 1 txop_duration[6:0], reserved_1a[15:7], crc[19:16], tail[25:20], reserved_1b[31:26]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2
+
+struct he_sig_a_mu_ul_info {
+ uint32_t format_indication : 1, //[0]
+ bss_color_id : 6, //[6:1]
+ spatial_reuse : 16, //[22:7]
+ reserved_0a : 1, //[23]
+ transmit_bw : 2, //[25:24]
+ reserved_0b : 6; //[31:26]
+ uint32_t txop_duration : 7, //[6:0]
+ reserved_1a : 9, //[15:7]
+ crc : 4, //[19:16]
+ tail : 6, //[25:20]
+ reserved_1b : 6; //[31:26]
+};
+
+/*
+
+format_indication
+
+ Indicates whether the transmission is SU PPDU or a
+ trigger based UL MU PDDU
+
+ <enum 0 HE_SIGA_FORMAT_HE_TRIG>
+
+ <enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
+
+ <legal all>
+
+bss_color_id
+
+ BSS color ID
+
+ <legal all>
+
+spatial_reuse
+
+ Spatial reuse
+
+
+
+ <legal all>
+
+reserved_0a
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+
+transmit_bw
+
+ Bandwidth of the PPDU.
+
+
+
+ <enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
+
+ <enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal 0-3>
+
+reserved_0b
+
+ <legal 0>
+
+txop_duration
+
+ Indicates the remaining time in the current TXOP <legal
+ all>
+
+reserved_1a
+
+ Set to value indicated in the trigger frame
+
+ <legal 255>
+
+crc
+
+ CRC for HE-SIG-A contents.
+
+ This CRC may also cover some fields of L-SIG (TBD)
+
+ <legal all>
+
+tail
+
+ BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
+ used
+
+ <legal 0>
+
+reserved_1b
+
+ <legal 0>
+*/
+
+
+/* Description HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION
+
+ Indicates whether the transmission is SU PPDU or a
+ trigger based UL MU PDDU
+
+ <enum 0 HE_SIGA_FORMAT_HE_TRIG>
+
+ <enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_LSB 0
+#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_MASK 0x00000001
+
+/* Description HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID
+
+ BSS color ID
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_LSB 1
+#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_MASK 0x0000007e
+
+/* Description HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE
+
+ Spatial reuse
+
+
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_LSB 7
+#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_MASK 0x007fff80
+
+/* Description HE_SIG_A_MU_UL_INFO_0_RESERVED_0A
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+*/
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_LSB 23
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_MASK 0x00800000
+
+/* Description HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW
+
+ Bandwidth of the PPDU.
+
+
+
+ <enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
+
+ <enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal 0-3>
+*/
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_LSB 24
+#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_MASK 0x03000000
+
+/* Description HE_SIG_A_MU_UL_INFO_0_RESERVED_0B
+
+ <legal 0>
+*/
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_LSB 26
+#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_MASK 0xfc000000
+
+/* Description HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION
+
+ Indicates the remaining time in the current TXOP <legal
+ all>
+*/
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_LSB 0
+#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_MASK 0x0000007f
+
+/* Description HE_SIG_A_MU_UL_INFO_1_RESERVED_1A
+
+ Set to value indicated in the trigger frame
+
+ <legal 255>
+*/
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_LSB 7
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_MASK 0x0000ff80
+
+/* Description HE_SIG_A_MU_UL_INFO_1_CRC
+
+ CRC for HE-SIG-A contents.
+
+ This CRC may also cover some fields of L-SIG (TBD)
+
+ <legal all>
+*/
+#define HE_SIG_A_MU_UL_INFO_1_CRC_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_CRC_LSB 16
+#define HE_SIG_A_MU_UL_INFO_1_CRC_MASK 0x000f0000
+
+/* Description HE_SIG_A_MU_UL_INFO_1_TAIL
+
+ BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
+ used
+
+ <legal 0>
+*/
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_LSB 20
+#define HE_SIG_A_MU_UL_INFO_1_TAIL_MASK 0x03f00000
+
+/* Description HE_SIG_A_MU_UL_INFO_1_RESERVED_1B
+
+ <legal 0>
+*/
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_OFFSET 0x00000004
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_LSB 26
+#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_MASK 0xfc000000
+
+
+#endif // _HE_SIG_A_MU_UL_INFO_H_
diff --git a/hw/qca5018/he_sig_a_su_info.h b/hw/qca5018/he_sig_a_su_info.h
new file mode 100644
index 0000000..34ad0ad
--- /dev/null
+++ b/hw/qca5018/he_sig_a_su_info.h
@@ -0,0 +1,832 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HE_SIG_A_SU_INFO_H_
+#define _HE_SIG_A_SU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 format_indication[0], beam_change[1], dl_ul_flag[2], transmit_mcs[6:3], dcm[7], bss_color_id[13:8], reserved_0a[14], spatial_reuse[18:15], transmit_bw[20:19], cp_ltf_size[22:21], nsts[25:23], reserved_0b[31:26]
+// 1 txop_duration[6:0], coding[7], ldpc_extra_symbol[8], stbc[9], txbf[10], packet_extension_a_factor[12:11], packet_extension_pe_disambiguity[13], reserved_1a[14], doppler_indication[15], crc[19:16], tail[25:20], dot11ax_su_extended[26], dot11ax_ext_ru_size[30:27], rx_ndp[31]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2
+
+struct he_sig_a_su_info {
+ uint32_t format_indication : 1, //[0]
+ beam_change : 1, //[1]
+ dl_ul_flag : 1, //[2]
+ transmit_mcs : 4, //[6:3]
+ dcm : 1, //[7]
+ bss_color_id : 6, //[13:8]
+ reserved_0a : 1, //[14]
+ spatial_reuse : 4, //[18:15]
+ transmit_bw : 2, //[20:19]
+ cp_ltf_size : 2, //[22:21]
+ nsts : 3, //[25:23]
+ reserved_0b : 6; //[31:26]
+ uint32_t txop_duration : 7, //[6:0]
+ coding : 1, //[7]
+ ldpc_extra_symbol : 1, //[8]
+ stbc : 1, //[9]
+ txbf : 1, //[10]
+ packet_extension_a_factor : 2, //[12:11]
+ packet_extension_pe_disambiguity: 1, //[13]
+ reserved_1a : 1, //[14]
+ doppler_indication : 1, //[15]
+ crc : 4, //[19:16]
+ tail : 6, //[25:20]
+ dot11ax_su_extended : 1, //[26]
+ dot11ax_ext_ru_size : 4, //[30:27]
+ rx_ndp : 1; //[31]
+};
+
+/*
+
+format_indication
+
+ <enum 0 HE_SIGA_FORMAT_HE_TRIG>
+
+ <enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
+
+ <legal all>
+
+beam_change
+
+ Indicates whether spatial mapping is changed between
+ legacy and HE portion of preamble. If not, channel
+ estimation can include legacy preamble to improve accuracy
+
+ <legal all>
+
+dl_ul_flag
+
+ Differentiates between DL and UL transmission
+
+
+
+ <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
+
+ <enum 1 DL_UL_FLAG_IS_UL>
+
+ <legal all>
+
+transmit_mcs
+
+ Indicates the data MCS
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+
+dcm
+
+
+ 0: No DCM
+
+ 1:DCM
+
+ <legal all>
+
+bss_color_id
+
+ BSS color ID
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+
+reserved_0a
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+
+spatial_reuse
+
+ Spatial reuse
+
+
+
+ For 20MHz one SR field corresponding to entire 20MHz
+ (other 3 fields indicate identical values)
+
+ For 40MHz two SR fields for each 20MHz (other 2 fields
+ indicate identical values)
+
+ For 80MHz four SR fields for each 20MHz
+
+ For 160MHz four SR fields for each 40MHz
+
+ <legal all>
+
+transmit_bw
+
+ Bandwidth of the PPDU.
+
+
+
+ For HE SU PPDU
+
+
+ <enum 0 HE_SIG_A_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_BW80> 80 Mhz
+
+ <enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
+
+
+
+ For HE Extended Range SU PPDU
+
+ Set to 0 for 242-tone RU
+ Set to 1 for right 106-tone RU within the primary 20 MHz
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal all>
+
+cp_ltf_size
+
+ Indicates the CP and HE-LTF type
+
+
+
+
+
+ <enum 3 FourX_LTF_0_8CP_3_2CP>
+
+ When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
+
+ When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
+ In this scenario, Neither DCM nor STBC is applied to HE data
+ field.
+
+
+ NOTE:
+
+
+ If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
+
+ 0 = 1xLTF + 0.4 usec
+
+ 1 = 2xLTF + 0.4 usec
+
+ 2~3 = Reserved
+
+
+
+ <legal all>
+
+nsts
+
+
+
+
+ For HE SU PPDU
+
+
+
+ For HE Extended Range PPDU
+
+ <legal all>
+
+reserved_0b
+
+ <legal 0>
+
+txop_duration
+
+ Indicates the remaining time in the current TXOP
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+
+coding
+
+ Distinguishes between BCC and LDPC coding.
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+
+ldpc_extra_symbol
+
+ If LDPC,
+
+ 0: LDPC extra symbol not present
+
+ 1: LDPC extra symbol present
+
+ Else
+
+ Set to 1
+
+ <legal all>
+
+stbc
+
+ Indicates whether STBC is applied
+
+ 0: No STBC
+
+ 1: STBC
+
+ <legal all>
+
+txbf
+
+ Indicates whether beamforming is applied
+
+ 0: No beamforming
+
+ 1: beamforming
+
+ <legal all>
+
+packet_extension_a_factor
+
+ Common trigger info
+
+
+
+ the packet extension duration of the trigger-based PPDU
+ response with these two bits indicating the a-factor
+
+
+
+ <enum 0 a_factor_4>
+
+ <enum 1 a_factor_1>
+
+ <enum 2 a_factor_2>
+
+ <enum 3 a_factor_3>
+
+
+
+ <legal all>
+
+packet_extension_pe_disambiguity
+
+ Common trigger info
+
+
+
+ the packet extension duration of the trigger-based PPDU
+ response with this bit indicating the PE-Disambiguity
+
+ <legal all>
+
+reserved_1a
+
+ Note: per standard, set to 1
+
+ <legal 1>
+
+doppler_indication
+
+ 0: No Doppler support
+
+ 1: Doppler support
+
+ <legal all>
+
+crc
+
+ CRC for HE-SIG-A contents.
+
+ <legal all>
+
+tail
+
+ <legal 0>
+
+dot11ax_su_extended
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:
+
+ On RX side, evaluated by MAC HW. This is the only way
+ for MAC RX to know that this was an HE_SIG_A_SU received in
+ 'extended' format
+
+
+
+
+ <legal all>
+
+dot11ax_ext_ru_size
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:
+
+ Field only contains valid info when dot11ax_su_extended
+ is set.
+
+
+
+ On RX side, evaluated by MAC HW. This is the only way
+ for MAC RX to know what the number of based RUs was in this
+ extended range reception. It is used by the MAC to determine
+ the RU size for the response...
+
+ <legal all>
+
+rx_ndp
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:Valid on RX side only, and looked at by MAC HW
+
+
+
+ When set, PHY has received (expected) NDP frame
+
+ <legal all>
+*/
+
+
+/* Description HE_SIG_A_SU_INFO_0_FORMAT_INDICATION
+
+ <enum 0 HE_SIGA_FORMAT_HE_TRIG>
+
+ <enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_LSB 0
+#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_MASK 0x00000001
+
+/* Description HE_SIG_A_SU_INFO_0_BEAM_CHANGE
+
+ Indicates whether spatial mapping is changed between
+ legacy and HE portion of preamble. If not, channel
+ estimation can include legacy preamble to improve accuracy
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_LSB 1
+#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_MASK 0x00000002
+
+/* Description HE_SIG_A_SU_INFO_0_DL_UL_FLAG
+
+ Differentiates between DL and UL transmission
+
+
+
+ <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
+
+ <enum 1 DL_UL_FLAG_IS_UL>
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_LSB 2
+#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_MASK 0x00000004
+
+/* Description HE_SIG_A_SU_INFO_0_TRANSMIT_MCS
+
+ Indicates the data MCS
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_LSB 3
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_MASK 0x00000078
+
+/* Description HE_SIG_A_SU_INFO_0_DCM
+
+
+ 0: No DCM
+
+ 1:DCM
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_DCM_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_DCM_LSB 7
+#define HE_SIG_A_SU_INFO_0_DCM_MASK 0x00000080
+
+/* Description HE_SIG_A_SU_INFO_0_BSS_COLOR_ID
+
+ BSS color ID
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_LSB 8
+#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_MASK 0x00003f00
+
+/* Description HE_SIG_A_SU_INFO_0_RESERVED_0A
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+*/
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_LSB 14
+#define HE_SIG_A_SU_INFO_0_RESERVED_0A_MASK 0x00004000
+
+/* Description HE_SIG_A_SU_INFO_0_SPATIAL_REUSE
+
+ Spatial reuse
+
+
+
+ For 20MHz one SR field corresponding to entire 20MHz
+ (other 3 fields indicate identical values)
+
+ For 40MHz two SR fields for each 20MHz (other 2 fields
+ indicate identical values)
+
+ For 80MHz four SR fields for each 20MHz
+
+ For 160MHz four SR fields for each 40MHz
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_LSB 15
+#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_MASK 0x00078000
+
+/* Description HE_SIG_A_SU_INFO_0_TRANSMIT_BW
+
+ Bandwidth of the PPDU.
+
+
+
+ For HE SU PPDU
+
+
+ <enum 0 HE_SIG_A_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_BW80> 80 Mhz
+
+ <enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
+
+
+
+ For HE Extended Range SU PPDU
+
+ Set to 0 for 242-tone RU
+ Set to 1 for right 106-tone RU within the primary 20 MHz
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_LSB 19
+#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_MASK 0x00180000
+
+/* Description HE_SIG_A_SU_INFO_0_CP_LTF_SIZE
+
+ Indicates the CP and HE-LTF type
+
+
+
+
+ <enum 3 FourX_LTF_0_8CP_3_2CP>
+
+ When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
+
+ When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
+ In this scenario, Neither DCM nor STBC is applied to HE data
+ field.
+
+
+ NOTE:
+
+
+ If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
+
+ 0 = 1xLTF + 0.4 usec
+
+ 1 = 2xLTF + 0.4 usec
+
+ 2~3 = Reserved
+
+
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_LSB 21
+#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_MASK 0x00600000
+
+/* Description HE_SIG_A_SU_INFO_0_NSTS
+
+
+
+
+ For HE SU PPDU
+
+
+
+ For HE Extended Range PPDU
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_0_NSTS_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_NSTS_LSB 23
+#define HE_SIG_A_SU_INFO_0_NSTS_MASK 0x03800000
+
+/* Description HE_SIG_A_SU_INFO_0_RESERVED_0B
+
+ <legal 0>
+*/
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_LSB 26
+#define HE_SIG_A_SU_INFO_0_RESERVED_0B_MASK 0xfc000000
+
+/* Description HE_SIG_A_SU_INFO_1_TXOP_DURATION
+
+ Indicates the remaining time in the current TXOP
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_LSB 0
+#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_MASK 0x0000007f
+
+/* Description HE_SIG_A_SU_INFO_1_CODING
+
+ Distinguishes between BCC and LDPC coding.
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_CODING_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_CODING_LSB 7
+#define HE_SIG_A_SU_INFO_1_CODING_MASK 0x00000080
+
+/* Description HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL
+
+ If LDPC,
+
+ 0: LDPC extra symbol not present
+
+ 1: LDPC extra symbol present
+
+ Else
+
+ Set to 1
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_LSB 8
+#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000100
+
+/* Description HE_SIG_A_SU_INFO_1_STBC
+
+ Indicates whether STBC is applied
+
+ 0: No STBC
+
+ 1: STBC
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_STBC_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_STBC_LSB 9
+#define HE_SIG_A_SU_INFO_1_STBC_MASK 0x00000200
+
+/* Description HE_SIG_A_SU_INFO_1_TXBF
+
+ Indicates whether beamforming is applied
+
+ 0: No beamforming
+
+ 1: beamforming
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_TXBF_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_TXBF_LSB 10
+#define HE_SIG_A_SU_INFO_1_TXBF_MASK 0x00000400
+
+/* Description HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR
+
+ Common trigger info
+
+
+
+ the packet extension duration of the trigger-based PPDU
+ response with these two bits indicating the a-factor
+
+
+
+ <enum 0 a_factor_4>
+
+ <enum 1 a_factor_1>
+
+ <enum 2 a_factor_2>
+
+ <enum 3 a_factor_3>
+
+
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+/* Description HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY
+
+ Common trigger info
+
+
+
+ the packet extension duration of the trigger-based PPDU
+ response with this bit indicating the PE-Disambiguity
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+/* Description HE_SIG_A_SU_INFO_1_RESERVED_1A
+
+ Note: per standard, set to 1
+
+ <legal 1>
+*/
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_LSB 14
+#define HE_SIG_A_SU_INFO_1_RESERVED_1A_MASK 0x00004000
+
+/* Description HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION
+
+ 0: No Doppler support
+
+ 1: Doppler support
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_LSB 15
+#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_MASK 0x00008000
+
+/* Description HE_SIG_A_SU_INFO_1_CRC
+
+ CRC for HE-SIG-A contents.
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_CRC_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_CRC_LSB 16
+#define HE_SIG_A_SU_INFO_1_CRC_MASK 0x000f0000
+
+/* Description HE_SIG_A_SU_INFO_1_TAIL
+
+ <legal 0>
+*/
+#define HE_SIG_A_SU_INFO_1_TAIL_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_TAIL_LSB 20
+#define HE_SIG_A_SU_INFO_1_TAIL_MASK 0x03f00000
+
+/* Description HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:
+
+ On RX side, evaluated by MAC HW. This is the only way
+ for MAC RX to know that this was an HE_SIG_A_SU received in
+ 'extended' format
+
+
+
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_LSB 26
+#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+/* Description HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:
+
+ Field only contains valid info when dot11ax_su_extended
+ is set.
+
+
+
+ On RX side, evaluated by MAC HW. This is the only way
+ for MAC RX to know what the number of based RUs was in this
+ extended range reception. It is used by the MAC to determine
+ the RU size for the response...
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_LSB 27
+#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_MASK 0x78000000
+
+/* Description HE_SIG_A_SU_INFO_1_RX_NDP
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:Valid on RX side only, and looked at by MAC HW
+
+
+
+ When set, PHY has received (expected) NDP frame
+
+ <legal all>
+*/
+#define HE_SIG_A_SU_INFO_1_RX_NDP_OFFSET 0x00000004
+#define HE_SIG_A_SU_INFO_1_RX_NDP_LSB 31
+#define HE_SIG_A_SU_INFO_1_RX_NDP_MASK 0x80000000
+
+
+#endif // _HE_SIG_A_SU_INFO_H_
diff --git a/hw/qca5018/he_sig_b1_mu_info.h b/hw/qca5018/he_sig_b1_mu_info.h
new file mode 100644
index 0000000..06901ac
--- /dev/null
+++ b/hw/qca5018/he_sig_b1_mu_info.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HE_SIG_B1_MU_INFO_H_
+#define _HE_SIG_B1_MU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 ru_allocation[7:0], reserved_0[31:8]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1
+
+struct he_sig_b1_mu_info {
+ uint32_t ru_allocation : 8, //[7:0]
+ reserved_0 : 24; //[31:8]
+};
+
+/*
+
+ru_allocation
+
+ RU allocation for the user(s) following this common
+ portion of the SIG
+
+
+
+ For details, refer to RU_TYPE description
+
+ <legal all>
+
+reserved_0
+
+ <legal 0>
+*/
+
+
+/* Description HE_SIG_B1_MU_INFO_0_RU_ALLOCATION
+
+ RU allocation for the user(s) following this common
+ portion of the SIG
+
+
+
+ For details, refer to RU_TYPE description
+
+ <legal all>
+*/
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_OFFSET 0x00000000
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_LSB 0
+#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_MASK 0x000000ff
+
+/* Description HE_SIG_B1_MU_INFO_0_RESERVED_0
+
+ <legal 0>
+*/
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_LSB 8
+#define HE_SIG_B1_MU_INFO_0_RESERVED_0_MASK 0xffffff00
+
+
+#endif // _HE_SIG_B1_MU_INFO_H_
diff --git a/hw/qca5018/he_sig_b2_mu_info.h b/hw/qca5018/he_sig_b2_mu_info.h
new file mode 100644
index 0000000..dbbfd15
--- /dev/null
+++ b/hw/qca5018/he_sig_b2_mu_info.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HE_SIG_B2_MU_INFO_H_
+#define _HE_SIG_B2_MU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 sta_id[10:0], sta_spatial_config[14:11], sta_mcs[18:15], reserved_set_to_1[19], sta_coding[20], reserved_0a[28:21], nsts[31:29]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 1
+
+struct he_sig_b2_mu_info {
+ uint32_t sta_id : 11, //[10:0]
+ sta_spatial_config : 4, //[14:11]
+ sta_mcs : 4, //[18:15]
+ reserved_set_to_1 : 1, //[19]
+ sta_coding : 1, //[20]
+ reserved_0a : 8, //[28:21]
+ nsts : 3; //[31:29]
+};
+
+/*
+
+sta_id
+
+ Identifies the STA that is addressed. Details of STA ID
+ are TBD
+
+sta_spatial_config
+
+ Number of assigned spatial streams and their
+ corresponding index.
+
+ Total number of spatial streams assigned for the MU-MIMO
+ allocation is also signaled.
+
+sta_mcs
+
+ Indicates the data MCS
+
+reserved_set_to_1
+
+ <legal 1>
+
+sta_coding
+
+ Distinguishes between BCC/LDPC
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+
+reserved_0a
+
+ <legal 0>
+
+nsts
+
+ MAC RX side usage only:
+
+ Needed by RXPCU. Provided by PHY so that RXPCU does not
+ need to have the RU number decoding logic.
+
+
+
+ Number of spatial streams for this user
+
+
+
+ <enum 0 1_spatial_stream>Single spatial stream
+
+ <enum 1 2_spatial_streams>2 spatial streams
+
+ <enum 2 3_spatial_streams>3 spatial streams
+
+ <enum 3 4_spatial_streams>4 spatial streams
+
+ <enum 4 5_spatial_streams>5 spatial streams
+
+ <enum 5 6_spatial_streams>6 spatial streams
+
+ <enum 6 7_spatial_streams>7 spatial streams
+
+ <enum 7 8_spatial_streams>8 spatial streams
+*/
+
+
+/* Description HE_SIG_B2_MU_INFO_0_STA_ID
+
+ Identifies the STA that is addressed. Details of STA ID
+ are TBD
+*/
+#define HE_SIG_B2_MU_INFO_0_STA_ID_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_ID_LSB 0
+#define HE_SIG_B2_MU_INFO_0_STA_ID_MASK 0x000007ff
+
+/* Description HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG
+
+ Number of assigned spatial streams and their
+ corresponding index.
+
+ Total number of spatial streams assigned for the MU-MIMO
+ allocation is also signaled.
+*/
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_LSB 11
+#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_MASK 0x00007800
+
+/* Description HE_SIG_B2_MU_INFO_0_STA_MCS
+
+ Indicates the data MCS
+*/
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_LSB 15
+#define HE_SIG_B2_MU_INFO_0_STA_MCS_MASK 0x00078000
+
+/* Description HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1
+
+ <legal 1>
+*/
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_LSB 19
+#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_MASK 0x00080000
+
+/* Description HE_SIG_B2_MU_INFO_0_STA_CODING
+
+ Distinguishes between BCC/LDPC
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+*/
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_LSB 20
+#define HE_SIG_B2_MU_INFO_0_STA_CODING_MASK 0x00100000
+
+/* Description HE_SIG_B2_MU_INFO_0_RESERVED_0A
+
+ <legal 0>
+*/
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_LSB 21
+#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_MASK 0x1fe00000
+
+/* Description HE_SIG_B2_MU_INFO_0_NSTS
+
+ MAC RX side usage only:
+
+ Needed by RXPCU. Provided by PHY so that RXPCU does not
+ need to have the RU number decoding logic.
+
+
+
+ Number of spatial streams for this user
+
+
+
+ <enum 0 1_spatial_stream>Single spatial stream
+
+ <enum 1 2_spatial_streams>2 spatial streams
+
+ <enum 2 3_spatial_streams>3 spatial streams
+
+ <enum 3 4_spatial_streams>4 spatial streams
+
+ <enum 4 5_spatial_streams>5 spatial streams
+
+ <enum 5 6_spatial_streams>6 spatial streams
+
+ <enum 6 7_spatial_streams>7 spatial streams
+
+ <enum 7 8_spatial_streams>8 spatial streams
+*/
+#define HE_SIG_B2_MU_INFO_0_NSTS_OFFSET 0x00000000
+#define HE_SIG_B2_MU_INFO_0_NSTS_LSB 29
+#define HE_SIG_B2_MU_INFO_0_NSTS_MASK 0xe0000000
+
+
+#endif // _HE_SIG_B2_MU_INFO_H_
diff --git a/hw/qca5018/he_sig_b2_ofdma_info.h b/hw/qca5018/he_sig_b2_ofdma_info.h
new file mode 100644
index 0000000..1eb761f
--- /dev/null
+++ b/hw/qca5018/he_sig_b2_ofdma_info.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HE_SIG_B2_OFDMA_INFO_H_
+#define _HE_SIG_B2_OFDMA_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 sta_id[10:0], nsts[13:11], txbf[14], sta_mcs[18:15], sta_dcm[19], sta_coding[20], reserved_0[31:21]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 1
+
+struct he_sig_b2_ofdma_info {
+ uint32_t sta_id : 11, //[10:0]
+ nsts : 3, //[13:11]
+ txbf : 1, //[14]
+ sta_mcs : 4, //[18:15]
+ sta_dcm : 1, //[19]
+ sta_coding : 1, //[20]
+ reserved_0 : 11; //[31:21]
+};
+
+/*
+
+sta_id
+
+ Identifies the STA that is addressed. Details of STA ID
+ are TBD
+
+nsts
+
+ MAC RX side usage only:
+
+
+
+ Number of spatial streams for this user
+
+
+
+ <enum 0 1_spatial_stream>Single spatial stream
+
+ <enum 1 2_spatial_streams>2 spatial streams
+
+ <enum 2 3_spatial_streams>3 spatial streams
+
+ <enum 3 4_spatial_streams>4 spatial streams
+
+ <enum 4 5_spatial_streams>5 spatial streams
+
+ <enum 5 6_spatial_streams>6 spatial streams
+
+ <enum 6 7_spatial_streams>7 spatial streams
+
+ <enum 7 8_spatial_streams>8 spatial streams
+
+txbf
+
+ Indicates whether beamforming is applied
+
+ 0: No beamforming
+
+ 1: beamforming
+
+ <legal all>
+
+sta_mcs
+
+ Indicates the data MCS
+
+sta_dcm
+
+
+ 0: No DCM
+
+ 1:DCM
+
+ <legal all>
+
+sta_coding
+
+ Distinguishes between BCC/LDPC
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+
+reserved_0
+
+ <legal 0>
+*/
+
+
+/* Description HE_SIG_B2_OFDMA_INFO_0_STA_ID
+
+ Identifies the STA that is addressed. Details of STA ID
+ are TBD
+*/
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_LSB 0
+#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_MASK 0x000007ff
+
+/* Description HE_SIG_B2_OFDMA_INFO_0_NSTS
+
+ MAC RX side usage only:
+
+
+
+ Number of spatial streams for this user
+
+
+
+ <enum 0 1_spatial_stream>Single spatial stream
+
+ <enum 1 2_spatial_streams>2 spatial streams
+
+ <enum 2 3_spatial_streams>3 spatial streams
+
+ <enum 3 4_spatial_streams>4 spatial streams
+
+ <enum 4 5_spatial_streams>5 spatial streams
+
+ <enum 5 6_spatial_streams>6 spatial streams
+
+ <enum 6 7_spatial_streams>7 spatial streams
+
+ <enum 7 8_spatial_streams>8 spatial streams
+*/
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_LSB 11
+#define HE_SIG_B2_OFDMA_INFO_0_NSTS_MASK 0x00003800
+
+/* Description HE_SIG_B2_OFDMA_INFO_0_TXBF
+
+ Indicates whether beamforming is applied
+
+ 0: No beamforming
+
+ 1: beamforming
+
+ <legal all>
+*/
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_LSB 14
+#define HE_SIG_B2_OFDMA_INFO_0_TXBF_MASK 0x00004000
+
+/* Description HE_SIG_B2_OFDMA_INFO_0_STA_MCS
+
+ Indicates the data MCS
+*/
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_LSB 15
+#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_MASK 0x00078000
+
+/* Description HE_SIG_B2_OFDMA_INFO_0_STA_DCM
+
+
+ 0: No DCM
+
+ 1:DCM
+
+ <legal all>
+*/
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_LSB 19
+#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_MASK 0x00080000
+
+/* Description HE_SIG_B2_OFDMA_INFO_0_STA_CODING
+
+ Distinguishes between BCC/LDPC
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+*/
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_LSB 20
+#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_MASK 0x00100000
+
+/* Description HE_SIG_B2_OFDMA_INFO_0_RESERVED_0
+
+ <legal 0>
+*/
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_LSB 21
+#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_MASK 0xffe00000
+
+
+#endif // _HE_SIG_B2_OFDMA_INFO_H_
diff --git a/hw/qca5018/ht_sig_info.h b/hw/qca5018/ht_sig_info.h
new file mode 100644
index 0000000..e0f2c5e
--- /dev/null
+++ b/hw/qca5018/ht_sig_info.h
@@ -0,0 +1,388 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _HT_SIG_INFO_H_
+#define _HT_SIG_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 mcs[6:0], cbw[7], length[23:8], reserved_0[31:24]
+// 1 smoothing[0], not_sounding[1], ht_reserved[2], aggregation[3], stbc[5:4], fec_coding[6], short_gi[7], num_ext_sp_str[9:8], crc[17:10], signal_tail[23:18], reserved_1[31:24]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_HT_SIG_INFO 2
+
+struct ht_sig_info {
+ uint32_t mcs : 7, //[6:0]
+ cbw : 1, //[7]
+ length : 16, //[23:8]
+ reserved_0 : 8; //[31:24]
+ uint32_t smoothing : 1, //[0]
+ not_sounding : 1, //[1]
+ ht_reserved : 1, //[2]
+ aggregation : 1, //[3]
+ stbc : 2, //[5:4]
+ fec_coding : 1, //[6]
+ short_gi : 1, //[7]
+ num_ext_sp_str : 2, //[9:8]
+ crc : 8, //[17:10]
+ signal_tail : 6, //[23:18]
+ reserved_1 : 8; //[31:24]
+};
+
+/*
+
+mcs
+
+ Modulation Coding Scheme:
+
+ 0-7 are used for single stream
+
+ 8-15 are used for 2 streams
+
+ 16-23 are used for 3 streams
+
+ 24-31 are used for 4 streams
+
+ 32 is used for duplicate HT20 (unsupported)
+
+ 33-76 is used for unequal modulation (unsupported)
+
+ 77-127 is reserved.
+
+ <legal 0-31>
+
+cbw
+
+ Packet bandwidth:
+
+ <enum 0 ht_20_mhz>
+
+ <enum 1 ht_40_mhz>
+
+ <legal 0-1>
+
+length
+
+ This is the MPDU or A-MPDU length in octets of the PPDU
+
+ <legal all>
+
+reserved_0
+
+ This field is not part of HT-SIG
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+
+smoothing
+
+ Field indicates if smoothing is needed
+
+ E_num 0 do_smoothing Unsupported setting: indicates
+ smoothing is often used for beamforming
+
+
+ <legal 1>
+
+not_sounding
+
+ E_num 0 sounding Unsupported setting: indicates
+ sounding is used
+
+ <enum 1 no_sounding> Indicates no sounding is used
+
+ <legal 1>
+
+ht_reserved
+
+ Reserved: Should be set to 1 by the MAC and ignored by
+ the PHY
+
+ <legal 1>
+
+aggregation
+
+ <enum 0 mpdu> Indicates MPDU format
+
+ <enum 1 a_mpdu> Indicates A-MPDU format
+
+ <legal 0-1>
+
+stbc
+
+ <enum 0 no_stbc> Indicates no STBC
+
+ <enum 1 1_str_stbc> Indicates 1 stream STBC
+
+ E_num 2 2_str_stbc Indicates 2 stream STBC
+ (Unsupported)
+
+ <legal 0-1>
+
+fec_coding
+
+ <enum 0 ht_bcc> Indicates BCC coding
+
+ <enum 1 ht_ldpc> Indicates LDPC coding
+
+ <legal 0-1>
+
+short_gi
+
+ <enum 0 ht_normal_gi> Indicates normal guard
+ interval
+
+
+ <legal 0-1>
+
+num_ext_sp_str
+
+ Number of extension spatial streams: (Used for TxBF)
+
+ <enum 0 0_ext_sp_str> No extension spatial streams
+
+ E_num 1 1_ext_sp_str Not supported: 1 extension
+ spatial streams
+
+ E_num 2 2_ext_sp_str Not supported: 2 extension
+ spatial streams
+
+ <legal 0>
+
+crc
+
+ The CRC protects the HT-SIG (HT-SIG[0][23:0] and
+ HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 +
+ D + 1. <legal all>
+
+signal_tail
+
+ The 6 bits of tail is always set to 0 is used to flush
+ the BCC encoder and decoder. <legal 0>
+
+reserved_1
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY. <legal 0>
+*/
+
+
+/* Description HT_SIG_INFO_0_MCS
+
+ Modulation Coding Scheme:
+
+ 0-7 are used for single stream
+
+ 8-15 are used for 2 streams
+
+ 16-23 are used for 3 streams
+
+ 24-31 are used for 4 streams
+
+ 32 is used for duplicate HT20 (unsupported)
+
+ 33-76 is used for unequal modulation (unsupported)
+
+ 77-127 is reserved.
+
+ <legal 0-31>
+*/
+#define HT_SIG_INFO_0_MCS_OFFSET 0x00000000
+#define HT_SIG_INFO_0_MCS_LSB 0
+#define HT_SIG_INFO_0_MCS_MASK 0x0000007f
+
+/* Description HT_SIG_INFO_0_CBW
+
+ Packet bandwidth:
+
+ <enum 0 ht_20_mhz>
+
+ <enum 1 ht_40_mhz>
+
+ <legal 0-1>
+*/
+#define HT_SIG_INFO_0_CBW_OFFSET 0x00000000
+#define HT_SIG_INFO_0_CBW_LSB 7
+#define HT_SIG_INFO_0_CBW_MASK 0x00000080
+
+/* Description HT_SIG_INFO_0_LENGTH
+
+ This is the MPDU or A-MPDU length in octets of the PPDU
+
+ <legal all>
+*/
+#define HT_SIG_INFO_0_LENGTH_OFFSET 0x00000000
+#define HT_SIG_INFO_0_LENGTH_LSB 8
+#define HT_SIG_INFO_0_LENGTH_MASK 0x00ffff00
+
+/* Description HT_SIG_INFO_0_RESERVED_0
+
+ This field is not part of HT-SIG
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+*/
+#define HT_SIG_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define HT_SIG_INFO_0_RESERVED_0_LSB 24
+#define HT_SIG_INFO_0_RESERVED_0_MASK 0xff000000
+
+/* Description HT_SIG_INFO_1_SMOOTHING
+
+ Field indicates if smoothing is needed
+
+ E_num 0 do_smoothing Unsupported setting: indicates
+ smoothing is often used for beamforming
+
+
+ <legal 1>
+*/
+#define HT_SIG_INFO_1_SMOOTHING_OFFSET 0x00000004
+#define HT_SIG_INFO_1_SMOOTHING_LSB 0
+#define HT_SIG_INFO_1_SMOOTHING_MASK 0x00000001
+
+/* Description HT_SIG_INFO_1_NOT_SOUNDING
+
+ E_num 0 sounding Unsupported setting: indicates
+ sounding is used
+
+ <enum 1 no_sounding> Indicates no sounding is used
+
+ <legal 1>
+*/
+#define HT_SIG_INFO_1_NOT_SOUNDING_OFFSET 0x00000004
+#define HT_SIG_INFO_1_NOT_SOUNDING_LSB 1
+#define HT_SIG_INFO_1_NOT_SOUNDING_MASK 0x00000002
+
+/* Description HT_SIG_INFO_1_HT_RESERVED
+
+ Reserved: Should be set to 1 by the MAC and ignored by
+ the PHY
+
+ <legal 1>
+*/
+#define HT_SIG_INFO_1_HT_RESERVED_OFFSET 0x00000004
+#define HT_SIG_INFO_1_HT_RESERVED_LSB 2
+#define HT_SIG_INFO_1_HT_RESERVED_MASK 0x00000004
+
+/* Description HT_SIG_INFO_1_AGGREGATION
+
+ <enum 0 mpdu> Indicates MPDU format
+
+ <enum 1 a_mpdu> Indicates A-MPDU format
+
+ <legal 0-1>
+*/
+#define HT_SIG_INFO_1_AGGREGATION_OFFSET 0x00000004
+#define HT_SIG_INFO_1_AGGREGATION_LSB 3
+#define HT_SIG_INFO_1_AGGREGATION_MASK 0x00000008
+
+/* Description HT_SIG_INFO_1_STBC
+
+ <enum 0 no_stbc> Indicates no STBC
+
+ <enum 1 1_str_stbc> Indicates 1 stream STBC
+
+ E_num 2 2_str_stbc Indicates 2 stream STBC
+ (Unsupported)
+
+ <legal 0-1>
+*/
+#define HT_SIG_INFO_1_STBC_OFFSET 0x00000004
+#define HT_SIG_INFO_1_STBC_LSB 4
+#define HT_SIG_INFO_1_STBC_MASK 0x00000030
+
+/* Description HT_SIG_INFO_1_FEC_CODING
+
+ <enum 0 ht_bcc> Indicates BCC coding
+
+ <enum 1 ht_ldpc> Indicates LDPC coding
+
+ <legal 0-1>
+*/
+#define HT_SIG_INFO_1_FEC_CODING_OFFSET 0x00000004
+#define HT_SIG_INFO_1_FEC_CODING_LSB 6
+#define HT_SIG_INFO_1_FEC_CODING_MASK 0x00000040
+
+/* Description HT_SIG_INFO_1_SHORT_GI
+
+ <enum 0 ht_normal_gi> Indicates normal guard
+ interval
+
+
+ <legal 0-1>
+*/
+#define HT_SIG_INFO_1_SHORT_GI_OFFSET 0x00000004
+#define HT_SIG_INFO_1_SHORT_GI_LSB 7
+#define HT_SIG_INFO_1_SHORT_GI_MASK 0x00000080
+
+/* Description HT_SIG_INFO_1_NUM_EXT_SP_STR
+
+ Number of extension spatial streams: (Used for TxBF)
+
+ <enum 0 0_ext_sp_str> No extension spatial streams
+
+ E_num 1 1_ext_sp_str Not supported: 1 extension
+ spatial streams
+
+ E_num 2 2_ext_sp_str Not supported: 2 extension
+ spatial streams
+
+ <legal 0>
+*/
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_OFFSET 0x00000004
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_LSB 8
+#define HT_SIG_INFO_1_NUM_EXT_SP_STR_MASK 0x00000300
+
+/* Description HT_SIG_INFO_1_CRC
+
+ The CRC protects the HT-SIG (HT-SIG[0][23:0] and
+ HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 +
+ D + 1. <legal all>
+*/
+#define HT_SIG_INFO_1_CRC_OFFSET 0x00000004
+#define HT_SIG_INFO_1_CRC_LSB 10
+#define HT_SIG_INFO_1_CRC_MASK 0x0003fc00
+
+/* Description HT_SIG_INFO_1_SIGNAL_TAIL
+
+ The 6 bits of tail is always set to 0 is used to flush
+ the BCC encoder and decoder. <legal 0>
+*/
+#define HT_SIG_INFO_1_SIGNAL_TAIL_OFFSET 0x00000004
+#define HT_SIG_INFO_1_SIGNAL_TAIL_LSB 18
+#define HT_SIG_INFO_1_SIGNAL_TAIL_MASK 0x00fc0000
+
+/* Description HT_SIG_INFO_1_RESERVED_1
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY. <legal 0>
+*/
+#define HT_SIG_INFO_1_RESERVED_1_OFFSET 0x00000004
+#define HT_SIG_INFO_1_RESERVED_1_LSB 24
+#define HT_SIG_INFO_1_RESERVED_1_MASK 0xff000000
+
+
+#endif // _HT_SIG_INFO_H_
diff --git a/hw/qca5018/l_sig_a_info.h b/hw/qca5018/l_sig_a_info.h
new file mode 100644
index 0000000..20c2315
--- /dev/null
+++ b/hw/qca5018/l_sig_a_info.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _L_SIG_A_INFO_H_
+#define _L_SIG_A_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 rate[3:0], lsig_reserved[4], length[16:5], parity[17], tail[23:18], pkt_type[27:24], captured_implicit_sounding[28], reserved[31:29]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_L_SIG_A_INFO 1
+
+struct l_sig_a_info {
+ uint32_t rate : 4, //[3:0]
+ lsig_reserved : 1, //[4]
+ length : 12, //[16:5]
+ parity : 1, //[17]
+ tail : 6, //[23:18]
+ pkt_type : 4, //[27:24]
+ captured_implicit_sounding : 1, //[28]
+ reserved : 3; //[31:29]
+};
+
+/*
+
+rate
+
+ This format is originally defined for OFDM as a 4 bit
+ field but the 5th bit was added to indicate 11b formatted
+ frames. In the standard bit [4] is specified as reserved.
+ For 11b frames this L-SIG is transformed in the PHY into the
+ 11b preamble format. The following are the rates:
+
+ <enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
+
+ <enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
+
+ <enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
+
+ <enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
+
+ <enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
+
+ <enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
+
+ <enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
+
+ <enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
+
+ <legal 8-15>
+
+lsig_reserved
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY
+
+ <legal 0>
+
+length
+
+ The length indicates the number of octets in this MPDU.
+ Note that when using mixed mode 11n preamble this length
+ provides the spoofed length for the PPDU. This length
+ provides part of the information to derive the actually PPDU
+ length. For legacy OFDM and 11B frames the maximum length
+ is
+
+ <legal all>
+
+parity
+
+ 11a/n/ac TX: This field provides even parity over the
+ first 18 bits of the signal field which means that the sum
+ of 1s in the signal field will always be even on
+
+ 11a/n/ac RX: this field contains the received parity
+ field from the L-SIG symbol for the current packet.
+
+ <legal 0-1>
+
+tail
+
+ The 6 bits of tail is always set to 0 is used to flush
+ the BCC encoder and decoder. <legal 0>
+
+pkt_type
+
+ Only used on the RX side.
+
+ Note: This is not really part of L-SIG
+
+
+
+ Packet type:
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+
+captured_implicit_sounding
+
+ Only used on the RX side.
+
+ Note: This is not really part of L-SIG
+
+
+
+ This indicates that the PHY has captured implicit
+ sounding.
+
+reserved
+
+ Reserved: Should be set to 0 by the transmitting MAC and
+ ignored by the PHY <legal 0>
+*/
+
+
+/* Description L_SIG_A_INFO_0_RATE
+
+ This format is originally defined for OFDM as a 4 bit
+ field but the 5th bit was added to indicate 11b formatted
+ frames. In the standard bit [4] is specified as reserved.
+ For 11b frames this L-SIG is transformed in the PHY into the
+ 11b preamble format. The following are the rates:
+
+ <enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
+
+ <enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
+
+ <enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
+
+ <enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
+
+ <enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
+
+ <enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
+
+ <enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
+
+ <enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
+
+ <legal 8-15>
+*/
+#define L_SIG_A_INFO_0_RATE_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_RATE_LSB 0
+#define L_SIG_A_INFO_0_RATE_MASK 0x0000000f
+
+/* Description L_SIG_A_INFO_0_LSIG_RESERVED
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY
+
+ <legal 0>
+*/
+#define L_SIG_A_INFO_0_LSIG_RESERVED_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_LSIG_RESERVED_LSB 4
+#define L_SIG_A_INFO_0_LSIG_RESERVED_MASK 0x00000010
+
+/* Description L_SIG_A_INFO_0_LENGTH
+
+ The length indicates the number of octets in this MPDU.
+ Note that when using mixed mode 11n preamble this length
+ provides the spoofed length for the PPDU. This length
+ provides part of the information to derive the actually PPDU
+ length. For legacy OFDM and 11B frames the maximum length
+ is
+
+ <legal all>
+*/
+#define L_SIG_A_INFO_0_LENGTH_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_LENGTH_LSB 5
+#define L_SIG_A_INFO_0_LENGTH_MASK 0x0001ffe0
+
+/* Description L_SIG_A_INFO_0_PARITY
+
+ 11a/n/ac TX: This field provides even parity over the
+ first 18 bits of the signal field which means that the sum
+ of 1s in the signal field will always be even on
+
+ 11a/n/ac RX: this field contains the received parity
+ field from the L-SIG symbol for the current packet.
+
+ <legal 0-1>
+*/
+#define L_SIG_A_INFO_0_PARITY_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_PARITY_LSB 17
+#define L_SIG_A_INFO_0_PARITY_MASK 0x00020000
+
+/* Description L_SIG_A_INFO_0_TAIL
+
+ The 6 bits of tail is always set to 0 is used to flush
+ the BCC encoder and decoder. <legal 0>
+*/
+#define L_SIG_A_INFO_0_TAIL_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_TAIL_LSB 18
+#define L_SIG_A_INFO_0_TAIL_MASK 0x00fc0000
+
+/* Description L_SIG_A_INFO_0_PKT_TYPE
+
+ Only used on the RX side.
+
+ Note: This is not really part of L-SIG
+
+
+
+ Packet type:
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+*/
+#define L_SIG_A_INFO_0_PKT_TYPE_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_PKT_TYPE_LSB 24
+#define L_SIG_A_INFO_0_PKT_TYPE_MASK 0x0f000000
+
+/* Description L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING
+
+ Only used on the RX side.
+
+ Note: This is not really part of L-SIG
+
+
+
+ This indicates that the PHY has captured implicit
+ sounding.
+*/
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_LSB 28
+#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
+
+/* Description L_SIG_A_INFO_0_RESERVED
+
+ Reserved: Should be set to 0 by the transmitting MAC and
+ ignored by the PHY <legal 0>
+*/
+#define L_SIG_A_INFO_0_RESERVED_OFFSET 0x00000000
+#define L_SIG_A_INFO_0_RESERVED_LSB 29
+#define L_SIG_A_INFO_0_RESERVED_MASK 0xe0000000
+
+
+#endif // _L_SIG_A_INFO_H_
diff --git a/hw/qca5018/l_sig_b_info.h b/hw/qca5018/l_sig_b_info.h
new file mode 100644
index 0000000..21366ea
--- /dev/null
+++ b/hw/qca5018/l_sig_b_info.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _L_SIG_B_INFO_H_
+#define _L_SIG_B_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 rate[3:0], length[15:4], reserved[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_L_SIG_B_INFO 1
+
+struct l_sig_b_info {
+ uint32_t rate : 4, //[3:0]
+ length : 12, //[15:4]
+ reserved : 16; //[31:16]
+};
+
+/*
+
+rate
+
+ <enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
+
+ <enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
+
+ <enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
+
+ <enum 4 cck_11_mbps_long> CCK 11 Mbps long
+
+ <enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
+
+ <enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
+
+ <enum 7 cck_11_mbps_short> CCK 11 Mbps short
+
+ <legal 1-7>
+
+length
+
+ The length indicates the number of octets in this MPDU.
+
+ <legal all>
+
+reserved
+
+ Reserved: Should be set to 0 by the transmitting MAC and
+ ignored by the PHY <legal 0>
+*/
+
+
+/* Description L_SIG_B_INFO_0_RATE
+
+ <enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
+
+ <enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
+
+ <enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
+
+ <enum 4 cck_11_mbps_long> CCK 11 Mbps long
+
+ <enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
+
+ <enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
+
+ <enum 7 cck_11_mbps_short> CCK 11 Mbps short
+
+ <legal 1-7>
+*/
+#define L_SIG_B_INFO_0_RATE_OFFSET 0x00000000
+#define L_SIG_B_INFO_0_RATE_LSB 0
+#define L_SIG_B_INFO_0_RATE_MASK 0x0000000f
+
+/* Description L_SIG_B_INFO_0_LENGTH
+
+ The length indicates the number of octets in this MPDU.
+
+ <legal all>
+*/
+#define L_SIG_B_INFO_0_LENGTH_OFFSET 0x00000000
+#define L_SIG_B_INFO_0_LENGTH_LSB 4
+#define L_SIG_B_INFO_0_LENGTH_MASK 0x0000fff0
+
+/* Description L_SIG_B_INFO_0_RESERVED
+
+ Reserved: Should be set to 0 by the transmitting MAC and
+ ignored by the PHY <legal 0>
+*/
+#define L_SIG_B_INFO_0_RESERVED_OFFSET 0x00000000
+#define L_SIG_B_INFO_0_RESERVED_LSB 16
+#define L_SIG_B_INFO_0_RESERVED_MASK 0xffff0000
+
+
+#endif // _L_SIG_B_INFO_H_
diff --git a/hw/qca5018/mac_tcl_reg_seq_hwiobase.h b/hw/qca5018/mac_tcl_reg_seq_hwiobase.h
new file mode 100644
index 0000000..2ee6571
--- /dev/null
+++ b/hw/qca5018/mac_tcl_reg_seq_hwiobase.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
+// User Name:c_landav
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __MAC_TCL_REG_SEQ_BASE_H__
+#define __MAC_TCL_REG_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+#endif
+
diff --git a/hw/qca5018/mac_tcl_reg_seq_hwioreg.h b/hw/qca5018/mac_tcl_reg_seq_hwioreg.h
new file mode 100644
index 0000000..d8fb4ba
--- /dev/null
+++ b/hw/qca5018/mac_tcl_reg_seq_hwioreg.h
@@ -0,0 +1,6597 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 2/21/2020
+// User Name:c_landav
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __MAC_TCL_REG_SEQ_REG_H__
+#define __MAC_TCL_REG_SEQ_REG_H__
+
+#include "seq_hwio.h"
+#include "mac_tcl_reg_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block MAC_TCL_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register TCL_R0_SW2TCL1_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5
+
+//// Register TCL_R0_SW2TCL2_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5
+
+//// Register TCL_R0_SW2TCL3_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5
+
+//// Register TCL_R0_FW2TCL1_RING_CTRL ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x) (x+0x00000010)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_PHYS(x) (x+0x00000010)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK 0x0003ffe0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_SHFT 5
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_SHFT 0x6
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_BMSK 0x00000020
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_SHFT 0x5
+
+//// Register TCL_R0_CONS_RING_CMN_CTRL_REG ////
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x001fffff
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_BMSK 0x00100000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_SHFT 0x14
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x00080000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 0x13
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_BMSK 0x00040000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_SHFT 0x12
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x00020000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 0x11
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x0001c000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 0xe
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x00002000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 0xd
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_BMSK 0x00001000
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_SHFT 0xc
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_BMSK 0x00000080
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_SHFT 0x7
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_BMSK 0x0000c000
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_SHFT 0xe
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x00002000
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 0xd
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x00001000
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 0xc
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0
+
+//// Register TCL_R0_GEN_CTRL ////
+
+#define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028)
+#define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028)
+#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xfffff1fb
+#define HWIO_TCL_R0_GEN_CTRL_SHFT 0
+#define HWIO_TCL_R0_GEN_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK)
+#define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000
+#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10
+
+#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x00008000
+#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 0xf
+
+#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000
+#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe
+
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd
+
+#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000
+#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc
+
+#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100
+#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8
+
+#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080
+#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7
+
+#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040
+#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6
+
+#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020
+#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5
+
+#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010
+#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4
+
+#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008
+#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3
+
+#define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x00000002
+#define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 0x1
+
+#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001
+#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0
+
+//// Register TCL_R0_DSCP_TID_MAP_n ////
+
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n) (base+0x2C+0x4*n)
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base, n) (base+0x2C+0x4*n)
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_SHFT 0
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 287
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n) \
+ in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base, n, mask) \
+ in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask)
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base, n, val) \
+ out_dword( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), val)
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base, n, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask, val, HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0x0
+
+//// Register TCL_R0_PCP_TID_MAP ////
+
+#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x000004ac)
+#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x000004ac)
+#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff
+#define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0
+#define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK)
+#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask)
+#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val)
+#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_31_0 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x000004b0)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x000004b0)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_63_32 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x000004b4)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x000004b4)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_64 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x000004b8)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x000004b8)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0
+
+//// Register TCL_R0_CONFIG_SEARCH_QUEUE ////
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x000004bc)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x000004bc)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00fffdfc
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_BMSK 0x00800000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_SHFT 0x17
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x00700000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 0x14
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0x000e0000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 0x11
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x0001c000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 0xe
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2
+
+//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW ////
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c0)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c0)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0
+
+//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH ////
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004c4)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004c4)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0
+
+//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW ////
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c8)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c8)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0
+
+//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH ////
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004cc)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004cc)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0
+
+//// Register TCL_R0_CONFIG_SEARCH_METADATA ////
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000004d0)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000004d0)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0
+
+//// Register TCL_R0_TID_MAP_PRTY ////
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000004d4)
+#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000004d4)
+#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef
+#define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0
+#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK)
+#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask)
+#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val)
+#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0
+#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f
+#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0
+
+//// Register TCL_R0_INVALID_APB_ACC_ADDR ////
+
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000004d8)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000004d8)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0
+
+//// Register TCL_R0_WATCHDOG ////
+
+#define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000004dc)
+#define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000004dc)
+#define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff
+#define HWIO_TCL_R0_WATCHDOG_SHFT 0
+#define HWIO_TCL_R0_WATCHDOG_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK)
+#define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask)
+#define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val)
+#define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10
+
+#define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff
+#define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0
+
+//// Register TCL_R0_LCE_RULE_n ////
+
+#define HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n) (base+0x4E0+0x4*n)
+#define HWIO_TCL_R0_LCE_RULE_n_PHYS(base, n) (base+0x4E0+0x4*n)
+#define HWIO_TCL_R0_LCE_RULE_n_RMSK 0x007fffff
+#define HWIO_TCL_R0_LCE_RULE_n_SHFT 0
+#define HWIO_TCL_R0_LCE_RULE_n_MAXn 25
+#define HWIO_TCL_R0_LCE_RULE_n_INI(base, n) \
+ in_dword_masked ( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), HWIO_TCL_R0_LCE_RULE_n_RMSK)
+#define HWIO_TCL_R0_LCE_RULE_n_INMI(base, n, mask) \
+ in_dword_masked ( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), mask)
+#define HWIO_TCL_R0_LCE_RULE_n_OUTI(base, n, val) \
+ out_dword( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), val)
+#define HWIO_TCL_R0_LCE_RULE_n_OUTMI(base, n, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_RULE_n_INI(base, n)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_BMSK 0x00400000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_SHFT 0x16
+
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_BMSK 0x00200000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_SHFT 0x15
+
+#define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_BMSK 0x00180000
+#define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_SHFT 0x13
+
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_BMSK 0x00040000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_SHFT 0x12
+
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_BMSK 0x00020000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_SHFT 0x11
+
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_BMSK 0x00010000
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_SHFT 0x10
+
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_BMSK 0x0000ffff
+#define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_SHFT 0x0
+
+//// Register TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n ////
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n) (base+0x548+0x4*n)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_PHYS(base, n) (base+0x548+0x4*n)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK 0xffffffff
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_SHFT 0
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_MAXn 25
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base, n) \
+ in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INMI(base, n, mask) \
+ in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), mask)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTI(base, n, val) \
+ out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), val)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTMI(base, n, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base, n)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_SHFT 0x0
+
+//// Register TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n ////
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n) (base+0x5B0+0x4*n)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_PHYS(base, n) (base+0x5B0+0x4*n)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK 0x000000ff
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_SHFT 0
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_MAXn 25
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base, n) \
+ in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INMI(base, n, mask) \
+ in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), mask)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTI(base, n, val) \
+ out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), val)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTMI(base, n, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base, n)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_BMSK 0x000000ff
+#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_SHFT 0x0
+
+//// Register TCL_R0_LCE_CLFY_INFO_HANDLER_n ////
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n) (base+0x618+0x4*n)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_PHYS(base, n) (base+0x618+0x4*n)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK 0x003fffff
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_SHFT 0
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MAXn 25
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base, n) \
+ in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INMI(base, n, mask) \
+ in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), mask)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTI(base, n, val) \
+ out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), val)
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTMI(base, n, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base, n)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_BMSK 0x00200000
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_SHFT 0x15
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_BMSK 0x001fffe0
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_SHFT 0x5
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_BMSK 0x00000010
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_SHFT 0x4
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_BMSK 0x00000008
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_SHFT 0x3
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_BMSK 0x00000004
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_SHFT 0x2
+
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_BMSK 0x00000003
+#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_SHFT 0x0
+
+//// Register TCL_R0_CLKGATE_DISABLE ////
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x00000680)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x00000680)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0
+#define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_SHFT 0x1f
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_BMSK 0x20000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_SHFT 0x1d
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_BMSK 0x10000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_SHFT 0x1c
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_BMSK 0x08000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_SHFT 0x1b
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_BMSK 0x04000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_SHFT 0x1a
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_BMSK 0x02000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_SHFT 0x19
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_BMSK 0x01000000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_SHFT 0x18
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_BMSK 0x00800000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_SHFT 0x17
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_BMSK 0x00400000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_SHFT 0x16
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_BMSK 0x00200000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_SHFT 0x15
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_BMSK 0x00100000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_SHFT 0x14
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_BMSK 0x00080000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_SHFT 0x13
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_BMSK 0x00040000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_SHFT 0x12
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_BMSK 0x00020000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_SHFT 0x11
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_BMSK 0x00010000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_SHFT 0x10
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_BMSK 0x00008000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_SHFT 0xf
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_BMSK 0x00004000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_SHFT 0xe
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_BMSK 0x00002000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_SHFT 0xd
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_BMSK 0x00001000
+#define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_SHFT 0xc
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_BMSK 0x00000800
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_SHFT 0xb
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_BMSK 0x00000400
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_SHFT 0xa
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_BMSK 0x00000200
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_SHFT 0x9
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_BMSK 0x00000100
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_SHFT 0x8
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_BMSK 0x00000080
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_SHFT 0x7
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_BMSK 0x00000040
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_SHFT 0x6
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_BMSK 0x00000020
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_SHFT 0x5
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_BMSK 0x00000010
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_SHFT 0x4
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_BMSK 0x00000008
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_SHFT 0x3
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_BMSK 0x00000004
+#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_SHFT 0x2
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_LCE_CCE_BMSK 0x00000002
+#define HWIO_TCL_R0_CLKGATE_DISABLE_LCE_CCE_SHFT 0x1
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_BMSK 0x00000001
+#define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_SHFT 0x0
+
+//// Register TCL_R0_CREDIT_COUNT ////
+
+#define HWIO_TCL_R0_CREDIT_COUNT_ADDR(x) (x+0x00000684)
+#define HWIO_TCL_R0_CREDIT_COUNT_PHYS(x) (x+0x00000684)
+#define HWIO_TCL_R0_CREDIT_COUNT_RMSK 0x0001ffff
+#define HWIO_TCL_R0_CREDIT_COUNT_SHFT 0
+#define HWIO_TCL_R0_CREDIT_COUNT_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), HWIO_TCL_R0_CREDIT_COUNT_RMSK)
+#define HWIO_TCL_R0_CREDIT_COUNT_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), mask)
+#define HWIO_TCL_R0_CREDIT_COUNT_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), val)
+#define HWIO_TCL_R0_CREDIT_COUNT_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), mask, val, HWIO_TCL_R0_CREDIT_COUNT_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_BMSK 0x00010000
+#define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_SHFT 0x10
+
+#define HWIO_TCL_R0_CREDIT_COUNT_VAL_BMSK 0x0000ffff
+#define HWIO_TCL_R0_CREDIT_COUNT_VAL_SHFT 0x0
+
+//// Register TCL_R0_CURRENT_CREDIT_COUNT ////
+
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x) (x+0x00000688)
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_PHYS(x) (x+0x00000688)
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK 0x0000ffff
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_SHFT 0
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK)
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), mask)
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), val)
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), mask, val, HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_BMSK 0x0000ffff
+#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_SHFT 0x0
+
+//// Register TCL_R0_S_PARE_REGISTER ////
+
+#define HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x) (x+0x0000068c)
+#define HWIO_TCL_R0_S_PARE_REGISTER_PHYS(x) (x+0x0000068c)
+#define HWIO_TCL_R0_S_PARE_REGISTER_RMSK 0xffffffff
+#define HWIO_TCL_R0_S_PARE_REGISTER_SHFT 0
+#define HWIO_TCL_R0_S_PARE_REGISTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), HWIO_TCL_R0_S_PARE_REGISTER_RMSK)
+#define HWIO_TCL_R0_S_PARE_REGISTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask)
+#define HWIO_TCL_R0_S_PARE_REGISTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), val)
+#define HWIO_TCL_R0_S_PARE_REGISTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask, val, HWIO_TCL_R0_S_PARE_REGISTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_S_PARE_REGISTER_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_S_PARE_REGISTER_VAL_SHFT 0x0
+
+//// Register TCL_R0_MISC_CTRL ////
+
+#define HWIO_TCL_R0_MISC_CTRL_ADDR(x) (x+0x00000690)
+#define HWIO_TCL_R0_MISC_CTRL_PHYS(x) (x+0x00000690)
+#define HWIO_TCL_R0_MISC_CTRL_RMSK 0x00000003
+#define HWIO_TCL_R0_MISC_CTRL_SHFT 0
+#define HWIO_TCL_R0_MISC_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_MISC_CTRL_ADDR(x), HWIO_TCL_R0_MISC_CTRL_RMSK)
+#define HWIO_TCL_R0_MISC_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_MISC_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_MISC_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_MISC_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_MISC_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_MISC_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_MISC_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_BMSK 0x00000002
+#define HWIO_TCL_R0_MISC_CTRL_DATA_CORRUPT_FIX_DISABLE_CHK_BIT_SHFT 0x1
+
+#define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_BMSK 0x00000001
+#define HWIO_TCL_R0_MISC_CTRL_MSI_DISABLE_CHK_BIT_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000694)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000694)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000698)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000698)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x0000069c)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x0000069c)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x000006a0)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x000006a0)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000006a4)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000006a4)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000006b0)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000006b0)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000006b4)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000006b4)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000006c4)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000006c4)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000006c8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000006c8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000006cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000006cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000006d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000006d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000006d4)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000006d4)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000006d8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000006d8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006dc)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006dc)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006e0)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006e0)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006e4)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006e4)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006e8)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006e8)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x000006ec)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x000006ec)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x000006f0)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x000006f0)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x000006f4)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x000006f4)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x000006f8)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x000006f8)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x000006fc)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x000006fc)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000708)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000708)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000070c)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000070c)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000071c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000071c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000720)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000720)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000724)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000724)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000728)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000728)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000072c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000072c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000730)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000730)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000734)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000734)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000738)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000738)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x0000073c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x0000073c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000740)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000740)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000744)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000744)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000748)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000748)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x0000074c)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x0000074c)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x00000750)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x00000750)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000754)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000754)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000760)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000760)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000764)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000764)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000774)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000774)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000778)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000778)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000077c)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000077c)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000780)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000780)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000784)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000784)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000788)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000788)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000078c)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000078c)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000790)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000790)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x00000794)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x00000794)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000798)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000798)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) (x+0x0000079c)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) (x+0x0000079c)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) (x+0x000007a0)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) (x+0x000007a0)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) (x+0x000007a4)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) (x+0x000007a4)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) (x+0x000007a8)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) (x+0x000007a8)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) (x+0x000007ac)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) (x+0x000007ac)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK 0x003fffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) (x+0x000007b8)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) (x+0x000007b8)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) (x+0x000007bc)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) (x+0x000007bc)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000007cc)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000007cc)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000007d0)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000007d0)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000007d4)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000007d4)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000007d8)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000007d8)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000007dc)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000007dc)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000007e0)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000007e0)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007e4)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007e4)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007e8)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007e8)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) (x+0x000007ec)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) (x+0x000007ec)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007f0)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007f0)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000007f4)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000007f4)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000007f8)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000007f8)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_ID ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x000007fc)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x000007fc)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x00000800)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x00000800)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MISC ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000804)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000804)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000810)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000810)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000814)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000814)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000824)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000824)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000828)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000828)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000082c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000082c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000830)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000830)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000834)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000834)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000838)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000838)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000083c)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000083c)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000840)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000840)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000844)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000844)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000848)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000848)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x0000084c)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x0000084c)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x00000850)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x00000850)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_ID ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000854)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000854)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000858)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000858)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x0000085c)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x0000085c)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000860)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000860)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000864)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000864)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000870)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000870)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000874)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000874)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000878)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000878)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000894)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000894)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000898)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000898)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) (x+0x0000089c)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) (x+0x0000089c)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008a0)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008a0)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000008a4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000008a4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000008a8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000008a8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_ID ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000008ac)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000008ac)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000008b0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000008b0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000008b4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000008b4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008b8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008b8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008bc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008bc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008c8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008c8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008cc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008cc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008d0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008d0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008ec)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008ec)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008f0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008f0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x000008f4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x000008f4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008f8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008f8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x000008fc)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x000008fc)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x00000900)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x00000900)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_ID ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000904)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000904)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000908)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000908)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x0000090c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x0000090c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000910)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000910)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000914)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000914)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000920)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000920)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000924)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000924)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000928)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000928)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000944)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000944)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000948)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000948)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x0000094c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x0000094c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000950)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000950)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000954)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000954)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000958)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000958)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_ID ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x0000095c)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x0000095c)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x00000960)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x00000960)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000964)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000964)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000968)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000968)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000096c)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000096c)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000978)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000978)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000097c)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000097c)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000980)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000980)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000099c)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000099c)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000009a0)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000009a0)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x) (x+0x000009a4)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_PHYS(x) (x+0x000009a4)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009a8)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009a8)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register TCL_R0_GXI_TESTBUS_LOWER ////
+
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000009ac)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000009ac)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_GXI_TESTBUS_UPPER ////
+
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000009b0)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000009b0)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0
+
+//// Register TCL_R0_GXI_SM_STATES_IX_0 ////
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000009b4)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000009b4)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0
+
+//// Register TCL_R0_GXI_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000009b8)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000009b8)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+//// Register TCL_R0_GXI_CLOCK_GATE_DISABLE ////
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000009bc)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000009bc)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_ERR_INTS ////
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000009c0)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000009c0)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_ERR_STATS ////
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000009c4)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000009c4)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000009c8)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000009c8)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_REDUCED_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000009cc)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000009cc)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_MISC_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000009d0)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000009d0)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_WDOG_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000009d4)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000009d4)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_WDOG_STATUS ////
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000009d8)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000009d8)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_IDLE_COUNTERS ////
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000009dc)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000009dc)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_RD_LATENCY_CTRL ////
+
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x000009e0)
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x000009e0)
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11
+
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10
+
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_WR_LATENCY_CTRL ////
+
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x000009e4)
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x000009e4)
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11
+
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10
+
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 ////
+
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009e8)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009e8)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 ////
+
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009ec)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009ec)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 ////
+
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009f0)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009f0)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 ////
+
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009f4)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009f4)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0
+
+//// Register TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL ////
+
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000009f8)
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000009f8)
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask)
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf
+
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8
+
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7
+
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f
+#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0
+
+//// Register TCL_R0_ASE_GST_BASE_ADDR_LOW ////
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x000009fc)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x000009fc)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0
+
+//// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH ////
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x00000a00)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x00000a00)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0
+
+//// Register TCL_R0_ASE_GST_SIZE ////
+
+#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000a04)
+#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000a04)
+#define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff
+#define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0
+#define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK)
+#define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff
+#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0
+
+//// Register TCL_R0_ASE_SEARCH_CTRL ////
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x00000a08)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x00000a08)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff3fff
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_BMSK 0x00002000
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_SHFT 0xd
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_BMSK 0x00001000
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_SHFT 0xc
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_BMSK 0x00000800
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_SHFT 0xb
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0
+
+//// Register TCL_R0_ASE_WATCHDOG ////
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000a0c)
+#define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000a0c)
+#define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0
+#define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK)
+#define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff
+#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0
+
+//// Register TCL_R0_ASE_CLKGATE_DISABLE ////
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000a10)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000a10)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffffe00
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0x9
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000100
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 0x8
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x00000080
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 0x7
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000040
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x6
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000020
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x5
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0
+
+//// Register TCL_R0_ASE_WRITE_BACK_PENDING ////
+
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000a14)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000a14)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \
+ out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0
+
+//// Register TCL_R1_CACHE_FLUSH ////
+
+#define HWIO_TCL_R1_CACHE_FLUSH_ADDR(x) (x+0x00001000)
+#define HWIO_TCL_R1_CACHE_FLUSH_PHYS(x) (x+0x00001000)
+#define HWIO_TCL_R1_CACHE_FLUSH_RMSK 0x00000003
+#define HWIO_TCL_R1_CACHE_FLUSH_SHFT 0
+#define HWIO_TCL_R1_CACHE_FLUSH_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), HWIO_TCL_R1_CACHE_FLUSH_RMSK)
+#define HWIO_TCL_R1_CACHE_FLUSH_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), mask)
+#define HWIO_TCL_R1_CACHE_FLUSH_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), val)
+#define HWIO_TCL_R1_CACHE_FLUSH_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), mask, val, HWIO_TCL_R1_CACHE_FLUSH_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_CACHE_FLUSH_STATUS_BMSK 0x00000002
+#define HWIO_TCL_R1_CACHE_FLUSH_STATUS_SHFT 0x1
+
+#define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_BMSK 0x00000001
+#define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_SHFT 0x0
+
+//// Register TCL_R1_SM_STATES_IX_0 ////
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001004)
+#define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001004)
+#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x3fffffff
+#define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0
+#define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK)
+#define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask)
+#define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_RES_WR_BMSK 0x30000000
+#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_RES_WR_SHFT 0x1c
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x0e000000
+#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x19
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x01e00000
+#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000
+#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000
+#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_BMSK 0x00007000
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_SHFT 0xc
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00
+#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0
+
+//// Register TCL_R1_SM_STATES_IX_1 ////
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001008)
+#define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001008)
+#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x001fffff
+#define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0
+#define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK)
+#define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask)
+#define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val)
+#define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_BMSK 0x001c0000
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_IDLE_SEQUENCE_SHFT 0x12
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x00038000
+#define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 0xf
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000
+#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0
+
+//// Register TCL_R1_STATUS ////
+
+#define HWIO_TCL_R1_STATUS_ADDR(x) (x+0x0000100c)
+#define HWIO_TCL_R1_STATUS_PHYS(x) (x+0x0000100c)
+#define HWIO_TCL_R1_STATUS_RMSK 0x07ffffff
+#define HWIO_TCL_R1_STATUS_SHFT 0
+#define HWIO_TCL_R1_STATUS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_STATUS_ADDR(x), HWIO_TCL_R1_STATUS_RMSK)
+#define HWIO_TCL_R1_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_STATUS_ADDR(x), mask)
+#define HWIO_TCL_R1_STATUS_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_STATUS_ADDR(x), val)
+#define HWIO_TCL_R1_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_STATUS_ADDR(x), mask, val, HWIO_TCL_R1_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_BMSK 0x04000000
+#define HWIO_TCL_R1_STATUS_HDR_BUF_EMPTY_SHFT 0x1a
+
+#define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_BMSK 0x02000000
+#define HWIO_TCL_R1_STATUS_DESC_BUF_EMPTY_SHFT 0x19
+
+#define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_BMSK 0x01000000
+#define HWIO_TCL_R1_STATUS_GSE_CCE_RES_IDLE_SHFT 0x18
+
+#define HWIO_TCL_R1_STATUS_PROD_RING_BUNC_FIFO_CTRL_IDLE_BMSK 0x00800000
+#define HWIO_TCL_R1_STATUS_PROD_RING_BUNC_FIFO_CTRL_IDLE_SHFT 0x17
+
+#define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_BMSK 0x00400000
+#define HWIO_TCL_R1_STATUS_PROD_RING_CTRL_IDLE_SHFT 0x16
+
+#define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_BMSK 0x00200000
+#define HWIO_TCL_R1_STATUS_TLV_DECODER_IDLE_SHFT 0x15
+
+#define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_BMSK 0x00100000
+#define HWIO_TCL_R1_STATUS_TLV_GEN_IDLE_SHFT 0x14
+
+#define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_BMSK 0x00080000
+#define HWIO_TCL_R1_STATUS_GSE_CTRL_IDLE_SHFT 0x13
+
+#define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_BMSK 0x00040000
+#define HWIO_TCL_R1_STATUS_CLFY_WRAP_IDLE_SHFT 0x12
+
+#define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_BMSK 0x00020000
+#define HWIO_TCL_R1_STATUS_CCE_OR_LCE_IDLE_SHFT 0x11
+
+#define HWIO_TCL_R1_STATUS_ASE_IDLE_BMSK 0x00010000
+#define HWIO_TCL_R1_STATUS_ASE_IDLE_SHFT 0x10
+
+#define HWIO_TCL_R1_STATUS_PARSER_IDLE_BMSK 0x00008000
+#define HWIO_TCL_R1_STATUS_PARSER_IDLE_SHFT 0xf
+
+#define HWIO_TCL_R1_STATUS_TCL_STATUS2_PROD_IDLE_BMSK 0x00004000
+#define HWIO_TCL_R1_STATUS_TCL_STATUS2_PROD_IDLE_SHFT 0xe
+
+#define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_BMSK 0x00002000
+#define HWIO_TCL_R1_STATUS_TCL_STATUS1_PROD_IDLE_SHFT 0xd
+
+#define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_BMSK 0x00001000
+#define HWIO_TCL_R1_STATUS_TCL2FW_PROD_IDLE_SHFT 0xc
+
+#define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_BMSK 0x00000800
+#define HWIO_TCL_R1_STATUS_TCL2TQM_PROD_IDLE_SHFT 0xb
+
+#define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_BMSK 0x00000400
+#define HWIO_TCL_R1_STATUS_SW2TCL_CREDIT_CONS_IDLE_SHFT 0xa
+
+#define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_BMSK 0x00000200
+#define HWIO_TCL_R1_STATUS_FW2TCL1_CONS_IDLE_SHFT 0x9
+
+#define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_BMSK 0x00000100
+#define HWIO_TCL_R1_STATUS_SW2TCL3_CONS_IDLE_SHFT 0x8
+
+#define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_BMSK 0x00000080
+#define HWIO_TCL_R1_STATUS_SW2TCL2_CONS_IDLE_SHFT 0x7
+
+#define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_BMSK 0x00000040
+#define HWIO_TCL_R1_STATUS_SW2TCL1_CONS_IDLE_SHFT 0x6
+
+#define HWIO_TCL_R1_STATUS_GXI_IDLE_BMSK 0x00000020
+#define HWIO_TCL_R1_STATUS_GXI_IDLE_SHFT 0x5
+
+#define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_BMSK 0x00000010
+#define HWIO_TCL_R1_STATUS_DESC_RD_IDLE_SHFT 0x4
+
+#define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_BMSK 0x00000008
+#define HWIO_TCL_R1_STATUS_SDU_HDR_FETCH_IDLE_SHFT 0x3
+
+#define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_BMSK 0x00000004
+#define HWIO_TCL_R1_STATUS_LINK_DESC_FETCH_IDLE_SHFT 0x2
+
+#define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_BMSK 0x00000002
+#define HWIO_TCL_R1_STATUS_DATA_FETCH_IDLE_SHFT 0x1
+
+#define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_BMSK 0x00000001
+#define HWIO_TCL_R1_STATUS_TCL_INT_IDLE_SHFT 0x0
+
+//// Register TCL_R1_TESTBUS_CTRL_0 ////
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x00001010)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x00001010)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x3fffffff
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x20000000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x1d
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0
+
+//// Register TCL_R1_TESTBUS_LOW ////
+
+#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x00001014)
+#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x00001014)
+#define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff
+#define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0
+#define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK)
+#define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask)
+#define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0
+
+//// Register TCL_R1_TESTBUS_HIGH ////
+
+#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001018)
+#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001018)
+#define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff
+#define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0
+#define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK)
+#define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask)
+#define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff
+#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_0 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x0000101c)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x0000101c)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0
+#define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_1 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x00001020)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x00001020)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0
+#define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_2 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00001024)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00001024)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0
+#define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_3 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001028)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001028)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0
+#define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0
+
+//// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL ////
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x0000102c)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x0000102c)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0
+
+//// Register TCL_R1_SPARE_REGISTER ////
+
+#define HWIO_TCL_R1_SPARE_REGISTER_ADDR(x) (x+0x00001030)
+#define HWIO_TCL_R1_SPARE_REGISTER_PHYS(x) (x+0x00001030)
+#define HWIO_TCL_R1_SPARE_REGISTER_RMSK 0xffffffff
+#define HWIO_TCL_R1_SPARE_REGISTER_SHFT 0
+#define HWIO_TCL_R1_SPARE_REGISTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), HWIO_TCL_R1_SPARE_REGISTER_RMSK)
+#define HWIO_TCL_R1_SPARE_REGISTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), mask)
+#define HWIO_TCL_R1_SPARE_REGISTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), val)
+#define HWIO_TCL_R1_SPARE_REGISTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), mask, val, HWIO_TCL_R1_SPARE_REGISTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_BMSK 0xffffffff
+#define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_SHFT 0x0
+
+//// Register TCL_R1_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001034)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001034)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+//// Register TCL_R1_ASE_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x00001038)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x00001038)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+//// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x0000103c)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x0000103c)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0
+
+//// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x00001040)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x00001040)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0
+
+//// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001044)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001044)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0
+
+//// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x00001048)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x00001048)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0
+
+//// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x0000104c)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x0000104c)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0
+
+//// Register TCL_R1_ASE_SM_STATES ////
+
+#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x00001050)
+#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x00001050)
+#define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fff0f
+#define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0
+#define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK)
+#define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000
+#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14
+
+#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000
+#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8
+
+#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f
+#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001054)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001054)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x00001058)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x00001058)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \
+ out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x105C+0x4*n)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x105C+0x4*n)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \
+ in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \
+ out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0
+
+//// Register TCL_R2_SW2TCL1_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_SW2TCL1_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R2_SW2TCL2_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_SW2TCL2_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R2_SW2TCL3_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_SW2TCL3_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R2_SW2TCL_CREDIT_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) (x+0x00002018)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_PHYS(x) (x+0x00002018)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_SHFT 0
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_SW2TCL_CREDIT_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x) (x+0x0000201c)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_PHYS(x) (x+0x0000201c)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_SHFT 0
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R2_FW2TCL1_RING_HP ////
+
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_FW2TCL1_RING_TP ////
+
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R2_TCL2TQM_RING_HP ////
+
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_TCL2TQM_RING_TP ////
+
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R2_TCL_STATUS1_RING_HP ////
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_TCL_STATUS1_RING_TP ////
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R2_TCL_STATUS2_RING_HP ////
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_TCL_STATUS2_RING_TP ////
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register TCL_R2_TCL2FW_RING_HP ////
+
+#define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0
+#define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register TCL_R2_TCL2FW_RING_TP ////
+
+#define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0
+#define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \
+ out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0
+
+
+#endif
+
diff --git a/hw/qca5018/macrx_abort_request_info.h b/hw/qca5018/macrx_abort_request_info.h
new file mode 100644
index 0000000..27b13eb
--- /dev/null
+++ b/hw/qca5018/macrx_abort_request_info.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _MACRX_ABORT_REQUEST_INFO_H_
+#define _MACRX_ABORT_REQUEST_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 macrx_abort_reason[7:0], reserved_0[15:8]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1
+
+struct macrx_abort_request_info {
+ uint16_t macrx_abort_reason : 8, //[7:0]
+ reserved_0 : 8; //[15:8]
+};
+
+/*
+
+macrx_abort_reason
+
+ <enum 0 macrx_abort_sw_initiated>
+
+ <enum 1 macrx_abort_obss_reception> Upon receiving this
+ abort reason, PHY should stop reception of the current frame
+ and go back into a search mode
+
+ <enum 2 macrx_abort_other>
+
+ <enum 3 macrx_abort_sw_initiated_channel_switch > MAC FW
+ issued an abort for channel switch reasons
+
+ <enum 4 macrx_abort_sw_initiated_power_save > MAC FW
+ issued an abort power save reasons
+
+ <enum 5 macrx_abort_too_much_bad_data > RXPCU is
+ terminating the current ongoing reception, as the data that
+ MAC is receiving seems to be all garbage... The PER is too
+ high, or in case of MU UL, Likely the trigger frame never
+ got properly received by any of the targeted MU UL devices.
+ After the abort, PHYRX can resume a normal search mode.
+
+
+
+ <legal 0-5>
+
+reserved_0
+
+ <legal 0>
+*/
+
+
+/* Description MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON
+
+ <enum 0 macrx_abort_sw_initiated>
+
+ <enum 1 macrx_abort_obss_reception> Upon receiving this
+ abort reason, PHY should stop reception of the current frame
+ and go back into a search mode
+
+ <enum 2 macrx_abort_other>
+
+ <enum 3 macrx_abort_sw_initiated_channel_switch > MAC FW
+ issued an abort for channel switch reasons
+
+ <enum 4 macrx_abort_sw_initiated_power_save > MAC FW
+ issued an abort power save reasons
+
+ <enum 5 macrx_abort_too_much_bad_data > RXPCU is
+ terminating the current ongoing reception, as the data that
+ MAC is receiving seems to be all garbage... The PER is too
+ high, or in case of MU UL, Likely the trigger frame never
+ got properly received by any of the targeted MU UL devices.
+ After the abort, PHYRX can resume a normal search mode.
+
+
+
+ <legal 0-5>
+*/
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_OFFSET 0x00000000
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_LSB 0
+#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_MASK 0x000000ff
+
+/* Description MACRX_ABORT_REQUEST_INFO_0_RESERVED_0
+
+ <legal 0>
+*/
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 8
+#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000ff00
+
+
+#endif // _MACRX_ABORT_REQUEST_INFO_H_
diff --git a/hw/qca5018/phyrx_abort_request_info.h b/hw/qca5018/phyrx_abort_request_info.h
new file mode 100644
index 0000000..8de8c6c
--- /dev/null
+++ b/hw/qca5018/phyrx_abort_request_info.h
@@ -0,0 +1,413 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_ABORT_REQUEST_INFO_H_
+#define _PHYRX_ABORT_REQUEST_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 phyrx_abort_reason[7:0], phy_enters_nap_state[8], phy_enters_defer_state[9], reserved_0[15:10], receive_duration[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1
+
+struct phyrx_abort_request_info {
+ uint32_t phyrx_abort_reason : 8, //[7:0]
+ phy_enters_nap_state : 1, //[8]
+ phy_enters_defer_state : 1, //[9]
+ reserved_0 : 6, //[15:10]
+ receive_duration : 16; //[31:16]
+};
+
+/*
+
+phyrx_abort_reason
+
+ <enum 0 phyrx_err_phy_off> Reception aborted due to
+ receiving a PHY_OFF TLV
+
+ <enum 1 phyrx_err_synth_off>
+
+ <enum 2 phyrx_err_ofdma_timing>
+
+ <enum 3 phyrx_err_ofdma_signal_parity>
+
+ <enum 4 phyrx_err_ofdma_rate_illegal>
+
+ <enum 5 phyrx_err_ofdma_length_illegal>
+
+ <enum 6 phyrx_err_ofdma_restart>
+
+ <enum 7 phyrx_err_ofdma_service>
+
+ <enum 8 phyrx_err_ppdu_ofdma_power_drop>
+
+
+
+ <enum 9 phyrx_err_cck_blokker>
+
+ <enum 10 phyrx_err_cck_timing>
+
+ <enum 11 phyrx_err_cck_header_crc>
+
+ <enum 12 phyrx_err_cck_rate_illegal>
+
+ <enum 13 phyrx_err_cck_length_illegal>
+
+ <enum 14 phyrx_err_cck_restart>
+
+ <enum 15 phyrx_err_cck_service>
+
+ <enum 16 phyrx_err_cck_power_drop>
+
+
+
+ <enum 17 phyrx_err_ht_crc_err>
+
+ <enum 18 phyrx_err_ht_length_illegal>
+
+ <enum 19 phyrx_err_ht_rate_illegal>
+
+ <enum 20 phyrx_err_ht_zlf>
+
+ <enum 21 phyrx_err_false_radar_ext>
+
+
+
+ <enum 22 phyrx_err_green_field>
+
+
+
+ <enum 23 phyrx_err_bw_gt_dyn_bw>
+
+ <enum 24 phyrx_err_leg_ht_mismatch>
+
+ <enum 25 phyrx_err_vht_crc_error>
+
+ <enum 26 phyrx_err_vht_siga_unsupported>
+
+ <enum 27 phyrx_err_vht_lsig_len_invalid>
+
+ <enum 28 phyrx_err_vht_ndp_or_zlf>
+
+ <enum 29 phyrx_err_vht_nsym_lt_zero>
+
+ <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch>
+
+ <enum 31 phyrx_err_vht_rx_skip_group_id0>
+
+ <enum 32 phyrx_err_vht_rx_skip_group_id1to62>
+
+ <enum 33 phyrx_err_vht_rx_skip_group_id63>
+
+ <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled>
+
+ <enum 35 phyrx_err_defer_nap>
+
+ <enum 36 phyrx_err_fdomain_timeout>
+
+ <enum 37 phyrx_err_lsig_rel_check>
+
+ <enum 38 phyrx_err_bt_collision>
+
+ <enum 39 phyrx_err_unsupported_mu_feedback>
+
+ <enum 40 phyrx_err_ppdu_tx_interrupt_rx>
+
+ <enum 41 phyrx_err_unsupported_cbf>
+
+
+
+ <enum 42 phyrx_err_other> Should not really be used. If
+ needed, ask for documentation update
+
+
+
+ <enum 43 phyrx_err_he_siga_unsupported > <enum 44
+ phyrx_err_he_crc_error > <enum 45
+ phyrx_err_he_sigb_unsupported > <enum 46
+ phyrx_err_he_mu_mode_unsupported > <enum 47
+ phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero
+ > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50
+ phyrx_err_he_num_users_unsupported ><enum 51
+ phyrx_err_he_sounding_params_unsupported >
+
+
+
+ <enum 52 phyrx_err_MU_UL_no_power_detected>
+
+ <enum 53 phyrx_err_MU_UL_not_for_me>
+
+
+
+ <legal 0 - 53>
+
+phy_enters_nap_state
+
+ When set, PHY enters PHY NAP state after sending this
+ abort
+
+
+
+ Note that nap and defer state are mutually exclusive.
+
+
+
+ Field put pro-actively in place....usage still to be
+ agreed upon.
+
+ <legal all>
+
+phy_enters_defer_state
+
+ When set, PHY enters PHY defer state after sending this
+ abort
+
+
+
+ Note that nap and defer state are mutually exclusive.
+
+
+
+ Field put pro-actively in place....usage still to be
+ agreed upon.
+
+ <legal all>
+
+reserved_0
+
+ <legal 0>
+
+receive_duration
+
+ The remaining receive duration of this PPDU in the
+ medium (in us). When PHY does not know this duration when
+ this TLV is generated, the field will be set to 0.
+
+ The timing reference point is the reception by the MAC
+ of this TLV. The value shall be accurate to within 2us.
+
+
+
+ In case Phy_enters_nap_state and/or
+ Phy_enters_defer_state is set, there is a possibility that
+ MAC PMM can also decide to go into a low(er) power state.
+
+ <legal all>
+*/
+
+
+/* Description PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON
+
+ <enum 0 phyrx_err_phy_off> Reception aborted due to
+ receiving a PHY_OFF TLV
+
+ <enum 1 phyrx_err_synth_off>
+
+ <enum 2 phyrx_err_ofdma_timing>
+
+ <enum 3 phyrx_err_ofdma_signal_parity>
+
+ <enum 4 phyrx_err_ofdma_rate_illegal>
+
+ <enum 5 phyrx_err_ofdma_length_illegal>
+
+ <enum 6 phyrx_err_ofdma_restart>
+
+ <enum 7 phyrx_err_ofdma_service>
+
+ <enum 8 phyrx_err_ppdu_ofdma_power_drop>
+
+
+
+ <enum 9 phyrx_err_cck_blokker>
+
+ <enum 10 phyrx_err_cck_timing>
+
+ <enum 11 phyrx_err_cck_header_crc>
+
+ <enum 12 phyrx_err_cck_rate_illegal>
+
+ <enum 13 phyrx_err_cck_length_illegal>
+
+ <enum 14 phyrx_err_cck_restart>
+
+ <enum 15 phyrx_err_cck_service>
+
+ <enum 16 phyrx_err_cck_power_drop>
+
+
+
+ <enum 17 phyrx_err_ht_crc_err>
+
+ <enum 18 phyrx_err_ht_length_illegal>
+
+ <enum 19 phyrx_err_ht_rate_illegal>
+
+ <enum 20 phyrx_err_ht_zlf>
+
+ <enum 21 phyrx_err_false_radar_ext>
+
+
+
+ <enum 22 phyrx_err_green_field>
+
+
+
+ <enum 23 phyrx_err_bw_gt_dyn_bw>
+
+ <enum 24 phyrx_err_leg_ht_mismatch>
+
+ <enum 25 phyrx_err_vht_crc_error>
+
+ <enum 26 phyrx_err_vht_siga_unsupported>
+
+ <enum 27 phyrx_err_vht_lsig_len_invalid>
+
+ <enum 28 phyrx_err_vht_ndp_or_zlf>
+
+ <enum 29 phyrx_err_vht_nsym_lt_zero>
+
+ <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch>
+
+ <enum 31 phyrx_err_vht_rx_skip_group_id0>
+
+ <enum 32 phyrx_err_vht_rx_skip_group_id1to62>
+
+ <enum 33 phyrx_err_vht_rx_skip_group_id63>
+
+ <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled>
+
+ <enum 35 phyrx_err_defer_nap>
+
+ <enum 36 phyrx_err_fdomain_timeout>
+
+ <enum 37 phyrx_err_lsig_rel_check>
+
+ <enum 38 phyrx_err_bt_collision>
+
+ <enum 39 phyrx_err_unsupported_mu_feedback>
+
+ <enum 40 phyrx_err_ppdu_tx_interrupt_rx>
+
+ <enum 41 phyrx_err_unsupported_cbf>
+
+
+
+ <enum 42 phyrx_err_other> Should not really be used. If
+ needed, ask for documentation update
+
+
+
+ <enum 43 phyrx_err_he_siga_unsupported > <enum 44
+ phyrx_err_he_crc_error > <enum 45
+ phyrx_err_he_sigb_unsupported > <enum 46
+ phyrx_err_he_mu_mode_unsupported > <enum 47
+ phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero
+ > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50
+ phyrx_err_he_num_users_unsupported ><enum 51
+ phyrx_err_he_sounding_params_unsupported >
+
+
+
+ <enum 52 phyrx_err_MU_UL_no_power_detected>
+
+ <enum 53 phyrx_err_MU_UL_not_for_me>
+
+
+
+ <legal 0 - 53>
+*/
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB 0
+#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK 0x000000ff
+
+/* Description PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE
+
+ When set, PHY enters PHY NAP state after sending this
+ abort
+
+
+
+ Note that nap and defer state are mutually exclusive.
+
+
+
+ Field put pro-actively in place....usage still to be
+ agreed upon.
+
+ <legal all>
+*/
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB 8
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK 0x00000100
+
+/* Description PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE
+
+ When set, PHY enters PHY defer state after sending this
+ abort
+
+
+
+ Note that nap and defer state are mutually exclusive.
+
+
+
+ Field put pro-actively in place....usage still to be
+ agreed upon.
+
+ <legal all>
+*/
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB 9
+#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
+
+/* Description PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0
+
+ <legal 0>
+*/
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 10
+#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000fc00
+
+/* Description PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION
+
+ The remaining receive duration of this PPDU in the
+ medium (in us). When PHY does not know this duration when
+ this TLV is generated, the field will be set to 0.
+
+ The timing reference point is the reception by the MAC
+ of this TLV. The value shall be accurate to within 2us.
+
+
+
+ In case Phy_enters_nap_state and/or
+ Phy_enters_defer_state is set, there is a possibility that
+ MAC PMM can also decide to go into a low(er) power state.
+
+ <legal all>
+*/
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB 16
+#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK 0xffff0000
+
+
+#endif // _PHYRX_ABORT_REQUEST_INFO_H_
diff --git a/hw/qca5018/phyrx_he_sig_a_mu_dl.h b/hw/qca5018/phyrx_he_sig_a_mu_dl.h
new file mode 100644
index 0000000..211a136
--- /dev/null
+++ b/hw/qca5018/phyrx_he_sig_a_mu_dl.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_HE_SIG_A_MU_DL_H_
+#define _PHYRX_HE_SIG_A_MU_DL_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_mu_dl_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2
+
+struct phyrx_he_sig_a_mu_dl {
+ struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details;
+};
+
+/*
+
+struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details */
+
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG
+
+ Differentiates between DL and UL transmission
+
+
+
+ <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
+
+ <enum 1 DL_UL_FLAG_IS_UL>
+
+ NOTE: This is unsupported for HE MU format (including
+ MU_SU) Tx in Napier and Hastings80.
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B
+
+ Indicates the MCS of HE-SIG-B
+
+ <legal 0-5>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B
+
+ Indicates whether dual sub-carrier modulation is applied
+ to HE-SIG-B
+
+
+
+ 0: No DCM for HE_SIG_B
+
+ 1: DCM for HE_SIG_B
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID
+
+ BSS color ID
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE
+
+ Spatial reuse
+
+
+
+ For 20MHz one SR field corresponding to entire 20MHz
+ (other 3 fields indicate identical values)
+
+ For 40MHz two SR fields for each 20MHz (other 2 fields
+ indicate identical values)
+
+ For 80MHz four SR fields for each 20MHz
+
+ For 160MHz four SR fields for each 40MHz
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW
+
+ Bandwidth of the PPDU.
+
+
+
+ <enum 0 HE_SIG_A_MU_DL_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_MU_DL_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_MU_DL_BW80> 80 MHz non-preamble
+ puncturing mode
+
+ <enum 3 HE_SIG_A_MU_DL_BW160> 160 MHz and 80+80 MHz
+ non-preamble puncturing mode
+
+ <enum 4 HE_SIG_A_MU_DL_BW80_SEC_20_PUNC> for preamble
+ puncturing in 80 MHz, where in the preamble only the
+ secondary 20 MHz is punctured
+
+ <enum 5 HE_SIG_A_MU_DL_BW80_20_PUNC_IN_SEC_40> for
+ preamble puncturing in 80 MHz, where in the preamble only
+ one of the two 20 MHz sub-channels in secondary 40 MHz is
+ punctured.
+
+ <enum 6 HE_SIG_A_MU_DL_BW160_SEC_20_PUNC> for preamble
+ puncturing in 160 MHz or 80+80 MHz, where in the primary 80
+ MHz of the preamble only the secondary 20 MHz is punctured.
+
+ <enum 7 HE_SIG_A_MU_DL_BW160_SEC_40_80_PUNC> for
+ preamble puncturing in 160 MHz or 80+80 MHz, where in the
+ primary 80 MHz of the preamble the primary 40 MHz is
+ present.
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal 0-7>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS
+
+ Number of symbols
+
+
+
+ For OFDMA, the actual number of symbols is 1 larger then
+ indicated in this field.
+
+
+
+ For MU-MIMO this is equal to the number of users - 1:
+ the following encoding is used:
+
+ 1 => 2 users
+
+ 2 => 3 users
+
+ Etc.
+
+
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B
+
+ Indicates the compression mode of HE-SIG-B
+
+
+
+ 0: Regular [uncomp mode]
+
+ 1: compressed mode (full-BW MU-MIMO only)
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE
+
+ Indicates the CP and HE-LTF type
+
+
+
+ <enum 0 MU_FourX_LTF_0_8CP> 4xLTF + 0.8 us CP
+
+ <enum 1 MU_TwoX_LTF_0_8CP> 2x LTF + 0.8 µs CP
+
+ <enum 2 MU_TwoX_LTF_1_6CP> 2x LTF + 1.6 µs CP
+
+ <enum 3 MU_FourX_LTF_3_2CP> 4x LTF + 3.2 µs CP
+
+
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION
+
+ 0: No Doppler support
+
+ 1: Doppler support
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
+#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION
+
+ Indicates the remaining time in the current TXOP
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS
+
+ Indicates the number of HE-LTF symbols
+
+
+
+ 0: 1 LTF
+
+ 1: 2 LTFs
+
+ 2: 4 LTFs
+
+ 3: 6 LTFs
+
+ 4: 8 LTFs
+
+
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL
+
+ If LDPC,
+
+ 0: LDPC extra symbol not present
+
+ 1: LDPC extra symbol present
+
+ Else
+
+ Set to 1
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC
+
+ Indicates whether STBC is applied
+
+ 0: No STBC
+
+ 1: STBC
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR
+
+ the packet extension duration of the trigger-based PPDU
+ response with these two bits indicating the a-factor
+
+
+
+ <enum 0 a_factor_4>
+
+ <enum 1 a_factor_1>
+
+ <enum 2 a_factor_2>
+
+ <enum 3 a_factor_3>
+
+
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY
+
+ the packet extension duration of the trigger-based PPDU
+ response with this bit indicating the PE-Disambiguity
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC
+
+ CRC for HE-SIG-A contents.
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
+
+
+#endif // _PHYRX_HE_SIG_A_MU_DL_H_
diff --git a/hw/qca5018/phyrx_he_sig_a_mu_ul.h b/hw/qca5018/phyrx_he_sig_a_mu_ul.h
new file mode 100644
index 0000000..9f74e92
--- /dev/null
+++ b/hw/qca5018/phyrx_he_sig_a_mu_ul.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_HE_SIG_A_MU_UL_H_
+#define _PHYRX_HE_SIG_A_MU_UL_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_mu_ul_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2
+
+struct phyrx_he_sig_a_mu_ul {
+ struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details;
+};
+
+/*
+
+struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details */
+
+
+/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION
+
+ Indicates whether the transmission is SU PPDU or a
+ trigger based UL MU PDDU
+
+ <enum 0 HE_SIGA_FORMAT_HE_TRIG>
+
+ <enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID
+
+ BSS color ID
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e
+
+/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE
+
+ Spatial reuse
+
+
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80
+
+/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000
+
+/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW
+
+ Bandwidth of the PPDU.
+
+
+
+ <enum 0 HE_SIG_A_MU_UL_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_MU_UL_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_MU_UL_BW80> 80 Mhz
+
+ <enum 3 HE_SIG_A_MU_UL_BW160> 160 MHz or 80+80 MHz
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal 0-3>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000
+
+/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
+#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION
+
+ Indicates the remaining time in the current TXOP <legal
+ all>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A
+
+ Set to value indicated in the trigger frame
+
+ <legal 255>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80
+
+/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC
+
+ CRC for HE-SIG-A contents.
+
+ This CRC may also cover some fields of L-SIG (TBD)
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000
+
+/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL
+
+ BCC encoding (similar to VHT-SIG-A) with 6 tail bits is
+ used
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26
+#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000
+
+
+#endif // _PHYRX_HE_SIG_A_MU_UL_H_
diff --git a/hw/qca5018/phyrx_he_sig_a_su.h b/hw/qca5018/phyrx_he_sig_a_su.h
new file mode 100644
index 0000000..454b5bf
--- /dev/null
+++ b/hw/qca5018/phyrx_he_sig_a_su.h
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_HE_SIG_A_SU_H_
+#define _PHYRX_HE_SIG_A_SU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_a_su_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2
+
+struct phyrx_he_sig_a_su {
+ struct he_sig_a_su_info phyrx_he_sig_a_su_info_details;
+};
+
+/*
+
+struct he_sig_a_su_info phyrx_he_sig_a_su_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct he_sig_a_su_info phyrx_he_sig_a_su_info_details */
+
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION
+
+ <enum 0 HE_SIGA_FORMAT_HE_TRIG>
+
+ <enum 1 HE_SIGA_FORMAT_SU_OR_EXT_SU>
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE
+
+ Indicates whether spatial mapping is changed between
+ legacy and HE portion of preamble. If not, channel
+ estimation can include legacy preamble to improve accuracy
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG
+
+ Differentiates between DL and UL transmission
+
+
+
+ <enum 0 DL_UL_FLAG_IS_DL_OR_TDLS>
+
+ <enum 1 DL_UL_FLAG_IS_UL>
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS
+
+ Indicates the data MCS
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM
+
+
+ 0: No DCM
+
+ 1:DCM
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID
+
+ BSS color ID
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A
+
+ Note: spec indicates this shall be set to 1
+
+ <legal 1>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE
+
+ Spatial reuse
+
+
+
+ For 20MHz one SR field corresponding to entire 20MHz
+ (other 3 fields indicate identical values)
+
+ For 40MHz two SR fields for each 20MHz (other 2 fields
+ indicate identical values)
+
+ For 80MHz four SR fields for each 20MHz
+
+ For 160MHz four SR fields for each 40MHz
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW
+
+ Bandwidth of the PPDU.
+
+
+
+ For HE SU PPDU
+
+
+ <enum 0 HE_SIG_A_BW20> 20 Mhz
+
+ <enum 1 HE_SIG_A_BW40> 40 Mhz
+
+ <enum 2 HE_SIG_A_BW80> 80 Mhz
+
+ <enum 3 HE_SIG_A_BW160> 160 MHz or 80+80 MHz
+
+
+
+ For HE Extended Range SU PPDU
+
+ Set to 0 for 242-tone RU
+ Set to 1 for right 106-tone RU within the primary 20 MHz
+
+
+
+ On RX side, Field Used by MAC HW
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE
+
+ Indicates the CP and HE-LTF type
+
+
+
+
+ <enum 3 FourX_LTF_0_8CP_3_2CP>
+
+ When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP
+
+ When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note:
+ In this scenario, Neither DCM nor STBC is applied to HE data
+ field.
+
+
+ NOTE:
+
+
+ If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0)
+
+ 0 = 1xLTF + 0.4 usec
+
+ 1 = 2xLTF + 0.4 usec
+
+ 2~3 = Reserved
+
+
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS
+
+
+
+
+ For HE SU PPDU
+
+
+
+ For HE Extended Range PPDU
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000
+
+/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
+#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION
+
+ Indicates the remaining time in the current TXOP
+
+
+
+ Field Used by MAC HW
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING
+
+ Distinguishes between BCC and LDPC coding.
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL
+
+ If LDPC,
+
+ 0: LDPC extra symbol not present
+
+ 1: LDPC extra symbol present
+
+ Else
+
+ Set to 1
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC
+
+ Indicates whether STBC is applied
+
+ 0: No STBC
+
+ 1: STBC
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF
+
+ Indicates whether beamforming is applied
+
+ 0: No beamforming
+
+ 1: beamforming
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR
+
+ Common trigger info
+
+
+
+ the packet extension duration of the trigger-based PPDU
+ response with these two bits indicating the a-factor
+
+
+
+ <enum 0 a_factor_4>
+
+ <enum 1 a_factor_1>
+
+ <enum 2 a_factor_2>
+
+ <enum 3 a_factor_3>
+
+
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY
+
+ Common trigger info
+
+
+
+ the packet extension duration of the trigger-based PPDU
+ response with this bit indicating the PE-Disambiguity
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A
+
+ Note: per standard, set to 1
+
+ <legal 1>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION
+
+ 0: No Doppler support
+
+ 1: Doppler support
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC
+
+ CRC for HE-SIG-A contents.
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:
+
+ On RX side, evaluated by MAC HW. This is the only way
+ for MAC RX to know that this was an HE_SIG_A_SU received in
+ 'extended' format
+
+
+
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:
+
+ Field only contains valid info when dot11ax_su_extended
+ is set.
+
+
+
+ On RX side, evaluated by MAC HW. This is the only way
+ for MAC RX to know what the number of based RUs was in this
+ extended range reception. It is used by the MAC to determine
+ the RU size for the response...
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x78000000
+
+/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP
+
+ TX side:
+
+ Set to 0
+
+
+
+ RX side:Valid on RX side only, and looked at by MAC HW
+
+
+
+ When set, PHY has received (expected) NDP frame
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 31
+#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x80000000
+
+
+#endif // _PHYRX_HE_SIG_A_SU_H_
diff --git a/hw/qca5018/phyrx_he_sig_b1_mu.h b/hw/qca5018/phyrx_he_sig_b1_mu.h
new file mode 100644
index 0000000..2e58763
--- /dev/null
+++ b/hw/qca5018/phyrx_he_sig_b1_mu.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_HE_SIG_B1_MU_H_
+#define _PHYRX_HE_SIG_B1_MU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b1_mu_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1
+
+struct phyrx_he_sig_b1_mu {
+ struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details;
+};
+
+/*
+
+struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details */
+
+
+/* Description PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION
+
+ RU allocation for the user(s) following this common
+ portion of the SIG
+
+
+
+ For details, refer to RU_TYPE description
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff
+
+/* Description PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
+#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0xffffff00
+
+
+#endif // _PHYRX_HE_SIG_B1_MU_H_
diff --git a/hw/qca5018/phyrx_he_sig_b2_mu.h b/hw/qca5018/phyrx_he_sig_b2_mu.h
new file mode 100644
index 0000000..b49d7b7
--- /dev/null
+++ b/hw/qca5018/phyrx_he_sig_b2_mu.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_HE_SIG_B2_MU_H_
+#define _PHYRX_HE_SIG_B2_MU_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b2_mu_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 1
+
+struct phyrx_he_sig_b2_mu {
+ struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details;
+};
+
+/*
+
+struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details */
+
+
+/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID
+
+ Identifies the STA that is addressed. Details of STA ID
+ are TBD
+*/
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG
+
+ Number of assigned spatial streams and their
+ corresponding index.
+
+ Total number of spatial streams assigned for the MU-MIMO
+ allocation is also signaled.
+*/
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800
+
+/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS
+
+ Indicates the data MCS
+*/
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1
+
+ <legal 1>
+*/
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000
+
+/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING
+
+ Distinguishes between BCC/LDPC
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x1fe00000
+
+/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS
+
+ MAC RX side usage only:
+
+ Needed by RXPCU. Provided by PHY so that RXPCU does not
+ need to have the RU number decoding logic.
+
+
+
+ Number of spatial streams for this user
+
+
+
+ <enum 0 1_spatial_stream>Single spatial stream
+
+ <enum 1 2_spatial_streams>2 spatial streams
+
+ <enum 2 3_spatial_streams>3 spatial streams
+
+ <enum 3 4_spatial_streams>4 spatial streams
+
+ <enum 4 5_spatial_streams>5 spatial streams
+
+ <enum 5 6_spatial_streams>6 spatial streams
+
+ <enum 6 7_spatial_streams>7 spatial streams
+
+ <enum 7 8_spatial_streams>8 spatial streams
+*/
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 29
+#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0xe0000000
+
+
+#endif // _PHYRX_HE_SIG_B2_MU_H_
diff --git a/hw/qca5018/phyrx_he_sig_b2_ofdma.h b/hw/qca5018/phyrx_he_sig_b2_ofdma.h
new file mode 100644
index 0000000..1446dcb
--- /dev/null
+++ b/hw/qca5018/phyrx_he_sig_b2_ofdma.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_
+#define _PHYRX_HE_SIG_B2_OFDMA_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "he_sig_b2_ofdma_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 1
+
+struct phyrx_he_sig_b2_ofdma {
+ struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details;
+};
+
+/*
+
+struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details */
+
+
+/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID
+
+ Identifies the STA that is addressed. Details of STA ID
+ are TBD
+*/
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff
+
+/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS
+
+ MAC RX side usage only:
+
+
+
+ Number of spatial streams for this user
+
+
+
+ <enum 0 1_spatial_stream>Single spatial stream
+
+ <enum 1 2_spatial_streams>2 spatial streams
+
+ <enum 2 3_spatial_streams>3 spatial streams
+
+ <enum 3 4_spatial_streams>4 spatial streams
+
+ <enum 4 5_spatial_streams>5 spatial streams
+
+ <enum 5 6_spatial_streams>6 spatial streams
+
+ <enum 6 7_spatial_streams>7 spatial streams
+
+ <enum 7 8_spatial_streams>8 spatial streams
+*/
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800
+
+/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF
+
+ Indicates whether beamforming is applied
+
+ 0: No beamforming
+
+ 1: beamforming
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000
+
+/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS
+
+ Indicates the data MCS
+*/
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000
+
+/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM
+
+
+ 0: No DCM
+
+ 1:DCM
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000
+
+/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING
+
+ Distinguishes between BCC/LDPC
+
+
+
+ 0: BCC
+
+ 1: LDPC
+
+ <legal all>
+*/
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000
+
+/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0
+
+ <legal 0>
+*/
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
+#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0xffe00000
+
+
+#endif // _PHYRX_HE_SIG_B2_OFDMA_H_
diff --git a/hw/qca5018/phyrx_ht_sig.h b/hw/qca5018/phyrx_ht_sig.h
new file mode 100644
index 0000000..4ad0763
--- /dev/null
+++ b/hw/qca5018/phyrx_ht_sig.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_HT_SIG_H_
+#define _PHYRX_HT_SIG_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "ht_sig_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct ht_sig_info phyrx_ht_sig_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_HT_SIG 2
+
+struct phyrx_ht_sig {
+ struct ht_sig_info phyrx_ht_sig_info_details;
+};
+
+/*
+
+struct ht_sig_info phyrx_ht_sig_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct ht_sig_info phyrx_ht_sig_info_details */
+
+
+/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS
+
+ Modulation Coding Scheme:
+
+ 0-7 are used for single stream
+
+ 8-15 are used for 2 streams
+
+ 16-23 are used for 3 streams
+
+ 24-31 are used for 4 streams
+
+ 32 is used for duplicate HT20 (unsupported)
+
+ 33-76 is used for unequal modulation (unsupported)
+
+ 77-127 is reserved.
+
+ <legal 0-31>
+*/
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f
+
+/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW
+
+ Packet bandwidth:
+
+ <enum 0 ht_20_mhz>
+
+ <enum 1 ht_40_mhz>
+
+ <legal 0-1>
+*/
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080
+
+/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH
+
+ This is the MPDU or A-MPDU length in octets of the PPDU
+
+ <legal all>
+*/
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00
+
+/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0
+
+ This field is not part of HT-SIG
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+*/
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
+#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING
+
+ Field indicates if smoothing is needed
+
+ E_num 0 do_smoothing Unsupported setting: indicates
+ smoothing is often used for beamforming
+
+
+ <legal 1>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING
+
+ E_num 0 sounding Unsupported setting: indicates
+ sounding is used
+
+ <enum 1 no_sounding> Indicates no sounding is used
+
+ <legal 1>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED
+
+ Reserved: Should be set to 1 by the MAC and ignored by
+ the PHY
+
+ <legal 1>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION
+
+ <enum 0 mpdu> Indicates MPDU format
+
+ <enum 1 a_mpdu> Indicates A-MPDU format
+
+ <legal 0-1>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC
+
+ <enum 0 no_stbc> Indicates no STBC
+
+ <enum 1 1_str_stbc> Indicates 1 stream STBC
+
+ E_num 2 2_str_stbc Indicates 2 stream STBC
+ (Unsupported)
+
+ <legal 0-1>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING
+
+ <enum 0 ht_bcc> Indicates BCC coding
+
+ <enum 1 ht_ldpc> Indicates LDPC coding
+
+ <legal 0-1>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI
+
+ <enum 0 ht_normal_gi> Indicates normal guard
+ interval
+
+
+ <legal 0-1>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR
+
+ Number of extension spatial streams: (Used for TxBF)
+
+ <enum 0 0_ext_sp_str> No extension spatial streams
+
+ E_num 1 1_ext_sp_str Not supported: 1 extension
+ spatial streams
+
+ E_num 2 2_ext_sp_str Not supported: 2 extension
+ spatial streams
+
+ <legal 0>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC
+
+ The CRC protects the HT-SIG (HT-SIG[0][23:0] and
+ HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 +
+ D + 1. <legal all>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL
+
+ The 6 bits of tail is always set to 0 is used to flush
+ the BCC encoder and decoder. <legal 0>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000
+
+/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY. <legal 0>
+*/
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24
+#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0xff000000
+
+
+#endif // _PHYRX_HT_SIG_H_
diff --git a/hw/qca5018/phyrx_l_sig_a.h b/hw/qca5018/phyrx_l_sig_a.h
new file mode 100644
index 0000000..0a5e225
--- /dev/null
+++ b/hw/qca5018/phyrx_l_sig_a.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_L_SIG_A_H_
+#define _PHYRX_L_SIG_A_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "l_sig_a_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct l_sig_a_info phyrx_l_sig_a_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1
+
+struct phyrx_l_sig_a {
+ struct l_sig_a_info phyrx_l_sig_a_info_details;
+};
+
+/*
+
+struct l_sig_a_info phyrx_l_sig_a_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct l_sig_a_info phyrx_l_sig_a_info_details */
+
+
+/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE
+
+ This format is originally defined for OFDM as a 4 bit
+ field but the 5th bit was added to indicate 11b formatted
+ frames. In the standard bit [4] is specified as reserved.
+ For 11b frames this L-SIG is transformed in the PHY into the
+ 11b preamble format. The following are the rates:
+
+ <enum 8 ofdm_48_mbps> 64-QAM 2/3 (48 Mbps)
+
+ <enum 9 ofdm_24_mbps> 16-QAM 1/2 (24 Mbps)
+
+ <enum 10 ofdm_12_mbps> QPSK 1/2 (12 Mbps)
+
+ <enum 11 ofdm_6_mbps> BPSK 1/2 (6 Mbps)
+
+ <enum 12 ofdm_54_mbps> 64-QAM 3/4 (54 Mbps)
+
+ <enum 13 ofdm_36_mbps> 16-QAM 3/4 (36 Mbps)
+
+ <enum 14 ofdm_18_mbps> QPSK 1/2 (18 Mbps)
+
+ <enum 15 ofdm_9_mbps> BPSK 3/4 (9 Mbps)
+
+ <legal 8-15>
+*/
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f
+
+/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY
+
+ <legal 0>
+*/
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010
+
+/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH
+
+ The length indicates the number of octets in this MPDU.
+ Note that when using mixed mode 11n preamble this length
+ provides the spoofed length for the PPDU. This length
+ provides part of the information to derive the actually PPDU
+ length. For legacy OFDM and 11B frames the maximum length
+ is
+
+ <legal all>
+*/
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0
+
+/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY
+
+ 11a/n/ac TX: This field provides even parity over the
+ first 18 bits of the signal field which means that the sum
+ of 1s in the signal field will always be even on
+
+ 11a/n/ac RX: this field contains the received parity
+ field from the L-SIG symbol for the current packet.
+
+ <legal 0-1>
+*/
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000
+
+/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL
+
+ The 6 bits of tail is always set to 0 is used to flush
+ the BCC encoder and decoder. <legal 0>
+*/
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
+
+/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE
+
+ Only used on the RX side.
+
+ Note: This is not really part of L-SIG
+
+
+
+ Packet type:
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+*/
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING
+
+ Only used on the RX side.
+
+ Note: This is not really part of L-SIG
+
+
+
+ This indicates that the PHY has captured implicit
+ sounding.
+*/
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000
+
+/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED
+
+ Reserved: Should be set to 0 by the transmitting MAC and
+ ignored by the PHY <legal 0>
+*/
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
+#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0xe0000000
+
+
+#endif // _PHYRX_L_SIG_A_H_
diff --git a/hw/qca5018/phyrx_l_sig_b.h b/hw/qca5018/phyrx_l_sig_b.h
new file mode 100644
index 0000000..b6a7d6c
--- /dev/null
+++ b/hw/qca5018/phyrx_l_sig_b.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_L_SIG_B_H_
+#define _PHYRX_L_SIG_B_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "l_sig_b_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct l_sig_b_info phyrx_l_sig_b_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1
+
+struct phyrx_l_sig_b {
+ struct l_sig_b_info phyrx_l_sig_b_info_details;
+};
+
+/*
+
+struct l_sig_b_info phyrx_l_sig_b_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct l_sig_b_info phyrx_l_sig_b_info_details */
+
+
+/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE
+
+ <enum 1 dsss_1_mpbs_long> DSSS 1 Mbps long
+
+ <enum 2 dsss_2_mbps_long> DSSS 2 Mbps long
+
+ <enum 3 cck_5_5_mbps_long> CCK 5.5 Mbps long
+
+ <enum 4 cck_11_mbps_long> CCK 11 Mbps long
+
+ <enum 5 dsss_2_mbps_short> DSSS 2 Mbps short
+
+ <enum 6 cck_5_5_mbps_short> CCK 5.5 Mbps short
+
+ <enum 7 cck_11_mbps_short> CCK 11 Mbps short
+
+ <legal 1-7>
+*/
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f
+
+/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH
+
+ The length indicates the number of octets in this MPDU.
+
+ <legal all>
+*/
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0
+
+/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED
+
+ Reserved: Should be set to 0 by the transmitting MAC and
+ ignored by the PHY <legal 0>
+*/
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
+#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0xffff0000
+
+
+#endif // _PHYRX_L_SIG_B_H_
diff --git a/hw/qca5018/phyrx_pkt_end.h b/hw/qca5018/phyrx_pkt_end.h
new file mode 100644
index 0000000..01b14e6
--- /dev/null
+++ b/hw/qca5018/phyrx_pkt_end.h
@@ -0,0 +1,1708 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_PKT_END_H_
+#define _PHYRX_PKT_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "phyrx_pkt_end_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-32 struct phyrx_pkt_end_info rx_pkt_end_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_PKT_END 33
+
+struct phyrx_pkt_end {
+ struct phyrx_pkt_end_info rx_pkt_end_details;
+};
+
+/*
+
+struct phyrx_pkt_end_info rx_pkt_end_details
+
+ Overview of the final receive related parameters from
+ the PHY RX
+*/
+
+
+ /* EXTERNAL REFERENCE : struct phyrx_pkt_end_info rx_pkt_end_details */
+
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP
+
+ When set, PHY RX entered an internal NAP state, as PHY
+ determined that this reception was not destined to this
+ device
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID
+
+ Indicates that the RX_LOCATION_INFO structure later on
+ in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID
+
+ Indicates that the RX_TIMING_OFFSET_INFO structure later
+ on in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID
+
+ Indicates that the RECEIVE_RSSI_INFO structure later on
+ in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED
+
+ When clear, no action is needed in the MAC.
+
+
+
+ When set, the falling edge of the rx_frame happened 4us
+ too late. MAC will need to compensate for this delay in
+ order to maintain proper SIFS timing and/or not to get
+ de-slotted.
+
+
+
+ PHY uses this for very short 11a frames.
+
+
+
+ When set, PHY will have passed this TLV to the MAC up to
+ 8 us into the 'real SIFS' time, and thus within 4us from the
+ falling edge of the rx_frame.
+
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_LSB 4
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED
+
+ When set, PHY has received the 'frameless frame' . Can
+ be used in the 'MU-RTS -CTS exchange where CTS reception can
+ be problematic.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_LSB 6
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000fc0
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID
+
+ When set, the following DL_ofdma_... fields are valid.
+
+ It provides the MAC insight into which RU was allocated
+ to this device.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_LSB 12
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_MASK 0x00001000
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX
+
+ RU index number to which User is assigned
+
+ RU numbering is over the entire BW, starting from 0 and
+ in increasing frequency order and not primary-secondary
+ order
+
+ <legal 0-73>
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_LSB 13
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH
+
+ The size of the RU for this user.
+
+ In units of 1 (26 tone) RU
+
+ <legal 1-74>
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_LSB 20
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_MASK 0x07f00000
+
+/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_LSB 27
+#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0xf8000000
+
+/* Description PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32
+
+ TODO PHY: cleanup descriptionThe PHY timestamp in the
+ AMPI of the first rising edge of rx_clear_pri after
+ TX_PHY_DESC. . This field should set to 0 by the PHY and
+ should be updated by the AMPI before being forwarded to the
+ rest of the MAC. This field indicates the lower 32 bits of
+ the timestamp
+*/
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the first rising edge
+ of rx_clear_pri after TX_PHY_DESC. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ lower 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+ /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */
+
+
+/* Description PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the first selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+/* Description PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the second selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16
+#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+/* Description PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the first
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff
+
+/* Description PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the second
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16
+#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS
+
+ Status of rtt_fac_legacy
+
+
+
+ <enum 0 location_fac_legacy_status_not_valid>
+
+ <enum 1 location_fac_legacy_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS
+
+ Status of rtt_fac_legacy_ext80
+
+
+
+ <enum 0 location_fac_legacy_ext80_status_not_valid>
+
+ <enum 1 location_fac_legacy_ext80_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS
+
+ Status of rtt_fac_vht
+
+
+
+ <enum 0 location_fac_vht_status_not_valid>
+
+ <enum 1 location_fac_vht_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS
+
+ Status of rtt_fac_vht_ext80
+
+
+
+ <enum 0 location_fac_vht_ext80_status_not_valid>
+
+ <enum 1 location_fac_vht_ext80_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS
+
+ To support fine SIFS adjustment, need to provide FAC
+ value @ integer number of 320 MHz clock cycles to MAC. It
+ is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF
+ if it is a (V)HT/HE packet
+
+
+
+ 12 bits, signed, no fractional part
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS
+
+ Status of rtt_fac_sifs
+
+ 0: not valid
+
+ 1: valid and from L-LTF
+
+ 2: valid and from (V)HT/HE-LTF
+
+ 3: reserved
+
+ <legal 0-2>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS
+
+ Status of channel frequency response dump
+
+
+
+ <enum 0 location_CFR_dump_not_valid>
+
+ <enum 1 location_CFR_dump_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS
+
+ Status of channel impulse response dump
+
+
+
+ <enum 0 location_CIR_dump_not_valid>
+
+ <enum 1 location_CIR_dump_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE
+
+ Channel dump size. It shows how many tones in CFR in
+ one chain, for example, it will show 52 for Legacy20 and 484
+ for VHT160
+
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE
+
+ Indicator showing if HW IFFT mode or SW IFFT mode
+
+
+
+ <enum 0 location_sw_ifft_mode>
+
+ <enum 1 location_hw_ifft_mode>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31
+#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS
+
+ Indicate if BTCF is used to capture the timestamps
+
+
+
+ <enum 0 location_not_BTCF_based_ts>
+
+ <enum 1 location_BTCF_based_ts>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE
+
+ Indicate preamble type
+
+
+
+ <enum 0 location_preamble_type_legacy>
+
+ <enum 1 location_preamble_type_ht>
+
+ <enum 2 location_preamble_type_vht>
+
+ <enum 3 location_preamble_type_he_su_4xltf>
+
+ <enum 4 location_preamble_type_he_su_2xltf>
+
+ <enum 5 location_preamble_type_he_su_1xltf>
+
+ <enum 6
+ location_preamble_type_he_trigger_based_ul_4xltf>
+
+ <enum 7
+ location_preamble_type_he_trigger_based_ul_2xltf>
+
+ <enum 8
+ location_preamble_type_he_trigger_based_ul_1xltf>
+
+ <enum 9 location_preamble_type_he_mu_4xltf>
+
+ <enum 10 location_preamble_type_he_mu_2xltf>
+
+ <enum 11 location_preamble_type_he_mu_1xltf>
+
+ <enum 12
+ location_preamble_type_he_extended_range_su_4xltf>
+
+ <enum 13
+ location_preamble_type_he_extended_range_su_2xltf>
+
+ <enum 14
+ location_preamble_type_he_extended_range_su_1xltf>
+
+ <legal 0-14>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG
+
+ Indicate the bandwidth of L-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT
+
+ Indicate the bandwidth of (V)HT/HE-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE
+
+ Indicate GI (guard interval) type
+
+
+
+ <enum 0 gi_0_8_us > HE related GI. Can also be used
+ for HE
+
+ <enum 1 gi_0_4_us > HE related GI. Can also be used
+ for HE
+
+ <enum 2 gi_1_6_us > HE related GI
+
+ <enum 3 gi_3_2_us > HE related GI
+
+ <legal 0 - 3>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE
+
+ Bits 0~4 indicate MCS rate, if Legacy,
+
+ 0: 48 Mbps,
+
+ 1: 24 Mbps,
+
+ 2: 12 Mbps,
+
+ 3: 6 Mbps,
+
+ 4: 54 Mbps,
+
+ 5: 36 Mbps,
+
+ 6: 18 Mbps,
+
+ 7: 9 Mbps,
+
+
+
+ if HT, 0-7: MCS0-MCS7,
+
+ if VHT, 0-9: MCS0-MCS9,
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN
+
+ For 20/40/80, this field shows the first selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected pri80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80
+
+ For 20/40/80, this field shows the second selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected ext80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK
+
+ Rx chain mask, each bit is a Rx chain
+
+ 0: the Rx chain is not used
+
+ 1: the Rx chain is used
+
+ Support up to 8 Rx chains
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31
+#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000
+
+/* Description PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS
+
+ RX packet start timestamp
+
+
+
+ It reports the time the first L-STF ADC sample arrived
+ at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS
+
+ RX packet end timestamp
+
+
+
+ It reports the time the last symbol's last ADC sample
+ arrived at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START
+
+ The phase of the SFO of the first symbol's first FFT
+ input sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+/* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END
+
+ The phase of the SFO of the last symbol's last FFT input
+ sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+/* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8
+
+ The high 8 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 8 bits
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32
+
+ The low 32 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 32 bits
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT
+
+ CFO measurement. Needed for passive locationing
+
+
+
+ 14 bits, signed 1.13. 13 bits fraction to provide a
+ resolution of 153 Hz
+
+
+
+ In units of cycles/800 ns
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD
+
+ Channel delay spread measurement. Needed for selecting
+ GI length
+
+
+
+ 8 bits, unsigned. At 25 ns step. Can represent up to
+ 6375 ns
+
+
+
+ In units of cycles @ 40 MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL
+
+ Indicate which timing backoff value is used
+
+
+
+ <enum 0 timing_backoff_low_rssi>
+
+ <enum 1 timing_backoff_mid_rssi>
+
+ <enum 2 timing_backoff_high_rssi>
+
+ <enum 3 reserved>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000
+
+/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID
+
+ <enum 0 rx_location_info_is_not_valid>
+
+ <enum 1 rx_location_info_is_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31
+#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */
+
+
+/* Description PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET
+
+ Cumulative reference frequency error at end of RX
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+/* Description PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+ /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */
+
+
+/* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000007c
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0
+#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x00000080
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0
+#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff
+
+
+#endif // _PHYRX_PKT_END_H_
diff --git a/hw/qca5018/phyrx_pkt_end_info.h b/hw/qca5018/phyrx_pkt_end_info.h
new file mode 100644
index 0000000..5509b7e
--- /dev/null
+++ b/hw/qca5018/phyrx_pkt_end_info.h
@@ -0,0 +1,1896 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_PKT_END_INFO_H_
+#define _PHYRX_PKT_END_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_location_info.h"
+#include "rx_timing_offset_info.h"
+#include "receive_rssi_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27]
+// 1 phy_timestamp_1_lower_32[31:0]
+// 2 phy_timestamp_1_upper_32[31:0]
+// 3 phy_timestamp_2_lower_32[31:0]
+// 4 phy_timestamp_2_upper_32[31:0]
+// 5-13 struct rx_location_info rx_location_info_details;
+// 14 struct rx_timing_offset_info rx_timing_offset_info_details;
+// 15-30 struct receive_rssi_info post_rssi_info_details;
+// 31 phy_sw_status_31_0[31:0]
+// 32 phy_sw_status_63_32[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33
+
+struct phyrx_pkt_end_info {
+ uint32_t phy_internal_nap : 1, //[0]
+ location_info_valid : 1, //[1]
+ timing_info_valid : 1, //[2]
+ rssi_info_valid : 1, //[3]
+ rx_frame_correction_needed : 1, //[4]
+ frameless_frame_received : 1, //[5]
+ reserved_0a : 6, //[11:6]
+ dl_ofdma_info_valid : 1, //[12]
+ dl_ofdma_ru_start_index : 7, //[19:13]
+ dl_ofdma_ru_width : 7, //[26:20]
+ reserved_0b : 5; //[31:27]
+ uint32_t phy_timestamp_1_lower_32 : 32; //[31:0]
+ uint32_t phy_timestamp_1_upper_32 : 32; //[31:0]
+ uint32_t phy_timestamp_2_lower_32 : 32; //[31:0]
+ uint32_t phy_timestamp_2_upper_32 : 32; //[31:0]
+ struct rx_location_info rx_location_info_details;
+ struct rx_timing_offset_info rx_timing_offset_info_details;
+ struct receive_rssi_info post_rssi_info_details;
+ uint32_t phy_sw_status_31_0 : 32; //[31:0]
+ uint32_t phy_sw_status_63_32 : 32; //[31:0]
+};
+
+/*
+
+phy_internal_nap
+
+ When set, PHY RX entered an internal NAP state, as PHY
+ determined that this reception was not destined to this
+ device
+
+location_info_valid
+
+ Indicates that the RX_LOCATION_INFO structure later on
+ in the TLV contains valid info
+
+timing_info_valid
+
+ Indicates that the RX_TIMING_OFFSET_INFO structure later
+ on in the TLV contains valid info
+
+rssi_info_valid
+
+ Indicates that the RECEIVE_RSSI_INFO structure later on
+ in the TLV contains valid info
+
+rx_frame_correction_needed
+
+ When clear, no action is needed in the MAC.
+
+
+
+ When set, the falling edge of the rx_frame happened 4us
+ too late. MAC will need to compensate for this delay in
+ order to maintain proper SIFS timing and/or not to get
+ de-slotted.
+
+
+
+ PHY uses this for very short 11a frames.
+
+
+
+ When set, PHY will have passed this TLV to the MAC up to
+ 8 us into the 'real SIFS' time, and thus within 4us from the
+ falling edge of the rx_frame.
+
+
+
+ <legal all>
+
+frameless_frame_received
+
+ When set, PHY has received the 'frameless frame' . Can
+ be used in the 'MU-RTS -CTS exchange where CTS reception can
+ be problematic.
+
+ <legal all>
+
+reserved_0a
+
+ <legal 0>
+
+dl_ofdma_info_valid
+
+ When set, the following DL_ofdma_... fields are valid.
+
+ It provides the MAC insight into which RU was allocated
+ to this device.
+
+ <legal all>
+
+dl_ofdma_ru_start_index
+
+ RU index number to which User is assigned
+
+ RU numbering is over the entire BW, starting from 0 and
+ in increasing frequency order and not primary-secondary
+ order
+
+ <legal 0-73>
+
+dl_ofdma_ru_width
+
+ The size of the RU for this user.
+
+ In units of 1 (26 tone) RU
+
+ <legal 1-74>
+
+reserved_0b
+
+ <legal 0>
+
+phy_timestamp_1_lower_32
+
+ TODO PHY: cleanup descriptionThe PHY timestamp in the
+ AMPI of the first rising edge of rx_clear_pri after
+ TX_PHY_DESC. . This field should set to 0 by the PHY and
+ should be updated by the AMPI before being forwarded to the
+ rest of the MAC. This field indicates the lower 32 bits of
+ the timestamp
+
+phy_timestamp_1_upper_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the first rising edge
+ of rx_clear_pri after TX_PHY_DESC. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+
+phy_timestamp_2_lower_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ lower 32 bits of the timestamp
+
+phy_timestamp_2_upper_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+
+struct rx_location_info rx_location_info_details
+
+ Overview of location related info
+
+struct rx_timing_offset_info rx_timing_offset_info_details
+
+ Overview of timing offset related info
+
+struct receive_rssi_info post_rssi_info_details
+
+ Overview of the post-RSSI values.
+
+phy_sw_status_31_0
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+
+phy_sw_status_63_32
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+*/
+
+
+/* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP
+
+ When set, PHY RX entered an internal NAP state, as PHY
+ determined that this reception was not destined to this
+ device
+*/
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0
+#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID
+
+ Indicates that the RX_LOCATION_INFO structure later on
+ in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1
+#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002
+
+/* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID
+
+ Indicates that the RX_TIMING_OFFSET_INFO structure later
+ on in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2
+#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004
+
+/* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID
+
+ Indicates that the RECEIVE_RSSI_INFO structure later on
+ in the TLV contains valid info
+*/
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3
+#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008
+
+/* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED
+
+ When clear, no action is needed in the MAC.
+
+
+
+ When set, the falling edge of the rx_frame happened 4us
+ too late. MAC will need to compensate for this delay in
+ order to maintain proper SIFS timing and/or not to get
+ de-slotted.
+
+
+
+ PHY uses this for very short 11a frames.
+
+
+
+ When set, PHY will have passed this TLV to the MAC up to
+ 8 us into the 'real SIFS' time, and thus within 4us from the
+ falling edge of the rx_frame.
+
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4
+#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010
+
+/* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED
+
+ When set, PHY has received the 'frameless frame' . Can
+ be used in the 'MU-RTS -CTS exchange where CTS reception can
+ be problematic.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5
+#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020
+
+/* Description PHYRX_PKT_END_INFO_0_RESERVED_0A
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6
+#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0
+
+/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID
+
+ When set, the following DL_ofdma_... fields are valid.
+
+ It provides the MAC insight into which RU was allocated
+ to this device.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000
+
+/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX
+
+ RU index number to which User is assigned
+
+ RU numbering is over the entire BW, starting from 0 and
+ in increasing frequency order and not primary-secondary
+ order
+
+ <legal 0-73>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000
+
+/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH
+
+ The size of the RU for this user.
+
+ In units of 1 (26 tone) RU
+
+ <legal 1-74>
+*/
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20
+#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000
+
+/* Description PHYRX_PKT_END_INFO_0_RESERVED_0B
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27
+#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000
+
+/* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32
+
+ TODO PHY: cleanup descriptionThe PHY timestamp in the
+ AMPI of the first rising edge of rx_clear_pri after
+ TX_PHY_DESC. . This field should set to 0 by the PHY and
+ should be updated by the AMPI before being forwarded to the
+ rest of the MAC. This field indicates the lower 32 bits of
+ the timestamp
+*/
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0
+#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the first rising edge
+ of rx_clear_pri after TX_PHY_DESC. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0
+#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ lower 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0
+#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32
+
+ TODO PHY: cleanup description
+
+ The PHY timestamp in the AMPI of the rising edge of
+ rx_clear_pri after RX_RSSI_LEGACY. This field should set to
+ 0 by the PHY and should be updated by the AMPI before being
+ forwarded to the rest of the MAC. This field indicates the
+ upper 32 bits of the timestamp
+*/
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0
+#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff
+
+ /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */
+
+
+/* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the first selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+/* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the second selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+/* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the first
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff
+
+/* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the second
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16
+#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS
+
+ Status of rtt_fac_legacy
+
+
+
+ <enum 0 location_fac_legacy_status_not_valid>
+
+ <enum 1 location_fac_legacy_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS
+
+ Status of rtt_fac_legacy_ext80
+
+
+
+ <enum 0 location_fac_legacy_ext80_status_not_valid>
+
+ <enum 1 location_fac_legacy_ext80_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS
+
+ Status of rtt_fac_vht
+
+
+
+ <enum 0 location_fac_vht_status_not_valid>
+
+ <enum 1 location_fac_vht_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS
+
+ Status of rtt_fac_vht_ext80
+
+
+
+ <enum 0 location_fac_vht_ext80_status_not_valid>
+
+ <enum 1 location_fac_vht_ext80_status_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS
+
+ To support fine SIFS adjustment, need to provide FAC
+ value @ integer number of 320 MHz clock cycles to MAC. It
+ is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF
+ if it is a (V)HT/HE packet
+
+
+
+ 12 bits, signed, no fractional part
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS
+
+ Status of rtt_fac_sifs
+
+ 0: not valid
+
+ 1: valid and from L-LTF
+
+ 2: valid and from (V)HT/HE-LTF
+
+ 3: reserved
+
+ <legal 0-2>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS
+
+ Status of channel frequency response dump
+
+
+
+ <enum 0 location_CFR_dump_not_valid>
+
+ <enum 1 location_CFR_dump_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS
+
+ Status of channel impulse response dump
+
+
+
+ <enum 0 location_CIR_dump_not_valid>
+
+ <enum 1 location_CIR_dump_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE
+
+ Channel dump size. It shows how many tones in CFR in
+ one chain, for example, it will show 52 for Legacy20 and 484
+ for VHT160
+
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE
+
+ Indicator showing if HW IFFT mode or SW IFFT mode
+
+
+
+ <enum 0 location_sw_ifft_mode>
+
+ <enum 1 location_hw_ifft_mode>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31
+#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS
+
+ Indicate if BTCF is used to capture the timestamps
+
+
+
+ <enum 0 location_not_BTCF_based_ts>
+
+ <enum 1 location_BTCF_based_ts>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE
+
+ Indicate preamble type
+
+
+
+ <enum 0 location_preamble_type_legacy>
+
+ <enum 1 location_preamble_type_ht>
+
+ <enum 2 location_preamble_type_vht>
+
+ <enum 3 location_preamble_type_he_su_4xltf>
+
+ <enum 4 location_preamble_type_he_su_2xltf>
+
+ <enum 5 location_preamble_type_he_su_1xltf>
+
+ <enum 6
+ location_preamble_type_he_trigger_based_ul_4xltf>
+
+ <enum 7
+ location_preamble_type_he_trigger_based_ul_2xltf>
+
+ <enum 8
+ location_preamble_type_he_trigger_based_ul_1xltf>
+
+ <enum 9 location_preamble_type_he_mu_4xltf>
+
+ <enum 10 location_preamble_type_he_mu_2xltf>
+
+ <enum 11 location_preamble_type_he_mu_1xltf>
+
+ <enum 12
+ location_preamble_type_he_extended_range_su_4xltf>
+
+ <enum 13
+ location_preamble_type_he_extended_range_su_2xltf>
+
+ <enum 14
+ location_preamble_type_he_extended_range_su_1xltf>
+
+ <legal 0-14>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG
+
+ Indicate the bandwidth of L-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT
+
+ Indicate the bandwidth of (V)HT/HE-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE
+
+ Indicate GI (guard interval) type
+
+
+
+ <enum 0 gi_0_8_us > HE related GI. Can also be used
+ for HE
+
+ <enum 1 gi_0_4_us > HE related GI. Can also be used
+ for HE
+
+ <enum 2 gi_1_6_us > HE related GI
+
+ <enum 3 gi_3_2_us > HE related GI
+
+ <legal 0 - 3>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE
+
+ Bits 0~4 indicate MCS rate, if Legacy,
+
+ 0: 48 Mbps,
+
+ 1: 24 Mbps,
+
+ 2: 12 Mbps,
+
+ 3: 6 Mbps,
+
+ 4: 54 Mbps,
+
+ 5: 36 Mbps,
+
+ 6: 18 Mbps,
+
+ 7: 9 Mbps,
+
+
+
+ if HT, 0-7: MCS0-MCS7,
+
+ if VHT, 0-9: MCS0-MCS9,
+
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN
+
+ For 20/40/80, this field shows the first selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected pri80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80
+
+ For 20/40/80, this field shows the second selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected ext80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK
+
+ Rx chain mask, each bit is a Rx chain
+
+ 0: the Rx chain is not used
+
+ 1: the Rx chain is used
+
+ Support up to 8 Rx chains
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31
+#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000
+
+/* Description PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS
+
+ RX packet start timestamp
+
+
+
+ It reports the time the first L-STF ADC sample arrived
+ at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0
+#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS
+
+ RX packet end timestamp
+
+
+
+ It reports the time the last symbol's last ADC sample
+ arrived at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0
+#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START
+
+ The phase of the SFO of the first symbol's first FFT
+ input sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END
+
+ The phase of the SFO of the last symbol's last FFT input
+ sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8
+
+ The high 8 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 8 bits
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32
+
+ The low 32 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 32 bits
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT
+
+ CFO measurement. Needed for passive locationing
+
+
+
+ 14 bits, signed 1.13. 13 bits fraction to provide a
+ resolution of 153 Hz
+
+
+
+ In units of cycles/800 ns
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD
+
+ Channel delay spread measurement. Needed for selecting
+ GI length
+
+
+
+ 8 bits, unsigned. At 25 ns step. Can represent up to
+ 6375 ns
+
+
+
+ In units of cycles @ 40 MHz
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL
+
+ Indicate which timing backoff value is used
+
+
+
+ <enum 0 timing_backoff_low_rssi>
+
+ <enum 1 timing_backoff_mid_rssi>
+
+ <enum 2 timing_backoff_high_rssi>
+
+ <enum 3 reserved>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000
+
+/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID
+
+ <enum 0 rx_location_info_is_not_valid>
+
+ <enum 1 rx_location_info_is_valid>
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31
+#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */
+
+
+/* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET
+
+ Cumulative reference frequency error at end of RX
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+/* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED
+
+ <legal 0>
+*/
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12
+#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000
+
+ /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */
+
+
+/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0
+#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff
+
+/* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32
+
+ Some PHY micro code status that can be put in here.
+ Details of definition within SW specification
+
+ This field can be used for debugging, FW - SW message
+ exchange, etc.
+
+ It could for example be a pointer to a DDR memory
+ location where PHY FW put some debug info.
+
+ <legal all>
+*/
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0
+#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff
+
+
+#endif // _PHYRX_PKT_END_INFO_H_
diff --git a/hw/qca5018/phyrx_rssi_legacy.h b/hw/qca5018/phyrx_rssi_legacy.h
new file mode 100644
index 0000000..820c66f
--- /dev/null
+++ b/hw/qca5018/phyrx_rssi_legacy.h
@@ -0,0 +1,2423 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_RSSI_LEGACY_H_
+#define _PHYRX_RSSI_LEGACY_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_rssi_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 reception_type[3:0], rx_chain_mask_type[4], reserved_0[5], receive_bandwidth[7:6], rx_chain_mask[15:8], phy_ppdu_id[31:16]
+// 1 sw_phy_meta_data[31:0]
+// 2 ppdu_start_timestamp[31:0]
+// 3-18 struct receive_rssi_info pre_rssi_info_details;
+// 19-34 struct receive_rssi_info preamble_rssi_info_details;
+// 35 pre_rssi_comb[7:0], rssi_comb[15:8], normalized_pre_rssi_comb[23:16], normalized_rssi_comb[31:24]
+// 36 rssi_comb_ppdu[7:0], rssi_db_to_dbm_offset[15:8], rssi_for_spatial_reuse[23:16], rssi_for_trigger_resp[31:24]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 37
+
+struct phyrx_rssi_legacy {
+ uint32_t reception_type : 4, //[3:0]
+ rx_chain_mask_type : 1, //[4]
+ reserved_0 : 1, //[5]
+ receive_bandwidth : 2, //[7:6]
+ rx_chain_mask : 8, //[15:8]
+ phy_ppdu_id : 16; //[31:16]
+ uint32_t sw_phy_meta_data : 32; //[31:0]
+ uint32_t ppdu_start_timestamp : 32; //[31:0]
+ struct receive_rssi_info pre_rssi_info_details;
+ struct receive_rssi_info preamble_rssi_info_details;
+ uint32_t pre_rssi_comb : 8, //[7:0]
+ rssi_comb : 8, //[15:8]
+ normalized_pre_rssi_comb : 8, //[23:16]
+ normalized_rssi_comb : 8; //[31:24]
+ uint32_t rssi_comb_ppdu : 8, //[7:0]
+ rssi_db_to_dbm_offset : 8, //[15:8]
+ rssi_for_spatial_reuse : 8, //[23:16]
+ rssi_for_trigger_resp : 8; //[31:24]
+};
+
+/*
+
+reception_type
+
+ This field helps MAC SW determine which field in this
+ (and following TLVs) will contain valid information. For
+ example some RSSI info not valid in case of uplink_ofdma..
+
+
+
+ In case of UL MU OFDMA or UL MU-MIMO reception
+ pre-announced by MAC during trigger Tx, e-nums 0 or 1 should
+ be used.
+
+
+
+ In case of UL MU OFDMA+MIMO reception, or in case of UL
+ MU reception when PHY has not been pre-informed, e-num 2
+ should be used.
+
+ If this happens, the UL MU frame in the medium is by
+ definition not for this device.
+
+ As reference, see doc:
+
+ Lithium_mac_phy_interface_hld.docx
+
+ Chapter: 7.15.1: 11ax UL MU Reception TLV sequences when
+ this device is not targeted.
+
+
+
+ <enum 0 reception_is_uplink_ofdma>
+
+ <enum 1 reception_is_uplink_mimo>
+
+ <enum 2 reception_is_other>
+
+ <enum 3 reception_is_frameless> PHY RX has been
+ instructed in advance that the upcoming reception is
+ frameless. This implieas that in advance it is known that
+ all frames will collide in the medium, and nothing can be
+ properly decoded... This can happen during the CTS reception
+ in response to the triggered MU-RTS transmission.
+
+ MAC takes no action when seeing this e_num. For the
+ frameless reception the indication in pkt_end is the final
+ one evaluated by the MAC
+
+
+
+ For the relationship between pkt_type and this field,
+ see the table at the end of this TLV description.
+
+ <legal 0-3>
+
+rx_chain_mask_type
+
+ Indicates if the field rx_chain_mask represents the mask
+ at start of reception (on which the Rssi_comb value is
+ based), or the setting used during the remainder of the
+ reception
+
+
+
+ 1'b0: rxtd.listen_pri80_mask
+
+ 1'b1: Final receive mask
+
+
+
+ <legal all>
+
+reserved_0
+
+ <legal 0>
+
+receive_bandwidth
+
+ Full receive Bandwidth
+
+
+
+ <enum 0 full_rx_bw_20_mhz>
+
+ <enum 1 full_rx_bw_40_mhz>
+
+ <enum 2 full_rx_bw_80_mhz>
+
+ <enum 3 full_rx_bw_160_mhz>
+
+
+
+ <legal 0-3>
+
+rx_chain_mask
+
+ The chain mask at the start of the reception of this
+ frame.
+
+
+
+ each bit is one antenna
+
+ 0: the chain is NOT used
+
+ 1: the chain is used
+
+
+
+ Supports up to 8 chains
+
+
+
+ Used in 11ax TPC calculations for UL OFDMA/MIMO and has
+ to be in sync with the rssi_comb value as this is also used
+ by the MAC for the TPC calculations.
+
+ <legal all>
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+
+sw_phy_meta_data
+
+ 32 bit Meta data that SW can program in a 32 bit PHY
+ register and PHY will insert the value in every
+ RX_RSSI_LEGACY TLV that it generates.
+
+ SW uses this field to embed among other things some SW
+ channel info.
+
+ppdu_start_timestamp
+
+ Timestamp that indicates when the PPDU that contained
+ this MPDU started on the medium.
+
+
+
+ Note that PHY will detect the start later, and will have
+ to derive out of the preamble info when the frame actually
+ appeared on the medium
+
+ <legal 0- 10>
+
+struct receive_rssi_info pre_rssi_info_details
+
+ This field is not valid when reception_is_uplink_ofdma
+
+
+
+ Overview of the pre-RSSI values. That is RSSI values
+ measured on the medium before this reception started.
+
+struct receive_rssi_info preamble_rssi_info_details
+
+ This field is not valid when reception_is_uplink_ofdma
+
+
+
+ Overview of the RSSI values measured during the
+ pre-amble phase of this reception
+
+pre_rssi_comb
+
+ Combined pre_rssi of all chains. Based on primary
+ channel RSSI.
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ <legal all>
+
+rssi_comb
+
+ Combined rssi of all chains. Based on primary channel
+ RSSI.
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ <legal all>
+
+normalized_pre_rssi_comb
+
+ Combined pre_rssi of all chains, but normalized back to
+ a single chain. This avoids PDG from having to evaluate this
+ in combination with receive chain mask and perform all kinds
+ of pre-processing algorithms.
+
+
+
+ Based on primary channel RSSI.
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ <legal all>
+
+normalized_rssi_comb
+
+ Combined rssi of all chains, but normalized back to a
+ single chain. This avoids PDG from having to evaluate this
+ in combination with receive chain mask and perform all kinds
+ of pre-processing algorithms.
+
+
+
+ Based on primary channel RSSI.
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ <legal all>
+
+rssi_comb_ppdu
+
+ Combined rssi of all chains, based on active
+ RUs/subchannels, a.k.a. rssi_pkt_bw_mac
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ When packet BW is 20 MHz,
+
+ rssi_comb_ppdu = rssi_comb.
+
+
+
+ When packet BW > 20 MHz,
+
+ rssi_comb < rssi_comb_ppdu because rssi_comb only
+ includes power of primary 20 MHz while rssi_comb_ppdu
+ includes power of active RUs/subchannels.
+
+
+
+ <legal all>
+
+rssi_db_to_dbm_offset
+
+ Offset between 'dB' and 'dBm' values. SW can use this
+ value to convert RSSI 'dBm' values back to 'dB,' and report
+ both the values.
+
+
+
+ When rssi_db_to_dbm_offset = 0,
+
+ all rssi_xxx fields are defined in dB.
+
+
+
+ When rssi_db_to_dbm_offset is a large negative value,
+ all rssi_xxx fields are defined in dBm.
+
+
+
+ <legal all>
+
+rssi_for_spatial_reuse
+
+ RSSI to be used by HWSCH for transmit (power) selection
+ during an SR opportunity, reported as an 8-bit signed value
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for
+ OBSS PD spatial reuse, the received signal strength level
+ should be measured from the L-STF or L-LTF (but not L-SIG),
+ just as measured to indicate CCA.
+
+
+
+ Also, as per 802.11ax draft 3.3, for OBSS PD spatial
+ reuse, MAC should compare this value with its programmed
+ OBSS_PDlevel scaled from 20 MHz to the Rx PPDU bandwidth.
+ Since MAC does not do this scaling, PHY is instead expected
+ to normalize the reported RSSI to 20 MHz.
+
+
+
+ Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2,
+ for SRP spatial reuse, the received power level should be
+ measured from the L-STF or L-LTF (but not L-SIG) and
+ normalized to 20 MHz.
+
+ <legal all>
+
+rssi_for_trigger_resp
+
+ RSSI to be used by PDG for transmit (power) selection
+ during trigger response, reported as an 8-bit signed value
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for
+ trigger response, the received power should be measured from
+ the non-HE portion of the preamble of the PPDU containing
+ the trigger, normalized to 20 MHz, averaged over the
+ antennas over which the average pathloss is being computed.
+
+ <legal all>
+*/
+
+
+/* Description PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE
+
+ This field helps MAC SW determine which field in this
+ (and following TLVs) will contain valid information. For
+ example some RSSI info not valid in case of uplink_ofdma..
+
+
+
+ In case of UL MU OFDMA or UL MU-MIMO reception
+ pre-announced by MAC during trigger Tx, e-nums 0 or 1 should
+ be used.
+
+
+
+ In case of UL MU OFDMA+MIMO reception, or in case of UL
+ MU reception when PHY has not been pre-informed, e-num 2
+ should be used.
+
+ If this happens, the UL MU frame in the medium is by
+ definition not for this device.
+
+ As reference, see doc:
+
+ Lithium_mac_phy_interface_hld.docx
+
+ Chapter: 7.15.1: 11ax UL MU Reception TLV sequences when
+ this device is not targeted.
+
+
+
+ <enum 0 reception_is_uplink_ofdma>
+
+ <enum 1 reception_is_uplink_mimo>
+
+ <enum 2 reception_is_other>
+
+ <enum 3 reception_is_frameless> PHY RX has been
+ instructed in advance that the upcoming reception is
+ frameless. This implieas that in advance it is known that
+ all frames will collide in the medium, and nothing can be
+ properly decoded... This can happen during the CTS reception
+ in response to the triggered MU-RTS transmission.
+
+ MAC takes no action when seeing this e_num. For the
+ frameless reception the indication in pkt_end is the final
+ one evaluated by the MAC
+
+
+
+ For the relationship between pkt_type and this field,
+ see the table at the end of this TLV description.
+
+ <legal 0-3>
+*/
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_LSB 0
+#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_MASK 0x0000000f
+
+/* Description PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE
+
+ Indicates if the field rx_chain_mask represents the mask
+ at start of reception (on which the Rssi_comb value is
+ based), or the setting used during the remainder of the
+ reception
+
+
+
+ 1'b0: rxtd.listen_pri80_mask
+
+ 1'b1: Final receive mask
+
+
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_LSB 4
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_MASK 0x00000010
+
+/* Description PHYRX_RSSI_LEGACY_0_RESERVED_0
+
+ <legal 0>
+*/
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_LSB 5
+#define PHYRX_RSSI_LEGACY_0_RESERVED_0_MASK 0x00000020
+
+/* Description PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH
+
+ Full receive Bandwidth
+
+
+
+ <enum 0 full_rx_bw_20_mhz>
+
+ <enum 1 full_rx_bw_40_mhz>
+
+ <enum 2 full_rx_bw_80_mhz>
+
+ <enum 3 full_rx_bw_160_mhz>
+
+
+
+ <legal 0-3>
+*/
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_LSB 6
+#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+/* Description PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK
+
+ The chain mask at the start of the reception of this
+ frame.
+
+
+
+ each bit is one antenna
+
+ 0: the chain is NOT used
+
+ 1: the chain is used
+
+
+
+ Supports up to 8 chains
+
+
+
+ Used in 11ax TPC calculations for UL OFDMA/MIMO and has
+ to be in sync with the rssi_comb value as this is also used
+ by the MAC for the TPC calculations.
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_LSB 8
+#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_LSB 16
+#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA
+
+ 32 bit Meta data that SW can program in a 32 bit PHY
+ register and PHY will insert the value in every
+ RX_RSSI_LEGACY TLV that it generates.
+
+ SW uses this field to embed among other things some SW
+ channel info.
+*/
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_OFFSET 0x00000004
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_LSB 0
+#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_MASK 0xffffffff
+
+/* Description PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP
+
+ Timestamp that indicates when the PPDU that contained
+ this MPDU started on the medium.
+
+
+
+ Note that PHY will detect the start later, and will have
+ to derive out of the preamble info when the frame actually
+ appeared on the medium
+
+ <legal 0- 10>
+*/
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_LSB 0
+#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_MASK 0xffffffff
+
+ /* EXTERNAL REFERENCE : struct receive_rssi_info pre_rssi_info_details */
+
+
+/* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000c
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000010
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000014
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000018
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000001c
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000020
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000024
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000028
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000002c
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000030
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000034
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000038
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000003c
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000040
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000044
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000048
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+ /* EXTERNAL REFERENCE : struct receive_rssi_info preamble_rssi_info_details */
+
+
+/* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000004c
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000050
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000054
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000058
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000005c
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000060
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000064
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000068
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000006c
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000070
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000074
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000078
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000007c
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000080
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000084
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000088
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB
+
+ Combined pre_rssi of all chains. Based on primary
+ channel RSSI.
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_LSB 0
+#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_35_RSSI_COMB
+
+ Combined rssi of all chains. Based on primary channel
+ RSSI.
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_LSB 8
+#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB
+
+ Combined pre_rssi of all chains, but normalized back to
+ a single chain. This avoids PDG from having to evaluate this
+ in combination with receive chain mask and perform all kinds
+ of pre-processing algorithms.
+
+
+
+ Based on primary channel RSSI.
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_LSB 16
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB
+
+ Combined rssi of all chains, but normalized back to a
+ single chain. This avoids PDG from having to evaluate this
+ in combination with receive chain mask and perform all kinds
+ of pre-processing algorithms.
+
+
+
+ Based on primary channel RSSI.
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_OFFSET 0x0000008c
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_LSB 24
+#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_MASK 0xff000000
+
+/* Description PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU
+
+ Combined rssi of all chains, based on active
+ RUs/subchannels, a.k.a. rssi_pkt_bw_mac
+
+
+
+ RSSI is reported as 8b signed values. Nominally value is
+ in dB units above or below the noisefloor(minCCApwr).
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ When packet BW is 20 MHz,
+
+ rssi_comb_ppdu = rssi_comb.
+
+
+
+ When packet BW > 20 MHz,
+
+ rssi_comb < rssi_comb_ppdu because rssi_comb only
+ includes power of primary 20 MHz while rssi_comb_ppdu
+ includes power of active RUs/subchannels.
+
+
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_LSB 0
+#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_MASK 0x000000ff
+
+/* Description PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET
+
+ Offset between 'dB' and 'dBm' values. SW can use this
+ value to convert RSSI 'dBm' values back to 'dB,' and report
+ both the values.
+
+
+
+ When rssi_db_to_dbm_offset = 0,
+
+ all rssi_xxx fields are defined in dB.
+
+
+
+ When rssi_db_to_dbm_offset is a large negative value,
+ all rssi_xxx fields are defined in dBm.
+
+
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB 8
+#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00
+
+/* Description PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE
+
+ RSSI to be used by HWSCH for transmit (power) selection
+ during an SR opportunity, reported as an 8-bit signed value
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for
+ OBSS PD spatial reuse, the received signal strength level
+ should be measured from the L-STF or L-LTF (but not L-SIG),
+ just as measured to indicate CCA.
+
+
+
+ Also, as per 802.11ax draft 3.3, for OBSS PD spatial
+ reuse, MAC should compare this value with its programmed
+ OBSS_PDlevel scaled from 20 MHz to the Rx PPDU bandwidth.
+ Since MAC does not do this scaling, PHY is instead expected
+ to normalize the reported RSSI to 20 MHz.
+
+
+
+ Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2,
+ for SRP spatial reuse, the received power level should be
+ measured from the L-STF or L-LTF (but not L-SIG) and
+ normalized to 20 MHz.
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB 16
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000
+
+/* Description PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP
+
+ RSSI to be used by PDG for transmit (power) selection
+ during trigger response, reported as an 8-bit signed value
+
+
+
+ The resolution can be:
+
+ 1dB or 0.5dB. This is statically configured within the
+ PHY and MAC
+
+
+
+ In case of 1dB, the Range is:
+
+ -128dB to 127dB
+
+
+
+ In case of 0.5dB, the Range is:
+
+ -64dB to 63.5dB
+
+
+
+ As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for
+ trigger response, the received power should be measured from
+ the non-HE portion of the preamble of the PPDU containing
+ the trigger, normalized to 20 MHz, averaged over the
+ antennas over which the average pathloss is being computed.
+
+ <legal all>
+*/
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000090
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB 24
+#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000
+
+
+#endif // _PHYRX_RSSI_LEGACY_H_
diff --git a/hw/qca5018/phyrx_vht_sig_a.h b/hw/qca5018/phyrx_vht_sig_a.h
new file mode 100644
index 0000000..9b5cc5a
--- /dev/null
+++ b/hw/qca5018/phyrx_vht_sig_a.h
@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _PHYRX_VHT_SIG_A_H_
+#define _PHYRX_VHT_SIG_A_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "vht_sig_a_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct vht_sig_a_info phyrx_vht_sig_a_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2
+
+struct phyrx_vht_sig_a {
+ struct vht_sig_a_info phyrx_vht_sig_a_info_details;
+};
+
+/*
+
+struct vht_sig_a_info phyrx_vht_sig_a_info_details
+
+ See detailed description of the STRUCT
+*/
+
+
+ /* EXTERNAL REFERENCE : struct vht_sig_a_info phyrx_vht_sig_a_info_details */
+
+
+/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH
+
+ Packet bandwidth
+
+
+
+ <enum 0 20_MHZ_11AC>
+
+ <enum 1 40_MHZ_11AC>
+
+ <enum 2 80_MHZ_11AC>
+
+ <enum 3 160_MHZ_11AC>
+
+
+
+ <legal 0-3>
+*/
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003
+
+/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0
+
+ Reserved. Set to 1 by MAC, PHY should ignore
+
+ <legal 1>
+*/
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004
+
+/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC
+
+ Space time block coding:
+
+ <enum 0 stbc_disabled> Indicates STBC is disabled
+
+ <enum 1 stbc_enabled> Indicates STBC is enabled on
+ all streams
+
+ <legal 0-1>
+*/
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008
+
+/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID
+
+ In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed
+ to an AP or to a mesh STA, the Group ID field is set to 0,
+ otherwise it is set to 63. In an NDP PPDU the Group ID is
+ set according to IEEE 802.11ac_D1.0 Section 9.30.6
+ (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID
+ is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID).
+ <legal all>
+*/
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0
+
+/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS
+
+ For MU:
+
+ 3 bits/user with maximum of 4 users (user u uses
+
+ vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2,
+ 3)
+
+ Set to 0 for 0 space time streams
+
+ Set to 1 for 1 space time stream
+
+ Set to 2 for 2 space time streams
+
+ Set to 3 for 3 space time streams
+
+ Set to 4 for 4 space time streams (not supported in Wifi
+ 3.0)
+
+ Values 5-7 are reserved
+
+ In this field, references to user u should be
+ interpreted as MU user u. As described in the previous
+ chapter in this document (see chapter on User number), the
+ MU user value for a given client is defined for each MU
+ group that the client participates in. The MU user number is
+ not related to the internal user number that is used within
+ the BFer.
+
+
+
+
+
+ For SU:
+
+ vht_sig_a[0][12:10]
+
+ Set to 0 for 1 space time stream
+
+ Set to 1 for 2 space time streams
+
+ Set to 2 for 3 space time streams
+
+ Set to 3 for 4 space time streams
+
+ Set to 4 for 5 space time streams
+
+ Set to 5 for 6 space time streams
+
+ Set to 6 for 7 space time streams
+
+ Set to 7 for 8 space time streams
+
+
+
+ vht_sig_a[0][21:13]
+
+ Partial AID:
+
+ Set to the value of the TXVECTOR parameter PARTIAL_AID.
+ Partial AID provides an abbreviated indication of the
+ intended recipient(s) of the frame (see IEEE802.11ac_D1.0
+ Section 9.17a (Partial AID in VHT PPDUs)).
+
+ <legal all>
+*/
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00
+
+/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED
+
+ E_num 0 txop_ps_allowed Not supported: If set to by
+ VHT AP if it allows non-AP VHT STAs in TXOP power save mode
+ to enter Doze state during a TXOP
+
+ <enum 1 no_txop_ps_allowed> Otherwise
+
+ <legal 1>
+*/
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
+
+/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B
+
+ Reserved: Should be set to 1 by the MAC and ignored by
+ the PHY <legal 1>
+*/
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000
+
+/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+*/
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
+#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING
+
+ <enum 0 normal_gi> Indicates short guard interval
+ is not used in the data field
+
+ <enum 1 short_gi> Indicates short guard interval is
+ used in the data field
+
+ <enum 3 short_gi_ambiguity> Indicates short guard
+ interval is used in the data field and NSYM mod 10 = 9
+
+ NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3
+ (TXTIME and PSDU_LENGTH calculation).
+
+ <legal 0,1,3>
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING
+
+ For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For
+ an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then
+ B2 indicates the coding used for user 0; set to 0 for BCC
+ and 1 for LDPC. If the MU[0] NSTS field is 0, then this
+ field is reserved and set to 1
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL
+
+ Set to 1 if the LDPC PPDU encoding process (if an SU
+ PPDU), or at least one LDPC user's PPDU encoding process (if
+ an MU PPDU), results in an extra OFDM symbol (or symbols) as
+ described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
+ (Encoding process for MU PPDUs). Set to 0 otherwise.
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS
+
+ For SU:
+
+ Set to 0 for BPSK 1/2
+
+ Set to 1 for QPSK 1/2
+
+ Set to 2 for QPSK 3/4
+
+ Set to 3 for 16-QAM 1/2
+
+ Set to 4 for 16-QAM 3/4
+
+ Set to 5 for 64-QAM 2/3
+
+ Set to 6 for 64-QAM 3/4
+
+ Set to 7 for 64-QAM 5/6
+
+ Set to 8 for 256-QAM 3/4
+
+ Set to 9 for 256-QAM 5/6
+
+ For MU:
+
+ If NSTS for user 1 is non-zero, then vht_sig_a[1][4]
+ indicates coding for user 1: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is
+ reserved and set to 1.
+
+ If NSTS for user 2 is non-zero, then vht_sig_a[1][5]
+ indicates coding for user 2: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is
+ reserved and set to 1.
+
+ If NSTS for user 3 is non-zero, then vht_sig_a[1][6]
+ indicates coding for user 3: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is
+ reserved and set to 1.
+
+ vht_sig_a[1][7] is reserved and set to 1
+
+ <legal 0-15>
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED
+
+ For SU:
+
+ Set to 1 if a Beamforming steering matrix is applied to
+ the waveform in an SU transmission as described in
+ IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping),
+ set to 0 otherwise.
+
+ For MU:
+
+ Reserved and set to 1
+
+ <legal 0-1>
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1
+
+ Reserved and set to 1. <legal 1>
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC
+
+ CRC calculated as in IEEE802.11ac_D1.0 Section
+ 19.3.9.4.4 (CRC calculation for HTSIG) with C7 in
+ vht_sig_a[1][10], etc. <legal all>
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL
+
+ Used to terminate the trellis of the convolutional
+ decoder. Set to 0. <legal 0>
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000
+
+/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+*/
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24
+#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0xff000000
+
+
+#endif // _PHYRX_VHT_SIG_A_H_
diff --git a/hw/qca5018/receive_rssi_info.h b/hw/qca5018/receive_rssi_info.h
new file mode 100644
index 0000000..df3de45
--- /dev/null
+++ b/hw/qca5018/receive_rssi_info.h
@@ -0,0 +1,1255 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RECEIVE_RSSI_INFO_H_
+#define _RECEIVE_RSSI_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 rssi_pri20_chain0[7:0], rssi_ext20_chain0[15:8], rssi_ext40_low20_chain0[23:16], rssi_ext40_high20_chain0[31:24]
+// 1 rssi_ext80_low20_chain0[7:0], rssi_ext80_low_high20_chain0[15:8], rssi_ext80_high_low20_chain0[23:16], rssi_ext80_high20_chain0[31:24]
+// 2 rssi_pri20_chain1[7:0], rssi_ext20_chain1[15:8], rssi_ext40_low20_chain1[23:16], rssi_ext40_high20_chain1[31:24]
+// 3 rssi_ext80_low20_chain1[7:0], rssi_ext80_low_high20_chain1[15:8], rssi_ext80_high_low20_chain1[23:16], rssi_ext80_high20_chain1[31:24]
+// 4 rssi_pri20_chain2[7:0], rssi_ext20_chain2[15:8], rssi_ext40_low20_chain2[23:16], rssi_ext40_high20_chain2[31:24]
+// 5 rssi_ext80_low20_chain2[7:0], rssi_ext80_low_high20_chain2[15:8], rssi_ext80_high_low20_chain2[23:16], rssi_ext80_high20_chain2[31:24]
+// 6 rssi_pri20_chain3[7:0], rssi_ext20_chain3[15:8], rssi_ext40_low20_chain3[23:16], rssi_ext40_high20_chain3[31:24]
+// 7 rssi_ext80_low20_chain3[7:0], rssi_ext80_low_high20_chain3[15:8], rssi_ext80_high_low20_chain3[23:16], rssi_ext80_high20_chain3[31:24]
+// 8 rssi_pri20_chain4[7:0], rssi_ext20_chain4[15:8], rssi_ext40_low20_chain4[23:16], rssi_ext40_high20_chain4[31:24]
+// 9 rssi_ext80_low20_chain4[7:0], rssi_ext80_low_high20_chain4[15:8], rssi_ext80_high_low20_chain4[23:16], rssi_ext80_high20_chain4[31:24]
+// 10 rssi_pri20_chain5[7:0], rssi_ext20_chain5[15:8], rssi_ext40_low20_chain5[23:16], rssi_ext40_high20_chain5[31:24]
+// 11 rssi_ext80_low20_chain5[7:0], rssi_ext80_low_high20_chain5[15:8], rssi_ext80_high_low20_chain5[23:16], rssi_ext80_high20_chain5[31:24]
+// 12 rssi_pri20_chain6[7:0], rssi_ext20_chain6[15:8], rssi_ext40_low20_chain6[23:16], rssi_ext40_high20_chain6[31:24]
+// 13 rssi_ext80_low20_chain6[7:0], rssi_ext80_low_high20_chain6[15:8], rssi_ext80_high_low20_chain6[23:16], rssi_ext80_high20_chain6[31:24]
+// 14 rssi_pri20_chain7[7:0], rssi_ext20_chain7[15:8], rssi_ext40_low20_chain7[23:16], rssi_ext40_high20_chain7[31:24]
+// 15 rssi_ext80_low20_chain7[7:0], rssi_ext80_low_high20_chain7[15:8], rssi_ext80_high_low20_chain7[23:16], rssi_ext80_high20_chain7[31:24]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16
+
+struct receive_rssi_info {
+ uint32_t rssi_pri20_chain0 : 8, //[7:0]
+ rssi_ext20_chain0 : 8, //[15:8]
+ rssi_ext40_low20_chain0 : 8, //[23:16]
+ rssi_ext40_high20_chain0 : 8; //[31:24]
+ uint32_t rssi_ext80_low20_chain0 : 8, //[7:0]
+ rssi_ext80_low_high20_chain0 : 8, //[15:8]
+ rssi_ext80_high_low20_chain0 : 8, //[23:16]
+ rssi_ext80_high20_chain0 : 8; //[31:24]
+ uint32_t rssi_pri20_chain1 : 8, //[7:0]
+ rssi_ext20_chain1 : 8, //[15:8]
+ rssi_ext40_low20_chain1 : 8, //[23:16]
+ rssi_ext40_high20_chain1 : 8; //[31:24]
+ uint32_t rssi_ext80_low20_chain1 : 8, //[7:0]
+ rssi_ext80_low_high20_chain1 : 8, //[15:8]
+ rssi_ext80_high_low20_chain1 : 8, //[23:16]
+ rssi_ext80_high20_chain1 : 8; //[31:24]
+ uint32_t rssi_pri20_chain2 : 8, //[7:0]
+ rssi_ext20_chain2 : 8, //[15:8]
+ rssi_ext40_low20_chain2 : 8, //[23:16]
+ rssi_ext40_high20_chain2 : 8; //[31:24]
+ uint32_t rssi_ext80_low20_chain2 : 8, //[7:0]
+ rssi_ext80_low_high20_chain2 : 8, //[15:8]
+ rssi_ext80_high_low20_chain2 : 8, //[23:16]
+ rssi_ext80_high20_chain2 : 8; //[31:24]
+ uint32_t rssi_pri20_chain3 : 8, //[7:0]
+ rssi_ext20_chain3 : 8, //[15:8]
+ rssi_ext40_low20_chain3 : 8, //[23:16]
+ rssi_ext40_high20_chain3 : 8; //[31:24]
+ uint32_t rssi_ext80_low20_chain3 : 8, //[7:0]
+ rssi_ext80_low_high20_chain3 : 8, //[15:8]
+ rssi_ext80_high_low20_chain3 : 8, //[23:16]
+ rssi_ext80_high20_chain3 : 8; //[31:24]
+ uint32_t rssi_pri20_chain4 : 8, //[7:0]
+ rssi_ext20_chain4 : 8, //[15:8]
+ rssi_ext40_low20_chain4 : 8, //[23:16]
+ rssi_ext40_high20_chain4 : 8; //[31:24]
+ uint32_t rssi_ext80_low20_chain4 : 8, //[7:0]
+ rssi_ext80_low_high20_chain4 : 8, //[15:8]
+ rssi_ext80_high_low20_chain4 : 8, //[23:16]
+ rssi_ext80_high20_chain4 : 8; //[31:24]
+ uint32_t rssi_pri20_chain5 : 8, //[7:0]
+ rssi_ext20_chain5 : 8, //[15:8]
+ rssi_ext40_low20_chain5 : 8, //[23:16]
+ rssi_ext40_high20_chain5 : 8; //[31:24]
+ uint32_t rssi_ext80_low20_chain5 : 8, //[7:0]
+ rssi_ext80_low_high20_chain5 : 8, //[15:8]
+ rssi_ext80_high_low20_chain5 : 8, //[23:16]
+ rssi_ext80_high20_chain5 : 8; //[31:24]
+ uint32_t rssi_pri20_chain6 : 8, //[7:0]
+ rssi_ext20_chain6 : 8, //[15:8]
+ rssi_ext40_low20_chain6 : 8, //[23:16]
+ rssi_ext40_high20_chain6 : 8; //[31:24]
+ uint32_t rssi_ext80_low20_chain6 : 8, //[7:0]
+ rssi_ext80_low_high20_chain6 : 8, //[15:8]
+ rssi_ext80_high_low20_chain6 : 8, //[23:16]
+ rssi_ext80_high20_chain6 : 8; //[31:24]
+ uint32_t rssi_pri20_chain7 : 8, //[7:0]
+ rssi_ext20_chain7 : 8, //[15:8]
+ rssi_ext40_low20_chain7 : 8, //[23:16]
+ rssi_ext40_high20_chain7 : 8; //[31:24]
+ uint32_t rssi_ext80_low20_chain7 : 8, //[7:0]
+ rssi_ext80_low_high20_chain7 : 8, //[15:8]
+ rssi_ext80_high_low20_chain7 : 8, //[23:16]
+ rssi_ext80_high20_chain7 : 8; //[31:24]
+};
+
+/*
+
+rssi_pri20_chain0
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext20_chain0
+
+ RSSI of RX PPDU on chain 0 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_low20_chain0
+
+ RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_high20_chain0
+
+ RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low20_chain0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low_high20_chain0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high_low20_chain0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high20_chain0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_pri20_chain1
+
+ RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext20_chain1
+
+ RSSI of RX PPDU on chain 1 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_low20_chain1
+
+ RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_high20_chain1
+
+ RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low20_chain1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low_high20_chain1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high_low20_chain1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high20_chain1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_pri20_chain2
+
+ RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext20_chain2
+
+ RSSI of RX PPDU on chain 2 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_low20_chain2
+
+ RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_high20_chain2
+
+ RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low20_chain2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low_high20_chain2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high_low20_chain2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high20_chain2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_pri20_chain3
+
+ RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext20_chain3
+
+ RSSI of RX PPDU on chain 3 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_low20_chain3
+
+ RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_high20_chain3
+
+ RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low20_chain3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low_high20_chain3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high_low20_chain3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high20_chain3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_pri20_chain4
+
+ RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext20_chain4
+
+ RSSI of RX PPDU on chain 4 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_low20_chain4
+
+ RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_high20_chain4
+
+ RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low20_chain4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low_high20_chain4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high_low20_chain4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high20_chain4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_pri20_chain5
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext20_chain5
+
+ RSSI of RX PPDU on chain 5 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_low20_chain5
+
+ RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_high20_chain5
+
+ RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low20_chain5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low_high20_chain5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high_low20_chain5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high20_chain5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_pri20_chain6
+
+ RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext20_chain6
+
+ RSSI of RX PPDU on chain 6 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_low20_chain6
+
+ RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_high20_chain6
+
+ RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low20_chain6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low_high20_chain6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high_low20_chain6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high20_chain6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_pri20_chain7
+
+ RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext20_chain7
+
+ RSSI of RX PPDU on chain 7 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_low20_chain7
+
+ RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext40_high20_chain7
+
+ RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low20_chain7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_low_high20_chain7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high_low20_chain7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+
+rssi_ext80_high20_chain7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+
+
+/* Description RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_LSB 0
+#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_LSB 8
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_LSB 16
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_LSB 24
+#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_LSB 0
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0
+
+ RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_LSB 24
+#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_LSB 0
+#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_LSB 8
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_LSB 16
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000008
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_LSB 24
+#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_LSB 0
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1
+
+ RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000c
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_LSB 24
+#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_LSB 0
+#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_LSB 8
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_LSB 16
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000010
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_LSB 24
+#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_LSB 0
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2
+
+ RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000014
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_LSB 24
+#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_LSB 0
+#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_LSB 8
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_LSB 16
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000018
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_LSB 24
+#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_LSB 0
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3
+
+ RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000001c
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_LSB 24
+#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_LSB 0
+#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_LSB 8
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_LSB 16
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x00000020
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_LSB 24
+#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_LSB 0
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4
+
+ RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000024
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_LSB 24
+#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5
+
+ RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_LSB 0
+#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_LSB 8
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_LSB 16
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000028
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_LSB 24
+#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_LSB 0
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5
+
+ RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x0000002c
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_LSB 24
+#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_LSB 0
+#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_LSB 8
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_LSB 16
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x00000030
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_LSB 24
+#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_LSB 0
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6
+
+ RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000034
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_LSB 24
+#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_LSB 0
+#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_LSB 8
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_LSB 16
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000038
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_LSB 24
+#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000
+
+/* Description RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_LSB 0
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff
+
+/* Description RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, low-high 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00
+
+/* Description RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high-low 20
+ MHz bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000
+
+/* Description RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7
+
+ RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz
+ bandwidth.
+
+ Value of 0x80 indicates invalid.
+*/
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x0000003c
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_LSB 24
+#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000
+
+
+#endif // _RECEIVE_RSSI_INFO_H_
diff --git a/hw/qca5018/receive_user_info.h b/hw/qca5018/receive_user_info.h
new file mode 100644
index 0000000..b6e1dbd
--- /dev/null
+++ b/hw/qca5018/receive_user_info.h
@@ -0,0 +1,549 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RECEIVE_USER_INFO_H_
+#define _RECEIVE_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 phy_ppdu_id[15:0], user_rssi[23:16], pkt_type[27:24], stbc[28], reception_type[31:29]
+// 1 rate_mcs[3:0], sgi[5:4], receive_bandwidth[7:6], mimo_ss_bitmap[15:8], ofdma_ru_allocation[23:16], ofdma_user_index[30:24], ofdma_content_channel[31]
+// 2 ldpc[0], ru_width[7:1], reserved_2a[31:8]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RECEIVE_USER_INFO 3
+
+struct receive_user_info {
+ uint32_t phy_ppdu_id : 16, //[15:0]
+ user_rssi : 8, //[23:16]
+ pkt_type : 4, //[27:24]
+ stbc : 1, //[28]
+ reception_type : 3; //[31:29]
+ uint32_t rate_mcs : 4, //[3:0]
+ sgi : 2, //[5:4]
+ receive_bandwidth : 2, //[7:6]
+ mimo_ss_bitmap : 8, //[15:8]
+ ofdma_ru_allocation : 8, //[23:16]
+ ofdma_user_index : 7, //[30:24]
+ ofdma_content_channel : 1; //[31]
+ uint32_t ldpc : 1, //[0]
+ ru_width : 7, //[7:1]
+ reserved_2a : 24; //[31:8]
+};
+
+/*
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+
+user_rssi
+
+ RSSI for this user
+
+ Frequency domain RSSI measurement for this user. Based
+ on the channel estimate.
+
+
+
+ <legal all>
+
+pkt_type
+
+ Packet type:
+
+
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+
+stbc
+
+ When set, use STBC transmission rates
+
+reception_type
+
+ Indicates what type of reception this is.
+
+ <enum 0 reception_type_SU > Basic SU reception (not
+ part of OFDMA or MU-MIMO)
+
+ <enum 1 reception_type_MU_MIMO > This is related to
+ DL type of reception
+
+ <enum 2 reception_type_MU_OFDMA > This is related
+ to DL type of reception
+
+ <enum 3 reception_type_MU_OFDMA_MIMO > This is
+ related to DL type of reception
+
+ <enum 4 reception_type_UL_MU_MIMO > This is related
+ to UL type of reception
+
+ <enum 5 reception_type_UL_MU_OFDMA > This is
+ related to UL type of reception
+
+ <enum 6 reception_type_UL_MU_OFDMA_MIMO > This is
+ related to UL type of reception
+
+
+
+ <legal 0-6>
+
+rate_mcs
+
+ For details, refer to MCS_TYPE description
+
+ <legal all>
+
+sgi
+
+ Field only valid when pkt type is HT, VHT or HE.
+
+
+
+ <enum 0 gi_0_8_us > Legacy normal GI. Can also be
+ used for HE
+
+ <enum 1 gi_0_4_us > Legacy short GI. Can also be
+ used for HE
+
+ <enum 2 gi_1_6_us > HE related GI
+
+ <enum 3 gi_3_2_us > HE related GI
+
+ <legal 0 - 3>
+
+receive_bandwidth
+
+ Full receive Bandwidth
+
+
+
+ <enum 0 full_rx_bw_20_mhz>
+
+ <enum 1 full_rx_bw_40_mhz>
+
+ <enum 2 full_rx_bw_80_mhz>
+
+ <enum 3 full_rx_bw_160_mhz>
+
+
+
+ <legal 0-3>
+
+mimo_ss_bitmap
+
+ Bitmap, with each bit indicating if the related spatial
+ stream is used for this STA
+
+ LSB related to SS 0
+
+
+
+ 0: spatial stream not used for this reception
+
+ 1: spatial stream used for this reception
+
+
+
+ <legal all>
+
+ofdma_ru_allocation
+
+ Field only valid in case of OFDMA type receptions (DL
+ and UL)
+
+
+
+ Indicates the RU number associated with this user.
+
+
+
+ In case of reception where the transmission was DL MU
+ OFDMA, this field provides the RU pattern. Note that fields
+ ofdma_user_index and ofdma_content_channel are needed to
+ determine which RU (within a 40 MHz channel) was actually
+ assigned to this user, but this does not give info on which
+ 40 MHz channel was assigned to this user. Please refer
+ DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for
+ this user.
+
+
+
+ In case of reception where the transmission was UL MU
+ OFDMA, PHY is recommended to insert the RU start index in
+ this field. Note that PHY may insert the RU width in
+ Reserved_2a[6:0].
+
+ <legal all>
+
+ofdma_user_index
+
+ Field only valid in the of DL MU OFDMA reception
+
+
+
+ The user number within the RU_allocation.
+
+
+
+ This is needed for SW to determine the exact RU position
+ within the reception.
+
+ <legal all>
+
+ofdma_content_channel
+
+ Field only valid in the of DL MU OFDMA/MIMO reception
+
+
+
+ In case of DL MU reception, this field indicates the
+ content channel number where PHY found the RU information
+ for this user
+
+
+
+ This is needed for SW to determine the exact RU position
+ within the reception.
+
+
+
+ <enum 0 content_channel_1>
+
+ <enum 1 content_channel_2>
+
+
+
+ <legal all>
+
+ldpc
+
+ When set, use LDPC transmission rates were used.
+
+ <legal all>
+
+ru_width
+
+ In case of UL OFDMA reception, PHY is recommended to
+ insert the RU width
+
+ In Hastings80: was using Reserved_2a[6:0].
+
+ <legal 1 - 74>
+
+reserved_2a
+
+ <legal 0>
+*/
+
+
+/* Description RECEIVE_USER_INFO_0_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB 0
+#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK 0x0000ffff
+
+/* Description RECEIVE_USER_INFO_0_USER_RSSI
+
+ RSSI for this user
+
+ Frequency domain RSSI measurement for this user. Based
+ on the channel estimate.
+
+
+
+ <legal all>
+*/
+#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_USER_RSSI_LSB 16
+#define RECEIVE_USER_INFO_0_USER_RSSI_MASK 0x00ff0000
+
+/* Description RECEIVE_USER_INFO_0_PKT_TYPE
+
+ Packet type:
+
+
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+*/
+#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB 24
+#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK 0x0f000000
+
+/* Description RECEIVE_USER_INFO_0_STBC
+
+ When set, use STBC transmission rates
+*/
+#define RECEIVE_USER_INFO_0_STBC_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_STBC_LSB 28
+#define RECEIVE_USER_INFO_0_STBC_MASK 0x10000000
+
+/* Description RECEIVE_USER_INFO_0_RECEPTION_TYPE
+
+ Indicates what type of reception this is.
+
+ <enum 0 reception_type_SU > Basic SU reception (not
+ part of OFDMA or MU-MIMO)
+
+ <enum 1 reception_type_MU_MIMO > This is related to
+ DL type of reception
+
+ <enum 2 reception_type_MU_OFDMA > This is related
+ to DL type of reception
+
+ <enum 3 reception_type_MU_OFDMA_MIMO > This is
+ related to DL type of reception
+
+ <enum 4 reception_type_UL_MU_MIMO > This is related
+ to UL type of reception
+
+ <enum 5 reception_type_UL_MU_OFDMA > This is
+ related to UL type of reception
+
+ <enum 6 reception_type_UL_MU_OFDMA_MIMO > This is
+ related to UL type of reception
+
+
+
+ <legal 0-6>
+*/
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_OFFSET 0x00000000
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_LSB 29
+#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_MASK 0xe0000000
+
+/* Description RECEIVE_USER_INFO_1_RATE_MCS
+
+ For details, refer to MCS_TYPE description
+
+ <legal all>
+*/
+#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_RATE_MCS_LSB 0
+#define RECEIVE_USER_INFO_1_RATE_MCS_MASK 0x0000000f
+
+/* Description RECEIVE_USER_INFO_1_SGI
+
+ Field only valid when pkt type is HT, VHT or HE.
+
+
+
+ <enum 0 gi_0_8_us > Legacy normal GI. Can also be
+ used for HE
+
+ <enum 1 gi_0_4_us > Legacy short GI. Can also be
+ used for HE
+
+ <enum 2 gi_1_6_us > HE related GI
+
+ <enum 3 gi_3_2_us > HE related GI
+
+ <legal 0 - 3>
+*/
+#define RECEIVE_USER_INFO_1_SGI_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_SGI_LSB 4
+#define RECEIVE_USER_INFO_1_SGI_MASK 0x00000030
+
+/* Description RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH
+
+ Full receive Bandwidth
+
+
+
+ <enum 0 full_rx_bw_20_mhz>
+
+ <enum 1 full_rx_bw_40_mhz>
+
+ <enum 2 full_rx_bw_80_mhz>
+
+ <enum 3 full_rx_bw_160_mhz>
+
+
+
+ <legal 0-3>
+*/
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB 6
+#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+/* Description RECEIVE_USER_INFO_1_MIMO_SS_BITMAP
+
+ Bitmap, with each bit indicating if the related spatial
+ stream is used for this STA
+
+ LSB related to SS 0
+
+
+
+ 0: spatial stream not used for this reception
+
+ 1: spatial stream used for this reception
+
+
+
+ <legal all>
+*/
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB 8
+#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+/* Description RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION
+
+ Field only valid in case of OFDMA type receptions (DL
+ and UL)
+
+
+
+ Indicates the RU number associated with this user.
+
+
+
+ In case of reception where the transmission was DL MU
+ OFDMA, this field provides the RU pattern. Note that fields
+ ofdma_user_index and ofdma_content_channel are needed to
+ determine which RU (within a 40 MHz channel) was actually
+ assigned to this user, but this does not give info on which
+ 40 MHz channel was assigned to this user. Please refer
+ DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for
+ this user.
+
+
+
+ In case of reception where the transmission was UL MU
+ OFDMA, PHY is recommended to insert the RU start index in
+ this field. Note that PHY may insert the RU width in
+ Reserved_2a[6:0].
+
+ <legal all>
+*/
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_LSB 16
+#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
+
+/* Description RECEIVE_USER_INFO_1_OFDMA_USER_INDEX
+
+ Field only valid in the of DL MU OFDMA reception
+
+
+
+ The user number within the RU_allocation.
+
+
+
+ This is needed for SW to determine the exact RU position
+ within the reception.
+
+ <legal all>
+*/
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_LSB 24
+#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_MASK 0x7f000000
+
+/* Description RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL
+
+ Field only valid in the of DL MU OFDMA/MIMO reception
+
+
+
+ In case of DL MU reception, this field indicates the
+ content channel number where PHY found the RU information
+ for this user
+
+
+
+ This is needed for SW to determine the exact RU position
+ within the reception.
+
+
+
+ <enum 0 content_channel_1>
+
+ <enum 1 content_channel_2>
+
+
+
+ <legal all>
+*/
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_LSB 31
+#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
+
+/* Description RECEIVE_USER_INFO_2_LDPC
+
+ When set, use LDPC transmission rates were used.
+
+ <legal all>
+*/
+#define RECEIVE_USER_INFO_2_LDPC_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_2_LDPC_LSB 0
+#define RECEIVE_USER_INFO_2_LDPC_MASK 0x00000001
+
+/* Description RECEIVE_USER_INFO_2_RU_WIDTH
+
+ In case of UL OFDMA reception, PHY is recommended to
+ insert the RU width
+
+ In Hastings80: was using Reserved_2a[6:0].
+
+ <legal 1 - 74>
+*/
+#define RECEIVE_USER_INFO_2_RU_WIDTH_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_2_RU_WIDTH_LSB 1
+#define RECEIVE_USER_INFO_2_RU_WIDTH_MASK 0x000000fe
+
+/* Description RECEIVE_USER_INFO_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define RECEIVE_USER_INFO_2_RESERVED_2A_OFFSET 0x00000008
+#define RECEIVE_USER_INFO_2_RESERVED_2A_LSB 8
+#define RECEIVE_USER_INFO_2_RESERVED_2A_MASK 0xffffff00
+
+
+#endif // _RECEIVE_USER_INFO_H_
diff --git a/hw/qca5018/reo_descriptor_threshold_reached_status.h b/hw/qca5018/reo_descriptor_threshold_reached_status.h
new file mode 100644
index 0000000..a12a10e
--- /dev/null
+++ b/hw/qca5018/reo_descriptor_threshold_reached_status.h
@@ -0,0 +1,657 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct uniform_reo_status_header status_header;
+// 2 threshold_index[1:0], reserved_2[31:2]
+// 3 link_descriptor_counter0[23:0], reserved_3[31:24]
+// 4 link_descriptor_counter1[23:0], reserved_4[31:24]
+// 5 link_descriptor_counter2[23:0], reserved_5[31:24]
+// 6 link_descriptor_counter_sum[25:0], reserved_6[31:26]
+// 7 reserved_7[31:0]
+// 8 reserved_8[31:0]
+// 9 reserved_9a[31:0]
+// 10 reserved_10a[31:0]
+// 11 reserved_11a[31:0]
+// 12 reserved_12a[31:0]
+// 13 reserved_13a[31:0]
+// 14 reserved_14a[31:0]
+// 15 reserved_15a[31:0]
+// 16 reserved_16a[31:0]
+// 17 reserved_17a[31:0]
+// 18 reserved_18a[31:0]
+// 19 reserved_19a[31:0]
+// 20 reserved_20a[31:0]
+// 21 reserved_21a[31:0]
+// 22 reserved_22a[31:0]
+// 23 reserved_23a[31:0]
+// 24 reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25
+
+struct reo_descriptor_threshold_reached_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t threshold_index : 2, //[1:0]
+ reserved_2 : 30; //[31:2]
+ uint32_t link_descriptor_counter0 : 24, //[23:0]
+ reserved_3 : 8; //[31:24]
+ uint32_t link_descriptor_counter1 : 24, //[23:0]
+ reserved_4 : 8; //[31:24]
+ uint32_t link_descriptor_counter2 : 24, //[23:0]
+ reserved_5 : 8; //[31:24]
+ uint32_t link_descriptor_counter_sum : 26, //[25:0]
+ reserved_6 : 6; //[31:26]
+ uint32_t reserved_7 : 32; //[31:0]
+ uint32_t reserved_8 : 32; //[31:0]
+ uint32_t reserved_9a : 32; //[31:0]
+ uint32_t reserved_10a : 32; //[31:0]
+ uint32_t reserved_11a : 32; //[31:0]
+ uint32_t reserved_12a : 32; //[31:0]
+ uint32_t reserved_13a : 32; //[31:0]
+ uint32_t reserved_14a : 32; //[31:0]
+ uint32_t reserved_15a : 32; //[31:0]
+ uint32_t reserved_16a : 32; //[31:0]
+ uint32_t reserved_17a : 32; //[31:0]
+ uint32_t reserved_18a : 32; //[31:0]
+ uint32_t reserved_19a : 32; //[31:0]
+ uint32_t reserved_20a : 32; //[31:0]
+ uint32_t reserved_21a : 32; //[31:0]
+ uint32_t reserved_22a : 32; //[31:0]
+ uint32_t reserved_23a : 32; //[31:0]
+ uint32_t reserved_24a : 28, //[27:0]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+ Consumer: SW
+
+ Producer: REO
+
+
+
+ Details that can link this status with the original
+ command. It also contains info on how long REO took to
+ execute this command.
+
+threshold_index
+
+ The index of the threshold register whose value got
+ reached
+
+
+
+ <enum 0 reo_desc_counter0_threshold>
+
+ <enum 1 reo_desc_counter1_threshold>
+
+ <enum 2 reo_desc_counter2_threshold>
+
+ <enum 3 reo_desc_counter_sum_threshold>
+
+
+
+ <legal all>
+
+reserved_2
+
+ <legal 0>
+
+link_descriptor_counter0
+
+ Value of this counter at generation of this message
+
+ <legal all>
+
+reserved_3
+
+ <legal 0>
+
+link_descriptor_counter1
+
+ Value of this counter at generation of this message
+
+ <legal all>
+
+reserved_4
+
+ <legal 0>
+
+link_descriptor_counter2
+
+ Value of this counter at generation of this message
+
+ <legal all>
+
+reserved_5
+
+ <legal 0>
+
+link_descriptor_counter_sum
+
+ Value of this counter at generation of this message
+
+ <legal all>
+
+reserved_6
+
+ <legal 0>
+
+reserved_7
+
+ <legal 0>
+
+reserved_8
+
+ <legal 0>
+
+reserved_9a
+
+ <legal 0>
+
+reserved_10a
+
+ <legal 0>
+
+reserved_11a
+
+ <legal 0>
+
+reserved_12a
+
+ <legal 0>
+
+reserved_13a
+
+ <legal 0>
+
+reserved_14a
+
+ <legal 0>
+
+reserved_15a
+
+ <legal 0>
+
+reserved_16a
+
+ <legal 0>
+
+reserved_17a
+
+ <legal 0>
+
+reserved_18a
+
+ <legal 0>
+
+reserved_19a
+
+ <legal 0>
+
+reserved_20a
+
+ <legal 0>
+
+reserved_21a
+
+ <legal 0>
+
+reserved_22a
+
+ <legal 0>
+
+reserved_23a
+
+ <legal 0>
+
+reserved_24a
+
+ <legal 0>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
+
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX
+
+ The index of the threshold register whose value got
+ reached
+
+
+
+ <enum 0 reo_desc_counter0_threshold>
+
+ <enum 1 reo_desc_counter1_threshold>
+
+ <enum 2 reo_desc_counter2_threshold>
+
+ <enum 3 reo_desc_counter_sum_threshold>
+
+
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0
+
+ Value of this counter at generation of this message
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1
+
+ Value of this counter at generation of this message
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2
+
+ Value of this counter at generation of this message
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM
+
+ Value of this counter at generation of this message
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A
+
+ <legal 0>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_
diff --git a/hw/qca5018/reo_destination_ring.h b/hw/qca5018/reo_destination_ring.h
new file mode 100644
index 0000000..b592a4c
--- /dev/null
+++ b/hw/qca5018/reo_destination_ring.h
@@ -0,0 +1,1688 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "rx_msdu_desc_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct buffer_addr_info buf_or_link_desc_addr_info;
+// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+// 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details;
+// 6 rx_reo_queue_desc_addr_31_0[31:0]
+// 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16]
+// 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], captured_msdu_data_size[20:17], sw_exception[21], reserved_8a[31:22]
+// 9 reo_destination_struct_signature[31:0]
+// 10 reserved_10a[31:0]
+// 11 reserved_11a[31:0]
+// 12 reserved_12a[31:0]
+// 13 reserved_13a[31:0]
+// 14 reserved_14a[31:0]
+// 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 16
+
+struct reo_destination_ring {
+ struct buffer_addr_info buf_or_link_desc_addr_info;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
+ reo_dest_buffer_type : 1, //[8]
+ reo_push_reason : 2, //[10:9]
+ reo_error_code : 5, //[15:11]
+ receive_queue_number : 16; //[31:16]
+ uint32_t soft_reorder_info_valid : 1, //[0]
+ reorder_opcode : 4, //[4:1]
+ reorder_slot_index : 8, //[12:5]
+ mpdu_fragment_number : 4, //[16:13]
+ captured_msdu_data_size : 4, //[20:17]
+ sw_exception : 1, //[21]
+ reserved_8a : 10; //[31:22]
+ uint32_t reo_destination_struct_signature: 32; //[31:0]
+ uint32_t reserved_10a : 32; //[31:0]
+ uint32_t reserved_11a : 32; //[31:0]
+ uint32_t reserved_12a : 32; //[31:0]
+ uint32_t reserved_13a : 32; //[31:0]
+ uint32_t reserved_14a : 32; //[31:0]
+ uint32_t reserved_15 : 20, //[19:0]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct buffer_addr_info buf_or_link_desc_addr_info
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Details of the physical address of the a buffer or MSDU
+ link descriptor
+
+struct rx_mpdu_desc_info rx_mpdu_desc_info_details
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ General information related to the MPDU that is passed
+ on from REO entrance ring to the REO destination ring
+
+struct rx_msdu_desc_info rx_msdu_desc_info_details
+
+ General information related to the MSDU that is passed
+ on from RXDMA all the way to to the REO destination ring.
+
+rx_reo_queue_desc_addr_31_0
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+ <legal all>
+
+rx_reo_queue_desc_addr_39_32
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+ <legal all>
+
+reo_dest_buffer_type
+
+ Indicates the type of address provided in the
+ 'Buf_or_link_desc_addr_info'
+
+
+
+ <enum 0 MSDU_buf_address> The address of an MSDU buffer
+
+ <enum 1 MSDU_link_desc_address> The address of the MSDU
+ link descriptor.
+
+
+
+ <legal all>
+
+reo_push_reason
+
+ Indicates why REO pushed the frame to this exit ring
+
+
+
+ <enum 0 reo_error_detected> Reo detected an error an
+ pushed this frame to this queue
+
+ <enum 1 reo_routing_instruction> Reo pushed the frame to
+ this queue per received routing instructions. No error
+ within REO was detected
+
+
+
+
+
+ <legal 0 - 1>
+
+reo_error_code
+
+ Field only valid when 'Reo_push_reason' set to
+ 'reo_error_detected'.
+
+
+
+ <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+ provided in the REO_ENTRANCE ring is set to 0
+
+ <enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+ valid bit is NOT set
+
+ <enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+ session having been setup.
+
+ <enum 3 non_ba_duplicate> Non-BA session, SN equal to
+ SSN, Retry bit set: duplicate frame
+
+ <enum 4 ba_duplicate> BA session, duplicate frame
+
+ <enum 5 regular_frame_2k_jump> A normal (management/data
+ frame) received with 2K jump in SN
+
+ <enum 6 bar_frame_2k_jump> A bar received with 2K jump
+ in SSN
+
+ <enum 7 regular_frame_OOR> A normal (management/data
+ frame) received with SN falling within the OOR window
+
+ <enum 8 bar_frame_OOR> A bar received with SSN falling
+ within the OOR window
+
+ <enum 9 bar_frame_no_ba_session> A bar received without
+ a BA session
+
+ <enum 10 bar_frame_sn_equals_ssn> A bar received with
+ SSN equal to SN
+
+ <enum 11 pn_check_failed> PN Check Failed packet.
+
+ <enum 12 2k_error_handling_flag_set> Frame is forwarded
+ as a result of the 'Seq_2k_error_detected_flag' been set in
+ the REO Queue descriptor
+
+ <enum 13 pn_error_handling_flag_set> Frame is forwarded
+ as a result of the 'pn_error_detected_flag' been set in the
+ REO Queue descriptor
+
+ <enum 14 queue_descriptor_blocked_set> Frame is
+ forwarded as a result of the queue descriptor(address) being
+ blocked as SW/FW seems to be currently in the process of
+ making updates to this descriptor...
+
+
+
+ <legal 0-14>
+
+receive_queue_number
+
+ This field in NOT valid (should be set to 0), when
+ SW_exception is set.
+
+ This field indicates the REO MPDU reorder queue ID from
+ which this frame originated. This field is populated from a
+ field with the same name in the RX_REO_QUEUE descriptor.
+
+ <legal all>
+
+soft_reorder_info_valid
+
+ This field in NOT valid (should be set to 0), when
+ SW_exception is set.
+
+ When set, REO has been instructed to not perform the
+ actual re-ordering of frames for this queue, but just to
+ insert the reorder opcodes
+
+ <legal all>
+
+reorder_opcode
+
+ Field is valid when 'Soft_reorder_info_valid' is set.
+ This field is always valid for debug purpose as well.
+
+ Details are in the MLD.
+
+
+
+ <enum 0 invalid>
+
+ <enum 1 fwdcur_fwdbuf>
+
+ <enum 2 fwdbuf_fwdcur>
+
+ <enum 3 qcur>
+
+ <enum 4 fwdbuf_qcur>
+
+ <enum 5 fwdbuf_drop>
+
+ <enum 6 fwdall_drop>
+
+ <enum 7 fwdall_qcur>
+
+ <enum 8 reserved_reo_opcode_1>
+
+ <enum 9 dropcur> the error reason code is in
+ reo_error_code field.
+
+ <enum 10 reserved_reo_opcode_2>
+
+ <enum 11 reserved_reo_opcode_3>
+
+ <enum 12 reserved_reo_opcode_4>
+
+ <enum 13 reserved_reo_opcode_5>
+
+ <enum 14 reserved_reo_opcode_6>
+
+ <enum 15 reserved_reo_opcode_7>
+
+
+
+ <legal all>
+
+reorder_slot_index
+
+ Field only valid when 'Soft_reorder_info_valid' is set.
+
+
+
+ TODO: add description
+
+
+
+ <legal all>
+
+mpdu_fragment_number
+
+ Field only valid when Rx_mpdu_desc_info_details.
+ Fragment_flag is set.
+
+
+
+ The fragment number from the 802.11 header.
+
+
+
+ Note that the sequence number is embedded in the field:
+ Rx_mpdu_desc_info_details. Mpdu_sequence_number
+
+
+
+ <legal all>
+
+captured_msdu_data_size
+
+ The number of following REO_DESTINATION STRUCTs that
+ have been replaced with msdu_data extracted from the
+ msdu_buffer and copied into the ring for easy FW/SW access.
+
+ Note that it is possible that these STRUCTs wrap around
+ the end of the ring.
+
+ Feature supported only in HastingsPrime
+
+ <legal 0-4>
+
+sw_exception
+
+ This field has the same setting as the SW_exception
+ field in the corresponding REO_entrance_ring descriptor.
+
+ When set, the REO entrance descriptor is generated by
+ FW, and the MPDU was processed in the following way:
+
+ - NO re-order function is needed.
+
+ - MPDU delinking is determined by the setting of
+ Entrance ring field: SW_excection_mpdu_delink
+
+ - Destination ring selection is based on the setting of
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+
+reserved_8a
+
+ <legal 0>
+
+reo_destination_struct_signature
+
+ Set to value 0x8888_88888 when msdu capture mode is
+ enabled for this ring (supported only in HastingsPrime)
+
+ <legal 0, 2290649224 >
+
+reserved_10a
+
+ <legal 0>
+
+reserved_11a
+
+ <legal 0>
+
+reserved_12a
+
+ <legal 0>
+
+reserved_13a
+
+ <legal 0>
+
+reserved_14a
+
+ <legal 0>
+
+reserved_15
+
+ <legal 0>
+
+ring_id
+
+ The buffer pointer ring ID.
+
+ 0 refers to the IDLE ring
+
+ 1 - N refers to other rings
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buf_or_link_desc_addr_info */
+
+
+/* Description REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
+
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The number of MSDUs within the MPDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The field can have two different meanings based on the
+ setting of field 'BAR_frame':
+
+
+
+ 'BAR_frame' is NOT set:
+
+ The MPDU sequence number of the received frame.
+
+
+
+ 'BAR_frame' is set.
+
+ The MPDU Start sequence number from the BAR frame
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, this MPDU is a fragment and REO should forward
+ this fragment MPDU to the REO destination ring without any
+ reorder checks, pn checks or bitmap update. This implies
+ that REO is forwarding the pointer to the MSDU link
+ descriptor. The destination ring is coming from a
+ programmable register setting in REO
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The retry bit setting from the MPDU header of the
+ received frame
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the MPDU was received as part of an A-MPDU.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the received frame is a BAR frame. After
+ processing, this frame shall be pushed to SW or deleted.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Copied here by RXDMA from RX_MPDU_END
+
+ When not set, REO will Not perform a PN sequence number
+ check
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ When set, OLE found a valid SA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC source address search due to the expiration
+ of the search timer.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ When set, OLE found a valid DA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ When set, at least one of the DA addresses is a
+ Multicast or Broadcast address.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC destination address search due to the
+ expiration of the search timer.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Field only valid when first_msdu_in_mpdu_flag is set.
+
+
+
+ When set, the contents in the MSDU buffer contains a
+ 'RAW' MPDU. This 'RAW' MPDU might be spread out over
+ multiple MSDU buffers.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+/* Description REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
+
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+/* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+/* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+/* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE
+
+ Indicates the type of address provided in the
+ 'Buf_or_link_desc_addr_info'
+
+
+
+ <enum 0 MSDU_buf_address> The address of an MSDU buffer
+
+ <enum 1 MSDU_link_desc_address> The address of the MSDU
+ link descriptor.
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100
+
+/* Description REO_DESTINATION_RING_7_REO_PUSH_REASON
+
+ Indicates why REO pushed the frame to this exit ring
+
+
+
+ <enum 0 reo_error_detected> Reo detected an error an
+ pushed this frame to this queue
+
+ <enum 1 reo_routing_instruction> Reo pushed the frame to
+ this queue per received routing instructions. No error
+ within REO was detected
+
+
+
+
+
+ <legal 0 - 1>
+*/
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600
+
+/* Description REO_DESTINATION_RING_7_REO_ERROR_CODE
+
+ Field only valid when 'Reo_push_reason' set to
+ 'reo_error_detected'.
+
+
+
+ <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+ provided in the REO_ENTRANCE ring is set to 0
+
+ <enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+ valid bit is NOT set
+
+ <enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+ session having been setup.
+
+ <enum 3 non_ba_duplicate> Non-BA session, SN equal to
+ SSN, Retry bit set: duplicate frame
+
+ <enum 4 ba_duplicate> BA session, duplicate frame
+
+ <enum 5 regular_frame_2k_jump> A normal (management/data
+ frame) received with 2K jump in SN
+
+ <enum 6 bar_frame_2k_jump> A bar received with 2K jump
+ in SSN
+
+ <enum 7 regular_frame_OOR> A normal (management/data
+ frame) received with SN falling within the OOR window
+
+ <enum 8 bar_frame_OOR> A bar received with SSN falling
+ within the OOR window
+
+ <enum 9 bar_frame_no_ba_session> A bar received without
+ a BA session
+
+ <enum 10 bar_frame_sn_equals_ssn> A bar received with
+ SSN equal to SN
+
+ <enum 11 pn_check_failed> PN Check Failed packet.
+
+ <enum 12 2k_error_handling_flag_set> Frame is forwarded
+ as a result of the 'Seq_2k_error_detected_flag' been set in
+ the REO Queue descriptor
+
+ <enum 13 pn_error_handling_flag_set> Frame is forwarded
+ as a result of the 'pn_error_detected_flag' been set in the
+ REO Queue descriptor
+
+ <enum 14 queue_descriptor_blocked_set> Frame is
+ forwarded as a result of the queue descriptor(address) being
+ blocked as SW/FW seems to be currently in the process of
+ making updates to this descriptor...
+
+
+
+ <legal 0-14>
+*/
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800
+
+/* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER
+
+ This field in NOT valid (should be set to 0), when
+ SW_exception is set.
+
+ This field indicates the REO MPDU reorder queue ID from
+ which this frame originated. This field is populated from a
+ field with the same name in the RX_REO_QUEUE descriptor.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000
+
+/* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID
+
+ This field in NOT valid (should be set to 0), when
+ SW_exception is set.
+
+ When set, REO has been instructed to not perform the
+ actual re-ordering of frames for this queue, but just to
+ insert the reorder opcodes
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001
+
+/* Description REO_DESTINATION_RING_8_REORDER_OPCODE
+
+ Field is valid when 'Soft_reorder_info_valid' is set.
+ This field is always valid for debug purpose as well.
+
+ Details are in the MLD.
+
+
+
+ <enum 0 invalid>
+
+ <enum 1 fwdcur_fwdbuf>
+
+ <enum 2 fwdbuf_fwdcur>
+
+ <enum 3 qcur>
+
+ <enum 4 fwdbuf_qcur>
+
+ <enum 5 fwdbuf_drop>
+
+ <enum 6 fwdall_drop>
+
+ <enum 7 fwdall_qcur>
+
+ <enum 8 reserved_reo_opcode_1>
+
+ <enum 9 dropcur> the error reason code is in
+ reo_error_code field.
+
+ <enum 10 reserved_reo_opcode_2>
+
+ <enum 11 reserved_reo_opcode_3>
+
+ <enum 12 reserved_reo_opcode_4>
+
+ <enum 13 reserved_reo_opcode_5>
+
+ <enum 14 reserved_reo_opcode_6>
+
+ <enum 15 reserved_reo_opcode_7>
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e
+
+/* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX
+
+ Field only valid when 'Soft_reorder_info_valid' is set.
+
+
+
+ TODO: add description
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0
+
+/* Description REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER
+
+ Field only valid when Rx_mpdu_desc_info_details.
+ Fragment_flag is set.
+
+
+
+ The fragment number from the 802.11 header.
+
+
+
+ Note that the sequence number is embedded in the field:
+ Rx_mpdu_desc_info_details. Mpdu_sequence_number
+
+
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13
+#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000
+
+/* Description REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE
+
+ The number of following REO_DESTINATION STRUCTs that
+ have been replaced with msdu_data extracted from the
+ msdu_buffer and copied into the ring for easy FW/SW access.
+
+ Note that it is possible that these STRUCTs wrap around
+ the end of the ring.
+
+ Feature supported only in HastingsPrime
+
+ <legal 0-4>
+*/
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17
+#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000
+
+/* Description REO_DESTINATION_RING_8_SW_EXCEPTION
+
+ This field has the same setting as the SW_exception
+ field in the corresponding REO_entrance_ring descriptor.
+
+ When set, the REO entrance descriptor is generated by
+ FW, and the MPDU was processed in the following way:
+
+ - NO re-order function is needed.
+
+ - MPDU delinking is determined by the setting of
+ Entrance ring field: SW_excection_mpdu_delink
+
+ - Destination ring selection is based on the setting of
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21
+#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000
+
+/* Description REO_DESTINATION_RING_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22
+#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000
+
+/* Description REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE
+
+ Set to value 0x8888_88888 when msdu capture mode is
+ enabled for this ring (supported only in HastingsPrime)
+
+ <legal 0, 2290649224 >
+*/
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0
+#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff
+
+/* Description REO_DESTINATION_RING_10_RESERVED_10A
+
+ <legal 0>
+*/
+#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0
+#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description REO_DESTINATION_RING_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0
+#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description REO_DESTINATION_RING_12_RESERVED_12A
+
+ <legal 0>
+*/
+#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0
+#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description REO_DESTINATION_RING_13_RESERVED_13A
+
+ <legal 0>
+*/
+#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0
+#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description REO_DESTINATION_RING_14_RESERVED_14A
+
+ <legal 0>
+*/
+#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0
+#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description REO_DESTINATION_RING_15_RESERVED_15
+
+ <legal 0>
+*/
+#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c
+#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0
+#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff
+
+/* Description REO_DESTINATION_RING_15_RING_ID
+
+ The buffer pointer ring ID.
+
+ 0 refers to the IDLE ring
+
+ 1 - N refers to other rings
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c
+#define REO_DESTINATION_RING_15_RING_ID_LSB 20
+#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000
+
+/* Description REO_DESTINATION_RING_15_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_DESTINATION_RING_H_
diff --git a/hw/qca5018/reo_entrance_ring.h b/hw/qca5018/reo_entrance_ring.h
new file mode 100644
index 0000000..1c1e494
--- /dev/null
+++ b/hw/qca5018/reo_entrance_ring.h
@@ -0,0 +1,1547 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_details.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info;
+// 4 rx_reo_queue_desc_addr_31_0[31:0]
+// 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
+// 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], sw_exception[11], sw_exception_mpdu_delink[12], sw_exception_destination_ring_valid[13], sw_exception_destination_ring[18:14], reserved_6a[31:19]
+// 7 phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+ struct rx_mpdu_details reo_level_mpdu_frame_info;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
+ rounded_mpdu_byte_count : 14, //[21:8]
+ reo_destination_indication : 5, //[26:22]
+ frameless_bar : 1, //[27]
+ reserved_5a : 4; //[31:28]
+ uint32_t rxdma_push_reason : 2, //[1:0]
+ rxdma_error_code : 5, //[6:2]
+ mpdu_fragment_number : 4, //[10:7]
+ sw_exception : 1, //[11]
+ sw_exception_mpdu_delink : 1, //[12]
+ sw_exception_destination_ring_valid: 1, //[13]
+ sw_exception_destination_ring : 5, //[18:14]
+ reserved_6a : 13; //[31:19]
+ uint32_t phy_ppdu_id : 16, //[15:0]
+ reserved_7a : 4, //[19:16]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct rx_mpdu_details reo_level_mpdu_frame_info
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Details related to the MPDU being pushed into the REO
+
+rx_reo_queue_desc_addr_31_0
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+ <legal all>
+
+rx_reo_queue_desc_addr_39_32
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+ <legal all>
+
+rounded_mpdu_byte_count
+
+ An approximation of the number of bytes received in this
+ MPDU.
+
+ Used to keeps stats on the amount of data flowing
+ through a queue.
+
+ <legal all>
+
+reo_destination_indication
+
+ RXDMA copy the MPDU's first MSDU's destination
+ indication field here. This is used for REO to be able to
+ re-route the packet to a different SW destination ring if
+ the packet is detected as error in REO.
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+
+frameless_bar
+
+ When set, this REO entrance ring struct contains BAR
+ info from a multi TID BAR frame. The original multi TID BAR
+ frame itself contained all the REO info for the first TID,
+ but all the subsequent TID info and their linkage to the REO
+ descriptors is passed down as 'frameless' BAR info.
+
+
+
+ The only fields valid in this descriptor when this bit
+ is set are:
+
+ Rx_reo_queue_desc_addr_31_0
+
+ RX_reo_queue_desc_addr_39_32
+
+
+
+ And within the
+
+ Reo_level_mpdu_frame_info:
+
+ Within Rx_mpdu_desc_info_details:
+
+ Mpdu_Sequence_number
+
+ BAR_frame
+
+ Peer_meta_data
+
+ All other fields shall be set to 0
+
+
+
+ <legal all>
+
+reserved_5a
+
+ <legal 0>
+
+rxdma_push_reason
+
+ Indicates why rxdma pushed the frame to this ring
+
+
+
+ This field is ignored by REO.
+
+
+
+ <enum 0 rxdma_error_detected> RXDMA detected an error an
+ pushed this frame to this queue
+
+ <enum 1 rxdma_routing_instruction> RXDMA pushed the
+ frame to this queue per received routing instructions. No
+ error within RXDMA was detected
+
+ <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
+ result the MSDU link descriptor might not have the
+ last_msdu_in_mpdu_flag set, but instead WBM might just see a
+ NULL pointer in the MSDU link descriptor. This is to be
+ considered a normal condition for this scenario.
+
+
+
+ <legal 0 - 2>
+
+rxdma_error_code
+
+ Field only valid when 'rxdma_push_reason' set to
+ 'rxdma_error_detected'.
+
+
+
+ This field is ignored by REO.
+
+
+
+ <enum 0 rxdma_overflow_err>MPDU frame is not complete
+ due to a FIFO overflow error in RXPCU.
+
+ <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+ due to receiving incomplete MPDU from the PHY
+
+
+ <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+ error or CRYPTO received an encrypted frame, but did not get
+ a valid corresponding key id in the peer entry.
+
+ <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+ error
+
+ <enum 5 rxdma_unecrypted_err>CRYPTO reported an
+ unencrypted frame error when encrypted was expected
+
+ <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+ length error
+
+ <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+ number of MSDUs allowed in an MPDU got exceeded
+
+ <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+ error
+
+ <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+ parsing error
+
+ <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+ during SA search
+
+ <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+ during DA search
+
+ <enum 12 rxdma_flow_timeout_err>RX OLE reported a
+ timeout during flow search
+
+ <enum 13 rxdma_flush_request>RXDMA received a flush
+ request
+
+ <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
+ present as well as a fragmented MPDU. A-MSDU defragmentation
+ is not supported in Lithium SW so this is treated as an
+ error.
+
+mpdu_fragment_number
+
+ Field only valid when Reo_level_mpdu_frame_info.
+ Rx_mpdu_desc_info_details.Fragment_flag is set.
+
+
+
+ The fragment number from the 802.11 header.
+
+
+
+ Note that the sequence number is embedded in the field:
+ Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.
+ Mpdu_sequence_number
+
+
+
+ <legal all>
+
+sw_exception
+
+ When not set, REO is performing all its default MPDU
+ processing operations,
+
+ When set, this REO entrance descriptor is generated by
+ FW, and should be processed as an exception. This implies:
+
+ NO re-order function is needed.
+
+ MPDU delinking is determined by the setting of field
+ SW_excection_mpdu_delink
+
+ Destination ring selection is based on the setting of
+ the field SW_exception_destination_ring_valid
+
+ In the destination ring descriptor set bit:
+ SW_exception_entry
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+
+sw_exception_mpdu_delink
+
+ Field only valid when SW_exception is set.
+
+ 1'b0: REO should NOT delink the MPDU, and thus pass this
+ MPDU on to the destination ring as is. This implies that in
+ the REO_DESTINATION_RING struct field
+ Buf_or_link_desc_addr_info should point to an MSDU link
+ descriptor
+
+ 1'b1: REO should perform the normal MPDU delink into
+ MSDU operations.
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+
+sw_exception_destination_ring_valid
+
+ Field only valid when SW_exception is set.
+
+ 1'b0: REO shall push the MPDU (or delinked MPDU based on
+ the setting of SW_exception_mpdu_delink) to the destination
+ ring according to field reo_destination_indication.
+
+ 1'b1: REO shall push the MPDU (or delinked MPDU based on
+ the setting of SW_exception_mpdu_delink) to the destination
+ ring according to field SW_exception_destination_ring.
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+
+sw_exception_destination_ring
+
+ Field only valid when fields SW_exception and
+ SW_exception_destination_ring_valid are set.
+
+ The ID of the ring where REO shall push this frame.
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> REO remaps this
+
+ <enum 8 reo_destination_sw6> REO remaps this
+
+ <enum 9 reo_destination_9> REO remaps this
+
+ <enum 10 reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+
+reserved_6a
+
+ <legal 0>
+
+phy_ppdu_id
+
+ A PPDU counter value that PHY increments for every PPDU
+ received
+
+ The counter value wraps around. Pine RXDMA can be
+ configured to copy this from the RX_PPDU_START TLV for every
+ output descriptor.
+
+
+
+ This field is ignored by REO.
+
+
+
+ Feature supported only in Pine
+
+ <legal all>
+
+reserved_7a
+
+ <legal 0>
+
+ring_id
+
+ Consumer: SW/REO/DEBUG
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+ It help to identify the ring that is being looked <legal
+ all>
+
+looping_count
+
+ Consumer: SW/REO/DEBUG
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */
+
+
+/* Description REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
+
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The number of MSDUs within the MPDU
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The field can have two different meanings based on the
+ setting of field 'BAR_frame':
+
+
+
+ 'BAR_frame' is NOT set:
+
+ The MPDU sequence number of the received frame.
+
+
+
+ 'BAR_frame' is set.
+
+ The MPDU Start sequence number from the BAR frame
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, this MPDU is a fragment and REO should forward
+ this fragment MPDU to the REO destination ring without any
+ reorder checks, pn checks or bitmap update. This implies
+ that REO is forwarding the pointer to the MSDU link
+ descriptor. The destination ring is coming from a
+ programmable register setting in REO
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The retry bit setting from the MPDU header of the
+ received frame
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the MPDU was received as part of an A-MPDU.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the received frame is a BAR frame. After
+ processing, this frame shall be pushed to SW or deleted.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Copied here by RXDMA from RX_MPDU_END
+
+ When not set, REO will Not perform a PN sequence number
+ check
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ When set, OLE found a valid SA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC source address search due to the expiration
+ of the search timer.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ When set, OLE found a valid DA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ When set, at least one of the DA addresses is a
+ Multicast or Broadcast address.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC destination address search due to the
+ expiration of the search timer.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Field only valid when first_msdu_in_mpdu_flag is set.
+
+
+
+ When set, the contents in the MSDU buffer contains a
+ 'RAW' MPDU. This 'RAW' MPDU might be spread out over
+ multiple MSDU buffers.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+/* Description REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+/* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
+
+ Consumer: REO
+
+ Producer: RXDMA
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
+
+ An approximation of the number of bytes received in this
+ MPDU.
+
+ Used to keeps stats on the amount of data flowing
+ through a queue.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00
+
+/* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
+
+ RXDMA copy the MPDU's first MSDU's destination
+ indication field here. This is used for REO to be able to
+ re-route the packet to a different SW destination ring if
+ the packet is detected as error in REO.
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000
+
+/* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR
+
+ When set, this REO entrance ring struct contains BAR
+ info from a multi TID BAR frame. The original multi TID BAR
+ frame itself contained all the REO info for the first TID,
+ but all the subsequent TID info and their linkage to the REO
+ descriptors is passed down as 'frameless' BAR info.
+
+
+
+ The only fields valid in this descriptor when this bit
+ is set are:
+
+ Rx_reo_queue_desc_addr_31_0
+
+ RX_reo_queue_desc_addr_39_32
+
+
+
+ And within the
+
+ Reo_level_mpdu_frame_info:
+
+ Within Rx_mpdu_desc_info_details:
+
+ Mpdu_Sequence_number
+
+ BAR_frame
+
+ Peer_meta_data
+
+ All other fields shall be set to 0
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000
+
+/* Description REO_ENTRANCE_RING_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28
+#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000
+
+/* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
+
+ Indicates why rxdma pushed the frame to this ring
+
+
+
+ This field is ignored by REO.
+
+
+
+ <enum 0 rxdma_error_detected> RXDMA detected an error an
+ pushed this frame to this queue
+
+ <enum 1 rxdma_routing_instruction> RXDMA pushed the
+ frame to this queue per received routing instructions. No
+ error within RXDMA was detected
+
+ <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
+ result the MSDU link descriptor might not have the
+ last_msdu_in_mpdu_flag set, but instead WBM might just see a
+ NULL pointer in the MSDU link descriptor. This is to be
+ considered a normal condition for this scenario.
+
+
+
+ <legal 0 - 2>
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003
+
+/* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
+
+ Field only valid when 'rxdma_push_reason' set to
+ 'rxdma_error_detected'.
+
+
+
+ This field is ignored by REO.
+
+
+
+ <enum 0 rxdma_overflow_err>MPDU frame is not complete
+ due to a FIFO overflow error in RXPCU.
+
+ <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+ due to receiving incomplete MPDU from the PHY
+
+
+ <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+ error or CRYPTO received an encrypted frame, but did not get
+ a valid corresponding key id in the peer entry.
+
+ <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+ error
+
+ <enum 5 rxdma_unecrypted_err>CRYPTO reported an
+ unencrypted frame error when encrypted was expected
+
+ <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+ length error
+
+ <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+ number of MSDUs allowed in an MPDU got exceeded
+
+ <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+ error
+
+ <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+ parsing error
+
+ <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+ during SA search
+
+ <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+ during DA search
+
+ <enum 12 rxdma_flow_timeout_err>RX OLE reported a
+ timeout during flow search
+
+ <enum 13 rxdma_flush_request>RXDMA received a flush
+ request
+
+ <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
+ present as well as a fragmented MPDU. A-MSDU defragmentation
+ is not supported in Lithium SW so this is treated as an
+ error.
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c
+
+/* Description REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER
+
+ Field only valid when Reo_level_mpdu_frame_info.
+ Rx_mpdu_desc_info_details.Fragment_flag is set.
+
+
+
+ The fragment number from the 802.11 header.
+
+
+
+ Note that the sequence number is embedded in the field:
+ Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details.
+ Mpdu_sequence_number
+
+
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7
+#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780
+
+/* Description REO_ENTRANCE_RING_6_SW_EXCEPTION
+
+ When not set, REO is performing all its default MPDU
+ processing operations,
+
+ When set, this REO entrance descriptor is generated by
+ FW, and should be processed as an exception. This implies:
+
+ NO re-order function is needed.
+
+ MPDU delinking is determined by the setting of field
+ SW_excection_mpdu_delink
+
+ Destination ring selection is based on the setting of
+ the field SW_exception_destination_ring_valid
+
+ In the destination ring descriptor set bit:
+ SW_exception_entry
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800
+
+/* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK
+
+ Field only valid when SW_exception is set.
+
+ 1'b0: REO should NOT delink the MPDU, and thus pass this
+ MPDU on to the destination ring as is. This implies that in
+ the REO_DESTINATION_RING struct field
+ Buf_or_link_desc_addr_info should point to an MSDU link
+ descriptor
+
+ 1'b1: REO should perform the normal MPDU delink into
+ MSDU operations.
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000
+
+/* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID
+
+ Field only valid when SW_exception is set.
+
+ 1'b0: REO shall push the MPDU (or delinked MPDU based on
+ the setting of SW_exception_mpdu_delink) to the destination
+ ring according to field reo_destination_indication.
+
+ 1'b1: REO shall push the MPDU (or delinked MPDU based on
+ the setting of SW_exception_mpdu_delink) to the destination
+ ring according to field SW_exception_destination_ring.
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000
+
+/* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING
+
+ Field only valid when fields SW_exception and
+ SW_exception_destination_ring_valid are set.
+
+ The ID of the ring where REO shall push this frame.
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> REO remaps this
+
+ <enum 8 reo_destination_sw6> REO remaps this
+
+ <enum 9 reo_destination_9> REO remaps this
+
+ <enum 10 reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ Feature supported only in HastingsPrime
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14
+#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000
+
+/* Description REO_ENTRANCE_RING_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19
+#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000
+
+/* Description REO_ENTRANCE_RING_7_PHY_PPDU_ID
+
+ A PPDU counter value that PHY increments for every PPDU
+ received
+
+ The counter value wraps around. Pine RXDMA can be
+ configured to copy this from the RX_PPDU_START TLV for every
+ output descriptor.
+
+
+
+ This field is ignored by REO.
+
+
+
+ Feature supported only in Pine
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0
+#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff
+
+/* Description REO_ENTRANCE_RING_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16
+#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000
+
+/* Description REO_ENTRANCE_RING_7_RING_ID
+
+ Consumer: SW/REO/DEBUG
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+ It help to identify the ring that is being looked <legal
+ all>
+*/
+#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_RING_ID_LSB 20
+#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000
+
+/* Description REO_ENTRANCE_RING_7_LOOPING_COUNT
+
+ Consumer: SW/REO/DEBUG
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_ENTRANCE_RING_H_
diff --git a/hw/qca5018/reo_flush_cache.h b/hw/qca5018/reo_flush_cache.h
new file mode 100644
index 0000000..e646bbb
--- /dev/null
+++ b/hw/qca5018/reo_flush_cache.h
@@ -0,0 +1,533 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_FLUSH_CACHE_H_
+#define _REO_FLUSH_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_reo_cmd_header cmd_header;
+// 1 flush_addr_31_0[31:0]
+// 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9
+
+struct reo_flush_cache {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t flush_addr_31_0 : 32; //[31:0]
+ uint32_t flush_addr_39_32 : 8, //[7:0]
+ forward_all_mpdus_in_queue : 1, //[8]
+ release_cache_block_index : 1, //[9]
+ cache_block_resource_index : 2, //[11:10]
+ flush_without_invalidate : 1, //[12]
+ block_cache_usage_after_flush : 1, //[13]
+ flush_entire_cache : 1, //[14]
+ reserved_2b : 17; //[31:15]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Details for command execution tracking purposes.
+
+flush_addr_31_0
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (lower 32 bits) of the descriptor to flush
+
+ <legal all>
+
+flush_addr_39_32
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (upper 8 bits) of the descriptor to flush
+
+ <legal all>
+
+forward_all_mpdus_in_queue
+
+ Is only allowed to be set when the flush address
+ corresponds with a REO descriptor.
+
+
+
+ When set, REO shall first forward all the MPDUs held in
+ the indicated re-order queue, before flushing the descriptor
+ from the cache.
+
+ <legal all>
+
+release_cache_block_index
+
+ Field not valid when Flush_entire_cache is set.
+
+
+
+ If SW has previously used a blocking resource that it
+ now wants to re-use for this command, this bit shall be set.
+ It prevents SW from having to send a separate
+ REO_UNBLOCK_CACHE command.
+
+
+
+ When set, HW will first release the blocking resource
+ (indicated in field 'Cache_block_resouce_index') before this
+ command gets executed.
+
+ If that resource was already unblocked, this will be
+ considered an error. This command will not be executed, and
+ an error shall be returned.
+
+ <legal all>
+
+cache_block_resource_index
+
+ Field not valid when Flush_entire_cache is set.
+
+
+
+ Indicates which of the four blocking resources in REO
+ will be assigned for managing the blocking of this
+ (descriptor) address
+
+ <legal all>
+
+flush_without_invalidate
+
+ Field not valid when Flush_entire_cache is set.
+
+
+
+ When set, REO shall flush the cache line contents from
+ the cache, but there is NO need to invalidate the cache line
+ entry... The contents in the cache can be maintained. This
+ feature can be used by SW (and DV) to get a current snapshot
+ of the contents in the cache
+
+
+
+ <legal all>
+
+block_cache_usage_after_flush
+
+ Field not valid when Flush_entire_cache is set.
+
+
+
+ When set, REO shall block any cache accesses to this
+ address till explicitly unblocked.
+
+
+
+ Whenever SW sets this bit, SW shall also set bit
+ 'Forward_all_mpdus_in_queue' to ensure all packets are
+ flushed out in order to make sure this queue desc is not in
+ one of the aging link lists. In case SW does not want to
+ flush the MPDUs in the queue, see the recipe description
+ below this TLV definition.
+
+
+
+ The 'blocking' index to be used for this is indicated in
+ field 'cache_block_resource_index'. If SW had previously
+ used this blocking resource and was not freed up yet, SW
+ shall first unblock that index (by setting bit
+ Release_cache_block_index) or use an unblock command.
+
+
+
+ If the resource indicated here was already blocked (and
+ did not get unblocked in this command), it is considered an
+ error scenario...
+
+ No flush shall happen. The status for this command shall
+ indicate error.
+
+
+
+ <legal all>
+
+flush_entire_cache
+
+ When set, the entire cache shall be flushed. The entire
+ cache will also remain blocked, till the
+ 'REO_UNBLOCK_COMMAND' is received with bit unblock type set
+ to unblock_cache. All other fields in this command are to be
+ ignored.
+
+
+
+ Note that flushing the entire cache has no changes to
+ the current settings of the blocking resource settings
+
+
+
+ <legal all>
+
+reserved_2b
+
+ <legal 0>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
+
+
+/* Description REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER
+
+ Consumer: REO/SW/DEBUG
+
+ Producer: SW
+
+
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statusses
+
+
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+/* Description REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ <enum 0 NoStatus> REO does not need to generate a status
+ TLV for the execution of this command
+
+ <enum 1 StatusRequired> REO shall generate a status TLV
+ for the execution of this command
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+/* Description REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+/* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (lower 32 bits) of the descriptor to flush
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0
+#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (upper 8 bits) of the descriptor to flush
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0
+#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE
+
+ Is only allowed to be set when the flush address
+ corresponds with a REO descriptor.
+
+
+
+ When set, REO shall first forward all the MPDUs held in
+ the indicated re-order queue, before flushing the descriptor
+ from the cache.
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8
+#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100
+
+/* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX
+
+ Field not valid when Flush_entire_cache is set.
+
+
+
+ If SW has previously used a blocking resource that it
+ now wants to re-use for this command, this bit shall be set.
+ It prevents SW from having to send a separate
+ REO_UNBLOCK_CACHE command.
+
+
+
+ When set, HW will first release the blocking resource
+ (indicated in field 'Cache_block_resouce_index') before this
+ command gets executed.
+
+ If that resource was already unblocked, this will be
+ considered an error. This command will not be executed, and
+ an error shall be returned.
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9
+#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200
+
+/* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX
+
+ Field not valid when Flush_entire_cache is set.
+
+
+
+ Indicates which of the four blocking resources in REO
+ will be assigned for managing the blocking of this
+ (descriptor) address
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10
+#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00
+
+/* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE
+
+ Field not valid when Flush_entire_cache is set.
+
+
+
+ When set, REO shall flush the cache line contents from
+ the cache, but there is NO need to invalidate the cache line
+ entry... The contents in the cache can be maintained. This
+ feature can be used by SW (and DV) to get a current snapshot
+ of the contents in the cache
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12
+#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000
+
+/* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH
+
+ Field not valid when Flush_entire_cache is set.
+
+
+
+ When set, REO shall block any cache accesses to this
+ address till explicitly unblocked.
+
+
+
+ Whenever SW sets this bit, SW shall also set bit
+ 'Forward_all_mpdus_in_queue' to ensure all packets are
+ flushed out in order to make sure this queue desc is not in
+ one of the aging link lists. In case SW does not want to
+ flush the MPDUs in the queue, see the recipe description
+ below this TLV definition.
+
+
+
+ The 'blocking' index to be used for this is indicated in
+ field 'cache_block_resource_index'. If SW had previously
+ used this blocking resource and was not freed up yet, SW
+ shall first unblock that index (by setting bit
+ Release_cache_block_index) or use an unblock command.
+
+
+
+ If the resource indicated here was already blocked (and
+ did not get unblocked in this command), it is considered an
+ error scenario...
+
+ No flush shall happen. The status for this command shall
+ indicate error.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13
+#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000
+
+/* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE
+
+ When set, the entire cache shall be flushed. The entire
+ cache will also remain blocked, till the
+ 'REO_UNBLOCK_COMMAND' is received with bit unblock type set
+ to unblock_cache. All other fields in this command are to be
+ ignored.
+
+
+
+ Note that flushing the entire cache has no changes to
+ the current settings of the blocking resource settings
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14
+#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000
+
+/* Description REO_FLUSH_CACHE_2_RESERVED_2B
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15
+#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000
+
+/* Description REO_FLUSH_CACHE_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff
+
+
+#endif // _REO_FLUSH_CACHE_H_
diff --git a/hw/qca5018/reo_flush_cache_status.h b/hw/qca5018/reo_flush_cache_status.h
new file mode 100644
index 0000000..083b03e
--- /dev/null
+++ b/hw/qca5018/reo_flush_cache_status.h
@@ -0,0 +1,796 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_FLUSH_CACHE_STATUS_H_
+#define _REO_FLUSH_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct uniform_reo_status_header status_header;
+// 2 error_detected[0], block_error_details[2:1], reserved_2a[7:3], cache_controller_flush_status_hit[8], cache_controller_flush_status_desc_type[11:9], cache_controller_flush_status_client_id[15:12], cache_controller_flush_status_error[17:16], cache_controller_flush_count[25:18], reserved_2b[31:26]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+// 9 reserved_9a[31:0]
+// 10 reserved_10a[31:0]
+// 11 reserved_11a[31:0]
+// 12 reserved_12a[31:0]
+// 13 reserved_13a[31:0]
+// 14 reserved_14a[31:0]
+// 15 reserved_15a[31:0]
+// 16 reserved_16a[31:0]
+// 17 reserved_17a[31:0]
+// 18 reserved_18a[31:0]
+// 19 reserved_19a[31:0]
+// 20 reserved_20a[31:0]
+// 21 reserved_21a[31:0]
+// 22 reserved_22a[31:0]
+// 23 reserved_23a[31:0]
+// 24 reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25
+
+struct reo_flush_cache_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1, //[0]
+ block_error_details : 2, //[2:1]
+ reserved_2a : 5, //[7:3]
+ cache_controller_flush_status_hit: 1, //[8]
+ cache_controller_flush_status_desc_type: 3, //[11:9]
+ cache_controller_flush_status_client_id: 4, //[15:12]
+ cache_controller_flush_status_error: 2, //[17:16]
+ cache_controller_flush_count : 8, //[25:18]
+ reserved_2b : 6; //[31:26]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+ uint32_t reserved_9a : 32; //[31:0]
+ uint32_t reserved_10a : 32; //[31:0]
+ uint32_t reserved_11a : 32; //[31:0]
+ uint32_t reserved_12a : 32; //[31:0]
+ uint32_t reserved_13a : 32; //[31:0]
+ uint32_t reserved_14a : 32; //[31:0]
+ uint32_t reserved_15a : 32; //[31:0]
+ uint32_t reserved_16a : 32; //[31:0]
+ uint32_t reserved_17a : 32; //[31:0]
+ uint32_t reserved_18a : 32; //[31:0]
+ uint32_t reserved_19a : 32; //[31:0]
+ uint32_t reserved_20a : 32; //[31:0]
+ uint32_t reserved_21a : 32; //[31:0]
+ uint32_t reserved_22a : 32; //[31:0]
+ uint32_t reserved_23a : 32; //[31:0]
+ uint32_t reserved_24a : 28, //[27:0]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+ Consumer: SW
+
+ Producer: REO
+
+
+
+ Details that can link this status with the original
+ command. It also contains info on how long REO took to
+ execute this command.
+
+error_detected
+
+ Status for blocking resource handling
+
+
+
+ 0: No error has been detected while executing this
+ command
+
+ 1: an error in the blocking resource management was
+ detected
+
+ See field 'Block_error_details'
+
+block_error_details
+
+ Field only valid when 'Error_detected' is set.
+
+ 0: no blocking related error found
+
+ 1: blocking resource was already in use
+
+ 2: resource that was asked to be unblocked, was not
+ blocked
+
+ <legal 0-2>
+
+reserved_2a
+
+ <legal 0>
+
+cache_controller_flush_status_hit
+
+ The status that the cache controller returned for
+ executing the flush command
+
+
+
+ descriptor hit
+
+ 1 = hit
+
+ 0 = miss
+
+ <legal all>
+
+cache_controller_flush_status_desc_type
+
+ The status that the cache controller returned for
+ executing the flush command
+
+ Descriptor type
+
+ FLOW_QUEUE_DESCRIPTOR
+ 3'd0
+
+
+ <legal all>
+
+cache_controller_flush_status_client_id
+
+ The status that the cache controller returned for
+ executing the flush command
+
+
+
+ client ID
+
+ Module who made flush the request
+
+
+
+ In REO, this is always set to 0
+
+ <legal 0>
+
+cache_controller_flush_status_error
+
+ The status that the cache controller returned for
+ executing the flush command
+
+
+
+ Error condition
+
+ 2'b00: No error found
+
+ 2'b01: HW IF still busy
+
+ 2'b10: Line is currently locked. Used for the one line
+ flush command.
+
+ 2'b11: At least one line is currently still locked. Used
+ for the cache flush command.
+
+
+
+ <legal all>
+
+cache_controller_flush_count
+
+ The number of lines that were actually flushed out.
+
+ <legal all>
+
+reserved_2b
+
+ <legal 0>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+
+reserved_9a
+
+ <legal 0>
+
+reserved_10a
+
+ <legal 0>
+
+reserved_11a
+
+ <legal 0>
+
+reserved_12a
+
+ <legal 0>
+
+reserved_13a
+
+ <legal 0>
+
+reserved_14a
+
+ <legal 0>
+
+reserved_15a
+
+ <legal 0>
+
+reserved_16a
+
+ <legal 0>
+
+reserved_17a
+
+ <legal 0>
+
+reserved_18a
+
+ <legal 0>
+
+reserved_19a
+
+ <legal 0>
+
+reserved_20a
+
+ <legal 0>
+
+reserved_21a
+
+ <legal 0>
+
+reserved_22a
+
+ <legal 0>
+
+reserved_23a
+
+ <legal 0>
+
+reserved_24a
+
+ <legal 0>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
+
+
+/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+*/
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+/* Description REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED
+
+ Status for blocking resource handling
+
+
+
+ 0: No error has been detected while executing this
+ command
+
+ 1: an error in the blocking resource management was
+ detected
+
+ See field 'Block_error_details'
+*/
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
+
+/* Description REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS
+
+ Field only valid when 'Error_detected' is set.
+
+ 0: no blocking related error found
+
+ 1: blocking resource was already in use
+
+ 2: resource that was asked to be unblocked, was not
+ blocked
+
+ <legal 0-2>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1
+#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006
+
+/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8
+
+/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT
+
+ The status that the cache controller returned for
+ executing the flush command
+
+
+
+ descriptor hit
+
+ 1 = hit
+
+ 0 = miss
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100
+
+/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE
+
+ The status that the cache controller returned for
+ executing the flush command
+
+ Descriptor type
+
+ FLOW_QUEUE_DESCRIPTOR
+ 3'd0
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00
+
+/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID
+
+ The status that the cache controller returned for
+ executing the flush command
+
+
+
+ client ID
+
+ Module who made flush the request
+
+
+
+ In REO, this is always set to 0
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000
+
+/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR
+
+ The status that the cache controller returned for
+ executing the flush command
+
+
+
+ Error condition
+
+ 2'b00: No error found
+
+ 2'b01: HW IF still busy
+
+ 2'b10: Line is currently locked. Used for the one line
+ flush command.
+
+ 2'b11: At least one line is currently still locked. Used
+ for the cache flush command.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000
+
+/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT
+
+ The number of lines that were actually flushed out.
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18
+#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000
+
+/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2B
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26
+#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000
+
+/* Description REO_FLUSH_CACHE_STATUS_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_9_RESERVED_9A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_10_RESERVED_10A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_12_RESERVED_12A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_13_RESERVED_13A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_14_RESERVED_14A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_15_RESERVED_15A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_16_RESERVED_16A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_17_RESERVED_17A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_18_RESERVED_18A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_19_RESERVED_19A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_20_RESERVED_20A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_21_RESERVED_21A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_22_RESERVED_22A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_23_RESERVED_23A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_24_RESERVED_24A
+
+ <legal 0>
+*/
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0
+#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_FLUSH_CACHE_STATUS_H_
diff --git a/hw/qca5018/reo_flush_queue.h b/hw/qca5018/reo_flush_queue.h
new file mode 100644
index 0000000..6f85678
--- /dev/null
+++ b/hw/qca5018/reo_flush_queue.h
@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_FLUSH_QUEUE_H_
+#define _REO_FLUSH_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_reo_cmd_header cmd_header;
+// 1 flush_desc_addr_31_0[31:0]
+// 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], invalidate_queue_and_flush[11], reserved_2a[31:12]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
+
+struct reo_flush_queue {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t flush_desc_addr_31_0 : 32; //[31:0]
+ uint32_t flush_desc_addr_39_32 : 8, //[7:0]
+ block_desc_addr_usage_after_flush: 1, //[8]
+ block_resource_index : 2, //[10:9]
+ invalidate_queue_and_flush : 1, //[11]
+ reserved_2a : 20; //[31:12]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Details for command execution tracking purposes.
+
+flush_desc_addr_31_0
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (lower 32 bits) of the descriptor to flush
+
+ <legal all>
+
+flush_desc_addr_39_32
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (upper 8 bits) of the descriptor to flush
+
+ <legal all>
+
+block_desc_addr_usage_after_flush
+
+ When set, REO shall not re-fetch this address till SW
+ explicitly unblocked this address
+
+
+
+ If the blocking resource was already used, this command
+ shall fail and an error is reported
+
+
+
+ <legal all>
+
+block_resource_index
+
+ Field only valid when 'Block_desc_addr_usage_after_flush
+ ' is set.
+
+
+
+ Indicates which of the four blocking resources in REO
+ will be assigned for managing the blocking of this address.
+
+ <legal all>
+
+invalidate_queue_and_flush
+
+ When set, after the queue has been completely flushed,
+ invalidate the queue by clearing VLD and flush the queue
+ descriptor from the cache.
+
+
+
+ <legal all>
+
+reserved_2a
+
+ <legal 0>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
+
+
+/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER
+
+ Consumer: REO/SW/DEBUG
+
+ Producer: SW
+
+
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statusses
+
+
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ <enum 0 NoStatus> REO does not need to generate a status
+ TLV for the execution of this command
+
+ <enum 1 StatusRequired> REO shall generate a status TLV
+ for the execution of this command
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+/* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (lower 32 bits) of the descriptor to flush
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0
+#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (upper 8 bits) of the descriptor to flush
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0
+#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
+
+ When set, REO shall not re-fetch this address till SW
+ explicitly unblocked this address
+
+
+
+ If the blocking resource was already used, this command
+ shall fail and an error is reported
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
+#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100
+
+/* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
+
+ Field only valid when 'Block_desc_addr_usage_after_flush
+ ' is set.
+
+
+
+ Indicates which of the four blocking resources in REO
+ will be assigned for managing the blocking of this address.
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9
+#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600
+
+/* Description REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH
+
+ When set, after the queue has been completely flushed,
+ invalidate the queue by clearing VLD and flush the queue
+ descriptor from the cache.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11
+#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800
+
+/* Description REO_FLUSH_QUEUE_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12
+#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000
+
+/* Description REO_FLUSH_QUEUE_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff
+
+
+#endif // _REO_FLUSH_QUEUE_H_
diff --git a/hw/qca5018/reo_flush_queue_status.h b/hw/qca5018/reo_flush_queue_status.h
new file mode 100644
index 0000000..258e23d
--- /dev/null
+++ b/hw/qca5018/reo_flush_queue_status.h
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_FLUSH_QUEUE_STATUS_H_
+#define _REO_FLUSH_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct uniform_reo_status_header status_header;
+// 2 error_detected[0], reserved_2a[31:1]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+// 9 reserved_9a[31:0]
+// 10 reserved_10a[31:0]
+// 11 reserved_11a[31:0]
+// 12 reserved_12a[31:0]
+// 13 reserved_13a[31:0]
+// 14 reserved_14a[31:0]
+// 15 reserved_15a[31:0]
+// 16 reserved_16a[31:0]
+// 17 reserved_17a[31:0]
+// 18 reserved_18a[31:0]
+// 19 reserved_19a[31:0]
+// 20 reserved_20a[31:0]
+// 21 reserved_21a[31:0]
+// 22 reserved_22a[31:0]
+// 23 reserved_23a[31:0]
+// 24 reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25
+
+struct reo_flush_queue_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1, //[0]
+ reserved_2a : 31; //[31:1]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+ uint32_t reserved_9a : 32; //[31:0]
+ uint32_t reserved_10a : 32; //[31:0]
+ uint32_t reserved_11a : 32; //[31:0]
+ uint32_t reserved_12a : 32; //[31:0]
+ uint32_t reserved_13a : 32; //[31:0]
+ uint32_t reserved_14a : 32; //[31:0]
+ uint32_t reserved_15a : 32; //[31:0]
+ uint32_t reserved_16a : 32; //[31:0]
+ uint32_t reserved_17a : 32; //[31:0]
+ uint32_t reserved_18a : 32; //[31:0]
+ uint32_t reserved_19a : 32; //[31:0]
+ uint32_t reserved_20a : 32; //[31:0]
+ uint32_t reserved_21a : 32; //[31:0]
+ uint32_t reserved_22a : 32; //[31:0]
+ uint32_t reserved_23a : 32; //[31:0]
+ uint32_t reserved_24a : 28, //[27:0]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+ Consumer: SW
+
+ Producer: REO
+
+
+
+ Details that can link this status with the original
+ command. It also contains info on how long REO took to
+ execute this command.
+
+error_detected
+
+ Status of the blocking resource
+
+ 0: No error has been detected while executing this
+ command
+
+ 1: Error detected: The resource to be used for blocking
+ was already in use.
+
+reserved_2a
+
+ <legal 0>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+
+reserved_9a
+
+ <legal 0>
+
+reserved_10a
+
+ <legal 0>
+
+reserved_11a
+
+ <legal 0>
+
+reserved_12a
+
+ <legal 0>
+
+reserved_13a
+
+ <legal 0>
+
+reserved_14a
+
+ <legal 0>
+
+reserved_15a
+
+ <legal 0>
+
+reserved_16a
+
+ <legal 0>
+
+reserved_17a
+
+ <legal 0>
+
+reserved_18a
+
+ <legal 0>
+
+reserved_19a
+
+ <legal 0>
+
+reserved_20a
+
+ <legal 0>
+
+reserved_21a
+
+ <legal 0>
+
+reserved_22a
+
+ <legal 0>
+
+reserved_23a
+
+ <legal 0>
+
+reserved_24a
+
+ <legal 0>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
+
+
+/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+*/
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+/* Description REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED
+
+ Status of the blocking resource
+
+ 0: No error has been detected while executing this
+ command
+
+ 1: Error detected: The resource to be used for blocking
+ was already in use.
+*/
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
+
+/* Description REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1
+#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe
+
+/* Description REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A
+
+ <legal 0>
+*/
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0
+#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_FLUSH_QUEUE_STATUS_H_
diff --git a/hw/qca5018/reo_flush_timeout_list.h b/hw/qca5018/reo_flush_timeout_list.h
new file mode 100644
index 0000000..8ff454e
--- /dev/null
+++ b/hw/qca5018/reo_flush_timeout_list.h
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_H_
+#define _REO_FLUSH_TIMEOUT_LIST_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_reo_cmd_header cmd_header;
+// 1 ac_timout_list[1:0], reserved_1[31:2]
+// 2 minimum_release_desc_count[15:0], minimum_forward_buf_count[31:16]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9
+
+struct reo_flush_timeout_list {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t ac_timout_list : 2, //[1:0]
+ reserved_1 : 30; //[31:2]
+ uint32_t minimum_release_desc_count : 16, //[15:0]
+ minimum_forward_buf_count : 16; //[31:16]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Details for command execution tracking purposes.
+
+ac_timout_list
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The AC_timeout list to be used for this command
+
+ <legal all>
+
+reserved_1
+
+ <legal 0>
+
+minimum_release_desc_count
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The minimum number of link descriptors requested to be
+ released. If set to 0, only buffer release counts seems to
+ be important... When set to very high value, likely the
+ entire timeout list will be exhausted before this count is
+ reached or maybe this count will not get reached. REO
+ however will stop here as it can not do anything else.
+
+
+
+ When both this field and field Minimum_forward_buf_count
+ are > 0, REO needs to meet both requirements. When both
+ entries are 0 (which should be a programming error), REO
+ does not need to do anything.
+
+
+
+ Note that this includes counts of MPDU link Desc as well
+ as MSDU link Desc. Where the count of MSDU link Desc is not
+ known to REO it's approximated by deriving from MSDU count
+
+ <legal all>
+
+minimum_forward_buf_count
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The minimum number of buffer descriptors requested to be
+ passed on to the REO destination rings.
+
+
+
+ If set to 0, only descriptor release counts seems to be
+ important...
+
+
+
+ When set to very high value, likely the entire timeout
+ list will be exhausted before this count is reached or maybe
+ this count will not get reached. REO however will stop here
+ as it can not do anything else.
+
+
+
+ Note that REO does not know the exact buffer count. This
+ can be approximated by using the MSDU_COUNT
+
+ <legal all>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
+
+
+/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER
+
+ Consumer: REO/SW/DEBUG
+
+ Producer: SW
+
+
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statusses
+
+
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ <enum 0 NoStatus> REO does not need to generate a status
+ TLV for the execution of this command
+
+ <enum 1 StatusRequired> REO shall generate a status TLV
+ for the execution of this command
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+/* Description REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The AC_timeout list to be used for this command
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003
+
+/* Description REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2
+#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc
+
+/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The minimum number of link descriptors requested to be
+ released. If set to 0, only buffer release counts seems to
+ be important... When set to very high value, likely the
+ entire timeout list will be exhausted before this count is
+ reached or maybe this count will not get reached. REO
+ however will stop here as it can not do anything else.
+
+
+
+ When both this field and field Minimum_forward_buf_count
+ are > 0, REO needs to meet both requirements. When both
+ entries are 0 (which should be a programming error), REO
+ does not need to do anything.
+
+
+
+ Note that this includes counts of MPDU link Desc as well
+ as MSDU link Desc. Where the count of MSDU link Desc is not
+ known to REO it's approximated by deriving from MSDU count
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The minimum number of buffer descriptors requested to be
+ passed on to the REO destination rings.
+
+
+
+ If set to 0, only descriptor release counts seems to be
+ important...
+
+
+
+ When set to very high value, likely the entire timeout
+ list will be exhausted before this count is reached or maybe
+ this count will not get reached. REO however will stop here
+ as it can not do anything else.
+
+
+
+ Note that REO does not know the exact buffer count. This
+ can be approximated by using the MSDU_COUNT
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000
+
+/* Description REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff
+
+
+#endif // _REO_FLUSH_TIMEOUT_LIST_H_
diff --git a/hw/qca5018/reo_flush_timeout_list_status.h b/hw/qca5018/reo_flush_timeout_list_status.h
new file mode 100644
index 0000000..736df06
--- /dev/null
+++ b/hw/qca5018/reo_flush_timeout_list_status.h
@@ -0,0 +1,643 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct uniform_reo_status_header status_header;
+// 2 error_detected[0], timout_list_empty[1], reserved_2a[31:2]
+// 3 release_desc_count[15:0], forward_buf_count[31:16]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+// 9 reserved_9a[31:0]
+// 10 reserved_10a[31:0]
+// 11 reserved_11a[31:0]
+// 12 reserved_12a[31:0]
+// 13 reserved_13a[31:0]
+// 14 reserved_14a[31:0]
+// 15 reserved_15a[31:0]
+// 16 reserved_16a[31:0]
+// 17 reserved_17a[31:0]
+// 18 reserved_18a[31:0]
+// 19 reserved_19a[31:0]
+// 20 reserved_20a[31:0]
+// 21 reserved_21a[31:0]
+// 22 reserved_22a[31:0]
+// 23 reserved_23a[31:0]
+// 24 reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25
+
+struct reo_flush_timeout_list_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1, //[0]
+ timout_list_empty : 1, //[1]
+ reserved_2a : 30; //[31:2]
+ uint32_t release_desc_count : 16, //[15:0]
+ forward_buf_count : 16; //[31:16]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+ uint32_t reserved_9a : 32; //[31:0]
+ uint32_t reserved_10a : 32; //[31:0]
+ uint32_t reserved_11a : 32; //[31:0]
+ uint32_t reserved_12a : 32; //[31:0]
+ uint32_t reserved_13a : 32; //[31:0]
+ uint32_t reserved_14a : 32; //[31:0]
+ uint32_t reserved_15a : 32; //[31:0]
+ uint32_t reserved_16a : 32; //[31:0]
+ uint32_t reserved_17a : 32; //[31:0]
+ uint32_t reserved_18a : 32; //[31:0]
+ uint32_t reserved_19a : 32; //[31:0]
+ uint32_t reserved_20a : 32; //[31:0]
+ uint32_t reserved_21a : 32; //[31:0]
+ uint32_t reserved_22a : 32; //[31:0]
+ uint32_t reserved_23a : 32; //[31:0]
+ uint32_t reserved_24a : 28, //[27:0]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+ Consumer: SW
+
+ Producer: REO
+
+
+
+ Details that can link this status with the original
+ command. It also contains info on how long REO took to
+ execute this command.
+
+error_detected
+
+ 0: No error has been detected while executing this
+ command
+
+ 1: command not properly executed and returned with an
+ error
+
+
+
+ NOTE: Current no error is defined, but field is put in
+ place to avoid data structure changes in future...
+
+timout_list_empty
+
+ When set, REO has depleted the timeout list and all
+ entries are gone.
+
+ <legal all>
+
+reserved_2a
+
+ <legal 0>
+
+release_desc_count
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The number of link descriptors released
+
+ <legal all>
+
+forward_buf_count
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The number of buffers forwarded to the REO destination
+ rings
+
+ <legal all>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+
+reserved_9a
+
+ <legal 0>
+
+reserved_10a
+
+ <legal 0>
+
+reserved_11a
+
+ <legal 0>
+
+reserved_12a
+
+ <legal 0>
+
+reserved_13a
+
+ <legal 0>
+
+reserved_14a
+
+ <legal 0>
+
+reserved_15a
+
+ <legal 0>
+
+reserved_16a
+
+ <legal 0>
+
+reserved_17a
+
+ <legal 0>
+
+reserved_18a
+
+ <legal 0>
+
+reserved_19a
+
+ <legal 0>
+
+reserved_20a
+
+ <legal 0>
+
+reserved_21a
+
+ <legal 0>
+
+reserved_22a
+
+ <legal 0>
+
+reserved_23a
+
+ <legal 0>
+
+reserved_24a
+
+ <legal 0>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
+
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED
+
+ 0: No error has been detected while executing this
+ command
+
+ 1: command not properly executed and returned with an
+ error
+
+
+
+ NOTE: Current no error is defined, but field is put in
+ place to avoid data structure changes in future...
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY
+
+ When set, REO has depleted the timeout list and all
+ entries are gone.
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The number of link descriptors released
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ The number of buffers forwarded to the REO destination
+ rings
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A
+
+ <legal 0>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_FLUSH_TIMEOUT_LIST_STATUS_H_
diff --git a/hw/qca5018/reo_get_queue_stats.h b/hw/qca5018/reo_get_queue_stats.h
new file mode 100644
index 0000000..4723b8a
--- /dev/null
+++ b/hw/qca5018/reo_get_queue_stats.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_GET_QUEUE_STATS_H_
+#define _REO_GET_QUEUE_STATS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_reo_cmd_header cmd_header;
+// 1 rx_reo_queue_desc_addr_31_0[31:0]
+// 2 rx_reo_queue_desc_addr_39_32[7:0], clear_stats[8], reserved_2a[31:9]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
+
+struct reo_get_queue_stats {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
+ clear_stats : 1, //[8]
+ reserved_2a : 23; //[31:9]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Details for command execution tracking purposes.
+
+rx_reo_queue_desc_addr_31_0
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor
+
+ <legal all>
+
+rx_reo_queue_desc_addr_39_32
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor
+
+ <legal all>
+
+clear_stats
+
+ Clear stat settings....
+
+
+
+ <enum 0 no_clear> Do NOT clear the stats after
+ generating the status
+
+ <enum 1 clear_the_stats> Clear the stats after
+ generating the status.
+
+
+
+ The stats actually cleared are:
+
+ Timeout_count
+
+ Forward_due_to_bar_count
+
+ Duplicate_count
+
+ Frames_in_order_count
+
+ BAR_received_count
+
+ MPDU_Frames_processed_count
+
+ MSDU_Frames_processed_count
+
+ Total_processed_byte_count
+
+ Late_receive_MPDU_count
+
+ window_jump_2k
+
+ Hole_count
+
+ <legal 0-1>
+
+reserved_2a
+
+ <legal 0>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
+
+
+/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER
+
+ Consumer: REO/SW/DEBUG
+
+ Producer: SW
+
+
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statusses
+
+
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ <enum 0 NoStatus> REO does not need to generate a status
+ TLV for the execution of this command
+
+ <enum 1 StatusRequired> REO shall generate a status TLV
+ for the execution of this command
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+/* Description REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_GET_QUEUE_STATS_2_CLEAR_STATS
+
+ Clear stat settings....
+
+
+
+ <enum 0 no_clear> Do NOT clear the stats after
+ generating the status
+
+ <enum 1 clear_the_stats> Clear the stats after
+ generating the status.
+
+
+
+ The stats actually cleared are:
+
+ Timeout_count
+
+ Forward_due_to_bar_count
+
+ Duplicate_count
+
+ Frames_in_order_count
+
+ BAR_received_count
+
+ MPDU_Frames_processed_count
+
+ MSDU_Frames_processed_count
+
+ Total_processed_byte_count
+
+ Late_receive_MPDU_count
+
+ window_jump_2k
+
+ Hole_count
+
+ <legal 0-1>
+*/
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100
+
+/* Description REO_GET_QUEUE_STATS_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00
+
+/* Description REO_GET_QUEUE_STATS_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff
+
+
+#endif // _REO_GET_QUEUE_STATS_H_
diff --git a/hw/qca5018/reo_get_queue_stats_status.h b/hw/qca5018/reo_get_queue_stats_status.h
new file mode 100644
index 0000000..11b7b6d
--- /dev/null
+++ b/hw/qca5018/reo_get_queue_stats_status.h
@@ -0,0 +1,965 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
+#define _REO_GET_QUEUE_STATS_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct uniform_reo_status_header status_header;
+// 2 ssn[11:0], current_index[19:12], reserved_2[31:20]
+// 3 pn_31_0[31:0]
+// 4 pn_63_32[31:0]
+// 5 pn_95_64[31:0]
+// 6 pn_127_96[31:0]
+// 7 last_rx_enqueue_timestamp[31:0]
+// 8 last_rx_dequeue_timestamp[31:0]
+// 9 rx_bitmap_31_0[31:0]
+// 10 rx_bitmap_63_32[31:0]
+// 11 rx_bitmap_95_64[31:0]
+// 12 rx_bitmap_127_96[31:0]
+// 13 rx_bitmap_159_128[31:0]
+// 14 rx_bitmap_191_160[31:0]
+// 15 rx_bitmap_223_192[31:0]
+// 16 rx_bitmap_255_224[31:0]
+// 17 current_mpdu_count[6:0], current_msdu_count[31:7]
+// 18 reserved_18[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16]
+// 19 frames_in_order_count[23:0], bar_received_count[31:24]
+// 20 mpdu_frames_processed_count[31:0]
+// 21 msdu_frames_processed_count[31:0]
+// 22 total_processed_byte_count[31:0]
+// 23 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16]
+// 24 reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25
+
+struct reo_get_queue_stats_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t ssn : 12, //[11:0]
+ current_index : 8, //[19:12]
+ reserved_2 : 12; //[31:20]
+ uint32_t pn_31_0 : 32; //[31:0]
+ uint32_t pn_63_32 : 32; //[31:0]
+ uint32_t pn_95_64 : 32; //[31:0]
+ uint32_t pn_127_96 : 32; //[31:0]
+ uint32_t last_rx_enqueue_timestamp : 32; //[31:0]
+ uint32_t last_rx_dequeue_timestamp : 32; //[31:0]
+ uint32_t rx_bitmap_31_0 : 32; //[31:0]
+ uint32_t rx_bitmap_63_32 : 32; //[31:0]
+ uint32_t rx_bitmap_95_64 : 32; //[31:0]
+ uint32_t rx_bitmap_127_96 : 32; //[31:0]
+ uint32_t rx_bitmap_159_128 : 32; //[31:0]
+ uint32_t rx_bitmap_191_160 : 32; //[31:0]
+ uint32_t rx_bitmap_223_192 : 32; //[31:0]
+ uint32_t rx_bitmap_255_224 : 32; //[31:0]
+ uint32_t current_mpdu_count : 7, //[6:0]
+ current_msdu_count : 25; //[31:7]
+ uint32_t reserved_18 : 4, //[3:0]
+ timeout_count : 6, //[9:4]
+ forward_due_to_bar_count : 6, //[15:10]
+ duplicate_count : 16; //[31:16]
+ uint32_t frames_in_order_count : 24, //[23:0]
+ bar_received_count : 8; //[31:24]
+ uint32_t mpdu_frames_processed_count : 32; //[31:0]
+ uint32_t msdu_frames_processed_count : 32; //[31:0]
+ uint32_t total_processed_byte_count : 32; //[31:0]
+ uint32_t late_receive_mpdu_count : 12, //[11:0]
+ window_jump_2k : 4, //[15:12]
+ hole_count : 16; //[31:16]
+ uint32_t reserved_24a : 28, //[27:0]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+ Consumer: SW
+
+ Producer: REO
+
+
+
+ Details that can link this status with the original
+ command. It also contains info on how long REO took to
+ execute this command.
+
+ssn
+
+ Starting Sequence number of the session, this changes
+ whenever window moves. (can be filled by SW then maintained
+ by REO)
+
+ <legal all>
+
+current_index
+
+ Points to last forwarded packet
+
+ <legal all>
+
+reserved_2
+
+ <legal 0>
+
+pn_31_0
+
+
+ <legal all>
+
+pn_63_32
+
+ Bits [63:32] of the PN number.
+
+ <legal all>
+
+pn_95_64
+
+ Bits [95:64] of the PN number.
+
+ <legal all>
+
+pn_127_96
+
+ Bits [127:96] of the PN number.
+
+ <legal all>
+
+last_rx_enqueue_timestamp
+
+ Timestamp of arrival of the last MPDU for this queue
+
+ <legal all>
+
+last_rx_dequeue_timestamp
+
+ Timestamp of forwarding an MPDU
+
+
+
+ If the queue is empty when a frame gets received, this
+ time shall be initialized to the 'enqueue' timestamp
+
+
+
+ Used for aging
+
+ <legal all>
+
+rx_bitmap_31_0
+
+ When a bit is set, the corresponding frame is currently
+ held in the re-order queue.
+
+ The bitmap is Fully managed by HW.
+
+ SW shall init this to 0, and then never ever change it
+
+ <legal all>
+
+rx_bitmap_63_32
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_95_64
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_127_96
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_159_128
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_191_160
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_223_192
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_255_224
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+current_mpdu_count
+
+ The number of MPDUs in the queue.
+
+
+
+ <legal all>
+
+current_msdu_count
+
+ The number of MSDUs in the queue.
+
+ <legal all>
+
+reserved_18
+
+ <legal 0>
+
+timeout_count
+
+ The number of times that REO started forwarding frames
+ even though there is a hole in the bitmap. Forwarding reason
+ is Timeout
+
+
+
+ The counter saturates and freezes at 0x3F
+
+
+
+ <legal all>
+
+forward_due_to_bar_count
+
+ The number of times that REO started forwarding frames
+ even though there is a hole in the bitmap. Forwarding reason
+ is reception of BAR frame.
+
+
+
+ The counter saturates and freezes at 0x3F
+
+
+
+ <legal all>
+
+duplicate_count
+
+ The number of duplicate frames that have been detected
+
+ <legal all>
+
+frames_in_order_count
+
+ The number of frames that have been received in order
+ (without a hole that prevented them from being forwarded
+ immediately)
+
+
+
+ This corresponds to the Reorder opcodes:
+
+ 'FWDCUR' and 'FWD BUF'
+
+
+
+ <legal all>
+
+bar_received_count
+
+ The number of times a BAR frame is received.
+
+
+
+ This corresponds to the Reorder opcodes with 'DROP'
+
+
+
+ The counter saturates and freezes at 0xFF
+
+ <legal all>
+
+mpdu_frames_processed_count
+
+ The total number of MPDU frames that have been processed
+ by REO. This includes the duplicates.
+
+
+
+ <legal all>
+
+msdu_frames_processed_count
+
+ The total number of MSDU frames that have been processed
+ by REO. This includes the duplicates.
+
+
+
+ <legal all>
+
+total_processed_byte_count
+
+ An approximation of the number of bytes received for
+ this queue.
+
+
+
+ In 64 byte units
+
+ <legal all>
+
+late_receive_mpdu_count
+
+ The number of MPDUs received after the window had
+ already moved on. The 'late' sequence window is defined as
+ (Window SSN - 256) - (Window SSN - 1)
+
+
+
+ This corresponds with Out of order detection in
+ duplicate detect FSM
+
+
+
+ The counter saturates and freezes at 0xFFF
+
+
+
+ <legal all>
+
+window_jump_2k
+
+ The number of times the window moved more then 2K
+
+
+
+ The counter saturates and freezes at 0xF
+
+
+
+ (Note: field name can not start with number: previous
+ 2k_window_jump)
+
+
+
+ <legal all>
+
+hole_count
+
+ The number of times a hole was created in the receive
+ bitmap.
+
+
+
+ This corresponds to the Reorder opcodes with 'QCUR'
+
+
+
+ <legal all>
+
+reserved_24a
+
+ <legal 0>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
+
+
+/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_2_SSN
+
+ Starting Sequence number of the session, this changes
+ whenever window moves. (can be filled by SW then maintained
+ by REO)
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX
+
+ Points to last forwarded packet
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_3_PN_31_0
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_4_PN_63_32
+
+ Bits [63:32] of the PN number.
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_5_PN_95_64
+
+ Bits [95:64] of the PN number.
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_6_PN_127_96
+
+ Bits [127:96] of the PN number.
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP
+
+ Timestamp of arrival of the last MPDU for this queue
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP
+
+ Timestamp of forwarding an MPDU
+
+
+
+ If the queue is empty when a frame gets received, this
+ time shall be initialized to the 'enqueue' timestamp
+
+
+
+ Used for aging
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0
+
+ When a bit is set, the corresponding frame is currently
+ held in the re-order queue.
+
+ The bitmap is Fully managed by HW.
+
+ SW shall init this to 0, and then never ever change it
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT
+
+ The number of MPDUs in the queue.
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f
+
+/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT
+
+ The number of MSDUs in the queue.
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80
+
+/* Description REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f
+
+/* Description REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT
+
+ The number of times that REO started forwarding frames
+ even though there is a hole in the bitmap. Forwarding reason
+ is Timeout
+
+
+
+ The counter saturates and freezes at 0x3F
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0
+
+/* Description REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT
+
+ The number of times that REO started forwarding frames
+ even though there is a hole in the bitmap. Forwarding reason
+ is reception of BAR frame.
+
+
+
+ The counter saturates and freezes at 0x3F
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
+
+/* Description REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT
+
+ The number of duplicate frames that have been detected
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT
+
+ The number of frames that have been received in order
+ (without a hole that prevented them from being forwarded
+ immediately)
+
+
+
+ This corresponds to the Reorder opcodes:
+
+ 'FWDCUR' and 'FWD BUF'
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT
+
+ The number of times a BAR frame is received.
+
+
+
+ This corresponds to the Reorder opcodes with 'DROP'
+
+
+
+ The counter saturates and freezes at 0xFF
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT
+
+ The total number of MPDU frames that have been processed
+ by REO. This includes the duplicates.
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT
+
+ The total number of MSDU frames that have been processed
+ by REO. This includes the duplicates.
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT
+
+ An approximation of the number of bytes received for
+ this queue.
+
+
+
+ In 64 byte units
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT
+
+ The number of MPDUs received after the window had
+ already moved on. The 'late' sequence window is defined as
+ (Window SSN - 256) - (Window SSN - 1)
+
+
+
+ This corresponds with Out of order detection in
+ duplicate detect FSM
+
+
+
+ The counter saturates and freezes at 0xFFF
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K
+
+ The number of times the window moved more then 2K
+
+
+
+ The counter saturates and freezes at 0xF
+
+
+
+ (Note: field name can not start with number: previous
+ 2k_window_jump)
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT
+
+ The number of times a hole was created in the receive
+ bitmap.
+
+
+
+ This corresponds to the Reorder opcodes with 'QCUR'
+
+
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000
+
+/* Description REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A
+
+ <legal 0>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_GET_QUEUE_STATS_STATUS_H_
diff --git a/hw/qca5018/reo_reg_seq_hwiobase.h b/hw/qca5018/reo_reg_seq_hwiobase.h
new file mode 100644
index 0000000..463a83d
--- /dev/null
+++ b/hw/qca5018/reo_reg_seq_hwiobase.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
+// User Name:c_landav
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __REO_REG_SEQ_BASE_H__
+#define __REO_REG_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+#endif
+
diff --git a/hw/qca5018/reo_reg_seq_hwioreg.h b/hw/qca5018/reo_reg_seq_hwioreg.h
new file mode 100644
index 0000000..10f3559
--- /dev/null
+++ b/hw/qca5018/reo_reg_seq_hwioreg.h
@@ -0,0 +1,9097 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 2/21/2020
+// User Name:c_landav
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __REO_REG_SEQ_REG_H__
+#define __REO_REG_SEQ_REG_H__
+
+#include "seq_hwio.h"
+#include "reo_reg_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block REO_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register REO_R0_GENERAL_ENABLE ////
+
+#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000)
+#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000)
+#define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0xfbffff7f
+#define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0
+#define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK)
+#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask)
+#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val)
+#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x80000000
+#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 0x1f
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK 0x40000000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT 0x1e
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK 0x20000000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT 0x1d
+
+#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000
+#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 0x1c
+
+#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x08000000
+#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1b
+
+#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x03800000
+#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x17
+
+#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00400000
+#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x16
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00200000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x15
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00100000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x14
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00080000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x13
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00040000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x12
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00020000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x11
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00010000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0x10
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00008000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xf
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00004000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xe
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00002000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xd
+
+#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00001000
+#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xc
+
+#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000e00
+#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x9
+
+#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000100
+#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x8
+
+#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x00000070
+#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4
+
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3
+
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0
+
+//// Register REO_R0_DESTINATION_RING_CTRL_IX_0 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0x77777777
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0x70000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1c
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x07000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x18
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00070000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x10
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x00007000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0xc
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0x8
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00000070
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0x4
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000007
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x0
+
+//// Register REO_R0_DESTINATION_RING_CTRL_IX_1 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0x77777777
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0x70000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1c
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x07000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x18
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00070000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x10
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x00007000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0xc
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0x8
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00000070
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0x4
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000007
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x0
+
+//// Register REO_R0_DESTINATION_RING_CTRL_IX_2 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0x77777777
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0x70000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1c
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x07000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x18
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00070000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x10
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x00007000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0xc
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0x8
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00000070
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0x4
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000007
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x0
+
+//// Register REO_R0_DESTINATION_RING_CTRL_IX_3 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0x77777777
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 0
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0x70000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1c
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x07000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x18
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00070000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x10
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x00007000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0xc
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0x8
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00000070
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0x4
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000007
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x0
+
+//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0x77777777
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 0
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0x70000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1c
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x07000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x18
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00070000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x10
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x00007000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0xc
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0x8
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00000070
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0x4
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000007
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x0
+
+//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0x77777777
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 0
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0x70000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1c
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x07000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x18
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00070000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x10
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x00007000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0xc
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0x8
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00000070
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0x4
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000007
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x0
+
+//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0x77777777
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 0
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0x70000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1c
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x07000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x18
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00070000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x10
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x00007000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0xc
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0x8
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00000070
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0x4
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000007
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x0
+
+//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0x77777777
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 0
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0x70000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1c
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x07000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x18
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00070000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x10
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x00007000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0xc
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0x8
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00000070
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0x4
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000007
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x0
+
+//// Register REO_R0_TIMESTAMP ////
+
+#define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024)
+#define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024)
+#define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff
+#define HWIO_REO_R0_TIMESTAMP_SHFT 0
+#define HWIO_REO_R0_TIMESTAMP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK)
+#define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask)
+#define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val)
+#define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff
+#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0
+
+//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 ////
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0x77777777
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x70000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x1c
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x07000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x18
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00700000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0x14
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00070000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0x10
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00007000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0xc
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x00000700
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x8
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000070
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x4
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0
+
+//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 ////
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0x77777777
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x70000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0x1c
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x07000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0x18
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00700000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x14
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x00070000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x10
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00007000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0xc
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000700
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x8
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0x00000070
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 0x4
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0x00000007
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0x0
+
+//// Register REO_R0_IDLE_REQ_CTRL ////
+
+#define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003
+#define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1
+
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_ID ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_MISC ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x003fffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000008c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000008c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000090)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000090)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_ID ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000094)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000094)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_STATUS ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000098)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000098)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_MISC ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000009c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000009c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x003fffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000000dc)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000000dc)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x000000e4)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x000000e4)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x000000e8)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x000000e8)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_ID ////
+
+#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x000000ec)
+#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x000000ec)
+#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_STATUS ////
+
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000000f0)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000000f0)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_MISC ////
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000000f4)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000000f4)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x003fffff
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x00000134)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x00000134)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x0000013c)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x0000013c)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x00000140)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x00000140)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_ID ////
+
+#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x00000144)
+#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x00000144)
+#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_STATUS ////
+
+#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x00000148)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x00000148)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_MISC ////
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x0000014c)
+#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x0000014c)
+#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x003fffff
+#define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000184)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000184)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000188)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000188)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000018c)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000018c)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) (x+0x00000194)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) (x+0x00000194)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000198)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000198)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_ID ////
+
+#define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) (x+0x0000019c)
+#define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) (x+0x0000019c)
+#define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO1_RING_ID_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO1_RING_ID_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_STATUS ////
+
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) (x+0x000001a0)
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) (x+0x000001a0)
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_MISC ////
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) (x+0x000001a4)
+#define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) (x+0x000001a4)
+#define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x003fffff
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MISC_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000001e4)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000001e4)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8)
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8)
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x000001ec)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x000001ec)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x000001f0)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x000001f0)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_ID ////
+
+#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x000001f4)
+#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x000001f4)
+#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x000001f8)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x000001f8)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_MISC ////
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x000001fc)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x000001fc)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x03ffffff
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000200)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000200)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000204)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000204)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000210)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000210)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000214)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000214)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000218)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000218)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x0000023c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x0000023c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x00000244)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x00000244)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x00000248)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x00000248)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_ID ////
+
+#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x0000024c)
+#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x0000024c)
+#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x00000250)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x00000250)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_MISC ////
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x00000254)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x00000254)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x03ffffff
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x00000294)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x00000294)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x0000029c)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x0000029c)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002a0)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002a0)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_ID ////
+
+#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002a4)
+#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002a4)
+#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x000002a8)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x000002a8)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_MISC ////
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x000002ac)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x000002ac)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x03ffffff
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x000002ec)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x000002ec)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x000002f4)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x000002f4)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x000002f8)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x000002f8)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_ID ////
+
+#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x000002fc)
+#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x000002fc)
+#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000300)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000300)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_MISC ////
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x00000304)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x00000304)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x03ffffff
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x00000344)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x00000344)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003fc)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003fc)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x00000400)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x00000400)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_ID ////
+
+#define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x00000404)
+#define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x00000404)
+#define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x00000408)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x00000408)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_MISC ////
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x0000040c)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x0000040c)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x03ffffff
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x0000044c)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x0000044c)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x00000454)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x00000454)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000458)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000458)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_ID ////
+
+#define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x0000045c)
+#define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x0000045c)
+#define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000460)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000460)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_MISC ////
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x00000464)
+#define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x00000464)
+#define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x03ffffff
+#define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000049c)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000049c)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004a0)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004a0)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x000004a4)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x000004a4)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000004ac)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000004ac)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000004b0)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000004b0)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_ID ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x000004b4)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x000004b4)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_STATUS ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x000004b8)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x000004b8)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_MISC ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x000004bc)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x000004bc)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x03ffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000004fc)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000004fc)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000504)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000504)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x00000508)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x00000508)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_ID ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x0000050c)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x0000050c)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_STATUS ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x00000510)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x00000510)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_MISC ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x00000514)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x00000514)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x03ffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000518)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000518)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000051c)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000051c)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000528)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000528)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000052c)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000052c)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000530)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000530)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000054c)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000054c)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000550)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000550)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x00000554)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x00000554)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000558)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000558)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register REO_R0_WATCHDOG_TIMEOUT ////
+
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000055c)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000055c)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00003fff
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \
+ out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x00003000
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 0xc
+
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0
+
+//// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 ////
+
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000560)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000560)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0
+
+//// Register REO_R0_AGING_THRESHOLD_IX_0 ////
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x00000564)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x00000564)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0
+
+//// Register REO_R0_AGING_THRESHOLD_IX_1 ////
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000568)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000568)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0
+
+//// Register REO_R0_AGING_THRESHOLD_IX_2 ////
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x0000056c)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x0000056c)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0
+
+//// Register REO_R0_AGING_THRESHOLD_IX_3 ////
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000570)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000570)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x00000574)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x00000574)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000578)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000578)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x0000057c)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x0000057c)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000580)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000580)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x00000584)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x00000584)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000588)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000588)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x0000058c)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x0000058c)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000590)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000590)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x00000594)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x00000594)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000598)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000598)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x0000059c)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x0000059c)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x000005a0)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x000005a0)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x000005a4)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x000005a4)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x000005a8)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x000005a8)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x000005ac)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x000005ac)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x000005b0)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x000005b0)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_AGING_NUM_QUEUES_IX_0 ////
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x000005b4)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x000005b4)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0
+
+//// Register REO_R0_AGING_NUM_QUEUES_IX_1 ////
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x000005b8)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x000005b8)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0
+
+//// Register REO_R0_AGING_NUM_QUEUES_IX_2 ////
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x000005bc)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x000005bc)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0
+
+//// Register REO_R0_AGING_NUM_QUEUES_IX_3 ////
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x000005c0)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x000005c0)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0
+
+//// Register REO_R0_AGING_TIMESTAMP_IX_0 ////
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x000005c4)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x000005c4)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0
+
+//// Register REO_R0_AGING_TIMESTAMP_IX_1 ////
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x000005c8)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x000005c8)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0
+
+//// Register REO_R0_AGING_TIMESTAMP_IX_2 ////
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x000005cc)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x000005cc)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0
+
+//// Register REO_R0_AGING_TIMESTAMP_IX_3 ////
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x000005d0)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x000005d0)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0
+
+//// Register REO_R0_AGING_CONTROL ////
+
+#define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x000005d4)
+#define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x000005d4)
+#define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f
+#define HWIO_REO_R0_AGING_CONTROL_SHFT 0
+#define HWIO_REO_R0_AGING_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK)
+#define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask)
+#define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f
+#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_MISC_CTL ////
+
+#define HWIO_REO_R0_MISC_CTL_ADDR(x) (x+0x000005d8)
+#define HWIO_REO_R0_MISC_CTL_PHYS(x) (x+0x000005d8)
+#define HWIO_REO_R0_MISC_CTL_RMSK 0x000fffff
+#define HWIO_REO_R0_MISC_CTL_SHFT 0
+#define HWIO_REO_R0_MISC_CTL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), HWIO_REO_R0_MISC_CTL_RMSK)
+#define HWIO_REO_R0_MISC_CTL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), mask)
+#define HWIO_REO_R0_MISC_CTL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_MISC_CTL_ADDR(x), val)
+#define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x), mask, val, HWIO_REO_R0_MISC_CTL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x000e0000
+#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 0x11
+
+#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x00010000
+#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 0x10
+
+#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK 0x00008000
+#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT 0xf
+
+#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x00007fff
+#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0x0
+
+//// Register REO_R0_HIGH_MEMORY_THRESHOLD ////
+
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x000005dc)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x000005dc)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \
+ out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_AC_BUFFERS_USED_IX_0 ////
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x000005e0)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x000005e0)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0
+
+//// Register REO_R0_AC_BUFFERS_USED_IX_1 ////
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x000005e4)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x000005e4)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0
+
+//// Register REO_R0_AC_BUFFERS_USED_IX_2 ////
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x000005e8)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x000005e8)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0
+
+//// Register REO_R0_AC_BUFFERS_USED_IX_3 ////
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x000005ec)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x000005ec)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x000005f0)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x000005f0)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x000005f4)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x000005f4)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x000005f8)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x000005f8)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005fc)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005fc)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x00000600)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x00000600)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x00000604)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x00000604)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x00000608)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x00000608)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x0000060c)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x0000060c)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x00000610)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x00000610)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x00000614)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x00000614)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x00000618)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x00000618)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x0000061c)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x0000061c)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x00000620)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x00000620)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x00000624)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x00000624)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x00000628)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x00000628)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x0000062c)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x0000062c)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_INFO ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x00000630)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x00000630)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \
+ out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0
+
+//// Register REO_R0_GXI_TESTBUS_LOWER ////
+
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000654)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000654)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0
+
+//// Register REO_R0_GXI_TESTBUS_UPPER ////
+
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000658)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000658)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0
+
+//// Register REO_R0_GXI_SM_STATES_IX_0 ////
+
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000065c)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000065c)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9
+
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4
+
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0
+
+//// Register REO_R0_GXI_END_OF_TEST_CHECK ////
+
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000660)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000660)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+//// Register REO_R0_GXI_CLOCK_GATE_DISABLE ////
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000664)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000664)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_ERR_INTS ////
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x00000668)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x00000668)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_ERR_STATS ////
+
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x0000066c)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x0000066c)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10
+
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8
+
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_DEFAULT_CONTROL ////
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000670)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000670)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_REDUCED_CONTROL ////
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000674)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000674)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_MISC_CONTROL ////
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000678)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000678)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_WDOG_CONTROL ////
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x0000067c)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x0000067c)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_WDOG_STATUS ////
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000680)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000680)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_IDLE_COUNTERS ////
+
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000684)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000684)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10
+
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_RD_LATENCY_CTRL ////
+
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x00000688)
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x00000688)
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11
+
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10
+
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff
+#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_WR_LATENCY_CTRL ////
+
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x0000068c)
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x0000068c)
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11
+
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10
+
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff
+#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 ////
+
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000690)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000690)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 ////
+
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x00000694)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x00000694)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 ////
+
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000698)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000698)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 ////
+
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x0000069c)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x0000069c)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0
+
+//// Register REO_R0_GXI_GXI_AXI_OUTSANDING_CTL ////
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000006a0)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000006a0)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7
+
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f
+#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0
+
+//// Register REO_R0_CACHE_CTL_CONFIG ////
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x000006a4)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x000006a4)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \
+ out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 0x18
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x00800000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 0x17
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00400000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x16
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00200000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x15
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00100000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x14
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00080000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x13
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00040000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x12
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00020000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x11
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x9
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000001ff
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0
+
+//// Register REO_R0_CACHE_CTL_CONTROL ////
+
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x000006a8)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x000006a8)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000003
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x00000002
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 0x1
+
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0
+
+//// Register REO_R0_CACHE_CTL_CONFIG_SET ////
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) (x+0x000006ac)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) (x+0x000006ac)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x01ffffff
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_SHFT 0
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, val) \
+ out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), val)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_BMSK 0x01ffffff
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CONFIG_SET_SHFT 0x0
+
+//// Register REO_R0_CACHE_CTL_SET_SIZE ////
+
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) (x+0x000006b0)
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) (x+0x000006b0)
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x000001ff
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SHFT 0
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK)
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask)
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, val) \
+ out_dword( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), val)
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x000001ff
+#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0x0
+
+//// Register REO_R0_CLK_GATE_CTRL ////
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x000006b4)
+#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x000006b4)
+#define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff
+#define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0
+#define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK)
+#define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask)
+#define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \
+ out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val)
+#define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_BMSK 0x00001000
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_SHFT 0xc
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_BMSK 0x00000800
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_SHFT 0xb
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400
+#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0
+
+//// Register REO_R0_EVENTMASK_IX_0 ////
+
+#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x000006b8)
+#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x000006b8)
+#define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0
+#define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK)
+#define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask)
+#define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0
+
+//// Register REO_R0_EVENTMASK_IX_1 ////
+
+#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x000006bc)
+#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x000006bc)
+#define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0
+#define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK)
+#define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask)
+#define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0
+
+//// Register REO_R0_EVENTMASK_IX_2 ////
+
+#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x000006c0)
+#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x000006c0)
+#define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0
+#define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK)
+#define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask)
+#define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0
+
+//// Register REO_R0_EVENTMASK_IX_3 ////
+
+#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x000006c4)
+#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x000006c4)
+#define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0
+#define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK)
+#define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask)
+#define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0
+
+//// Register REO_R1_MISC_DEBUG_CTRL ////
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0xffffffff
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \
+ out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_BMSK 0x80000000
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_SHFT 0x1f
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x40000000
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 0x1e
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0
+
+//// Register REO_R1_MISC_PERF_DEBUG_CTRL ////
+
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \
+ out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc
+
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_CONTROL ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x00000fff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000800
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0xb
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000400
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0xa
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000200
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x9
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x000001ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_STM ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x0007ffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0007fc00
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0xa
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000003ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST1 ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) (x+0x00002024)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) (x+0x00002024)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x0007ffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x0007fc00
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 0xa
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x000003ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST2 ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) (x+0x00002028)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) (x+0x00002028)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x0007ffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x0007fc00
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 0xa
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x000003ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST3 ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) (x+0x0000202c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) (x+0x0000202c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x0007ffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x0007fc00
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 0xa
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x000003ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) (x+0x00002030)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) (x+0x00002030)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) (x+0x00002034)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) (x+0x00002034)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) (x+0x00002038)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) (x+0x00002038)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0x000fffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0x000ffc00
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 0xa
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x000003ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK ////
+
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x0000203c)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x0000203c)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1 ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x) (x+0x00002040)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_PHYS(x) (x+0x00002040)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK 0x000007ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_BMSK 0x000007f8
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_BACKUP_SHFT 0x3
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_BMSK 0x00000004
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_WITHOUT_INVALIDATE_SHFT 0x2
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_BMSK 0x00000002
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_ENTIRE_CACHE_SHFT 0x1
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_BMSK 0x00000001
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG1_FLUSH_REQ_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2 ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x) (x+0x00002044)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_PHYS(x) (x+0x00002044)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_BMSK 0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG2_FLUSH_ADDR_31_0_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3 ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x) (x+0x00002048)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_PHYS(x) (x+0x00002048)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK 0x000000ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_BMSK 0x000000ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_CONFIG3_FLUSH_ADDR_39_32_SHFT 0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x) (x+0x0000204c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_PHYS(x) (x+0x0000204c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK 0x3fffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_SHFT 0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUT(x, val) \
+ out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_BMSK 0x3fc00000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_BACKUP_SHFT 0x16
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_BMSK 0x003ff000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_COUNT_SHFT 0xc
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_BMSK 0x00000800
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HW_IF_BUSY_SHFT 0xb
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_BMSK 0x00000600
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_ERROR_SHFT 0x9
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_BMSK 0x000001e0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_CLIENT_ID_SHFT 0x5
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_BMSK 0x0000001c
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_DESC_TYPE_SHFT 0x2
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_BMSK 0x00000002
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_STATUS_HIT_SHFT 0x1
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_BMSK 0x00000001
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_FLUSH_STATUS_FLUSH_DONE_SHFT 0x0
+
+//// Register REO_R1_END_OF_TEST_CHECK ////
+
+#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002050)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002050)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001
+#define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0
+#define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \
+ out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+//// Register REO_R1_SM_ALL_IDLE ////
+
+#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x00002054)
+#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x00002054)
+#define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007
+#define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0
+#define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK)
+#define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask)
+#define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \
+ out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val)
+#define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004
+#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2
+
+#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002
+#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1
+
+#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001
+#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0
+
+//// Register REO_R1_TESTBUS_CTRL ////
+
+#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002058)
+#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002058)
+#define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f
+#define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0
+#define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK)
+#define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask)
+#define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \
+ out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val)
+#define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f
+#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0
+
+//// Register REO_R1_TESTBUS_LOWER ////
+
+#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x0000205c)
+#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x0000205c)
+#define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff
+#define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0
+#define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK)
+#define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask)
+#define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \
+ out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0
+
+//// Register REO_R1_TESTBUS_HIGHER ////
+
+#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002060)
+#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002060)
+#define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff
+#define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0
+#define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK)
+#define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask)
+#define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \
+ out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val)
+#define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff
+#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0
+
+//// Register REO_R1_SM_STATES_IX_0 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002064)
+#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002064)
+#define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0
+#define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask)
+#define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0
+
+//// Register REO_R1_SM_STATES_IX_1 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002068)
+#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002068)
+#define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0
+#define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask)
+#define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \
+ out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0
+
+//// Register REO_R1_SM_STATES_IX_2 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x0000206c)
+#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x0000206c)
+#define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0
+#define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask)
+#define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \
+ out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0
+
+//// Register REO_R1_SM_STATES_IX_3 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002070)
+#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002070)
+#define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0
+#define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask)
+#define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \
+ out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0
+
+//// Register REO_R1_SM_STATES_IX_4 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x00002074)
+#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x00002074)
+#define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0
+#define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask)
+#define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \
+ out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0
+
+//// Register REO_R1_SM_STATES_IX_5 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002078)
+#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002078)
+#define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0
+#define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask)
+#define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \
+ out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0
+
+//// Register REO_R1_SM_STATES_IX_6 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x0000207c)
+#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x0000207c)
+#define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0
+#define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask)
+#define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \
+ out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0
+
+//// Register REO_R1_IDLE_STATES_IX_0 ////
+
+#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002080)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002080)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff
+#define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0
+#define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \
+ out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff
+#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0
+
+//// Register REO_R1_INVALID_APB_ACCESS ////
+
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x00002084)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x00002084)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff
+#define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0
+#define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \
+ in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \
+ out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11
+
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0
+
+//// Register REO_R2_RXDMA2REO0_RING_HP ////
+
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_RXDMA2REO0_RING_TP ////
+
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_WBM2REO_LINK_RING_HP ////
+
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003008)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003008)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_WBM2REO_LINK_RING_TP ////
+
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000300c)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000300c)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO_CMD_RING_HP ////
+
+#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003010)
+#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003010)
+#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff
+#define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK)
+#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO_CMD_RING_TP ////
+
+#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003014)
+#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003014)
+#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff
+#define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK)
+#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_SW2REO_RING_HP ////
+
+#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003018)
+#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003018)
+#define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff
+#define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0
+#define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK)
+#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_SW2REO_RING_TP ////
+
+#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000301c)
+#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000301c)
+#define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff
+#define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0
+#define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK)
+#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_SW2REO1_RING_HP ////
+
+#define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) (x+0x00003020)
+#define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) (x+0x00003020)
+#define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0x0000ffff
+#define HWIO_REO_R2_SW2REO1_RING_HP_SHFT 0
+#define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_HP_RMSK)
+#define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_SW2REO1_RING_TP ////
+
+#define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) (x+0x00003024)
+#define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) (x+0x00003024)
+#define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0x0000ffff
+#define HWIO_REO_R2_SW2REO1_RING_TP_SHFT 0
+#define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_TP_RMSK)
+#define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2SW1_RING_HP ////
+
+#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003028)
+#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003028)
+#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2SW1_RING_TP ////
+
+#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x0000302c)
+#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x0000302c)
+#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2SW2_RING_HP ////
+
+#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003030)
+#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003030)
+#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2SW2_RING_TP ////
+
+#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x00003034)
+#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x00003034)
+#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2SW3_RING_HP ////
+
+#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003038)
+#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003038)
+#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2SW3_RING_TP ////
+
+#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x0000303c)
+#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x0000303c)
+#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2SW4_RING_HP ////
+
+#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003040)
+#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003040)
+#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2SW4_RING_TP ////
+
+#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x00003044)
+#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x00003044)
+#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2TCL_RING_HP ////
+
+#define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003058)
+#define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003058)
+#define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2TCL_RING_TP ////
+
+#define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x0000305c)
+#define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x0000305c)
+#define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2FW_RING_HP ////
+
+#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003060)
+#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003060)
+#define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO2FW_RING_TP ////
+
+#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x00003064)
+#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x00003064)
+#define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x000fffff
+#define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO_RELEASE_RING_HP ////
+
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003068)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003068)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO_RELEASE_RING_TP ////
+
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x0000306c)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x0000306c)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register REO_R2_REO_STATUS_RING_HP ////
+
+#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003070)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003070)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff
+#define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0
+#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register REO_R2_REO_STATUS_RING_TP ////
+
+#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x00003074)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x00003074)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff
+#define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0
+#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \
+ out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+
+#endif
+
diff --git a/hw/qca5018/reo_unblock_cache.h b/hw/qca5018/reo_unblock_cache.h
new file mode 100644
index 0000000..4853c1a
--- /dev/null
+++ b/hw/qca5018/reo_unblock_cache.h
@@ -0,0 +1,312 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_UNBLOCK_CACHE_H_
+#define _REO_UNBLOCK_CACHE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_reo_cmd_header cmd_header;
+// 1 unblock_type[0], cache_block_resource_index[2:1], reserved_1a[31:3]
+// 2 reserved_2a[31:0]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9
+
+struct reo_unblock_cache {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t unblock_type : 1, //[0]
+ cache_block_resource_index : 2, //[2:1]
+ reserved_1a : 29; //[31:3]
+ uint32_t reserved_2a : 32; //[31:0]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Details for command execution tracking purposes.
+
+unblock_type
+
+ Unblock type
+
+
+
+ <enum 0 unblock_resource_index> Unblock a block
+ resource, whose index is given in field
+ 'cache_block_resource_index'.
+
+ If the indicated blocking resource is not in use (=> not
+ blocking an address at the moment), the command status will
+ indicate an error.
+
+
+
+ <enum 1 unblock_cache> The entire cache usage is
+ unblocked.
+
+ If the entire cache is not in a blocked mode at the
+ moment this command is received, the command status will
+ indicate an error.
+
+ Note that unlocking the entire cache has no changes to
+ the current settings of the blocking resource settings
+
+
+
+ <legal all>
+
+cache_block_resource_index
+
+ Field not valid when field Unblock_type is set to
+ unblock_cache.
+
+
+
+ Indicates which of the four blocking resources in REO
+ should be released from blocking a (descriptor) address.
+
+ <legal all>
+
+reserved_1a
+
+ <legal 0>
+
+reserved_2a
+
+ <legal 0>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
+
+
+/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER
+
+ Consumer: REO/SW/DEBUG
+
+ Producer: SW
+
+
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statusses
+
+
+
+
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ <enum 0 NoStatus> REO does not need to generate a status
+ TLV for the execution of this command
+
+ <enum 1 StatusRequired> REO shall generate a status TLV
+ for the execution of this command
+
+
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+/* Description REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE
+
+ Unblock type
+
+
+
+ <enum 0 unblock_resource_index> Unblock a block
+ resource, whose index is given in field
+ 'cache_block_resource_index'.
+
+ If the indicated blocking resource is not in use (=> not
+ blocking an address at the moment), the command status will
+ indicate an error.
+
+
+
+ <enum 1 unblock_cache> The entire cache usage is
+ unblocked.
+
+ If the entire cache is not in a blocked mode at the
+ moment this command is received, the command status will
+ indicate an error.
+
+ Note that unlocking the entire cache has no changes to
+ the current settings of the blocking resource settings
+
+
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0
+#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001
+
+/* Description REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX
+
+ Field not valid when field Unblock_type is set to
+ unblock_cache.
+
+
+
+ Indicates which of the four blocking resources in REO
+ should be released from blocking a (descriptor) address.
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1
+#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006
+
+/* Description REO_UNBLOCK_CACHE_1_RESERVED_1A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3
+#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8
+
+/* Description REO_UNBLOCK_CACHE_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0
+#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0
+#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0
+#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0
+#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0
+#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0
+#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0
+#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff
+
+
+#endif // _REO_UNBLOCK_CACHE_H_
diff --git a/hw/qca5018/reo_unblock_cache_status.h b/hw/qca5018/reo_unblock_cache_status.h
new file mode 100644
index 0000000..321a7e8
--- /dev/null
+++ b/hw/qca5018/reo_unblock_cache_status.h
@@ -0,0 +1,616 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_UNBLOCK_CACHE_STATUS_H_
+#define _REO_UNBLOCK_CACHE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct uniform_reo_status_header status_header;
+// 2 error_detected[0], unblock_type[1], reserved_2a[31:2]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+// 9 reserved_9a[31:0]
+// 10 reserved_10a[31:0]
+// 11 reserved_11a[31:0]
+// 12 reserved_12a[31:0]
+// 13 reserved_13a[31:0]
+// 14 reserved_14a[31:0]
+// 15 reserved_15a[31:0]
+// 16 reserved_16a[31:0]
+// 17 reserved_17a[31:0]
+// 18 reserved_18a[31:0]
+// 19 reserved_19a[31:0]
+// 20 reserved_20a[31:0]
+// 21 reserved_21a[31:0]
+// 22 reserved_22a[31:0]
+// 23 reserved_23a[31:0]
+// 24 reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25
+
+struct reo_unblock_cache_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t error_detected : 1, //[0]
+ unblock_type : 1, //[1]
+ reserved_2a : 30; //[31:2]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+ uint32_t reserved_9a : 32; //[31:0]
+ uint32_t reserved_10a : 32; //[31:0]
+ uint32_t reserved_11a : 32; //[31:0]
+ uint32_t reserved_12a : 32; //[31:0]
+ uint32_t reserved_13a : 32; //[31:0]
+ uint32_t reserved_14a : 32; //[31:0]
+ uint32_t reserved_15a : 32; //[31:0]
+ uint32_t reserved_16a : 32; //[31:0]
+ uint32_t reserved_17a : 32; //[31:0]
+ uint32_t reserved_18a : 32; //[31:0]
+ uint32_t reserved_19a : 32; //[31:0]
+ uint32_t reserved_20a : 32; //[31:0]
+ uint32_t reserved_21a : 32; //[31:0]
+ uint32_t reserved_22a : 32; //[31:0]
+ uint32_t reserved_23a : 32; //[31:0]
+ uint32_t reserved_24a : 28, //[27:0]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+ Consumer: SW
+
+ Producer: REO
+
+
+
+ Details that can link this status with the original
+ command. It also contains info on how long REO took to
+ execute this command.
+
+error_detected
+
+ Status for blocking resource handling
+
+
+
+ 0: No error has been detected while executing this
+ command
+
+ 1: The blocking resource was not in use, and therefor it
+ could not be 'unblocked'
+
+unblock_type
+
+ Reference to the type of Unblock command type...
+
+
+
+ <enum 0 unblock_resource_index> Unblock a blocking
+ resource
+
+
+
+ <enum 1 unblock_cache> The entire cache usage is
+ unblock.
+
+
+
+ <legal all>
+
+reserved_2a
+
+ <legal 0>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+
+reserved_9a
+
+ <legal 0>
+
+reserved_10a
+
+ <legal 0>
+
+reserved_11a
+
+ <legal 0>
+
+reserved_12a
+
+ <legal 0>
+
+reserved_13a
+
+ <legal 0>
+
+reserved_14a
+
+ <legal 0>
+
+reserved_15a
+
+ <legal 0>
+
+reserved_16a
+
+ <legal 0>
+
+reserved_17a
+
+ <legal 0>
+
+reserved_18a
+
+ <legal 0>
+
+reserved_19a
+
+ <legal 0>
+
+reserved_20a
+
+ <legal 0>
+
+reserved_21a
+
+ <legal 0>
+
+reserved_22a
+
+ <legal 0>
+
+reserved_23a
+
+ <legal 0>
+
+reserved_24a
+
+ <legal 0>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
+
+
+/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+/* Description REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED
+
+ Status for blocking resource handling
+
+
+
+ 0: No error has been detected while executing this
+ command
+
+ 1: The blocking resource was not in use, and therefor it
+ could not be 'unblocked'
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001
+
+/* Description REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE
+
+ Reference to the type of Unblock command type...
+
+
+
+ <enum 0 unblock_resource_index> Unblock a blocking
+ resource
+
+
+
+ <enum 1 unblock_cache> The entire cache usage is
+ unblock.
+
+
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1
+#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002
+
+/* Description REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2
+#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc
+
+/* Description REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A
+
+ <legal 0>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0
+#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_UNBLOCK_CACHE_STATUS_H_
diff --git a/hw/qca5018/reo_update_rx_reo_queue.h b/hw/qca5018/reo_update_rx_reo_queue.h
new file mode 100644
index 0000000..1981a45
--- /dev/null
+++ b/hw/qca5018/reo_update_rx_reo_queue.h
@@ -0,0 +1,1670 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_H_
+#define _REO_UPDATE_RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_reo_cmd_header cmd_header;
+// 1 rx_reo_queue_desc_addr_31_0[31:0]
+// 2 rx_reo_queue_desc_addr_39_32[7:0], update_receive_queue_number[8], update_vld[9], update_associated_link_descriptor_counter[10], update_disable_duplicate_detection[11], update_soft_reorder_enable[12], update_ac[13], update_bar[14], update_rty[15], update_chk_2k_mode[16], update_oor_mode[17], update_ba_window_size[18], update_pn_check_needed[19], update_pn_shall_be_even[20], update_pn_shall_be_uneven[21], update_pn_handling_enable[22], update_pn_size[23], update_ignore_ampdu_flag[24], update_svld[25], update_ssn[26], update_seq_2k_error_detected_flag[27], update_pn_error_detected_flag[28], update_pn_valid[29], update_pn[30], clear_stat_counters[31]
+// 3 receive_queue_number[15:0], vld[16], associated_link_descriptor_counter[18:17], disable_duplicate_detection[19], soft_reorder_enable[20], ac[22:21], bar[23], rty[24], chk_2k_mode[25], oor_mode[26], pn_check_needed[27], pn_shall_be_even[28], pn_shall_be_uneven[29], pn_handling_enable[30], ignore_ampdu_flag[31]
+// 4 ba_window_size[7:0], pn_size[9:8], svld[10], ssn[22:11], seq_2k_error_detected_flag[23], pn_error_detected_flag[24], pn_valid[25], flush_from_cache[26], reserved_4a[31:27]
+// 5 pn_31_0[31:0]
+// 6 pn_63_32[31:0]
+// 7 pn_95_64[31:0]
+// 8 pn_127_96[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9
+
+struct reo_update_rx_reo_queue {
+ struct uniform_reo_cmd_header cmd_header;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
+ update_receive_queue_number : 1, //[8]
+ update_vld : 1, //[9]
+ update_associated_link_descriptor_counter: 1, //[10]
+ update_disable_duplicate_detection: 1, //[11]
+ update_soft_reorder_enable : 1, //[12]
+ update_ac : 1, //[13]
+ update_bar : 1, //[14]
+ update_rty : 1, //[15]
+ update_chk_2k_mode : 1, //[16]
+ update_oor_mode : 1, //[17]
+ update_ba_window_size : 1, //[18]
+ update_pn_check_needed : 1, //[19]
+ update_pn_shall_be_even : 1, //[20]
+ update_pn_shall_be_uneven : 1, //[21]
+ update_pn_handling_enable : 1, //[22]
+ update_pn_size : 1, //[23]
+ update_ignore_ampdu_flag : 1, //[24]
+ update_svld : 1, //[25]
+ update_ssn : 1, //[26]
+ update_seq_2k_error_detected_flag: 1, //[27]
+ update_pn_error_detected_flag : 1, //[28]
+ update_pn_valid : 1, //[29]
+ update_pn : 1, //[30]
+ clear_stat_counters : 1; //[31]
+ uint32_t receive_queue_number : 16, //[15:0]
+ vld : 1, //[16]
+ associated_link_descriptor_counter: 2, //[18:17]
+ disable_duplicate_detection : 1, //[19]
+ soft_reorder_enable : 1, //[20]
+ ac : 2, //[22:21]
+ bar : 1, //[23]
+ rty : 1, //[24]
+ chk_2k_mode : 1, //[25]
+ oor_mode : 1, //[26]
+ pn_check_needed : 1, //[27]
+ pn_shall_be_even : 1, //[28]
+ pn_shall_be_uneven : 1, //[29]
+ pn_handling_enable : 1, //[30]
+ ignore_ampdu_flag : 1; //[31]
+ uint32_t ba_window_size : 8, //[7:0]
+ pn_size : 2, //[9:8]
+ svld : 1, //[10]
+ ssn : 12, //[22:11]
+ seq_2k_error_detected_flag : 1, //[23]
+ pn_error_detected_flag : 1, //[24]
+ pn_valid : 1, //[25]
+ flush_from_cache : 1, //[26]
+ reserved_4a : 5; //[31:27]
+ uint32_t pn_31_0 : 32; //[31:0]
+ uint32_t pn_63_32 : 32; //[31:0]
+ uint32_t pn_95_64 : 32; //[31:0]
+ uint32_t pn_127_96 : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Details for command execution tracking purposes.
+
+rx_reo_queue_desc_addr_31_0
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor
+
+ <legal all>
+
+rx_reo_queue_desc_addr_39_32
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor
+
+ <legal all>
+
+update_receive_queue_number
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, receive_queue_number from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+update_vld
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ When clear, REO will NOT update the VLD bit setting. For
+ this setting, SW MUST set the Flush_from_cache bit in this
+ command.
+
+
+
+ When set, VLD from this command will be updated in the
+ descriptor.
+
+ <legal all>
+
+update_associated_link_descriptor_counter
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Associated_link_descriptor_counter from this
+ command will be updated in the descriptor.
+
+ <legal all>
+
+update_disable_duplicate_detection
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Disable_duplicate_detection from this command
+ will be updated in the descriptor.
+
+ <legal all>
+
+update_soft_reorder_enable
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Soft_reorder_enable from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+update_ac
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, AC from this command will be updated in the
+ descriptor.
+
+ <legal all>
+
+update_bar
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, BAR from this command will be updated in the
+ descriptor.
+
+ <legal all>
+
+update_rty
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, RTY from this command will be updated in the
+ descriptor.
+
+ <legal all>
+
+update_chk_2k_mode
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Chk_2k_mode from this command will be updated
+ in the descriptor.
+
+ <legal all>
+
+update_oor_mode
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, OOR_Mode from this command will be updated in
+ the descriptor.
+
+ <legal all>
+
+update_ba_window_size
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, BA_window_size from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+update_pn_check_needed
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_check_needed from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+update_pn_shall_be_even
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_shall_be_even from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+update_pn_shall_be_uneven
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_shall_be_uneven from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+update_pn_handling_enable
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_handling_enable from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+update_pn_size
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_size from this command will be updated in
+ the descriptor.
+
+ <legal all>
+
+update_ignore_ampdu_flag
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Ignore_ampdu_flag from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+update_svld
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Svld from this command will be updated in the
+ descriptor.
+
+ <legal all>
+
+update_ssn
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, SSN from this command will be updated in the
+ descriptor.
+
+ <legal all>
+
+update_seq_2k_error_detected_flag
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Seq_2k_error_detected_flag from this command
+ will be updated in the descriptor.
+
+ <legal all>
+
+update_pn_error_detected_flag
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, pn_error_detected_flag from this command will
+ be updated in the descriptor.
+
+ <legal all>
+
+update_pn_valid
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, pn_valid from this command will be updated in
+ the descriptor.
+
+ <legal all>
+
+update_pn
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, all pn_... fields from this command will be
+ updated in the descriptor.
+
+ <legal all>
+
+clear_stat_counters
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, REO will clear (=> set to 0) the following
+ stat counters in the REO_QUEUE_STRUCT
+
+
+
+ Last_rx_enqueue_TimeStamp
+
+ Last_rx_dequeue_Timestamp
+
+ Rx_bitmap (not a counter, but bitmap is cleared)
+
+ Timeout_count
+
+ Forward_due_to_bar_count
+
+ Duplicate_count
+
+ Frames_in_order_count
+
+ BAR_received_count
+
+ MPDU_Frames_processed_count
+
+ MSDU_Frames_processed_count
+
+ Total_processed_byte_count
+
+ Late_receive_MPDU_count
+
+ window_jump_2k
+
+ Hole_count
+
+
+
+ <legal all>
+
+receive_queue_number
+
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+vld
+
+ Field only valid when Update_VLD is set
+
+
+
+ For Update_VLD set and VLD clear, SW MUST set the
+ Flush_from_cache bit in this command.
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+associated_link_descriptor_counter
+
+ Field only valid when
+ Update_Associated_link_descriptor_counter is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+disable_duplicate_detection
+
+ Field only valid when Update_Disable_duplicate_detection
+ is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+soft_reorder_enable
+
+ Field only valid when Update_Soft_reorder_enable is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+ac
+
+ Field only valid when Update_AC is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+bar
+
+ Field only valid when Update_BAR is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+rty
+
+ Field only valid when Update_RTY is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+chk_2k_mode
+
+ Field only valid when Update_Chk_2k_Mode is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+oor_mode
+
+ Field only valid when Update_OOR_Mode is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_check_needed
+
+ Field only valid when Update_Pn_check_needed is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_shall_be_even
+
+ Field only valid when Update_Pn_shall_be_even is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_shall_be_uneven
+
+ Field only valid when Update_Pn_shall_be_uneven is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_handling_enable
+
+ Field only valid when Update_Pn_handling_enable is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+ignore_ampdu_flag
+
+ Field only valid when Update_Ignore_ampdu_flag is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+ba_window_size
+
+ Field only valid when Update_BA_window_size is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_size
+
+ Field only valid when Update_Pn_size is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+
+
+ <enum 0 pn_size_24>
+
+ <enum 1 pn_size_48>
+
+ <enum 2 pn_size_128>
+
+
+
+ <legal 0-2>
+
+svld
+
+ Field only valid when Update_Svld is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+ssn
+
+ Field only valid when Update_SSN is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+seq_2k_error_detected_flag
+
+ Field only valid when Update_Seq_2k_error_detected_flag
+ is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_error_detected_flag
+
+ Field only valid when Update_pn_error_detected_flag is
+ set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_valid
+
+ Field only valid when Update_pn_valid is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+flush_from_cache
+
+ When set, REO shall, after finishing the execution of
+ this command, flush the related descriptor from the cache.
+
+ <legal all>
+
+reserved_4a
+
+ <legal 0>
+
+pn_31_0
+
+ Field only valid when Update_Pn is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_63_32
+
+ Field only valid when Update_pn is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_95_64
+
+ Field only valid when Update_pn is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+
+pn_127_96
+
+ Field only valid when Update_pn is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
+
+
+/* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER
+
+ Consumer: REO/SW/DEBUG
+
+ Producer: SW
+
+
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statusses
+
+
+
+
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ <enum 0 NoStatus> REO does not need to generate a status
+ TLV for the execution of this command
+
+ <enum 1 StatusRequired> REO shall generate a status TLV
+ for the execution of this command
+
+
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, receive_queue_number from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ When clear, REO will NOT update the VLD bit setting. For
+ this setting, SW MUST set the Flush_from_cache bit in this
+ command.
+
+
+
+ When set, VLD from this command will be updated in the
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB 9
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK 0x00000200
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Associated_link_descriptor_counter from this
+ command will be updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Disable_duplicate_detection from this command
+ will be updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Soft_reorder_enable from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB 12
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, AC from this command will be updated in the
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB 13
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK 0x00002000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, BAR from this command will be updated in the
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB 14
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK 0x00004000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, RTY from this command will be updated in the
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB 15
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK 0x00008000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Chk_2k_mode from this command will be updated
+ in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK 0x00010000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, OOR_Mode from this command will be updated in
+ the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK 0x00020000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, BA_window_size from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB 18
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_check_needed from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB 19
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_shall_be_even from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB 20
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_shall_be_uneven from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_handling_enable from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB 22
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Pn_size from this command will be updated in
+ the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB 23
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK 0x00800000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Ignore_ampdu_flag from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB 24
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Svld from this command will be updated in the
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK 0x02000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, SSN from this command will be updated in the
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK 0x04000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, Seq_2k_error_detected_flag from this command
+ will be updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, pn_error_detected_flag from this command will
+ be updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, pn_valid from this command will be updated in
+ the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB 29
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK 0x20000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, all pn_... fields from this command will be
+ updated in the descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB 30
+#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK 0x40000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS
+
+ Consumer: REO
+
+ Producer: SW
+
+ When set, REO will clear (=> set to 0) the following
+ stat counters in the REO_QUEUE_STRUCT
+
+
+
+ Last_rx_enqueue_TimeStamp
+
+ Last_rx_dequeue_Timestamp
+
+ Rx_bitmap (not a counter, but bitmap is cleared)
+
+ Timeout_count
+
+ Forward_due_to_bar_count
+
+ Duplicate_count
+
+ Frames_in_order_count
+
+ BAR_received_count
+
+ MPDU_Frames_processed_count
+
+ MSDU_Frames_processed_count
+
+ Total_processed_byte_count
+
+ Late_receive_MPDU_count
+
+ window_jump_2k
+
+ Hole_count
+
+
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_LSB 31
+#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_MASK 0x80000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER
+
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_VLD
+
+ Field only valid when Update_VLD is set
+
+
+
+ For Update_VLD set and VLD clear, SW MUST set the
+ Flush_from_cache bit in this command.
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK 0x00010000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
+
+ Field only valid when
+ Update_Associated_link_descriptor_counter is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17
+#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION
+
+ Field only valid when Update_Disable_duplicate_detection
+ is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB 19
+#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE
+
+ Field only valid when Update_Soft_reorder_enable is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB 20
+#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK 0x00100000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_AC
+
+ Field only valid when Update_AC is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB 21
+#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK 0x00600000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_BAR
+
+ Field only valid when Update_BAR is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB 23
+#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK 0x00800000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_RTY
+
+ Field only valid when Update_RTY is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB 24
+#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK 0x01000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE
+
+ Field only valid when Update_Chk_2k_Mode is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK 0x02000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE
+
+ Field only valid when Update_OOR_Mode is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK 0x04000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED
+
+ Field only valid when Update_Pn_check_needed is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK 0x08000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN
+
+ Field only valid when Update_Pn_shall_be_even is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK 0x10000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN
+
+ Field only valid when Update_Pn_shall_be_uneven is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB 29
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK 0x20000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE
+
+ Field only valid when Update_Pn_handling_enable is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB 30
+#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK 0x40000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG
+
+ Field only valid when Update_Ignore_ampdu_flag is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB 31
+#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK 0x80000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE
+
+ Field only valid when Update_BA_window_size is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK 0x000000ff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE
+
+ Field only valid when Update_Pn_size is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+
+
+ <enum 0 pn_size_24>
+
+ <enum 1 pn_size_48>
+
+ <enum 2 pn_size_128>
+
+
+
+ <legal 0-2>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB 8
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK 0x00000300
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_SVLD
+
+ Field only valid when Update_Svld is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB 10
+#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK 0x00000400
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_SSN
+
+ Field only valid when Update_SSN is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB 11
+#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK 0x007ff800
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG
+
+ Field only valid when Update_Seq_2k_error_detected_flag
+ is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23
+#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG
+
+ Field only valid when Update_pn_error_detected_flag is
+ set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB 24
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK 0x01000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_PN_VALID
+
+ Field only valid when Update_pn_valid is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB 25
+#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK 0x02000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE
+
+ When set, REO shall, after finishing the execution of
+ this command, flush the related descriptor from the cache.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_MASK 0x04000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB 27
+#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK 0xf8000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_5_PN_31_0
+
+ Field only valid when Update_Pn is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET 0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_6_PN_63_32
+
+ Field only valid when Update_pn is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET 0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_7_PN_95_64
+
+ Field only valid when Update_pn is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET 0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_8_PN_127_96
+
+ Field only valid when Update_pn is set
+
+
+
+ Field value to be copied over into the RX_REO_QUEUE
+ descriptor.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET 0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK 0xffffffff
+
+
+#endif // _REO_UPDATE_RX_REO_QUEUE_H_
diff --git a/hw/qca5018/reo_update_rx_reo_queue_status.h b/hw/qca5018/reo_update_rx_reo_queue_status.h
new file mode 100644
index 0000000..868548e
--- /dev/null
+++ b/hw/qca5018/reo_update_rx_reo_queue_status.h
@@ -0,0 +1,546 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct uniform_reo_status_header status_header;
+// 2 reserved_2a[31:0]
+// 3 reserved_3a[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[31:0]
+// 8 reserved_8a[31:0]
+// 9 reserved_9a[31:0]
+// 10 reserved_10a[31:0]
+// 11 reserved_11a[31:0]
+// 12 reserved_12a[31:0]
+// 13 reserved_13a[31:0]
+// 14 reserved_14a[31:0]
+// 15 reserved_15a[31:0]
+// 16 reserved_16a[31:0]
+// 17 reserved_17a[31:0]
+// 18 reserved_18a[31:0]
+// 19 reserved_19a[31:0]
+// 20 reserved_20a[31:0]
+// 21 reserved_21a[31:0]
+// 22 reserved_22a[31:0]
+// 23 reserved_23a[31:0]
+// 24 reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25
+
+struct reo_update_rx_reo_queue_status {
+ struct uniform_reo_status_header status_header;
+ uint32_t reserved_2a : 32; //[31:0]
+ uint32_t reserved_3a : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 32; //[31:0]
+ uint32_t reserved_8a : 32; //[31:0]
+ uint32_t reserved_9a : 32; //[31:0]
+ uint32_t reserved_10a : 32; //[31:0]
+ uint32_t reserved_11a : 32; //[31:0]
+ uint32_t reserved_12a : 32; //[31:0]
+ uint32_t reserved_13a : 32; //[31:0]
+ uint32_t reserved_14a : 32; //[31:0]
+ uint32_t reserved_15a : 32; //[31:0]
+ uint32_t reserved_16a : 32; //[31:0]
+ uint32_t reserved_17a : 32; //[31:0]
+ uint32_t reserved_18a : 32; //[31:0]
+ uint32_t reserved_19a : 32; //[31:0]
+ uint32_t reserved_20a : 32; //[31:0]
+ uint32_t reserved_21a : 32; //[31:0]
+ uint32_t reserved_22a : 32; //[31:0]
+ uint32_t reserved_23a : 32; //[31:0]
+ uint32_t reserved_24a : 28, //[27:0]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+
+ Consumer: SW
+
+ Producer: REO
+
+
+
+ Details that can link this status with the original
+ command. It also contains info on how long REO took to
+ execute this command.
+
+reserved_2a
+
+ <legal 0>
+
+reserved_3a
+
+ <legal 0>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+reserved_8a
+
+ <legal 0>
+
+reserved_9a
+
+ <legal 0>
+
+reserved_10a
+
+ <legal 0>
+
+reserved_11a
+
+ <legal 0>
+
+reserved_12a
+
+ <legal 0>
+
+reserved_13a
+
+ <legal 0>
+
+reserved_14a
+
+ <legal 0>
+
+reserved_15a
+
+ <legal 0>
+
+reserved_16a
+
+ <legal 0>
+
+reserved_17a
+
+ <legal 0>
+
+reserved_18a
+
+ <legal 0>
+
+reserved_19a
+
+ <legal 0>
+
+reserved_20a
+
+ <legal 0>
+
+reserved_21a
+
+ <legal 0>
+
+reserved_22a
+
+ <legal 0>
+
+reserved_23a
+
+ <legal 0>
+
+reserved_24a
+
+ <legal 0>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */
+
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A
+
+ <legal 0>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff
+
+/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into this Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28
+#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_
diff --git a/hw/qca5018/rfa_from_wsi_seq_hwiobase.h b/hw/qca5018/rfa_from_wsi_seq_hwiobase.h
new file mode 100644
index 0000000..97dedb3
--- /dev/null
+++ b/hw/qca5018/rfa_from_wsi_seq_hwiobase.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// rfa_from_wsi_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
+// User Name:c_landav
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __RFA_FROM_WSI_SEQ_BASE_H__
+#define __RFA_FROM_WSI_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_from_wsi
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x000142e0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480
+#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800
+#define SEQ_RFA_FROM_WSI_RFA_CMN_DPLL_OFFSET 0x00014c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016240
+#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00
+#define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET 0x0001a000
+#define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET 0x0001a000
+#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH2_OFFSET 0x0001c000
+#define SEQ_RFA_FROM_WSI_RFA_BT_HLS_BT_REGFILE_OFFSET 0x0001c400
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001c800
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001c840
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001c880
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001c8c0
+#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET 0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET 0x00021640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET 0x00028000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET 0x00029640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_cmn
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_CMN_AON_OFFSET 0x00000000
+#define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240
+#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0
+#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x000002e0
+#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300
+#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400
+#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480
+#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800
+#define SEQ_RFA_CMN_DPLL_OFFSET 0x00000c00
+#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000
+#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040
+#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100
+#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140
+#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180
+#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0
+#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002240
+#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_pmu
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_PMU_PMU_OFFSET 0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_bt
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_BT_BT_CH2_OFFSET 0x00000000
+#define SEQ_RFA_BT_HLS_BT_REGFILE_OFFSET 0x00000400
+#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00000800
+#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00000840
+#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00000880
+#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x000008c0
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_wl
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000
+#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400
+#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800
+#define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000
+#define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300
+#define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600
+#define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640
+#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000
+#define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000
+#define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000
+#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400
+#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800
+#define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000
+#define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300
+#define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600
+#define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640
+#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000
+#define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000
+
+
+#endif
+
diff --git a/hw/qca5018/rx_attention.h b/hw/qca5018/rx_attention.h
new file mode 100644
index 0000000..f62f589
--- /dev/null
+++ b/hw/qca5018/rx_attention.h
@@ -0,0 +1,1178 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
+// 1 first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31]
+// 2 flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_ATTENTION 3
+
+struct rx_attention {
+ uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
+ sw_frame_group_id : 7, //[8:2]
+ reserved_0 : 7, //[15:9]
+ phy_ppdu_id : 16; //[31:16]
+ uint32_t first_mpdu : 1, //[0]
+ reserved_1a : 1, //[1]
+ mcast_bcast : 1, //[2]
+ ast_index_not_found : 1, //[3]
+ ast_index_timeout : 1, //[4]
+ power_mgmt : 1, //[5]
+ non_qos : 1, //[6]
+ null_data : 1, //[7]
+ mgmt_type : 1, //[8]
+ ctrl_type : 1, //[9]
+ more_data : 1, //[10]
+ eosp : 1, //[11]
+ a_msdu_error : 1, //[12]
+ fragment_flag : 1, //[13]
+ order : 1, //[14]
+ cce_match : 1, //[15]
+ overflow_err : 1, //[16]
+ msdu_length_err : 1, //[17]
+ tcp_udp_chksum_fail : 1, //[18]
+ ip_chksum_fail : 1, //[19]
+ sa_idx_invalid : 1, //[20]
+ da_idx_invalid : 1, //[21]
+ reserved_1b : 1, //[22]
+ rx_in_tx_decrypt_byp : 1, //[23]
+ encrypt_required : 1, //[24]
+ directed : 1, //[25]
+ buffer_fragment : 1, //[26]
+ mpdu_length_err : 1, //[27]
+ tkip_mic_err : 1, //[28]
+ decrypt_err : 1, //[29]
+ unencrypted_frame_err : 1, //[30]
+ fcs_err : 1; //[31]
+ uint32_t flow_idx_timeout : 1, //[0]
+ flow_idx_invalid : 1, //[1]
+ wifi_parser_error : 1, //[2]
+ amsdu_parser_error : 1, //[3]
+ sa_idx_timeout : 1, //[4]
+ da_idx_timeout : 1, //[5]
+ msdu_limit_error : 1, //[6]
+ da_is_valid : 1, //[7]
+ da_is_mcbc : 1, //[8]
+ sa_is_valid : 1, //[9]
+ decrypt_status_code : 3, //[12:10]
+ rx_bitmap_not_updated : 1, //[13]
+ reserved_2 : 17, //[30:14]
+ msdu_done : 1; //[31]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+ <legal 0-2>
+
+sw_frame_group_id
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame>
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+
+
+
+
+
+ <legal 0-37>
+
+reserved_0
+
+ <legal 0>
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+
+first_mpdu
+
+ Indicates the first MSDU of the PPDU. If both
+ first_mpdu and last_mpdu are set in the MSDU then this is a
+ not an A-MPDU frame but a stand alone MPDU. Interior MPDU
+ in an A-MPDU shall have both first_mpdu and last_mpdu bits
+ set to 0. The PPDU start status will only be valid when
+ this bit is set.
+
+reserved_1a
+
+ <legal 0>
+
+mcast_bcast
+
+ Multicast / broadcast indicator. Only set when the MAC
+ address 1 bit 0 is set indicating mcast/bcast and the BSSID
+ matches one of the 4 BSSID registers. Only set when
+ first_msdu is set.
+
+ast_index_not_found
+
+ Only valid when first_msdu is set.
+
+
+
+ Indicates no AST matching entries within the the max
+ search count.
+
+ast_index_timeout
+
+ Only valid when first_msdu is set.
+
+
+
+ Indicates an unsuccessful search in the address seach
+ table due to timeout.
+
+power_mgmt
+
+ Power management bit set in the 802.11 header. Only set
+ when first_msdu is set.
+
+non_qos
+
+ Set if packet is not a non-QoS data frame. Only set
+ when first_msdu is set.
+
+null_data
+
+ Set if frame type indicates either null data or QoS null
+ data format. Only set when first_msdu is set.
+
+mgmt_type
+
+ Set if packet is a management packet. Only set when
+ first_msdu is set.
+
+ctrl_type
+
+ Set if packet is a control packet. Only set when
+ first_msdu is set.
+
+more_data
+
+ Set if more bit in frame control is set. Only set when
+ first_msdu is set.
+
+eosp
+
+ Set if the EOSP (end of service period) bit in the QoS
+ control field is set. Only set when first_msdu is set.
+
+a_msdu_error
+
+ Set if number of MSDUs in A-MSDU is above a threshold or
+ if the size of the MSDU is invalid. This receive buffer
+ will contain all of the remainder of the MSDUs in this MPDU
+ without decapsulation.
+
+fragment_flag
+
+ Indicates that this is an 802.11 fragment frame. This
+ is set when either the more_frag bit is set in the frame
+ control or the fragment number is not zero. Only set when
+ first_msdu is set.
+
+order
+
+ Set if the order bit in the frame control is set. Only
+ set when first_msdu is set.
+
+cce_match
+
+ Indicates that this status has a corresponding MSDU that
+ requires FW processing. The OLE will have classification
+ ring mask registers which will indicate the ring(s) for
+ packets and descriptors which need FW attention.
+
+overflow_err
+
+ RXPCU Receive FIFO ran out of space to receive the full
+ MPDU. Therefor this MPDU is terminated early and is thus
+ corrupted.
+
+
+
+ This MPDU will not be ACKed.
+
+ RXPCU might still be able to correctly receive the
+ following MPDUs in the PPDU if enough fifo space became
+ available in time
+
+msdu_length_err
+
+ Indicates that the MSDU length from the 802.3
+ encapsulated length field extends beyond the MPDU boundary
+ or if the length is less than 14 bytes.
+
+ Merged with original other_msdu_err: Indicates that the
+ MSDU threshold was exceeded and thus all the rest of the
+ MSDUs will not be scattered and will not be decasulated but
+ will be DMA'ed in RAW format as a single MSDU buffer
+
+tcp_udp_chksum_fail
+
+ Indicates that the computed checksum (tcp_udp_chksum in
+ 'RX_MSDU_END') did not match the checksum in the TCP/UDP
+ header.
+
+ip_chksum_fail
+
+ Indicates that the computed checksum (ip_hdr_chksum in
+ 'RX_MSDU_END') did not match the checksum in the IP header.
+
+sa_idx_invalid
+
+ Indicates no matching entry was found in the address
+ search table for the source MAC address.
+
+da_idx_invalid
+
+ Indicates no matching entry was found in the address
+ search table for the destination MAC address.
+
+reserved_1b
+
+ <legal 0>
+
+rx_in_tx_decrypt_byp
+
+ Indicates that RX packet is not decrypted as Crypto is
+ busy with TX packet processing.
+
+encrypt_required
+
+ Indicates that this data type frame is not encrypted
+ even if the policy for this MPDU requires encryption as
+ indicated in the peer entry key type.
+
+directed
+
+ MPDU is a directed packet which means that the RA
+ matched our STA addresses. In proxySTA it means that the TA
+ matched an entry in our address search table with the
+ corresponding no_ack bit is the address search entry
+ cleared.
+
+buffer_fragment
+
+ Indicates that at least one of the rx buffers has been
+ fragmented. If set the FW should look at the rx_frag_info
+ descriptor described below.
+
+mpdu_length_err
+
+ Indicates that the MPDU was pre-maturely terminated
+ resulting in a truncated MPDU. Don't trust the MPDU length
+ field.
+
+tkip_mic_err
+
+ Indicates that the MPDU Michael integrity check failed
+
+decrypt_err
+
+ Indicates that the MPDU decrypt integrity check failed
+ or CRYPTO received an encrypted frame, but did not get a
+ valid corresponding key id in the peer entry.
+
+unencrypted_frame_err
+
+ Copied here by RX OLE from the RX_MPDU_END TLV
+
+fcs_err
+
+ Indicates that the MPDU FCS check failed
+
+flow_idx_timeout
+
+ Indicates an unsuccessful flow search due to the
+ expiring of the search timer.
+
+ <legal all>
+
+flow_idx_invalid
+
+ flow id is not valid
+
+ <legal all>
+
+wifi_parser_error
+
+ Indicates that the WiFi frame has one of the following
+ errors
+
+ o has less than minimum allowed bytes as per standard
+
+ o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
+
+ <legal all>
+
+amsdu_parser_error
+
+ A-MSDU could not be properly de-agregated.
+
+ <legal all>
+
+sa_idx_timeout
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer.
+
+da_idx_timeout
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer.
+
+msdu_limit_error
+
+ Indicates that the MSDU threshold was exceeded and thus
+ all the rest of the MSDUs will not be scattered and will not
+ be decasulated but will be DMA'ed in RAW format as a single
+ MSDU buffer
+
+da_is_valid
+
+ Indicates that OLE found a valid DA entry
+
+da_is_mcbc
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address.
+
+sa_is_valid
+
+ Indicates that OLE found a valid SA entry
+
+decrypt_status_code
+
+ Field provides insight into the decryption performed
+
+
+
+ <enum 0 decrypt_ok> Frame had protection enabled and
+ decrypted properly
+
+ <enum 1 decrypt_unprotected_frame > Frame is unprotected
+ and hence bypassed
+
+ <enum 2 decrypt_data_err > Frame has protection enabled
+ and could not be properly decrypted due to MIC/ICV mismatch
+ etc.
+
+ <enum 3 decrypt_key_invalid > Frame has protection
+ enabled but the key that was required to decrypt this frame
+ was not valid
+
+ <enum 4 decrypt_peer_entry_invalid > Frame has
+ protection enabled but the key that was required to decrypt
+ this frame was not valid
+
+ <enum 5 decrypt_other > Reserved for other indications
+
+
+
+ <legal 0 - 5>
+
+rx_bitmap_not_updated
+
+ Frame is received, but RXPCU could not update the
+ receive bitmap due to (temporary) fifo contraints.
+
+ <legal all>
+
+reserved_2
+
+ <legal 0>
+
+msdu_done
+
+ If set indicates that the RX packet data, RX header
+ data, RX PPDU start descriptor, RX MPDU start/end
+ descriptor, RX MSDU start/end descriptors and RX Attention
+ descriptor are all valid. This bit must be in the last
+ octet of the descriptor.
+*/
+
+
+/* Description RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+ <legal 0-2>
+*/
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+/* Description RX_ATTENTION_0_SW_FRAME_GROUP_ID
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame>
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+
+
+
+
+
+ <legal 0-37>
+*/
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+/* Description RX_ATTENTION_0_RESERVED_0
+
+ <legal 0>
+*/
+#define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000
+#define RX_ATTENTION_0_RESERVED_0_LSB 9
+#define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00
+
+/* Description RX_ATTENTION_0_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16
+#define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description RX_ATTENTION_1_FIRST_MPDU
+
+ Indicates the first MSDU of the PPDU. If both
+ first_mpdu and last_mpdu are set in the MSDU then this is a
+ not an A-MPDU frame but a stand alone MPDU. Interior MPDU
+ in an A-MPDU shall have both first_mpdu and last_mpdu bits
+ set to 0. The PPDU start status will only be valid when
+ this bit is set.
+*/
+#define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004
+#define RX_ATTENTION_1_FIRST_MPDU_LSB 0
+#define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001
+
+/* Description RX_ATTENTION_1_RESERVED_1A
+
+ <legal 0>
+*/
+#define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_ATTENTION_1_RESERVED_1A_LSB 1
+#define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002
+
+/* Description RX_ATTENTION_1_MCAST_BCAST
+
+ Multicast / broadcast indicator. Only set when the MAC
+ address 1 bit 0 is set indicating mcast/bcast and the BSSID
+ matches one of the 4 BSSID registers. Only set when
+ first_msdu is set.
+*/
+#define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004
+#define RX_ATTENTION_1_MCAST_BCAST_LSB 2
+#define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004
+
+/* Description RX_ATTENTION_1_AST_INDEX_NOT_FOUND
+
+ Only valid when first_msdu is set.
+
+
+
+ Indicates no AST matching entries within the the max
+ search count.
+*/
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008
+
+/* Description RX_ATTENTION_1_AST_INDEX_TIMEOUT
+
+ Only valid when first_msdu is set.
+
+
+
+ Indicates an unsuccessful search in the address seach
+ table due to timeout.
+*/
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010
+
+/* Description RX_ATTENTION_1_POWER_MGMT
+
+ Power management bit set in the 802.11 header. Only set
+ when first_msdu is set.
+*/
+#define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004
+#define RX_ATTENTION_1_POWER_MGMT_LSB 5
+#define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020
+
+/* Description RX_ATTENTION_1_NON_QOS
+
+ Set if packet is not a non-QoS data frame. Only set
+ when first_msdu is set.
+*/
+#define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004
+#define RX_ATTENTION_1_NON_QOS_LSB 6
+#define RX_ATTENTION_1_NON_QOS_MASK 0x00000040
+
+/* Description RX_ATTENTION_1_NULL_DATA
+
+ Set if frame type indicates either null data or QoS null
+ data format. Only set when first_msdu is set.
+*/
+#define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004
+#define RX_ATTENTION_1_NULL_DATA_LSB 7
+#define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080
+
+/* Description RX_ATTENTION_1_MGMT_TYPE
+
+ Set if packet is a management packet. Only set when
+ first_msdu is set.
+*/
+#define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004
+#define RX_ATTENTION_1_MGMT_TYPE_LSB 8
+#define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100
+
+/* Description RX_ATTENTION_1_CTRL_TYPE
+
+ Set if packet is a control packet. Only set when
+ first_msdu is set.
+*/
+#define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004
+#define RX_ATTENTION_1_CTRL_TYPE_LSB 9
+#define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200
+
+/* Description RX_ATTENTION_1_MORE_DATA
+
+ Set if more bit in frame control is set. Only set when
+ first_msdu is set.
+*/
+#define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004
+#define RX_ATTENTION_1_MORE_DATA_LSB 10
+#define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400
+
+/* Description RX_ATTENTION_1_EOSP
+
+ Set if the EOSP (end of service period) bit in the QoS
+ control field is set. Only set when first_msdu is set.
+*/
+#define RX_ATTENTION_1_EOSP_OFFSET 0x00000004
+#define RX_ATTENTION_1_EOSP_LSB 11
+#define RX_ATTENTION_1_EOSP_MASK 0x00000800
+
+/* Description RX_ATTENTION_1_A_MSDU_ERROR
+
+ Set if number of MSDUs in A-MSDU is above a threshold or
+ if the size of the MSDU is invalid. This receive buffer
+ will contain all of the remainder of the MSDUs in this MPDU
+ without decapsulation.
+*/
+#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004
+#define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12
+#define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000
+
+/* Description RX_ATTENTION_1_FRAGMENT_FLAG
+
+ Indicates that this is an 802.11 fragment frame. This
+ is set when either the more_frag bit is set in the frame
+ control or the fragment number is not zero. Only set when
+ first_msdu is set.
+*/
+#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004
+#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13
+#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000
+
+/* Description RX_ATTENTION_1_ORDER
+
+ Set if the order bit in the frame control is set. Only
+ set when first_msdu is set.
+*/
+#define RX_ATTENTION_1_ORDER_OFFSET 0x00000004
+#define RX_ATTENTION_1_ORDER_LSB 14
+#define RX_ATTENTION_1_ORDER_MASK 0x00004000
+
+/* Description RX_ATTENTION_1_CCE_MATCH
+
+ Indicates that this status has a corresponding MSDU that
+ requires FW processing. The OLE will have classification
+ ring mask registers which will indicate the ring(s) for
+ packets and descriptors which need FW attention.
+*/
+#define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004
+#define RX_ATTENTION_1_CCE_MATCH_LSB 15
+#define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000
+
+/* Description RX_ATTENTION_1_OVERFLOW_ERR
+
+ RXPCU Receive FIFO ran out of space to receive the full
+ MPDU. Therefor this MPDU is terminated early and is thus
+ corrupted.
+
+
+
+ This MPDU will not be ACKed.
+
+ RXPCU might still be able to correctly receive the
+ following MPDUs in the PPDU if enough fifo space became
+ available in time
+*/
+#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16
+#define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000
+
+/* Description RX_ATTENTION_1_MSDU_LENGTH_ERR
+
+ Indicates that the MSDU length from the 802.3
+ encapsulated length field extends beyond the MPDU boundary
+ or if the length is less than 14 bytes.
+
+ Merged with original other_msdu_err: Indicates that the
+ MSDU threshold was exceeded and thus all the rest of the
+ MSDUs will not be scattered and will not be decasulated but
+ will be DMA'ed in RAW format as a single MSDU buffer
+*/
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000
+
+/* Description RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL
+
+ Indicates that the computed checksum (tcp_udp_chksum in
+ 'RX_MSDU_END') did not match the checksum in the TCP/UDP
+ header.
+*/
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000
+
+/* Description RX_ATTENTION_1_IP_CHKSUM_FAIL
+
+ Indicates that the computed checksum (ip_hdr_chksum in
+ 'RX_MSDU_END') did not match the checksum in the IP header.
+*/
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000
+
+/* Description RX_ATTENTION_1_SA_IDX_INVALID
+
+ Indicates no matching entry was found in the address
+ search table for the source MAC address.
+*/
+#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004
+#define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20
+#define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000
+
+/* Description RX_ATTENTION_1_DA_IDX_INVALID
+
+ Indicates no matching entry was found in the address
+ search table for the destination MAC address.
+*/
+#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004
+#define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21
+#define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000
+
+/* Description RX_ATTENTION_1_RESERVED_1B
+
+ <legal 0>
+*/
+#define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004
+#define RX_ATTENTION_1_RESERVED_1B_LSB 22
+#define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000
+
+/* Description RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP
+
+ Indicates that RX packet is not decrypted as Crypto is
+ busy with TX packet processing.
+*/
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000
+
+/* Description RX_ATTENTION_1_ENCRYPT_REQUIRED
+
+ Indicates that this data type frame is not encrypted
+ even if the policy for this MPDU requires encryption as
+ indicated in the peer entry key type.
+*/
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000
+
+/* Description RX_ATTENTION_1_DIRECTED
+
+ MPDU is a directed packet which means that the RA
+ matched our STA addresses. In proxySTA it means that the TA
+ matched an entry in our address search table with the
+ corresponding no_ack bit is the address search entry
+ cleared.
+*/
+#define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004
+#define RX_ATTENTION_1_DIRECTED_LSB 25
+#define RX_ATTENTION_1_DIRECTED_MASK 0x02000000
+
+/* Description RX_ATTENTION_1_BUFFER_FRAGMENT
+
+ Indicates that at least one of the rx buffers has been
+ fragmented. If set the FW should look at the rx_frag_info
+ descriptor described below.
+*/
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000
+
+/* Description RX_ATTENTION_1_MPDU_LENGTH_ERR
+
+ Indicates that the MPDU was pre-maturely terminated
+ resulting in a truncated MPDU. Don't trust the MPDU length
+ field.
+*/
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000
+
+/* Description RX_ATTENTION_1_TKIP_MIC_ERR
+
+ Indicates that the MPDU Michael integrity check failed
+*/
+#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28
+#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000
+
+/* Description RX_ATTENTION_1_DECRYPT_ERR
+
+ Indicates that the MPDU decrypt integrity check failed
+ or CRYPTO received an encrypted frame, but did not get a
+ valid corresponding key id in the peer entry.
+*/
+#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_DECRYPT_ERR_LSB 29
+#define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000
+
+/* Description RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR
+
+ Copied here by RX OLE from the RX_MPDU_END TLV
+*/
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000
+
+/* Description RX_ATTENTION_1_FCS_ERR
+
+ Indicates that the MPDU FCS check failed
+*/
+#define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004
+#define RX_ATTENTION_1_FCS_ERR_LSB 31
+#define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000
+
+/* Description RX_ATTENTION_2_FLOW_IDX_TIMEOUT
+
+ Indicates an unsuccessful flow search due to the
+ expiring of the search timer.
+
+ <legal all>
+*/
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001
+
+/* Description RX_ATTENTION_2_FLOW_IDX_INVALID
+
+ flow id is not valid
+
+ <legal all>
+*/
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002
+
+/* Description RX_ATTENTION_2_WIFI_PARSER_ERROR
+
+ Indicates that the WiFi frame has one of the following
+ errors
+
+ o has less than minimum allowed bytes as per standard
+
+ o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
+
+ <legal all>
+*/
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004
+
+/* Description RX_ATTENTION_2_AMSDU_PARSER_ERROR
+
+ A-MSDU could not be properly de-agregated.
+
+ <legal all>
+*/
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008
+
+/* Description RX_ATTENTION_2_SA_IDX_TIMEOUT
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer.
+*/
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010
+
+/* Description RX_ATTENTION_2_DA_IDX_TIMEOUT
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer.
+*/
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020
+
+/* Description RX_ATTENTION_2_MSDU_LIMIT_ERROR
+
+ Indicates that the MSDU threshold was exceeded and thus
+ all the rest of the MSDUs will not be scattered and will not
+ be decasulated but will be DMA'ed in RAW format as a single
+ MSDU buffer
+*/
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040
+
+/* Description RX_ATTENTION_2_DA_IS_VALID
+
+ Indicates that OLE found a valid DA entry
+*/
+#define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008
+#define RX_ATTENTION_2_DA_IS_VALID_LSB 7
+#define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080
+
+/* Description RX_ATTENTION_2_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address.
+*/
+#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_ATTENTION_2_DA_IS_MCBC_LSB 8
+#define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100
+
+/* Description RX_ATTENTION_2_SA_IS_VALID
+
+ Indicates that OLE found a valid SA entry
+*/
+#define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008
+#define RX_ATTENTION_2_SA_IS_VALID_LSB 9
+#define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200
+
+/* Description RX_ATTENTION_2_DECRYPT_STATUS_CODE
+
+ Field provides insight into the decryption performed
+
+
+
+ <enum 0 decrypt_ok> Frame had protection enabled and
+ decrypted properly
+
+ <enum 1 decrypt_unprotected_frame > Frame is unprotected
+ and hence bypassed
+
+ <enum 2 decrypt_data_err > Frame has protection enabled
+ and could not be properly decrypted due to MIC/ICV mismatch
+ etc.
+
+ <enum 3 decrypt_key_invalid > Frame has protection
+ enabled but the key that was required to decrypt this frame
+ was not valid
+
+ <enum 4 decrypt_peer_entry_invalid > Frame has
+ protection enabled but the key that was required to decrypt
+ this frame was not valid
+
+ <enum 5 decrypt_other > Reserved for other indications
+
+
+
+ <legal 0 - 5>
+*/
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00
+
+/* Description RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED
+
+ Frame is received, but RXPCU could not update the
+ receive bitmap due to (temporary) fifo contraints.
+
+ <legal all>
+*/
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000
+
+/* Description RX_ATTENTION_2_RESERVED_2
+
+ <legal 0>
+*/
+#define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008
+#define RX_ATTENTION_2_RESERVED_2_LSB 14
+#define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000
+
+/* Description RX_ATTENTION_2_MSDU_DONE
+
+ If set indicates that the RX packet data, RX header
+ data, RX PPDU start descriptor, RX MPDU start/end
+ descriptor, RX MSDU start/end descriptors and RX Attention
+ descriptor are all valid. This bit must be in the last
+ octet of the descriptor.
+*/
+#define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008
+#define RX_ATTENTION_2_MSDU_DONE_LSB 31
+#define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000
+
+
+#endif // _RX_ATTENTION_H_
diff --git a/hw/qca5018/rx_flow_search_entry.h b/hw/qca5018/rx_flow_search_entry.h
new file mode 100644
index 0000000..0430be7
--- /dev/null
+++ b/hw/qca5018/rx_flow_search_entry.h
@@ -0,0 +1,786 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 src_ip_127_96[31:0]
+// 1 src_ip_95_64[31:0]
+// 2 src_ip_63_32[31:0]
+// 3 src_ip_31_0[31:0]
+// 4 dest_ip_127_96[31:0]
+// 5 dest_ip_95_64[31:0]
+// 6 dest_ip_63_32[31:0]
+// 7 dest_ip_31_0[31:0]
+// 8 src_port[15:0], dest_port[31:16]
+// 9 l4_protocol[7:0], valid[8], reserved_9[23:9], reo_destination_indication[28:24], msdu_drop[29], reo_destination_handler[31:30]
+// 10 metadata[31:0]
+// 11 aggregation_count[6:0], lro_eligible[7], msdu_count[31:8]
+// 12 msdu_byte_count[31:0]
+// 13 timestamp[31:0]
+// 14 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16]
+// 15 tcp_sequence_number[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+ uint32_t src_ip_127_96 : 32; //[31:0]
+ uint32_t src_ip_95_64 : 32; //[31:0]
+ uint32_t src_ip_63_32 : 32; //[31:0]
+ uint32_t src_ip_31_0 : 32; //[31:0]
+ uint32_t dest_ip_127_96 : 32; //[31:0]
+ uint32_t dest_ip_95_64 : 32; //[31:0]
+ uint32_t dest_ip_63_32 : 32; //[31:0]
+ uint32_t dest_ip_31_0 : 32; //[31:0]
+ uint32_t src_port : 16, //[15:0]
+ dest_port : 16; //[31:16]
+ uint32_t l4_protocol : 8, //[7:0]
+ valid : 1, //[8]
+ reserved_9 : 15, //[23:9]
+ reo_destination_indication : 5, //[28:24]
+ msdu_drop : 1, //[29]
+ reo_destination_handler : 2; //[31:30]
+ uint32_t metadata : 32; //[31:0]
+ uint32_t aggregation_count : 7, //[6:0]
+ lro_eligible : 1, //[7]
+ msdu_count : 24; //[31:8]
+ uint32_t msdu_byte_count : 32; //[31:0]
+ uint32_t timestamp : 32; //[31:0]
+ uint32_t cumulative_l4_checksum : 16, //[15:0]
+ cumulative_ip_length : 16; //[31:16]
+ uint32_t tcp_sequence_number : 32; //[31:0]
+};
+
+/*
+
+src_ip_127_96
+
+ Uppermost 32 bits of source IPv6 address or prefix as
+ per Common Parser register field IP_DA_SA_PREFIX (with the
+ first byte in the MSB and the last byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order in an IPv6 packet)
+
+ <legal all>
+
+src_ip_95_64
+
+ Next 32 bits of source IPv6 address or prefix (requiring
+ a byte-swap for little-endian SW) <legal all>
+
+src_ip_63_32
+
+ Next 32 bits of source IPv6 address or lowest 32 bits of
+ prefix (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+
+src_ip_31_0
+
+ Lowest 32 bits of source IPv6 address, or source IPv4
+ address (requiring a byte-swap for little-endian SW w.r.t.
+ the byte order in an IPv6 or IPv4 packet)
+
+ <legal all>
+
+dest_ip_127_96
+
+ Uppermost 32 bits of destination IPv6 address or prefix
+ as per Common Parser register field IP_DA_SA_PREFIX (with
+ the first byte in the MSB and the last byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order as in an IPv6 packet)
+
+ <legal all>
+
+dest_ip_95_64
+
+ Next 32 bits of destination IPv6 address or prefix
+ (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+
+dest_ip_63_32
+
+ Next 32 bits of destination IPv6 address or lowest 32
+ bits of prefix (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+
+dest_ip_31_0
+
+ Lowest 32 bits of destination IPv6 address, or
+ destination IPv4 address (requiring a byte-swap for
+ little-endian SW w.r.t. the byte order in an IPv6 or IPv4
+ packet)
+
+ <legal all>
+
+src_port
+
+ LSB of SPI in case of ESP/AH
+
+ else source port in case of TCP/UDP without IPsec,
+
+ else zeros in case of ICMP (with the first/third byte in
+ the MSB and the second/fourth byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order as in an IPv6 or IPv4 packet) <legal all>
+
+dest_port
+
+ MSB of SPI in case of ESP/AH
+
+ else destination port in case of TCP/UDP without IPsec,
+
+ else zeros in case of ICMP (with the first byte in the
+ MSB and the second byte in the LSB, i.e. requiring a
+ byte-swap for little-endian SW w.r.t. the byte order as in
+ an IPv6 or IPv4 packet)
+
+ <legal all>
+
+l4_protocol
+
+ IPsec or L4 protocol
+
+
+
+ <enum 1 ICMPV4>
+
+ <enum 6 TCP>
+
+ <enum 17 UDP>
+
+ <enum 50 ESP>
+
+ <enum 51 AH>
+
+ <enum 58 ICMPV6>
+
+ <legal 1, 6, 17, 50, 51, 58>
+
+valid
+
+ Indicates validity of entry
+
+ <legal all>
+
+reserved_9
+
+ <legal 0>
+
+reo_destination_indication
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+
+msdu_drop
+
+ Overriding indication to REO to forward to REO release
+ ring
+
+ <legal all>
+
+reo_destination_handler
+
+ Indicates how to decide the REO destination indication
+
+ <enum 0 RXFT_USE_FT> Follow this entry
+
+ <enum 1 RXFT_USE_ASPT> Use address search+peer table
+ entry
+
+ <enum 2 RXFT_USE_FT2> Follow this entry
+
+ <enum 3 RXFT_USE_CCE> Use CCE super-rule
+
+ <legal all>
+
+metadata
+
+ Value to be passed to SW if this flow search entry
+ matches
+
+ <legal all>
+
+aggregation_count
+
+ FISA: Number'of MSDU's aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+lro_eligible
+
+ FISA: To indicate whether the previous MSDU for this
+ flow is eligible for LRO/FISA
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+msdu_count
+
+ Number of Rx MSDUs matching this flow
+
+ <legal all>
+
+msdu_byte_count
+
+ Number of bytes in Rx MSDUs matching this flow
+
+ <legal all>
+
+timestamp
+
+ Time of last reception (as measured at Rx OLE) matching
+ this flow
+
+ <legal all>
+
+cumulative_l4_checksum
+
+ FISA: checksum 'or MSDU's that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+cumulative_ip_length
+
+ FISA: Total MSDU length that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+tcp_sequence_number
+
+ FISA: TCP Sequence number of the last packet in this
+ flow to detect sequence number jump
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+
+
+/* Description RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96
+
+ Uppermost 32 bits of source IPv6 address or prefix as
+ per Common Parser register field IP_DA_SA_PREFIX (with the
+ first byte in the MSB and the last byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order in an IPv6 packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64
+
+ Next 32 bits of source IPv6 address or prefix (requiring
+ a byte-swap for little-endian SW) <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32
+
+ Next 32 bits of source IPv6 address or lowest 32 bits of
+ prefix (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0
+
+ Lowest 32 bits of source IPv6 address, or source IPv4
+ address (requiring a byte-swap for little-endian SW w.r.t.
+ the byte order in an IPv6 or IPv4 packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96
+
+ Uppermost 32 bits of destination IPv6 address or prefix
+ as per Common Parser register field IP_DA_SA_PREFIX (with
+ the first byte in the MSB and the last byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order as in an IPv6 packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64
+
+ Next 32 bits of destination IPv6 address or prefix
+ (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32
+
+ Next 32 bits of destination IPv6 address or lowest 32
+ bits of prefix (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0
+
+ Lowest 32 bits of destination IPv6 address, or
+ destination IPv4 address (requiring a byte-swap for
+ little-endian SW w.r.t. the byte order in an IPv6 or IPv4
+ packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_8_SRC_PORT
+
+ LSB of SPI in case of ESP/AH
+
+ else source port in case of TCP/UDP without IPsec,
+
+ else zeros in case of ICMP (with the first/third byte in
+ the MSB and the second/fourth byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order as in an IPv6 or IPv4 packet) <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_8_DEST_PORT
+
+ MSB of SPI in case of ESP/AH
+
+ else destination port in case of TCP/UDP without IPsec,
+
+ else zeros in case of ICMP (with the first byte in the
+ MSB and the second byte in the LSB, i.e. requiring a
+ byte-swap for little-endian SW w.r.t. the byte order as in
+ an IPv6 or IPv4 packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL
+
+ IPsec or L4 protocol
+
+
+
+ <enum 1 ICMPV4>
+
+ <enum 6 TCP>
+
+ <enum 17 UDP>
+
+ <enum 50 ESP>
+
+ <enum 51 AH>
+
+ <enum 58 ICMPV6>
+
+ <legal 1, 6, 17, 50, 51, 58>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_VALID
+
+ Indicates validity of entry
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_RESERVED_9
+
+ <legal 0>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP
+
+ Overriding indication to REO to forward to REO release
+ ring
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER
+
+ Indicates how to decide the REO destination indication
+
+ <enum 0 RXFT_USE_FT> Follow this entry
+
+ <enum 1 RXFT_USE_ASPT> Use address search+peer table
+ entry
+
+ <enum 2 RXFT_USE_FT2> Follow this entry
+
+ <enum 3 RXFT_USE_CCE> Use CCE super-rule
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000
+
+/* Description RX_FLOW_SEARCH_ENTRY_10_METADATA
+
+ Value to be passed to SW if this flow search entry
+ matches
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT
+
+ FISA: Number'of MSDU's aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f
+
+/* Description RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE
+
+ FISA: To indicate whether the previous MSDU for this
+ flow is eligible for LRO/FISA
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080
+
+/* Description RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT
+
+ Number of Rx MSDUs matching this flow
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00
+
+/* Description RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT
+
+ Number of bytes in Rx MSDUs matching this flow
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP
+
+ Time of last reception (as measured at Rx OLE) matching
+ this flow
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM
+
+ FISA: checksum 'or MSDU's that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH
+
+ FISA: Total MSDU length that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
+
+/* Description RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER
+
+ FISA: TCP Sequence number of the last packet in this
+ flow to detect sequence number jump
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff
+
+
+#endif // _RX_FLOW_SEARCH_ENTRY_H_
diff --git a/hw/qca5018/rx_location_info.h b/hw/qca5018/rx_location_info.h
new file mode 100644
index 0000000..a0c57ba
--- /dev/null
+++ b/hw/qca5018/rx_location_info.h
@@ -0,0 +1,1369 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_LOCATION_INFO_H_
+#define _RX_LOCATION_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 rtt_fac_legacy[15:0], rtt_fac_legacy_ext80[31:16]
+// 1 rtt_fac_vht[15:0], rtt_fac_vht_ext80[31:16]
+// 2 rtt_fac_legacy_status[0], rtt_fac_legacy_ext80_status[1], rtt_fac_vht_status[2], rtt_fac_vht_ext80_status[3], rtt_fac_sifs[15:4], rtt_fac_sifs_status[17:16], rtt_cfr_status[18], rtt_cir_status[19], rtt_channel_dump_size[30:20], rtt_hw_ifft_mode[31]
+// 3 rtt_btcf_status[0], rtt_preamble_type[5:1], rtt_pkt_bw_leg[7:6], rtt_pkt_bw_vht[9:8], rtt_gi_type[11:10], rtt_mcs_rate[16:12], rtt_strongest_chain[19:17], rtt_strongest_chain_ext80[22:20], rtt_rx_chain_mask[30:23], reserved_3[31]
+// 4 rx_start_ts[31:0]
+// 5 rx_end_ts[31:0]
+// 6 sfo_phase_pkt_start[11:0], sfo_phase_pkt_end[23:12], rtt_che_buffer_pointer_high8[31:24]
+// 7 rtt_che_buffer_pointer_low32[31:0]
+// 8 rtt_cfo_measurement[13:0], rtt_chan_spread[21:14], rtt_timing_backoff_sel[23:22], reserved_8[30:24], rx_location_info_valid[31]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_LOCATION_INFO 9
+
+struct rx_location_info {
+ uint32_t rtt_fac_legacy : 16, //[15:0]
+ rtt_fac_legacy_ext80 : 16; //[31:16]
+ uint32_t rtt_fac_vht : 16, //[15:0]
+ rtt_fac_vht_ext80 : 16; //[31:16]
+ uint32_t rtt_fac_legacy_status : 1, //[0]
+ rtt_fac_legacy_ext80_status : 1, //[1]
+ rtt_fac_vht_status : 1, //[2]
+ rtt_fac_vht_ext80_status : 1, //[3]
+ rtt_fac_sifs : 12, //[15:4]
+ rtt_fac_sifs_status : 2, //[17:16]
+ rtt_cfr_status : 1, //[18]
+ rtt_cir_status : 1, //[19]
+ rtt_channel_dump_size : 11, //[30:20]
+ rtt_hw_ifft_mode : 1; //[31]
+ uint32_t rtt_btcf_status : 1, //[0]
+ rtt_preamble_type : 5, //[5:1]
+ rtt_pkt_bw_leg : 2, //[7:6]
+ rtt_pkt_bw_vht : 2, //[9:8]
+ rtt_gi_type : 2, //[11:10]
+ rtt_mcs_rate : 5, //[16:12]
+ rtt_strongest_chain : 3, //[19:17]
+ rtt_strongest_chain_ext80 : 3, //[22:20]
+ rtt_rx_chain_mask : 8, //[30:23]
+ reserved_3 : 1; //[31]
+ uint32_t rx_start_ts : 32; //[31:0]
+ uint32_t rx_end_ts : 32; //[31:0]
+ uint32_t sfo_phase_pkt_start : 12, //[11:0]
+ sfo_phase_pkt_end : 12, //[23:12]
+ rtt_che_buffer_pointer_high8 : 8; //[31:24]
+ uint32_t rtt_che_buffer_pointer_low32 : 32; //[31:0]
+ uint32_t rtt_cfo_measurement : 14, //[13:0]
+ rtt_chan_spread : 8, //[21:14]
+ rtt_timing_backoff_sel : 2, //[23:22]
+ reserved_8 : 7, //[30:24]
+ rx_location_info_valid : 1; //[31]
+};
+
+/*
+
+rtt_fac_legacy
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the first selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+
+rtt_fac_legacy_ext80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the second selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+
+rtt_fac_vht
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the first
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+
+rtt_fac_vht_ext80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the second
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+
+rtt_fac_legacy_status
+
+ Status of rtt_fac_legacy
+
+
+
+ <enum 0 location_fac_legacy_status_not_valid>
+
+ <enum 1 location_fac_legacy_status_valid>
+
+ <legal all>
+
+rtt_fac_legacy_ext80_status
+
+ Status of rtt_fac_legacy_ext80
+
+
+
+ <enum 0 location_fac_legacy_ext80_status_not_valid>
+
+ <enum 1 location_fac_legacy_ext80_status_valid>
+
+ <legal all>
+
+rtt_fac_vht_status
+
+ Status of rtt_fac_vht
+
+
+
+ <enum 0 location_fac_vht_status_not_valid>
+
+ <enum 1 location_fac_vht_status_valid>
+
+ <legal all>
+
+rtt_fac_vht_ext80_status
+
+ Status of rtt_fac_vht_ext80
+
+
+
+ <enum 0 location_fac_vht_ext80_status_not_valid>
+
+ <enum 1 location_fac_vht_ext80_status_valid>
+
+ <legal all>
+
+rtt_fac_sifs
+
+ To support fine SIFS adjustment, need to provide FAC
+ value @ integer number of 320 MHz clock cycles to MAC. It
+ is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF
+ if it is a (V)HT/HE packet
+
+
+
+ 12 bits, signed, no fractional part
+
+ <legal all>
+
+rtt_fac_sifs_status
+
+ Status of rtt_fac_sifs
+
+ 0: not valid
+
+ 1: valid and from L-LTF
+
+ 2: valid and from (V)HT/HE-LTF
+
+ 3: reserved
+
+ <legal 0-2>
+
+rtt_cfr_status
+
+ Status of channel frequency response dump
+
+
+
+ <enum 0 location_CFR_dump_not_valid>
+
+ <enum 1 location_CFR_dump_valid>
+
+ <legal all>
+
+rtt_cir_status
+
+ Status of channel impulse response dump
+
+
+
+ <enum 0 location_CIR_dump_not_valid>
+
+ <enum 1 location_CIR_dump_valid>
+
+ <legal all>
+
+rtt_channel_dump_size
+
+ Channel dump size. It shows how many tones in CFR in
+ one chain, for example, it will show 52 for Legacy20 and 484
+ for VHT160
+
+
+
+ <legal all>
+
+rtt_hw_ifft_mode
+
+ Indicator showing if HW IFFT mode or SW IFFT mode
+
+
+
+ <enum 0 location_sw_ifft_mode>
+
+ <enum 1 location_hw_ifft_mode>
+
+ <legal all>
+
+rtt_btcf_status
+
+ Indicate if BTCF is used to capture the timestamps
+
+
+
+ <enum 0 location_not_BTCF_based_ts>
+
+ <enum 1 location_BTCF_based_ts>
+
+ <legal all>
+
+rtt_preamble_type
+
+ Indicate preamble type
+
+
+
+ <enum 0 location_preamble_type_legacy>
+
+ <enum 1 location_preamble_type_ht>
+
+ <enum 2 location_preamble_type_vht>
+
+ <enum 3 location_preamble_type_he_su_4xltf>
+
+ <enum 4 location_preamble_type_he_su_2xltf>
+
+ <enum 5 location_preamble_type_he_su_1xltf>
+
+ <enum 6
+ location_preamble_type_he_trigger_based_ul_4xltf>
+
+ <enum 7
+ location_preamble_type_he_trigger_based_ul_2xltf>
+
+ <enum 8
+ location_preamble_type_he_trigger_based_ul_1xltf>
+
+ <enum 9 location_preamble_type_he_mu_4xltf>
+
+ <enum 10 location_preamble_type_he_mu_2xltf>
+
+ <enum 11 location_preamble_type_he_mu_1xltf>
+
+ <enum 12
+ location_preamble_type_he_extended_range_su_4xltf>
+
+ <enum 13
+ location_preamble_type_he_extended_range_su_2xltf>
+
+ <enum 14
+ location_preamble_type_he_extended_range_su_1xltf>
+
+ <legal 0-14>
+
+rtt_pkt_bw_leg
+
+ Indicate the bandwidth of L-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+
+rtt_pkt_bw_vht
+
+ Indicate the bandwidth of (V)HT/HE-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+
+rtt_gi_type
+
+ Indicate GI (guard interval) type
+
+
+
+ <enum 0 gi_0_8_us > HE related GI. Can also be used
+ for HE
+
+ <enum 1 gi_0_4_us > HE related GI. Can also be used
+ for HE
+
+ <enum 2 gi_1_6_us > HE related GI
+
+ <enum 3 gi_3_2_us > HE related GI
+
+ <legal 0 - 3>
+
+rtt_mcs_rate
+
+ Bits 0~4 indicate MCS rate, if Legacy,
+
+ 0: 48 Mbps,
+
+ 1: 24 Mbps,
+
+ 2: 12 Mbps,
+
+ 3: 6 Mbps,
+
+ 4: 54 Mbps,
+
+ 5: 36 Mbps,
+
+ 6: 18 Mbps,
+
+ 7: 9 Mbps,
+
+
+
+ if HT, 0-7: MCS0-MCS7,
+
+ if VHT, 0-9: MCS0-MCS9,
+
+
+ <legal all>
+
+rtt_strongest_chain
+
+ For 20/40/80, this field shows the first selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected pri80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+
+rtt_strongest_chain_ext80
+
+ For 20/40/80, this field shows the second selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected ext80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+
+rtt_rx_chain_mask
+
+ Rx chain mask, each bit is a Rx chain
+
+ 0: the Rx chain is not used
+
+ 1: the Rx chain is used
+
+ Support up to 8 Rx chains
+
+ <legal all>
+
+reserved_3
+
+ <legal 0>
+
+rx_start_ts
+
+ RX packet start timestamp
+
+
+
+ It reports the time the first L-STF ADC sample arrived
+ at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+
+rx_end_ts
+
+ RX packet end timestamp
+
+
+
+ It reports the time the last symbol's last ADC sample
+ arrived at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+
+sfo_phase_pkt_start
+
+ The phase of the SFO of the first symbol's first FFT
+ input sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+
+sfo_phase_pkt_end
+
+ The phase of the SFO of the last symbol's last FFT input
+ sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+
+rtt_che_buffer_pointer_high8
+
+ The high 8 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 8 bits
+
+ <legal all>
+
+rtt_che_buffer_pointer_low32
+
+ The low 32 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 32 bits
+
+ <legal all>
+
+rtt_cfo_measurement
+
+ CFO measurement. Needed for passive locationing
+
+
+
+ 14 bits, signed 1.13. 13 bits fraction to provide a
+ resolution of 153 Hz
+
+
+
+ In units of cycles/800 ns
+
+ <legal all>
+
+rtt_chan_spread
+
+ Channel delay spread measurement. Needed for selecting
+ GI length
+
+
+
+ 8 bits, unsigned. At 25 ns step. Can represent up to
+ 6375 ns
+
+
+
+ In units of cycles @ 40 MHz
+
+ <legal all>
+
+rtt_timing_backoff_sel
+
+ Indicate which timing backoff value is used
+
+
+
+ <enum 0 timing_backoff_low_rssi>
+
+ <enum 1 timing_backoff_mid_rssi>
+
+ <enum 2 timing_backoff_high_rssi>
+
+ <enum 3 reserved>
+
+ <legal all>
+
+reserved_8
+
+ <legal 0>
+
+rx_location_info_valid
+
+ <enum 0 rx_location_info_is_not_valid>
+
+ <enum 1 rx_location_info_is_valid>
+
+ <legal all>
+*/
+
+
+/* Description RX_LOCATION_INFO_0_RTT_FAC_LEGACY
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the first selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_OFFSET 0x00000000
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_LSB 0
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_MASK 0x0000ffff
+
+/* Description RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from L-LTF on the second selected
+ Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from L-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000000
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_LSB 16
+#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000
+
+/* Description RX_LOCATION_INFO_1_RTT_FAC_VHT
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the first
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on pri80 on the
+ selected pri80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover pri80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_OFFSET 0x00000004
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_LSB 0
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_MASK 0x0000ffff
+
+/* Description RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80
+
+ For 20/40/80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on the second
+ selected Rx chain
+
+
+
+ For 80+80, this field shows the RTT first arrival
+ correction value computed from (V)HT/HE-LTF on ext80 on the
+ selected ext80 Rx chain
+
+
+
+ 16 bits, signed 12.4. 12 bits integer to cover -6.4us to
+ 6.4us, and 4 bits fraction to cover ext80 and 32x FAC
+ interpolation
+
+
+
+ clock unit is 320MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_OFFSET 0x00000004
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_LSB 16
+#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_MASK 0xffff0000
+
+/* Description RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS
+
+ Status of rtt_fac_legacy
+
+
+
+ <enum 0 location_fac_legacy_status_not_valid>
+
+ <enum 1 location_fac_legacy_status_valid>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_LSB 0
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_MASK 0x00000001
+
+/* Description RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS
+
+ Status of rtt_fac_legacy_ext80
+
+
+
+ <enum 0 location_fac_legacy_ext80_status_not_valid>
+
+ <enum 1 location_fac_legacy_ext80_status_valid>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1
+#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002
+
+/* Description RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS
+
+ Status of rtt_fac_vht
+
+
+
+ <enum 0 location_fac_vht_status_not_valid>
+
+ <enum 1 location_fac_vht_status_valid>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_LSB 2
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_MASK 0x00000004
+
+/* Description RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS
+
+ Status of rtt_fac_vht_ext80
+
+
+
+ <enum 0 location_fac_vht_ext80_status_not_valid>
+
+ <enum 1 location_fac_vht_ext80_status_valid>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_LSB 3
+#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008
+
+/* Description RX_LOCATION_INFO_2_RTT_FAC_SIFS
+
+ To support fine SIFS adjustment, need to provide FAC
+ value @ integer number of 320 MHz clock cycles to MAC. It
+ is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF
+ if it is a (V)HT/HE packet
+
+
+
+ 12 bits, signed, no fractional part
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_LSB 4
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_MASK 0x0000fff0
+
+/* Description RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS
+
+ Status of rtt_fac_sifs
+
+ 0: not valid
+
+ 1: valid and from L-LTF
+
+ 2: valid and from (V)HT/HE-LTF
+
+ 3: reserved
+
+ <legal 0-2>
+*/
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_LSB 16
+#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_MASK 0x00030000
+
+/* Description RX_LOCATION_INFO_2_RTT_CFR_STATUS
+
+ Status of channel frequency response dump
+
+
+
+ <enum 0 location_CFR_dump_not_valid>
+
+ <enum 1 location_CFR_dump_valid>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_LSB 18
+#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_MASK 0x00040000
+
+/* Description RX_LOCATION_INFO_2_RTT_CIR_STATUS
+
+ Status of channel impulse response dump
+
+
+
+ <enum 0 location_CIR_dump_not_valid>
+
+ <enum 1 location_CIR_dump_valid>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_LSB 19
+#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_MASK 0x00080000
+
+/* Description RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE
+
+ Channel dump size. It shows how many tones in CFR in
+ one chain, for example, it will show 52 for Legacy20 and 484
+ for VHT160
+
+
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_LSB 20
+#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000
+
+/* Description RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE
+
+ Indicator showing if HW IFFT mode or SW IFFT mode
+
+
+
+ <enum 0 location_sw_ifft_mode>
+
+ <enum 1 location_hw_ifft_mode>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_OFFSET 0x00000008
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_LSB 31
+#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_MASK 0x80000000
+
+/* Description RX_LOCATION_INFO_3_RTT_BTCF_STATUS
+
+ Indicate if BTCF is used to capture the timestamps
+
+
+
+ <enum 0 location_not_BTCF_based_ts>
+
+ <enum 1 location_BTCF_based_ts>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_LSB 0
+#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_MASK 0x00000001
+
+/* Description RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE
+
+ Indicate preamble type
+
+
+
+ <enum 0 location_preamble_type_legacy>
+
+ <enum 1 location_preamble_type_ht>
+
+ <enum 2 location_preamble_type_vht>
+
+ <enum 3 location_preamble_type_he_su_4xltf>
+
+ <enum 4 location_preamble_type_he_su_2xltf>
+
+ <enum 5 location_preamble_type_he_su_1xltf>
+
+ <enum 6
+ location_preamble_type_he_trigger_based_ul_4xltf>
+
+ <enum 7
+ location_preamble_type_he_trigger_based_ul_2xltf>
+
+ <enum 8
+ location_preamble_type_he_trigger_based_ul_1xltf>
+
+ <enum 9 location_preamble_type_he_mu_4xltf>
+
+ <enum 10 location_preamble_type_he_mu_2xltf>
+
+ <enum 11 location_preamble_type_he_mu_1xltf>
+
+ <enum 12
+ location_preamble_type_he_extended_range_su_4xltf>
+
+ <enum 13
+ location_preamble_type_he_extended_range_su_2xltf>
+
+ <enum 14
+ location_preamble_type_he_extended_range_su_1xltf>
+
+ <legal 0-14>
+*/
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_LSB 1
+#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_MASK 0x0000003e
+
+/* Description RX_LOCATION_INFO_3_RTT_PKT_BW_LEG
+
+ Indicate the bandwidth of L-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_LSB 6
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_MASK 0x000000c0
+
+/* Description RX_LOCATION_INFO_3_RTT_PKT_BW_VHT
+
+ Indicate the bandwidth of (V)HT/HE-LTF
+
+
+
+ <enum 0 location_pkt_bw_20MHz>
+
+ <enum 1 location_pkt_bw_40MHz>
+
+ <enum 2 location_pkt_bw_80MHz>
+
+ <enum 3 location_pkt_bw_160MHz>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_LSB 8
+#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_MASK 0x00000300
+
+/* Description RX_LOCATION_INFO_3_RTT_GI_TYPE
+
+ Indicate GI (guard interval) type
+
+
+
+ <enum 0 gi_0_8_us > HE related GI. Can also be used
+ for HE
+
+ <enum 1 gi_0_4_us > HE related GI. Can also be used
+ for HE
+
+ <enum 2 gi_1_6_us > HE related GI
+
+ <enum 3 gi_3_2_us > HE related GI
+
+ <legal 0 - 3>
+*/
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_LSB 10
+#define RX_LOCATION_INFO_3_RTT_GI_TYPE_MASK 0x00000c00
+
+/* Description RX_LOCATION_INFO_3_RTT_MCS_RATE
+
+ Bits 0~4 indicate MCS rate, if Legacy,
+
+ 0: 48 Mbps,
+
+ 1: 24 Mbps,
+
+ 2: 12 Mbps,
+
+ 3: 6 Mbps,
+
+ 4: 54 Mbps,
+
+ 5: 36 Mbps,
+
+ 6: 18 Mbps,
+
+ 7: 9 Mbps,
+
+
+
+ if HT, 0-7: MCS0-MCS7,
+
+ if VHT, 0-9: MCS0-MCS9,
+
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_LSB 12
+#define RX_LOCATION_INFO_3_RTT_MCS_RATE_MASK 0x0001f000
+
+/* Description RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN
+
+ For 20/40/80, this field shows the first selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected pri80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_LSB 17
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_MASK 0x000e0000
+
+/* Description RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80
+
+ For 20/40/80, this field shows the second selected Rx
+ chain that is used in HW IFFT mode
+
+
+
+ For 80+80, this field shows the selected ext80 Rx chain
+ that is used in HW IFFT mode
+
+
+
+ <enum 0 location_strongest_chain_is_0>
+
+ <enum 1 location_strongest_chain_is_1>
+
+ <enum 2 location_strongest_chain_is_2>
+
+ <enum 3 location_strongest_chain_is_3>
+
+ <enum 4 location_strongest_chain_is_4>
+
+ <enum 5 location_strongest_chain_is_5>
+
+ <enum 6 location_strongest_chain_is_6>
+
+ <enum 7 location_strongest_chain_is_7>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_LSB 20
+#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000
+
+/* Description RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK
+
+ Rx chain mask, each bit is a Rx chain
+
+ 0: the Rx chain is not used
+
+ 1: the Rx chain is used
+
+ Support up to 8 Rx chains
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_LSB 23
+#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_MASK 0x7f800000
+
+/* Description RX_LOCATION_INFO_3_RESERVED_3
+
+ <legal 0>
+*/
+#define RX_LOCATION_INFO_3_RESERVED_3_OFFSET 0x0000000c
+#define RX_LOCATION_INFO_3_RESERVED_3_LSB 31
+#define RX_LOCATION_INFO_3_RESERVED_3_MASK 0x80000000
+
+/* Description RX_LOCATION_INFO_4_RX_START_TS
+
+ RX packet start timestamp
+
+
+
+ It reports the time the first L-STF ADC sample arrived
+ at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_4_RX_START_TS_OFFSET 0x00000010
+#define RX_LOCATION_INFO_4_RX_START_TS_LSB 0
+#define RX_LOCATION_INFO_4_RX_START_TS_MASK 0xffffffff
+
+/* Description RX_LOCATION_INFO_5_RX_END_TS
+
+ RX packet end timestamp
+
+
+
+ It reports the time the last symbol's last ADC sample
+ arrived at RX antenna
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_5_RX_END_TS_OFFSET 0x00000014
+#define RX_LOCATION_INFO_5_RX_END_TS_LSB 0
+#define RX_LOCATION_INFO_5_RX_END_TS_MASK 0xffffffff
+
+/* Description RX_LOCATION_INFO_6_SFO_PHASE_PKT_START
+
+ The phase of the SFO of the first symbol's first FFT
+ input sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_OFFSET 0x00000018
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_LSB 0
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_MASK 0x00000fff
+
+/* Description RX_LOCATION_INFO_6_SFO_PHASE_PKT_END
+
+ The phase of the SFO of the last symbol's last FFT input
+ sample
+
+
+
+ 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to
+ 66.7ns, and 6 bits fraction to provide a resolution of
+ 0.03ns
+
+
+
+ clock unit is 480MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_OFFSET 0x00000018
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_LSB 12
+#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_MASK 0x00fff000
+
+/* Description RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8
+
+ The high 8 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 8 bits
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x00000018
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24
+#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000
+
+/* Description RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32
+
+ The low 32 bits of the 40 bits pointer pointed to the
+ external RTT channel information buffer
+
+
+
+ 32 bits
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000001c
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0
+#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff
+
+/* Description RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT
+
+ CFO measurement. Needed for passive locationing
+
+
+
+ 14 bits, signed 1.13. 13 bits fraction to provide a
+ resolution of 153 Hz
+
+
+
+ In units of cycles/800 ns
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_LSB 0
+#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_MASK 0x00003fff
+
+/* Description RX_LOCATION_INFO_8_RTT_CHAN_SPREAD
+
+ Channel delay spread measurement. Needed for selecting
+ GI length
+
+
+
+ 8 bits, unsigned. At 25 ns step. Can represent up to
+ 6375 ns
+
+
+
+ In units of cycles @ 40 MHz
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_LSB 14
+#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_MASK 0x003fc000
+
+/* Description RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL
+
+ Indicate which timing backoff value is used
+
+
+
+ <enum 0 timing_backoff_low_rssi>
+
+ <enum 1 timing_backoff_mid_rssi>
+
+ <enum 2 timing_backoff_high_rssi>
+
+ <enum 3 reserved>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_LSB 22
+#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000
+
+/* Description RX_LOCATION_INFO_8_RESERVED_8
+
+ <legal 0>
+*/
+#define RX_LOCATION_INFO_8_RESERVED_8_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RESERVED_8_LSB 24
+#define RX_LOCATION_INFO_8_RESERVED_8_MASK 0x7f000000
+
+/* Description RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID
+
+ <enum 0 rx_location_info_is_not_valid>
+
+ <enum 1 rx_location_info_is_valid>
+
+ <legal all>
+*/
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_OFFSET 0x00000020
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_LSB 31
+#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_MASK 0x80000000
+
+
+#endif // _RX_LOCATION_INFO_H_
diff --git a/hw/qca5018/rx_mpdu_desc_info.h b/hw/qca5018/rx_mpdu_desc_info.h
new file mode 100644
index 0000000..112c41f
--- /dev/null
+++ b/hw/qca5018/rx_mpdu_desc_info.h
@@ -0,0 +1,468 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 msdu_count[7:0], mpdu_sequence_number[19:8], fragment_flag[20], mpdu_retry_bit[21], ampdu_flag[22], bar_frame[23], pn_fields_contain_valid_info[24], sa_is_valid[25], sa_idx_timeout[26], da_is_valid[27], da_is_mcbc[28], da_idx_timeout[29], raw_mpdu[30], more_fragment_flag[31]
+// 1 peer_meta_data[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+ uint32_t msdu_count : 8, //[7:0]
+ mpdu_sequence_number : 12, //[19:8]
+ fragment_flag : 1, //[20]
+ mpdu_retry_bit : 1, //[21]
+ ampdu_flag : 1, //[22]
+ bar_frame : 1, //[23]
+ pn_fields_contain_valid_info : 1, //[24]
+ sa_is_valid : 1, //[25]
+ sa_idx_timeout : 1, //[26]
+ da_is_valid : 1, //[27]
+ da_is_mcbc : 1, //[28]
+ da_idx_timeout : 1, //[29]
+ raw_mpdu : 1, //[30]
+ more_fragment_flag : 1; //[31]
+ uint32_t peer_meta_data : 32; //[31:0]
+};
+
+/*
+
+msdu_count
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The number of MSDUs within the MPDU
+
+ <legal all>
+
+mpdu_sequence_number
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The field can have two different meanings based on the
+ setting of field 'BAR_frame':
+
+
+
+ 'BAR_frame' is NOT set:
+
+ The MPDU sequence number of the received frame.
+
+
+
+ 'BAR_frame' is set.
+
+ The MPDU Start sequence number from the BAR frame
+
+ <legal all>
+
+fragment_flag
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, this MPDU is a fragment and REO should forward
+ this fragment MPDU to the REO destination ring without any
+ reorder checks, pn checks or bitmap update. This implies
+ that REO is forwarding the pointer to the MSDU link
+ descriptor. The destination ring is coming from a
+ programmable register setting in REO
+
+
+
+ <legal all>
+
+mpdu_retry_bit
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The retry bit setting from the MPDU header of the
+ received frame
+
+ <legal all>
+
+ampdu_flag
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the MPDU was received as part of an A-MPDU.
+
+ <legal all>
+
+bar_frame
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the received frame is a BAR frame. After
+ processing, this frame shall be pushed to SW or deleted.
+
+ <legal all>
+
+pn_fields_contain_valid_info
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Copied here by RXDMA from RX_MPDU_END
+
+ When not set, REO will Not perform a PN sequence number
+ check
+
+sa_is_valid
+
+ When set, OLE found a valid SA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+
+sa_idx_timeout
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC source address search due to the expiration
+ of the search timer.
+
+ <legal all>
+
+da_is_valid
+
+ When set, OLE found a valid DA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+
+da_is_mcbc
+
+ Field Only valid if da_is_valid is set
+
+
+
+ When set, at least one of the DA addresses is a
+ Multicast or Broadcast address.
+
+ <legal all>
+
+da_idx_timeout
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC destination address search due to the
+ expiration of the search timer.
+
+ <legal all>
+
+raw_mpdu
+
+ Field only valid when first_msdu_in_mpdu_flag is set.
+
+
+
+ When set, the contents in the MSDU buffer contains a
+ 'RAW' MPDU. This 'RAW' MPDU might be spread out over
+ multiple MSDU buffers.
+
+ <legal all>
+
+more_fragment_flag
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+
+peer_meta_data
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+*/
+
+
+/* Description RX_MPDU_DESC_INFO_0_MSDU_COUNT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The number of MSDUs within the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff
+
+/* Description RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The field can have two different meanings based on the
+ setting of field 'BAR_frame':
+
+
+
+ 'BAR_frame' is NOT set:
+
+ The MPDU sequence number of the received frame.
+
+
+
+ 'BAR_frame' is set.
+
+ The MPDU Start sequence number from the BAR frame
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+/* Description RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, this MPDU is a fragment and REO should forward
+ this fragment MPDU to the REO destination ring without any
+ reorder checks, pn checks or bitmap update. This implies
+ that REO is forwarding the pointer to the MSDU link
+ descriptor. The destination ring is coming from a
+ programmable register setting in REO
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000
+
+/* Description RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The retry bit setting from the MPDU header of the
+ received frame
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000
+
+/* Description RX_MPDU_DESC_INFO_0_AMPDU_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the MPDU was received as part of an A-MPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000
+
+/* Description RX_MPDU_DESC_INFO_0_BAR_FRAME
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the received frame is a BAR frame. After
+ processing, this frame shall be pushed to SW or deleted.
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000
+
+/* Description RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Copied here by RXDMA from RX_MPDU_END
+
+ When not set, REO will Not perform a PN sequence number
+ check
+*/
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+/* Description RX_MPDU_DESC_INFO_0_SA_IS_VALID
+
+ When set, OLE found a valid SA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC source address search due to the expiration
+ of the search timer.
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000
+
+/* Description RX_MPDU_DESC_INFO_0_DA_IS_VALID
+
+ When set, OLE found a valid DA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000
+
+/* Description RX_MPDU_DESC_INFO_0_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ When set, at least one of the DA addresses is a
+ Multicast or Broadcast address.
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000
+
+/* Description RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC destination address search due to the
+ expiration of the search timer.
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000
+
+/* Description RX_MPDU_DESC_INFO_0_RAW_MPDU
+
+ Field only valid when first_msdu_in_mpdu_flag is set.
+
+
+
+ When set, the contents in the MSDU buffer contains a
+ 'RAW' MPDU. This 'RAW' MPDU might be spread out over
+ multiple MSDU buffers.
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000
+
+/* Description RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_OFFSET 0x00000000
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_LSB 31
+#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+/* Description RX_MPDU_DESC_INFO_1_PEER_META_DATA
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+*/
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff
+
+
+#endif // _RX_MPDU_DESC_INFO_H_
diff --git a/hw/qca5018/rx_mpdu_details.h b/hw/qca5018/rx_mpdu_details.h
new file mode 100644
index 0000000..a116b20
--- /dev/null
+++ b/hw/qca5018/rx_mpdu_details.h
@@ -0,0 +1,487 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct buffer_addr_info msdu_link_desc_addr_info;
+// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
+
+struct rx_mpdu_details {
+ struct buffer_addr_info msdu_link_desc_addr_info;
+ struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+};
+
+/*
+
+struct buffer_addr_info msdu_link_desc_addr_info
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Details of the physical address of the MSDU link
+ descriptor that contains pointers to MSDUs related to this
+ MPDU
+
+struct rx_mpdu_desc_info rx_mpdu_desc_info_details
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ General information related to the MPDU that should be
+*/
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */
+
+
+/* Description RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */
+
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The number of MSDUs within the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The field can have two different meanings based on the
+ setting of field 'BAR_frame':
+
+
+
+ 'BAR_frame' is NOT set:
+
+ The MPDU sequence number of the received frame.
+
+
+
+ 'BAR_frame' is set.
+
+ The MPDU Start sequence number from the BAR frame
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, this MPDU is a fragment and REO should forward
+ this fragment MPDU to the REO destination ring without any
+ reorder checks, pn checks or bitmap update. This implies
+ that REO is forwarding the pointer to the MSDU link
+ descriptor. The destination ring is coming from a
+ programmable register setting in REO
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ The retry bit setting from the MPDU header of the
+ received frame
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the MPDU was received as part of an A-MPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ When set, the received frame is a BAR frame. After
+ processing, this frame shall be pushed to SW or deleted.
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO
+
+ Consumer: REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Copied here by RXDMA from RX_MPDU_END
+
+ When not set, REO will Not perform a PN sequence number
+ check
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ When set, OLE found a valid SA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC source address search due to the expiration
+ of the search timer.
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ When set, OLE found a valid DA entry for all MSDUs in
+ this MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ When set, at least one of the DA addresses is a
+ Multicast or Broadcast address.
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ When set, at least 1 MSDU within the MPDU has an
+ unsuccessful MAC destination address search due to the
+ expiration of the search timer.
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Field only valid when first_msdu_in_mpdu_flag is set.
+
+
+
+ When set, the contents in the MSDU buffer contains a
+ 'RAW' MPDU. This 'RAW' MPDU might be spread out over
+ multiple MSDU buffers.
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000
+
+/* Description RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+*/
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+
+#endif // _RX_MPDU_DETAILS_H_
diff --git a/hw/qca5018/rx_mpdu_end.h b/hw/qca5018/rx_mpdu_end.h
new file mode 100644
index 0000000..b0b2c80
--- /dev/null
+++ b/hw/qca5018/rx_mpdu_end.h
@@ -0,0 +1,755 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
+// 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_END 2
+
+struct rx_mpdu_end {
+ uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
+ sw_frame_group_id : 7, //[8:2]
+ reserved_0 : 7, //[15:9]
+ phy_ppdu_id : 16; //[31:16]
+ uint32_t reserved_1a : 11, //[10:0]
+ unsup_ktype_short_frame : 1, //[11]
+ rx_in_tx_decrypt_byp : 1, //[12]
+ overflow_err : 1, //[13]
+ mpdu_length_err : 1, //[14]
+ tkip_mic_err : 1, //[15]
+ decrypt_err : 1, //[16]
+ unencrypted_frame_err : 1, //[17]
+ pn_fields_contain_valid_info : 1, //[18]
+ fcs_err : 1, //[19]
+ msdu_length_err : 1, //[20]
+ rxdma0_destination_ring : 2, //[22:21]
+ rxdma1_destination_ring : 2, //[24:23]
+ decrypt_status_code : 3, //[27:25]
+ rx_bitmap_not_updated : 1, //[28]
+ reserved_1b : 3; //[31:29]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+ <legal 0-2>
+
+sw_frame_group_id
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame>
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+
+
+
+
+
+ <legal 0-37>
+
+reserved_0
+
+ <legal 0>
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+
+reserved_1a
+
+ <legal 0>
+
+unsup_ktype_short_frame
+
+ This bit will be '1' when WEP or TKIP or WAPI key type
+ is received for 11ah short frame. Crypto will bypass the
+ received packet without decryption to RxOLE after setting
+ this bit.
+
+rx_in_tx_decrypt_byp
+
+ Indicates that RX packet is not decrypted as Crypto is
+ busy with TX packet processing.
+
+overflow_err
+
+ RXPCU Receive FIFO ran out of space to receive the full
+ MPDU. Therefor this MPDU is terminated early and is thus
+ corrupted.
+
+
+
+ This MPDU will not be ACKed.
+
+ RXPCU might still be able to correctly receive the
+ following MPDUs in the PPDU if enough fifo space became
+ available in time
+
+mpdu_length_err
+
+ Set by RXPCU if the expected MPDU length does not
+ correspond with the actually received number of bytes in the
+ MPDU.
+
+tkip_mic_err
+
+ Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
+ for this MPDU
+
+decrypt_err
+
+ Set by RX CRYPTO when CRYPTO detected a decrypt error
+ for this MPDU or CRYPTO received an encrypted frame, but did
+ not get a valid corresponding key id in the peer entry.
+
+unencrypted_frame_err
+
+ Set by RX CRYPTO when CRYPTO detected an unencrypted
+ frame while in the peer entry field
+ 'All_frames_shall_be_encrypted' is set.
+
+pn_fields_contain_valid_info
+
+ Set by RX CRYPTO to indicate that there is a valid PN
+ field present in this MPDU
+
+fcs_err
+
+ Set by RXPCU when there is an FCS error detected for
+ this MPDU
+
+ NOTE that when this field is set, all other (error)
+ field settings should be ignored as modules could have made
+ wrong decisions based on the corrupted data.
+
+msdu_length_err
+
+ Set by RXOLE when there is an msdu length error detected
+ in at least 1 of the MSDUs embedded within the MPDU
+
+rxdma0_destination_ring
+
+ The ring to which RXDMA0 shall push the frame, assuming
+ no MPDU level errors are detected. In case of MPDU level
+ errors, RXDMA0 might change the RXDMA0 destination
+
+
+
+ <enum 0 rxdma_release_ring > RXDMA0 shall push the
+ frame to the Release ring. Effectively this means the frame
+ needs to be dropped.
+
+
+
+ <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
+ the FW ring
+
+
+
+ <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
+ the SW ring
+
+
+
+ <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
+ to the REO entrance ring
+
+
+
+ <legal all>
+
+rxdma1_destination_ring
+
+ The ring to which RXDMA1 shall push the frame, assuming
+ no MPDU level errors are detected. In case of MPDU level
+ errors, RXDMA1 might change the RXDMA destination
+
+
+
+ <enum 0 rxdma_release_ring > RXDMA1 shall push the
+ frame to the Release ring. Effectively this means the frame
+ needs to be dropped.
+
+
+
+ <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
+ the FW ring
+
+
+
+ <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
+ the SW ring
+
+
+
+ <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
+ to the REO entrance ring
+
+
+
+ <legal all>
+
+decrypt_status_code
+
+ Field provides insight into the decryption performed
+
+
+
+ <enum 0 decrypt_ok> Frame had protection enabled and
+ decrypted properly
+
+ <enum 1 decrypt_unprotected_frame > Frame is unprotected
+ and hence bypassed
+
+ <enum 2 decrypt_data_err > Frame has protection enabled
+ and could not be properly decrypted due to MIC/ICV mismatch
+ etc.
+
+ <enum 3 decrypt_key_invalid > Frame has protection
+ enabled but the key that was required to decrypt this frame
+ was not valid
+
+ <enum 4 decrypt_peer_entry_invalid > Frame has
+ protection enabled but the key that was required to decrypt
+ this frame was not valid
+
+ <enum 5 decrypt_other > Reserved for other indications
+
+
+
+ <legal 0 - 5>
+
+rx_bitmap_not_updated
+
+ Frame is received, but RXPCU could not update the
+ receive bitmap due to (temporary) fifo contraints.
+
+ <legal all>
+
+reserved_1b
+
+ <legal 0>
+*/
+
+
+/* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+ <legal 0-2>
+*/
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+/* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame>
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+
+
+
+
+
+ <legal 0-37>
+*/
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+/* Description RX_MPDU_END_0_RESERVED_0
+
+ <legal 0>
+*/
+#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000
+#define RX_MPDU_END_0_RESERVED_0_LSB 9
+#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00
+
+/* Description RX_MPDU_END_0_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description RX_MPDU_END_1_RESERVED_1A
+
+ <legal 0>
+*/
+#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_MPDU_END_1_RESERVED_1A_LSB 0
+#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff
+
+/* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME
+
+ This bit will be '1' when WEP or TKIP or WAPI key type
+ is received for 11ah short frame. Crypto will bypass the
+ received packet without decryption to RxOLE after setting
+ this bit.
+*/
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800
+
+/* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP
+
+ Indicates that RX packet is not decrypted as Crypto is
+ busy with TX packet processing.
+*/
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000
+
+/* Description RX_MPDU_END_1_OVERFLOW_ERR
+
+ RXPCU Receive FIFO ran out of space to receive the full
+ MPDU. Therefor this MPDU is terminated early and is thus
+ corrupted.
+
+
+
+ This MPDU will not be ACKed.
+
+ RXPCU might still be able to correctly receive the
+ following MPDUs in the PPDU if enough fifo space became
+ available in time
+*/
+#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13
+#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000
+
+/* Description RX_MPDU_END_1_MPDU_LENGTH_ERR
+
+ Set by RXPCU if the expected MPDU length does not
+ correspond with the actually received number of bytes in the
+ MPDU.
+*/
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000
+
+/* Description RX_MPDU_END_1_TKIP_MIC_ERR
+
+ Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
+ for this MPDU
+*/
+#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15
+#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000
+
+/* Description RX_MPDU_END_1_DECRYPT_ERR
+
+ Set by RX CRYPTO when CRYPTO detected a decrypt error
+ for this MPDU or CRYPTO received an encrypted frame, but did
+ not get a valid corresponding key id in the peer entry.
+*/
+#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16
+#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000
+
+/* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR
+
+ Set by RX CRYPTO when CRYPTO detected an unencrypted
+ frame while in the peer entry field
+ 'All_frames_shall_be_encrypted' is set.
+*/
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000
+
+/* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO
+
+ Set by RX CRYPTO to indicate that there is a valid PN
+ field present in this MPDU
+*/
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000
+
+/* Description RX_MPDU_END_1_FCS_ERR
+
+ Set by RXPCU when there is an FCS error detected for
+ this MPDU
+
+ NOTE that when this field is set, all other (error)
+ field settings should be ignored as modules could have made
+ wrong decisions based on the corrupted data.
+*/
+#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_FCS_ERR_LSB 19
+#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000
+
+/* Description RX_MPDU_END_1_MSDU_LENGTH_ERR
+
+ Set by RXOLE when there is an msdu length error detected
+ in at least 1 of the MSDUs embedded within the MPDU
+*/
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000
+
+/* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING
+
+ The ring to which RXDMA0 shall push the frame, assuming
+ no MPDU level errors are detected. In case of MPDU level
+ errors, RXDMA0 might change the RXDMA0 destination
+
+
+
+ <enum 0 rxdma_release_ring > RXDMA0 shall push the
+ frame to the Release ring. Effectively this means the frame
+ needs to be dropped.
+
+
+
+ <enum 1 rxdma2fw_ring > RXDMA0 shall push the frame to
+ the FW ring
+
+
+
+ <enum 2 rxdma2sw_ring > RXDMA0 shall push the frame to
+ the SW ring
+
+
+
+ <enum 3 rxdma2reo_ring > RXDMA0 shall push the frame
+ to the REO entrance ring
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000
+
+/* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING
+
+ The ring to which RXDMA1 shall push the frame, assuming
+ no MPDU level errors are detected. In case of MPDU level
+ errors, RXDMA1 might change the RXDMA destination
+
+
+
+ <enum 0 rxdma_release_ring > RXDMA1 shall push the
+ frame to the Release ring. Effectively this means the frame
+ needs to be dropped.
+
+
+
+ <enum 1 rxdma2fw_ring > RXDMA1 shall push the frame to
+ the FW ring
+
+
+
+ <enum 2 rxdma2sw_ring > RXDMA1 shall push the frame to
+ the SW ring
+
+
+
+ <enum 3 rxdma2reo_ring > RXDMA1 shall push the frame
+ to the REO entrance ring
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000
+
+/* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE
+
+ Field provides insight into the decryption performed
+
+
+
+ <enum 0 decrypt_ok> Frame had protection enabled and
+ decrypted properly
+
+ <enum 1 decrypt_unprotected_frame > Frame is unprotected
+ and hence bypassed
+
+ <enum 2 decrypt_data_err > Frame has protection enabled
+ and could not be properly decrypted due to MIC/ICV mismatch
+ etc.
+
+ <enum 3 decrypt_key_invalid > Frame has protection
+ enabled but the key that was required to decrypt this frame
+ was not valid
+
+ <enum 4 decrypt_peer_entry_invalid > Frame has
+ protection enabled but the key that was required to decrypt
+ this frame was not valid
+
+ <enum 5 decrypt_other > Reserved for other indications
+
+
+
+ <legal 0 - 5>
+*/
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000
+
+/* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED
+
+ Frame is received, but RXPCU could not update the
+ receive bitmap due to (temporary) fifo contraints.
+
+ <legal all>
+*/
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000
+
+/* Description RX_MPDU_END_1_RESERVED_1B
+
+ <legal 0>
+*/
+#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004
+#define RX_MPDU_END_1_RESERVED_1B_LSB 29
+#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000
+
+
+#endif // _RX_MPDU_END_H_
diff --git a/hw/qca5018/rx_mpdu_info.h b/hw/qca5018/rx_mpdu_info.h
new file mode 100644
index 0000000..47a3ed4
--- /dev/null
+++ b/hw/qca5018/rx_mpdu_info.h
@@ -0,0 +1,3385 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rxpt_classify_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct rxpt_classify_info rxpt_classify_info_details;
+// 1 rx_reo_queue_desc_addr_31_0[31:0]
+// 2 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_2a[31:26]
+// 3 pn_31_0[31:0]
+// 4 pn_63_32[31:0]
+// 5 pn_95_64[31:0]
+// 6 pn_127_96[31:0]
+// 7 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], wep_key_width_for_variable_key[7:6], mesh_sta[9:8], bssid_hit[10], bssid_number[14:11], tid[18:15], reserved_7a[31:19]
+// 8 peer_meta_data[31:0]
+// 9 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_9a[15:14], phy_ppdu_id[31:16]
+// 10 ast_index[15:0], sw_peer_id[31:16]
+// 11 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], mpdu_fragment_number[13:10], more_fragment_flag[14], reserved_11a[15], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20]
+// 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], raw_mpdu[30], reserved_12[31]
+// 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], amsdu_present[30], reserved_13[31]
+// 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16]
+// 15 mac_addr_ad1_31_0[31:0]
+// 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16]
+// 17 mac_addr_ad2_47_16[31:0]
+// 18 mac_addr_ad3_31_0[31:0]
+// 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16]
+// 20 mac_addr_ad4_31_0[31:0]
+// 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16]
+// 22 mpdu_ht_control_field[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_INFO 23
+
+struct rx_mpdu_info {
+ struct rxpt_classify_info rxpt_classify_info_details;
+ uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0]
+ uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0]
+ receive_queue_number : 16, //[23:8]
+ pre_delim_err_warning : 1, //[24]
+ first_delim_err : 1, //[25]
+ reserved_2a : 6; //[31:26]
+ uint32_t pn_31_0 : 32; //[31:0]
+ uint32_t pn_63_32 : 32; //[31:0]
+ uint32_t pn_95_64 : 32; //[31:0]
+ uint32_t pn_127_96 : 32; //[31:0]
+ uint32_t epd_en : 1, //[0]
+ all_frames_shall_be_encrypted : 1, //[1]
+ encrypt_type : 4, //[5:2]
+ wep_key_width_for_variable_key : 2, //[7:6]
+ mesh_sta : 2, //[9:8]
+ bssid_hit : 1, //[10]
+ bssid_number : 4, //[14:11]
+ tid : 4, //[18:15]
+ reserved_7a : 13; //[31:19]
+ uint32_t peer_meta_data : 32; //[31:0]
+ uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
+ sw_frame_group_id : 7, //[8:2]
+ ndp_frame : 1, //[9]
+ phy_err : 1, //[10]
+ phy_err_during_mpdu_header : 1, //[11]
+ protocol_version_err : 1, //[12]
+ ast_based_lookup_valid : 1, //[13]
+ reserved_9a : 2, //[15:14]
+ phy_ppdu_id : 16; //[31:16]
+ uint32_t ast_index : 16, //[15:0]
+ sw_peer_id : 16; //[31:16]
+ uint32_t mpdu_frame_control_valid : 1, //[0]
+ mpdu_duration_valid : 1, //[1]
+ mac_addr_ad1_valid : 1, //[2]
+ mac_addr_ad2_valid : 1, //[3]
+ mac_addr_ad3_valid : 1, //[4]
+ mac_addr_ad4_valid : 1, //[5]
+ mpdu_sequence_control_valid : 1, //[6]
+ mpdu_qos_control_valid : 1, //[7]
+ mpdu_ht_control_valid : 1, //[8]
+ frame_encryption_info_valid : 1, //[9]
+ mpdu_fragment_number : 4, //[13:10]
+ more_fragment_flag : 1, //[14]
+ reserved_11a : 1, //[15]
+ fr_ds : 1, //[16]
+ to_ds : 1, //[17]
+ encrypted : 1, //[18]
+ mpdu_retry : 1, //[19]
+ mpdu_sequence_number : 12; //[31:20]
+ uint32_t key_id_octet : 8, //[7:0]
+ new_peer_entry : 1, //[8]
+ decrypt_needed : 1, //[9]
+ decap_type : 2, //[11:10]
+ rx_insert_vlan_c_tag_padding : 1, //[12]
+ rx_insert_vlan_s_tag_padding : 1, //[13]
+ strip_vlan_c_tag_decap : 1, //[14]
+ strip_vlan_s_tag_decap : 1, //[15]
+ pre_delim_count : 12, //[27:16]
+ ampdu_flag : 1, //[28]
+ bar_frame : 1, //[29]
+ raw_mpdu : 1, //[30]
+ reserved_12 : 1; //[31]
+ uint32_t mpdu_length : 14, //[13:0]
+ first_mpdu : 1, //[14]
+ mcast_bcast : 1, //[15]
+ ast_index_not_found : 1, //[16]
+ ast_index_timeout : 1, //[17]
+ power_mgmt : 1, //[18]
+ non_qos : 1, //[19]
+ null_data : 1, //[20]
+ mgmt_type : 1, //[21]
+ ctrl_type : 1, //[22]
+ more_data : 1, //[23]
+ eosp : 1, //[24]
+ fragment_flag : 1, //[25]
+ order : 1, //[26]
+ u_apsd_trigger : 1, //[27]
+ encrypt_required : 1, //[28]
+ directed : 1, //[29]
+ amsdu_present : 1, //[30]
+ reserved_13 : 1; //[31]
+ uint32_t mpdu_frame_control_field : 16, //[15:0]
+ mpdu_duration_field : 16; //[31:16]
+ uint32_t mac_addr_ad1_31_0 : 32; //[31:0]
+ uint32_t mac_addr_ad1_47_32 : 16, //[15:0]
+ mac_addr_ad2_15_0 : 16; //[31:16]
+ uint32_t mac_addr_ad2_47_16 : 32; //[31:0]
+ uint32_t mac_addr_ad3_31_0 : 32; //[31:0]
+ uint32_t mac_addr_ad3_47_32 : 16, //[15:0]
+ mpdu_sequence_control_field : 16; //[31:16]
+ uint32_t mac_addr_ad4_31_0 : 32; //[31:0]
+ uint32_t mac_addr_ad4_47_32 : 16, //[15:0]
+ mpdu_qos_control_field : 16; //[31:16]
+ uint32_t mpdu_ht_control_field : 32; //[31:0]
+};
+
+/*
+
+struct rxpt_classify_info rxpt_classify_info_details
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ RXOLE related classification info
+
+ <legal all
+
+rx_reo_queue_desc_addr_31_0
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+
+
+ If no Peer entry lookup happened for this frame, the
+ value wil be set to 0, and the frame shall never be pushed
+ to REO entrance ring.
+
+ <legal all>
+
+rx_reo_queue_desc_addr_39_32
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+
+
+ If no Peer entry lookup happened for this frame, the
+ value wil be set to 0, and the frame shall never be pushed
+ to REO entrance ring.
+
+ <legal all>
+
+receive_queue_number
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Indicates the MPDU queue ID to which this MPDU link
+ descriptor belongs
+
+ Used for tracking and debugging
+
+ <legal all>
+
+pre_delim_err_warning
+
+ Indicates that a delimiter FCS error was found in
+ between the Previous MPDU and this MPDU.
+
+
+
+ Note that this is just a warning, and does not mean that
+ this MPDU is corrupted in any way. If it is, there will be
+ other errors indicated such as FCS or decrypt errors
+
+
+
+ In case of ndp or phy_err, this field will indicate at
+ least one of delimiters located after the last MPDU in the
+ previous PPDU has been corrupted.
+
+first_delim_err
+
+ Indicates that the first delimiter had a FCS failure.
+ Only valid when first_mpdu and first_msdu are set.
+
+
+
+
+reserved_2a
+
+ <legal 0>
+
+pn_31_0
+
+
+
+
+
+ WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0]
+ is valid.
+
+ TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
+ WEPSeed[1], pn1}. Only pn[47:0] is valid.
+
+ AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0,
+ pn1, pn0}. Only pn[47:0] is valid.
+
+ WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12,
+ pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1,
+ pn0}. pn[127:0] are valid.
+
+
+
+
+pn_63_32
+
+
+
+
+ Bits [63:32] of the PN number. See description for
+ pn_31_0.
+
+
+
+
+pn_95_64
+
+
+
+
+ Bits [95:64] of the PN number. See description for
+ pn_31_0.
+
+
+
+
+pn_127_96
+
+
+
+
+ Bits [127:96] of the PN number. See description for
+ pn_31_0.
+
+
+
+
+epd_en
+
+ Field only valid when AST_based_lookup_valid == 1.
+
+
+
+
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ If set to one use EPD instead of LPD
+
+
+
+
+ <legal all>
+
+all_frames_shall_be_encrypted
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, all frames (data only ?) shall be encrypted.
+ If not, RX CRYPTO shall set an error flag.
+
+ <legal all>
+
+encrypt_type
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Indicates type of decrypt cipher used (as defined in the
+ peer entry)
+
+
+
+ <enum 0 wep_40> WEP 40-bit
+
+ <enum 1 wep_104> WEP 104-bit
+
+ <enum 2 tkip_no_mic> TKIP without MIC
+
+ <enum 3 wep_128> WEP 128-bit
+
+ <enum 4 tkip_with_mic> TKIP with MIC
+
+ <enum 5 wapi> WAPI
+
+ <enum 6 aes_ccmp_128> AES CCMP 128
+
+ <enum 7 no_cipher> No crypto
+
+ <enum 8 aes_ccmp_256> AES CCMP 256
+
+ <enum 9 aes_gcmp_128> AES CCMP 128
+
+ <enum 10 aes_gcmp_256> AES CCMP 256
+
+ <enum 11 wapi_gcm_sm4> WAPI GCM SM4
+
+
+
+ <enum 12 wep_varied_width> WEP encryption. As for WEP
+ per keyid the key bit width can vary, the key bit width for
+ this MPDU will be indicated in field
+ wep_key_width_for_variable key
+
+ <legal 0-12>
+
+wep_key_width_for_variable_key
+
+ Field only valid when key_type is set to
+ wep_varied_width.
+
+
+
+ This field indicates the size of the wep key for this
+ MPDU.
+
+
+
+ <enum 0 wep_varied_width_40> WEP 40-bit
+
+ <enum 1 wep_varied_width_104> WEP 104-bit
+
+ <enum 2 wep_varied_width_128> WEP 128-bit
+
+
+
+ <legal 0-2>
+
+mesh_sta
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, this is a Mesh (11s) STA.
+
+
+
+ The interpretation of the A-MSDU 'Length' field in the
+ MPDU (if any) is decided by the e-numerations below.
+
+
+
+ <enum 0 MESH_DISABLE>
+
+ <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and
+ includes the length of Mesh Control.
+
+ <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and
+ excludes the length of Mesh Control.
+
+ <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian
+ and excludes the length of Mesh Control. This is
+ 802.11s-compliant.
+
+ <legal all>
+
+bssid_hit
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, the BSSID of the incoming frame matched one of
+ the 8 BSSID register values
+
+
+
+ <legal all>
+
+bssid_number
+
+ Field only valid when bssid_hit is set.
+
+
+
+ This number indicates which one out of the 8 BSSID
+ register values matched the incoming frame
+
+ <legal all>
+
+tid
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The TID field in the QoS control field
+
+ <legal all>
+
+reserved_7a
+
+ <legal 0>
+
+peer_meta_data
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+
+rxpcu_mpdu_filter_in_category
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+
+
+ Note: for ndp frame, if it was expected because the
+ preceding NDPA was filter_pass, the setting
+ rxpcu_filter_pass will be used. This setting will also be
+ used for every ndp frame in case Promiscuous mode is
+ enabled.
+
+
+
+ In case promiscuous is not enabled, and an NDP is not
+ preceded by a NPDA filter pass frame, the only other setting
+ that could appear here for the NDP is rxpcu_monitor_other.
+
+ (rxpcu has a configuration bit specifically for this
+ scenario)
+
+
+
+ Note: for
+
+ <legal 0-2>
+
+sw_frame_group_id
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame> Note: The
+ corresponding Rxpcu_Mpdu_filter_in_category can be
+ rxpcu_filter_pass or rxpcu_monitor_other
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+ Note: The corresponding Rxpcu_Mpdu_filter_in_category
+ can only be rxpcu_monitor_other
+
+
+
+
+ Note: The corresponding Rxpcu_Mpdu_filter_in_category
+ can be rxpcu_filter_pass
+
+
+
+ <legal 0-37>
+
+ndp_frame
+
+ When set, the received frame was an NDP frame, and thus
+ there will be no MPDU data.
+
+ <legal all>
+
+phy_err
+
+ When set, a PHY error was received before MAC received
+ any data, and thus there will be no MPDU data.
+
+ <legal all>
+
+phy_err_during_mpdu_header
+
+ When set, a PHY error was received before MAC received
+ the complete MPDU header which was needed for proper
+ decoding
+
+ <legal all>
+
+protocol_version_err
+
+ Set when RXPCU detected a version error in the Frame
+ control field
+
+ <legal all>
+
+ast_based_lookup_valid
+
+ When set, AST based lookup for this frame has found a
+ valid result.
+
+
+
+ Note that for NDP frame this will never be set
+
+ <legal all>
+
+reserved_9a
+
+ <legal 0>
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+
+ast_index
+
+ This field indicates the index of the AST entry
+ corresponding to this MPDU. It is provided by the GSE module
+ instantiated in RXPCU.
+
+ A value of 0xFFFF indicates an invalid AST index,
+ meaning that No AST entry was found or NO AST search was
+ performed
+
+
+
+ In case of ndp or phy_err, this field will be set to
+ 0xFFFF
+
+ <legal all>
+
+sw_peer_id
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ This field indicates a unique peer identifier. It is set
+ equal to field 'sw_peer_id' from the AST entry
+
+
+
+ <legal all>
+
+mpdu_frame_control_valid
+
+ When set, the field Mpdu_Frame_control_field has valid
+ information
+
+
+
+
+ <legal all>
+
+mpdu_duration_valid
+
+ When set, the field Mpdu_duration_field has valid
+ information
+
+
+
+
+ <legal all>
+
+mac_addr_ad1_valid
+
+ When set, the fields mac_addr_ad1_..... have valid
+ information
+
+
+
+
+ <legal all>
+
+mac_addr_ad2_valid
+
+ When set, the fields mac_addr_ad2_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+
+mac_addr_ad3_valid
+
+ When set, the fields mac_addr_ad3_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+
+mac_addr_ad4_valid
+
+ When set, the fields mac_addr_ad4_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+
+mpdu_sequence_control_valid
+
+ When set, the fields mpdu_sequence_control_field and
+ mpdu_sequence_number have valid information as well as field
+
+
+
+ For MPDUs without a sequence control field, this field
+ will not be set.
+
+
+
+
+ <legal all>
+
+mpdu_qos_control_valid
+
+ When set, the field mpdu_qos_control_field has valid
+ information
+
+
+
+ For MPDUs without a QoS control field, this field will
+ not be set.
+
+
+
+
+ <legal all>
+
+mpdu_ht_control_valid
+
+ When set, the field mpdu_HT_control_field has valid
+ information
+
+
+
+ For MPDUs without a HT control field, this field will
+ not be set.
+
+
+
+
+ <legal all>
+
+frame_encryption_info_valid
+
+ When set, the encryption related info fields, like IV
+ and PN are valid
+
+
+
+ For MPDUs that are not encrypted, this will not be set.
+
+
+
+
+ <legal all>
+
+mpdu_fragment_number
+
+ Field only valid when Mpdu_sequence_control_valid is set
+ AND Fragment_flag is set
+
+
+
+ The fragment number from the 802.11 header
+
+
+
+ <legal all>
+
+more_fragment_flag
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+
+reserved_11a
+
+ <legal 0>
+
+fr_ds
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ Set if the from DS bit is set in the frame control.
+
+ <legal all>
+
+to_ds
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ Set if the to DS bit is set in the frame control.
+
+ <legal all>
+
+encrypted
+
+ Field only valid when Mpdu_frame_control_valid is set.
+
+
+
+ Protected bit from the frame control.
+
+ <legal all>
+
+mpdu_retry
+
+ Field only valid when Mpdu_frame_control_valid is set.
+
+
+
+ Retry bit from the frame control. Only valid when
+ first_msdu is set.
+
+ <legal all>
+
+mpdu_sequence_number
+
+ Field only valid when Mpdu_sequence_control_valid is
+ set.
+
+
+
+ The sequence number from the 802.11 header.
+
+ <legal all>
+
+key_id_octet
+
+
+
+
+ The key ID octet from the IV.
+
+
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+ <legal all>
+
+new_peer_entry
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Set if new RX_PEER_ENTRY TLV follows. If clear,
+ RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either
+ uses old peer entry or not decrypt.
+
+ <legal all>
+
+decrypt_needed
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Set if decryption is needed.
+
+
+
+ Note:
+
+ When RXPCU sets bit 'ast_index_not_found' and/or
+ ast_index_timeout', RXPCU will also ensure that this bit is
+ NOT set
+
+ CRYPTO for that reason only needs to evaluate this bit
+ and non of the other ones.
+
+ <legal all>
+
+decap_type
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Used by the OLE during decapsulation.
+
+
+
+ Indicates the decapsulation that HW will perform:
+
+
+
+ <enum 0 RAW> No encapsulation
+
+ <enum 1 Native_WiFi>
+
+ <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses
+ SNAP/LLC)
+
+ <enum 3 802_3> Indicate Ethernet
+
+
+
+ <legal all>
+
+rx_insert_vlan_c_tag_padding
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Insert 4 byte of all zeros as VLAN tag if the rx payload
+ does not have VLAN. Used during decapsulation.
+
+ <legal all>
+
+rx_insert_vlan_s_tag_padding
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Insert 4 byte of all zeros as double VLAN tag if the rx
+ payload does not have VLAN. Used during
+
+ <legal all>
+
+strip_vlan_c_tag_decap
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Strip the VLAN during decapsulation. Used by the OLE.
+
+ <legal all>
+
+strip_vlan_s_tag_decap
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Strip the double VLAN during decapsulation. Used by
+ the OLE.
+
+ <legal all>
+
+pre_delim_count
+
+ The number of delimiters before this MPDU.
+
+
+
+ Note that this number is cleared at PPDU start.
+
+
+
+ If this MPDU is the first received MPDU in the PPDU and
+ this MPDU gets filtered-in, this field will indicate the
+ number of delimiters located after the last MPDU in the
+ previous PPDU.
+
+
+
+ If this MPDU is located after the first received MPDU in
+ an PPDU, this field will indicate the number of delimiters
+ located between the previous MPDU and this MPDU.
+
+
+
+ In case of ndp or phy_err, this field will indicate the
+ number of delimiters located after the last MPDU in the
+ previous PPDU.
+
+ <legal all>
+
+ampdu_flag
+
+ When set, received frame was part of an A-MPDU.
+
+
+
+
+ <legal all>
+
+bar_frame
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, received frame is a BAR frame
+
+ <legal all>
+
+raw_mpdu
+
+ Consumer: SW
+
+ Producer: RXOLE
+
+
+
+ RXPCU sets this field to 0 and RXOLE overwrites it.
+
+
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+
+reserved_12
+
+ <legal 0>
+
+mpdu_length
+
+ In case of ndp or phy_err this field will be set to 0
+
+
+
+ MPDU length before decapsulation.
+
+ <legal all>
+
+first_mpdu
+
+ See definition in RX attention descriptor
+
+
+
+ In case of ndp or phy_err, this field will be set. Note
+ however that there will not actually be any data contents in
+ the MPDU.
+
+ <legal all>
+
+mcast_bcast
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+ast_index_not_found
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+ast_index_timeout
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+power_mgmt
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+non_qos
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 1
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+null_data
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+mgmt_type
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+ctrl_type
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+more_data
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+eosp
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+fragment_flag
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+order
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+
+
+ <legal all>
+
+u_apsd_trigger
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+encrypt_required
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+directed
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+
+amsdu_present
+
+ Field only valid when Mpdu_qos_control_valid is set
+
+
+
+ The 'amsdu_present' bit within the QoS control field of
+ the MPDU
+
+ <legal all>
+
+reserved_13
+
+ <legal 0>
+
+mpdu_frame_control_field
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ The frame control field of this received MPDU.
+
+
+
+ Field only valid when Ndp_frame and phy_err are NOT set
+
+
+
+ Bytes 0 + 1 of the received MPDU
+
+ <legal all>
+
+mpdu_duration_field
+
+ Field only valid when Mpdu_duration_valid is set
+
+
+
+ The duration field of this received MPDU.
+
+ <legal all>
+
+mac_addr_ad1_31_0
+
+ Field only valid when mac_addr_ad1_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD1
+
+ <legal all>
+
+mac_addr_ad1_47_32
+
+ Field only valid when mac_addr_ad1_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD1
+
+ <legal all>
+
+mac_addr_ad2_15_0
+
+ Field only valid when mac_addr_ad2_valid is set
+
+
+
+ The Least Significant 2 bytes of the Received Frames MAC
+ Address AD2
+
+ <legal all>
+
+mac_addr_ad2_47_16
+
+ Field only valid when mac_addr_ad2_valid is set
+
+
+
+ The 4 most significant bytes of the Received Frames MAC
+ Address AD2
+
+ <legal all>
+
+mac_addr_ad3_31_0
+
+ Field only valid when mac_addr_ad3_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD3
+
+ <legal all>
+
+mac_addr_ad3_47_32
+
+ Field only valid when mac_addr_ad3_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD3
+
+ <legal all>
+
+mpdu_sequence_control_field
+
+
+
+
+ The sequence control field of the MPDU
+
+ <legal all>
+
+mac_addr_ad4_31_0
+
+ Field only valid when mac_addr_ad4_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD4
+
+ <legal all>
+
+mac_addr_ad4_47_32
+
+ Field only valid when mac_addr_ad4_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD4
+
+ <legal all>
+
+mpdu_qos_control_field
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The sequence control field of the MPDU
+
+ <legal all>
+
+mpdu_ht_control_field
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The HT control field of the MPDU
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */
+
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB
+
+ If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb
+ is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1,
+ hash[3:0]} using the chosen Toeplitz hash from Common Parser
+ if flow search fails.
+
+ If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb
+ 's not 2'b00, Rx OLE uses a REO desination indication of
+ {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash
+ from Common Parser if flow search fails.
+
+ This LMAC/peer-based routing is not supported in
+ Hastings80 and HastingsPrime.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY
+
+ Indication to Rx OLE to enable REO destination routing
+ based on the chosen Toeplitz hash from Common Parser, in
+ case flow search fails
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA
+
+ Filter pass Unicast data frame (matching
+ rxpcu_filter_pass and sw_frame_group_Unicast_data) routing
+ selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA
+
+ Filter pass Multicast data frame (matching
+ rxpcu_filter_pass and sw_frame_group_Multicast_data) routing
+ selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000
+
+ Filter pass BAR frame (matching rxpcu_filter_pass and
+ sw_frame_group_ctrl_1000) routing selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION
+
+ Field only valid when for the received frame type the
+ corresponding pkt_selection_fp_... bit is set
+
+
+
+ <enum 0 wbm2rxdma_buf_source_ring> The data buffer for
+
+ <enum 1 fw2rxdma_buf_source_ring> The data buffer for
+ this frame shall be sourced by fw2rxdma buffer source ring.
+
+ <enum 2 sw2rxdma_buf_source_ring> The data buffer for
+ this frame shall be sourced by sw2rxdma buffer source ring.
+
+ <enum 3 no_buffer_ring> The frame shall not be written
+ to any data buffer.
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION
+
+ Field only valid when for the received frame type the
+ corresponding pkt_selection_fp_... bit is set
+
+
+
+ <enum 0 rxdma_release_ring> RXDMA0 shall push the frame
+ to the Release ring. Effectively this means the frame needs
+ to be dropped.
+
+ <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to
+ the FW ring.
+
+ <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to
+ the SW ring.
+
+ <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to
+ the REO entrance ring.
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
+
+/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B
+
+ <legal 0>
+*/
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15
+#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000
+
+/* Description RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+
+
+ If no Peer entry lookup happened for this frame, the
+ value wil be set to 0, and the frame shall never be pushed
+ to REO entrance ring.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+
+
+ If no Peer entry lookup happened for this frame, the
+ value wil be set to 0, and the frame shall never be pushed
+ to REO entrance ring.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Indicates the MPDU queue ID to which this MPDU link
+ descriptor belongs
+
+ Used for tracking and debugging
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8
+#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00
+
+/* Description RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING
+
+ Indicates that a delimiter FCS error was found in
+ between the Previous MPDU and this MPDU.
+
+
+
+ Note that this is just a warning, and does not mean that
+ this MPDU is corrupted in any way. If it is, there will be
+ other errors indicated such as FCS or decrypt errors
+
+
+
+ In case of ndp or phy_err, this field will indicate at
+ least one of delimiters located after the last MPDU in the
+ previous PPDU has been corrupted.
+*/
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24
+#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000
+
+/* Description RX_MPDU_INFO_2_FIRST_DELIM_ERR
+
+ Indicates that the first delimiter had a FCS failure.
+ Only valid when first_mpdu and first_msdu are set.
+
+
+
+*/
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25
+#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000
+
+/* Description RX_MPDU_INFO_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008
+#define RX_MPDU_INFO_2_RESERVED_2A_LSB 26
+#define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000
+
+/* Description RX_MPDU_INFO_3_PN_31_0
+
+
+
+
+
+ WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0]
+ is valid.
+
+ TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
+ WEPSeed[1], pn1}. Only pn[47:0] is valid.
+
+ AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0,
+ pn1, pn0}. Only pn[47:0] is valid.
+
+ WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12,
+ pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1,
+ pn0}. pn[127:0] are valid.
+
+
+
+*/
+#define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c
+#define RX_MPDU_INFO_3_PN_31_0_LSB 0
+#define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_4_PN_63_32
+
+
+
+
+ Bits [63:32] of the PN number. See description for
+ pn_31_0.
+
+
+
+*/
+#define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010
+#define RX_MPDU_INFO_4_PN_63_32_LSB 0
+#define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_5_PN_95_64
+
+
+
+
+ Bits [95:64] of the PN number. See description for
+ pn_31_0.
+
+
+
+*/
+#define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014
+#define RX_MPDU_INFO_5_PN_95_64_LSB 0
+#define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_6_PN_127_96
+
+
+
+
+ Bits [127:96] of the PN number. See description for
+ pn_31_0.
+
+
+
+*/
+#define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018
+#define RX_MPDU_INFO_6_PN_127_96_LSB 0
+#define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_7_EPD_EN
+
+ Field only valid when AST_based_lookup_valid == 1.
+
+
+
+
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ If set to one use EPD instead of LPD
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_EPD_EN_LSB 0
+#define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001
+
+/* Description RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, all frames (data only ?) shall be encrypted.
+ If not, RX CRYPTO shall set an error flag.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1
+#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002
+
+/* Description RX_MPDU_INFO_7_ENCRYPT_TYPE
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Indicates type of decrypt cipher used (as defined in the
+ peer entry)
+
+
+
+ <enum 0 wep_40> WEP 40-bit
+
+ <enum 1 wep_104> WEP 104-bit
+
+ <enum 2 tkip_no_mic> TKIP without MIC
+
+ <enum 3 wep_128> WEP 128-bit
+
+ <enum 4 tkip_with_mic> TKIP with MIC
+
+ <enum 5 wapi> WAPI
+
+ <enum 6 aes_ccmp_128> AES CCMP 128
+
+ <enum 7 no_cipher> No crypto
+
+ <enum 8 aes_ccmp_256> AES CCMP 256
+
+ <enum 9 aes_gcmp_128> AES CCMP 128
+
+ <enum 10 aes_gcmp_256> AES CCMP 256
+
+ <enum 11 wapi_gcm_sm4> WAPI GCM SM4
+
+
+
+ <enum 12 wep_varied_width> WEP encryption. As for WEP
+ per keyid the key bit width can vary, the key bit width for
+ this MPDU will be indicated in field
+ wep_key_width_for_variable key
+
+ <legal 0-12>
+*/
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2
+#define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c
+
+/* Description RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY
+
+ Field only valid when key_type is set to
+ wep_varied_width.
+
+
+
+ This field indicates the size of the wep key for this
+ MPDU.
+
+
+
+ <enum 0 wep_varied_width_40> WEP 40-bit
+
+ <enum 1 wep_varied_width_104> WEP 104-bit
+
+ <enum 2 wep_varied_width_128> WEP 128-bit
+
+
+
+ <legal 0-2>
+*/
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6
+#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0
+
+/* Description RX_MPDU_INFO_7_MESH_STA
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, this is a Mesh (11s) STA.
+
+
+
+ The interpretation of the A-MSDU 'Length' field in the
+ MPDU (if any) is decided by the e-numerations below.
+
+
+
+ <enum 0 MESH_DISABLE>
+
+ <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and
+ includes the length of Mesh Control.
+
+ <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and
+ excludes the length of Mesh Control.
+
+ <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian
+ and excludes the length of Mesh Control. This is
+ 802.11s-compliant.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_7_MESH_STA_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_MESH_STA_LSB 8
+#define RX_MPDU_INFO_7_MESH_STA_MASK 0x00000300
+
+/* Description RX_MPDU_INFO_7_BSSID_HIT
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, the BSSID of the incoming frame matched one of
+ the 8 BSSID register values
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_BSSID_HIT_LSB 10
+#define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400
+
+/* Description RX_MPDU_INFO_7_BSSID_NUMBER
+
+ Field only valid when bssid_hit is set.
+
+
+
+ This number indicates which one out of the 8 BSSID
+ register values matched the incoming frame
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11
+#define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800
+
+/* Description RX_MPDU_INFO_7_TID
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The TID field in the QoS control field
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_TID_LSB 15
+#define RX_MPDU_INFO_7_TID_MASK 0x00078000
+
+/* Description RX_MPDU_INFO_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c
+#define RX_MPDU_INFO_7_RESERVED_7A_LSB 19
+#define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000
+
+/* Description RX_MPDU_INFO_8_PEER_META_DATA
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020
+#define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0
+#define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+
+
+ Note: for ndp frame, if it was expected because the
+ preceding NDPA was filter_pass, the setting
+ rxpcu_filter_pass will be used. This setting will also be
+ used for every ndp frame in case Promiscuous mode is
+ enabled.
+
+
+
+ In case promiscuous is not enabled, and an NDP is not
+ preceded by a NPDA filter pass frame, the only other setting
+ that could appear here for the NDP is rxpcu_monitor_other.
+
+ (rxpcu has a configuration bit specifically for this
+ scenario)
+
+
+
+ Note: for
+
+ <legal 0-2>
+*/
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+/* Description RX_MPDU_INFO_9_SW_FRAME_GROUP_ID
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame> Note: The
+ corresponding Rxpcu_Mpdu_filter_in_category can be
+ rxpcu_filter_pass or rxpcu_monitor_other
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+ Note: The corresponding Rxpcu_Mpdu_filter_in_category
+ can only be rxpcu_monitor_other
+
+
+
+
+ Note: The corresponding Rxpcu_Mpdu_filter_in_category
+ can be rxpcu_filter_pass
+
+
+
+ <legal 0-37>
+*/
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+/* Description RX_MPDU_INFO_9_NDP_FRAME
+
+ When set, the received frame was an NDP frame, and thus
+ there will be no MPDU data.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_NDP_FRAME_LSB 9
+#define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200
+
+/* Description RX_MPDU_INFO_9_PHY_ERR
+
+ When set, a PHY error was received before MAC received
+ any data, and thus there will be no MPDU data.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_PHY_ERR_LSB 10
+#define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400
+
+/* Description RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER
+
+ When set, a PHY error was received before MAC received
+ the complete MPDU header which was needed for proper
+ decoding
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11
+#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800
+
+/* Description RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR
+
+ Set when RXPCU detected a version error in the Frame
+ control field
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12
+#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000
+
+/* Description RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID
+
+ When set, AST based lookup for this frame has found a
+ valid result.
+
+
+
+ Note that for NDP frame this will never be set
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13
+#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000
+
+/* Description RX_MPDU_INFO_9_RESERVED_9A
+
+ <legal 0>
+*/
+#define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_RESERVED_9A_LSB 14
+#define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000
+
+/* Description RX_MPDU_INFO_9_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description RX_MPDU_INFO_10_AST_INDEX
+
+ This field indicates the index of the AST entry
+ corresponding to this MPDU. It is provided by the GSE module
+ instantiated in RXPCU.
+
+ A value of 0xFFFF indicates an invalid AST index,
+ meaning that No AST entry was found or NO AST search was
+ performed
+
+
+
+ In case of ndp or phy_err, this field will be set to
+ 0xFFFF
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028
+#define RX_MPDU_INFO_10_AST_INDEX_LSB 0
+#define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff
+
+/* Description RX_MPDU_INFO_10_SW_PEER_ID
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ This field indicates a unique peer identifier. It is set
+ equal to field 'sw_peer_id' from the AST entry
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028
+#define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16
+#define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000
+
+/* Description RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID
+
+ When set, the field Mpdu_Frame_control_field has valid
+ information
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0
+#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001
+
+/* Description RX_MPDU_INFO_11_MPDU_DURATION_VALID
+
+ When set, the field Mpdu_duration_field has valid
+ information
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1
+#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002
+
+/* Description RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID
+
+ When set, the fields mac_addr_ad1_..... have valid
+ information
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2
+#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004
+
+/* Description RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID
+
+ When set, the fields mac_addr_ad2_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3
+#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008
+
+/* Description RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID
+
+ When set, the fields mac_addr_ad3_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4
+#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010
+
+/* Description RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID
+
+ When set, the fields mac_addr_ad4_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5
+#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020
+
+/* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID
+
+ When set, the fields mpdu_sequence_control_field and
+ mpdu_sequence_number have valid information as well as field
+
+
+
+ For MPDUs without a sequence control field, this field
+ will not be set.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040
+
+/* Description RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID
+
+ When set, the field mpdu_qos_control_field has valid
+ information
+
+
+
+ For MPDUs without a QoS control field, this field will
+ not be set.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7
+#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080
+
+/* Description RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID
+
+ When set, the field mpdu_HT_control_field has valid
+ information
+
+
+
+ For MPDUs without a HT control field, this field will
+ not be set.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8
+#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100
+
+/* Description RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID
+
+ When set, the encryption related info fields, like IV
+ and PN are valid
+
+
+
+ For MPDUs that are not encrypted, this will not be set.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9
+#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200
+
+/* Description RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER
+
+ Field only valid when Mpdu_sequence_control_valid is set
+ AND Fragment_flag is set
+
+
+
+ The fragment number from the 802.11 header
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10
+#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00
+
+/* Description RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+/* Description RX_MPDU_INFO_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_RESERVED_11A_LSB 15
+#define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000
+
+/* Description RX_MPDU_INFO_11_FR_DS
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ Set if the from DS bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_FR_DS_LSB 16
+#define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000
+
+/* Description RX_MPDU_INFO_11_TO_DS
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ Set if the to DS bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_TO_DS_LSB 17
+#define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000
+
+/* Description RX_MPDU_INFO_11_ENCRYPTED
+
+ Field only valid when Mpdu_frame_control_valid is set.
+
+
+
+ Protected bit from the frame control.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_ENCRYPTED_LSB 18
+#define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000
+
+/* Description RX_MPDU_INFO_11_MPDU_RETRY
+
+ Field only valid when Mpdu_frame_control_valid is set.
+
+
+
+ Retry bit from the frame control. Only valid when
+ first_msdu is set.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19
+#define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000
+
+/* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER
+
+ Field only valid when Mpdu_sequence_control_valid is
+ set.
+
+
+
+ The sequence number from the 802.11 header.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20
+#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000
+
+/* Description RX_MPDU_INFO_12_KEY_ID_OCTET
+
+
+
+
+ The key ID octet from the IV.
+
+
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff
+
+/* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Set if new RX_PEER_ENTRY TLV follows. If clear,
+ RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either
+ uses old peer entry or not decrypt.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100
+
+/* Description RX_MPDU_INFO_12_DECRYPT_NEEDED
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Set if decryption is needed.
+
+
+
+ Note:
+
+ When RXPCU sets bit 'ast_index_not_found' and/or
+ ast_index_timeout', RXPCU will also ensure that this bit is
+ NOT set
+
+ CRYPTO for that reason only needs to evaluate this bit
+ and non of the other ones.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200
+
+/* Description RX_MPDU_INFO_12_DECAP_TYPE
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Used by the OLE during decapsulation.
+
+
+
+ Indicates the decapsulation that HW will perform:
+
+
+
+ <enum 0 RAW> No encapsulation
+
+ <enum 1 Native_WiFi>
+
+ <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses
+ SNAP/LLC)
+
+ <enum 3 802_3> Indicate Ethernet
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10
+#define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00
+
+/* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Insert 4 byte of all zeros as VLAN tag if the rx payload
+ does not have VLAN. Used during decapsulation.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000
+
+/* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Insert 4 byte of all zeros as double VLAN tag if the rx
+ payload does not have VLAN. Used during
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000
+
+/* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Strip the VLAN during decapsulation. Used by the OLE.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000
+
+/* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Strip the double VLAN during decapsulation. Used by
+ the OLE.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000
+
+/* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT
+
+ The number of delimiters before this MPDU.
+
+
+
+ Note that this number is cleared at PPDU start.
+
+
+
+ If this MPDU is the first received MPDU in the PPDU and
+ this MPDU gets filtered-in, this field will indicate the
+ number of delimiters located after the last MPDU in the
+ previous PPDU.
+
+
+
+ If this MPDU is located after the first received MPDU in
+ an PPDU, this field will indicate the number of delimiters
+ located between the previous MPDU and this MPDU.
+
+
+
+ In case of ndp or phy_err, this field will indicate the
+ number of delimiters located after the last MPDU in the
+ previous PPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000
+
+/* Description RX_MPDU_INFO_12_AMPDU_FLAG
+
+ When set, received frame was part of an A-MPDU.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28
+#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000
+
+/* Description RX_MPDU_INFO_12_BAR_FRAME
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, received frame is a BAR frame
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_BAR_FRAME_LSB 29
+#define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000
+
+/* Description RX_MPDU_INFO_12_RAW_MPDU
+
+ Consumer: SW
+
+ Producer: RXOLE
+
+
+
+ RXPCU sets this field to 0 and RXOLE overwrites it.
+
+
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_RAW_MPDU_LSB 30
+#define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000
+
+/* Description RX_MPDU_INFO_12_RESERVED_12
+
+ <legal 0>
+*/
+#define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030
+#define RX_MPDU_INFO_12_RESERVED_12_LSB 31
+#define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000
+
+/* Description RX_MPDU_INFO_13_MPDU_LENGTH
+
+ In case of ndp or phy_err this field will be set to 0
+
+
+
+ MPDU length before decapsulation.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0
+#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff
+
+/* Description RX_MPDU_INFO_13_FIRST_MPDU
+
+ See definition in RX attention descriptor
+
+
+
+ In case of ndp or phy_err, this field will be set. Note
+ however that there will not actually be any data contents in
+ the MPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14
+#define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000
+
+/* Description RX_MPDU_INFO_13_MCAST_BCAST
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15
+#define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000
+
+/* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000
+
+/* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000
+
+/* Description RX_MPDU_INFO_13_POWER_MGMT
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_POWER_MGMT_LSB 18
+#define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000
+
+/* Description RX_MPDU_INFO_13_NON_QOS
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 1
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_NON_QOS_LSB 19
+#define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000
+
+/* Description RX_MPDU_INFO_13_NULL_DATA
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_NULL_DATA_LSB 20
+#define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000
+
+/* Description RX_MPDU_INFO_13_MGMT_TYPE
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21
+#define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000
+
+/* Description RX_MPDU_INFO_13_CTRL_TYPE
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22
+#define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000
+
+/* Description RX_MPDU_INFO_13_MORE_DATA
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_MORE_DATA_LSB 23
+#define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000
+
+/* Description RX_MPDU_INFO_13_EOSP
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_EOSP_LSB 24
+#define RX_MPDU_INFO_13_EOSP_MASK 0x01000000
+
+/* Description RX_MPDU_INFO_13_FRAGMENT_FLAG
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000
+
+/* Description RX_MPDU_INFO_13_ORDER
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_ORDER_LSB 26
+#define RX_MPDU_INFO_13_ORDER_MASK 0x04000000
+
+/* Description RX_MPDU_INFO_13_U_APSD_TRIGGER
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000
+
+/* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000
+
+/* Description RX_MPDU_INFO_13_DIRECTED
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_DIRECTED_LSB 29
+#define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000
+
+/* Description RX_MPDU_INFO_13_AMSDU_PRESENT
+
+ Field only valid when Mpdu_qos_control_valid is set
+
+
+
+ The 'amsdu_present' bit within the QoS control field of
+ the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30
+#define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000
+
+/* Description RX_MPDU_INFO_13_RESERVED_13
+
+ <legal 0>
+*/
+#define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034
+#define RX_MPDU_INFO_13_RESERVED_13_LSB 31
+#define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000
+
+/* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ The frame control field of this received MPDU.
+
+
+
+ Field only valid when Ndp_frame and phy_err are NOT set
+
+
+
+ Bytes 0 + 1 of the received MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff
+
+/* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD
+
+ Field only valid when Mpdu_duration_valid is set
+
+
+
+ The duration field of this received MPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000
+
+/* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0
+
+ Field only valid when mac_addr_ad1_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD1
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32
+
+ Field only valid when mac_addr_ad1_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD1
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff
+
+/* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0
+
+ Field only valid when mac_addr_ad2_valid is set
+
+
+
+ The Least Significant 2 bytes of the Received Frames MAC
+ Address AD2
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000
+
+/* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16
+
+ Field only valid when mac_addr_ad2_valid is set
+
+
+
+ The 4 most significant bytes of the Received Frames MAC
+ Address AD2
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0
+
+ Field only valid when mac_addr_ad3_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD3
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32
+
+ Field only valid when mac_addr_ad3_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD3
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff
+
+/* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD
+
+
+
+
+ The sequence control field of the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000
+
+/* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0
+
+ Field only valid when mac_addr_ad4_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD4
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32
+
+ Field only valid when mac_addr_ad4_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD4
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff
+
+/* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The sequence control field of the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+/* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The HT control field of the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff
+
+
+#endif // _RX_MPDU_INFO_H_
diff --git a/hw/qca5018/rx_mpdu_link_ptr.h b/hw/qca5018/rx_mpdu_link_ptr.h
new file mode 100644
index 0000000..658836e
--- /dev/null
+++ b/hw/qca5018/rx_mpdu_link_ptr.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct buffer_addr_info mpdu_link_desc_addr_info;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+ struct buffer_addr_info mpdu_link_desc_addr_info;
+};
+
+/*
+
+struct buffer_addr_info mpdu_link_desc_addr_info
+
+ Details of the physical address of an MPDU link
+ descriptor
+*/
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+
+#endif // _RX_MPDU_LINK_PTR_H_
diff --git a/hw/qca5018/rx_mpdu_start.h b/hw/qca5018/rx_mpdu_start.h
new file mode 100644
index 0000000..0ca10e7
--- /dev/null
+++ b/hw/qca5018/rx_mpdu_start.h
@@ -0,0 +1,1974 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-22 struct rx_mpdu_info rx_mpdu_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_START 23
+
+struct rx_mpdu_start {
+ struct rx_mpdu_info rx_mpdu_info_details;
+};
+
+/*
+
+struct rx_mpdu_info rx_mpdu_info_details
+
+ Structure containing all the MPDU header details that
+ might be needed for other modules further down the received
+ path
+*/
+
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_info rx_mpdu_info_details */
+
+
+ /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */
+
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB
+
+ If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb
+ is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1,
+ hash[3:0]} using the chosen Toeplitz hash from Common Parser
+ if flow search fails.
+
+ If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb
+ 's not 2'b00, Rx OLE uses a REO desination indication of
+ {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash
+ from Common Parser if flow search fails.
+
+ This LMAC/peer-based routing is not supported in
+ Hastings80 and HastingsPrime.
+
+ <legal all>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY
+
+ Indication to Rx OLE to enable REO destination routing
+ based on the chosen Toeplitz hash from Common Parser, in
+ case flow search fails
+
+ <legal all>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA
+
+ Filter pass Unicast data frame (matching
+ rxpcu_filter_pass and sw_frame_group_Unicast_data) routing
+ selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA
+
+ Filter pass Multicast data frame (matching
+ rxpcu_filter_pass and sw_frame_group_Multicast_data) routing
+ selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000
+
+ Filter pass BAR frame (matching rxpcu_filter_pass and
+ sw_frame_group_ctrl_1000) routing selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION
+
+ Field only valid when for the received frame type the
+ corresponding pkt_selection_fp_... bit is set
+
+
+
+ <enum 0 wbm2rxdma_buf_source_ring> The data buffer for
+
+ <enum 1 fw2rxdma_buf_source_ring> The data buffer for
+ this frame shall be sourced by fw2rxdma buffer source ring.
+
+ <enum 2 sw2rxdma_buf_source_ring> The data buffer for
+ this frame shall be sourced by sw2rxdma buffer source ring.
+
+ <enum 3 no_buffer_ring> The frame shall not be written
+ to any data buffer.
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION
+
+ Field only valid when for the received frame type the
+ corresponding pkt_selection_fp_... bit is set
+
+
+
+ <enum 0 rxdma_release_ring> RXDMA0 shall push the frame
+ to the Release ring. Effectively this means the frame needs
+ to be dropped.
+
+ <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to
+ the FW ring.
+
+ <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to
+ the SW ring.
+
+ <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to
+ the REO entrance ring.
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
+
+/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B
+
+ <legal 0>
+*/
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15
+#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000
+
+/* Description RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Address (lower 32 bits) of the REO queue descriptor.
+
+
+
+ If no Peer entry lookup happened for this frame, the
+ value wil be set to 0, and the frame shall never be pushed
+ to REO entrance ring.
+
+ <legal all>
+*/
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0
+#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Address (upper 8 bits) of the REO queue descriptor.
+
+
+
+ If no Peer entry lookup happened for this frame, the
+ value wil be set to 0, and the frame shall never be pushed
+ to REO entrance ring.
+
+ <legal all>
+*/
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Indicates the MPDU queue ID to which this MPDU link
+ descriptor belongs
+
+ Used for tracking and debugging
+
+ <legal all>
+*/
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00
+
+/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING
+
+ Indicates that a delimiter FCS error was found in
+ between the Previous MPDU and this MPDU.
+
+
+
+ Note that this is just a warning, and does not mean that
+ this MPDU is corrupted in any way. If it is, there will be
+ other errors indicated such as FCS or decrypt errors
+
+
+
+ In case of ndp or phy_err, this field will indicate at
+ least one of delimiters located after the last MPDU in the
+ previous PPDU has been corrupted.
+*/
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000
+
+/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR
+
+ Indicates that the first delimiter had a FCS failure.
+ Only valid when first_mpdu and first_msdu are set.
+
+
+
+*/
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000
+
+/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A
+
+ <legal 0>
+*/
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26
+#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000
+
+/* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0
+
+
+
+
+
+ WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0]
+ is valid.
+
+ TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
+ WEPSeed[1], pn1}. Only pn[47:0] is valid.
+
+ AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0,
+ pn1, pn0}. Only pn[47:0] is valid.
+
+ WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12,
+ pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1,
+ pn0}. pn[127:0] are valid.
+
+
+
+*/
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0
+#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32
+
+
+
+
+ Bits [63:32] of the PN number. See description for
+ pn_31_0.
+
+
+
+*/
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0
+#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff
+
+/* Description RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64
+
+
+
+
+ Bits [95:64] of the PN number. See description for
+ pn_31_0.
+
+
+
+*/
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0
+#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff
+
+/* Description RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96
+
+
+
+
+ Bits [127:96] of the PN number. See description for
+ pn_31_0.
+
+
+
+*/
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0
+#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN
+
+ Field only valid when AST_based_lookup_valid == 1.
+
+
+
+
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ If set to one use EPD instead of LPD
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, all frames (data only ?) shall be encrypted.
+ If not, RX CRYPTO shall set an error flag.
+
+ <legal all>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Indicates type of decrypt cipher used (as defined in the
+ peer entry)
+
+
+
+ <enum 0 wep_40> WEP 40-bit
+
+ <enum 1 wep_104> WEP 104-bit
+
+ <enum 2 tkip_no_mic> TKIP without MIC
+
+ <enum 3 wep_128> WEP 128-bit
+
+ <enum 4 tkip_with_mic> TKIP with MIC
+
+ <enum 5 wapi> WAPI
+
+ <enum 6 aes_ccmp_128> AES CCMP 128
+
+ <enum 7 no_cipher> No crypto
+
+ <enum 8 aes_ccmp_256> AES CCMP 256
+
+ <enum 9 aes_gcmp_128> AES CCMP 128
+
+ <enum 10 aes_gcmp_256> AES CCMP 256
+
+ <enum 11 wapi_gcm_sm4> WAPI GCM SM4
+
+
+
+ <enum 12 wep_varied_width> WEP encryption. As for WEP
+ per keyid the key bit width can vary, the key bit width for
+ this MPDU will be indicated in field
+ wep_key_width_for_variable key
+
+ <legal 0-12>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY
+
+ Field only valid when key_type is set to
+ wep_varied_width.
+
+
+
+ This field indicates the size of the wep key for this
+ MPDU.
+
+
+
+ <enum 0 wep_varied_width_40> WEP 40-bit
+
+ <enum 1 wep_varied_width_104> WEP 104-bit
+
+ <enum 2 wep_varied_width_128> WEP 128-bit
+
+
+
+ <legal 0-2>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, this is a Mesh (11s) STA.
+
+
+
+ The interpretation of the A-MSDU 'Length' field in the
+ MPDU (if any) is decided by the e-numerations below.
+
+
+
+ <enum 0 MESH_DISABLE>
+
+ <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and
+ includes the length of Mesh Control.
+
+ <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and
+ excludes the length of Mesh Control.
+
+ <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian
+ and excludes the length of Mesh Control. This is
+ 802.11s-compliant.
+
+ <legal all>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 8
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x00000300
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, the BSSID of the incoming frame matched one of
+ the 8 BSSID register values
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER
+
+ Field only valid when bssid_hit is set.
+
+
+
+ This number indicates which one out of the 8 BSSID
+ register values matched the incoming frame
+
+ <legal all>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The TID field in the QoS control field
+
+ <legal all>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000
+
+/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A
+
+ <legal 0>
+*/
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19
+#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000
+
+/* Description RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Meta data that SW has programmed in the Peer table entry
+ of the transmitting STA.
+
+ <legal all>
+*/
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0
+#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+
+
+ Note: for ndp frame, if it was expected because the
+ preceding NDPA was filter_pass, the setting
+ rxpcu_filter_pass will be used. This setting will also be
+ used for every ndp frame in case Promiscuous mode is
+ enabled.
+
+
+
+ In case promiscuous is not enabled, and an NDP is not
+ preceded by a NPDA filter pass frame, the only other setting
+ that could appear here for the NDP is rxpcu_monitor_other.
+
+ (rxpcu has a configuration bit specifically for this
+ scenario)
+
+
+
+ Note: for
+
+ <legal 0-2>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame> Note: The
+ corresponding Rxpcu_Mpdu_filter_in_category can be
+ rxpcu_filter_pass or rxpcu_monitor_other
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+ Note: The corresponding Rxpcu_Mpdu_filter_in_category
+ can only be rxpcu_monitor_other
+
+
+
+
+ Note: The corresponding Rxpcu_Mpdu_filter_in_category
+ can be rxpcu_filter_pass
+
+
+
+ <legal 0-37>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME
+
+ When set, the received frame was an NDP frame, and thus
+ there will be no MPDU data.
+
+ <legal all>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR
+
+ When set, a PHY error was received before MAC received
+ any data, and thus there will be no MPDU data.
+
+ <legal all>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER
+
+ When set, a PHY error was received before MAC received
+ the complete MPDU header which was needed for proper
+ decoding
+
+ <legal all>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR
+
+ Set when RXPCU detected a version error in the Frame
+ control field
+
+ <legal all>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID
+
+ When set, AST based lookup for this frame has found a
+ valid result.
+
+
+
+ Note that for NDP frame this will never be set
+
+ <legal all>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A
+
+ <legal 0>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 14
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000c000
+
+/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX
+
+ This field indicates the index of the AST entry
+ corresponding to this MPDU. It is provided by the GSE module
+ instantiated in RXPCU.
+
+ A value of 0xFFFF indicates an invalid AST index,
+ meaning that No AST entry was found or NO AST search was
+ performed
+
+
+
+ In case of ndp or phy_err, this field will be set to
+ 0xFFFF
+
+ <legal all>
+*/
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff
+
+/* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ This field indicates a unique peer identifier. It is set
+ equal to field 'sw_peer_id' from the AST entry
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16
+#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID
+
+ When set, the field Mpdu_Frame_control_field has valid
+ information
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID
+
+ When set, the field Mpdu_duration_field has valid
+ information
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID
+
+ When set, the fields mac_addr_ad1_..... have valid
+ information
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID
+
+ When set, the fields mac_addr_ad2_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID
+
+ When set, the fields mac_addr_ad3_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID
+
+ When set, the fields mac_addr_ad4_..... have valid
+ information
+
+
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID
+
+ When set, the fields mpdu_sequence_control_field and
+ mpdu_sequence_number have valid information as well as field
+
+
+
+ For MPDUs without a sequence control field, this field
+ will not be set.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID
+
+ When set, the field mpdu_qos_control_field has valid
+ information
+
+
+
+ For MPDUs without a QoS control field, this field will
+ not be set.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID
+
+ When set, the field mpdu_HT_control_field has valid
+ information
+
+
+
+ For MPDUs without a HT control field, this field will
+ not be set.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID
+
+ When set, the encryption related info fields, like IV
+ and PN are valid
+
+
+
+ For MPDUs that are not encrypted, this will not be set.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER
+
+ Field only valid when Mpdu_sequence_control_valid is set
+ AND Fragment_flag is set
+
+
+
+ The fragment number from the 802.11 header
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG
+
+ The More Fragment bit setting from the MPDU header of
+ the received frame
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A
+
+ <legal 0>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ Set if the from DS bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ Set if the to DS bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED
+
+ Field only valid when Mpdu_frame_control_valid is set.
+
+
+
+ Protected bit from the frame control.
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY
+
+ Field only valid when Mpdu_frame_control_valid is set.
+
+
+
+ Retry bit from the frame control. Only valid when
+ first_msdu is set.
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000
+
+/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER
+
+ Field only valid when Mpdu_sequence_control_valid is
+ set.
+
+
+
+ The sequence number from the 802.11 header.
+
+ <legal all>
+*/
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20
+#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET
+
+
+
+
+ The key ID octet from the IV.
+
+
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Set if new RX_PEER_ENTRY TLV follows. If clear,
+ RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either
+ uses old peer entry or not decrypt.
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Set if decryption is needed.
+
+
+
+ Note:
+
+ When RXPCU sets bit 'ast_index_not_found' and/or
+ ast_index_timeout', RXPCU will also ensure that this bit is
+ NOT set
+
+ CRYPTO for that reason only needs to evaluate this bit
+ and non of the other ones.
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Used by the OLE during decapsulation.
+
+
+
+ Indicates the decapsulation that HW will perform:
+
+
+
+ <enum 0 RAW> No encapsulation
+
+ <enum 1 Native_WiFi>
+
+ <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses
+ SNAP/LLC)
+
+ <enum 3 802_3> Indicate Ethernet
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Insert 4 byte of all zeros as VLAN tag if the rx payload
+ does not have VLAN. Used during decapsulation.
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Insert 4 byte of all zeros as double VLAN tag if the rx
+ payload does not have VLAN. Used during
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Strip the VLAN during decapsulation. Used by the OLE.
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ Strip the double VLAN during decapsulation. Used by
+ the OLE.
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT
+
+ The number of delimiters before this MPDU.
+
+
+
+ Note that this number is cleared at PPDU start.
+
+
+
+ If this MPDU is the first received MPDU in the PPDU and
+ this MPDU gets filtered-in, this field will indicate the
+ number of delimiters located after the last MPDU in the
+ previous PPDU.
+
+
+
+ If this MPDU is located after the first received MPDU in
+ an PPDU, this field will indicate the number of delimiters
+ located between the previous MPDU and this MPDU.
+
+
+
+ In case of ndp or phy_err, this field will indicate the
+ number of delimiters located after the last MPDU in the
+ previous PPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG
+
+ When set, received frame was part of an A-MPDU.
+
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME
+
+ In case of ndp or phy_err or AST_based_lookup_valid ==
+ 0, this field will be set to 0
+
+
+
+ When set, received frame is a BAR frame
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU
+
+ Consumer: SW
+
+ Producer: RXOLE
+
+
+
+ RXPCU sets this field to 0 and RXOLE overwrites it.
+
+
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000
+
+/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12
+
+ <legal 0>
+*/
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31
+#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH
+
+ In case of ndp or phy_err this field will be set to 0
+
+
+
+ MPDU length before decapsulation.
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU
+
+ See definition in RX attention descriptor
+
+
+
+ In case of ndp or phy_err, this field will be set. Note
+ however that there will not actually be any data contents in
+ the MPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 1
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED
+
+ In case of ndp or phy_err or Phy_err_during_mpdu_header
+ this field will be set to 0
+
+
+
+ See definition in RX attention descriptor
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT
+
+ Field only valid when Mpdu_qos_control_valid is set
+
+
+
+ The 'amsdu_present' bit within the QoS control field of
+ the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000
+
+/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13
+
+ <legal 0>
+*/
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31
+#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000
+
+/* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD
+
+ Field only valid when Mpdu_frame_control_valid is set
+
+
+
+ The frame control field of this received MPDU.
+
+
+
+ Field only valid when Ndp_frame and phy_err are NOT set
+
+
+
+ Bytes 0 + 1 of the received MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff
+
+/* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD
+
+ Field only valid when Mpdu_duration_valid is set
+
+
+
+ The duration field of this received MPDU.
+
+ <legal all>
+*/
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16
+#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000
+
+/* Description RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0
+
+ Field only valid when mac_addr_ad1_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD1
+
+ <legal all>
+*/
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0
+#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32
+
+ Field only valid when mac_addr_ad1_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD1
+
+ <legal all>
+*/
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff
+
+/* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0
+
+ Field only valid when mac_addr_ad2_valid is set
+
+
+
+ The Least Significant 2 bytes of the Received Frames MAC
+ Address AD2
+
+ <legal all>
+*/
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16
+#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000
+
+/* Description RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16
+
+ Field only valid when mac_addr_ad2_valid is set
+
+
+
+ The 4 most significant bytes of the Received Frames MAC
+ Address AD2
+
+ <legal all>
+*/
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0
+#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff
+
+/* Description RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0
+
+ Field only valid when mac_addr_ad3_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD3
+
+ <legal all>
+*/
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0
+#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32
+
+ Field only valid when mac_addr_ad3_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD3
+
+ <legal all>
+*/
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff
+
+/* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD
+
+
+
+
+ The sequence control field of the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16
+#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000
+
+/* Description RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0
+
+ Field only valid when mac_addr_ad4_valid is set
+
+
+
+ The Least Significant 4 bytes of the Received Frames MAC
+ Address AD4
+
+ <legal all>
+*/
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0
+#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff
+
+/* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32
+
+ Field only valid when mac_addr_ad4_valid is set
+
+
+
+ The 2 most significant bytes of the Received Frames MAC
+ Address AD4
+
+ <legal all>
+*/
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff
+
+/* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The sequence control field of the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16
+#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+/* Description RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD
+
+ Field only valid when mpdu_qos_control_valid is set
+
+
+
+ The HT control field of the MPDU
+
+ <legal all>
+*/
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0
+#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff
+
+
+#endif // _RX_MPDU_START_H_
diff --git a/hw/qca5018/rx_msdu_desc_info.h b/hw/qca5018/rx_msdu_desc_info.h
new file mode 100644
index 0000000..3e160df
--- /dev/null
+++ b/hw/qca5018/rx_msdu_desc_info.h
@@ -0,0 +1,840 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 first_msdu_in_mpdu_flag[0], last_msdu_in_mpdu_flag[1], msdu_continuation[2], msdu_length[16:3], reo_destination_indication[21:17], msdu_drop[22], sa_is_valid[23], sa_idx_timeout[24], da_is_valid[25], da_is_mcbc[26], da_idx_timeout[27], l3_header_padding_msb[28], tcp_udp_chksum_fail[29], ip_chksum_fail[30], raw_mpdu[31]
+// 1 sa_idx_or_sw_peer_id_14_0[14:0], mpdu_ast_idx_or_sw_peer_id_14_0[29:15], fr_ds[30], to_ds[31]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2
+
+struct rx_msdu_desc_info {
+ uint32_t first_msdu_in_mpdu_flag : 1, //[0]
+ last_msdu_in_mpdu_flag : 1, //[1]
+ msdu_continuation : 1, //[2]
+ msdu_length : 14, //[16:3]
+ reo_destination_indication : 5, //[21:17]
+ msdu_drop : 1, //[22]
+ sa_is_valid : 1, //[23]
+ sa_idx_timeout : 1, //[24]
+ da_is_valid : 1, //[25]
+ da_is_mcbc : 1, //[26]
+ da_idx_timeout : 1, //[27]
+ l3_header_padding_msb : 1, //[28]
+ tcp_udp_chksum_fail : 1, //[29]
+ ip_chksum_fail : 1, //[30]
+ raw_mpdu : 1; //[31]
+ uint32_t sa_idx_or_sw_peer_id_14_0 : 15, //[14:0]
+ mpdu_ast_idx_or_sw_peer_id_14_0 : 15, //[29:15]
+ fr_ds : 1, //[30]
+ to_ds : 1; //[31]
+};
+
+/*
+
+first_msdu_in_mpdu_flag
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+
+last_msdu_in_mpdu_flag
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+
+msdu_continuation
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+
+msdu_length
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+
+reo_destination_indication
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+
+msdu_drop
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+
+sa_is_valid
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+
+sa_idx_timeout
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+
+da_is_valid
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+
+da_is_mcbc
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+
+da_idx_timeout
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+
+l3_header_padding_msb
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+
+tcp_udp_chksum_fail
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+
+ip_chksum_fail
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+
+raw_mpdu
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+
+sa_idx_or_sw_peer_id_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+
+mpdu_ast_idx_or_sw_peer_id_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+
+fr_ds
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+
+to_ds
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+
+
+/* Description RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description RX_MSDU_DESC_INFO_0_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description RX_MSDU_DESC_INFO_0_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000
+
+/* Description RX_MSDU_DESC_INFO_0_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description RX_MSDU_DESC_INFO_0_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MSDU_DESC_INFO_0_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000
+
+/* Description RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_DESC_INFO_0_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_DESC_INFO_0_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_DESC_INFO_0_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_DESC_INFO_0_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_LSB 31
+#define RX_MSDU_DESC_INFO_0_RAW_MPDU_MASK 0x80000000
+
+/* Description RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_DESC_INFO_1_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x00000004
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_DESC_INFO_1_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description RX_MSDU_DESC_INFO_1_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_1_FR_DS_OFFSET 0x00000004
+#define RX_MSDU_DESC_INFO_1_FR_DS_LSB 30
+#define RX_MSDU_DESC_INFO_1_FR_DS_MASK 0x40000000
+
+/* Description RX_MSDU_DESC_INFO_1_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_DESC_INFO_1_TO_DS_OFFSET 0x00000004
+#define RX_MSDU_DESC_INFO_1_TO_DS_LSB 31
+#define RX_MSDU_DESC_INFO_1_TO_DS_MASK 0x80000000
+
+
+#endif // _RX_MSDU_DESC_INFO_H_
diff --git a/hw/qca5018/rx_msdu_details.h b/hw/qca5018/rx_msdu_details.h
new file mode 100644
index 0000000..c361245
--- /dev/null
+++ b/hw/qca5018/rx_msdu_details.h
@@ -0,0 +1,680 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_msdu_desc_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct buffer_addr_info buffer_addr_info_details;
+// 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+ struct buffer_addr_info buffer_addr_info_details;
+ struct rx_msdu_desc_info rx_msdu_desc_info_details;
+};
+
+/*
+
+struct buffer_addr_info buffer_addr_info_details
+
+ Consumer: REO/SW
+
+ Producer: RXDMA
+
+
+
+ Details of the physical address of the buffer containing
+ an MSDU (or entire MPDU)
+
+struct rx_msdu_desc_info rx_msdu_desc_info_details
+
+ Consumer: REO/SW
+
+ Producer: RXDMA
+
+
+
+ General information related to the MSDU that should be
+ passed on from RXDMA all the way to to the REO destination
+ ring.
+*/
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
+
+
+/* Description RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
+
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+
+#endif // _RX_MSDU_DETAILS_H_
diff --git a/hw/qca5018/rx_msdu_end.h b/hw/qca5018/rx_msdu_end.h
new file mode 100644
index 0000000..afd9020
--- /dev/null
+++ b/hw/qca5018/rx_msdu_end.h
@@ -0,0 +1,1590 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
+// 1 ip_hdr_chksum[15:0], reported_mpdu_length[29:16], reserved_1a[31:30]
+// 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], cumulative_l3_checksum[31:16]
+// 3 rule_indication_31_0[31:0]
+// 4 rule_indication_63_32[31:0]
+// 5 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_5a[15:14], l3_type[31:16]
+// 6 ipv6_options_crc[31:0]
+// 7 tcp_seq_number[31:0]
+// 8 tcp_ack_number[31:0]
+// 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16]
+// 10 tcp_udp_chksum[15:0], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], first_msdu[28], last_msdu[29], tcp_udp_chksum_fail[30], ip_chksum_fail[31]
+// 11 sa_idx[15:0], da_idx_or_sw_peer_id[31:16]
+// 12 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_12a[31:26]
+// 13 fse_metadata[31:0]
+// 14 cce_metadata[15:0], sa_sw_peer_id[31:16]
+// 15 aggregation_count[7:0], flow_aggregation_continuation[8], fisa_timeout[9], reserved_15a[31:10]
+// 16 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_END 17
+
+struct rx_msdu_end {
+ uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
+ sw_frame_group_id : 7, //[8:2]
+ reserved_0 : 7, //[15:9]
+ phy_ppdu_id : 16; //[31:16]
+ uint32_t ip_hdr_chksum : 16, //[15:0]
+ reported_mpdu_length : 14, //[29:16]
+ reserved_1a : 2; //[31:30]
+ uint32_t key_id_octet : 8, //[7:0]
+ cce_super_rule : 6, //[13:8]
+ cce_classify_not_done_truncate : 1, //[14]
+ cce_classify_not_done_cce_dis : 1, //[15]
+ cumulative_l3_checksum : 16; //[31:16]
+ uint32_t rule_indication_31_0 : 32; //[31:0]
+ uint32_t rule_indication_63_32 : 32; //[31:0]
+ uint32_t da_offset : 6, //[5:0]
+ sa_offset : 6, //[11:6]
+ da_offset_valid : 1, //[12]
+ sa_offset_valid : 1, //[13]
+ reserved_5a : 2, //[15:14]
+ l3_type : 16; //[31:16]
+ uint32_t ipv6_options_crc : 32; //[31:0]
+ uint32_t tcp_seq_number : 32; //[31:0]
+ uint32_t tcp_ack_number : 32; //[31:0]
+ uint32_t tcp_flag : 9, //[8:0]
+ lro_eligible : 1, //[9]
+ reserved_9a : 6, //[15:10]
+ window_size : 16; //[31:16]
+ uint32_t tcp_udp_chksum : 16, //[15:0]
+ sa_idx_timeout : 1, //[16]
+ da_idx_timeout : 1, //[17]
+ msdu_limit_error : 1, //[18]
+ flow_idx_timeout : 1, //[19]
+ flow_idx_invalid : 1, //[20]
+ wifi_parser_error : 1, //[21]
+ amsdu_parser_error : 1, //[22]
+ sa_is_valid : 1, //[23]
+ da_is_valid : 1, //[24]
+ da_is_mcbc : 1, //[25]
+ l3_header_padding : 2, //[27:26]
+ first_msdu : 1, //[28]
+ last_msdu : 1, //[29]
+ tcp_udp_chksum_fail : 1, //[30]
+ ip_chksum_fail : 1; //[31]
+ uint32_t sa_idx : 16, //[15:0]
+ da_idx_or_sw_peer_id : 16; //[31:16]
+ uint32_t msdu_drop : 1, //[0]
+ reo_destination_indication : 5, //[5:1]
+ flow_idx : 20, //[25:6]
+ reserved_12a : 6; //[31:26]
+ uint32_t fse_metadata : 32; //[31:0]
+ uint32_t cce_metadata : 16, //[15:0]
+ sa_sw_peer_id : 16; //[31:16]
+ uint32_t aggregation_count : 8, //[7:0]
+ flow_aggregation_continuation : 1, //[8]
+ fisa_timeout : 1, //[9]
+ reserved_15a : 22; //[31:10]
+ uint32_t cumulative_l4_checksum : 16, //[15:0]
+ cumulative_ip_length : 16; //[31:16]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+ <legal 0-2>
+
+sw_frame_group_id
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame>
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+
+
+
+
+
+ <legal 0-37>
+
+reserved_0
+
+ <legal 0>
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+
+ip_hdr_chksum
+
+ This can include the IP header checksum or the pseudo
+ header checksum used by TCP/UDP checksum.
+
+ (with the first byte in the MSB and the second byte in
+ the LSB, i.e. requiring a byte-swap for little-endian FW/SW
+ w.r.t. the byte order in a packet)
+
+reported_mpdu_length
+
+ MPDU length before decapsulation. Only valid when
+ first_msdu is set. This field is taken directly from the
+ length field of the A-MPDU delimiter or the preamble length
+ field for non-A-MPDU frames.
+
+reserved_1a
+
+ <legal 0>
+
+key_id_octet
+
+ The key ID octet from the IV. Only valid when
+ first_msdu is set.
+
+cce_super_rule
+
+ Indicates the super filter rule
+
+cce_classify_not_done_truncate
+
+ Classification failed due to truncated frame
+
+cce_classify_not_done_cce_dis
+
+ Classification failed due to CCE global disable
+
+cumulative_l3_checksum
+
+ FISA: IP header checksum including the total MSDU length
+ that is part of this flow aggregated so far, reported if
+ 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+rule_indication_31_0
+
+ Bitmap indicating which of rules 31-0 have matched
+
+rule_indication_63_32
+
+ Bitmap indicating which of rules 63-32 have matched
+
+da_offset
+
+ Offset into MSDU buffer for DA
+
+sa_offset
+
+ Offset into MSDU buffer for SA
+
+da_offset_valid
+
+ da_offset field is valid. This will be set to 0 in case
+ of a dynamic A-MSDU when DA is compressed
+
+sa_offset_valid
+
+ sa_offset field is valid. This will be set to 0 in case
+ of a dynamic A-MSDU when SA is compressed
+
+reserved_5a
+
+ <legal 0>
+
+l3_type
+
+ The 16-bit type value indicating the type of L3 later
+ extracted from LLC/SNAP, set to zero if SNAP is not
+ available
+
+ipv6_options_crc
+
+ 32 bit CRC computed out of IP v6 extension headers
+
+tcp_seq_number
+
+ TCP sequence number (as a number assembled from a TCP
+ packet in big-endian order, i.e. requiring a byte-swap for
+ little-endian FW/SW w.r.t. the byte order in a packet)
+
+
+
+ In Pine, if 'RXOLE_R0_MISC_CONFIG.
+ OVERRIDE_MSDU_END_FIELDS' is set, toeplitz_hash_2_or_4 from
+ 'RX_MSDU_START' will be reported here:
+
+ Controlled by multiple RxOLE registers for TCP/UDP over
+ IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4
+ or IPv6 src/dest addresses is reported; or, Toeplitz hash
+ computed over 4-tuple IPv4 or IPv6 src/dest addresses and
+ src/dest ports is reported. The Flow_id_toeplitz hash can
+ also be reported here. Usually the hash reported here is the
+ one used for hash-based REO routing (see
+ use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO').
+ Optionally the 3-tuple Toeplitz hash over IPv4 or IPv6
+ src/dest addresses and L4 protocol can be reported here.
+
+ (Unsupported in HastingsPrime)
+
+tcp_ack_number
+
+ TCP acknowledge number (as a number assembled from a TCP
+ packet in big-endian order, i.e. requiring a byte-swap for
+ little-endian FW/SW w.r.t. the byte order in a packet)
+
+
+
+ In Pine, if 'RXOLE_R0_MISC_CONFIG.
+ OVERRIDE_MSDU_END_FIELDS' is set, flow_id_toeplitz from
+ 'RX_MSDU_START' will be reported here:
+
+ Toeplitz hash of 5-tuple {IP source address, IP
+ destination address, IP source port, IP destination port, L4
+ protocol} in case of non-IPSec. In case of IPSec - Toeplitz
+ hash of 4-tuple {IP source address, IP destination address,
+ SPI, L4 protocol}. Optionally the 3-tuple Toeplitz hash over
+ IPv4 or IPv6 src/dest addresses and L4 protocol can be
+ reported here.
+
+ The relevant Toeplitz key registers are provided in
+ RxOLE's instance of common parser module. These registers
+ are separate from the Toeplitz keys used by ASE/FSE modules
+ inside RxOLE. The actual value will be passed on from common
+ parser module to RxOLE in one of the WHO_* TLVs.
+
+ (Unsupported in HastingsPrime)
+
+tcp_flag
+
+ TCP flags
+
+ {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit
+ in bit 8 and the FIN bit in bit 0, i.e. in big-endian order,
+ i.e. requiring a byte-swap for little-endian FW/SW w.r.t.
+ the byte order in a packet)
+
+lro_eligible
+
+ Computed out of TCP and IP fields to indicate that this
+ MSDU is eligible for LRO
+
+reserved_9a
+
+ NOTE: DO not assign a field... Internally used in
+ RXOLE..
+
+ <legal 0>
+
+window_size
+
+ TCP receive window size (as a number assembled from a
+ TCP packet in big-endian order, i.e. requiring a byte-swap
+ for little-endian FW/SW w.r.t. the byte order in a packet)
+
+
+
+ In Pine, if 'RXOLE_R0_MISC_CONFIG.
+ OVERRIDE_MSDU_END_FIELDS' is set, msdu_length from
+ 'RX_MSDU_START' will be reported in the 14 LSBs here:
+
+ MSDU length in bytes after decapsulation. This field is
+ still valid for MPDU frames without A-MSDU. It still
+ represents MSDU length after decapsulation.
+
+ (Unsupported in HastingsPrime)
+
+tcp_udp_chksum
+
+ The value of the computed TCP/UDP checksum. A mode bit
+ selects whether this checksum is the full checksum or the
+ partial checksum which does not include the pseudo header.
+ (with the first byte in the MSB and the second byte in the
+ LSB, i.e. requiring a byte-swap for little-endian FW/SW
+ w.r.t. the byte order in a packet)
+
+sa_idx_timeout
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer.
+
+da_idx_timeout
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer.
+
+msdu_limit_error
+
+ Indicates that the MSDU threshold was exceeded and thus
+ all the rest of the MSDUs will not be scattered and will not
+ be decapsulated but will be DMA'ed in RAW format as a single
+ MSDU buffer
+
+flow_idx_timeout
+
+ Indicates an unsuccessful flow search due to the
+ expiring of the search timer.
+
+ <legal all>
+
+flow_idx_invalid
+
+ flow id is not valid
+
+ <legal all>
+
+wifi_parser_error
+
+ Indicates that the WiFi frame has one of the following
+ errors
+
+ o has less than minimum allowed bytes as per standard
+
+ o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
+
+ <legal all>
+
+amsdu_parser_error
+
+ A-MSDU could not be properly de-agregated.
+
+ <legal all>
+
+sa_is_valid
+
+ Indicates that OLE found a valid SA entry
+
+da_is_valid
+
+ Indicates that OLE found a valid DA entry
+
+da_is_mcbc
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address.
+
+l3_header_padding
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+first_msdu
+
+ Indicates the first MSDU of A-MSDU. If both first_msdu
+ and last_msdu are set in the MSDU then this is a
+ non-aggregated MSDU frame: normal MPDU. Interior MSDU in an
+ A-MSDU shall have both first_mpdu and last_mpdu bits set to
+ 0.
+
+last_msdu
+
+ Indicates the last MSDU of the A-MSDU. MPDU end status
+ is only valid when last_msdu is set.
+
+tcp_udp_chksum_fail
+
+ if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is
+ set, tcp_udp_chksum_fail from 'RX_ATTENTION' will be
+ reported here:
+
+ Indicates that the computed checksum (tcp_udp_chksum)
+ did not match the checksum in the TCP/UDP header.
+
+ (unsupported in HastingsPrime)
+
+ip_chksum_fail
+
+ If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is
+ set, ip_chksum_fail from 'RX_MSDU_START' will be reported in
+ the MSB here:
+
+ Indicates that the computed checksum (ip_hdr_chksum) did
+ not match the checksum in the IP header.
+
+ (unsupported in HastingsPrime)
+
+sa_idx
+
+ The offset in the address table which matches the MAC
+ source address.
+
+da_idx_or_sw_peer_id
+
+ Based on a register configuration in RXOLE, this field
+ will contain:
+
+ The offset in the address table which matches the MAC
+ destination address
+
+ OR:
+
+ sw_peer_id from the address search entry corresponding
+ to the destination address of the MSDU
+
+msdu_drop
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+
+reo_destination_indication
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+
+flow_idx
+
+ Flow table index
+
+ <legal all>
+
+reserved_12a
+
+ <legal 0>
+
+fse_metadata
+
+ FSE related meta data:
+
+ <legal all>
+
+cce_metadata
+
+ CCE related meta data:
+
+ <legal all>
+
+sa_sw_peer_id
+
+ sw_peer_id from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+
+aggregation_count
+
+ FISA: Number of MSDU's aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+flow_aggregation_continuation
+
+ FISA: To indicate that this MSDU can be aggregated with
+ the previous packet with the same flow id
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+fisa_timeout
+
+ FISA: To indicate that the aggregation has restarted for
+ this flow due to timeout
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+reserved_15a
+
+ <legal 0>
+
+cumulative_l4_checksum
+
+ FISA: checksum for MSDU's that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+cumulative_ip_length
+
+ FISA: Total MSDU length that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+
+
+/* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+ <legal 0-2>
+*/
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+/* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame>
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+
+
+
+
+
+ <legal 0-37>
+*/
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+/* Description RX_MSDU_END_0_RESERVED_0
+
+ <legal 0>
+*/
+#define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000
+#define RX_MSDU_END_0_RESERVED_0_LSB 9
+#define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00
+
+/* Description RX_MSDU_END_0_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16
+#define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description RX_MSDU_END_1_IP_HDR_CHKSUM
+
+ This can include the IP header checksum or the pseudo
+ header checksum used by TCP/UDP checksum.
+
+ (with the first byte in the MSB and the second byte in
+ the LSB, i.e. requiring a byte-swap for little-endian FW/SW
+ w.r.t. the byte order in a packet)
+*/
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff
+
+/* Description RX_MSDU_END_1_REPORTED_MPDU_LENGTH
+
+ MPDU length before decapsulation. Only valid when
+ first_msdu is set. This field is taken directly from the
+ length field of the A-MPDU delimiter or the preamble length
+ field for non-A-MPDU frames.
+*/
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16
+#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000
+
+/* Description RX_MSDU_END_1_RESERVED_1A
+
+ <legal 0>
+*/
+#define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_MSDU_END_1_RESERVED_1A_LSB 30
+#define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000
+
+/* Description RX_MSDU_END_2_KEY_ID_OCTET
+
+ The key ID octet from the IV. Only valid when
+ first_msdu is set.
+*/
+#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008
+#define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0
+#define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff
+
+/* Description RX_MSDU_END_2_CCE_SUPER_RULE
+
+ Indicates the super filter rule
+*/
+#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008
+#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8
+#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00
+
+/* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE
+
+ Classification failed due to truncated frame
+*/
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000
+
+/* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS
+
+ Classification failed due to CCE global disable
+*/
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000
+
+/* Description RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM
+
+ FISA: IP header checksum including the total MSDU length
+ that is part of this flow aggregated so far, reported if
+ 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16
+#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000
+
+/* Description RX_MSDU_END_3_RULE_INDICATION_31_0
+
+ Bitmap indicating which of rules 31-0 have matched
+*/
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0
+#define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_END_4_RULE_INDICATION_63_32
+
+ Bitmap indicating which of rules 63-32 have matched
+*/
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0
+#define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff
+
+/* Description RX_MSDU_END_5_DA_OFFSET
+
+ Offset into MSDU buffer for DA
+*/
+#define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014
+#define RX_MSDU_END_5_DA_OFFSET_LSB 0
+#define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f
+
+/* Description RX_MSDU_END_5_SA_OFFSET
+
+ Offset into MSDU buffer for SA
+*/
+#define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014
+#define RX_MSDU_END_5_SA_OFFSET_LSB 6
+#define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0
+
+/* Description RX_MSDU_END_5_DA_OFFSET_VALID
+
+ da_offset field is valid. This will be set to 0 in case
+ of a dynamic A-MSDU when DA is compressed
+*/
+#define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014
+#define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12
+#define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000
+
+/* Description RX_MSDU_END_5_SA_OFFSET_VALID
+
+ sa_offset field is valid. This will be set to 0 in case
+ of a dynamic A-MSDU when SA is compressed
+*/
+#define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014
+#define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13
+#define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000
+
+/* Description RX_MSDU_END_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014
+#define RX_MSDU_END_5_RESERVED_5A_LSB 14
+#define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000
+
+/* Description RX_MSDU_END_5_L3_TYPE
+
+ The 16-bit type value indicating the type of L3 later
+ extracted from LLC/SNAP, set to zero if SNAP is not
+ available
+*/
+#define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014
+#define RX_MSDU_END_5_L3_TYPE_LSB 16
+#define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000
+
+/* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC
+
+ 32 bit CRC computed out of IP v6 extension headers
+*/
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff
+
+/* Description RX_MSDU_END_7_TCP_SEQ_NUMBER
+
+ TCP sequence number (as a number assembled from a TCP
+ packet in big-endian order, i.e. requiring a byte-swap for
+ little-endian FW/SW w.r.t. the byte order in a packet)
+
+
+
+ In Pine, if 'RXOLE_R0_MISC_CONFIG.
+ OVERRIDE_MSDU_END_FIELDS' is set, toeplitz_hash_2_or_4 from
+ 'RX_MSDU_START' will be reported here:
+
+ Controlled by multiple RxOLE registers for TCP/UDP over
+ IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4
+ or IPv6 src/dest addresses is reported; or, Toeplitz hash
+ computed over 4-tuple IPv4 or IPv6 src/dest addresses and
+ src/dest ports is reported. The Flow_id_toeplitz hash can
+ also be reported here. Usually the hash reported here is the
+ one used for hash-based REO routing (see
+ use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO').
+ Optionally the 3-tuple Toeplitz hash over IPv4 or IPv6
+ src/dest addresses and L4 protocol can be reported here.
+
+ (Unsupported in HastingsPrime)
+*/
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff
+
+/* Description RX_MSDU_END_8_TCP_ACK_NUMBER
+
+ TCP acknowledge number (as a number assembled from a TCP
+ packet in big-endian order, i.e. requiring a byte-swap for
+ little-endian FW/SW w.r.t. the byte order in a packet)
+
+
+
+ In Pine, if 'RXOLE_R0_MISC_CONFIG.
+ OVERRIDE_MSDU_END_FIELDS' is set, flow_id_toeplitz from
+ 'RX_MSDU_START' will be reported here:
+
+ Toeplitz hash of 5-tuple {IP source address, IP
+ destination address, IP source port, IP destination port, L4
+ protocol} in case of non-IPSec. In case of IPSec - Toeplitz
+ hash of 4-tuple {IP source address, IP destination address,
+ SPI, L4 protocol}. Optionally the 3-tuple Toeplitz hash over
+ IPv4 or IPv6 src/dest addresses and L4 protocol can be
+ reported here.
+
+ The relevant Toeplitz key registers are provided in
+ RxOLE's instance of common parser module. These registers
+ are separate from the Toeplitz keys used by ASE/FSE modules
+ inside RxOLE. The actual value will be passed on from common
+ parser module to RxOLE in one of the WHO_* TLVs.
+
+ (Unsupported in HastingsPrime)
+*/
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff
+
+/* Description RX_MSDU_END_9_TCP_FLAG
+
+ TCP flags
+
+ {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit
+ in bit 8 and the FIN bit in bit 0, i.e. in big-endian order,
+ i.e. requiring a byte-swap for little-endian FW/SW w.r.t.
+ the byte order in a packet)
+*/
+#define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024
+#define RX_MSDU_END_9_TCP_FLAG_LSB 0
+#define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff
+
+/* Description RX_MSDU_END_9_LRO_ELIGIBLE
+
+ Computed out of TCP and IP fields to indicate that this
+ MSDU is eligible for LRO
+*/
+#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024
+#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9
+#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200
+
+/* Description RX_MSDU_END_9_RESERVED_9A
+
+ NOTE: DO not assign a field... Internally used in
+ RXOLE..
+
+ <legal 0>
+*/
+#define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024
+#define RX_MSDU_END_9_RESERVED_9A_LSB 10
+#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00
+
+/* Description RX_MSDU_END_9_WINDOW_SIZE
+
+ TCP receive window size (as a number assembled from a
+ TCP packet in big-endian order, i.e. requiring a byte-swap
+ for little-endian FW/SW w.r.t. the byte order in a packet)
+
+
+
+ In Pine, if 'RXOLE_R0_MISC_CONFIG.
+ OVERRIDE_MSDU_END_FIELDS' is set, msdu_length from
+ 'RX_MSDU_START' will be reported in the 14 LSBs here:
+
+ MSDU length in bytes after decapsulation. This field is
+ still valid for MPDU frames without A-MSDU. It still
+ represents MSDU length after decapsulation.
+
+ (Unsupported in HastingsPrime)
+*/
+#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024
+#define RX_MSDU_END_9_WINDOW_SIZE_LSB 16
+#define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000
+
+/* Description RX_MSDU_END_10_TCP_UDP_CHKSUM
+
+ The value of the computed TCP/UDP checksum. A mode bit
+ selects whether this checksum is the full checksum or the
+ partial checksum which does not include the pseudo header.
+ (with the first byte in the MSB and the second byte in the
+ LSB, i.e. requiring a byte-swap for little-endian FW/SW
+ w.r.t. the byte order in a packet)
+*/
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff
+
+/* Description RX_MSDU_END_10_SA_IDX_TIMEOUT
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer.
+*/
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16
+#define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000
+
+/* Description RX_MSDU_END_10_DA_IDX_TIMEOUT
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer.
+*/
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17
+#define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000
+
+/* Description RX_MSDU_END_10_MSDU_LIMIT_ERROR
+
+ Indicates that the MSDU threshold was exceeded and thus
+ all the rest of the MSDUs will not be scattered and will not
+ be decapsulated but will be DMA'ed in RAW format as a single
+ MSDU buffer
+*/
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18
+#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000
+
+/* Description RX_MSDU_END_10_FLOW_IDX_TIMEOUT
+
+ Indicates an unsuccessful flow search due to the
+ expiring of the search timer.
+
+ <legal all>
+*/
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19
+#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000
+
+/* Description RX_MSDU_END_10_FLOW_IDX_INVALID
+
+ flow id is not valid
+
+ <legal all>
+*/
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20
+#define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000
+
+/* Description RX_MSDU_END_10_WIFI_PARSER_ERROR
+
+ Indicates that the WiFi frame has one of the following
+ errors
+
+ o has less than minimum allowed bytes as per standard
+
+ o has incomplete VLAN LLC/SNAP (only for non A-MSDUs)
+
+ <legal all>
+*/
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21
+#define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000
+
+/* Description RX_MSDU_END_10_AMSDU_PARSER_ERROR
+
+ A-MSDU could not be properly de-agregated.
+
+ <legal all>
+*/
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22
+#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000
+
+/* Description RX_MSDU_END_10_SA_IS_VALID
+
+ Indicates that OLE found a valid SA entry
+*/
+#define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_END_10_SA_IS_VALID_LSB 23
+#define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_END_10_DA_IS_VALID
+
+ Indicates that OLE found a valid DA entry
+*/
+#define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_END_10_DA_IS_VALID_LSB 24
+#define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000
+
+/* Description RX_MSDU_END_10_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address.
+*/
+#define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028
+#define RX_MSDU_END_10_DA_IS_MCBC_LSB 25
+#define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000
+
+/* Description RX_MSDU_END_10_L3_HEADER_PADDING
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+*/
+#define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028
+#define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26
+#define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000
+
+/* Description RX_MSDU_END_10_FIRST_MSDU
+
+ Indicates the first MSDU of A-MSDU. If both first_msdu
+ and last_msdu are set in the MSDU then this is a
+ non-aggregated MSDU frame: normal MPDU. Interior MSDU in an
+ A-MSDU shall have both first_mpdu and last_mpdu bits set to
+ 0.
+*/
+#define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028
+#define RX_MSDU_END_10_FIRST_MSDU_LSB 28
+#define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000
+
+/* Description RX_MSDU_END_10_LAST_MSDU
+
+ Indicates the last MSDU of the A-MSDU. MPDU end status
+ is only valid when last_msdu is set.
+*/
+#define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028
+#define RX_MSDU_END_10_LAST_MSDU_LSB 29
+#define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000
+
+/* Description RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL
+
+ if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is
+ set, tcp_udp_chksum_fail from 'RX_ATTENTION' will be
+ reported here:
+
+ Indicates that the computed checksum (tcp_udp_chksum)
+ did not match the checksum in the TCP/UDP header.
+
+ (unsupported in HastingsPrime)
+*/
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_END_10_IP_CHKSUM_FAIL
+
+ If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is
+ set, ip_chksum_fail from 'RX_MSDU_START' will be reported in
+ the MSB here:
+
+ Indicates that the computed checksum (ip_hdr_chksum) did
+ not match the checksum in the IP header.
+
+ (unsupported in HastingsPrime)
+*/
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31
+#define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000
+
+/* Description RX_MSDU_END_11_SA_IDX
+
+ The offset in the address table which matches the MAC
+ source address.
+*/
+#define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c
+#define RX_MSDU_END_11_SA_IDX_LSB 0
+#define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff
+
+/* Description RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID
+
+ Based on a register configuration in RXOLE, this field
+ will contain:
+
+ The offset in the address table which matches the MAC
+ destination address
+
+ OR:
+
+ sw_peer_id from the address search entry corresponding
+ to the destination address of the MSDU
+*/
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16
+#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000
+
+/* Description RX_MSDU_END_12_MSDU_DROP
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030
+#define RX_MSDU_END_12_MSDU_DROP_LSB 0
+#define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001
+
+/* Description RX_MSDU_END_12_REO_DESTINATION_INDICATION
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1
+#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e
+
+/* Description RX_MSDU_END_12_FLOW_IDX
+
+ Flow table index
+
+ <legal all>
+*/
+#define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030
+#define RX_MSDU_END_12_FLOW_IDX_LSB 6
+#define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0
+
+/* Description RX_MSDU_END_12_RESERVED_12A
+
+ <legal 0>
+*/
+#define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030
+#define RX_MSDU_END_12_RESERVED_12A_LSB 26
+#define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000
+
+/* Description RX_MSDU_END_13_FSE_METADATA
+
+ FSE related meta data:
+
+ <legal all>
+*/
+#define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034
+#define RX_MSDU_END_13_FSE_METADATA_LSB 0
+#define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff
+
+/* Description RX_MSDU_END_14_CCE_METADATA
+
+ CCE related meta data:
+
+ <legal all>
+*/
+#define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038
+#define RX_MSDU_END_14_CCE_METADATA_LSB 0
+#define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff
+
+/* Description RX_MSDU_END_14_SA_SW_PEER_ID
+
+ sw_peer_id from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038
+#define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16
+#define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000
+
+/* Description RX_MSDU_END_15_AGGREGATION_COUNT
+
+ FISA: Number of MSDU's aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c
+#define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0
+#define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff
+
+/* Description RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION
+
+ FISA: To indicate that this MSDU can be aggregated with
+ the previous packet with the same flow id
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8
+#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100
+
+/* Description RX_MSDU_END_15_FISA_TIMEOUT
+
+ FISA: To indicate that the aggregation has restarted for
+ this flow due to timeout
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c
+#define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9
+#define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200
+
+/* Description RX_MSDU_END_15_RESERVED_15A
+
+ <legal 0>
+*/
+#define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c
+#define RX_MSDU_END_15_RESERVED_15A_LSB 10
+#define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00
+
+/* Description RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM
+
+ FISA: checksum for MSDU's that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0
+#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
+
+/* Description RX_MSDU_END_16_CUMULATIVE_IP_LENGTH
+
+ FISA: Total MSDU length that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16
+#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
+
+
+#endif // _RX_MSDU_END_H_
diff --git a/hw/qca5018/rx_msdu_link.h b/hw/qca5018/rx_msdu_link.h
new file mode 100644
index 0000000..b7b6adf
--- /dev/null
+++ b/hw/qca5018/rx_msdu_link.h
@@ -0,0 +1,4225 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_descriptor_header descriptor_header;
+// 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info;
+// 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17]
+// 4 pn_31_0[31:0]
+// 5 pn_63_32[31:0]
+// 6 pn_95_64[31:0]
+// 7 pn_127_96[31:0]
+// 8-11 struct rx_msdu_details msdu_0;
+// 12-15 struct rx_msdu_details msdu_1;
+// 16-19 struct rx_msdu_details msdu_2;
+// 20-23 struct rx_msdu_details msdu_3;
+// 24-27 struct rx_msdu_details msdu_4;
+// 28-31 struct rx_msdu_details msdu_5;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_LINK 32
+
+struct rx_msdu_link {
+ struct uniform_descriptor_header descriptor_header;
+ struct buffer_addr_info next_msdu_link_desc_addr_info;
+ uint32_t receive_queue_number : 16, //[15:0]
+ first_rx_msdu_link_struct : 1, //[16]
+ reserved_3a : 15; //[31:17]
+ uint32_t pn_31_0 : 32; //[31:0]
+ uint32_t pn_63_32 : 32; //[31:0]
+ uint32_t pn_95_64 : 32; //[31:0]
+ uint32_t pn_127_96 : 32; //[31:0]
+ struct rx_msdu_details msdu_0;
+ struct rx_msdu_details msdu_1;
+ struct rx_msdu_details msdu_2;
+ struct rx_msdu_details msdu_3;
+ struct rx_msdu_details msdu_4;
+ struct rx_msdu_details msdu_5;
+};
+
+/*
+
+struct uniform_descriptor_header descriptor_header
+
+ Details about which module owns this struct.
+
+ Note that sub field Buffer_type shall be set to
+ Receive_MSDU_Link_descriptor
+
+struct buffer_addr_info next_msdu_link_desc_addr_info
+
+ Details of the physical address of the next MSDU link
+ descriptor that contains info about additional MSDUs that
+ are part of this MPDU.
+
+receive_queue_number
+
+ Indicates the Receive queue to which this MPDU
+ descriptor belongs
+
+ Used for tracking, finding bugs and debugging.
+
+ <legal all>
+
+first_rx_msdu_link_struct
+
+ When set, this RX_MSDU_link descriptor is the first one
+ in the MSDU link list. Field MSDU_0 points to the very first
+ MSDU buffer descriptor in the MPDU
+
+ <legal all>
+
+reserved_3a
+
+ <legal 0>
+
+pn_31_0
+
+
+
+
+ 31-0 bits of the 256-bit packet number bitmap.
+
+ <legal all>
+
+pn_63_32
+
+
+
+
+ 63-32 bits of the 256-bit packet number bitmap.
+
+ <legal all>
+
+pn_95_64
+
+
+
+
+ 95-64 bits of the 256-bit packet number bitmap.
+
+ <legal all>
+
+pn_127_96
+
+
+
+
+ 127-96 bits of the 256-bit packet number bitmap.
+
+ <legal all>
+
+struct rx_msdu_details msdu_0
+
+ When First_RX_MSDU_link_struct is set, this MSDU is the
+ first in the MPDU
+
+
+
+ When First_RX_MSDU_link_struct is NOT set, this MSDU
+ follows the last MSDU in the previous RX_MSDU_link data
+ structure
+
+struct rx_msdu_details msdu_1
+
+ Details of next MSDU in this (MSDU flow) linked list
+
+struct rx_msdu_details msdu_2
+
+ Details of next MSDU in this (MSDU flow) linked list
+
+struct rx_msdu_details msdu_3
+
+ Details of next MSDU in this (MSDU flow) linked list
+
+struct rx_msdu_details msdu_4
+
+ Details of next MSDU in this (MSDU flow) linked list
+
+struct rx_msdu_details msdu_5
+
+ Details of next MSDU in this (MSDU flow) linked list
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */
+
+
+/* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ The owner of this data structure:
+
+ <enum 0 WBM_owned> Buffer Manager currently owns this
+ data structure.
+
+ <enum 1 SW_OR_FW_owned> Software of FW currently owns
+ this data structure.
+
+ <enum 2 TQM_owned> Transmit Queue Manager currently owns
+ this data structure.
+
+ <enum 3 RXDMA_owned> Receive DMA currently owns this
+ data structure.
+
+ <enum 4 REO_owned> Reorder currently owns this data
+ structure.
+
+ <enum 5 SWITCH_owned> SWITCH currently owns this data
+ structure.
+
+
+
+ <legal 0-5>
+*/
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+/* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ Field describing what contents format is of this
+ descriptor
+
+
+
+ <enum 0 Transmit_MSDU_Link_descriptor >
+
+ <enum 1 Transmit_MPDU_Link_descriptor >
+
+ <enum 2 Transmit_MPDU_Queue_head_descriptor>
+
+ <enum 3 Transmit_MPDU_Queue_ext_descriptor>
+
+ <enum 4 Transmit_flow_descriptor>
+
+ <enum 5 Transmit_buffer > NOT TO BE USED:
+
+
+
+ <enum 6 Receive_MSDU_Link_descriptor >
+
+ <enum 7 Receive_MPDU_Link_descriptor >
+
+ <enum 8 Receive_REO_queue_descriptor >
+
+ <enum 9 Receive_REO_queue_ext_descriptor >
+
+
+
+ <enum 10 Receive_buffer >
+
+
+
+ <enum 11 Idle_link_list_entry>
+
+
+
+ <legal 0-11>
+*/
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+/* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
+#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info next_msdu_link_desc_addr_info */
+
+
+/* Description RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+/* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER
+
+ Indicates the Receive queue to which this MPDU
+ descriptor belongs
+
+ Used for tracking, finding bugs and debugging.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+/* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT
+
+ When set, this RX_MSDU_link descriptor is the first one
+ in the MSDU link list. Field MSDU_0 points to the very first
+ MSDU buffer descriptor in the MPDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000
+
+/* Description RX_MSDU_LINK_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c
+#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17
+#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000
+
+/* Description RX_MSDU_LINK_4_PN_31_0
+
+
+
+
+ 31-0 bits of the 256-bit packet number bitmap.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010
+#define RX_MSDU_LINK_4_PN_31_0_LSB 0
+#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_5_PN_63_32
+
+
+
+
+ 63-32 bits of the 256-bit packet number bitmap.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014
+#define RX_MSDU_LINK_5_PN_63_32_LSB 0
+#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_6_PN_95_64
+
+
+
+
+ 95-64 bits of the 256-bit packet number bitmap.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018
+#define RX_MSDU_LINK_6_PN_95_64_LSB 0
+#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_7_PN_127_96
+
+
+
+
+ 127-96 bits of the 256-bit packet number bitmap.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c
+#define RX_MSDU_LINK_7_PN_127_96_LSB 0
+#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_0 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
+
+
+/* Description RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
+
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000028
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+/* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000002c
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_1 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
+
+
+/* Description RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
+
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000038
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+/* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000003c
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_2 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
+
+
+/* Description RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
+
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000048
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+/* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000004c
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_3 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
+
+
+/* Description RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
+
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000058
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+/* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000005c
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_4 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
+
+
+/* Description RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
+
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000068
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+/* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000006c
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_5 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */
+
+
+/* Description RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
+#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11
+#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */
+
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_first_msdu> This is not the first MSDU in
+ the MPDU.
+
+ <enum 1 first_msdu> This MSDU is the first one in the
+ MPDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG
+
+ Consumer: WBM/REO/SW/FW
+
+ Producer: RXDMA
+
+
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ <enum 0 Not_last_msdu> There are more MSDUs linked to
+ this MSDU that belongs to this MPDU
+
+ <enum 1 Last_msdu> this MSDU is the last one in the
+ MPDU. This setting is only allowed in combination with
+ 'Msdu_continuation' set to 0. This implies that when an msdu
+ is spread out over multiple buffers and thus
+ msdu_continuation is set, only for the very last buffer of
+ the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+
+
+
+ When both first_msdu_in_mpdu_flag and
+ last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+ belongs to only contains a single MSDU.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION
+
+ When set, this MSDU buffer was not able to hold the
+ entire MSDU. The next buffer will therefor contain
+ additional information related to this MSDU.
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH
+
+ Parsed from RX_MSDU_START TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the First
+ buffer used by MSDU.
+
+
+
+ Full MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+ A-MSDU. It still represents MSDU length after decapsulation
+
+
+
+ Or in case of RAW MPDUs, it indicates the length of the
+ entire MPDU (without FCS field)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ When set, REO shall drop this MSDU and not forward it to
+ any other ring...
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid SA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC source address search due
+ to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates that OLE found a valid DA entry for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC
+
+ Field Only valid if da_is_valid is set
+
+
+
+ Indicates the DA address was a Multicast of Broadcast
+ address for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT
+
+ Parsed from RX_MSDU_END TLV . In the case MSDU spans
+ over multiple buffers, this field will be valid in the Last
+ buffer used by the MSDU
+
+
+
+ Indicates an unsuccessful MAC destination address search
+ due to the expiring of the search timer for this MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB
+
+ Passed on from 'RX_MSDU_END' TLV (only the MSB is
+ reported as the LSB is always zero)
+
+ Number of bytes padded to make sure that the L3 header
+ will always start of a Dword boundary
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_LSB 28
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_L3_HEADER_PADDING_MSB_MASK 0x10000000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the TCP/UDP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_LSB 29
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TCP_UDP_CHKSUM_FAIL_MASK 0x20000000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL
+
+ Passed on from 'RX_ATTENTION' TLV
+
+ Indicates that the computed checksum did not match the
+ checksum in the IP header.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_LSB 30
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_IP_CHKSUM_FAIL_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set to 1 by RXOLE when it has not performed any 802.11
+ to Ethernet/Natvie WiFi header conversion on this MPDU.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000078
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 31
+#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x80000000
+
+/* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MSDU_END' TLV (one MSB is omitted)
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The offset in the address search table which matches the
+ MAC source address
+
+ OR
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to the source address of the MSDU
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_LSB 0
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_OR_SW_PEER_ID_14_0_MASK 0x00007fff
+
+/* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV (one MSB is omitted)
+
+
+
+ Based on a register configuration in RXDMA, this field
+ will contain:
+
+ The index of the address search entry corresponding to
+ this MPDU (a value of 0xFFFF indicates an invalid AST index,
+ meaning that no AST entry was found or no AST search was
+ performed)
+
+
+
+ OR:
+
+
+
+ 'sw_peer_id' from the address search entry corresponding
+ to this MPDU (in case of ndp or phy_err or
+ AST_based_lookup_valid == 0, this field will be set to 0)
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_LSB 15
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MPDU_AST_IDX_OR_SW_PEER_ID_14_0_MASK 0x3fff8000
+
+/* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'from DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_LSB 30
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FR_DS_MASK 0x40000000
+
+/* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS
+
+ Passed on from 'RX_MPDU_INFO' structure in
+ 'RX_MPDU_START' TLV
+
+ Set if the 'to DS' bit is set in the frame control.
+
+ <legal all>
+*/
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_OFFSET 0x0000007c
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_LSB 31
+#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_TO_DS_MASK 0x80000000
+
+
+#endif // _RX_MSDU_LINK_H_
diff --git a/hw/qca5018/rx_msdu_start.h b/hw/qca5018/rx_msdu_start.h
new file mode 100644
index 0000000..da5fbb2
--- /dev/null
+++ b/hw/qca5018/rx_msdu_start.h
@@ -0,0 +1,1200 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
+// 1 msdu_length[13:0], reserved_1a[14], ipsec_esp[15], l3_offset[22:16], ipsec_ah[23], l4_offset[31:24]
+// 2 msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], da_is_bcast_mcast[16], toeplitz_hash_sel[18:17], ip_fixed_header_valid[19], ip_extn_header_valid[20], tcp_udp_header_valid[21], mesh_control_present[22], ldpc[23], ip4_protocol_ip6_next_header[31:24]
+// 3 toeplitz_hash_2_or_4[31:0]
+// 4 flow_id_toeplitz[31:0]
+// 5 user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[23:21], mimo_ss_bitmap[31:24]
+// 6 ppdu_start_timestamp[31:0]
+// 7 sw_phy_meta_data[31:0]
+// 8 vlan_ctag_ci[15:0], vlan_stag_ci[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_START 9
+
+struct rx_msdu_start {
+ uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0]
+ sw_frame_group_id : 7, //[8:2]
+ reserved_0 : 7, //[15:9]
+ phy_ppdu_id : 16; //[31:16]
+ uint32_t msdu_length : 14, //[13:0]
+ reserved_1a : 1, //[14]
+ ipsec_esp : 1, //[15]
+ l3_offset : 7, //[22:16]
+ ipsec_ah : 1, //[23]
+ l4_offset : 8; //[31:24]
+ uint32_t msdu_number : 8, //[7:0]
+ decap_format : 2, //[9:8]
+ ipv4_proto : 1, //[10]
+ ipv6_proto : 1, //[11]
+ tcp_proto : 1, //[12]
+ udp_proto : 1, //[13]
+ ip_frag : 1, //[14]
+ tcp_only_ack : 1, //[15]
+ da_is_bcast_mcast : 1, //[16]
+ toeplitz_hash_sel : 2, //[18:17]
+ ip_fixed_header_valid : 1, //[19]
+ ip_extn_header_valid : 1, //[20]
+ tcp_udp_header_valid : 1, //[21]
+ mesh_control_present : 1, //[22]
+ ldpc : 1, //[23]
+ ip4_protocol_ip6_next_header : 8; //[31:24]
+ uint32_t toeplitz_hash_2_or_4 : 32; //[31:0]
+ uint32_t flow_id_toeplitz : 32; //[31:0]
+ uint32_t user_rssi : 8, //[7:0]
+ pkt_type : 4, //[11:8]
+ stbc : 1, //[12]
+ sgi : 2, //[14:13]
+ rate_mcs : 4, //[18:15]
+ receive_bandwidth : 2, //[20:19]
+ reception_type : 3, //[23:21]
+ mimo_ss_bitmap : 8; //[31:24]
+ uint32_t ppdu_start_timestamp : 32; //[31:0]
+ uint32_t sw_phy_meta_data : 32; //[31:0]
+ uint32_t vlan_ctag_ci : 16, //[15:0]
+ vlan_stag_ci : 16; //[31:16]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+ <legal 0-2>
+
+sw_frame_group_id
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame>
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+
+
+
+
+
+ <legal 0-37>
+
+reserved_0
+
+ <legal 0>
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+
+msdu_length
+
+ MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+
+reserved_1a
+
+ <legal 0>
+
+ipsec_esp
+
+ Set if IPv4/v6 packet is using IPsec ESP
+
+l3_offset
+
+ Depending upon mode bit, this field either indicates the
+ L3 offset in bytes from the start of the RX_HEADER or the IP
+ offset in bytes from the start of the packet after
+ decapsulation. The latter is only valid if ipv4_proto or
+ ipv6_proto is set.
+
+ipsec_ah
+
+ Set if IPv4/v6 packet is using IPsec AH
+
+l4_offset
+
+ Depending upon mode bit, this field either indicates the
+ L4 offset nin bytes from the start of RX_HEADER(only valid
+ if either ipv4_proto or ipv6_proto is set to 1) or indicates
+ the offset in bytes to the start of TCP or UDP header from
+ the start of the IP header after decapsulation(Only valid if
+ tcp_proto or udp_proto is set). The value 0 indicates that
+ the offset is longer than 127 bytes.
+
+msdu_number
+
+ Indicates the MSDU number within a MPDU. This value is
+ reset to zero at the start of each MPDU. If the number of
+ MSDU exceeds 255 this number will wrap using modulo 256.
+
+decap_format
+
+ Indicates the format after decapsulation:
+
+
+
+ <enum 0 RAW> No encapsulation
+
+ <enum 1 Native_WiFi>
+
+ <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses
+ SNAP/LLC)
+
+ <enum 3 802_3> Indicate Ethernet
+
+
+
+ <legal all>
+
+ipv4_proto
+
+ Set if L2 layer indicates IPv4 protocol.
+
+ipv6_proto
+
+ Set if L2 layer indicates IPv6 protocol.
+
+tcp_proto
+
+ Set if the ipv4_proto or ipv6_proto are set and the IP
+ protocol indicates TCP.
+
+udp_proto
+
+ Set if the ipv4_proto or ipv6_proto are set and the IP
+ protocol indicates UDP.
+
+ip_frag
+
+ Indicates that either the IP More frag bit is set or IP
+ frag number is non-zero. If set indicates that this is a
+ fragmented IP packet.
+
+tcp_only_ack
+
+ Set if only the TCP Ack bit is set in the TCP flags and
+ if the TCP payload is 0.
+
+da_is_bcast_mcast
+
+ The destination address is broadcast or multicast.
+
+toeplitz_hash_sel
+
+ Actual choosen Hash.
+
+
+
+ 0 -> Toeplitz hash of 2-tuple (IP source address, IP
+ destination address)1 -> Toeplitz hash of 4-tuple (IP source
+ address, IP destination address, L4 (TCP/UDP) source port,
+ L4 (TCP/UDP) destination port)
+
+ 2 -> Toeplitz of flow_id
+
+ 3 -> Zero is used
+
+ <legal all>
+
+ip_fixed_header_valid
+
+ Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
+ fully within first 256 bytes of the packet
+
+ip_extn_header_valid
+
+ IPv6/IPv6 header, including IPv4 options and
+ recognizable extension headers parsed fully within first 256
+ bytes of the packet
+
+tcp_udp_header_valid
+
+ Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
+ header parsed fully within first 256 bytes of the packet
+
+mesh_control_present
+
+ When set, this MSDU includes the 'Mesh Control' field
+
+ <legal all>
+
+ldpc
+
+ When set, indicates that LDPC coding was used.
+
+ <legal all>
+
+ip4_protocol_ip6_next_header
+
+ For IPv4 this is the 8 bit protocol field (when
+ ipv4_proto is set). For IPv6 this is the 8 bit next_header
+ field (when ipv6_proto is set).
+
+toeplitz_hash_2_or_4
+
+ Controlled by multiple RxOLE registers for TCP/UDP over
+ IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple IPv4
+ or IPv6 src/dest addresses is reported; or, Toeplitz hash
+ computed over 4-tuple IPv4 or IPv6 src/dest addresses and
+ src/dest ports is reported. The Flow_id_toeplitz hash can
+ also be reported here. Usually the hash reported here is the
+ one used for hash-based REO routing (see
+ use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO').
+
+
+
+ In Pine, optionally the 3-tuple Toeplitz hash over IPv4
+ or IPv6 src/dest addresses and L4 protocol can be reported
+ here. (Unsupported in HastingsPrime)
+
+flow_id_toeplitz
+
+ Toeplitz hash of 5-tuple
+
+ {IP source address, IP destination address, IP source
+ port, IP destination port, L4 protocol} in case of
+ non-IPSec.
+
+ In case of IPSec - Toeplitz hash of 4-tuple
+
+ {IP source address, IP destination address, SPI, L4
+ protocol}
+
+
+
+ In Pine, optionally the 3-tuple Toeplitz hash over IPv4
+ or IPv6 src/dest addresses and L4 protocol can be reported
+ here. (Unsupported in HastingsPrime)
+
+
+
+ The relevant Toeplitz key registers are provided in
+ RxOLE's instance of common parser module. These registers
+ are separate from the Toeplitz keys used by ASE/FSE modules
+ inside RxOLE.The actual value will be passed on from common
+ parser module to RxOLE in one of the WHO_* TLVs.
+
+ <legal all>
+
+user_rssi
+
+ RSSI for this user
+
+ <legal all>
+
+pkt_type
+
+ Packet type:
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+
+stbc
+
+ When set, use STBC transmission rates
+
+sgi
+
+ Field only valid when pkt type is HT, VHT or HE.
+
+
+
+ <enum 0 0_8_us_sgi > Legacy normal GI. Can also be
+ used for HE
+
+ <enum 1 0_4_us_sgi > Legacy short GI. Can also be
+ used for HE
+
+ <enum 2 1_6_us_sgi > HE related GI
+
+ <enum 3 3_2_us_sgi > HE related GI
+
+ <legal 0 - 3>
+
+rate_mcs
+
+ For details, refer to MCS_TYPE description
+
+ Note: This is rate in case of 11a/11b
+
+
+
+ <legal all>
+
+receive_bandwidth
+
+ Full receive Bandwidth
+
+
+
+ <enum 0 full_rx_bw_20_mhz>
+
+ <enum 1 full_rx_bw_40_mhz>
+
+ <enum 2 full_rx_bw_80_mhz>
+
+ <enum 3 full_rx_bw_160_mhz>
+
+
+
+ <legal 0-3>
+
+reception_type
+
+ Indicates what type of reception this is.
+
+ <enum 0 reception_type_SU > Basic SU reception (not
+ part of OFDMA or MIMO)
+
+ <enum 1 reception_type_MU_MIMO > This is related to
+ DL type of reception
+
+ <enum 2 reception_type_MU_OFDMA > This is related
+ to DL type of reception
+
+ <enum 3 reception_type_MU_OFDMA_MIMO > This is
+ related to DL type of reception
+
+ <enum 4 reception_type_UL_MU_MIMO > This is related
+ to UL type of reception
+
+ <enum 5 reception_type_UL_MU_OFDMA > This is
+ related to UL type of reception
+
+ <enum 6 reception_type_UL_MU_OFDMA_MIMO > This is
+ related to UL type of reception
+
+
+
+ <legal 0-6>
+
+mimo_ss_bitmap
+
+ Field only valid when Reception_type for the MPDU from
+ this STA is some form of MIMO reception
+
+
+
+ Bitmap, with each bit indicating if the related spatial
+ stream is used for this STA
+
+ LSB related to SS 0
+
+
+
+ 0: spatial stream not used for this reception
+
+ 1: spatial stream used for this reception
+
+
+
+ <legal all>
+
+ppdu_start_timestamp
+
+ Timestamp that indicates when the PPDU that contained
+ this MPDU started on the medium.
+
+ <legal all>
+
+sw_phy_meta_data
+
+ SW programmed Meta data provided by the PHY.
+
+
+
+ Can be used for SW to indicate the channel the device is
+ on.
+
+ <legal all>
+
+vlan_ctag_ci
+
+ 2 bytes of C-VLAN Tag Control Information from
+ WHO_L2_LLC
+
+vlan_stag_ci
+
+ 2 bytes of S-VLAN Tag Control Information from
+ WHO_L2_LLC in case of double VLAN
+*/
+
+
+/* Description RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+
+ Field indicates what the reason was that this MPDU frame
+ was allowed to come into the receive path by RXPCU
+
+ <enum 0 rxpcu_filter_pass> This MPDU passed the normal
+ frame filter programming of rxpcu
+
+ <enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+ regular frame filter and would have been dropped, were it
+ not for the frame fitting into the 'monitor_client'
+ category.
+
+ <enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+ regular frame filter and also did not pass the
+ rxpcu_monitor_client filter. It would have been dropped
+ accept that it did pass the 'monitor_other' category.
+
+ <legal 0-2>
+*/
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003
+
+/* Description RX_MSDU_START_0_SW_FRAME_GROUP_ID
+
+ SW processes frames based on certain classifications.
+ This field indicates to what sw classification this MPDU is
+ mapped.
+
+ The classification is given in priority order
+
+
+
+ <enum 0 sw_frame_group_NDP_frame>
+
+
+
+ <enum 1 sw_frame_group_Multicast_data>
+
+ <enum 2 sw_frame_group_Unicast_data>
+
+ <enum 3 sw_frame_group_Null_data > This includes mpdus
+ of type Data Null as well as QoS Data Null
+
+
+
+ <enum 4 sw_frame_group_mgmt_0000 >
+
+ <enum 5 sw_frame_group_mgmt_0001 >
+
+ <enum 6 sw_frame_group_mgmt_0010 >
+
+ <enum 7 sw_frame_group_mgmt_0011 >
+
+ <enum 8 sw_frame_group_mgmt_0100 >
+
+ <enum 9 sw_frame_group_mgmt_0101 >
+
+ <enum 10 sw_frame_group_mgmt_0110 >
+
+ <enum 11 sw_frame_group_mgmt_0111 >
+
+ <enum 12 sw_frame_group_mgmt_1000 >
+
+ <enum 13 sw_frame_group_mgmt_1001 >
+
+ <enum 14 sw_frame_group_mgmt_1010 >
+
+ <enum 15 sw_frame_group_mgmt_1011 >
+
+ <enum 16 sw_frame_group_mgmt_1100 >
+
+ <enum 17 sw_frame_group_mgmt_1101 >
+
+ <enum 18 sw_frame_group_mgmt_1110 >
+
+ <enum 19 sw_frame_group_mgmt_1111 >
+
+
+
+ <enum 20 sw_frame_group_ctrl_0000 >
+
+ <enum 21 sw_frame_group_ctrl_0001 >
+
+ <enum 22 sw_frame_group_ctrl_0010 >
+
+ <enum 23 sw_frame_group_ctrl_0011 >
+
+ <enum 24 sw_frame_group_ctrl_0100 >
+
+ <enum 25 sw_frame_group_ctrl_0101 >
+
+ <enum 26 sw_frame_group_ctrl_0110 >
+
+ <enum 27 sw_frame_group_ctrl_0111 >
+
+ <enum 28 sw_frame_group_ctrl_1000 >
+
+ <enum 29 sw_frame_group_ctrl_1001 >
+
+ <enum 30 sw_frame_group_ctrl_1010 >
+
+ <enum 31 sw_frame_group_ctrl_1011 >
+
+ <enum 32 sw_frame_group_ctrl_1100 >
+
+ <enum 33 sw_frame_group_ctrl_1101 >
+
+ <enum 34 sw_frame_group_ctrl_1110 >
+
+ <enum 35 sw_frame_group_ctrl_1111 >
+
+
+
+ <enum 36 sw_frame_group_unsupported> This covers type 3
+ and protocol version != 0
+
+
+
+
+
+
+ <legal 0-37>
+*/
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB 2
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc
+
+/* Description RX_MSDU_START_0_RESERVED_0
+
+ <legal 0>
+*/
+#define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000
+#define RX_MSDU_START_0_RESERVED_0_LSB 9
+#define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00
+
+/* Description RX_MSDU_START_0_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_MSDU_START_0_PHY_PPDU_ID_LSB 16
+#define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description RX_MSDU_START_1_MSDU_LENGTH
+
+ MSDU length in bytes after decapsulation.
+
+
+
+ This field is still valid for MPDU frames without
+*/
+#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004
+#define RX_MSDU_START_1_MSDU_LENGTH_LSB 0
+#define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff
+
+/* Description RX_MSDU_START_1_RESERVED_1A
+
+ <legal 0>
+*/
+#define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_MSDU_START_1_RESERVED_1A_LSB 14
+#define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000
+
+/* Description RX_MSDU_START_1_IPSEC_ESP
+
+ Set if IPv4/v6 packet is using IPsec ESP
+*/
+#define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004
+#define RX_MSDU_START_1_IPSEC_ESP_LSB 15
+#define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000
+
+/* Description RX_MSDU_START_1_L3_OFFSET
+
+ Depending upon mode bit, this field either indicates the
+ L3 offset in bytes from the start of the RX_HEADER or the IP
+ offset in bytes from the start of the packet after
+ decapsulation. The latter is only valid if ipv4_proto or
+ ipv6_proto is set.
+*/
+#define RX_MSDU_START_1_L3_OFFSET_OFFSET 0x00000004
+#define RX_MSDU_START_1_L3_OFFSET_LSB 16
+#define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000
+
+/* Description RX_MSDU_START_1_IPSEC_AH
+
+ Set if IPv4/v6 packet is using IPsec AH
+*/
+#define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004
+#define RX_MSDU_START_1_IPSEC_AH_LSB 23
+#define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000
+
+/* Description RX_MSDU_START_1_L4_OFFSET
+
+ Depending upon mode bit, this field either indicates the
+ L4 offset nin bytes from the start of RX_HEADER(only valid
+ if either ipv4_proto or ipv6_proto is set to 1) or indicates
+ the offset in bytes to the start of TCP or UDP header from
+ the start of the IP header after decapsulation(Only valid if
+ tcp_proto or udp_proto is set). The value 0 indicates that
+ the offset is longer than 127 bytes.
+*/
+#define RX_MSDU_START_1_L4_OFFSET_OFFSET 0x00000004
+#define RX_MSDU_START_1_L4_OFFSET_LSB 24
+#define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000
+
+/* Description RX_MSDU_START_2_MSDU_NUMBER
+
+ Indicates the MSDU number within a MPDU. This value is
+ reset to zero at the start of each MPDU. If the number of
+ MSDU exceeds 255 this number will wrap using modulo 256.
+*/
+#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET 0x00000008
+#define RX_MSDU_START_2_MSDU_NUMBER_LSB 0
+#define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff
+
+/* Description RX_MSDU_START_2_DECAP_FORMAT
+
+ Indicates the format after decapsulation:
+
+
+
+ <enum 0 RAW> No encapsulation
+
+ <enum 1 Native_WiFi>
+
+ <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses
+ SNAP/LLC)
+
+ <enum 3 802_3> Indicate Ethernet
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008
+#define RX_MSDU_START_2_DECAP_FORMAT_LSB 8
+#define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300
+
+/* Description RX_MSDU_START_2_IPV4_PROTO
+
+ Set if L2 layer indicates IPv4 protocol.
+*/
+#define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_2_IPV4_PROTO_LSB 10
+#define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400
+
+/* Description RX_MSDU_START_2_IPV6_PROTO
+
+ Set if L2 layer indicates IPv6 protocol.
+*/
+#define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_2_IPV6_PROTO_LSB 11
+#define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800
+
+/* Description RX_MSDU_START_2_TCP_PROTO
+
+ Set if the ipv4_proto or ipv6_proto are set and the IP
+ protocol indicates TCP.
+*/
+#define RX_MSDU_START_2_TCP_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_2_TCP_PROTO_LSB 12
+#define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000
+
+/* Description RX_MSDU_START_2_UDP_PROTO
+
+ Set if the ipv4_proto or ipv6_proto are set and the IP
+ protocol indicates UDP.
+*/
+#define RX_MSDU_START_2_UDP_PROTO_OFFSET 0x00000008
+#define RX_MSDU_START_2_UDP_PROTO_LSB 13
+#define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000
+
+/* Description RX_MSDU_START_2_IP_FRAG
+
+ Indicates that either the IP More frag bit is set or IP
+ frag number is non-zero. If set indicates that this is a
+ fragmented IP packet.
+*/
+#define RX_MSDU_START_2_IP_FRAG_OFFSET 0x00000008
+#define RX_MSDU_START_2_IP_FRAG_LSB 14
+#define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000
+
+/* Description RX_MSDU_START_2_TCP_ONLY_ACK
+
+ Set if only the TCP Ack bit is set in the TCP flags and
+ if the TCP payload is 0.
+*/
+#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET 0x00000008
+#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15
+#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000
+
+/* Description RX_MSDU_START_2_DA_IS_BCAST_MCAST
+
+ The destination address is broadcast or multicast.
+*/
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET 0x00000008
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB 16
+#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK 0x00010000
+
+/* Description RX_MSDU_START_2_TOEPLITZ_HASH_SEL
+
+ Actual choosen Hash.
+
+
+
+ 0 -> Toeplitz hash of 2-tuple (IP source address, IP
+ destination address)1 -> Toeplitz hash of 4-tuple (IP source
+ address, IP destination address, L4 (TCP/UDP) source port,
+ L4 (TCP/UDP) destination port)
+
+ 2 -> Toeplitz of flow_id
+
+ 3 -> Zero is used
+
+ <legal all>
+*/
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_OFFSET 0x00000008
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_LSB 17
+#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_MASK 0x00060000
+
+/* Description RX_MSDU_START_2_IP_FIXED_HEADER_VALID
+
+ Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
+ fully within first 256 bytes of the packet
+*/
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_LSB 19
+#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_MASK 0x00080000
+
+/* Description RX_MSDU_START_2_IP_EXTN_HEADER_VALID
+
+ IPv6/IPv6 header, including IPv4 options and
+ recognizable extension headers parsed fully within first 256
+ bytes of the packet
+*/
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_LSB 20
+#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_MASK 0x00100000
+
+/* Description RX_MSDU_START_2_TCP_UDP_HEADER_VALID
+
+ Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
+ header parsed fully within first 256 bytes of the packet
+*/
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_OFFSET 0x00000008
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_LSB 21
+#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_MASK 0x00200000
+
+/* Description RX_MSDU_START_2_MESH_CONTROL_PRESENT
+
+ When set, this MSDU includes the 'Mesh Control' field
+
+ <legal all>
+*/
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_OFFSET 0x00000008
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_LSB 22
+#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_MASK 0x00400000
+
+/* Description RX_MSDU_START_2_LDPC
+
+ When set, indicates that LDPC coding was used.
+
+ <legal all>
+*/
+#define RX_MSDU_START_2_LDPC_OFFSET 0x00000008
+#define RX_MSDU_START_2_LDPC_LSB 23
+#define RX_MSDU_START_2_LDPC_MASK 0x00800000
+
+/* Description RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER
+
+ For IPv4 this is the 8 bit protocol field (when
+ ipv4_proto is set). For IPv6 this is the 8 bit next_header
+ field (when ipv6_proto is set).
+*/
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24
+#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000
+
+/* Description RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4
+
+ Controlled by multiple RxOLE registers for TCP/UDP over
+ IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple IPv4
+ or IPv6 src/dest addresses is reported; or, Toeplitz hash
+ computed over 4-tuple IPv4 or IPv6 src/dest addresses and
+ src/dest ports is reported. The Flow_id_toeplitz hash can
+ also be reported here. Usually the hash reported here is the
+ one used for hash-based REO routing (see
+ use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO').
+
+
+
+ In Pine, optionally the 3-tuple Toeplitz hash over IPv4
+ or IPv6 src/dest addresses and L4 protocol can be reported
+ here. (Unsupported in HastingsPrime)
+*/
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB 0
+#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff
+
+/* Description RX_MSDU_START_4_FLOW_ID_TOEPLITZ
+
+ Toeplitz hash of 5-tuple
+
+ {IP source address, IP destination address, IP source
+ port, IP destination port, L4 protocol} in case of
+ non-IPSec.
+
+ In case of IPSec - Toeplitz hash of 4-tuple
+
+ {IP source address, IP destination address, SPI, L4
+ protocol}
+
+
+
+ In Pine, optionally the 3-tuple Toeplitz hash over IPv4
+ or IPv6 src/dest addresses and L4 protocol can be reported
+ here. (Unsupported in HastingsPrime)
+
+
+
+ The relevant Toeplitz key registers are provided in
+ RxOLE's instance of common parser module. These registers
+ are separate from the Toeplitz keys used by ASE/FSE modules
+ inside RxOLE.The actual value will be passed on from common
+ parser module to RxOLE in one of the WHO_* TLVs.
+
+ <legal all>
+*/
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET 0x00000010
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB 0
+#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK 0xffffffff
+
+/* Description RX_MSDU_START_5_USER_RSSI
+
+ RSSI for this user
+
+ <legal all>
+*/
+#define RX_MSDU_START_5_USER_RSSI_OFFSET 0x00000014
+#define RX_MSDU_START_5_USER_RSSI_LSB 0
+#define RX_MSDU_START_5_USER_RSSI_MASK 0x000000ff
+
+/* Description RX_MSDU_START_5_PKT_TYPE
+
+ Packet type:
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+*/
+#define RX_MSDU_START_5_PKT_TYPE_OFFSET 0x00000014
+#define RX_MSDU_START_5_PKT_TYPE_LSB 8
+#define RX_MSDU_START_5_PKT_TYPE_MASK 0x00000f00
+
+/* Description RX_MSDU_START_5_STBC
+
+ When set, use STBC transmission rates
+*/
+#define RX_MSDU_START_5_STBC_OFFSET 0x00000014
+#define RX_MSDU_START_5_STBC_LSB 12
+#define RX_MSDU_START_5_STBC_MASK 0x00001000
+
+/* Description RX_MSDU_START_5_SGI
+
+ Field only valid when pkt type is HT, VHT or HE.
+
+
+
+ <enum 0 0_8_us_sgi > Legacy normal GI. Can also be
+ used for HE
+
+ <enum 1 0_4_us_sgi > Legacy short GI. Can also be
+ used for HE
+
+ <enum 2 1_6_us_sgi > HE related GI
+
+ <enum 3 3_2_us_sgi > HE related GI
+
+ <legal 0 - 3>
+*/
+#define RX_MSDU_START_5_SGI_OFFSET 0x00000014
+#define RX_MSDU_START_5_SGI_LSB 13
+#define RX_MSDU_START_5_SGI_MASK 0x00006000
+
+/* Description RX_MSDU_START_5_RATE_MCS
+
+ For details, refer to MCS_TYPE description
+
+ Note: This is rate in case of 11a/11b
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_START_5_RATE_MCS_OFFSET 0x00000014
+#define RX_MSDU_START_5_RATE_MCS_LSB 15
+#define RX_MSDU_START_5_RATE_MCS_MASK 0x00078000
+
+/* Description RX_MSDU_START_5_RECEIVE_BANDWIDTH
+
+ Full receive Bandwidth
+
+
+
+ <enum 0 full_rx_bw_20_mhz>
+
+ <enum 1 full_rx_bw_40_mhz>
+
+ <enum 2 full_rx_bw_80_mhz>
+
+ <enum 3 full_rx_bw_160_mhz>
+
+
+
+ <legal 0-3>
+*/
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET 0x00000014
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB 19
+#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK 0x00180000
+
+/* Description RX_MSDU_START_5_RECEPTION_TYPE
+
+ Indicates what type of reception this is.
+
+ <enum 0 reception_type_SU > Basic SU reception (not
+ part of OFDMA or MIMO)
+
+ <enum 1 reception_type_MU_MIMO > This is related to
+ DL type of reception
+
+ <enum 2 reception_type_MU_OFDMA > This is related
+ to DL type of reception
+
+ <enum 3 reception_type_MU_OFDMA_MIMO > This is
+ related to DL type of reception
+
+ <enum 4 reception_type_UL_MU_MIMO > This is related
+ to UL type of reception
+
+ <enum 5 reception_type_UL_MU_OFDMA > This is
+ related to UL type of reception
+
+ <enum 6 reception_type_UL_MU_OFDMA_MIMO > This is
+ related to UL type of reception
+
+
+
+ <legal 0-6>
+*/
+#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET 0x00000014
+#define RX_MSDU_START_5_RECEPTION_TYPE_LSB 21
+#define RX_MSDU_START_5_RECEPTION_TYPE_MASK 0x00e00000
+
+/* Description RX_MSDU_START_5_MIMO_SS_BITMAP
+
+ Field only valid when Reception_type for the MPDU from
+ this STA is some form of MIMO reception
+
+
+
+ Bitmap, with each bit indicating if the related spatial
+ stream is used for this STA
+
+ LSB related to SS 0
+
+
+
+ 0: spatial stream not used for this reception
+
+ 1: spatial stream used for this reception
+
+
+
+ <legal all>
+*/
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET 0x00000014
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_LSB 24
+#define RX_MSDU_START_5_MIMO_SS_BITMAP_MASK 0xff000000
+
+/* Description RX_MSDU_START_6_PPDU_START_TIMESTAMP
+
+ Timestamp that indicates when the PPDU that contained
+ this MPDU started on the medium.
+
+ <legal all>
+*/
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET 0x00000018
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB 0
+#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK 0xffffffff
+
+/* Description RX_MSDU_START_7_SW_PHY_META_DATA
+
+ SW programmed Meta data provided by the PHY.
+
+
+
+ Can be used for SW to indicate the channel the device is
+ on.
+
+ <legal all>
+*/
+#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET 0x0000001c
+#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB 0
+#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK 0xffffffff
+
+/* Description RX_MSDU_START_8_VLAN_CTAG_CI
+
+ 2 bytes of C-VLAN Tag Control Information from
+ WHO_L2_LLC
+*/
+#define RX_MSDU_START_8_VLAN_CTAG_CI_OFFSET 0x00000020
+#define RX_MSDU_START_8_VLAN_CTAG_CI_LSB 0
+#define RX_MSDU_START_8_VLAN_CTAG_CI_MASK 0x0000ffff
+
+/* Description RX_MSDU_START_8_VLAN_STAG_CI
+
+ 2 bytes of S-VLAN Tag Control Information from
+ WHO_L2_LLC in case of double VLAN
+*/
+#define RX_MSDU_START_8_VLAN_STAG_CI_OFFSET 0x00000020
+#define RX_MSDU_START_8_VLAN_STAG_CI_LSB 16
+#define RX_MSDU_START_8_VLAN_STAG_CI_MASK 0xffff0000
+
+
+#endif // _RX_MSDU_START_H_
diff --git a/hw/qca5018/rx_ppdu_end_user_stats.h b/hw/qca5018/rx_ppdu_end_user_stats.h
new file mode 100644
index 0000000..b0633bc
--- /dev/null
+++ b/hw/qca5018/rx_ppdu_end_user_stats.h
@@ -0,0 +1,2150 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_PPDU_END_USER_STATS_H_
+#define _RX_PPDU_END_USER_STATS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_rxpcu_classification_overview.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct rx_rxpcu_classification_overview rxpcu_classification_details;
+// 1 sta_full_aid[12:0], mcs[16:13], nss[19:17], ofdma_info_valid[20], dl_ofdma_ru_start_index[27:21], reserved_1a[31:28]
+// 2 dl_ofdma_ru_width[6:0], reserved_2a[7], user_receive_quality[15:8], mpdu_cnt_fcs_err[25:16], wbm2rxdma_buf_source_used[26], fw2rxdma_buf_source_used[27], sw2rxdma_buf_source_used[28], reserved_2b[31:29]
+// 3 mpdu_cnt_fcs_ok[8:0], frame_control_info_valid[9], qos_control_info_valid[10], ht_control_info_valid[11], data_sequence_control_info_valid[12], ht_control_info_null_valid[13], reserved_3a[15:14], rxdma2reo_ring_used[16], rxdma2fw_ring_used[17], rxdma2sw_ring_used[18], rxdma_release_ring_used[19], ht_control_field_pkt_type[23:20], reserved_3b[31:24]
+// 4 ast_index[15:0], frame_control_field[31:16]
+// 5 first_data_seq_ctrl[15:0], qos_control_field[31:16]
+// 6 ht_control_field[31:0]
+// 7 fcs_ok_bitmap_31_0[31:0]
+// 8 fcs_ok_bitmap_63_32[31:0]
+// 9 udp_msdu_count[15:0], tcp_msdu_count[31:16]
+// 10 other_msdu_count[15:0], tcp_ack_msdu_count[31:16]
+// 11 sw_response_reference_ptr[31:0]
+// 12 received_qos_data_tid_bitmap[15:0], received_qos_data_tid_eosp_bitmap[31:16]
+// 13 qosctrl_15_8_tid0[7:0], qosctrl_15_8_tid1[15:8], qosctrl_15_8_tid2[23:16], qosctrl_15_8_tid3[31:24]
+// 14 qosctrl_15_8_tid4[7:0], qosctrl_15_8_tid5[15:8], qosctrl_15_8_tid6[23:16], qosctrl_15_8_tid7[31:24]
+// 15 qosctrl_15_8_tid8[7:0], qosctrl_15_8_tid9[15:8], qosctrl_15_8_tid10[23:16], qosctrl_15_8_tid11[31:24]
+// 16 qosctrl_15_8_tid12[7:0], qosctrl_15_8_tid13[15:8], qosctrl_15_8_tid14[23:16], qosctrl_15_8_tid15[31:24]
+// 17 mpdu_ok_byte_count[24:0], ampdu_delim_ok_count_6_0[31:25]
+// 18 ampdu_delim_err_count[24:0], ampdu_delim_ok_count_13_7[31:25]
+// 19 mpdu_err_byte_count[24:0], ampdu_delim_ok_count_20_14[31:25]
+// 20 non_consecutive_delimiter_err[15:0], reserved_20a[31:16]
+// 21 ht_control_null_field[31:0]
+// 22 sw_response_reference_ptr_ext[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 23
+
+struct rx_ppdu_end_user_stats {
+ struct rx_rxpcu_classification_overview rxpcu_classification_details;
+ uint32_t sta_full_aid : 13, //[12:0]
+ mcs : 4, //[16:13]
+ nss : 3, //[19:17]
+ ofdma_info_valid : 1, //[20]
+ dl_ofdma_ru_start_index : 7, //[27:21]
+ reserved_1a : 4; //[31:28]
+ uint32_t dl_ofdma_ru_width : 7, //[6:0]
+ reserved_2a : 1, //[7]
+ user_receive_quality : 8, //[15:8]
+ mpdu_cnt_fcs_err : 10, //[25:16]
+ wbm2rxdma_buf_source_used : 1, //[26]
+ fw2rxdma_buf_source_used : 1, //[27]
+ sw2rxdma_buf_source_used : 1, //[28]
+ reserved_2b : 3; //[31:29]
+ uint32_t mpdu_cnt_fcs_ok : 9, //[8:0]
+ frame_control_info_valid : 1, //[9]
+ qos_control_info_valid : 1, //[10]
+ ht_control_info_valid : 1, //[11]
+ data_sequence_control_info_valid: 1, //[12]
+ ht_control_info_null_valid : 1, //[13]
+ reserved_3a : 2, //[15:14]
+ rxdma2reo_ring_used : 1, //[16]
+ rxdma2fw_ring_used : 1, //[17]
+ rxdma2sw_ring_used : 1, //[18]
+ rxdma_release_ring_used : 1, //[19]
+ ht_control_field_pkt_type : 4, //[23:20]
+ reserved_3b : 8; //[31:24]
+ uint32_t ast_index : 16, //[15:0]
+ frame_control_field : 16; //[31:16]
+ uint32_t first_data_seq_ctrl : 16, //[15:0]
+ qos_control_field : 16; //[31:16]
+ uint32_t ht_control_field : 32; //[31:0]
+ uint32_t fcs_ok_bitmap_31_0 : 32; //[31:0]
+ uint32_t fcs_ok_bitmap_63_32 : 32; //[31:0]
+ uint32_t udp_msdu_count : 16, //[15:0]
+ tcp_msdu_count : 16; //[31:16]
+ uint32_t other_msdu_count : 16, //[15:0]
+ tcp_ack_msdu_count : 16; //[31:16]
+ uint32_t sw_response_reference_ptr : 32; //[31:0]
+ uint32_t received_qos_data_tid_bitmap : 16, //[15:0]
+ received_qos_data_tid_eosp_bitmap: 16; //[31:16]
+ uint32_t qosctrl_15_8_tid0 : 8, //[7:0]
+ qosctrl_15_8_tid1 : 8, //[15:8]
+ qosctrl_15_8_tid2 : 8, //[23:16]
+ qosctrl_15_8_tid3 : 8; //[31:24]
+ uint32_t qosctrl_15_8_tid4 : 8, //[7:0]
+ qosctrl_15_8_tid5 : 8, //[15:8]
+ qosctrl_15_8_tid6 : 8, //[23:16]
+ qosctrl_15_8_tid7 : 8; //[31:24]
+ uint32_t qosctrl_15_8_tid8 : 8, //[7:0]
+ qosctrl_15_8_tid9 : 8, //[15:8]
+ qosctrl_15_8_tid10 : 8, //[23:16]
+ qosctrl_15_8_tid11 : 8; //[31:24]
+ uint32_t qosctrl_15_8_tid12 : 8, //[7:0]
+ qosctrl_15_8_tid13 : 8, //[15:8]
+ qosctrl_15_8_tid14 : 8, //[23:16]
+ qosctrl_15_8_tid15 : 8; //[31:24]
+ uint32_t mpdu_ok_byte_count : 25, //[24:0]
+ ampdu_delim_ok_count_6_0 : 7; //[31:25]
+ uint32_t ampdu_delim_err_count : 25, //[24:0]
+ ampdu_delim_ok_count_13_7 : 7; //[31:25]
+ uint32_t mpdu_err_byte_count : 25, //[24:0]
+ ampdu_delim_ok_count_20_14 : 7; //[31:25]
+ uint32_t non_consecutive_delimiter_err : 16, //[15:0]
+ reserved_20a : 16; //[31:16]
+ uint32_t ht_control_null_field : 32; //[31:0]
+ uint32_t sw_response_reference_ptr_ext : 32; //[31:0]
+};
+
+/*
+
+struct rx_rxpcu_classification_overview rxpcu_classification_details
+
+ Details related to what RXPCU classification types of
+ MPDUs have been received
+
+sta_full_aid
+
+ Consumer: FW
+
+ Producer: RXPCU
+
+
+
+ The full AID of this station.
+
+
+
+ <legal all>
+
+mcs
+
+ MCS of the received frame
+
+
+
+ For details, refer to MCS_TYPE description
+
+ Note: This is rate in case of 11a/11b
+
+
+
+ <legal all>
+
+nss
+
+ Number of spatial streams.
+
+
+
+ NOTE: RXPCU derives this from the 'Mimo_ss_bitmap'
+
+
+
+ <enum 0 1_spatial_stream>Single spatial stream
+
+ <enum 1 2_spatial_streams>2 spatial streams
+
+ <enum 2 3_spatial_streams>3 spatial streams
+
+ <enum 3 4_spatial_streams>4 spatial streams
+
+ <enum 4 5_spatial_streams>5 spatial streams
+
+ <enum 5 6_spatial_streams>6 spatial streams
+
+ <enum 6 7_spatial_streams>7 spatial streams
+
+ <enum 7 8_spatial_streams>8 spatial streams
+
+ofdma_info_valid
+
+ When set, ofdma RU related info in the following fields
+ is valid
+
+ <legal all>
+
+dl_ofdma_ru_start_index
+
+ Field only valid when Ofdma_info_valid is set
+
+
+
+ RU index number to which User is assigned
+
+ RU numbering is over the entire BW, starting from 0
+
+ <legal 0-73>
+
+reserved_1a
+
+ <legal 0>
+
+dl_ofdma_ru_width
+
+ The size of the RU for this user.
+
+ In units of 1 (26 tone) RU
+
+ <legal 1-74>
+
+reserved_2a
+
+ <legal 0>
+
+user_receive_quality
+
+ DO NOT USE
+
+
+
+ Field not populated by MAC HW
+
+ <legal all>
+
+mpdu_cnt_fcs_err
+
+ The number of MPDUs received from this STA in this PPDU
+ with FCS errors
+
+ <legal all>
+
+wbm2rxdma_buf_source_used
+
+ Field filled in by RXDMA
+
+
+
+ When set, RXDMA has used the wbm2rxdma_buf ring as
+ source for at least one of the frames in this PPDU.
+
+fw2rxdma_buf_source_used
+
+ Field filled in by RXDMA
+
+
+
+ When set, RXDMA has used the fw2rxdma_buf ring as source
+ for at least one of the frames in this PPDU.
+
+sw2rxdma_buf_source_used
+
+ Field filled in by RXDMA
+
+
+
+ When set, RXDMA has used the sw2rxdma_buf ring as source
+ for at least one of the frames in this PPDU.
+
+reserved_2b
+
+ <legal 0>
+
+mpdu_cnt_fcs_ok
+
+ The number of MPDUs received from this STA in this PPDU
+ with correct FCS
+
+ <legal all>
+
+frame_control_info_valid
+
+ When set, the frame_control_info field contains valid
+ information
+
+ <legal all>
+
+qos_control_info_valid
+
+ When set, the QoS_control_info field contains valid
+ information
+
+ <legal all>
+
+ht_control_info_valid
+
+ When set, the HT_control_field contains valid
+ information
+
+ <legal all>
+
+data_sequence_control_info_valid
+
+ When set, the First_data_seq_ctrl field contains valid
+ information
+
+ <legal all>
+
+ht_control_info_null_valid
+
+ When set, the HT_control_NULL_field contains valid
+ information
+
+ <legal all>
+
+reserved_3a
+
+ <legal 0>
+
+rxdma2reo_ring_used
+
+ Field filled in by RXDMA
+
+
+
+ Set when at least one frame during this PPDU got pushed
+ to this ring by RXDMA
+
+rxdma2fw_ring_used
+
+ Field filled in by RXDMA
+
+
+
+ Set when at least one frame during this PPDU got pushed
+ to this ring by RXDMA
+
+rxdma2sw_ring_used
+
+ Field filled in by RXDMA
+
+
+
+ Set when at least one frame during this PPDU got pushed
+ to this ring by RXDMA
+
+rxdma_release_ring_used
+
+ Field filled in by RXDMA
+
+
+
+ Set when at least one frame during this PPDU got pushed
+ to this ring by RXDMA
+
+ht_control_field_pkt_type
+
+ Field only valid when HT_control_info_valid or
+ HT_control_info_NULL_valid is set.
+
+
+
+ Indicates what the PHY receive type was for receiving
+ this frame. Can help determine if the HT_CONTROL field shall
+ be interpreted as HT/VHT or HE.
+
+
+
+ NOTE: later on in the 11ax IEEE spec a bit within the HT
+ control field was introduced that explicitly indicated how
+ to interpret the HT control field.... As HT, VHT, or HE.
+
+
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+
+reserved_3b
+
+ <legal 0>
+
+ast_index
+
+ This field indicates the index of the AST entry
+ corresponding to this MPDU. It is provided by the GSE module
+ instantiated in RXPCU.
+
+ A value of 0xFFFF indicates an invalid AST index,
+ meaning that No AST entry was found or NO AST search was
+ performed
+
+ <legal all>
+
+frame_control_field
+
+ Field only valid when Frame_control_info_valid is set.
+
+
+
+ Last successfully received Frame_control field of data
+ frame (excluding Data NULL/ QoS Null) for this user
+
+ Mainly used to track the PM state of the transmitted
+ device
+
+
+
+ NOTE: only data frame info is needed, as control and
+ management frames are already routed to the FW.
+
+ <legal all>
+
+first_data_seq_ctrl
+
+ Field only valid when Data_sequence_control_info_valid
+ is set.
+
+
+
+ Sequence control field of the first data frame
+ (excluding Data NULL or QoS Data null) received for this
+ user with correct FCS
+
+
+
+ NOTE: only data frame info is needed, as control and
+ management frames are already routed to the FW.
+
+ <legal all>
+
+qos_control_field
+
+ Field only valid when QoS_control_info_valid is set.
+
+
+
+ Last successfully received QoS_control field of data
+ frame (excluding Data NULL/ QoS Null) for this user
+
+
+
+ Note that in case of multi TID, this field can only
+ reflect the last properly received MPDU, and thus can not
+ indicate all potentially different TIDs that had been
+ received earlier.
+
+
+
+ There are however per TID fields, that will contain
+ among other things all buffer status info: See
+
+ QoSCtrl_15_8_tid???
+
+ <legal all>
+
+ht_control_field
+
+ Field only valid when HT_control_info_valid is set.
+
+
+
+ Last successfully received
+ HT_CONTROL/VHT_CONTROL/HE_CONTROL field of data frames,
+ excluding QoS Null frames for this user.
+
+
+
+ NOTE: HT control fields from QoS Null frames are
+ captured in field HT_control_NULL_field
+
+ <legal all>
+
+fcs_ok_bitmap_31_0
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+
+fcs_ok_bitmap_63_32
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+
+
+ NOTE: for users 0, 1, 2 and 3, additional bitmap info
+ (up to 256 bitmap window) is provided in
+ RX_PPDU_END_USER_STATS_EXT TLV
+
+ <legal all>
+
+udp_msdu_count
+
+ Field filled in by RX OLE
+
+ Set to 0 by RXPCU
+
+
+
+ The number of MSDUs that are part of MPDUs without FCS
+ error, that contain UDP frames.
+
+ <legal all>
+
+tcp_msdu_count
+
+ Field filled in by RX OLE
+
+ Set to 0 by RXPCU
+
+
+
+ The number of MSDUs that are part of MPDUs without FCS
+ error, that contain TCP frames.
+
+
+
+ (Note: This does NOT include TCP-ACK)
+
+ <legal all>
+
+other_msdu_count
+
+ Field filled in by RX OLE
+
+ Set to 0 by RXPCU
+
+
+
+ The number of MSDUs that are part of MPDUs without FCS
+ error, that contain neither UDP or TCP frames.
+
+
+
+ Includes Management and control frames.
+
+
+
+ <legal all>
+
+tcp_ack_msdu_count
+
+ Field filled in by RX OLE
+
+ Set to 0 by RXPCU
+
+
+
+ The number of MSDUs that are part of MPDUs without FCS
+ error, that contain TCP ack frames.
+
+ <legal all>
+
+sw_response_reference_ptr
+
+ Pointer that SW uses to refer back to an expected
+ response reception. Used for Rate adaptation purposes.
+
+ When a reception occurs that is not tied to an expected
+ response, this field is set to 0x0.
+
+
+
+ Note: further on in this TLV there is also the field:
+ Sw_response_reference_ptr_ext.
+
+ <legal all>
+
+received_qos_data_tid_bitmap
+
+ Whenever a frame is received that contains a QoS control
+ field (that includes QoS Data and/or QoS Null), the bit in
+ this field that corresponds to the received TID shall be
+ set.
+
+ ...Bitmap[0] = TID0
+
+ ...Bitmap[1] = TID1
+
+ Etc.
+
+ <legal all>
+
+received_qos_data_tid_eosp_bitmap
+
+ Field initialized to 0
+
+ For every QoS Data frame that is correctly received, the
+ EOSP bit of that frame is copied over into the corresponding
+ TID related field.
+
+ Note that this implies that the bits here represent the
+ EOSP bit status for each TID of the last MPDU received for
+ that TID.
+
+
+
+ received TID shall be set.
+
+ ...eosp_bitmap[0] = eosp of TID0
+
+ ...eosp_bitmap[1] = eosp of TID1
+
+ Etc.
+
+ <legal all>
+
+qosctrl_15_8_tid0
+
+ Field only valid when Received_qos_data_tid_bitmap[0] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 0
+
+qosctrl_15_8_tid1
+
+ Field only valid when Received_qos_data_tid_bitmap[1] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 1
+
+qosctrl_15_8_tid2
+
+ Field only valid when Received_qos_data_tid_bitmap[2] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 2
+
+qosctrl_15_8_tid3
+
+ Field only valid when Received_qos_data_tid_bitmap[3] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 3
+
+qosctrl_15_8_tid4
+
+ Field only valid when Received_qos_data_tid_bitmap[4] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 4
+
+qosctrl_15_8_tid5
+
+ Field only valid when Received_qos_data_tid_bitmap[5] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 5
+
+qosctrl_15_8_tid6
+
+ Field only valid when Received_qos_data_tid_bitmap[6] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 6
+
+qosctrl_15_8_tid7
+
+ Field only valid when Received_qos_data_tid_bitmap[7] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 7
+
+qosctrl_15_8_tid8
+
+ Field only valid when Received_qos_data_tid_bitmap[8] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 8
+
+qosctrl_15_8_tid9
+
+ Field only valid when Received_qos_data_tid_bitmap[9] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 9
+
+qosctrl_15_8_tid10
+
+ Field only valid when Received_qos_data_tid_bitmap[10]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 10
+
+qosctrl_15_8_tid11
+
+ Field only valid when Received_qos_data_tid_bitmap[11]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 11
+
+qosctrl_15_8_tid12
+
+ Field only valid when Received_qos_data_tid_bitmap[12]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 12
+
+qosctrl_15_8_tid13
+
+ Field only valid when Received_qos_data_tid_bitmap[13]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 13
+
+qosctrl_15_8_tid14
+
+ Field only valid when Received_qos_data_tid_bitmap[14]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 14
+
+qosctrl_15_8_tid15
+
+ Field only valid when Received_qos_data_tid_bitmap[15]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 15
+
+mpdu_ok_byte_count
+
+ The number of bytes received within an MPDU for this
+ user with correct FCS. This includes the FCS field
+
+
+
+ NOTE:
+
+ The sum of the four fields.....
+
+ Mpdu_ok_byte_count +
+
+ mpdu_err_byte_count +
+
+
+ .....is the total number of bytes that were received for
+ this user from the PHY.
+
+
+
+ <legal all>
+
+ampdu_delim_ok_count_6_0
+
+ Number of AMPDU delimiter received with correct
+ structure
+
+ LSB 7 bits from this counter
+
+
+
+ Note that this is a delimiter count and not byte count.
+ To get to the number of bytes occupied by these delimiters,
+ multiply this number by 4
+
+
+
+ <legal all>
+
+ampdu_delim_err_count
+
+ The number of MPDU delimiter errors counted for this
+ user.
+
+
+
+ Note that this is a delimiter count and not byte count.
+ To get to the number of bytes occupied by these delimiters,
+ multiply this number by 4
+
+ <legal all>
+
+ampdu_delim_ok_count_13_7
+
+ Number of AMPDU delimiters received with correct
+ structure
+
+ Bits 13-7 from this counter
+
+
+
+ Note that this is a delimiter count and not byte count.
+ To get to the number of bytes occupied by these delimiters,
+ multiply this number by 4
+
+ <legal all>
+
+mpdu_err_byte_count
+
+ The number of bytes belonging to MPDUs with an FCS
+ error. This includes the FCS field.
+
+
+
+ <legal all>
+
+ampdu_delim_ok_count_20_14
+
+ Number of AMPDU delimiters received with correct
+ structure
+
+ Bits 20-14 from this counter
+
+
+
+ Note that this is a delimiter count and not byte count.
+ To get to the number of bytes occupied by these delimiters,
+ multiply this number by 4
+
+
+
+ <legal all>
+
+non_consecutive_delimiter_err
+
+ The number of times an MPDU delimiter error is detected
+ that is not immediately preceded by another MPDU delimiter
+ also with FCS error.
+
+
+
+ The counter saturates at 0xFFFF
+
+
+
+ <legal all>
+
+reserved_20a
+
+ <legal 0>
+
+ht_control_null_field
+
+
+
+
+ Last successfully received
+ HT_CONTROL/VHT_CONTROL/HE_CONTROL field from QoS Null frame
+ for this user.
+
+ <legal all>
+
+sw_response_reference_ptr_ext
+
+ Extended Pointer info that SW uses to refer back to an
+ expected response transmission. Used for Rate adaptation
+ purposes.
+
+ When a reception occurs that is not tied to an expected
+ response, this field is set to 0x0.
+
+
+
+ Note: earlier on in this TLV there is also the field:
+ Sw_response_reference_ptr.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct rx_rxpcu_classification_overview rxpcu_classification_details */
+
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS
+
+ When set, at least one Filter Pass MPDU has been
+ received. FCS might or might not have been passing.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK
+
+ When set, at least one Filter Pass MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS
+
+ When set, at least one Monitor Direct MPDU has been
+ received. FCS might or might not have been passing
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK
+
+ When set, at least one Monitor Direct MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS
+
+ When set, at least one Monitor Direct MPDU has been
+ received. FCS might or might not have been passing.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK
+
+ When set, at least one Monitor Direct MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED
+
+ When set, PPDU reception was aborted by the PHY
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0
+
+ <legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80
+
+/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description RX_PPDU_END_USER_STATS_1_STA_FULL_AID
+
+ Consumer: FW
+
+ Producer: RXPCU
+
+
+
+ The full AID of this station.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB 0
+#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK 0x00001fff
+
+/* Description RX_PPDU_END_USER_STATS_1_MCS
+
+ MCS of the received frame
+
+
+
+ For details, refer to MCS_TYPE description
+
+ Note: This is rate in case of 11a/11b
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_1_MCS_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_MCS_LSB 13
+#define RX_PPDU_END_USER_STATS_1_MCS_MASK 0x0001e000
+
+/* Description RX_PPDU_END_USER_STATS_1_NSS
+
+ Number of spatial streams.
+
+
+
+ NOTE: RXPCU derives this from the 'Mimo_ss_bitmap'
+
+
+
+ <enum 0 1_spatial_stream>Single spatial stream
+
+ <enum 1 2_spatial_streams>2 spatial streams
+
+ <enum 2 3_spatial_streams>3 spatial streams
+
+ <enum 3 4_spatial_streams>4 spatial streams
+
+ <enum 4 5_spatial_streams>5 spatial streams
+
+ <enum 5 6_spatial_streams>6 spatial streams
+
+ <enum 6 7_spatial_streams>7 spatial streams
+
+ <enum 7 8_spatial_streams>8 spatial streams
+*/
+#define RX_PPDU_END_USER_STATS_1_NSS_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_NSS_LSB 17
+#define RX_PPDU_END_USER_STATS_1_NSS_MASK 0x000e0000
+
+/* Description RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID
+
+ When set, ofdma RU related info in the following fields
+ is valid
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_LSB 20
+#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_MASK 0x00100000
+
+/* Description RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX
+
+ Field only valid when Ofdma_info_valid is set
+
+
+
+ RU index number to which User is assigned
+
+ RU numbering is over the entire BW, starting from 0
+
+ <legal 0-73>
+*/
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_LSB 21
+#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_MASK 0x0fe00000
+
+/* Description RX_PPDU_END_USER_STATS_1_RESERVED_1A
+
+ <legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB 28
+#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK 0xf0000000
+
+/* Description RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH
+
+ The size of the RU for this user.
+
+ In units of 1 (26 tone) RU
+
+ <legal 1-74>
+*/
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_LSB 0
+#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_MASK 0x0000007f
+
+/* Description RX_PPDU_END_USER_STATS_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB 7
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK 0x00000080
+
+/* Description RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY
+
+ DO NOT USE
+
+
+
+ Field not populated by MAC HW
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB 8
+#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK 0x0000ff00
+
+/* Description RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR
+
+ The number of MPDUs received from this STA in this PPDU
+ with FCS errors
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB 16
+#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK 0x03ff0000
+
+/* Description RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED
+
+ Field filled in by RXDMA
+
+
+
+ When set, RXDMA has used the wbm2rxdma_buf ring as
+ source for at least one of the frames in this PPDU.
+*/
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB 26
+#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK 0x04000000
+
+/* Description RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED
+
+ Field filled in by RXDMA
+
+
+
+ When set, RXDMA has used the fw2rxdma_buf ring as source
+ for at least one of the frames in this PPDU.
+*/
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB 27
+#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK 0x08000000
+
+/* Description RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED
+
+ Field filled in by RXDMA
+
+
+
+ When set, RXDMA has used the sw2rxdma_buf ring as source
+ for at least one of the frames in this PPDU.
+*/
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB 28
+#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK 0x10000000
+
+/* Description RX_PPDU_END_USER_STATS_2_RESERVED_2B
+
+ <legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB 29
+#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK 0xe0000000
+
+/* Description RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK
+
+ The number of MPDUs received from this STA in this PPDU
+ with correct FCS
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB 0
+#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK 0x000001ff
+
+/* Description RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID
+
+ When set, the frame_control_info field contains valid
+ information
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB 9
+#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK 0x00000200
+
+/* Description RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID
+
+ When set, the QoS_control_info field contains valid
+ information
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB 10
+#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK 0x00000400
+
+/* Description RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID
+
+ When set, the HT_control_field contains valid
+ information
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB 11
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK 0x00000800
+
+/* Description RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID
+
+ When set, the First_data_seq_ctrl field contains valid
+ information
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12
+#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000
+
+/* Description RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID
+
+ When set, the HT_control_NULL_field contains valid
+ information
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_LSB 13
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_MASK 0x00002000
+
+/* Description RX_PPDU_END_USER_STATS_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB 14
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK 0x0000c000
+
+/* Description RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED
+
+ Field filled in by RXDMA
+
+
+
+ Set when at least one frame during this PPDU got pushed
+ to this ring by RXDMA
+*/
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB 16
+#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK 0x00010000
+
+/* Description RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED
+
+ Field filled in by RXDMA
+
+
+
+ Set when at least one frame during this PPDU got pushed
+ to this ring by RXDMA
+*/
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB 17
+#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK 0x00020000
+
+/* Description RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED
+
+ Field filled in by RXDMA
+
+
+
+ Set when at least one frame during this PPDU got pushed
+ to this ring by RXDMA
+*/
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB 18
+#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK 0x00040000
+
+/* Description RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED
+
+ Field filled in by RXDMA
+
+
+
+ Set when at least one frame during this PPDU got pushed
+ to this ring by RXDMA
+*/
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB 19
+#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK 0x00080000
+
+/* Description RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE
+
+ Field only valid when HT_control_info_valid or
+ HT_control_info_NULL_valid is set.
+
+
+
+ Indicates what the PHY receive type was for receiving
+ this frame. Can help determine if the HT_CONTROL field shall
+ be interpreted as HT/VHT or HE.
+
+
+
+ NOTE: later on in the 11ax IEEE spec a bit within the HT
+ control field was introduced that explicitly indicated how
+ to interpret the HT control field.... As HT, VHT, or HE.
+
+
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+*/
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB 20
+#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x00f00000
+
+/* Description RX_PPDU_END_USER_STATS_3_RESERVED_3B
+
+ <legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB 24
+#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK 0xff000000
+
+/* Description RX_PPDU_END_USER_STATS_4_AST_INDEX
+
+ This field indicates the index of the AST entry
+ corresponding to this MPDU. It is provided by the GSE module
+ instantiated in RXPCU.
+
+ A value of 0xFFFF indicates an invalid AST index,
+ meaning that No AST entry was found or NO AST search was
+ performed
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB 0
+#define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK 0x0000ffff
+
+/* Description RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD
+
+ Field only valid when Frame_control_info_valid is set.
+
+
+
+ Last successfully received Frame_control field of data
+ frame (excluding Data NULL/ QoS Null) for this user
+
+ Mainly used to track the PM state of the transmitted
+ device
+
+
+
+ NOTE: only data frame info is needed, as control and
+ management frames are already routed to the FW.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB 16
+#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK 0xffff0000
+
+/* Description RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL
+
+ Field only valid when Data_sequence_control_info_valid
+ is set.
+
+
+
+ Sequence control field of the first data frame
+ (excluding Data NULL or QoS Data null) received for this
+ user with correct FCS
+
+
+
+ NOTE: only data frame info is needed, as control and
+ management frames are already routed to the FW.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB 0
+#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff
+
+/* Description RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD
+
+ Field only valid when QoS_control_info_valid is set.
+
+
+
+ Last successfully received QoS_control field of data
+ frame (excluding Data NULL/ QoS Null) for this user
+
+
+
+ Note that in case of multi TID, this field can only
+ reflect the last properly received MPDU, and thus can not
+ indicate all potentially different TIDs that had been
+ received earlier.
+
+
+
+ There are however per TID fields, that will contain
+ among other things all buffer status info: See
+
+ QoSCtrl_15_8_tid???
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB 16
+#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK 0xffff0000
+
+/* Description RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD
+
+ Field only valid when HT_control_info_valid is set.
+
+
+
+ Last successfully received
+ HT_CONTROL/VHT_CONTROL/HE_CONTROL field of data frames,
+ excluding QoS Null frames for this user.
+
+
+
+ NOTE: HT control fields from QoS Null frames are
+ captured in field HT_control_NULL_field
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET 0x00000018
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB 0
+#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB 0
+#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+
+
+ NOTE: for users 0, 1, 2 and 3, additional bitmap info
+ (up to 256 bitmap window) is provided in
+ RX_PPDU_END_USER_STATS_EXT TLV
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET 0x00000020
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB 0
+#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT
+
+ Field filled in by RX OLE
+
+ Set to 0 by RXPCU
+
+
+
+ The number of MSDUs that are part of MPDUs without FCS
+ error, that contain UDP frames.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET 0x00000024
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK 0x0000ffff
+
+/* Description RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT
+
+ Field filled in by RX OLE
+
+ Set to 0 by RXPCU
+
+
+
+ The number of MSDUs that are part of MPDUs without FCS
+ error, that contain TCP frames.
+
+
+
+ (Note: This does NOT include TCP-ACK)
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET 0x00000024
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK 0xffff0000
+
+/* Description RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT
+
+ Field filled in by RX OLE
+
+ Set to 0 by RXPCU
+
+
+
+ The number of MSDUs that are part of MPDUs without FCS
+ error, that contain neither UDP or TCP frames.
+
+
+
+ Includes Management and control frames.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET 0x00000028
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK 0x0000ffff
+
+/* Description RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT
+
+ Field filled in by RX OLE
+
+ Set to 0 by RXPCU
+
+
+
+ The number of MSDUs that are part of MPDUs without FCS
+ error, that contain TCP ack frames.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB 16
+#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK 0xffff0000
+
+/* Description RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR
+
+ Pointer that SW uses to refer back to an expected
+ response reception. Used for Rate adaptation purposes.
+
+ When a reception occurs that is not tied to an expected
+ response, this field is set to 0x0.
+
+
+
+ Note: further on in this TLV there is also the field:
+ Sw_response_reference_ptr_ext.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB 0
+#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP
+
+ Whenever a frame is received that contains a QoS control
+ field (that includes QoS Data and/or QoS Null), the bit in
+ this field that corresponds to the received TID shall be
+ set.
+
+ ...Bitmap[0] = TID0
+
+ ...Bitmap[1] = TID1
+
+ Etc.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff
+
+/* Description RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP
+
+ Field initialized to 0
+
+ For every QoS Data frame that is correctly received, the
+ EOSP bit of that frame is copied over into the corresponding
+ TID related field.
+
+ Note that this implies that the bits here represent the
+ EOSP bit status for each TID of the last MPDU received for
+ that TID.
+
+
+
+ received TID shall be set.
+
+ ...eosp_bitmap[0] = eosp of TID0
+
+ ...eosp_bitmap[1] = eosp of TID1
+
+ Etc.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16
+#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000
+
+/* Description RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0
+
+ Field only valid when Received_qos_data_tid_bitmap[0] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 0
+*/
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB 0
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK 0x000000ff
+
+/* Description RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1
+
+ Field only valid when Received_qos_data_tid_bitmap[1] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 1
+*/
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB 8
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK 0x0000ff00
+
+/* Description RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2
+
+ Field only valid when Received_qos_data_tid_bitmap[2] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 2
+*/
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB 16
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK 0x00ff0000
+
+/* Description RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3
+
+ Field only valid when Received_qos_data_tid_bitmap[3] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 3
+*/
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET 0x00000034
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB 24
+#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK 0xff000000
+
+/* Description RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4
+
+ Field only valid when Received_qos_data_tid_bitmap[4] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 4
+*/
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB 0
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK 0x000000ff
+
+/* Description RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5
+
+ Field only valid when Received_qos_data_tid_bitmap[5] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 5
+*/
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB 8
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK 0x0000ff00
+
+/* Description RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6
+
+ Field only valid when Received_qos_data_tid_bitmap[6] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 6
+*/
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB 16
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK 0x00ff0000
+
+/* Description RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7
+
+ Field only valid when Received_qos_data_tid_bitmap[7] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 7
+*/
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET 0x00000038
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB 24
+#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK 0xff000000
+
+/* Description RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8
+
+ Field only valid when Received_qos_data_tid_bitmap[8] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 8
+*/
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB 0
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK 0x000000ff
+
+/* Description RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9
+
+ Field only valid when Received_qos_data_tid_bitmap[9] is
+ set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 9
+*/
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB 8
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK 0x0000ff00
+
+/* Description RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10
+
+ Field only valid when Received_qos_data_tid_bitmap[10]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 10
+*/
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB 16
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK 0x00ff0000
+
+/* Description RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11
+
+ Field only valid when Received_qos_data_tid_bitmap[11]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 11
+*/
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET 0x0000003c
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB 24
+#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK 0xff000000
+
+/* Description RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12
+
+ Field only valid when Received_qos_data_tid_bitmap[12]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 12
+*/
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB 0
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK 0x000000ff
+
+/* Description RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13
+
+ Field only valid when Received_qos_data_tid_bitmap[13]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 13
+*/
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB 8
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK 0x0000ff00
+
+/* Description RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14
+
+ Field only valid when Received_qos_data_tid_bitmap[14]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 14
+*/
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB 16
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK 0x00ff0000
+
+/* Description RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15
+
+ Field only valid when Received_qos_data_tid_bitmap[15]
+ is set
+
+
+
+ QoS control field bits 15-8 of the last properly
+ received MPDU with a QoS control field embedded, with TID
+ == 15
+*/
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET 0x00000040
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB 24
+#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK 0xff000000
+
+/* Description RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT
+
+ The number of bytes received within an MPDU for this
+ user with correct FCS. This includes the FCS field
+
+
+
+ NOTE:
+
+ The sum of the four fields.....
+
+ Mpdu_ok_byte_count +
+
+ mpdu_err_byte_count +
+
+
+ .....is the total number of bytes that were received for
+ this user from the PHY.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff
+
+/* Description RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0
+
+ Number of AMPDU delimiter received with correct
+ structure
+
+ LSB 7 bits from this counter
+
+
+
+ Note that this is a delimiter count and not byte count.
+ To get to the number of bytes occupied by these delimiters,
+ multiply this number by 4
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_LSB 25
+#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000
+
+/* Description RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT
+
+ The number of MPDU delimiter errors counted for this
+ user.
+
+
+
+ Note that this is a delimiter count and not byte count.
+ To get to the number of bytes occupied by these delimiters,
+ multiply this number by 4
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff
+
+/* Description RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7
+
+ Number of AMPDU delimiters received with correct
+ structure
+
+ Bits 13-7 from this counter
+
+
+
+ Note that this is a delimiter count and not byte count.
+ To get to the number of bytes occupied by these delimiters,
+ multiply this number by 4
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_LSB 25
+#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000
+
+/* Description RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT
+
+ The number of bytes belonging to MPDUs with an FCS
+ error. This includes the FCS field.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_LSB 0
+#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff
+
+/* Description RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14
+
+ Number of AMPDU delimiters received with correct
+ structure
+
+ Bits 20-14 from this counter
+
+
+
+ Note that this is a delimiter count and not byte count.
+ To get to the number of bytes occupied by these delimiters,
+ multiply this number by 4
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_LSB 25
+#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000
+
+/* Description RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR
+
+ The number of times an MPDU delimiter error is detected
+ that is not immediately preceded by another MPDU delimiter
+ also with FCS error.
+
+
+
+ The counter saturates at 0xFFFF
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0
+#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff
+
+/* Description RX_PPDU_END_USER_STATS_20_RESERVED_20A
+
+ <legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_OFFSET 0x00000050
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_LSB 16
+#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_MASK 0xffff0000
+
+/* Description RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD
+
+
+
+
+ Last successfully received
+ HT_CONTROL/VHT_CONTROL/HE_CONTROL field from QoS Null frame
+ for this user.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_LSB 0
+#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT
+
+ Extended Pointer info that SW uses to refer back to an
+ expected response transmission. Used for Rate adaptation
+ purposes.
+
+ When a reception occurs that is not tied to an expected
+ response, this field is set to 0x0.
+
+
+
+ Note: earlier on in this TLV there is also the field:
+ Sw_response_reference_ptr.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0
+#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff
+
+
+#endif // _RX_PPDU_END_USER_STATS_H_
diff --git a/hw/qca5018/rx_ppdu_end_user_stats_ext.h b/hw/qca5018/rx_ppdu_end_user_stats_ext.h
new file mode 100644
index 0000000..2c6d073
--- /dev/null
+++ b/hw/qca5018/rx_ppdu_end_user_stats_ext.h
@@ -0,0 +1,353 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_PPDU_END_USER_STATS_EXT_H_
+#define _RX_PPDU_END_USER_STATS_EXT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_rxpcu_classification_overview.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct rx_rxpcu_classification_overview rxpcu_classification_details;
+// 1 fcs_ok_bitmap_95_64[31:0]
+// 2 fcs_ok_bitmap_127_96[31:0]
+// 3 fcs_ok_bitmap_159_128[31:0]
+// 4 fcs_ok_bitmap_191_160[31:0]
+// 5 fcs_ok_bitmap_223_192[31:0]
+// 6 fcs_ok_bitmap_255_224[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7
+
+struct rx_ppdu_end_user_stats_ext {
+ struct rx_rxpcu_classification_overview rxpcu_classification_details;
+ uint32_t fcs_ok_bitmap_95_64 : 32; //[31:0]
+ uint32_t fcs_ok_bitmap_127_96 : 32; //[31:0]
+ uint32_t fcs_ok_bitmap_159_128 : 32; //[31:0]
+ uint32_t fcs_ok_bitmap_191_160 : 32; //[31:0]
+ uint32_t fcs_ok_bitmap_223_192 : 32; //[31:0]
+ uint32_t fcs_ok_bitmap_255_224 : 32; //[31:0]
+};
+
+/*
+
+struct rx_rxpcu_classification_overview rxpcu_classification_details
+
+ Details related to what RXPCU classification types of
+ MPDUs have been received
+
+fcs_ok_bitmap_95_64
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+
+fcs_ok_bitmap_127_96
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+
+fcs_ok_bitmap_159_128
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+
+fcs_ok_bitmap_191_160
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+
+fcs_ok_bitmap_223_192
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+
+fcs_ok_bitmap_255_224
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct rx_rxpcu_classification_overview rxpcu_classification_details */
+
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS
+
+ When set, at least one Filter Pass MPDU has been
+ received. FCS might or might not have been passing.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK
+
+ When set, at least one Filter Pass MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS
+
+ When set, at least one Monitor Direct MPDU has been
+ received. FCS might or might not have been passing
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK
+
+ When set, at least one Monitor Direct MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS
+
+ When set, at least one Monitor Direct MPDU has been
+ received. FCS might or might not have been passing.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK
+
+ When set, at least one Monitor Direct MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED
+
+ When set, PPDU reception was aborted by the PHY
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0
+
+ <legal 0>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80
+
+/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16
+#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000
+
+/* Description RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET 0x00000004
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET 0x00000008
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET 0x00000010
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET 0x00000014
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK 0xffffffff
+
+/* Description RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224
+
+ Bitmap indicates in order of received MPDUs, which MPDUs
+ had an passing FCS or had an error.
+
+ 1: FCS OK
+
+ 0: FCS error
+
+ <legal all>
+*/
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET 0x00000018
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB 0
+#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK 0xffffffff
+
+
+#endif // _RX_PPDU_END_USER_STATS_EXT_H_
diff --git a/hw/qca5018/rx_ppdu_start.h b/hw/qca5018/rx_ppdu_start.h
new file mode 100644
index 0000000..3f8ea27
--- /dev/null
+++ b/hw/qca5018/rx_ppdu_start.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_PPDU_START_H_
+#define _RX_PPDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 phy_ppdu_id[15:0], reserved_15[31:16]
+// 1 sw_phy_meta_data[31:0]
+// 2 ppdu_start_timestamp[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_PPDU_START 3
+
+struct rx_ppdu_start {
+ uint32_t phy_ppdu_id : 16, //[15:0]
+ reserved_15 : 16; //[31:16]
+ uint32_t sw_phy_meta_data : 32; //[31:0]
+ uint32_t ppdu_start_timestamp : 32; //[31:0]
+};
+
+/*
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+
+reserved_15
+
+ Reserved
+
+ <legal 0>
+
+sw_phy_meta_data
+
+ SW programmed Meta data provided by the PHY.
+
+
+
+ Can be used for SW to indicate the channel the device is
+ on.
+
+ppdu_start_timestamp
+
+ Timestamp that indicates when the PPDU that contained
+ this MPDU started on the medium.
+
+
+
+ The timestamp is captured by the PHY and given to the
+ MAC in PHYRX_RSSI_LEGACY.ppdu_start_timestamp
+
+ <legal all>
+*/
+
+
+/* Description RX_PPDU_START_0_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_START_0_PHY_PPDU_ID_LSB 0
+#define RX_PPDU_START_0_PHY_PPDU_ID_MASK 0x0000ffff
+
+/* Description RX_PPDU_START_0_RESERVED_15
+
+ Reserved
+
+ <legal 0>
+*/
+#define RX_PPDU_START_0_RESERVED_15_OFFSET 0x00000000
+#define RX_PPDU_START_0_RESERVED_15_LSB 16
+#define RX_PPDU_START_0_RESERVED_15_MASK 0xffff0000
+
+/* Description RX_PPDU_START_1_SW_PHY_META_DATA
+
+ SW programmed Meta data provided by the PHY.
+
+
+
+ Can be used for SW to indicate the channel the device is
+ on.
+*/
+#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET 0x00000004
+#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB 0
+#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK 0xffffffff
+
+/* Description RX_PPDU_START_2_PPDU_START_TIMESTAMP
+
+ Timestamp that indicates when the PPDU that contained
+ this MPDU started on the medium.
+
+
+
+ The timestamp is captured by the PHY and given to the
+ MAC in PHYRX_RSSI_LEGACY.ppdu_start_timestamp
+
+ <legal all>
+*/
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB 0
+#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK 0xffffffff
+
+
+#endif // _RX_PPDU_START_H_
diff --git a/hw/qca5018/rx_ppdu_start_user_info.h b/hw/qca5018/rx_ppdu_start_user_info.h
new file mode 100644
index 0000000..a92db96
--- /dev/null
+++ b/hw/qca5018/rx_ppdu_start_user_info.h
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_PPDU_START_USER_INFO_H_
+#define _RX_PPDU_START_USER_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "receive_user_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-2 struct receive_user_info receive_user_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 3
+
+struct rx_ppdu_start_user_info {
+ struct receive_user_info receive_user_info_details;
+};
+
+/*
+
+struct receive_user_info receive_user_info_details
+
+ Overview of receive parameters that the MAC needs to
+ prepend to every received MSDU/MPDU.
+*/
+
+
+ /* EXTERNAL REFERENCE : struct receive_user_info receive_user_info_details */
+
+
+/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
+
+/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI
+
+ RSSI for this user
+
+ Frequency domain RSSI measurement for this user. Based
+ on the channel estimate.
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000
+
+/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE
+
+ Packet type:
+
+
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+*/
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000
+
+/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC
+
+ When set, use STBC transmission rates
+*/
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000
+
+/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE
+
+ Indicates what type of reception this is.
+
+ <enum 0 reception_type_SU > Basic SU reception (not
+ part of OFDMA or MU-MIMO)
+
+ <enum 1 reception_type_MU_MIMO > This is related to
+ DL type of reception
+
+ <enum 2 reception_type_MU_OFDMA > This is related
+ to DL type of reception
+
+ <enum 3 reception_type_MU_OFDMA_MIMO > This is
+ related to DL type of reception
+
+ <enum 4 reception_type_UL_MU_MIMO > This is related
+ to UL type of reception
+
+ <enum 5 reception_type_UL_MU_OFDMA > This is
+ related to UL type of reception
+
+ <enum 6 reception_type_UL_MU_OFDMA_MIMO > This is
+ related to UL type of reception
+
+
+
+ <legal 0-6>
+*/
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29
+#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000
+
+/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS
+
+ For details, refer to MCS_TYPE description
+
+ <legal all>
+*/
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f
+
+/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI
+
+ Field only valid when pkt type is HT, VHT or HE.
+
+
+
+ <enum 0 gi_0_8_us > Legacy normal GI. Can also be
+ used for HE
+
+ <enum 1 gi_0_4_us > Legacy short GI. Can also be
+ used for HE
+
+ <enum 2 gi_1_6_us > HE related GI
+
+ <enum 3 gi_3_2_us > HE related GI
+
+ <legal 0 - 3>
+*/
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030
+
+/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH
+
+ Full receive Bandwidth
+
+
+
+ <enum 0 full_rx_bw_20_mhz>
+
+ <enum 1 full_rx_bw_40_mhz>
+
+ <enum 2 full_rx_bw_80_mhz>
+
+ <enum 3 full_rx_bw_160_mhz>
+
+
+
+ <legal 0-3>
+*/
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0
+
+/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP
+
+ Bitmap, with each bit indicating if the related spatial
+ stream is used for this STA
+
+ LSB related to SS 0
+
+
+
+ 0: spatial stream not used for this reception
+
+ 1: spatial stream used for this reception
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00
+
+/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION
+
+ Field only valid in case of OFDMA type receptions (DL
+ and UL)
+
+
+
+ Indicates the RU number associated with this user.
+
+
+
+ In case of reception where the transmission was DL MU
+ OFDMA, this field provides the RU pattern. Note that fields
+ ofdma_user_index and ofdma_content_channel are needed to
+ determine which RU (within a 40 MHz channel) was actually
+ assigned to this user, but this does not give info on which
+ 40 MHz channel was assigned to this user. Please refer
+ DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for
+ this user.
+
+
+
+ In case of reception where the transmission was UL MU
+ OFDMA, PHY is recommended to insert the RU start index in
+ this field. Note that PHY may insert the RU width in
+ Reserved_2a[6:0].
+
+ <legal all>
+*/
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000
+
+/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX
+
+ Field only valid in the of DL MU OFDMA reception
+
+
+
+ The user number within the RU_allocation.
+
+
+
+ This is needed for SW to determine the exact RU position
+ within the reception.
+
+ <legal all>
+*/
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000
+
+/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL
+
+ Field only valid in the of DL MU OFDMA/MIMO reception
+
+
+
+ In case of DL MU reception, this field indicates the
+ content channel number where PHY found the RU information
+ for this user
+
+
+
+ This is needed for SW to determine the exact RU position
+ within the reception.
+
+
+
+ <enum 0 content_channel_1>
+
+ <enum 1 content_channel_2>
+
+
+
+ <legal all>
+*/
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31
+#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000
+
+/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC
+
+ When set, use LDPC transmission rates were used.
+
+ <legal all>
+*/
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001
+
+/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH
+
+ In case of UL OFDMA reception, PHY is recommended to
+ insert the RU width
+
+ In Hastings80: was using Reserved_2a[6:0].
+
+ <legal 1 - 74>
+*/
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe
+
+/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A
+
+ <legal 0>
+*/
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8
+#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00
+
+
+#endif // _RX_PPDU_START_USER_INFO_H_
diff --git a/hw/qca5018/rx_reo_queue.h b/hw/qca5018/rx_reo_queue.h
new file mode 100644
index 0000000..1835cee
--- /dev/null
+++ b/hw/qca5018/rx_reo_queue.h
@@ -0,0 +1,1749 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_REO_QUEUE_H_
+#define _RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_descriptor_header descriptor_header;
+// 1 receive_queue_number[15:0], reserved_1b[31:16]
+// 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26]
+// 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31]
+// 4 pn_31_0[31:0]
+// 5 pn_63_32[31:0]
+// 6 pn_95_64[31:0]
+// 7 pn_127_96[31:0]
+// 8 last_rx_enqueue_timestamp[31:0]
+// 9 last_rx_dequeue_timestamp[31:0]
+// 10 ptr_to_next_aging_queue_31_0[31:0]
+// 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8]
+// 12 ptr_to_previous_aging_queue_31_0[31:0]
+// 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8]
+// 14 rx_bitmap_31_0[31:0]
+// 15 rx_bitmap_63_32[31:0]
+// 16 rx_bitmap_95_64[31:0]
+// 17 rx_bitmap_127_96[31:0]
+// 18 rx_bitmap_159_128[31:0]
+// 19 rx_bitmap_191_160[31:0]
+// 20 rx_bitmap_223_192[31:0]
+// 21 rx_bitmap_255_224[31:0]
+// 22 current_mpdu_count[6:0], current_msdu_count[31:7]
+// 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16]
+// 24 frames_in_order_count[23:0], bar_received_count[31:24]
+// 25 mpdu_frames_processed_count[31:0]
+// 26 msdu_frames_processed_count[31:0]
+// 27 total_processed_byte_count[31:0]
+// 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16]
+// 29 reserved_29[31:0]
+// 30 reserved_30[31:0]
+// 31 reserved_31[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_REO_QUEUE 32
+
+struct rx_reo_queue {
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t receive_queue_number : 16, //[15:0]
+ reserved_1b : 16; //[31:16]
+ uint32_t vld : 1, //[0]
+ associated_link_descriptor_counter: 2, //[2:1]
+ disable_duplicate_detection : 1, //[3]
+ soft_reorder_enable : 1, //[4]
+ ac : 2, //[6:5]
+ bar : 1, //[7]
+ rty : 1, //[8]
+ chk_2k_mode : 1, //[9]
+ oor_mode : 1, //[10]
+ ba_window_size : 8, //[18:11]
+ pn_check_needed : 1, //[19]
+ pn_shall_be_even : 1, //[20]
+ pn_shall_be_uneven : 1, //[21]
+ pn_handling_enable : 1, //[22]
+ pn_size : 2, //[24:23]
+ ignore_ampdu_flag : 1, //[25]
+ reserved_2b : 6; //[31:26]
+ uint32_t svld : 1, //[0]
+ ssn : 12, //[12:1]
+ current_index : 8, //[20:13]
+ seq_2k_error_detected_flag : 1, //[21]
+ pn_error_detected_flag : 1, //[22]
+ reserved_3a : 8, //[30:23]
+ pn_valid : 1; //[31]
+ uint32_t pn_31_0 : 32; //[31:0]
+ uint32_t pn_63_32 : 32; //[31:0]
+ uint32_t pn_95_64 : 32; //[31:0]
+ uint32_t pn_127_96 : 32; //[31:0]
+ uint32_t last_rx_enqueue_timestamp : 32; //[31:0]
+ uint32_t last_rx_dequeue_timestamp : 32; //[31:0]
+ uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0]
+ uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0]
+ reserved_11a : 24; //[31:8]
+ uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0]
+ uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0]
+ reserved_13a : 24; //[31:8]
+ uint32_t rx_bitmap_31_0 : 32; //[31:0]
+ uint32_t rx_bitmap_63_32 : 32; //[31:0]
+ uint32_t rx_bitmap_95_64 : 32; //[31:0]
+ uint32_t rx_bitmap_127_96 : 32; //[31:0]
+ uint32_t rx_bitmap_159_128 : 32; //[31:0]
+ uint32_t rx_bitmap_191_160 : 32; //[31:0]
+ uint32_t rx_bitmap_223_192 : 32; //[31:0]
+ uint32_t rx_bitmap_255_224 : 32; //[31:0]
+ uint32_t current_mpdu_count : 7, //[6:0]
+ current_msdu_count : 25; //[31:7]
+ uint32_t reserved_23 : 4, //[3:0]
+ timeout_count : 6, //[9:4]
+ forward_due_to_bar_count : 6, //[15:10]
+ duplicate_count : 16; //[31:16]
+ uint32_t frames_in_order_count : 24, //[23:0]
+ bar_received_count : 8; //[31:24]
+ uint32_t mpdu_frames_processed_count : 32; //[31:0]
+ uint32_t msdu_frames_processed_count : 32; //[31:0]
+ uint32_t total_processed_byte_count : 32; //[31:0]
+ uint32_t late_receive_mpdu_count : 12, //[11:0]
+ window_jump_2k : 4, //[15:12]
+ hole_count : 16; //[31:16]
+ uint32_t reserved_29 : 32; //[31:0]
+ uint32_t reserved_30 : 32; //[31:0]
+ uint32_t reserved_31 : 32; //[31:0]
+};
+
+/*
+
+struct uniform_descriptor_header descriptor_header
+
+ Details about which module owns this struct.
+
+ Note that sub field Buffer_type shall be set to
+ Receive_REO_queue_descriptor
+
+receive_queue_number
+
+ Indicates the MPDU queue ID to which this MPDU link
+ descriptor belongs
+
+ Used for tracking and debugging
+
+ <legal all>
+
+reserved_1b
+
+ <legal 0>
+
+vld
+
+ Valid bit indicating a session is established and the
+ queue descriptor is valid(Filled by SW)
+
+ <legal all>
+
+associated_link_descriptor_counter
+
+ Indicates which of the 3 link descriptor counters shall
+ be incremented or decremented when link descriptors are
+ added or removed from this flow queue.
+
+ MSDU link descriptors related with MPDUs stored in the
+ re-order buffer shall also be included in this count.
+
+
+
+ <legal 0-2>
+
+disable_duplicate_detection
+
+ When set, do not perform any duplicate detection.
+
+
+
+ <legal all>
+
+soft_reorder_enable
+
+ When set, REO has been instructed to not perform the
+ actual re-ordering of frames for this queue, but just to
+ insert the reorder opcodes.
+
+
+
+ Note that this implies that REO is also not going to
+ perform any MSDU level operations, and the entire MPDU (and
+ thus pointer to the MSDU link descriptor) will be pushed to
+ a destination ring that SW has programmed in a SW
+ programmable configuration register in REO
+
+
+
+ <legal all>
+
+ac
+
+ Indicates which access category the queue descriptor
+ belongs to(filled by SW)
+
+ <legal all>
+
+bar
+
+ Indicates if BAR has been received (mostly used for
+ debug purpose and this is filled by REO)
+
+ <legal all>
+
+rty
+
+ Retry bit is checked if this bit is set.
+
+ <legal all>
+
+chk_2k_mode
+
+ Indicates what type of operation is expected from Reo
+ when the received frame SN falls within the 2K window
+
+
+
+ See REO MLD document for programming details.
+
+ <legal all>
+
+oor_mode
+
+ Out of Order mode:
+
+ Indicates what type of operation is expected when the
+ received frame falls within the OOR window.
+
+
+
+ See REO MLD document for programming details.
+
+ <legal all>
+
+ba_window_size
+
+ Indicates the negotiated (window size + 1).
+
+ It can go up to Max of 256bits.
+
+
+
+ A value 255 means 256 bitmap, 63 means 64 bitmap, 0
+ (means non-BA session, with window size of 0). The 3 values
+ here are the main values validated, but other values should
+ work as well.
+
+
+
+ A BA window size of 0 (=> one frame entry bitmat), means
+ that there is NO RX_REO_QUEUE_EXT descriptor following this
+ RX_REO_QUEUE STRUCT in memory
+
+
+
+ A BA window size of 1 - 105, means that there is 1
+ RX_REO_QUEUE_EXT descriptor directly following this
+ RX_REO_QUEUE STRUCT in memory.
+
+
+
+ A BA window size of 106 - 210, means that there are 2
+ RX_REO_QUEUE_EXT descriptors directly following this
+ RX_REO_QUEUE STRUCT in memory
+
+
+
+ A BA window size of 211 - 256, means that there are 3
+ RX_REO_QUEUE_EXT descriptors directly following this
+ RX_REO_QUEUE STRUCT in memory
+
+
+
+ <legal 0 - 255>
+
+pn_check_needed
+
+ When set, REO shall perform the PN increment check
+
+ <legal all>
+
+pn_shall_be_even
+
+ Field only valid when 'pn_check_needed' is set.
+
+
+
+ When set, REO shall confirm that the received PN number
+ is not only incremented, but also always an even number
+
+ <legal all>
+
+pn_shall_be_uneven
+
+ Field only valid when 'pn_check_needed' is set.
+
+
+
+ When set, REO shall confirm that the received PN number
+ is not only incremented, but also always an uneven number
+
+ <legal all>
+
+pn_handling_enable
+
+ Field only valid when 'pn_check_needed' is set.
+
+
+
+ When set, and REO detected a PN error, HW shall set the
+ 'pn_error_detected_flag'.
+
+ <legal all>
+
+pn_size
+
+ Size of the PN field check.
+
+ Needed for wrap around handling...
+
+
+
+ <enum 0 pn_size_24>
+
+ <enum 1 pn_size_48>
+
+ <enum 2 pn_size_128>
+
+
+
+ <legal 0-2>
+
+ignore_ampdu_flag
+
+ When set, REO shall ignore the ampdu_flag on the
+ entrance descriptor for this queue.
+
+ <legal all>
+
+reserved_2b
+
+ <legal 0>
+
+svld
+
+ Sequence number in next field is valid one. It can be
+ filled by SW if the want to fill in the any negotiated SSN,
+ otherwise REO will fill the sequence number of first
+ received packet and set this bit to 1.
+
+ <legal all>
+
+ssn
+
+ Starting Sequence number of the session, this changes
+ whenever window moves. (can be filled by SW then maintained
+ by REO)
+
+ <legal all>
+
+current_index
+
+ Points to last forwarded packet
+
+ <legal all>
+
+seq_2k_error_detected_flag
+
+ Set by REO, can only be cleared by SW
+
+
+
+ When set, REO has detected a 2k error jump in the
+ sequence number and from that moment forward, all new frames
+ are forwarded directly to FW, without duplicate detect,
+ reordering, etc.
+
+ <legal all>
+
+pn_error_detected_flag
+
+ Set by REO, can only be cleared by SW
+
+
+
+ When set, REO has detected a PN error and from that
+ moment forward, all new frames are forwarded directly to FW,
+ without duplicate detect, reordering, etc.
+
+ <legal all>
+
+reserved_3a
+
+ <legal 0>
+
+pn_valid
+
+ PN number in next fields are valid. It can be filled by
+ SW if it wants to fill in the any negotiated SSN, otherwise
+ REO will fill the pn based on the first received packet and
+ set this bit to 1.
+
+ <legal all>
+
+pn_31_0
+
+
+ <legal all>
+
+pn_63_32
+
+ Bits [63:32] of the PN number.
+
+ <legal all>
+
+pn_95_64
+
+ Bits [95:64] of the PN number.
+
+ <legal all>
+
+pn_127_96
+
+ Bits [127:96] of the PN number.
+
+ <legal all>
+
+last_rx_enqueue_timestamp
+
+ This timestamp is updated when an MPDU is received and
+ accesses this Queue Descriptor. It does not include the
+ access due to Command TLVs or Aging (which will be updated
+ in Last_rx_dequeue_timestamp).
+
+ <legal all>
+
+last_rx_dequeue_timestamp
+
+ This timestamp is used for Aging. When an MPDU or
+ multiple MPDUs are forwarded, either due to window movement,
+ bar, aging or command flush, this timestamp is updated. Also
+ when the bitmap is all zero and the first time an MPDU is
+ queued (opcode=QCUR), this timestamp is updated for aging.
+
+ <legal all>
+
+ptr_to_next_aging_queue_31_0
+
+ Address (address bits 31-0)of next RX_REO_QUEUE
+ descriptor in the 'receive timestamp' ordered list.
+
+ From it the Position of this queue descriptor in the per
+ AC aging waitlist can be derived.
+
+ Value 0x0 indicates the 'NULL' pointer which implies
+ that this is the last entry in the list.
+
+ <legal all>
+
+ptr_to_next_aging_queue_39_32
+
+ Address (address bits 39-32)of next RX_REO_QUEUE
+ descriptor in the 'receive timestamp' ordered list.
+
+ From it the Position of this queue descriptor in the per
+ AC aging waitlist can be derived.
+
+ Value 0x0 indicates the 'NULL' pointer which implies
+ that this is the last entry in the list.
+
+ <legal all>
+
+reserved_11a
+
+ <legal 0>
+
+ptr_to_previous_aging_queue_31_0
+
+ Address (address bits 31-0)of next RX_REO_QUEUE
+ descriptor in the 'receive timestamp' ordered list.
+
+ From it the Position of this queue descriptor in the per
+ AC aging waitlist can be derived.
+
+ Value 0x0 indicates the 'NULL' pointer which implies
+ that this is the first entry in the list.
+
+ <legal all>
+
+ptr_to_previous_aging_queue_39_32
+
+ Address (address bits 39-32)of next RX_REO_QUEUE
+ descriptor in the 'receive timestamp' ordered list.
+
+ From it the Position of this queue descriptor in the per
+ AC aging waitlist can be derived.
+
+ Value 0x0 indicates the 'NULL' pointer which implies
+ that this is the first entry in the list.
+
+ <legal all>
+
+reserved_13a
+
+ <legal 0>
+
+rx_bitmap_31_0
+
+ When a bit is set, the corresponding frame is currently
+ held in the re-order queue.
+
+ The bitmap is Fully managed by HW.
+
+ SW shall init this to 0, and then never ever change it
+
+ <legal all>
+
+rx_bitmap_63_32
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_95_64
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_127_96
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_159_128
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_191_160
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_223_192
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+rx_bitmap_255_224
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+
+current_mpdu_count
+
+ The number of MPDUs in the queue.
+
+
+
+ <legal all>
+
+current_msdu_count
+
+ The number of MSDUs in the queue.
+
+ <legal all>
+
+reserved_23
+
+ <legal 0>
+
+timeout_count
+
+ The number of times that REO started forwarding frames
+ even though there is a hole in the bitmap. Forwarding reason
+ is Timeout
+
+
+
+ The counter saturates and freezes at 0x3F
+
+
+
+ <legal all>
+
+forward_due_to_bar_count
+
+ The number of times that REO started forwarding frames
+ even though there is a hole in the bitmap. Forwarding reason
+ is reception of BAR frame.
+
+
+
+ The counter saturates and freezes at 0x3F
+
+
+
+ <legal all>
+
+duplicate_count
+
+ The number of duplicate frames that have been detected
+
+ <legal all>
+
+frames_in_order_count
+
+ The number of frames that have been received in order
+ (without a hole that prevented them from being forwarded
+ immediately)
+
+
+
+ This corresponds to the Reorder opcodes:
+
+ 'FWDCUR' and 'FWD BUF'
+
+
+
+ <legal all>
+
+bar_received_count
+
+ The number of times a BAR frame is received.
+
+
+
+ This corresponds to the Reorder opcodes with 'DROP'
+
+
+
+ The counter saturates and freezes at 0xFF
+
+ <legal all>
+
+mpdu_frames_processed_count
+
+ The total number of MPDU frames that have been processed
+ by REO. 'Processing' here means that REO has received them
+ out of the entrance ring, and retrieved the corresponding
+ RX_REO_QUEUE Descriptor.
+
+
+
+ Note that this count includes duplicates, frames that
+ later had errors, etc.
+
+
+
+ Note that field 'Duplicate_count' indicates how many of
+ these MPDUs were duplicates.
+
+
+
+ <legal all>
+
+msdu_frames_processed_count
+
+ The total number of MSDU frames that have been processed
+ by REO. 'Processing' here means that REO has received them
+ out of the entrance ring, and retrieved the corresponding
+ RX_REO_QUEUE Descriptor.
+
+
+
+ Note that this count includes duplicates, frames that
+ later had errors, etc.
+
+
+
+ <legal all>
+
+total_processed_byte_count
+
+ An approximation of the number of bytes processed for
+ this queue.
+
+ 'Processing' here means that REO has received them out
+ of the entrance ring, and retrieved the corresponding
+ RX_REO_QUEUE Descriptor.
+
+
+
+ Note that this count includes duplicates, frames that
+ later had errors, etc.
+
+
+
+ In 64 byte units
+
+ <legal all>
+
+late_receive_mpdu_count
+
+ The number of MPDUs received after the window had
+ already moved on. The 'late' sequence window is defined as
+ (Window SSN - 256) - (Window SSN - 1)
+
+
+
+ This corresponds with Out of order detection in
+ duplicate detect FSM
+
+
+
+ The counter saturates and freezes at 0xFFF
+
+
+
+ <legal all>
+
+window_jump_2k
+
+ The number of times the window moved more then 2K
+
+
+
+ The counter saturates and freezes at 0xF
+
+
+
+ (Note: field name can not start with number: previous
+ 2k_window_jump)
+
+
+
+ <legal all>
+
+hole_count
+
+ The number of times a hole was created in the receive
+ bitmap.
+
+
+
+ This corresponds to the Reorder opcodes with 'QCUR'
+
+
+
+ <legal all>
+
+reserved_29
+
+ <legal 0>
+
+reserved_30
+
+ <legal 0>
+
+reserved_31
+
+ <legal 0>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */
+
+
+/* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ The owner of this data structure:
+
+ <enum 0 WBM_owned> Buffer Manager currently owns this
+ data structure.
+
+ <enum 1 SW_OR_FW_owned> Software of FW currently owns
+ this data structure.
+
+ <enum 2 TQM_owned> Transmit Queue Manager currently owns
+ this data structure.
+
+ <enum 3 RXDMA_owned> Receive DMA currently owns this
+ data structure.
+
+ <enum 4 REO_owned> Reorder currently owns this data
+ structure.
+
+ <enum 5 SWITCH_owned> SWITCH currently owns this data
+ structure.
+
+
+
+ <legal 0-5>
+*/
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+/* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ Field describing what contents format is of this
+ descriptor
+
+
+
+ <enum 0 Transmit_MSDU_Link_descriptor >
+
+ <enum 1 Transmit_MPDU_Link_descriptor >
+
+ <enum 2 Transmit_MPDU_Queue_head_descriptor>
+
+ <enum 3 Transmit_MPDU_Queue_ext_descriptor>
+
+ <enum 4 Transmit_flow_descriptor>
+
+ <enum 5 Transmit_buffer > NOT TO BE USED:
+
+
+
+ <enum 6 Receive_MSDU_Link_descriptor >
+
+ <enum 7 Receive_MPDU_Link_descriptor >
+
+ <enum 8 Receive_REO_queue_descriptor >
+
+ <enum 9 Receive_REO_queue_ext_descriptor >
+
+
+
+ <enum 10 Receive_buffer >
+
+
+
+ <enum 11 Idle_link_list_entry>
+
+
+
+ <legal 0-11>
+*/
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+/* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
+#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
+
+/* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER
+
+ Indicates the MPDU queue ID to which this MPDU link
+ descriptor belongs
+
+ Used for tracking and debugging
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff
+
+/* Description RX_REO_QUEUE_1_RESERVED_1B
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004
+#define RX_REO_QUEUE_1_RESERVED_1B_LSB 16
+#define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000
+
+/* Description RX_REO_QUEUE_2_VLD
+
+ Valid bit indicating a session is established and the
+ queue descriptor is valid(Filled by SW)
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_VLD_LSB 0
+#define RX_REO_QUEUE_2_VLD_MASK 0x00000001
+
+/* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
+
+ Indicates which of the 3 link descriptor counters shall
+ be incremented or decremented when link descriptors are
+ added or removed from this flow queue.
+
+ MSDU link descriptors related with MPDUs stored in the
+ re-order buffer shall also be included in this count.
+
+
+
+ <legal 0-2>
+*/
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006
+
+/* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION
+
+ When set, do not perform any duplicate detection.
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008
+
+/* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE
+
+ When set, REO has been instructed to not perform the
+ actual re-ordering of frames for this queue, but just to
+ insert the reorder opcodes.
+
+
+
+ Note that this implies that REO is also not going to
+ perform any MSDU level operations, and the entire MPDU (and
+ thus pointer to the MSDU link descriptor) will be pushed to
+ a destination ring that SW has programmed in a SW
+ programmable configuration register in REO
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010
+
+/* Description RX_REO_QUEUE_2_AC
+
+ Indicates which access category the queue descriptor
+ belongs to(filled by SW)
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_AC_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_AC_LSB 5
+#define RX_REO_QUEUE_2_AC_MASK 0x00000060
+
+/* Description RX_REO_QUEUE_2_BAR
+
+ Indicates if BAR has been received (mostly used for
+ debug purpose and this is filled by REO)
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_BAR_LSB 7
+#define RX_REO_QUEUE_2_BAR_MASK 0x00000080
+
+/* Description RX_REO_QUEUE_2_RTY
+
+ Retry bit is checked if this bit is set.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_RTY_LSB 8
+#define RX_REO_QUEUE_2_RTY_MASK 0x00000100
+
+/* Description RX_REO_QUEUE_2_CHK_2K_MODE
+
+ Indicates what type of operation is expected from Reo
+ when the received frame SN falls within the 2K window
+
+
+
+ See REO MLD document for programming details.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9
+#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200
+
+/* Description RX_REO_QUEUE_2_OOR_MODE
+
+ Out of Order mode:
+
+ Indicates what type of operation is expected when the
+ received frame falls within the OOR window.
+
+
+
+ See REO MLD document for programming details.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_OOR_MODE_LSB 10
+#define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400
+
+/* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE
+
+ Indicates the negotiated (window size + 1).
+
+ It can go up to Max of 256bits.
+
+
+
+ A value 255 means 256 bitmap, 63 means 64 bitmap, 0
+ (means non-BA session, with window size of 0). The 3 values
+ here are the main values validated, but other values should
+ work as well.
+
+
+
+ A BA window size of 0 (=> one frame entry bitmat), means
+ that there is NO RX_REO_QUEUE_EXT descriptor following this
+ RX_REO_QUEUE STRUCT in memory
+
+
+
+ A BA window size of 1 - 105, means that there is 1
+ RX_REO_QUEUE_EXT descriptor directly following this
+ RX_REO_QUEUE STRUCT in memory.
+
+
+
+ A BA window size of 106 - 210, means that there are 2
+ RX_REO_QUEUE_EXT descriptors directly following this
+ RX_REO_QUEUE STRUCT in memory
+
+
+
+ A BA window size of 211 - 256, means that there are 3
+ RX_REO_QUEUE_EXT descriptors directly following this
+ RX_REO_QUEUE STRUCT in memory
+
+
+
+ <legal 0 - 255>
+*/
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800
+
+/* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED
+
+ When set, REO shall perform the PN increment check
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000
+
+/* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN
+
+ Field only valid when 'pn_check_needed' is set.
+
+
+
+ When set, REO shall confirm that the received PN number
+ is not only incremented, but also always an even number
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000
+
+/* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN
+
+ Field only valid when 'pn_check_needed' is set.
+
+
+
+ When set, REO shall confirm that the received PN number
+ is not only incremented, but also always an uneven number
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000
+
+/* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE
+
+ Field only valid when 'pn_check_needed' is set.
+
+
+
+ When set, and REO detected a PN error, HW shall set the
+ 'pn_error_detected_flag'.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000
+
+/* Description RX_REO_QUEUE_2_PN_SIZE
+
+ Size of the PN field check.
+
+ Needed for wrap around handling...
+
+
+
+ <enum 0 pn_size_24>
+
+ <enum 1 pn_size_48>
+
+ <enum 2 pn_size_128>
+
+
+
+ <legal 0-2>
+*/
+#define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_PN_SIZE_LSB 23
+#define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000
+
+/* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG
+
+ When set, REO shall ignore the ampdu_flag on the
+ entrance descriptor for this queue.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000
+
+/* Description RX_REO_QUEUE_2_RESERVED_2B
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008
+#define RX_REO_QUEUE_2_RESERVED_2B_LSB 26
+#define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000
+
+/* Description RX_REO_QUEUE_3_SVLD
+
+ Sequence number in next field is valid one. It can be
+ filled by SW if the want to fill in the any negotiated SSN,
+ otherwise REO will fill the sequence number of first
+ received packet and set this bit to 1.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_SVLD_LSB 0
+#define RX_REO_QUEUE_3_SVLD_MASK 0x00000001
+
+/* Description RX_REO_QUEUE_3_SSN
+
+ Starting Sequence number of the session, this changes
+ whenever window moves. (can be filled by SW then maintained
+ by REO)
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_SSN_LSB 1
+#define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe
+
+/* Description RX_REO_QUEUE_3_CURRENT_INDEX
+
+ Points to last forwarded packet
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13
+#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000
+
+/* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG
+
+ Set by REO, can only be cleared by SW
+
+
+
+ When set, REO has detected a 2k error jump in the
+ sequence number and from that moment forward, all new frames
+ are forwarded directly to FW, without duplicate detect,
+ reordering, etc.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000
+
+/* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG
+
+ Set by REO, can only be cleared by SW
+
+
+
+ When set, REO has detected a PN error and from that
+ moment forward, all new frames are forwarded directly to FW,
+ without duplicate detect, reordering, etc.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000
+
+/* Description RX_REO_QUEUE_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_RESERVED_3A_LSB 23
+#define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000
+
+/* Description RX_REO_QUEUE_3_PN_VALID
+
+ PN number in next fields are valid. It can be filled by
+ SW if it wants to fill in the any negotiated SSN, otherwise
+ REO will fill the pn based on the first received packet and
+ set this bit to 1.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c
+#define RX_REO_QUEUE_3_PN_VALID_LSB 31
+#define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000
+
+/* Description RX_REO_QUEUE_4_PN_31_0
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_4_PN_31_0_LSB 0
+#define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_5_PN_63_32
+
+ Bits [63:32] of the PN number.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_5_PN_63_32_LSB 0
+#define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_6_PN_95_64
+
+ Bits [95:64] of the PN number.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018
+#define RX_REO_QUEUE_6_PN_95_64_LSB 0
+#define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_7_PN_127_96
+
+ Bits [127:96] of the PN number.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c
+#define RX_REO_QUEUE_7_PN_127_96_LSB 0
+#define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP
+
+ This timestamp is updated when an MPDU is received and
+ accesses this Queue Descriptor. It does not include the
+ access due to Command TLVs or Aging (which will be updated
+ in Last_rx_dequeue_timestamp).
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP
+
+ This timestamp is used for Aging. When an MPDU or
+ multiple MPDUs are forwarded, either due to window movement,
+ bar, aging or command flush, this timestamp is updated. Also
+ when the bitmap is all zero and the first time an MPDU is
+ queued (opcode=QCUR), this timestamp is updated for aging.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0
+
+ Address (address bits 31-0)of next RX_REO_QUEUE
+ descriptor in the 'receive timestamp' ordered list.
+
+ From it the Position of this queue descriptor in the per
+ AC aging waitlist can be derived.
+
+ Value 0x0 indicates the 'NULL' pointer which implies
+ that this is the last entry in the list.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32
+
+ Address (address bits 39-32)of next RX_REO_QUEUE
+ descriptor in the 'receive timestamp' ordered list.
+
+ From it the Position of this queue descriptor in the per
+ AC aging waitlist can be derived.
+
+ Value 0x0 indicates the 'NULL' pointer which implies
+ that this is the last entry in the list.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_11_RESERVED_11A
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c
+#define RX_REO_QUEUE_11_RESERVED_11A_LSB 8
+#define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00
+
+/* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0
+
+ Address (address bits 31-0)of next RX_REO_QUEUE
+ descriptor in the 'receive timestamp' ordered list.
+
+ From it the Position of this queue descriptor in the per
+ AC aging waitlist can be derived.
+
+ Value 0x0 indicates the 'NULL' pointer which implies
+ that this is the first entry in the list.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32
+
+ Address (address bits 39-32)of next RX_REO_QUEUE
+ descriptor in the 'receive timestamp' ordered list.
+
+ From it the Position of this queue descriptor in the per
+ AC aging waitlist can be derived.
+
+ Value 0x0 indicates the 'NULL' pointer which implies
+ that this is the first entry in the list.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_13_RESERVED_13A
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034
+#define RX_REO_QUEUE_13_RESERVED_13A_LSB 8
+#define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00
+
+/* Description RX_REO_QUEUE_14_RX_BITMAP_31_0
+
+ When a bit is set, the corresponding frame is currently
+ held in the re-order queue.
+
+ The bitmap is Fully managed by HW.
+
+ SW shall init this to 0, and then never ever change it
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_15_RX_BITMAP_63_32
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_16_RX_BITMAP_95_64
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_17_RX_BITMAP_127_96
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_18_RX_BITMAP_159_128
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_19_RX_BITMAP_191_160
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_20_RX_BITMAP_223_192
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_21_RX_BITMAP_255_224
+
+ See Rx_bitmap_31_0 description
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT
+
+ The number of MPDUs in the queue.
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f
+
+/* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT
+
+ The number of MSDUs in the queue.
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80
+
+/* Description RX_REO_QUEUE_23_RESERVED_23
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c
+#define RX_REO_QUEUE_23_RESERVED_23_LSB 0
+#define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f
+
+/* Description RX_REO_QUEUE_23_TIMEOUT_COUNT
+
+ The number of times that REO started forwarding frames
+ even though there is a hole in the bitmap. Forwarding reason
+ is Timeout
+
+
+
+ The counter saturates and freezes at 0x3F
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0
+
+/* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT
+
+ The number of times that REO started forwarding frames
+ even though there is a hole in the bitmap. Forwarding reason
+ is reception of BAR frame.
+
+
+
+ The counter saturates and freezes at 0x3F
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00
+
+/* Description RX_REO_QUEUE_23_DUPLICATE_COUNT
+
+ The number of duplicate frames that have been detected
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000
+
+/* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT
+
+ The number of frames that have been received in order
+ (without a hole that prevented them from being forwarded
+ immediately)
+
+
+
+ This corresponds to the Reorder opcodes:
+
+ 'FWDCUR' and 'FWD BUF'
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff
+
+/* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT
+
+ The number of times a BAR frame is received.
+
+
+
+ This corresponds to the Reorder opcodes with 'DROP'
+
+
+
+ The counter saturates and freezes at 0xFF
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000
+
+/* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT
+
+ The total number of MPDU frames that have been processed
+ by REO. 'Processing' here means that REO has received them
+ out of the entrance ring, and retrieved the corresponding
+ RX_REO_QUEUE Descriptor.
+
+
+
+ Note that this count includes duplicates, frames that
+ later had errors, etc.
+
+
+
+ Note that field 'Duplicate_count' indicates how many of
+ these MPDUs were duplicates.
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT
+
+ The total number of MSDU frames that have been processed
+ by REO. 'Processing' here means that REO has received them
+ out of the entrance ring, and retrieved the corresponding
+ RX_REO_QUEUE Descriptor.
+
+
+
+ Note that this count includes duplicates, frames that
+ later had errors, etc.
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT
+
+ An approximation of the number of bytes processed for
+ this queue.
+
+ 'Processing' here means that REO has received them out
+ of the entrance ring, and retrieved the corresponding
+ RX_REO_QUEUE Descriptor.
+
+
+
+ Note that this count includes duplicates, frames that
+ later had errors, etc.
+
+
+
+ In 64 byte units
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT
+
+ The number of MPDUs received after the window had
+ already moved on. The 'late' sequence window is defined as
+ (Window SSN - 256) - (Window SSN - 1)
+
+
+
+ This corresponds with Out of order detection in
+ duplicate detect FSM
+
+
+
+ The counter saturates and freezes at 0xFFF
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff
+
+/* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K
+
+ The number of times the window moved more then 2K
+
+
+
+ The counter saturates and freezes at 0xF
+
+
+
+ (Note: field name can not start with number: previous
+ 2k_window_jump)
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000
+
+/* Description RX_REO_QUEUE_28_HOLE_COUNT
+
+ The number of times a hole was created in the receive
+ bitmap.
+
+
+
+ This corresponds to the Reorder opcodes with 'QCUR'
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070
+#define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16
+#define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000
+
+/* Description RX_REO_QUEUE_29_RESERVED_29
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074
+#define RX_REO_QUEUE_29_RESERVED_29_LSB 0
+#define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_30_RESERVED_30
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078
+#define RX_REO_QUEUE_30_RESERVED_30_LSB 0
+#define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_31_RESERVED_31
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c
+#define RX_REO_QUEUE_31_RESERVED_31_LSB 0
+#define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff
+
+
+#endif // _RX_REO_QUEUE_H_
diff --git a/hw/qca5018/rx_reo_queue_ext.h b/hw/qca5018/rx_reo_queue_ext.h
new file mode 100644
index 0000000..4ad8130
--- /dev/null
+++ b/hw/qca5018/rx_reo_queue_ext.h
@@ -0,0 +1,3117 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_REO_QUEUE_EXT_H_
+#define _RX_REO_QUEUE_EXT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+#include "rx_mpdu_link_ptr.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 struct uniform_descriptor_header descriptor_header;
+// 1 reserved_1a[31:0]
+// 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0;
+// 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1;
+// 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2;
+// 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3;
+// 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4;
+// 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5;
+// 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6;
+// 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7;
+// 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8;
+// 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9;
+// 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10;
+// 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11;
+// 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12;
+// 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13;
+// 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
+
+struct rx_reo_queue_ext {
+ struct uniform_descriptor_header descriptor_header;
+ uint32_t reserved_1a : 32; //[31:0]
+ struct rx_mpdu_link_ptr mpdu_link_pointer_0;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_1;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_2;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_3;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_4;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_5;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_6;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_7;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_8;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_9;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_10;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_11;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_12;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_13;
+ struct rx_mpdu_link_ptr mpdu_link_pointer_14;
+};
+
+/*
+
+struct uniform_descriptor_header descriptor_header
+
+ Details about which module owns this struct.
+
+ Note that sub field Buffer_type shall be set to
+ Receive_REO_queue_ext_descriptor
+
+reserved_1a
+
+ <legal 0>
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_0
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_1
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_2
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_3
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_4
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_5
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_6
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_7
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_8
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_9
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_10
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_11
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_12
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_13
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_14
+
+ Consumer: REO
+
+ Producer: REO
+
+
+
+ Pointer to the next MPDU_link descriptor in the MPDU
+ queue
+*/
+
+
+ /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */
+
+
+/* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ The owner of this data structure:
+
+ <enum 0 WBM_owned> Buffer Manager currently owns this
+ data structure.
+
+ <enum 1 SW_OR_FW_owned> Software of FW currently owns
+ this data structure.
+
+ <enum 2 TQM_owned> Transmit Queue Manager currently owns
+ this data structure.
+
+ <enum 3 RXDMA_owned> Receive DMA currently owns this
+ data structure.
+
+ <enum 4 REO_owned> Reorder currently owns this data
+ structure.
+
+ <enum 5 SWITCH_owned> SWITCH currently owns this data
+ structure.
+
+
+
+ <legal 0-5>
+*/
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f
+
+/* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ Field describing what contents format is of this
+ descriptor
+
+
+
+ <enum 0 Transmit_MSDU_Link_descriptor >
+
+ <enum 1 Transmit_MPDU_Link_descriptor >
+
+ <enum 2 Transmit_MPDU_Queue_head_descriptor>
+
+ <enum 3 Transmit_MPDU_Queue_ext_descriptor>
+
+ <enum 4 Transmit_flow_descriptor>
+
+ <enum 5 Transmit_buffer > NOT TO BE USED:
+
+
+
+ <enum 6 Receive_MSDU_Link_descriptor >
+
+ <enum 7 Receive_MPDU_Link_descriptor >
+
+ <enum 8 Receive_REO_queue_descriptor >
+
+ <enum 9 Receive_REO_queue_ext_descriptor >
+
+
+
+ <enum 10 Receive_buffer >
+
+
+
+ <enum 11 Idle_link_list_entry>
+
+
+
+ <legal 0-11>
+*/
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0
+
+/* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8
+#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00
+
+/* Description RX_REO_QUEUE_EXT_1_RESERVED_1A
+
+ <legal 0>
+*/
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_0 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_1 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_2 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_3 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_4 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_5 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_6 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_7 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_8 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_9 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_10 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_11 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_12 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_13 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+ /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_14 */
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */
+
+
+/* Description RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+
+#endif // _RX_REO_QUEUE_EXT_H_
diff --git a/hw/qca5018/rx_rxpcu_classification_overview.h b/hw/qca5018/rx_rxpcu_classification_overview.h
new file mode 100644
index 0000000..4b703c5
--- /dev/null
+++ b/hw/qca5018/rx_rxpcu_classification_overview.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 filter_pass_mpdus[0], filter_pass_mpdus_fcs_ok[1], monitor_direct_mpdus[2], monitor_direct_mpdus_fcs_ok[3], monitor_other_mpdus[4], monitor_other_mpdus_fcs_ok[5], phyrx_abort_received[6], reserved_0[15:7], phy_ppdu_id[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1
+
+struct rx_rxpcu_classification_overview {
+ uint32_t filter_pass_mpdus : 1, //[0]
+ filter_pass_mpdus_fcs_ok : 1, //[1]
+ monitor_direct_mpdus : 1, //[2]
+ monitor_direct_mpdus_fcs_ok : 1, //[3]
+ monitor_other_mpdus : 1, //[4]
+ monitor_other_mpdus_fcs_ok : 1, //[5]
+ phyrx_abort_received : 1, //[6]
+ reserved_0 : 9, //[15:7]
+ phy_ppdu_id : 16; //[31:16]
+};
+
+/*
+
+filter_pass_mpdus
+
+ When set, at least one Filter Pass MPDU has been
+ received. FCS might or might not have been passing.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+
+filter_pass_mpdus_fcs_ok
+
+ When set, at least one Filter Pass MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+
+
+ <legal all>
+
+monitor_direct_mpdus
+
+ When set, at least one Monitor Direct MPDU has been
+ received. FCS might or might not have been passing
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+
+monitor_direct_mpdus_fcs_ok
+
+ When set, at least one Monitor Direct MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+
+
+ <legal all>
+
+monitor_other_mpdus
+
+ When set, at least one Monitor Direct MPDU has been
+ received. FCS might or might not have been passing.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+
+monitor_other_mpdus_fcs_ok
+
+ When set, at least one Monitor Direct MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+
+phyrx_abort_received
+
+ When set, PPDU reception was aborted by the PHY
+
+ <legal all>
+
+reserved_0
+
+ <legal 0>
+
+phy_ppdu_id
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS
+
+ When set, at least one Filter Pass MPDU has been
+ received. FCS might or might not have been passing.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK
+
+ When set, at least one Filter Pass MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+
+
+ <legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS
+
+ When set, at least one Monitor Direct MPDU has been
+ received. FCS might or might not have been passing
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK
+
+ When set, at least one Monitor Direct MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+
+
+ <legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS
+
+ When set, at least one Monitor Direct MPDU has been
+ received. FCS might or might not have been passing.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK
+
+ When set, at least one Monitor Direct MPDU has been
+ received that has a correct FCS.
+
+
+
+ For MU UL, in TLVs RX_PPDU_END and
+ RX_PPDU_END_STATUS_DONE, this field is the OR of all the
+ users.
+
+ <legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED
+
+ When set, PPDU reception was aborted by the PHY
+
+ <legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB 6
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0
+
+ <legal 0>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 7
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ff80
+
+/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID
+
+ A ppdu counter value that PHY increments for every PPDU
+ received. The counter value wraps around
+
+ <legal all>
+*/
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16
+#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000
+
+
+#endif // _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_
diff --git a/hw/qca5018/rx_timing_offset_info.h b/hw/qca5018/rx_timing_offset_info.h
new file mode 100644
index 0000000..c59bdad
--- /dev/null
+++ b/hw/qca5018/rx_timing_offset_info.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RX_TIMING_OFFSET_INFO_H_
+#define _RX_TIMING_OFFSET_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 residual_phase_offset[11:0], reserved[31:12]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1
+
+struct rx_timing_offset_info {
+ uint32_t residual_phase_offset : 12, //[11:0]
+ reserved : 20; //[31:12]
+};
+
+/*
+
+residual_phase_offset
+
+ Cumulative reference frequency error at end of RX
+
+ <legal all>
+
+reserved
+
+ <legal 0>
+*/
+
+
+/* Description RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET
+
+ Cumulative reference frequency error at end of RX
+
+ <legal all>
+*/
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_LSB 0
+#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff
+
+/* Description RX_TIMING_OFFSET_INFO_0_RESERVED
+
+ <legal 0>
+*/
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_OFFSET 0x00000000
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_LSB 12
+#define RX_TIMING_OFFSET_INFO_0_RESERVED_MASK 0xfffff000
+
+
+#endif // _RX_TIMING_OFFSET_INFO_H_
diff --git a/hw/qca5018/rxpcu_ppdu_end_info.h b/hw/qca5018/rxpcu_ppdu_end_info.h
new file mode 100644
index 0000000..cd257cb
--- /dev/null
+++ b/hw/qca5018/rxpcu_ppdu_end_info.h
@@ -0,0 +1,1227 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RXPCU_PPDU_END_INFO_H_
+#define _RXPCU_PPDU_END_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "phyrx_abort_request_info.h"
+#include "macrx_abort_request_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 wb_timestamp_lower_32[31:0]
+// 1 wb_timestamp_upper_32[31:0]
+// 2 rx_antenna[23:0], tx_ht_vht_ack[24], unsupported_mu_nc[25], otp_txbf_disable[26], previous_tlv_corrupted[27], phyrx_abort_request_info_valid[28], macrx_abort_request_info_valid[29], reserved[31:30]
+// 3 coex_bt_tx_from_start_of_rx[0], coex_bt_tx_after_start_of_rx[1], coex_wan_tx_from_start_of_rx[2], coex_wan_tx_after_start_of_rx[3], coex_wlan_tx_from_start_of_rx[4], coex_wlan_tx_after_start_of_rx[5], mpdu_delimiter_errors_seen[6], ftm_tm[8:7], dialog_token[16:9], follow_up_dialog_token[24:17], bb_captured_channel[25], bb_captured_reason[28:26], bb_captured_timeout[29], reserved_3[31:30]
+// 4 before_mpdu_count_passing_fcs[9:0], before_mpdu_count_failing_fcs[19:10], after_mpdu_count_passing_fcs[29:20], reserved_4[31:30]
+// 5 after_mpdu_count_failing_fcs[9:0], reserved_5[31:10]
+// 6 phy_timestamp_tx_lower_32[31:0]
+// 7 phy_timestamp_tx_upper_32[31:0]
+// 8 bb_length[15:0], bb_data[16], reserved_8[19:17], first_bt_broadcast_status_details[31:20]
+// 9 rx_ppdu_duration[23:0], reserved_9[31:24]
+// 10 ast_index[15:0], ast_index_valid[16], reserved_10[19:17], second_bt_broadcast_status_details[31:20]
+// 11 struct phyrx_abort_request_info phyrx_abort_request_info_details;
+// 12 struct macrx_abort_request_info macrx_abort_request_info_details;
+// 13 rx_ppdu_end_marker[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14
+
+struct rxpcu_ppdu_end_info {
+ uint32_t wb_timestamp_lower_32 : 32; //[31:0]
+ uint32_t wb_timestamp_upper_32 : 32; //[31:0]
+ uint32_t rx_antenna : 24, //[23:0]
+ tx_ht_vht_ack : 1, //[24]
+ unsupported_mu_nc : 1, //[25]
+ otp_txbf_disable : 1, //[26]
+ previous_tlv_corrupted : 1, //[27]
+ phyrx_abort_request_info_valid : 1, //[28]
+ macrx_abort_request_info_valid : 1, //[29]
+ reserved : 2; //[31:30]
+ uint32_t coex_bt_tx_from_start_of_rx : 1, //[0]
+ coex_bt_tx_after_start_of_rx : 1, //[1]
+ coex_wan_tx_from_start_of_rx : 1, //[2]
+ coex_wan_tx_after_start_of_rx : 1, //[3]
+ coex_wlan_tx_from_start_of_rx : 1, //[4]
+ coex_wlan_tx_after_start_of_rx : 1, //[5]
+ mpdu_delimiter_errors_seen : 1, //[6]
+ ftm_tm : 2, //[8:7]
+ dialog_token : 8, //[16:9]
+ follow_up_dialog_token : 8, //[24:17]
+ bb_captured_channel : 1, //[25]
+ bb_captured_reason : 3, //[28:26]
+ bb_captured_timeout : 1, //[29]
+ reserved_3 : 2; //[31:30]
+ uint32_t before_mpdu_count_passing_fcs : 10, //[9:0]
+ before_mpdu_count_failing_fcs : 10, //[19:10]
+ after_mpdu_count_passing_fcs : 10, //[29:20]
+ reserved_4 : 2; //[31:30]
+ uint32_t after_mpdu_count_failing_fcs : 10, //[9:0]
+ reserved_5 : 22; //[31:10]
+ uint32_t phy_timestamp_tx_lower_32 : 32; //[31:0]
+ uint32_t phy_timestamp_tx_upper_32 : 32; //[31:0]
+ uint32_t bb_length : 16, //[15:0]
+ bb_data : 1, //[16]
+ reserved_8 : 3, //[19:17]
+ first_bt_broadcast_status_details: 12; //[31:20]
+ uint32_t rx_ppdu_duration : 24, //[23:0]
+ reserved_9 : 8; //[31:24]
+ uint32_t ast_index : 16, //[15:0]
+ ast_index_valid : 1, //[16]
+ reserved_10 : 3, //[19:17]
+ second_bt_broadcast_status_details: 12; //[31:20]
+ struct phyrx_abort_request_info phyrx_abort_request_info_details;
+ struct macrx_abort_request_info macrx_abort_request_info_details;
+ uint16_t pre_bt_broadcast_status_details : 12, //[27:16]
+ reserved_12a : 4; //[31:28]
+ uint32_t rx_ppdu_end_marker : 32; //[31:0]
+};
+
+/*
+
+wb_timestamp_lower_32
+
+ WLAN/BT timestamp is a 1 usec resolution timestamp which
+ does not get updated based on receive beacon like TSF. The
+ same rules for capturing tsf_timestamp are used to capture
+ the wb_timestamp. This field represents the lower 32 bits of
+ the 64-bit timestamp
+
+wb_timestamp_upper_32
+
+ WLAN/BT timestamp is a 1 usec resolution timestamp which
+ does not get updated based on receive beacon like TSF. The
+ same rules for capturing tsf_timestamp are used to capture
+ the wb_timestamp. This field represents the upper 32 bits of
+ the 64-bit timestamp
+
+rx_antenna
+
+ Receive antenna value ???
+
+tx_ht_vht_ack
+
+ Indicates that a HT or VHT Ack/BA frame was transmitted
+ in response to this receive packet.
+
+unsupported_mu_nc
+
+ Set if MU Nc > 2 in received NDPA.
+
+ If this bit is set, even though AID and BSSID are
+ matched, MAC doesn't send tx_expect_ndp to PHY, because MU
+ Nc > 2 is not supported in Helium.
+
+otp_txbf_disable
+
+ Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is
+ set and if RXPU receives directed NDPA frame. Then, RXPCU
+ should not send TX_EXPECT_NDP TLV to SW but set this bit to
+ inform SW.
+
+previous_tlv_corrupted
+
+ When set, the TLV preceding this RXPCU_END_INFO TLV
+ within the RX_PPDU_END TLV, is corrupted. Not the entire TLV
+ was received.... Likely due to an abort scenario... If abort
+ is to blame, see the abort data datastructure for details.
+
+ <legal all>
+
+phyrx_abort_request_info_valid
+
+ When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to
+ RXPCU. The abort fields embedded in this TLV contain valid
+ info.
+
+ <legal all>
+
+macrx_abort_request_info_valid
+
+ When set, the MAC sent an MACRX_ABORT_REQUEST TLV to
+ PHYRX. The abort fields embedded in this TLV contain valid
+ info.
+
+ <legal all>
+
+reserved
+
+ <legal 0>
+
+coex_bt_tx_from_start_of_rx
+
+ Set when BT TX was ongoing when WLAN RX started
+
+coex_bt_tx_after_start_of_rx
+
+
+coex_wan_tx_from_start_of_rx
+
+ Set when WAN TX was ongoing when WLAN RX started
+
+coex_wan_tx_after_start_of_rx
+
+ Set when WAN TX started while WLAN RX was already
+ ongoing
+
+coex_wlan_tx_from_start_of_rx
+
+ Set when other WLAN TX was ongoing when WLAN RX started
+
+coex_wlan_tx_after_start_of_rx
+
+ Set when other WLAN TX started while WLAN RX was already
+ ongoing
+
+mpdu_delimiter_errors_seen
+
+ When set, MPDU delimiter errors have been detected
+ during this PPDU reception
+
+ftm_tm
+
+ Indicate the timestamp is for the FTM or TM frame
+
+
+
+ 0: non TM or FTM frame
+
+ 1: FTM frame
+
+ 2: TM frame
+
+ 3: reserved
+
+ <legal all>
+
+dialog_token
+
+ The dialog token in the FTM or TM frame. Only valid when
+ the FTM is set. Clear to 254 for a non-FTM frame
+
+ <legal all>
+
+follow_up_dialog_token
+
+ The follow up dialog token in the FTM or TM frame. Only
+ valid when the FTM is set. Clear to 0 for a non-FTM frame,
+ The follow up dialog token in the FTM frame. Only valid when
+ the FTM is set. Clear to 255 for a non-FTM frame<legal all>
+
+bb_captured_channel
+
+ Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is
+ sent to PHY, FW check it to correlate current PPDU TLVs with
+ uploaded channel information.
+
+
+
+ <legal all>
+
+bb_captured_reason
+
+ Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL TLV
+ to here for FW usage. Valid when bb_captured_channel or
+ bb_captured_timeout is set.
+
+
+
+ This field indicates why the MAC asked to capture the
+ channel
+
+ <enum 0 freeze_reason_TM>
+
+ <enum 1 freeze_reason_FTM>
+
+ <enum 2 freeze_reason_ACK_resp_to_TM_FTM>
+
+ <enum 3 freeze_reason_TA_RA_TYPE_FILTER>
+
+ <enum 4 freeze_reason_NDPA_NDP>
+
+ <enum 5 freeze_reason_ALL_PACKET>
+
+
+
+ <legal 0-5>
+
+bb_captured_timeout
+
+ Set by RxPCU to indicate channel capture condition is
+ meet, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY
+ due to AST long delay, which means the rx_frame_falling edge
+ to FREEZE TLV ready time exceed the threshold time defined
+ by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH.
+
+ Bb_captured_reason is still valid in this case.
+
+
+
+ <legal all>
+
+reserved_3
+
+ <legal 0>
+
+before_mpdu_count_passing_fcs
+
+ Number of MPDUs received in this PPDU that passed the
+ FCS check before the Coex TX started
+
+
+
+ The counter saturates at 0x3FF.
+
+ <legal all>
+
+before_mpdu_count_failing_fcs
+
+ Number of MPDUs received in this PPDU that failed the
+ FCS check before the Coex TX started
+
+
+
+ The counter saturates at 0x3FF.
+
+ <legal all>
+
+after_mpdu_count_passing_fcs
+
+ Number of MPDUs received in this PPDU that passed the
+ FCS check after the moment the Coex TX started
+
+
+
+ (Note: The partially received MPDU when the COEX tx
+ start event came in falls in the after category)
+
+
+
+ The counter saturates at 0x3FF.
+
+ <legal all>
+
+reserved_4
+
+ <legal 0>
+
+after_mpdu_count_failing_fcs
+
+ Number of MPDUs received in this PPDU that failed the
+ FCS check after the moment the Coex TX started
+
+
+
+ (Note: The partially received MPDU when the COEX tx
+ start event came in falls in the after category)
+
+
+
+ The counter saturates at 0x3FF.
+
+ <legal all>
+
+reserved_5
+
+ <legal 0>
+
+phy_timestamp_tx_lower_32
+
+ The PHY timestamp in the AMPI of the most recent rising
+ edge (TODO: of what ???) after the TX_PHY_DESC. This field
+ indicates the lower 32 bits of the timestamp
+
+phy_timestamp_tx_upper_32
+
+ The PHY timestamp in the AMPI of the most recent rising
+ edge (TODO: of what ???) after the TX_PHY_DESC. This field
+ indicates the upper 32 bits of the timestamp
+
+bb_length
+
+ Indicates the number of bytes of baseband information
+ for PPDUs where the BB descriptor preamble type is 0x80 to
+ 0xFF which indicates that this is not a normal PPDU but
+ rather contains baseband debug information.
+
+ TODO: Is this still needed ???
+
+bb_data
+
+ Indicates that BB data associated with this PPDU will
+ exist in the receive buffer. The exact contents of this BB
+ data can be found by decoding the BB TLV in the buffer
+ associated with the BB data. See vector_fragment in the
+ Helium_mac_phy_interface.docx
+
+reserved_8
+
+ Reserved: HW should fill with 0, FW should ignore.
+
+first_bt_broadcast_status_details
+
+ Same contents as field bt_broadcast_status_details for
+ the first received COEX_STATUS_BROADCAST tlv during this
+ PPDU reception.
+
+
+
+ If no COEX_STATUS_BROADCAST tlv is received during this
+ PPDU reception, this field will be set to 0
+
+
+
+
+
+ For detailed info see doc: TBD
+
+ <legal all>
+
+rx_ppdu_duration
+
+ The length of this PPDU reception in us
+
+reserved_9
+
+ <legal 0>
+
+ast_index
+
+ The AST index of the receive Ack/BA. This information
+ is provided from the TXPCU to the RXPCU for receive Ack/BA
+ for implicit beamforming.
+
+ <legal all>
+
+ast_index_valid
+
+ Indicates that ast_index is valid. Should only be set
+ for receive Ack/BA where single stream implicit sounding is
+ captured.
+
+reserved_10
+
+ <legal 0>
+
+second_bt_broadcast_status_details
+
+ Same contents as field bt_broadcast_status_details for
+ the second received COEX_STATUS_BROADCAST tlv during this
+ PPDU reception.
+
+
+
+ If no second COEX_STATUS_BROADCAST tlv is received
+ during this PPDU reception, this field will be set to 0
+
+
+
+
+
+ For detailed info see doc: TBD
+
+ <legal all>
+
+struct phyrx_abort_request_info phyrx_abort_request_info_details
+
+ Field only valid when Phyrx_abort_request_info_valid is
+ set
+
+ The reason why PHY generated an abort request
+
+struct macrx_abort_request_info macrx_abort_request_info_details
+
+ Field only valid when macrx_abort_request_info_valid is
+ set
+
+ The reason why MACRX generated an abort request
+
+rx_ppdu_end_marker
+
+ Field used by SW to double check that their structure
+ alignment is in sync with what HW has done.
+
+ <legal 0xAABBCCDD>
+*/
+
+
+/* Description RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32
+
+ WLAN/BT timestamp is a 1 usec resolution timestamp which
+ does not get updated based on receive beacon like TSF. The
+ same rules for capturing tsf_timestamp are used to capture
+ the wb_timestamp. This field represents the lower 32 bits of
+ the 64-bit timestamp
+*/
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff
+
+/* Description RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32
+
+ WLAN/BT timestamp is a 1 usec resolution timestamp which
+ does not get updated based on receive beacon like TSF. The
+ same rules for capturing tsf_timestamp are used to capture
+ the wb_timestamp. This field represents the upper 32 bits of
+ the 64-bit timestamp
+*/
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff
+
+/* Description RXPCU_PPDU_END_INFO_2_RX_ANTENNA
+
+ Receive antenna value ???
+*/
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0
+#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff
+
+/* Description RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK
+
+ Indicates that a HT or VHT Ack/BA frame was transmitted
+ in response to this receive packet.
+*/
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24
+#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000
+
+/* Description RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC
+
+ Set if MU Nc > 2 in received NDPA.
+
+ If this bit is set, even though AID and BSSID are
+ matched, MAC doesn't send tx_expect_ndp to PHY, because MU
+ Nc > 2 is not supported in Helium.
+*/
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25
+#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000
+
+/* Description RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE
+
+ Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is
+ set and if RXPU receives directed NDPA frame. Then, RXPCU
+ should not send TX_EXPECT_NDP TLV to SW but set this bit to
+ inform SW.
+*/
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26
+#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000
+
+/* Description RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED
+
+ When set, the TLV preceding this RXPCU_END_INFO TLV
+ within the RX_PPDU_END TLV, is corrupted. Not the entire TLV
+ was received.... Likely due to an abort scenario... If abort
+ is to blame, see the abort data datastructure for details.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27
+#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000
+
+/* Description RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID
+
+ When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to
+ RXPCU. The abort fields embedded in this TLV contain valid
+ info.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28
+#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000
+
+/* Description RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID
+
+ When set, the MAC sent an MACRX_ABORT_REQUEST TLV to
+ PHYRX. The abort fields embedded in this TLV contain valid
+ info.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29
+#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000
+
+/* Description RXPCU_PPDU_END_INFO_2_RESERVED
+
+ <legal 0>
+*/
+#define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008
+#define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30
+#define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000
+
+/* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX
+
+ Set when BT TX was ongoing when WLAN RX started
+*/
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001
+
+/* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX
+
+*/
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1
+#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002
+
+/* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX
+
+ Set when WAN TX was ongoing when WLAN RX started
+*/
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004
+
+/* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX
+
+ Set when WAN TX started while WLAN RX was already
+ ongoing
+*/
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3
+#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008
+
+/* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX
+
+ Set when other WLAN TX was ongoing when WLAN RX started
+*/
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010
+
+/* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX
+
+ Set when other WLAN TX started while WLAN RX was already
+ ongoing
+*/
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5
+#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020
+
+/* Description RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN
+
+ When set, MPDU delimiter errors have been detected
+ during this PPDU reception
+*/
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6
+#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040
+
+/* Description RXPCU_PPDU_END_INFO_3_FTM_TM
+
+ Indicate the timestamp is for the FTM or TM frame
+
+
+
+ 0: non TM or FTM frame
+
+ 1: FTM frame
+
+ 2: TM frame
+
+ 3: reserved
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_3_FTM_TM_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_FTM_TM_LSB 7
+#define RXPCU_PPDU_END_INFO_3_FTM_TM_MASK 0x00000180
+
+/* Description RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN
+
+ The dialog token in the FTM or TM frame. Only valid when
+ the FTM is set. Clear to 254 for a non-FTM frame
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9
+#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00
+
+/* Description RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN
+
+ The follow up dialog token in the FTM or TM frame. Only
+ valid when the FTM is set. Clear to 0 for a non-FTM frame,
+ The follow up dialog token in the FTM frame. Only valid when
+ the FTM is set. Clear to 255 for a non-FTM frame<legal all>
+*/
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17
+#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000
+
+/* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL
+
+ Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is
+ sent to PHY, FW check it to correlate current PPDU TLVs with
+ uploaded channel information.
+
+
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000
+
+/* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON
+
+ Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL TLV
+ to here for FW usage. Valid when bb_captured_channel or
+ bb_captured_timeout is set.
+
+
+
+ This field indicates why the MAC asked to capture the
+ channel
+
+ <enum 0 freeze_reason_TM>
+
+ <enum 1 freeze_reason_FTM>
+
+ <enum 2 freeze_reason_ACK_resp_to_TM_FTM>
+
+ <enum 3 freeze_reason_TA_RA_TYPE_FILTER>
+
+ <enum 4 freeze_reason_NDPA_NDP>
+
+ <enum 5 freeze_reason_ALL_PACKET>
+
+
+
+ <legal 0-5>
+*/
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000
+
+/* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT
+
+ Set by RxPCU to indicate channel capture condition is
+ meet, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY
+ due to AST long delay, which means the rx_frame_falling edge
+ to FREEZE TLV ready time exceed the threshold time defined
+ by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH.
+
+ Bb_captured_reason is still valid in this case.
+
+
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29
+#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000
+
+/* Description RXPCU_PPDU_END_INFO_3_RESERVED_3
+
+ <legal 0>
+*/
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30
+#define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000
+
+/* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS
+
+ Number of MPDUs received in this PPDU that passed the
+ FCS check before the Coex TX started
+
+
+
+ The counter saturates at 0x3FF.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff
+
+/* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS
+
+ Number of MPDUs received in this PPDU that failed the
+ FCS check before the Coex TX started
+
+
+
+ The counter saturates at 0x3FF.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10
+#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00
+
+/* Description RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS
+
+ Number of MPDUs received in this PPDU that passed the
+ FCS check after the moment the Coex TX started
+
+
+
+ (Note: The partially received MPDU when the COEX tx
+ start event came in falls in the after category)
+
+
+
+ The counter saturates at 0x3FF.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20
+#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000
+
+/* Description RXPCU_PPDU_END_INFO_4_RESERVED_4
+
+ <legal 0>
+*/
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30
+#define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000
+
+/* Description RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS
+
+ Number of MPDUs received in this PPDU that failed the
+ FCS check after the moment the Coex TX started
+
+
+
+ (Note: The partially received MPDU when the COEX tx
+ start event came in falls in the after category)
+
+
+
+ The counter saturates at 0x3FF.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0
+#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff
+
+/* Description RXPCU_PPDU_END_INFO_5_RESERVED_5
+
+ <legal 0>
+*/
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10
+#define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00
+
+/* Description RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32
+
+ The PHY timestamp in the AMPI of the most recent rising
+ edge (TODO: of what ???) after the TX_PHY_DESC. This field
+ indicates the lower 32 bits of the timestamp
+*/
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff
+
+/* Description RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32
+
+ The PHY timestamp in the AMPI of the most recent rising
+ edge (TODO: of what ???) after the TX_PHY_DESC. This field
+ indicates the upper 32 bits of the timestamp
+*/
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0
+#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff
+
+/* Description RXPCU_PPDU_END_INFO_8_BB_LENGTH
+
+ Indicates the number of bytes of baseband information
+ for PPDUs where the BB descriptor preamble type is 0x80 to
+ 0xFF which indicates that this is not a normal PPDU but
+ rather contains baseband debug information.
+
+ TODO: Is this still needed ???
+*/
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0
+#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff
+
+/* Description RXPCU_PPDU_END_INFO_8_BB_DATA
+
+ Indicates that BB data associated with this PPDU will
+ exist in the receive buffer. The exact contents of this BB
+ data can be found by decoding the BB TLV in the buffer
+ associated with the BB data. See vector_fragment in the
+ Helium_mac_phy_interface.docx
+*/
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16
+#define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000
+
+/* Description RXPCU_PPDU_END_INFO_8_RESERVED_8
+
+ Reserved: HW should fill with 0, FW should ignore.
+*/
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17
+#define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000
+
+/* Description RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS
+
+ Same contents as field bt_broadcast_status_details for
+ the first received COEX_STATUS_BROADCAST tlv during this
+ PPDU reception.
+
+
+
+ If no COEX_STATUS_BROADCAST tlv is received during this
+ PPDU reception, this field will be set to 0
+
+
+
+
+
+ For detailed info see doc: TBD
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20
+#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000
+
+/* Description RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION
+
+ The length of this PPDU reception in us
+*/
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0
+#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff
+
+/* Description RXPCU_PPDU_END_INFO_9_RESERVED_9
+
+ <legal 0>
+*/
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24
+#define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000
+
+/* Description RXPCU_PPDU_END_INFO_10_AST_INDEX
+
+ The AST index of the receive Ack/BA. This information
+ is provided from the TXPCU to the RXPCU for receive Ack/BA
+ for implicit beamforming.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff
+
+/* Description RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID
+
+ Indicates that ast_index is valid. Should only be set
+ for receive Ack/BA where single stream implicit sounding is
+ captured.
+*/
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16
+#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000
+
+/* Description RXPCU_PPDU_END_INFO_10_RESERVED_10
+
+ <legal 0>
+*/
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17
+#define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000
+
+/* Description RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS
+
+ Same contents as field bt_broadcast_status_details for
+ the second received COEX_STATUS_BROADCAST tlv during this
+ PPDU reception.
+
+
+
+ If no second COEX_STATUS_BROADCAST tlv is received
+ during this PPDU reception, this field will be set to 0
+
+
+
+
+
+ For detailed info see doc: TBD
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20
+#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000
+
+ /* EXTERNAL REFERENCE : struct phyrx_abort_request_info phyrx_abort_request_info_details */
+
+
+/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON
+
+ <enum 0 phyrx_err_phy_off> Reception aborted due to
+ receiving a PHY_OFF TLV
+
+ <enum 1 phyrx_err_synth_off>
+
+ <enum 2 phyrx_err_ofdma_timing>
+
+ <enum 3 phyrx_err_ofdma_signal_parity>
+
+ <enum 4 phyrx_err_ofdma_rate_illegal>
+
+ <enum 5 phyrx_err_ofdma_length_illegal>
+
+ <enum 6 phyrx_err_ofdma_restart>
+
+ <enum 7 phyrx_err_ofdma_service>
+
+ <enum 8 phyrx_err_ppdu_ofdma_power_drop>
+
+
+
+ <enum 9 phyrx_err_cck_blokker>
+
+ <enum 10 phyrx_err_cck_timing>
+
+ <enum 11 phyrx_err_cck_header_crc>
+
+ <enum 12 phyrx_err_cck_rate_illegal>
+
+ <enum 13 phyrx_err_cck_length_illegal>
+
+ <enum 14 phyrx_err_cck_restart>
+
+ <enum 15 phyrx_err_cck_service>
+
+ <enum 16 phyrx_err_cck_power_drop>
+
+
+
+ <enum 17 phyrx_err_ht_crc_err>
+
+ <enum 18 phyrx_err_ht_length_illegal>
+
+ <enum 19 phyrx_err_ht_rate_illegal>
+
+ <enum 20 phyrx_err_ht_zlf>
+
+ <enum 21 phyrx_err_false_radar_ext>
+
+
+
+ <enum 22 phyrx_err_green_field>
+
+
+
+ <enum 23 phyrx_err_bw_gt_dyn_bw>
+
+ <enum 24 phyrx_err_leg_ht_mismatch>
+
+ <enum 25 phyrx_err_vht_crc_error>
+
+ <enum 26 phyrx_err_vht_siga_unsupported>
+
+ <enum 27 phyrx_err_vht_lsig_len_invalid>
+
+ <enum 28 phyrx_err_vht_ndp_or_zlf>
+
+ <enum 29 phyrx_err_vht_nsym_lt_zero>
+
+ <enum 30 phyrx_err_vht_rx_extra_symbol_mismatch>
+
+ <enum 31 phyrx_err_vht_rx_skip_group_id0>
+
+ <enum 32 phyrx_err_vht_rx_skip_group_id1to62>
+
+ <enum 33 phyrx_err_vht_rx_skip_group_id63>
+
+ <enum 34 phyrx_err_ofdm_ldpc_decoder_disabled>
+
+ <enum 35 phyrx_err_defer_nap>
+
+ <enum 36 phyrx_err_fdomain_timeout>
+
+ <enum 37 phyrx_err_lsig_rel_check>
+
+ <enum 38 phyrx_err_bt_collision>
+
+ <enum 39 phyrx_err_unsupported_mu_feedback>
+
+ <enum 40 phyrx_err_ppdu_tx_interrupt_rx>
+
+ <enum 41 phyrx_err_unsupported_cbf>
+
+
+
+ <enum 42 phyrx_err_other> Should not really be used. If
+ needed, ask for documentation update
+
+
+
+ <enum 43 phyrx_err_he_siga_unsupported > <enum 44
+ phyrx_err_he_crc_error > <enum 45
+ phyrx_err_he_sigb_unsupported > <enum 46
+ phyrx_err_he_mu_mode_unsupported > <enum 47
+ phyrx_err_he_ndp_or_zlf > <enum 48 phyrx_err_he_nsym_lt_zero
+ > <enum 49 phyrx_err_he_ru_params_unsupported > <enum 50
+ phyrx_err_he_num_users_unsupported ><enum 51
+ phyrx_err_he_sounding_params_unsupported >
+
+
+
+ <enum 52 phyrx_err_MU_UL_no_power_detected>
+
+ <enum 53 phyrx_err_MU_UL_not_for_me>
+
+
+
+ <legal 0 - 53>
+*/
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff
+
+/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE
+
+ When set, PHY enters PHY NAP state after sending this
+ abort
+
+
+
+ Note that nap and defer state are mutually exclusive.
+
+
+
+ Field put pro-actively in place....usage still to be
+ agreed upon.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100
+
+/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE
+
+ When set, PHY enters PHY defer state after sending this
+ abort
+
+
+
+ Note that nap and defer state are mutually exclusive.
+
+
+
+ Field put pro-actively in place....usage still to be
+ agreed upon.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200
+
+/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0
+
+ <legal 0>
+*/
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00
+
+/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION
+
+ The remaining receive duration of this PPDU in the
+ medium (in us). When PHY does not know this duration when
+ this TLV is generated, the field will be set to 0.
+
+ The timing reference point is the reception by the MAC
+ of this TLV. The value shall be accurate to within 2us.
+
+
+
+ In case Phy_enters_nap_state and/or
+ Phy_enters_defer_state is set, there is a possibility that
+ MAC PMM can also decide to go into a low(er) power state.
+
+ <legal all>
+*/
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16
+#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000
+
+ /* EXTERNAL REFERENCE : struct macrx_abort_request_info macrx_abort_request_info_details */
+
+
+/* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON
+
+ <enum 0 macrx_abort_sw_initiated>
+
+ <enum 1 macrx_abort_obss_reception> Upon receiving this
+ abort reason, PHY should stop reception of the current frame
+ and go back into a search mode
+
+ <enum 2 macrx_abort_other>
+
+ <enum 3 macrx_abort_sw_initiated_channel_switch > MAC FW
+ issued an abort for channel switch reasons
+
+ <enum 4 macrx_abort_sw_initiated_power_save > MAC FW
+ issued an abort power save reasons
+
+ <enum 5 macrx_abort_too_much_bad_data > RXPCU is
+ terminating the current ongoing reception, as the data that
+ MAC is receiving seems to be all garbage... The PER is too
+ high, or in case of MU UL, Likely the trigger frame never
+ got properly received by any of the targeted MU UL devices.
+ After the abort, PHYRX can resume a normal search mode.
+
+
+
+ <legal 0-5>
+*/
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff
+
+/* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0
+
+ <legal 0>
+*/
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8
+#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00
+
+/* Description RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER
+
+ Field used by SW to double check that their structure
+ alignment is in sync with what HW has done.
+
+ <legal 0xAABBCCDD>
+*/
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0
+#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff
+
+
+#endif // _RXPCU_PPDU_END_INFO_H_
diff --git a/hw/qca5018/rxpt_classify_info.h b/hw/qca5018/rxpt_classify_info.h
new file mode 100644
index 0000000..fb85574
--- /dev/null
+++ b/hw/qca5018/rxpt_classify_info.h
@@ -0,0 +1,515 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 reo_destination_indication[4:0], lmac_peer_id_msb[6:5], use_flow_id_toeplitz_clfy[7], pkt_selection_fp_ucast_data[8], pkt_selection_fp_mcast_data[9], pkt_selection_fp_1000[10], rxdma0_source_ring_selection[12:11], rxdma0_destination_ring_selection[14:13], reserved_0b[31:15]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+ uint32_t reo_destination_indication : 5, //[4:0]
+ lmac_peer_id_msb : 2, //[6:5]
+ use_flow_id_toeplitz_clfy : 1, //[7]
+ pkt_selection_fp_ucast_data : 1, //[8]
+ pkt_selection_fp_mcast_data : 1, //[9]
+ pkt_selection_fp_1000 : 1, //[10]
+ rxdma0_source_ring_selection : 2, //[12:11]
+ rxdma0_destination_ring_selection: 2, //[14:13]
+ reserved_0b : 17; //[31:15]
+};
+
+/*
+
+reo_destination_indication
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+
+lmac_peer_id_msb
+
+ If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb
+ is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1,
+ hash[3:0]} using the chosen Toeplitz hash from Common Parser
+ if flow search fails.
+
+ If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb
+ 's not 2'b00, Rx OLE uses a REO desination indication of
+ {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash
+ from Common Parser if flow search fails.
+
+ This LMAC/peer-based routing is not supported in
+ Hastings80 and HastingsPrime.
+
+ <legal all>
+
+use_flow_id_toeplitz_clfy
+
+ Indication to Rx OLE to enable REO destination routing
+ based on the chosen Toeplitz hash from Common Parser, in
+ case flow search fails
+
+ <legal all>
+
+pkt_selection_fp_ucast_data
+
+ Filter pass Unicast data frame (matching
+ rxpcu_filter_pass and sw_frame_group_Unicast_data) routing
+ selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+
+pkt_selection_fp_mcast_data
+
+ Filter pass Multicast data frame (matching
+ rxpcu_filter_pass and sw_frame_group_Multicast_data) routing
+ selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+
+pkt_selection_fp_1000
+
+ Filter pass BAR frame (matching rxpcu_filter_pass and
+ sw_frame_group_ctrl_1000) routing selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+
+rxdma0_source_ring_selection
+
+ Field only valid when for the received frame type the
+ corresponding pkt_selection_fp_... bit is set
+
+
+
+ <enum 0 wbm2rxdma_buf_source_ring> The data buffer for
+
+ <enum 1 fw2rxdma_buf_source_ring> The data buffer for
+ this frame shall be sourced by fw2rxdma buffer source ring.
+
+ <enum 2 sw2rxdma_buf_source_ring> The data buffer for
+ this frame shall be sourced by sw2rxdma buffer source ring.
+
+ <enum 3 no_buffer_ring> The frame shall not be written
+ to any data buffer.
+
+
+
+ <legal all>
+
+rxdma0_destination_ring_selection
+
+ Field only valid when for the received frame type the
+ corresponding pkt_selection_fp_... bit is set
+
+
+
+ <enum 0 rxdma_release_ring> RXDMA0 shall push the frame
+ to the Release ring. Effectively this means the frame needs
+ to be dropped.
+
+ <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to
+ the FW ring.
+
+ <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to
+ the SW ring.
+
+ <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to
+ the REO entrance ring.
+
+
+
+ <legal all>
+
+reserved_0b
+
+ <legal 0>
+*/
+
+
+/* Description RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f
+
+/* Description RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB
+
+ If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb
+ is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1,
+ hash[3:0]} using the chosen Toeplitz hash from Common Parser
+ if flow search fails.
+
+ If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb
+ 's not 2'b00, Rx OLE uses a REO desination indication of
+ {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash
+ from Common Parser if flow search fails.
+
+ This LMAC/peer-based routing is not supported in
+ Hastings80 and HastingsPrime.
+
+ <legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB 5
+#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK 0x00000060
+
+/* Description RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY
+
+ Indication to Rx OLE to enable REO destination routing
+ based on the chosen Toeplitz hash from Common Parser, in
+ case flow search fails
+
+ <legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080
+
+/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA
+
+ Filter pass Unicast data frame (matching
+ rxpcu_filter_pass and sw_frame_group_Unicast_data) routing
+ selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_LSB 8
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100
+
+/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA
+
+ Filter pass Multicast data frame (matching
+ rxpcu_filter_pass and sw_frame_group_Multicast_data) routing
+ selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_LSB 9
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200
+
+/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000
+
+ Filter pass BAR frame (matching rxpcu_filter_pass and
+ sw_frame_group_ctrl_1000) routing selection
+
+
+
+ 1'b0: source and destination rings are selected from the
+ RxOLE register settings for the packet type
+
+
+
+ 1'b1: source ring and destination ring is selected from
+ the rxdma0_source_ring_selection and
+ rxdma0_destination_ring_selection fields in this STRUCT
+
+ <legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_LSB 10
+#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_MASK 0x00000400
+
+/* Description RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION
+
+ Field only valid when for the received frame type the
+ corresponding pkt_selection_fp_... bit is set
+
+
+
+ <enum 0 wbm2rxdma_buf_source_ring> The data buffer for
+
+ <enum 1 fw2rxdma_buf_source_ring> The data buffer for
+ this frame shall be sourced by fw2rxdma buffer source ring.
+
+ <enum 2 sw2rxdma_buf_source_ring> The data buffer for
+ this frame shall be sourced by sw2rxdma buffer source ring.
+
+ <enum 3 no_buffer_ring> The frame shall not be written
+ to any data buffer.
+
+
+
+ <legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_LSB 11
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800
+
+/* Description RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION
+
+ Field only valid when for the received frame type the
+ corresponding pkt_selection_fp_... bit is set
+
+
+
+ <enum 0 rxdma_release_ring> RXDMA0 shall push the frame
+ to the Release ring. Effectively this means the frame needs
+ to be dropped.
+
+ <enum 1 rxdma2fw_ring> RXDMA0 shall push the frame to
+ the FW ring.
+
+ <enum 2 rxdma2sw_ring> RXDMA0 shall push the frame to
+ the SW ring.
+
+ <enum 3 rxdma2reo_ring> RXDMA0 shall push the frame to
+ the REO entrance ring.
+
+
+
+ <legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_LSB 13
+#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000
+
+/* Description RXPT_CLASSIFY_INFO_0_RESERVED_0B
+
+ <legal 0>
+*/
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_OFFSET 0x00000000
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_LSB 15
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_MASK 0xffff8000
+
+
+#endif // _RXPT_CLASSIFY_INFO_H_
diff --git a/hw/qca5018/seq_hwio.h b/hw/qca5018/seq_hwio.h
new file mode 100644
index 0000000..636caef
--- /dev/null
+++ b/hw/qca5018/seq_hwio.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*********************************************************************************
+ *
+ * DESCRIPTION
+ * - This is an extension of standard msmhwio.h to support relative addressing
+ * scheme used in SCALe auto-generated sequences.
+ * - The objective of this new addressing scheme is enable the same C function
+ * definition to be applicable to multiple baseances of the same block.
+ * - Such code reuse is not feasible with the standard HWIO macros that use a
+ * absolute addressing scheme.
+ * - Compared to the standard HWIO macros, the new macros defined here take an
+ * additional parameter 'baseance offset'. So are the C functions generated
+ * by SCALe Autoseq from .seq inputs.
+ * - As such, macros defined in this file must be used with 'seq_msmhwiobase.h',
+ * 'seq_msmhwioreg.h', and the C codes generated from SCALe Autoseq.
+ * - Macros defined in this file leverage the lower-level macros from the
+ * standard 'msmhwio.h', and the two sets of macros are compatible.
+ *
+ ********************************************************************************/
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+
+
+/**** Register Ref Read ****/
+#define SEQ_INH(base, regtype, reg) \
+ SEQ_##regtype##_INH(base, reg)
+
+/**** Masked Register Read ****/
+#define SEQ_INMH(base, regtype, reg, mask) \
+ SEQ_##regtype##_INMH(base, reg, mask)
+
+
+/**** Ref Reg Field Read ****/
+#define SEQ_INFH(base, regtype, reg, fld) \
+ (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+
+/**** Ref Register Write ****/
+#define SEQ_OUTH(base, regtype, reg, val) \
+ SEQ_##regtype##_OUTH(base, reg, val)
+
+/**** Ref Register Masked Write ****/
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+ SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+
+/**** Ref Register Field Write ****/
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+ SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+
+/**** seq_msg() ****
+
+typedef enum {
+ DEBUG,
+ INFO,
+ WARNING,
+ ERROR,
+ FATAL
+} SeverityLevel ;
+
+void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... );
+
+*/
+
+/************ seq_wait() ************/
+
+typedef enum {
+ SEC,
+ MS,
+ US,
+ NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+
+/************ seq_poll() ************/
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif /* __SEQ_H__ */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/qca5018/sw_xml_headers.h b/hw/qca5018/sw_xml_headers.h
new file mode 100644
index 0000000..ad5f690
--- /dev/null
+++ b/hw/qca5018/sw_xml_headers.h
@@ -0,0 +1,401 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _SW_XML_HEADERS_H_
+#define _SW_XML_HEADERS_H_
+
+
+#include "ack_report.h"
+#include "addr_search_entry.h"
+#include "buffer_addr_info.h"
+#include "cce_rule.h"
+#include "ce_dst_desc.h"
+#include "ce_src_desc.h"
+#include "ce_stat_desc.h"
+#include "he_sig_a_mu_dl_info.h"
+#include "he_sig_a_mu_ul_info.h"
+#include "he_sig_a_su_info.h"
+#include "he_sig_b1_mu_info.h"
+#include "he_sig_b2_mu_info.h"
+#include "he_sig_b2_ofdma_info.h"
+#include "ht_sig_info.h"
+#include "l_sig_a_info.h"
+#include "l_sig_b_info.h"
+#include "mactx_abort_request_info.h"
+#include "mactx_prefetch_cv_bulk_user.h"
+#include "mimo_control_info.h"
+#include "mimo_control_info_l1.h"
+#include "no_ack_report.h"
+#include "pcu_ppdu_setup_end_info.h"
+#include "pdg_response_rate_setting.h"
+#include "peer_table_entry.h"
+#include "phyrx_abort_request_info.h"
+#include "phyrx_pkt_end_info.h"
+#include "ppdu_rate_setting.h"
+#include "prot_rate_setting.h"
+#include "receive_rssi_info.h"
+#include "receive_user_info.h"
+#include "receive_user_info_l1.h"
+#include "received_response_user_info.h"
+#include "received_trigger_info_details.h"
+#include "reo_destination_ring.h"
+#include "reo_entrance_ring.h"
+#include "reo_to_ppe_ring.h"
+#include "response_rate_setting.h"
+#include "rx_flow_search_entry.h"
+#include "rx_location_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "rx_mpdu_details.h"
+#include "rx_mpdu_info.h"
+#include "rx_mpdu_link.h"
+#include "rx_mpdu_link_ptr.h"
+#include "rx_msdu_desc_info.h"
+#include "rx_msdu_details.h"
+#include "rx_msdu_link.h"
+#include "rx_peer_entry_details.h"
+#include "rx_reo_queue.h"
+#include "rx_reo_queue_ext.h"
+#include "rx_reo_queue_reference.h"
+#include "rx_rxpcu_classification_overview.h"
+#include "rx_timing_offset_info.h"
+#include "rxole_cce_classify_info.h"
+#include "rxole_cce_info.h"
+#include "rxole_cce_superrule.h"
+#include "rxpt_classify_info.h"
+#include "scheduler_cmd.h"
+#include "service_info.h"
+#include "sw_monitor_ring.h"
+#include "sw_peer_info.h"
+#include "tcl_cce_classify_info.h"
+#include "tcl_cce_info.h"
+#include "tcl_cce_superrule.h"
+#include "tcl_compact_exit_ring.h"
+#include "tcl_entrance_from_ppe_ring.h"
+#include "tcl_exit_base.h"
+#include "tcl_extended_exit_ring.h"
+#include "tcl_regular_exit_ring.h"
+#include "tcl_status_ring.h"
+#include "tqm_entrance_ring.h"
+#include "tx_flow_search_entry.h"
+#include "tx_mpdu_details.h"
+#include "tx_mpdu_link.h"
+#include "tx_mpdu_link_ptr.h"
+#include "tx_mpdu_queue_ext.h"
+#include "tx_mpdu_queue_ext_ptr.h"
+#include "tx_mpdu_queue_head.h"
+#include "tx_msdu_details.h"
+#include "tx_msdu_extension.h"
+#include "tx_msdu_flow.h"
+#include "tx_msdu_link.h"
+#include "tx_msdu_link_entry_ptr.h"
+#include "tx_puncture_pattern.h"
+#include "tx_rate_stats_info.h"
+#include "txpcu_buffer_basics.h"
+#include "txpt_classify_info.h"
+#include "uniform_descriptor_header.h"
+#include "uniform_reo_cmd_header.h"
+#include "uniform_reo_status_header.h"
+#include "uniform_tqm_cmd_header.h"
+#include "uniform_tqm_status_header.h"
+#include "uplink_common_info.h"
+#include "uplink_common_info_punc.h"
+#include "uplink_user_setup_info.h"
+#include "user_rate_setting.h"
+#include "vht_sig_a_info.h"
+#include "vht_sig_b_mu160_info.h"
+#include "vht_sig_b_mu20_info.h"
+#include "vht_sig_b_mu40_info.h"
+#include "vht_sig_b_mu80_info.h"
+#include "vht_sig_b_su160_info.h"
+#include "vht_sig_b_su20_info.h"
+#include "vht_sig_b_su40_info.h"
+#include "vht_sig_b_su80_info.h"
+#include "wbm_buffer_ring.h"
+#include "wbm_link_descriptor_ring.h"
+#include "wbm_release_ring.h"
+#include "who_classify_info.h"
+#include "macrx_abort_request_info.h"
+#include "phytx_abort_request_info.h"
+#include "abort_from_phyrx_details.h"
+#include "coex_mac_nap.h"
+#include "coex_rx_status.h"
+#include "coex_status_broadcast.h"
+#include "coex_tx_req.h"
+#include "coex_tx_resp.h"
+#include "coex_tx_status.h"
+#include "coex_tx_stop_ctrl.h"
+#include "crypto_status.h"
+#include "expected_response.h"
+#include "hwsch_rxpcu_mac_info_announcement.h"
+#include "mactx_abort_request.h"
+#include "mactx_bf_params_common.h"
+#include "mactx_coex_phy_ctrl.h"
+#include "mactx_delete_cv.h"
+#include "mactx_expect_cbf_common.h"
+#include "mactx_he_sig_a_mu_dl.h"
+#include "mactx_he_sig_a_mu_ul.h"
+#include "mactx_he_sig_a_su.h"
+#include "mactx_he_sig_b1_mu.h"
+#include "mactx_ht_sig.h"
+#include "mactx_l_sig_a.h"
+#include "mactx_l_sig_b.h"
+#include "mactx_mu_uplink_common.h"
+#include "mactx_mu_uplink_common_punc.h"
+#include "mactx_other_transmit_info_dl_ofdma_tx.h"
+#include "mactx_other_transmit_info_emuphy_setup.h"
+#include "mactx_other_transmit_info_sch_details.h"
+#include "mactx_phy_desc.h"
+#include "mactx_phy_nap.h"
+#include "mactx_pre_phy_desc.h"
+#include "mactx_prefetch_cv.h"
+#include "mactx_prefetch_cv_bulk.h"
+#include "mactx_prefetch_cv_common.h"
+#include "mactx_user_desc_common.h"
+#include "mactx_vht_sig_a.h"
+#include "mactx_vht_sig_b_su160.h"
+#include "mactx_vht_sig_b_su20.h"
+#include "mactx_vht_sig_b_su40.h"
+#include "mactx_vht_sig_b_su80.h"
+#include "obss_sr_info.h"
+#include "ofdma_trigger_details.h"
+#include "ole_buf_status.h"
+#include "pcu_ppdu_setup_end.h"
+#include "pcu_ppdu_setup_init.h"
+#include "pcu_ppdu_setup_start.h"
+#include "pdg_fes_setup.h"
+#include "pdg_response.h"
+#include "pdg_sw_mode_bw_start.h"
+#include "pdg_tx_req.h"
+#include "pdg_wait_for_mac_request.h"
+#include "pdg_wait_for_phy_request.h"
+#include "phyrx_cbf_read_request_ack.h"
+#include "phyrx_generated_cbf_details.h"
+#include "phyrx_he_sig_a_mu_dl.h"
+#include "phyrx_he_sig_a_mu_ul.h"
+#include "phyrx_he_sig_a_su.h"
+#include "phyrx_he_sig_b1_mu.h"
+#include "phyrx_ht_sig.h"
+#include "phyrx_l_sig_a.h"
+#include "phyrx_l_sig_b.h"
+#include "phyrx_other_receive_info_108p_evm_details.h"
+#include "phyrx_other_receive_info_evm_details.h"
+#include "phyrx_other_receive_info_mu_rssi_common.h"
+#include "phyrx_pkt_end.h"
+#include "phyrx_rssi_ht.h"
+#include "phyrx_rssi_legacy.h"
+#include "phyrx_tx_start_timing.h"
+#include "phyrx_vht_sig_a.h"
+#include "phyrx_vht_sig_b_su160.h"
+#include "phyrx_vht_sig_b_su20.h"
+#include "phyrx_vht_sig_b_su40.h"
+#include "phyrx_vht_sig_b_su80.h"
+#include "received_response_info.h"
+#include "received_response_info_part2.h"
+#include "received_response_user_15_8.h"
+#include "received_response_user_23_16.h"
+#include "received_response_user_31_24.h"
+#include "received_response_user_36_32.h"
+#include "received_response_user_7_0.h"
+#include "received_trigger_info.h"
+#include "reo_descriptor_threshold_reached_status.h"
+#include "reo_flush_cache.h"
+#include "reo_flush_cache_status.h"
+#include "reo_flush_queue.h"
+#include "reo_flush_queue_status.h"
+#include "reo_flush_timeout_list.h"
+#include "reo_flush_timeout_list_status.h"
+#include "reo_get_queue_stats.h"
+#include "reo_get_queue_stats_status.h"
+#include "reo_unblock_cache.h"
+#include "reo_unblock_cache_status.h"
+#include "reo_update_rx_reo_queue.h"
+#include "reo_update_rx_reo_queue_status.h"
+#include "response_end_status.h"
+#include "response_start_status.h"
+#include "rx_frame_bitmap_req.h"
+#include "rx_pm_info.h"
+#include "rx_ppdu_ack_report.h"
+#include "rx_ppdu_end_status_done.h"
+#include "rx_ppdu_no_ack_report.h"
+#include "rx_ppdu_start.h"
+#include "rx_preamble.h"
+#include "rx_response_required_info.h"
+#include "rx_ring_mask.h"
+#include "rx_start_param.h"
+#include "rx_trig_info.h"
+#include "rxpcu_ppdu_end_info.h"
+#include "rxpcu_setup.h"
+#include "sch_coex_status.h"
+#include "sch_wait_instr.h"
+#include "sch_wait_instr_tx_path.h"
+#include "scheduler_command_status.h"
+#include "scheduler_rx_ppdu_no_response_status.h"
+#include "scheduler_rx_sifs_response_trigger_status.h"
+#include "scheduler_selfgen_response_status.h"
+#include "scheduler_sw_msg_status.h"
+#include "snoop_ppdu_end.h"
+#include "snoop_ppdu_start.h"
+#include "srp_info.h"
+#include "tcl_data_cmd.h"
+#include "tcl_gse_cmd.h"
+#include "tqm_2_sch_mpdu_available.h"
+#include "tqm_acked_mpdu_status.h"
+#include "tqm_add_msdu_status.h"
+#include "tqm_descriptor_threshold_reached_status.h"
+#include "tqm_flow_empty_status.h"
+#include "tqm_flow_not_empty_status.h"
+#include "tqm_flush_cache.h"
+#include "tqm_flush_cache_status.h"
+#include "tqm_gen_mpdu_length_list.h"
+#include "tqm_gen_mpdu_length_list_status.h"
+#include "tqm_gen_mpdus.h"
+#include "tqm_gen_mpdus_status.h"
+#include "tqm_get_mpdu_head_info.h"
+#include "tqm_get_mpdu_head_info_status.h"
+#include "tqm_get_mpdu_queue_stats.h"
+#include "tqm_get_mpdu_queue_stats_status.h"
+#include "tqm_get_msdu_flow_stats.h"
+#include "tqm_get_msdu_flow_stats_status.h"
+#include "tqm_mpdu_queue_empty_status.h"
+#include "tqm_remove_mpdu.h"
+#include "tqm_remove_mpdu_status.h"
+#include "tqm_remove_msdu.h"
+#include "tqm_remove_msdu_status.h"
+#include "tqm_sync_cmd.h"
+#include "tqm_sync_cmd_status.h"
+#include "tqm_threshold_drop_notification_status.h"
+#include "tqm_unblock_cache.h"
+#include "tqm_unblock_cache_status.h"
+#include "tqm_update_tx_mpdu_count_status.h"
+#include "tqm_update_tx_mpdu_queue_head.h"
+#include "tqm_update_tx_mpdu_queue_head_status.h"
+#include "tqm_update_tx_msdu_flow.h"
+#include "tqm_update_tx_msdu_flow_status.h"
+#include "tqm_write_cmd.h"
+#include "tqm_write_cmd_status.h"
+#include "tx_cbf_info.h"
+#include "tx_data_sync.h"
+#include "tx_fes_setup.h"
+#include "tx_fes_status_end.h"
+#include "tx_fes_status_prot.h"
+#include "tx_fes_status_start.h"
+#include "tx_fes_status_start_ppdu.h"
+#include "tx_fes_status_start_prot.h"
+#include "tx_flush_req.h"
+#include "tx_loopback_setup.h"
+#include "tx_puncture_setup.h"
+#include "tx_sw_mode_setup.h"
+#include "txpcu_buffer_status.h"
+#include "who_terminate.h"
+#include "data_to_time_config.h"
+#include "mactx_bf_params_per_user.h"
+#include "mactx_expect_cbf_per_user.h"
+#include "mactx_he_sig_b2_mu.h"
+#include "mactx_he_sig_b2_ofdma.h"
+#include "mactx_mu_uplink_user_setup.h"
+#include "mactx_mu_uplink_user_setup_punc.h"
+#include "mactx_service.h"
+#include "mactx_user_desc_per_user.h"
+#include "mactx_vht_sig_b_mu160.h"
+#include "mactx_vht_sig_b_mu20.h"
+#include "mactx_vht_sig_b_mu40.h"
+#include "mactx_vht_sig_b_mu80.h"
+#include "mpdu_info.h"
+#include "mpdu_info_bitmap.h"
+#include "mpdu_limit.h"
+#include "pcu_ppdu_setup_user.h"
+#include "pdg_user_setup.h"
+#include "phyrx_common_user_info.h"
+#include "phyrx_he_sig_b2_mu.h"
+#include "phyrx_he_sig_b2_ofdma.h"
+#include "phyrx_other_receive_info_mu_rssi_user.h"
+#include "phyrx_other_receive_info_ru_details.h"
+#include "phyrx_user_info.h"
+#include "phyrx_vht_sig_b_mu160.h"
+#include "phyrx_vht_sig_b_mu20.h"
+#include "phyrx_vht_sig_b_mu40.h"
+#include "phyrx_vht_sig_b_mu80.h"
+#include "rx_attention.h"
+#include "rx_frame_bitmap_ack.h"
+#include "rx_frameless_bar_details.h"
+#include "rx_header.h"
+#include "rx_mpdu_end.h"
+#include "rx_mpdu_pcu_start.h"
+#include "rx_mpdu_start.h"
+#include "rx_msdu_end.h"
+#include "rx_msdu_start.h"
+#include "rx_peer_entry.h"
+#include "rx_ppdu_end_user_stats.h"
+#include "rx_ppdu_end_user_stats_ext.h"
+#include "rx_ppdu_start_user_info.h"
+#include "rxpcu_user_setup.h"
+#include "rxpcu_user_setup_ext.h"
+#include "snoop_mpdu_usr_dbg_info.h"
+#include "snoop_mpdu_usr_stat_info.h"
+#include "snoop_msdu_usr_dbg_info.h"
+#include "tqm_acked_mpdu.h"
+#include "tqm_update_tx_mpdu_count.h"
+#include "tx_11ah_setup.h"
+#include "tx_fes_status_ack_or_ba.h"
+#include "tx_fes_status_user_ppdu.h"
+#include "tx_fes_status_user_response.h"
+#include "tx_mpdu_start.h"
+#include "tx_msdu_start.h"
+#include "tx_peer_entry.h"
+#include "tx_queue_extension.h"
+#include "tx_raw_or_native_frame_setup.h"
+#include "txpcu_user_buffer_status.h"
+#include "txpcu_user_setup.h"
+#include "who_anchor_value.h"
+#include "who_cce_info.h"
+#include "who_commit_done.h"
+#include "who_l2_llc.h"
+#include "who_l3_checksum.h"
+#include "who_l3_info.h"
+#include "who_l4_checksum.h"
+#include "who_l4_info.h"
+#include "who_mesh_control.h"
+#include "who_msdu_misc.h"
+#include "who_packet_hdr.h"
+#include "who_tso.h"
+#include "who_wmac_header_pv0.h"
+#include "who_wmac_header_pv1.h"
+#include "who_wmac_iv.h"
+#include "tlv_tag_def.h"
+#include "mactx_cbf_data.h"
+#include "mactx_cbf_done.h"
+#include "mactx_cbf_start.h"
+#include "mactx_data_resp.h"
+#include "phyrx_abort_request.h"
+#include "phyrx_cbf_data_resp.h"
+#include "phyrx_data.h"
+#include "phyrx_user_abort_notification.h"
+#include "macrx_abort_request.h"
+#include "macrx_cbf_data_request.h"
+#include "macrx_cbf_read_request.h"
+#include "macrx_chain_mask.h"
+#include "macrx_expect_ndp_reception.h"
+#include "macrx_freeze_capture_channel.h"
+#include "macrx_req_implicit_fb.h"
+#include "phytx_abort_request.h"
+#include "phytx_bf_cv_loading_done.h"
+#include "phytx_nap_ack.h"
+#include "phytx_pkt_end.h"
+#include "phytx_ppdu_header_info_request.h"
+#include "phytx_request_ctrl_info.h"
+
+
+#endif
diff --git a/hw/qca5018/tcl_data_cmd.h b/hw/qca5018/tcl_data_cmd.h
new file mode 100644
index 0000000..ccd657d
--- /dev/null
+++ b/hw/qca5018/tcl_data_cmd.h
@@ -0,0 +1,1264 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _TCL_DATA_CMD_H_
+#define _TCL_DATA_CMD_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct buffer_addr_info buf_addr_info;
+// 2 buf_or_ext_desc_type[0], epd[1], encap_type[3:2], encrypt_type[7:4], src_buffer_swap[8], link_meta_swap[9], tqm_no_drop[10], reserved_2a[11], search_type[13:12], addrx_en[14], addry_en[15], tcl_cmd_number[31:16]
+// 3 data_length[15:0], ipv4_checksum_en[16], udp_over_ipv4_checksum_en[17], udp_over_ipv6_checksum_en[18], tcp_over_ipv4_checksum_en[19], tcp_over_ipv6_checksum_en[20], to_fw[21], reserved_3a[22], packet_offset[31:23]
+// 4 buffer_timestamp[18:0], buffer_timestamp_valid[19], reserved_4a[20], hlos_tid_overwrite[21], hlos_tid[25:22], lmac_id[27:26], udp_flow_override[29:28], reserved_4b[31:30]
+// 5 dscp_tid_table_num[5:0], search_index[25:6], cache_set_num[29:26], mesh_enable[31:30]
+// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TCL_DATA_CMD 7
+
+struct tcl_data_cmd {
+ struct buffer_addr_info buf_addr_info;
+ uint32_t buf_or_ext_desc_type : 1, //[0]
+ epd : 1, //[1]
+ encap_type : 2, //[3:2]
+ encrypt_type : 4, //[7:4]
+ src_buffer_swap : 1, //[8]
+ link_meta_swap : 1, //[9]
+ tqm_no_drop : 1, //[10]
+ reserved_2a : 1, //[11]
+ search_type : 2, //[13:12]
+ addrx_en : 1, //[14]
+ addry_en : 1, //[15]
+ tcl_cmd_number : 16; //[31:16]
+ uint32_t data_length : 16, //[15:0]
+ ipv4_checksum_en : 1, //[16]
+ udp_over_ipv4_checksum_en : 1, //[17]
+ udp_over_ipv6_checksum_en : 1, //[18]
+ tcp_over_ipv4_checksum_en : 1, //[19]
+ tcp_over_ipv6_checksum_en : 1, //[20]
+ to_fw : 1, //[21]
+ reserved_3a : 1, //[22]
+ packet_offset : 9; //[31:23]
+ uint32_t buffer_timestamp : 19, //[18:0]
+ buffer_timestamp_valid : 1, //[19]
+ reserved_4a : 1, //[20]
+ hlos_tid_overwrite : 1, //[21]
+ hlos_tid : 4, //[25:22]
+ lmac_id : 2, //[27:26]
+ udp_flow_override : 2, //[29:28]
+ reserved_4b : 2; //[31:30]
+ uint32_t dscp_tid_table_num : 6, //[5:0]
+ search_index : 20, //[25:6]
+ cache_set_num : 4, //[29:26]
+ mesh_enable : 2; //[31:30]
+ uint32_t reserved_6a : 20, //[19:0]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct buffer_addr_info buf_addr_info
+
+ Details of the physical address for a single buffer
+
+ It also contains return ownership info as well as some
+ meta data for SW related to this buffer.
+
+
+
+ In case of Buf_or_ext_desc_type indicating
+ 'MSDU_buffer', this address indicates the start of the meta
+ data that is preceding the actual packet data.
+
+ The start of the actual packet data is provided by
+ field: Packet_offset
+
+buf_or_ext_desc_type
+
+ <enum 0 MSDU_buffer> The address points to an MSDU
+ buffer.
+
+ <enum 1 extension_descriptor> The address points to an
+ MSDU link extension descriptor
+
+ < legal all>
+
+epd
+
+ When this bit is set then input packet is an EPD type
+
+ <legal all>
+
+encap_type
+
+ Indicates the encapsulation that HW will perform:
+
+ <enum 0 RAW> No encapsulation
+
+ <enum 1 Native_WiFi>
+
+ <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses
+ SNAP/LLC)
+
+ <enum 3 802_3> DO NOT USE. Indicate Ethernet
+
+
+
+ Used by the OLE during encapsulation.
+
+ <legal all>
+
+encrypt_type
+
+ Field only valid for encap_type: RAW
+
+
+
+ Indicates type of decrypt cipher used (as defined in the
+ peer entry)
+
+ <enum 0 wep_40> WEP 40-bit
+
+ <enum 1 wep_104> WEP 104-bit
+
+ <enum 2 tkip_no_mic> TKIP without MIC
+
+ <enum 3 wep_128> WEP 128-bit
+
+ <enum 4 tkip_with_mic> TKIP with MIC
+
+ <enum 5 wapi> WAPI
+
+ <enum 6 aes_ccmp_128> AES CCMP 128
+
+ <enum 7 no_cipher> No crypto
+
+ <enum 8 aes_ccmp_256> AES CCMP 256
+
+ <enum 9 aes_gcmp_128> AES CCMP 128
+
+ <enum 10 aes_gcmp_256> AES CCMP 256
+
+ <enum 11 wapi_gcm_sm4> WAPI GCM SM4
+
+
+
+ <enum 12 wep_varied_width> DO not use... Only for higher
+ layer modules..
+
+ <legal 0-12>
+
+src_buffer_swap
+
+ Treats source memory (packet buffer) organization as
+ big-endian. The packets are read and byte swapped.
+
+ 1'b0: Source memory is little endian
+
+ 1'b1: Source memory is big endian
+
+ <legal all>
+
+link_meta_swap
+
+ Treats link descriptor and Metadata as big-endian. The
+ link descriptor/Metadata is read and byte swapped.
+
+ 1'b0: Memory is little endian
+
+ 1'b1: Memory is big endian
+
+ <legal all>
+
+tqm_no_drop
+
+ This bit is used to stop TQM from dropping MSDUs while
+ adding them to MSDU flows1'b1: Do not drop MSDU when any of
+ the threshold value is met while adding MSDU in a flow1'b1:
+ Drop MSDU when any of the threshold value is met while
+ adding MSDU in a flow
+
+ <legal all>
+
+reserved_2a
+
+ <legal 0>
+
+search_type
+
+ Search type select
+
+
+
+ <enum 0 Normal_search> Address and flow search will use
+ packet contents
+
+ <enum 1 Index_based_address_search> Address search will
+
+ <enum 2 Index_based_flow_search> Flow search will use
+ 'search_index', and address search will use packet contents
+
+ <legal 0-2>
+
+addrx_en
+
+ Address X search enable in ASE
+
+ 1'b0: Search disable
+
+ 1'b1: Search Enable
+
+ <legal all>
+
+addry_en
+
+ Address Y search enable in ASE
+
+ 1'b0: Search disable
+
+ 1'b1: Search Enable
+
+ <legal all>
+
+tcl_cmd_number
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statuses
+
+
+
+ Is set to the value 'TCL_CMD_Number' of the related
+ TCL_DATA command
+
+ <legal all>
+
+data_length
+
+ Valid Data length in bytes.
+
+
+
+ MSDU length in case of direct descriptor.
+
+ Length of link extension descriptor in case of Link
+ extension descriptor. This is used to know the size of
+ Metadata.
+
+ <legal all>
+
+ipv4_checksum_en
+
+ OLE related control
+
+ Enable IPv4 checksum replacement
+
+udp_over_ipv4_checksum_en
+
+ OLE related control
+
+ Enable UDP over IPv4 checksum replacement. UDP checksum
+ over IPv4 is optional for TCP/IP stacks.
+
+udp_over_ipv6_checksum_en
+
+ OLE related control
+
+ Enable UDP over IPv6 checksum replacement. UDP checksum
+ over IPv6 is mandatory for TCP/IP stacks.
+
+tcp_over_ipv4_checksum_en
+
+ OLE related control
+
+ Enable TCP checksum over IPv4 replacement
+
+tcp_over_ipv6_checksum_en
+
+ OLE related control
+
+ Enable TCP checksum over IPv6 replacement
+
+to_fw
+
+ Forward packet to FW along with classification result.
+ The packet will not be forward to TQM when this bit is set
+
+
+
+ 1'b0: Use classification result to forward the packet.
+
+ 1'b1: Override classification result and forward packet
+ only to FW.
+
+ <legal all>
+
+reserved_3a
+
+ <legal 0>
+
+packet_offset
+
+ Packet offset from Metadata in case of direct buffer
+ descriptor. This field is valid when Buf_or_ext_desc_type is
+ reset(= 0).
+
+ <legal all>
+
+buffer_timestamp
+
+ Field only valid when 'Buffer_timestamp_valid ' is set.
+
+
+
+ Frame system entrance timestamp. The timestamp is
+ related to the global system timer
+
+
+
+ Generally the first module (SW, TCL or TQM). that sees
+ this frame and this timestamp field is not valid, shall fill
+ in this field.
+
+
+
+ Timestamp in units of 1024 us
+
+buffer_timestamp_valid
+
+ When set, the Buffer_timestamp field contains valid
+ info.
+
+reserved_4a
+
+ <legal 0>
+
+hlos_tid_overwrite
+
+ When set, TCL shall ignore the IP DSCP and VLAN PCP
+ fields and use HLOS_TID as the final TID. Otherwise TCL
+ shall consider the DSCP and PCP fields as well as HLOS_TID
+ and choose a final TID based on the configured priority
+
+ <legal all>
+
+hlos_tid
+
+ HLOS MSDU priority
+
+
+
+ Field is used when HLOS_TID_overwrite is set.
+
+
+
+ Field is also used when HLOS_TID_overwrite is not set
+ and DSCP/PCP is not available in the packet
+
+ <legal all>
+
+lmac_id
+
+ TCL uses this LMAC_ID in address search, i.e, while
+ finding matching entry for the packet in AST corresponding
+ to given LMAC_ID
+
+ If LMAC ID is all 1s (=> value 3), it indicates wildcard
+ match for any MAC
+
+ <legal 0-3>
+
+udp_flow_override
+
+ TCL uses this to select the flow pointer from the peer
+ table, which can be overridden by SW for pre-encrypted raw
+ WiFi packets that cannot be parsed for UDP or for other
+ enterprise use cases:
+
+ <enum 0 FP_PARSE_IP> Use the flow-pointer based on
+ parsing the IPv4 or IPv6 header
+
+ <enum 1 FP_USE_NON_UDP> Use the non-UDP flow pointer
+
+ <enum 2 FP_USE_UDP> Use the UDP flow pointer
+
+
+
+ This is not supported in Moselle.
+
+ <legal 0-2>
+
+reserved_4b
+
+ <legal 0>
+
+dscp_tid_table_num
+
+ DSCP to TID mapping table number that need to be used
+ for the MSDU, should be specified using this field
+
+ <legal all>
+
+search_index
+
+ The index that will be used for index based address or
+ flow search. The field is valid when 'search_type' is 1 or
+ 2.
+
+ <legal all>
+
+cache_set_num
+
+ Cache set number that should be used to cache the index
+ based search results, for address and flow search. This
+ value should be equal to LSB four bits of the hash value of
+ match data, in case of search index points to an entry which
+ may be used in content based search also. The value can be
+ anything when the entry pointed by search index will not be
+ used for content based search.
+
+ <legal all>
+
+mesh_enable
+
+ If set to a non-zero value:
+
+ * For raw WiFi frames, this indicates transmission to a
+ mesh STA, enabling the interpretation of the 'Mesh Control
+ Present' bit (bit 8) of QoS Control (otherwise this bit is
+ ignored). The interpretation of the A-MSDU 'Length' field is
+ decided by the e-numerations below.
+
+ * For native WiFi frames, this indicates that a 'Mesh
+ Control' field is present between the header and the LLC.
+ The three non-zero values are interchangeable.
+
+
+
+ <enum 0 MESH_DISABLE>
+
+ <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and
+ includes the length of Mesh Control.
+
+ <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and
+ excludes the length of Mesh Control.
+
+ <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian
+ and excludes the length of Mesh Control. This is
+ 802.11s-compliant.
+
+ <legal 0-3>
+
+reserved_6a
+
+ <legal 0>
+
+ring_id
+
+ The buffer pointer ring ID.
+
+ 0 refers to the IDLE ring
+
+ 1 - N refers to other rings
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buf_addr_info */
+
+
+/* Description TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+/* Description TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE
+
+ <enum 0 MSDU_buffer> The address points to an MSDU
+ buffer.
+
+ <enum 1 extension_descriptor> The address points to an
+ MSDU link extension descriptor
+
+ < legal all>
+*/
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001
+
+/* Description TCL_DATA_CMD_2_EPD
+
+ When this bit is set then input packet is an EPD type
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_EPD_LSB 1
+#define TCL_DATA_CMD_2_EPD_MASK 0x00000002
+
+/* Description TCL_DATA_CMD_2_ENCAP_TYPE
+
+ Indicates the encapsulation that HW will perform:
+
+ <enum 0 RAW> No encapsulation
+
+ <enum 1 Native_WiFi>
+
+ <enum 2 Ethernet> Ethernet 2 (DIX) or 802.3 (uses
+ SNAP/LLC)
+
+ <enum 3 802_3> DO NOT USE. Indicate Ethernet
+
+
+
+ Used by the OLE during encapsulation.
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2
+#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c
+
+/* Description TCL_DATA_CMD_2_ENCRYPT_TYPE
+
+ Field only valid for encap_type: RAW
+
+
+
+ Indicates type of decrypt cipher used (as defined in the
+ peer entry)
+
+ <enum 0 wep_40> WEP 40-bit
+
+ <enum 1 wep_104> WEP 104-bit
+
+ <enum 2 tkip_no_mic> TKIP without MIC
+
+ <enum 3 wep_128> WEP 128-bit
+
+ <enum 4 tkip_with_mic> TKIP with MIC
+
+ <enum 5 wapi> WAPI
+
+ <enum 6 aes_ccmp_128> AES CCMP 128
+
+ <enum 7 no_cipher> No crypto
+
+ <enum 8 aes_ccmp_256> AES CCMP 256
+
+ <enum 9 aes_gcmp_128> AES CCMP 128
+
+ <enum 10 aes_gcmp_256> AES CCMP 256
+
+ <enum 11 wapi_gcm_sm4> WAPI GCM SM4
+
+
+
+ <enum 12 wep_varied_width> DO not use... Only for higher
+ layer modules..
+
+ <legal 0-12>
+*/
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0
+
+/* Description TCL_DATA_CMD_2_SRC_BUFFER_SWAP
+
+ Treats source memory (packet buffer) organization as
+ big-endian. The packets are read and byte swapped.
+
+ 1'b0: Source memory is little endian
+
+ 1'b1: Source memory is big endian
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100
+
+/* Description TCL_DATA_CMD_2_LINK_META_SWAP
+
+ Treats link descriptor and Metadata as big-endian. The
+ link descriptor/Metadata is read and byte swapped.
+
+ 1'b0: Memory is little endian
+
+ 1'b1: Memory is big endian
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9
+#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200
+
+/* Description TCL_DATA_CMD_2_TQM_NO_DROP
+
+ This bit is used to stop TQM from dropping MSDUs while
+ adding them to MSDU flows1'b1: Do not drop MSDU when any of
+ the threshold value is met while adding MSDU in a flow1'b1:
+ Drop MSDU when any of the threshold value is met while
+ adding MSDU in a flow
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_2_TQM_NO_DROP_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_TQM_NO_DROP_LSB 10
+#define TCL_DATA_CMD_2_TQM_NO_DROP_MASK 0x00000400
+
+/* Description TCL_DATA_CMD_2_RESERVED_2A
+
+ <legal 0>
+*/
+#define TCL_DATA_CMD_2_RESERVED_2A_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_RESERVED_2A_LSB 11
+#define TCL_DATA_CMD_2_RESERVED_2A_MASK 0x00000800
+
+/* Description TCL_DATA_CMD_2_SEARCH_TYPE
+
+ Search type select
+
+
+
+ <enum 0 Normal_search> Address and flow search will use
+ packet contents
+
+ <enum 1 Index_based_address_search> Address search will
+
+ <enum 2 Index_based_flow_search> Flow search will use
+ 'search_index', and address search will use packet contents
+
+ <legal 0-2>
+*/
+#define TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_SEARCH_TYPE_LSB 12
+#define TCL_DATA_CMD_2_SEARCH_TYPE_MASK 0x00003000
+
+/* Description TCL_DATA_CMD_2_ADDRX_EN
+
+ Address X search enable in ASE
+
+ 1'b0: Search disable
+
+ 1'b1: Search Enable
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14
+#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000
+
+/* Description TCL_DATA_CMD_2_ADDRY_EN
+
+ Address Y search enable in ASE
+
+ 1'b0: Search disable
+
+ 1'b1: Search Enable
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15
+#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000
+
+/* Description TCL_DATA_CMD_2_TCL_CMD_NUMBER
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statuses
+
+
+
+ Is set to the value 'TCL_CMD_Number' of the related
+ TCL_DATA command
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000
+
+/* Description TCL_DATA_CMD_3_DATA_LENGTH
+
+ Valid Data length in bytes.
+
+
+
+ MSDU length in case of direct descriptor.
+
+ Length of link extension descriptor in case of Link
+ extension descriptor. This is used to know the size of
+ Metadata.
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0
+#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff
+
+/* Description TCL_DATA_CMD_3_IPV4_CHECKSUM_EN
+
+ OLE related control
+
+ Enable IPv4 checksum replacement
+*/
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000
+
+/* Description TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN
+
+ OLE related control
+
+ Enable UDP over IPv4 checksum replacement. UDP checksum
+ over IPv4 is optional for TCP/IP stacks.
+*/
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000
+
+/* Description TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN
+
+ OLE related control
+
+ Enable UDP over IPv6 checksum replacement. UDP checksum
+ over IPv6 is mandatory for TCP/IP stacks.
+*/
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000
+
+/* Description TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN
+
+ OLE related control
+
+ Enable TCP checksum over IPv4 replacement
+*/
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000
+
+/* Description TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN
+
+ OLE related control
+
+ Enable TCP checksum over IPv6 replacement
+*/
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000
+
+/* Description TCL_DATA_CMD_3_TO_FW
+
+ Forward packet to FW along with classification result.
+ The packet will not be forward to TQM when this bit is set
+
+
+
+ 1'b0: Use classification result to forward the packet.
+
+ 1'b1: Override classification result and forward packet
+ only to FW.
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_TO_FW_LSB 21
+#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000
+
+/* Description TCL_DATA_CMD_3_RESERVED_3A
+
+ <legal 0>
+*/
+#define TCL_DATA_CMD_3_RESERVED_3A_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_RESERVED_3A_LSB 22
+#define TCL_DATA_CMD_3_RESERVED_3A_MASK 0x00400000
+
+/* Description TCL_DATA_CMD_3_PACKET_OFFSET
+
+ Packet offset from Metadata in case of direct buffer
+ descriptor. This field is valid when Buf_or_ext_desc_type is
+ reset(= 0).
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c
+#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23
+#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000
+
+/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP
+
+ Field only valid when 'Buffer_timestamp_valid ' is set.
+
+
+
+ Frame system entrance timestamp. The timestamp is
+ related to the global system timer
+
+
+
+ Generally the first module (SW, TCL or TQM). that sees
+ this frame and this timestamp field is not valid, shall fill
+ in this field.
+
+
+
+ Timestamp in units of 1024 us
+*/
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff
+
+/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID
+
+ When set, the Buffer_timestamp field contains valid
+ info.
+*/
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000
+
+/* Description TCL_DATA_CMD_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define TCL_DATA_CMD_4_RESERVED_4A_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_RESERVED_4A_LSB 20
+#define TCL_DATA_CMD_4_RESERVED_4A_MASK 0x00100000
+
+/* Description TCL_DATA_CMD_4_HLOS_TID_OVERWRITE
+
+ When set, TCL shall ignore the IP DSCP and VLAN PCP
+ fields and use HLOS_TID as the final TID. Otherwise TCL
+ shall consider the DSCP and PCP fields as well as HLOS_TID
+ and choose a final TID based on the configured priority
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000
+
+/* Description TCL_DATA_CMD_4_HLOS_TID
+
+ HLOS MSDU priority
+
+
+
+ Field is used when HLOS_TID_overwrite is set.
+
+
+
+ Field is also used when HLOS_TID_overwrite is not set
+ and DSCP/PCP is not available in the packet
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_HLOS_TID_LSB 22
+#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000
+
+/* Description TCL_DATA_CMD_4_LMAC_ID
+
+ TCL uses this LMAC_ID in address search, i.e, while
+ finding matching entry for the packet in AST corresponding
+ to given LMAC_ID
+
+ If LMAC ID is all 1s (=> value 3), it indicates wildcard
+ match for any MAC
+
+ <legal 0-3>
+*/
+#define TCL_DATA_CMD_4_LMAC_ID_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_LMAC_ID_LSB 26
+#define TCL_DATA_CMD_4_LMAC_ID_MASK 0x0c000000
+
+/* Description TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE
+
+ TCL uses this to select the flow pointer from the peer
+ table, which can be overridden by SW for pre-encrypted raw
+ WiFi packets that cannot be parsed for UDP or for other
+ enterprise use cases:
+
+ <enum 0 FP_PARSE_IP> Use the flow-pointer based on
+ parsing the IPv4 or IPv6 header
+
+ <enum 1 FP_USE_NON_UDP> Use the non-UDP flow pointer
+
+ <enum 2 FP_USE_UDP> Use the UDP flow pointer
+
+
+
+ This is not supported in Moselle.
+
+ <legal 0-2>
+*/
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_LSB 28
+#define TCL_DATA_CMD_4_UDP_FLOW_OVERRIDE_MASK 0x30000000
+
+/* Description TCL_DATA_CMD_4_RESERVED_4B
+
+ <legal 0>
+*/
+#define TCL_DATA_CMD_4_RESERVED_4B_OFFSET 0x00000010
+#define TCL_DATA_CMD_4_RESERVED_4B_LSB 30
+#define TCL_DATA_CMD_4_RESERVED_4B_MASK 0xc0000000
+
+/* Description TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM
+
+ DSCP to TID mapping table number that need to be used
+ for the MSDU, should be specified using this field
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_OFFSET 0x00000014
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_LSB 0
+#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_MASK 0x0000003f
+
+/* Description TCL_DATA_CMD_5_SEARCH_INDEX
+
+ The index that will be used for index based address or
+ flow search. The field is valid when 'search_type' is 1 or
+ 2.
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 0x00000014
+#define TCL_DATA_CMD_5_SEARCH_INDEX_LSB 6
+#define TCL_DATA_CMD_5_SEARCH_INDEX_MASK 0x03ffffc0
+
+/* Description TCL_DATA_CMD_5_CACHE_SET_NUM
+
+ Cache set number that should be used to cache the index
+ based search results, for address and flow search. This
+ value should be equal to LSB four bits of the hash value of
+ match data, in case of search index points to an entry which
+ may be used in content based search also. The value can be
+ anything when the entry pointed by search index will not be
+ used for content based search.
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 0x00000014
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_LSB 26
+#define TCL_DATA_CMD_5_CACHE_SET_NUM_MASK 0x3c000000
+
+/* Description TCL_DATA_CMD_5_MESH_ENABLE
+
+ If set to a non-zero value:
+
+ * For raw WiFi frames, this indicates transmission to a
+ mesh STA, enabling the interpretation of the 'Mesh Control
+ Present' bit (bit 8) of QoS Control (otherwise this bit is
+ ignored). The interpretation of the A-MSDU 'Length' field is
+ decided by the e-numerations below.
+
+ * For native WiFi frames, this indicates that a 'Mesh
+ Control' field is present between the header and the LLC.
+ The three non-zero values are interchangeable.
+
+
+
+ <enum 0 MESH_DISABLE>
+
+ <enum 1 MESH_Q2Q> A-MSDU 'Length' is big endian and
+ includes the length of Mesh Control.
+
+ <enum 2 MESH_11S_BE> A-MSDU 'Length' is big endian and
+ excludes the length of Mesh Control.
+
+ <enum 3 MESH_11S_LE> A-MSDU 'Length' is little endian
+ and excludes the length of Mesh Control. This is
+ 802.11s-compliant.
+
+ <legal 0-3>
+*/
+#define TCL_DATA_CMD_5_MESH_ENABLE_OFFSET 0x00000014
+#define TCL_DATA_CMD_5_MESH_ENABLE_LSB 30
+#define TCL_DATA_CMD_5_MESH_ENABLE_MASK 0xc0000000
+
+/* Description TCL_DATA_CMD_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018
+#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0
+#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff
+
+/* Description TCL_DATA_CMD_6_RING_ID
+
+ The buffer pointer ring ID.
+
+ 0 refers to the IDLE ring
+
+ 1 - N refers to other rings
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018
+#define TCL_DATA_CMD_6_RING_ID_LSB 20
+#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000
+
+/* Description TCL_DATA_CMD_6_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018
+#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28
+#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _TCL_DATA_CMD_H_
diff --git a/hw/qca5018/tcl_gse_cmd.h b/hw/qca5018/tcl_gse_cmd.h
new file mode 100644
index 0000000..88258f2
--- /dev/null
+++ b/hw/qca5018/tcl_gse_cmd.h
@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _TCL_GSE_CMD_H_
+#define _TCL_GSE_CMD_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 control_buffer_addr_31_0[31:0]
+// 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], index_search_en[15], cache_set_num[19:16], reserved_1a[31:20]
+// 2 cmd_meta_data_31_0[31:0]
+// 3 cmd_meta_data_63_32[31:0]
+// 4 reserved_4a[31:0]
+// 5 reserved_5a[31:0]
+// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TCL_GSE_CMD 7
+
+struct tcl_gse_cmd {
+ uint32_t control_buffer_addr_31_0 : 32; //[31:0]
+ uint32_t control_buffer_addr_39_32 : 8, //[7:0]
+ gse_ctrl : 4, //[11:8]
+ gse_sel : 1, //[12]
+ status_destination_ring_id : 1, //[13]
+ swap : 1, //[14]
+ index_search_en : 1, //[15]
+ cache_set_num : 4, //[19:16]
+ reserved_1a : 12; //[31:20]
+ uint32_t cmd_meta_data_31_0 : 32; //[31:0]
+ uint32_t cmd_meta_data_63_32 : 32; //[31:0]
+ uint32_t reserved_4a : 32; //[31:0]
+ uint32_t reserved_5a : 32; //[31:0]
+ uint32_t reserved_6a : 20, //[19:0]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+control_buffer_addr_31_0
+
+ Address (lower 32 bits) of a control buffer containing
+ additional info needed for this command execution.
+
+ <legal all>
+
+control_buffer_addr_39_32
+
+ Address (upper 8 bits) of a control buffer containing
+ additional info needed for this command execution.
+
+ <legal all>
+
+gse_ctrl
+
+ GSE control operations. This includes cache operations
+ and table entry statistics read/clear operation.
+
+ <enum 0 rd_stat> Report or Read statistics
+
+ <enum 1 srch_dis> Search disable. Report only Hash
+
+ <enum 2 Wr_bk_single> Write Back single entry
+
+ <enum 3 wr_bk_all> Write Back entire cache entry
+
+ <enum 4 inval_single> Invalidate single cache entry
+
+ <enum 5 inval_all> Invalidate entire cache
+
+ <enum 6 wr_bk_inval_single> Write back and Invalidate
+ single entry in cache
+
+ <enum 7 wr_bk_inval_all> write back and invalidate
+ entire cache
+
+ <enum 8 clr_stat_single> Clear statistics for single
+ entry
+
+ <legal 0-8>
+
+ Rest of the values reserved.
+
+ For all single entry control operations (write back,
+ Invalidate or both)Statistics will be reported
+
+gse_sel
+
+ Bit to select the ASE or FSE to do the operation mention
+ by GSE_ctrl bit
+
+ 0: FSE select
+
+ 1: ASE select
+
+status_destination_ring_id
+
+ The TCL status ring to which the GSE status needs to be
+ send.
+
+
+
+ <enum 0 tcl_status_0_ring>
+
+ <enum 1 tcl_status_1_ring>
+
+
+
+ <legal all>
+
+swap
+
+ Bit to enable byte swapping of contents of buffer
+
+ <enum 0 Byte_swap_disable >
+
+ <enum 1 byte_swap_enable >
+
+ <legal all>
+
+index_search_en
+
+ When this bit is set to 1 control_buffer_addr[19:0] will
+ be considered as index of the AST or Flow table and GSE
+ commands will be executed accordingly on the entry pointed
+ by the index.
+
+ This feature is disabled by setting this bit to 0.
+
+ <enum 0 index_based_cmd_disable>
+
+ <enum 1 index_based_cmd_enable>
+
+
+
+ <legal all>
+
+cache_set_num
+
+ Cache set number that should be used to cache the index
+ based search results, for address and flow search. This
+ value should be equal to value of cache_set_num for the
+ index that is issued in TCL_DATA_CMD during search index
+ based ASE or FSE. This field is valid for index based GSE
+ commands
+
+ <legal all>
+
+reserved_1a
+
+ <legal 0>
+
+cmd_meta_data_31_0
+
+ Meta data to be returned in the status descriptor
+
+ <legal all>
+
+cmd_meta_data_63_32
+
+ Meta data to be returned in the status descriptor
+
+ <legal all>
+
+reserved_4a
+
+ <legal 0>
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+ring_id
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+/* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of a control buffer containing
+ additional info needed for this command execution.
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of a control buffer containing
+ additional info needed for this command execution.
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description TCL_GSE_CMD_1_GSE_CTRL
+
+ GSE control operations. This includes cache operations
+ and table entry statistics read/clear operation.
+
+ <enum 0 rd_stat> Report or Read statistics
+
+ <enum 1 srch_dis> Search disable. Report only Hash
+
+ <enum 2 Wr_bk_single> Write Back single entry
+
+ <enum 3 wr_bk_all> Write Back entire cache entry
+
+ <enum 4 inval_single> Invalidate single cache entry
+
+ <enum 5 inval_all> Invalidate entire cache
+
+ <enum 6 wr_bk_inval_single> Write back and Invalidate
+ single entry in cache
+
+ <enum 7 wr_bk_inval_all> write back and invalidate
+ entire cache
+
+ <enum 8 clr_stat_single> Clear statistics for single
+ entry
+
+ <legal 0-8>
+
+ Rest of the values reserved.
+
+ For all single entry control operations (write back,
+ Invalidate or both)Statistics will be reported
+*/
+#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8
+#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00
+
+/* Description TCL_GSE_CMD_1_GSE_SEL
+
+ Bit to select the ASE or FSE to do the operation mention
+ by GSE_ctrl bit
+
+ 0: FSE select
+
+ 1: ASE select
+*/
+#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_GSE_SEL_LSB 12
+#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000
+
+/* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID
+
+ The TCL status ring to which the GSE status needs to be
+ send.
+
+
+
+ <enum 0 tcl_status_0_ring>
+
+ <enum 1 tcl_status_1_ring>
+
+
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000
+
+/* Description TCL_GSE_CMD_1_SWAP
+
+ Bit to enable byte swapping of contents of buffer
+
+ <enum 0 Byte_swap_disable >
+
+ <enum 1 byte_swap_enable >
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_SWAP_LSB 14
+#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000
+
+/* Description TCL_GSE_CMD_1_INDEX_SEARCH_EN
+
+ When this bit is set to 1 control_buffer_addr[19:0] will
+ be considered as index of the AST or Flow table and GSE
+ commands will be executed accordingly on the entry pointed
+ by the index.
+
+ This feature is disabled by setting this bit to 0.
+
+ <enum 0 index_based_cmd_disable>
+
+ <enum 1 index_based_cmd_enable>
+
+
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15
+#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000
+
+/* Description TCL_GSE_CMD_1_CACHE_SET_NUM
+
+ Cache set number that should be used to cache the index
+ based search results, for address and flow search. This
+ value should be equal to value of cache_set_num for the
+ index that is issued in TCL_DATA_CMD during search index
+ based ASE or FSE. This field is valid for index based GSE
+ commands
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16
+#define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000
+
+/* Description TCL_GSE_CMD_1_RESERVED_1A
+
+ <legal 0>
+*/
+#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004
+#define TCL_GSE_CMD_1_RESERVED_1A_LSB 20
+#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000
+
+/* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0
+
+ Meta data to be returned in the status descriptor
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff
+
+/* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32
+
+ Meta data to be returned in the status descriptor
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff
+
+/* Description TCL_GSE_CMD_4_RESERVED_4A
+
+ <legal 0>
+*/
+#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010
+#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0
+#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff
+
+/* Description TCL_GSE_CMD_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014
+#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0
+#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff
+
+/* Description TCL_GSE_CMD_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018
+#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0
+#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff
+
+/* Description TCL_GSE_CMD_6_RING_ID
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018
+#define TCL_GSE_CMD_6_RING_ID_LSB 20
+#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000
+
+/* Description TCL_GSE_CMD_6_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018
+#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28
+#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _TCL_GSE_CMD_H_
diff --git a/hw/qca5018/tcl_status_ring.h b/hw/qca5018/tcl_status_ring.h
new file mode 100644
index 0000000..fbc1d21
--- /dev/null
+++ b/hw/qca5018/tcl_status_ring.h
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], index_search_en[7], msdu_cnt_n[31:8]
+// 1 msdu_byte_cnt_n[31:0]
+// 2 msdu_timestmp_n[31:0]
+// 3 cmd_meta_data_31_0[31:0]
+// 4 cmd_meta_data_63_32[31:0]
+// 5 hash_indx_val[19:0], cache_set_num[23:20], reserved_5a[31:24]
+// 6 reserved_6a[31:0]
+// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+ uint32_t gse_ctrl : 4, //[3:0]
+ ase_fse_sel : 1, //[4]
+ cache_op_res : 2, //[6:5]
+ index_search_en : 1, //[7]
+ msdu_cnt_n : 24; //[31:8]
+ uint32_t msdu_byte_cnt_n : 32; //[31:0]
+ uint32_t msdu_timestmp_n : 32; //[31:0]
+ uint32_t cmd_meta_data_31_0 : 32; //[31:0]
+ uint32_t cmd_meta_data_63_32 : 32; //[31:0]
+ uint32_t hash_indx_val : 20, //[19:0]
+ cache_set_num : 4, //[23:20]
+ reserved_5a : 8; //[31:24]
+ uint32_t reserved_6a : 32; //[31:0]
+ uint32_t reserved_7a : 20, //[19:0]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+gse_ctrl
+
+ GSE control operations. This includes cache operations
+ and table entry statistics read/clear operation.
+
+ <enum 0 rd_stat> Report or Read statistics
+
+ <enum 1 srch_dis> Search disable. Report only Hash
+
+ <enum 2 Wr_bk_single> Write Back single entry
+
+ <enum 3 wr_bk_all> Write Back entire cache entry
+
+ <enum 4 inval_single> Invalidate single cache entry
+
+ <enum 5 inval_all> Invalidate entire cache
+
+ <enum 6 wr_bk_inval_single> Write back and Invalidate
+ single entry in cache
+
+ <enum 7 wr_bk_inval_all> write back and invalidate
+ entire cache
+
+ <enum 8 clr_stat_single> Clear statistics for single
+ entry
+
+ <legal 0-8>
+
+ Rest of the values reserved.
+
+ For all single entry control operations (write back,
+ Invalidate or both)Statistics will be reported
+
+ase_fse_sel
+
+ Search Engine for which operation is done.
+
+ 1'b0: Address Search Engine Result
+
+ 1'b1: Flow Search Engine result
+
+cache_op_res
+
+ Cache operation result. Following are results of cache
+ operation.
+
+ <enum 0 op_done> Operation successful
+
+ <enum 1 not_fnd> Entry not found in Table
+
+ <enum 2 timeout_er> Timeout Error
+
+ <legal 0-2>
+
+index_search_en
+
+ When this bit is set to 1 control_buffer_addr[19:0] will
+ be considered as index of the AST or Flow table and GSE
+ commands will be executed accordingly on the entry pointed
+ by the index.
+
+ This feature is disabled by setting this bit to 0.
+
+ <enum 0 index_based_cmd_disable>
+
+ <enum 1 index_based_cmd_enable>
+
+
+
+ <legal all>
+
+msdu_cnt_n
+
+ MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
+ 4'b1000
+
+msdu_byte_cnt_n
+
+ MSDU byte count for entry 1. Valid when GSE_CTRL is
+ 4'b0111 and 4'b1000
+
+msdu_timestmp_n
+
+ MSDU timestamp for entry 1. Valid when GSE_CTRL is
+ 4'b0111 and 4'b1000
+
+cmd_meta_data_31_0
+
+ Meta data from input ring
+
+ <legal all>
+
+cmd_meta_data_63_32
+
+ Meta data from input ring
+
+ <legal all>
+
+hash_indx_val
+
+
+ Hash value of the entry in table in case of search
+ failed or search disable.
+
+ <legal all>
+
+cache_set_num
+
+ Cache set number copied from TCL_GSE_CMD
+
+reserved_5a
+
+ <legal 0>
+
+reserved_6a
+
+ <legal 0>
+
+reserved_7a
+
+ <legal 0>
+
+ring_id
+
+ The buffer pointer ring ID.
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+
+looping_count
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+/* Description TCL_STATUS_RING_0_GSE_CTRL
+
+ GSE control operations. This includes cache operations
+ and table entry statistics read/clear operation.
+
+ <enum 0 rd_stat> Report or Read statistics
+
+ <enum 1 srch_dis> Search disable. Report only Hash
+
+ <enum 2 Wr_bk_single> Write Back single entry
+
+ <enum 3 wr_bk_all> Write Back entire cache entry
+
+ <enum 4 inval_single> Invalidate single cache entry
+
+ <enum 5 inval_all> Invalidate entire cache
+
+ <enum 6 wr_bk_inval_single> Write back and Invalidate
+ single entry in cache
+
+ <enum 7 wr_bk_inval_all> write back and invalidate
+ entire cache
+
+ <enum 8 clr_stat_single> Clear statistics for single
+ entry
+
+ <legal 0-8>
+
+ Rest of the values reserved.
+
+ For all single entry control operations (write back,
+ Invalidate or both)Statistics will be reported
+*/
+#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0
+#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f
+
+/* Description TCL_STATUS_RING_0_ASE_FSE_SEL
+
+ Search Engine for which operation is done.
+
+ 1'b0: Address Search Engine Result
+
+ 1'b1: Flow Search Engine result
+*/
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010
+
+/* Description TCL_STATUS_RING_0_CACHE_OP_RES
+
+ Cache operation result. Following are results of cache
+ operation.
+
+ <enum 0 op_done> Operation successful
+
+ <enum 1 not_fnd> Entry not found in Table
+
+ <enum 2 timeout_er> Timeout Error
+
+ <legal 0-2>
+*/
+#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5
+#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060
+
+/* Description TCL_STATUS_RING_0_INDEX_SEARCH_EN
+
+ When this bit is set to 1 control_buffer_addr[19:0] will
+ be considered as index of the AST or Flow table and GSE
+ commands will be executed accordingly on the entry pointed
+ by the index.
+
+ This feature is disabled by setting this bit to 0.
+
+ <enum 0 index_based_cmd_disable>
+
+ <enum 1 index_based_cmd_enable>
+
+
+
+ <legal all>
+*/
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7
+#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080
+
+/* Description TCL_STATUS_RING_0_MSDU_CNT_N
+
+ MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
+ 4'b1000
+*/
+#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000
+#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8
+#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00
+
+/* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N
+
+ MSDU byte count for entry 1. Valid when GSE_CTRL is
+ 4'b0111 and 4'b1000
+*/
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff
+
+/* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N
+
+ MSDU timestamp for entry 1. Valid when GSE_CTRL is
+ 4'b0111 and 4'b1000
+*/
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff
+
+/* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0
+
+ Meta data from input ring
+
+ <legal all>
+*/
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff
+
+/* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32
+
+ Meta data from input ring
+
+ <legal all>
+*/
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff
+
+/* Description TCL_STATUS_RING_5_HASH_INDX_VAL
+
+
+ Hash value of the entry in table in case of search
+ failed or search disable.
+
+ <legal all>
+*/
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff
+
+/* Description TCL_STATUS_RING_5_CACHE_SET_NUM
+
+ Cache set number copied from TCL_GSE_CMD
+*/
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20
+#define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000
+
+/* Description TCL_STATUS_RING_5_RESERVED_5A
+
+ <legal 0>
+*/
+#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014
+#define TCL_STATUS_RING_5_RESERVED_5A_LSB 24
+#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000
+
+/* Description TCL_STATUS_RING_6_RESERVED_6A
+
+ <legal 0>
+*/
+#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018
+#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0
+#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff
+
+/* Description TCL_STATUS_RING_7_RESERVED_7A
+
+ <legal 0>
+*/
+#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c
+#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0
+#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff
+
+/* Description TCL_STATUS_RING_7_RING_ID
+
+ The buffer pointer ring ID.
+
+
+
+ Helps with debugging when dumping ring contents.
+
+ <legal all>
+*/
+#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c
+#define TCL_STATUS_RING_7_RING_ID_LSB 20
+#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000
+
+/* Description TCL_STATUS_RING_7_LOOPING_COUNT
+
+ A count value that indicates the number of times the
+ producer of entries into the Ring has looped around the
+ ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
+#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28
+#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _TCL_STATUS_RING_H_
diff --git a/hw/qca5018/tlv_hdr.h b/hw/qca5018/tlv_hdr.h
new file mode 100644
index 0000000..5072476
--- /dev/null
+++ b/hw/qca5018/tlv_hdr.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _TLV_HDR_H_
+#define _TLV_HDR_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+struct tlv_usr_16_hdr {
+ volatile uint16_t tlv_cflg_reserved : 1,
+ tlv_tag : 5,
+ tlv_len : 4,
+ tlv_usrid : 6;
+};
+
+struct tlv_16_hdr {
+ volatile uint16_t tlv_cflg_reserved : 1,
+ tlv_tag : 5,
+ tlv_len : 4,
+ tlv_reserved : 6;
+};
+
+struct tlv_usr_32_hdr {
+ volatile uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : 9,
+ tlv_len : 16,
+ tlv_usrid : 6;
+};
+
+struct tlv_32_hdr {
+ volatile uint32_t tlv_cflg_reserved : 1,
+ tlv_tag : 9,
+ tlv_len : 16,
+ tlv_reserved : 6;
+};
+
+struct tlv_usr_42_hdr {
+ volatile uint64_t tlv_compression : 1,
+ tlv_tag : 9,
+ tlv_len : 16,
+ tlv_usrid : 6,
+ tlv_reserved : 10,
+ pad_42to64_bit : 22;
+};
+
+struct tlv_42_hdr {
+ volatile uint64_t tlv_compression : 1,
+ tlv_tag : 9,
+ tlv_len : 16,
+ tlv_reserved : 16,
+ pad_42to64_bit : 22;
+};
+
+struct tlv_usr_c_42_hdr {
+ volatile uint64_t tlv_compression : 1,
+ tlv_ctag : 3,
+ tlv_usrid : 6,
+ tlv_cdata : 32,
+ pad_42to64_bit : 22;
+};
+
+#endif
diff --git a/hw/qca5018/tlv_tag_def.h b/hw/qca5018/tlv_tag_def.h
new file mode 100644
index 0000000..570bfee
--- /dev/null
+++ b/hw/qca5018/tlv_tag_def.h
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum {
+
+ WIFIMACTX_CBF_START_E = 0 /* 0x0 */,
+ WIFIPHYRX_DATA_E = 1 /* 0x1 */,
+ WIFIPHYRX_CBF_DATA_RESP_E = 2 /* 0x2 */,
+ WIFIPHYRX_ABORT_REQUEST_E = 3 /* 0x3 */,
+ WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 /* 0x4 */,
+ WIFIMACTX_DATA_RESP_E = 5 /* 0x5 */,
+ WIFIMACTX_CBF_DATA_E = 6 /* 0x6 */,
+ WIFIMACTX_CBF_DONE_E = 7 /* 0x7 */,
+ WIFIMACRX_CBF_READ_REQUEST_E = 8 /* 0x8 */,
+ WIFIMACRX_CBF_DATA_REQUEST_E = 9 /* 0x9 */,
+ WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 /* 0xa */,
+ WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 /* 0xb */,
+ WIFIMACRX_NDP_TIMEOUT_E = 12 /* 0xc */,
+ WIFIMACRX_ABORT_ACK_E = 13 /* 0xd */,
+ WIFIMACRX_REQ_IMPLICIT_FB_E = 14 /* 0xe */,
+ WIFIMACRX_CHAIN_MASK_E = 15 /* 0xf */,
+ WIFIMACRX_NAP_USER_E = 16 /* 0x10 */,
+ WIFIMACRX_ABORT_REQUEST_E = 17 /* 0x11 */,
+ WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 /* 0x12 */,
+ WIFIPHYTX_ABORT_ACK_E = 19 /* 0x13 */,
+ WIFIPHYTX_ABORT_REQUEST_E = 20 /* 0x14 */,
+ WIFIPHYTX_PKT_END_E = 21 /* 0x15 */,
+ WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 /* 0x16 */,
+ WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 /* 0x17 */,
+ WIFIPHYTX_DATA_REQUEST_E = 24 /* 0x18 */,
+ WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 /* 0x19 */,
+ WIFIPHYTX_NAP_ACK_E = 26 /* 0x1a */,
+ WIFIPHYTX_NAP_DONE_E = 27 /* 0x1b */,
+ WIFIPHYTX_OFF_ACK_E = 28 /* 0x1c */,
+ WIFIPHYTX_ON_ACK_E = 29 /* 0x1d */,
+ WIFIPHYTX_SYNTH_OFF_ACK_E = 30 /* 0x1e */,
+ WIFIPHYTX_DEBUG16_E = 31 /* 0x1f */,
+ WIFIMACTX_ABORT_REQUEST_E = 32 /* 0x20 */,
+ WIFIMACTX_ABORT_ACK_E = 33 /* 0x21 */,
+ WIFIMACTX_PKT_END_E = 34 /* 0x22 */,
+ WIFIMACTX_PRE_PHY_DESC_E = 35 /* 0x23 */,
+ WIFIMACTX_BF_PARAMS_COMMON_E = 36 /* 0x24 */,
+ WIFIMACTX_BF_PARAMS_PER_USER_E = 37 /* 0x25 */,
+ WIFIMACTX_PREFETCH_CV_E = 38 /* 0x26 */,
+ WIFIMACTX_USER_DESC_COMMON_E = 39 /* 0x27 */,
+ WIFIMACTX_USER_DESC_PER_USER_E = 40 /* 0x28 */,
+ WIFIEXAMPLE_USER_TLV_16_E = 41 /* 0x29 */,
+ WIFIEXAMPLE_TLV_16_E = 42 /* 0x2a */,
+ WIFIMACTX_PHY_OFF_E = 43 /* 0x2b */,
+ WIFIMACTX_PHY_ON_E = 44 /* 0x2c */,
+ WIFIMACTX_SYNTH_OFF_E = 45 /* 0x2d */,
+ WIFIMACTX_EXPECT_CBF_COMMON_E = 46 /* 0x2e */,
+ WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 /* 0x2f */,
+ WIFIMACTX_PHY_DESC_E = 48 /* 0x30 */,
+ WIFIMACTX_L_SIG_A_E = 49 /* 0x31 */,
+ WIFIMACTX_L_SIG_B_E = 50 /* 0x32 */,
+ WIFIMACTX_HT_SIG_E = 51 /* 0x33 */,
+ WIFIMACTX_VHT_SIG_A_E = 52 /* 0x34 */,
+ WIFIMACTX_VHT_SIG_B_SU20_E = 53 /* 0x35 */,
+ WIFIMACTX_VHT_SIG_B_SU40_E = 54 /* 0x36 */,
+ WIFIMACTX_VHT_SIG_B_SU80_E = 55 /* 0x37 */,
+ WIFIMACTX_VHT_SIG_B_SU160_E = 56 /* 0x38 */,
+ WIFIMACTX_VHT_SIG_B_MU20_E = 57 /* 0x39 */,
+ WIFIMACTX_VHT_SIG_B_MU40_E = 58 /* 0x3a */,
+ WIFIMACTX_VHT_SIG_B_MU80_E = 59 /* 0x3b */,
+ WIFIMACTX_VHT_SIG_B_MU160_E = 60 /* 0x3c */,
+ WIFIMACTX_SERVICE_E = 61 /* 0x3d */,
+ WIFIMACTX_HE_SIG_A_SU_E = 62 /* 0x3e */,
+ WIFIMACTX_HE_SIG_A_MU_DL_E = 63 /* 0x3f */,
+ WIFIMACTX_HE_SIG_A_MU_UL_E = 64 /* 0x40 */,
+ WIFIMACTX_HE_SIG_B1_MU_E = 65 /* 0x41 */,
+ WIFIMACTX_HE_SIG_B2_MU_E = 66 /* 0x42 */,
+ WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 /* 0x43 */,
+ WIFIMACTX_DELETE_CV_E = 68 /* 0x44 */,
+ WIFIMACTX_MU_UPLINK_COMMON_E = 69 /* 0x45 */,
+ WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 /* 0x46 */,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 /* 0x47 */,
+ WIFIMACTX_PHY_NAP_E = 72 /* 0x48 */,
+ WIFIMACTX_DEBUG_E = 73 /* 0x49 */,
+ WIFIPHYRX_ABORT_ACK_E = 74 /* 0x4a */,
+ WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 /* 0x4b */,
+ WIFIPHYRX_RSSI_LEGACY_E = 76 /* 0x4c */,
+ WIFIPHYRX_RSSI_HT_E = 77 /* 0x4d */,
+ WIFIPHYRX_USER_INFO_E = 78 /* 0x4e */,
+ WIFIPHYRX_PKT_END_E = 79 /* 0x4f */,
+ WIFIPHYRX_DEBUG_E = 80 /* 0x50 */,
+ WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 /* 0x51 */,
+ WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 /* 0x52 */,
+ WIFIPHYRX_L_SIG_A_E = 83 /* 0x53 */,
+ WIFIPHYRX_L_SIG_B_E = 84 /* 0x54 */,
+ WIFIPHYRX_HT_SIG_E = 85 /* 0x55 */,
+ WIFIPHYRX_VHT_SIG_A_E = 86 /* 0x56 */,
+ WIFIPHYRX_VHT_SIG_B_SU20_E = 87 /* 0x57 */,
+ WIFIPHYRX_VHT_SIG_B_SU40_E = 88 /* 0x58 */,
+ WIFIPHYRX_VHT_SIG_B_SU80_E = 89 /* 0x59 */,
+ WIFIPHYRX_VHT_SIG_B_SU160_E = 90 /* 0x5a */,
+ WIFIPHYRX_VHT_SIG_B_MU20_E = 91 /* 0x5b */,
+ WIFIPHYRX_VHT_SIG_B_MU40_E = 92 /* 0x5c */,
+ WIFIPHYRX_VHT_SIG_B_MU80_E = 93 /* 0x5d */,
+ WIFIPHYRX_VHT_SIG_B_MU160_E = 94 /* 0x5e */,
+ WIFIPHYRX_HE_SIG_A_SU_E = 95 /* 0x5f */,
+ WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 /* 0x60 */,
+ WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 /* 0x61 */,
+ WIFIPHYRX_HE_SIG_B1_MU_E = 98 /* 0x62 */,
+ WIFIPHYRX_HE_SIG_B2_MU_E = 99 /* 0x63 */,
+ WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 /* 0x64 */,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 /* 0x65 */,
+ WIFIPHYRX_COMMON_USER_INFO_E = 102 /* 0x66 */,
+ WIFIPHYRX_DATA_DONE_E = 103 /* 0x67 */,
+ WIFIRECEIVE_RSSI_INFO_E = 104 /* 0x68 */,
+ WIFIRECEIVE_USER_INFO_E = 105 /* 0x69 */,
+ WIFIMIMO_CONTROL_INFO_E = 106 /* 0x6a */,
+ WIFIRX_LOCATION_INFO_E = 107 /* 0x6b */,
+ WIFICOEX_TX_REQ_E = 108 /* 0x6c */,
+ WIFIDUMMY_E = 109 /* 0x6d */,
+ WIFIRX_TIMING_OFFSET_INFO_E = 110 /* 0x6e */,
+ WIFIEXAMPLE_TLV_32_NAME_E = 111 /* 0x6f */,
+ WIFIMPDU_LIMIT_E = 112 /* 0x70 */,
+ WIFINA_LENGTH_END_E = 113 /* 0x71 */,
+ WIFIOLE_BUF_STATUS_E = 114 /* 0x72 */,
+ WIFIPCU_PPDU_SETUP_DONE_E = 115 /* 0x73 */,
+ WIFIPCU_PPDU_SETUP_END_E = 116 /* 0x74 */,
+ WIFIPCU_PPDU_SETUP_INIT_E = 117 /* 0x75 */,
+ WIFIPCU_PPDU_SETUP_START_E = 118 /* 0x76 */,
+ WIFIPDG_FES_SETUP_E = 119 /* 0x77 */,
+ WIFIPDG_RESPONSE_E = 120 /* 0x78 */,
+ WIFIPDG_TX_REQ_E = 121 /* 0x79 */,
+ WIFISCH_WAIT_INSTR_E = 122 /* 0x7a */,
+ WIFISCHEDULER_TLV_E = 123 /* 0x7b */,
+ WIFITQM_FLOW_EMPTY_STATUS_E = 124 /* 0x7c */,
+ WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 /* 0x7d */,
+ WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 /* 0x7e */,
+ WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 /* 0x7f */,
+ WIFITQM_GEN_MPDUS_E = 128 /* 0x80 */,
+ WIFITQM_GEN_MPDUS_STATUS_E = 129 /* 0x81 */,
+ WIFITQM_REMOVE_MPDU_E = 130 /* 0x82 */,
+ WIFITQM_REMOVE_MPDU_STATUS_E = 131 /* 0x83 */,
+ WIFITQM_REMOVE_MSDU_E = 132 /* 0x84 */,
+ WIFITQM_REMOVE_MSDU_STATUS_E = 133 /* 0x85 */,
+ WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 /* 0x86 */,
+ WIFITQM_WRITE_CMD_E = 135 /* 0x87 */,
+ WIFIOFDMA_TRIGGER_DETAILS_E = 136 /* 0x88 */,
+ WIFITX_DATA_E = 137 /* 0x89 */,
+ WIFITX_FES_SETUP_E = 138 /* 0x8a */,
+ WIFIRX_PACKET_E = 139 /* 0x8b */,
+ WIFIEXPECTED_RESPONSE_E = 140 /* 0x8c */,
+ WIFITX_MPDU_END_E = 141 /* 0x8d */,
+ WIFITX_MPDU_START_E = 142 /* 0x8e */,
+ WIFITX_MSDU_END_E = 143 /* 0x8f */,
+ WIFITX_MSDU_START_E = 144 /* 0x90 */,
+ WIFITX_SW_MODE_SETUP_E = 145 /* 0x91 */,
+ WIFITXPCU_BUFFER_STATUS_E = 146 /* 0x92 */,
+ WIFITXPCU_USER_BUFFER_STATUS_E = 147 /* 0x93 */,
+ WIFIDATA_TO_TIME_CONFIG_E = 148 /* 0x94 */,
+ WIFIEXAMPLE_USER_TLV_32_E = 149 /* 0x95 */,
+ WIFIMPDU_INFO_E = 150 /* 0x96 */,
+ WIFIPDG_USER_SETUP_E = 151 /* 0x97 */,
+ WIFITX_11AH_SETUP_E = 152 /* 0x98 */,
+ WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 /* 0x99 */,
+ WIFITX_PEER_ENTRY_E = 154 /* 0x9a */,
+ WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 /* 0x9b */,
+ WIFIEXAMPLE_STRUCT_NAME_E = 156 /* 0x9c */,
+ WIFIPCU_PPDU_SETUP_END_INFO_E = 157 /* 0x9d */,
+ WIFIPPDU_RATE_SETTING_E = 158 /* 0x9e */,
+ WIFIPROT_RATE_SETTING_E = 159 /* 0x9f */,
+ WIFIRX_MPDU_DETAILS_E = 160 /* 0xa0 */,
+ WIFIEXAMPLE_USER_TLV_42_E = 161 /* 0xa1 */,
+ WIFIRX_MSDU_LINK_E = 162 /* 0xa2 */,
+ WIFIRX_REO_QUEUE_E = 163 /* 0xa3 */,
+ WIFIADDR_SEARCH_ENTRY_E = 164 /* 0xa4 */,
+ WIFISCHEDULER_CMD_E = 165 /* 0xa5 */,
+ WIFITX_FLUSH_E = 166 /* 0xa6 */,
+ WIFITQM_ENTRANCE_RING_E = 167 /* 0xa7 */,
+ WIFITX_DATA_WORD_E = 168 /* 0xa8 */,
+ WIFITX_MPDU_DETAILS_E = 169 /* 0xa9 */,
+ WIFITX_MPDU_LINK_E = 170 /* 0xaa */,
+ WIFITX_MPDU_LINK_PTR_E = 171 /* 0xab */,
+ WIFITX_MPDU_QUEUE_HEAD_E = 172 /* 0xac */,
+ WIFITX_MPDU_QUEUE_EXT_E = 173 /* 0xad */,
+ WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 /* 0xae */,
+ WIFITX_MSDU_DETAILS_E = 175 /* 0xaf */,
+ WIFITX_MSDU_EXTENSION_E = 176 /* 0xb0 */,
+ WIFITX_MSDU_FLOW_E = 177 /* 0xb1 */,
+ WIFITX_MSDU_LINK_E = 178 /* 0xb2 */,
+ WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 /* 0xb3 */,
+ WIFIRESPONSE_RATE_SETTING_E = 180 /* 0xb4 */,
+ WIFITXPCU_BUFFER_BASICS_E = 181 /* 0xb5 */,
+ WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 /* 0xb6 */,
+ WIFIUNIFORM_TQM_CMD_HEADER_E = 183 /* 0xb7 */,
+ WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 /* 0xb8 */,
+ WIFIUSER_RATE_SETTING_E = 185 /* 0xb9 */,
+ WIFIWBM_BUFFER_RING_E = 186 /* 0xba */,
+ WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 /* 0xbb */,
+ WIFIWBM_RELEASE_RING_E = 188 /* 0xbc */,
+ WIFITX_FLUSH_REQ_E = 189 /* 0xbd */,
+ WIFIRX_MSDU_DETAILS_E = 190 /* 0xbe */,
+ WIFITQM_WRITE_CMD_STATUS_E = 191 /* 0xbf */,
+ WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 /* 0xc0 */,
+ WIFITQM_GET_MSDU_FLOW_STATS_E = 193 /* 0xc1 */,
+ WIFIEXAMPLE_USER_CTLV_32_E = 194 /* 0xc2 */,
+ WIFITX_FES_STATUS_START_E = 195 /* 0xc3 */,
+ WIFITX_FES_STATUS_USER_PPDU_E = 196 /* 0xc4 */,
+ WIFITX_FES_STATUS_USER_RESPONSE_E = 197 /* 0xc5 */,
+ WIFITX_FES_STATUS_END_E = 198 /* 0xc6 */,
+ WIFIRX_TRIG_INFO_E = 199 /* 0xc7 */,
+ WIFIRXPCU_TX_SETUP_CLEAR_E = 200 /* 0xc8 */,
+ WIFIRX_FRAME_BITMAP_REQ_E = 201 /* 0xc9 */,
+ WIFIRX_FRAME_BITMAP_ACK_E = 202 /* 0xca */,
+ WIFICOEX_RX_STATUS_E = 203 /* 0xcb */,
+ WIFIRX_START_PARAM_E = 204 /* 0xcc */,
+ WIFIRX_PPDU_START_E = 205 /* 0xcd */,
+ WIFIRX_PPDU_END_E = 206 /* 0xce */,
+ WIFIRX_MPDU_START_E = 207 /* 0xcf */,
+ WIFIRX_MPDU_END_E = 208 /* 0xd0 */,
+ WIFIRX_MSDU_START_E = 209 /* 0xd1 */,
+ WIFIRX_MSDU_END_E = 210 /* 0xd2 */,
+ WIFIRX_ATTENTION_E = 211 /* 0xd3 */,
+ WIFIRECEIVED_RESPONSE_INFO_E = 212 /* 0xd4 */,
+ WIFIRX_PHY_SLEEP_E = 213 /* 0xd5 */,
+ WIFIRX_HEADER_E = 214 /* 0xd6 */,
+ WIFIRX_PEER_ENTRY_E = 215 /* 0xd7 */,
+ WIFIRX_FLUSH_E = 216 /* 0xd8 */,
+ WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 /* 0xd9 */,
+ WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 /* 0xda */,
+ WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 /* 0xdb */,
+ WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 /* 0xdc */,
+ WIFITX_CBF_INFO_E = 221 /* 0xdd */,
+ WIFIPCU_PPDU_SETUP_USER_E = 222 /* 0xde */,
+ WIFIRX_MPDU_PCU_START_E = 223 /* 0xdf */,
+ WIFIRX_PM_INFO_E = 224 /* 0xe0 */,
+ WIFIRX_USER_PPDU_END_E = 225 /* 0xe1 */,
+ WIFIRX_PRE_PPDU_START_E = 226 /* 0xe2 */,
+ WIFIRX_PREAMBLE_E = 227 /* 0xe3 */,
+ WIFITX_FES_SETUP_COMPLETE_E = 228 /* 0xe4 */,
+ WIFITX_LAST_MPDU_FETCHED_E = 229 /* 0xe5 */,
+ WIFITXDMA_STOP_REQUEST_E = 230 /* 0xe6 */,
+ WIFIRXPCU_SETUP_E = 231 /* 0xe7 */,
+ WIFIRXPCU_USER_SETUP_E = 232 /* 0xe8 */,
+ WIFITX_FES_STATUS_ACK_OR_BA_E = 233 /* 0xe9 */,
+ WIFITQM_ACKED_MPDU_E = 234 /* 0xea */,
+ WIFICOEX_TX_RESP_E = 235 /* 0xeb */,
+ WIFICOEX_TX_STATUS_E = 236 /* 0xec */,
+ WIFIMACTX_COEX_PHY_CTRL_E = 237 /* 0xed */,
+ WIFICOEX_STATUS_BROADCAST_E = 238 /* 0xee */,
+ WIFIRESPONSE_START_STATUS_E = 239 /* 0xef */,
+ WIFIRESPONSE_END_STATUS_E = 240 /* 0xf0 */,
+ WIFICRYPTO_STATUS_E = 241 /* 0xf1 */,
+ WIFIRECEIVED_TRIGGER_INFO_E = 242 /* 0xf2 */,
+ WIFIREO_ENTRANCE_RING_E = 243 /* 0xf3 */,
+ WIFIRX_MPDU_LINK_E = 244 /* 0xf4 */,
+ WIFICOEX_TX_STOP_CTRL_E = 245 /* 0xf5 */,
+ WIFIRX_PPDU_ACK_REPORT_E = 246 /* 0xf6 */,
+ WIFIRX_PPDU_NO_ACK_REPORT_E = 247 /* 0xf7 */,
+ WIFISCH_COEX_STATUS_E = 248 /* 0xf8 */,
+ WIFISCHEDULER_COMMAND_STATUS_E = 249 /* 0xf9 */,
+ WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 /* 0xfa */,
+ WIFITX_FES_STATUS_PROT_E = 251 /* 0xfb */,
+ WIFITX_FES_STATUS_START_PPDU_E = 252 /* 0xfc */,
+ WIFITX_FES_STATUS_START_PROT_E = 253 /* 0xfd */,
+ WIFITXPCU_PHYTX_DEBUG32_E = 254 /* 0xfe */,
+ WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 /* 0xff */,
+ WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 /* 0x100 */,
+ WIFIWHO_ANCHOR_OFFSET_E = 257 /* 0x101 */,
+ WIFIWHO_ANCHOR_VALUE_E = 258 /* 0x102 */,
+ WIFIWHO_CCE_INFO_E = 259 /* 0x103 */,
+ WIFIWHO_COMMIT_E = 260 /* 0x104 */,
+ WIFIWHO_COMMIT_DONE_E = 261 /* 0x105 */,
+ WIFIWHO_FLUSH_E = 262 /* 0x106 */,
+ WIFIWHO_L2_LLC_E = 263 /* 0x107 */,
+ WIFIWHO_L2_PAYLOAD_E = 264 /* 0x108 */,
+ WIFIWHO_L3_CHECKSUM_E = 265 /* 0x109 */,
+ WIFIWHO_L3_INFO_E = 266 /* 0x10a */,
+ WIFIWHO_L4_CHECKSUM_E = 267 /* 0x10b */,
+ WIFIWHO_L4_INFO_E = 268 /* 0x10c */,
+ WIFIWHO_MSDU_E = 269 /* 0x10d */,
+ WIFIWHO_MSDU_MISC_E = 270 /* 0x10e */,
+ WIFIWHO_PACKET_DATA_E = 271 /* 0x10f */,
+ WIFIWHO_PACKET_HDR_E = 272 /* 0x110 */,
+ WIFIWHO_PPDU_END_E = 273 /* 0x111 */,
+ WIFIWHO_PPDU_START_E = 274 /* 0x112 */,
+ WIFIWHO_TSO_E = 275 /* 0x113 */,
+ WIFIWHO_WMAC_HEADER_PV0_E = 276 /* 0x114 */,
+ WIFIWHO_WMAC_HEADER_PV1_E = 277 /* 0x115 */,
+ WIFIWHO_WMAC_IV_E = 278 /* 0x116 */,
+ WIFIMPDU_INFO_END_E = 279 /* 0x117 */,
+ WIFIMPDU_INFO_BITMAP_E = 280 /* 0x118 */,
+ WIFITX_QUEUE_EXTENSION_E = 281 /* 0x119 */,
+ WIFIRX_PEER_ENTRY_DETAILS_E = 282 /* 0x11a */,
+ WIFIRX_REO_QUEUE_REFERENCE_E = 283 /* 0x11b */,
+ WIFIRX_REO_QUEUE_EXT_E = 284 /* 0x11c */,
+ WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 /* 0x11d */,
+ WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 /* 0x11e */,
+ WIFITQM_ACKED_MPDU_STATUS_E = 287 /* 0x11f */,
+ WIFITQM_ADD_MSDU_STATUS_E = 288 /* 0x120 */,
+ WIFIRX_MPDU_LINK_PTR_E = 289 /* 0x121 */,
+ WIFIREO_DESTINATION_RING_E = 290 /* 0x122 */,
+ WIFITQM_LIST_GEN_DONE_E = 291 /* 0x123 */,
+ WIFIWHO_TERMINATE_E = 292 /* 0x124 */,
+ WIFITX_LAST_MPDU_END_E = 293 /* 0x125 */,
+ WIFITX_CV_DATA_E = 294 /* 0x126 */,
+ WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 /* 0x127 */,
+ WIFIPPDU_TX_END_E = 296 /* 0x128 */,
+ WIFIPROT_TX_END_E = 297 /* 0x129 */,
+ WIFIPDG_RESPONSE_RATE_SETTING_E = 298 /* 0x12a */,
+ WIFIMPDU_INFO_GLOBAL_END_E = 299 /* 0x12b */,
+ WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 /* 0x12c */,
+ WIFIRX_PPDU_END_USER_STATS_E = 301 /* 0x12d */,
+ WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 /* 0x12e */,
+ WIFINO_ACK_REPORT_E = 303 /* 0x12f */,
+ WIFIACK_REPORT_E = 304 /* 0x130 */,
+ WIFIUNIFORM_REO_CMD_HEADER_E = 305 /* 0x131 */,
+ WIFIREO_GET_QUEUE_STATS_E = 306 /* 0x132 */,
+ WIFIREO_FLUSH_QUEUE_E = 307 /* 0x133 */,
+ WIFIREO_FLUSH_CACHE_E = 308 /* 0x134 */,
+ WIFIREO_UNBLOCK_CACHE_E = 309 /* 0x135 */,
+ WIFIUNIFORM_REO_STATUS_HEADER_E = 310 /* 0x136 */,
+ WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 /* 0x137 */,
+ WIFIREO_FLUSH_QUEUE_STATUS_E = 312 /* 0x138 */,
+ WIFIREO_FLUSH_CACHE_STATUS_E = 313 /* 0x139 */,
+ WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 /* 0x13a */,
+ WIFITQM_FLUSH_CACHE_E = 315 /* 0x13b */,
+ WIFITQM_UNBLOCK_CACHE_E = 316 /* 0x13c */,
+ WIFITQM_FLUSH_CACHE_STATUS_E = 317 /* 0x13d */,
+ WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 /* 0x13e */,
+ WIFIRX_PPDU_END_STATUS_DONE_E = 319 /* 0x13f */,
+ WIFIRX_STATUS_BUFFER_DONE_E = 320 /* 0x140 */,
+ WIFIBUFFER_ADDR_INFO_E = 321 /* 0x141 */,
+ WIFIRX_MSDU_DESC_INFO_E = 322 /* 0x142 */,
+ WIFIRX_MPDU_DESC_INFO_E = 323 /* 0x143 */,
+ WIFITCL_DATA_CMD_E = 324 /* 0x144 */,
+ WIFITCL_GSE_CMD_E = 325 /* 0x145 */,
+ WIFITCL_EXIT_BASE_E = 326 /* 0x146 */,
+ WIFITCL_COMPACT_EXIT_RING_E = 327 /* 0x147 */,
+ WIFITCL_REGULAR_EXIT_RING_E = 328 /* 0x148 */,
+ WIFITCL_EXTENDED_EXIT_RING_E = 329 /* 0x149 */,
+ WIFIUPLINK_COMMON_INFO_E = 330 /* 0x14a */,
+ WIFIUPLINK_USER_SETUP_INFO_E = 331 /* 0x14b */,
+ WIFITX_DATA_SYNC_E = 332 /* 0x14c */,
+ WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 /* 0x14d */,
+ WIFITCL_STATUS_RING_E = 334 /* 0x14e */,
+ WIFITQM_GET_MPDU_HEAD_INFO_E = 335 /* 0x14f */,
+ WIFITQM_SYNC_CMD_E = 336 /* 0x150 */,
+ WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 /* 0x151 */,
+ WIFITQM_SYNC_CMD_STATUS_E = 338 /* 0x152 */,
+ WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 /* 0x153 */,
+ WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 /* 0x154 */,
+ WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 /* 0x155 */,
+ WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 /* 0x156 */,
+ WIFIREO_TO_PPE_RING_E = 343 /* 0x157 */,
+ WIFIRX_MPDU_INFO_E = 344 /* 0x158 */,
+ WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 /* 0x159 */,
+ WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 /* 0x15a */,
+ WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 /* 0x15b */,
+ WIFIRX_PPDU_START_USER_INFO_E = 348 /* 0x15c */,
+ WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 /* 0x15d */,
+ WIFIRX_RING_MASK_E = 350 /* 0x15e */,
+ WIFIWHO_CLASSIFY_INFO_E = 351 /* 0x15f */,
+ WIFITXPT_CLASSIFY_INFO_E = 352 /* 0x160 */,
+ WIFIRXPT_CLASSIFY_INFO_E = 353 /* 0x161 */,
+ WIFITX_FLOW_SEARCH_ENTRY_E = 354 /* 0x162 */,
+ WIFIRX_FLOW_SEARCH_ENTRY_E = 355 /* 0x163 */,
+ WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 /* 0x164 */,
+ WIFICOEX_MAC_NAP_E = 357 /* 0x165 */,
+ WIFIMACRX_ABORT_REQUEST_INFO_E = 358 /* 0x166 */,
+ WIFIMACTX_ABORT_REQUEST_INFO_E = 359 /* 0x167 */,
+ WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 /* 0x168 */,
+ WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 /* 0x169 */,
+ WIFIRXPCU_PPDU_END_INFO_E = 362 /* 0x16a */,
+ WIFIWHO_MESH_CONTROL_E = 363 /* 0x16b */,
+ WIFIL_SIG_A_INFO_E = 364 /* 0x16c */,
+ WIFIL_SIG_B_INFO_E = 365 /* 0x16d */,
+ WIFIHT_SIG_INFO_E = 366 /* 0x16e */,
+ WIFIVHT_SIG_A_INFO_E = 367 /* 0x16f */,
+ WIFIVHT_SIG_B_SU20_INFO_E = 368 /* 0x170 */,
+ WIFIVHT_SIG_B_SU40_INFO_E = 369 /* 0x171 */,
+ WIFIVHT_SIG_B_SU80_INFO_E = 370 /* 0x172 */,
+ WIFIVHT_SIG_B_SU160_INFO_E = 371 /* 0x173 */,
+ WIFIVHT_SIG_B_MU20_INFO_E = 372 /* 0x174 */,
+ WIFIVHT_SIG_B_MU40_INFO_E = 373 /* 0x175 */,
+ WIFIVHT_SIG_B_MU80_INFO_E = 374 /* 0x176 */,
+ WIFIVHT_SIG_B_MU160_INFO_E = 375 /* 0x177 */,
+ WIFISERVICE_INFO_E = 376 /* 0x178 */,
+ WIFIHE_SIG_A_SU_INFO_E = 377 /* 0x179 */,
+ WIFIHE_SIG_A_MU_DL_INFO_E = 378 /* 0x17a */,
+ WIFIHE_SIG_A_MU_UL_INFO_E = 379 /* 0x17b */,
+ WIFIHE_SIG_B1_MU_INFO_E = 380 /* 0x17c */,
+ WIFIHE_SIG_B2_MU_INFO_E = 381 /* 0x17d */,
+ WIFIHE_SIG_B2_OFDMA_INFO_E = 382 /* 0x17e */,
+ WIFIPDG_SW_MODE_BW_START_E = 383 /* 0x17f */,
+ WIFIPDG_SW_MODE_BW_END_E = 384 /* 0x180 */,
+ WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 /* 0x181 */,
+ WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 /* 0x182 */,
+ WIFISCHEDULER_END_E = 387 /* 0x183 */,
+ WIFIPEER_TABLE_ENTRY_E = 388 /* 0x184 */,
+ WIFISW_PEER_INFO_E = 389 /* 0x185 */,
+ WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 /* 0x186 */,
+ WIFITCL_CCE_CLASSIFY_INFO_E = 391 /* 0x187 */,
+ WIFIRXOLE_CCE_INFO_E = 392 /* 0x188 */,
+ WIFITCL_CCE_INFO_E = 393 /* 0x189 */,
+ WIFITCL_CCE_SUPERRULE_E = 394 /* 0x18a */,
+ WIFICCE_RULE_E = 395 /* 0x18b */,
+ WIFIRX_PPDU_START_DROPPED_E = 396 /* 0x18c */,
+ WIFIRX_PPDU_END_DROPPED_E = 397 /* 0x18d */,
+ WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 /* 0x18e */,
+ WIFIRX_MPDU_START_DROPPED_E = 399 /* 0x18f */,
+ WIFIRX_MSDU_START_DROPPED_E = 400 /* 0x190 */,
+ WIFIRX_MSDU_END_DROPPED_E = 401 /* 0x191 */,
+ WIFIRX_MPDU_END_DROPPED_E = 402 /* 0x192 */,
+ WIFIRX_ATTENTION_DROPPED_E = 403 /* 0x193 */,
+ WIFITXPCU_USER_SETUP_E = 404 /* 0x194 */,
+ WIFIRXPCU_USER_SETUP_EXT_E = 405 /* 0x195 */,
+ WIFICE_SRC_DESC_E = 406 /* 0x196 */,
+ WIFICE_STAT_DESC_E = 407 /* 0x197 */,
+ WIFIRXOLE_CCE_SUPERRULE_E = 408 /* 0x198 */,
+ WIFITX_RATE_STATS_INFO_E = 409 /* 0x199 */,
+ WIFICMD_PART_0_END_E = 410 /* 0x19a */,
+ WIFIMACTX_SYNTH_ON_E = 411 /* 0x19b */,
+ WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 /* 0x19c */,
+ WIFITQM_MPDU_GLOBAL_START_E = 413 /* 0x19d */,
+ WIFIEXAMPLE_TLV_32_E = 414 /* 0x19e */,
+ WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 /* 0x19f */,
+ WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 /* 0x1a0 */,
+ WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 /* 0x1a1 */,
+ WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */,
+ WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 /* 0x1a3 */,
+ WIFICE_DST_DESC_E = 420 /* 0x1a4 */,
+ WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 421 /* 0x1a5 */,
+ WIFITQM_2_SCH_MPDU_AVAILABLE_E = 422 /* 0x1a6 */,
+ WIFIPDG_TRIG_RESPONSE_E = 423 /* 0x1a7 */,
+ WIFITRIGGER_RESPONSE_TX_DONE_E = 424 /* 0x1a8 */,
+ WIFIABORT_FROM_PHYRX_DETAILS_E = 425 /* 0x1a9 */,
+ WIFISCH_TQM_CMD_WRAPPER_E = 426 /* 0x1aa */,
+ WIFIMPDUS_AVAILABLE_E = 427 /* 0x1ab */,
+ WIFIRECEIVED_RESPONSE_INFO_PART2_E = 428 /* 0x1ac */,
+ WIFIPHYRX_PKT_END_INFO_E = 429 /* 0x1ad */,
+ WIFIPHYRX_TX_START_TIMING_E = 430 /* 0x1ae */,
+ WIFITXPCU_PREAMBLE_DONE_E = 431 /* 0x1af */,
+ WIFINDP_PREAMBLE_DONE_E = 432 /* 0x1b0 */,
+ WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 433 /* 0x1b1 */,
+ WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 434 /* 0x1b2 */,
+ WIFIMACTX_CLEAR_PREV_TX_INFO_E = 435 /* 0x1b3 */,
+ WIFITX_PUNCTURE_SETUP_E = 436 /* 0x1b4 */,
+ WIFITX_PUNCTURE_PATTERN_E = 437 /* 0x1b5 */,
+ WIFIR2R_STATUS_END_E = 438 /* 0x1b6 */,
+ WIFIMACTX_PREFETCH_CV_COMMON_E = 439 /* 0x1b7 */,
+ WIFIEND_OF_FLUSH_MARKER_E = 440 /* 0x1b8 */,
+ WIFIUPLINK_COMMON_INFO_PUNC_E = 441 /* 0x1b9 */,
+ WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 442 /* 0x1ba */,
+ WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 443 /* 0x1bb */,
+ WIFIRECEIVED_RESPONSE_USER_7_0_E = 444 /* 0x1bc */,
+ WIFIRECEIVED_RESPONSE_USER_15_8_E = 445 /* 0x1bd */,
+ WIFIRECEIVED_RESPONSE_USER_23_16_E = 446 /* 0x1be */,
+ WIFIRECEIVED_RESPONSE_USER_31_24_E = 447 /* 0x1bf */,
+ WIFIRECEIVED_RESPONSE_USER_36_32_E = 448 /* 0x1c0 */,
+ WIFIRECEIVED_RESPONSE_USER_INFO_E = 449 /* 0x1c1 */,
+ WIFITX_LOOPBACK_SETUP_E = 450 /* 0x1c2 */,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 451 /* 0x1c3 */,
+ WIFISCH_WAIT_INSTR_TX_PATH_E = 452 /* 0x1c4 */,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 453 /* 0x1c5 */,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 454 /* 0x1c6 */,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 455 /* 0x1c7 */,
+ WIFITX_WUR_DATA_E = 456 /* 0x1c8 */,
+ WIFIRX_PPDU_END_START_E = 457 /* 0x1c9 */,
+ WIFIRX_PPDU_END_MIDDLE_E = 458 /* 0x1ca */,
+ WIFIRX_PPDU_END_LAST_E = 459 /* 0x1cb */,
+ WIFIRECEIVE_USER_INFO_L1_E = 460 /* 0x1cc */,
+ WIFIMIMO_CONTROL_INFO_L1_E = 461 /* 0x1cd */,
+ WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 462 /* 0x1ce */,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 463 /* 0x1cf */,
+ WIFISRP_INFO_E = 464 /* 0x1d0 */,
+ WIFIOBSS_SR_INFO_E = 465 /* 0x1d1 */,
+ WIFISCHEDULER_SW_MSG_STATUS_E = 466 /* 0x1d2 */,
+ WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 467 /* 0x1d3 */,
+ WIFIRXPCU_SETUP_COMPLETE_E = 468 /* 0x1d4 */,
+ WIFISNOOP_PPDU_START_E = 469 /* 0x1d5 */,
+ WIFISNOOP_MPDU_USR_DBG_INFO_E = 470 /* 0x1d6 */,
+ WIFISNOOP_MSDU_USR_DBG_INFO_E = 471 /* 0x1d7 */,
+ WIFISNOOP_MSDU_USR_DATA_E = 472 /* 0x1d8 */,
+ WIFISNOOP_MPDU_USR_STAT_INFO_E = 473 /* 0x1d9 */,
+ WIFISNOOP_PPDU_END_E = 474 /* 0x1da */,
+ WIFISNOOP_SPARE_E = 475 /* 0x1db */,
+ WIFIMACTX_PREFETCH_CV_BULK_E = 476 /* 0x1dc */,
+ WIFIMACTX_PREFETCH_CV_BULK_USER_E = 477 /* 0x1dd */,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478 /* 0x1de */,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479 /* 0x1df */,
+ WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480 /* 0x1e0 */,
+ WIFISW_MONITOR_RING_E = 481 /* 0x1e1 */,
+ WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482 /* 0x1e2 */,
+ WIFISCH_TLV_WRAPPER_E = 483 /* 0x1e3 */,
+ WIFISCHEDULER_STATUS_WRAPPER_E = 484 /* 0x1e4 */,
+ WIFITLV_BASE_E = 511 /* 0x1ff */
+
+} tlv_tag_def__e; ///< tlv_tag_def Enum Type
+
+#endif // _TLV_TAG_DEF_
diff --git a/hw/qca5018/tx_msdu_extension.h b/hw/qca5018/tx_msdu_extension.h
new file mode 100644
index 0000000..e708530
--- /dev/null
+++ b/hw/qca5018/tx_msdu_extension.h
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 tso_enable[0], reserved_0a[6:1], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25]
+// 1 l2_length[15:0], ip_length[31:16]
+// 2 tcp_seq_number[31:0]
+// 3 ip_identification[15:0], udp_length[31:16]
+// 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30]
+// 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17]
+// 6 buf0_ptr_31_0[31:0]
+// 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16]
+// 8 buf1_ptr_31_0[31:0]
+// 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16]
+// 10 buf2_ptr_31_0[31:0]
+// 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16]
+// 12 buf3_ptr_31_0[31:0]
+// 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16]
+// 14 buf4_ptr_31_0[31:0]
+// 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16]
+// 16 buf5_ptr_31_0[31:0]
+// 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+ uint32_t tso_enable : 1, //[0]
+ reserved_0a : 6, //[6:1]
+ tcp_flag : 9, //[15:7]
+ tcp_flag_mask : 9, //[24:16]
+ reserved_0b : 7; //[31:25]
+ uint32_t l2_length : 16, //[15:0]
+ ip_length : 16; //[31:16]
+ uint32_t tcp_seq_number : 32; //[31:0]
+ uint32_t ip_identification : 16, //[15:0]
+ udp_length : 16; //[31:16]
+ uint32_t checksum_offset : 14, //[13:0]
+ partial_checksum_en : 1, //[14]
+ reserved_4a : 1, //[15]
+ payload_start_offset : 14, //[29:16]
+ reserved_4b : 2; //[31:30]
+ uint32_t payload_end_offset : 14, //[13:0]
+ reserved_5a : 2, //[15:14]
+ wds : 1, //[16]
+ reserved_5b : 15; //[31:17]
+ uint32_t buf0_ptr_31_0 : 32; //[31:0]
+ uint32_t buf0_ptr_39_32 : 8, //[7:0]
+ reserved_7a : 8, //[15:8]
+ buf0_len : 16; //[31:16]
+ uint32_t buf1_ptr_31_0 : 32; //[31:0]
+ uint32_t buf1_ptr_39_32 : 8, //[7:0]
+ reserved_9a : 8, //[15:8]
+ buf1_len : 16; //[31:16]
+ uint32_t buf2_ptr_31_0 : 32; //[31:0]
+ uint32_t buf2_ptr_39_32 : 8, //[7:0]
+ reserved_11a : 8, //[15:8]
+ buf2_len : 16; //[31:16]
+ uint32_t buf3_ptr_31_0 : 32; //[31:0]
+ uint32_t buf3_ptr_39_32 : 8, //[7:0]
+ reserved_13a : 8, //[15:8]
+ buf3_len : 16; //[31:16]
+ uint32_t buf4_ptr_31_0 : 32; //[31:0]
+ uint32_t buf4_ptr_39_32 : 8, //[7:0]
+ reserved_15a : 8, //[15:8]
+ buf4_len : 16; //[31:16]
+ uint32_t buf5_ptr_31_0 : 32; //[31:0]
+ uint32_t buf5_ptr_39_32 : 8, //[7:0]
+ reserved_17a : 8, //[15:8]
+ buf5_len : 16; //[31:16]
+};
+
+/*
+
+tso_enable
+
+ Enable transmit segmentation offload <legal all>
+
+reserved_0a
+
+ FW will set to 0, MAC will ignore. <legal 0>
+
+tcp_flag
+
+ TCP flags
+
+ {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
+
+tcp_flag_mask
+
+ TCP flag mask. Tcp_flag is inserted into the header
+ based on the mask, if TSO is enabled
+
+reserved_0b
+
+ FW will set to 0, MAC will ignore. <legal 0>
+
+l2_length
+
+ L2 length for the msdu, if TSO is enabled <legal all>
+
+ip_length
+
+ IP length for the msdu, if TSO is enabled <legal all>
+
+tcp_seq_number
+
+ Tcp_seq_number for the msdu, if TSO is enabled <legal
+ all>
+
+ip_identification
+
+ IP_identification for the msdu, if TSO is enabled <legal
+ all>
+
+udp_length
+
+ TXDMA is copies this field into MSDU START TLV
+
+checksum_offset
+
+ The calculated checksum from start offset to end offset
+ will be added to the checksum at the offset given by this
+ field<legal all>
+
+partial_checksum_en
+
+ Partial Checksum Enable Bit.
+
+ <legal 0-1>
+
+reserved_4a
+
+ <Legal 0>
+
+payload_start_offset
+
+ L4 checksum calculations will start fromt this offset
+
+ <Legal all>
+
+reserved_4b
+
+ <Legal 0>
+
+payload_end_offset
+
+ L4 checksum calculations will end at this offset.
+
+ <Legal all>
+
+reserved_5a
+
+ <Legal 0>
+
+wds
+
+ If set the current packet is 4-address frame. Required
+ because an aggregate can include some frames with 3 address
+ format and other frames with 4 address format. Used by the
+ OLE during encapsulation.
+
+ Note: there is also global wds tx control in the
+ TX_PEER_ENTRY
+
+ <legal all>
+
+reserved_5b
+
+ <Legal 0>
+
+buf0_ptr_31_0
+
+ Lower 32 bits of the first buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+
+buf0_ptr_39_32
+
+ Upper 8 bits of the first buffer pointer <legal all>
+
+reserved_7a
+
+ <Legal 0>
+
+buf0_len
+
+ Length of the first buffer <legal all>
+
+buf1_ptr_31_0
+
+ Lower 32 bits of the second buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+
+buf1_ptr_39_32
+
+ Upper 8 bits of the second buffer pointer <legal all>
+
+reserved_9a
+
+ <Legal 0>
+
+buf1_len
+
+ Length of the second buffer <legal all>
+
+buf2_ptr_31_0
+
+ Lower 32 bits of the third buffer pointer
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+
+buf2_ptr_39_32
+
+ Upper 8 bits of the third buffer pointer <legal all>
+
+reserved_11a
+
+ <Legal 0>
+
+buf2_len
+
+ Length of the third buffer <legal all>
+
+buf3_ptr_31_0
+
+ Lower 32 bits of the fourth buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+
+buf3_ptr_39_32
+
+ Upper 8 bits of the fourth buffer pointer <legal all>
+
+reserved_13a
+
+ <Legal 0>
+
+buf3_len
+
+ Length of the fourth buffer <legal all>
+
+buf4_ptr_31_0
+
+ Lower 32 bits of the fifth buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+
+buf4_ptr_39_32
+
+ Upper 8 bits of the fifth buffer pointer <legal all>
+
+reserved_15a
+
+ <Legal 0>
+
+buf4_len
+
+ Length of the fifth buffer <legal all>
+
+buf5_ptr_31_0
+
+ Lower 32 bits of the sixth buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+
+buf5_ptr_39_32
+
+ Upper 8 bits of the sixth buffer pointer <legal all>
+
+reserved_17a
+
+ <Legal 0>
+
+buf5_len
+
+ Length of the sixth buffer <legal all>
+*/
+
+
+/* Description TX_MSDU_EXTENSION_0_TSO_ENABLE
+
+ Enable transmit segmentation offload <legal all>
+*/
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001
+
+/* Description TX_MSDU_EXTENSION_0_RESERVED_0A
+
+ FW will set to 0, MAC will ignore. <legal 0>
+*/
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e
+
+/* Description TX_MSDU_EXTENSION_0_TCP_FLAG
+
+ TCP flags
+
+ {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
+*/
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80
+
+/* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK
+
+ TCP flag mask. Tcp_flag is inserted into the header
+ based on the mask, if TSO is enabled
+*/
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000
+
+/* Description TX_MSDU_EXTENSION_0_RESERVED_0B
+
+ FW will set to 0, MAC will ignore. <legal 0>
+*/
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000
+
+/* Description TX_MSDU_EXTENSION_1_L2_LENGTH
+
+ L2 length for the msdu, if TSO is enabled <legal all>
+*/
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff
+
+/* Description TX_MSDU_EXTENSION_1_IP_LENGTH
+
+ IP length for the msdu, if TSO is enabled <legal all>
+*/
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000
+
+/* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER
+
+ Tcp_seq_number for the msdu, if TSO is enabled <legal
+ all>
+*/
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff
+
+/* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION
+
+ IP_identification for the msdu, if TSO is enabled <legal
+ all>
+*/
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff
+
+/* Description TX_MSDU_EXTENSION_3_UDP_LENGTH
+
+ TXDMA is copies this field into MSDU START TLV
+*/
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000
+
+/* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET
+
+ The calculated checksum from start offset to end offset
+ will be added to the checksum at the offset given by this
+ field<legal all>
+*/
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff
+
+/* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN
+
+ Partial Checksum Enable Bit.
+
+ <legal 0-1>
+*/
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000
+
+/* Description TX_MSDU_EXTENSION_4_RESERVED_4A
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000
+
+/* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET
+
+ L4 checksum calculations will start fromt this offset
+
+ <Legal all>
+*/
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000
+
+/* Description TX_MSDU_EXTENSION_4_RESERVED_4B
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000
+
+/* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET
+
+ L4 checksum calculations will end at this offset.
+
+ <Legal all>
+*/
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff
+
+/* Description TX_MSDU_EXTENSION_5_RESERVED_5A
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000
+
+/* Description TX_MSDU_EXTENSION_5_WDS
+
+ If set the current packet is 4-address frame. Required
+ because an aggregate can include some frames with 3 address
+ format and other frames with 4 address format. Used by the
+ OLE during encapsulation.
+
+ Note: there is also global wds tx control in the
+ TX_PEER_ENTRY
+
+ <legal all>
+*/
+#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_5_WDS_LSB 16
+#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000
+
+/* Description TX_MSDU_EXTENSION_5_RESERVED_5B
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000
+
+/* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0
+
+ Lower 32 bits of the first buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+*/
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff
+
+/* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32
+
+ Upper 8 bits of the first buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff
+
+/* Description TX_MSDU_EXTENSION_7_RESERVED_7A
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00
+
+/* Description TX_MSDU_EXTENSION_7_BUF0_LEN
+
+ Length of the first buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000
+
+/* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0
+
+ Lower 32 bits of the second buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+*/
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff
+
+/* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32
+
+ Upper 8 bits of the second buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff
+
+/* Description TX_MSDU_EXTENSION_9_RESERVED_9A
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00
+
+/* Description TX_MSDU_EXTENSION_9_BUF1_LEN
+
+ Length of the second buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000
+
+/* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0
+
+ Lower 32 bits of the third buffer pointer
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+*/
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff
+
+/* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32
+
+ Upper 8 bits of the third buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff
+
+/* Description TX_MSDU_EXTENSION_11_RESERVED_11A
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00
+
+/* Description TX_MSDU_EXTENSION_11_BUF2_LEN
+
+ Length of the third buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000
+
+/* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0
+
+ Lower 32 bits of the fourth buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+*/
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff
+
+/* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32
+
+ Upper 8 bits of the fourth buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff
+
+/* Description TX_MSDU_EXTENSION_13_RESERVED_13A
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00
+
+/* Description TX_MSDU_EXTENSION_13_BUF3_LEN
+
+ Length of the fourth buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000
+
+/* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0
+
+ Lower 32 bits of the fifth buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+*/
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff
+
+/* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32
+
+ Upper 8 bits of the fifth buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff
+
+/* Description TX_MSDU_EXTENSION_15_RESERVED_15A
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00
+
+/* Description TX_MSDU_EXTENSION_15_BUF4_LEN
+
+ Length of the fifth buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000
+
+/* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0
+
+ Lower 32 bits of the sixth buffer pointer
+
+
+
+ NOTE: SW/FW manages the 'cookie' info related to this
+ buffer together with the 'cookie' info for this
+ MSDU_EXTENSION descriptor
+
+ <legal all>
+*/
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff
+
+/* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32
+
+ Upper 8 bits of the sixth buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff
+
+/* Description TX_MSDU_EXTENSION_17_RESERVED_17A
+
+ <Legal 0>
+*/
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00
+
+/* Description TX_MSDU_EXTENSION_17_BUF5_LEN
+
+ Length of the sixth buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000
+
+
+#endif // _TX_MSDU_EXTENSION_H_
diff --git a/hw/qca5018/tx_rate_stats_info.h b/hw/qca5018/tx_rate_stats_info.h
new file mode 100644
index 0000000..051090c
--- /dev/null
+++ b/hw/qca5018/tx_rate_stats_info.h
@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 tx_rate_stats_info_valid[0], transmit_bw[2:1], transmit_pkt_type[6:3], transmit_stbc[7], transmit_ldpc[8], transmit_sgi[10:9], transmit_mcs[14:11], ofdma_transmission[15], tones_in_ru[27:16], reserved_0a[31:28]
+// 1 ppdu_transmission_tsf[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+ uint32_t tx_rate_stats_info_valid : 1, //[0]
+ transmit_bw : 2, //[2:1]
+ transmit_pkt_type : 4, //[6:3]
+ transmit_stbc : 1, //[7]
+ transmit_ldpc : 1, //[8]
+ transmit_sgi : 2, //[10:9]
+ transmit_mcs : 4, //[14:11]
+ ofdma_transmission : 1, //[15]
+ tones_in_ru : 12, //[27:16]
+ reserved_0a : 4; //[31:28]
+ uint32_t ppdu_transmission_tsf : 32; //[31:0]
+};
+
+/*
+
+tx_rate_stats_info_valid
+
+ When set all other fields in this STRUCT contain valid
+ info.
+
+
+
+
+ <legal all>
+
+transmit_bw
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Indicates the BW of the upcoming transmission that shall
+ likely start in about 3 -4 us on the medium
+
+
+
+ <enum 0 transmit_bw_20_MHz>
+
+ <enum 1 transmit_bw_40_MHz>
+
+ <enum 2 transmit_bw_80_MHz>
+
+ <enum 3 transmit_bw_160_MHz>
+
+
+
+ <legal all>
+
+transmit_pkt_type
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ The packet type
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+
+transmit_stbc
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ When set, STBC transmission rate was used.
+
+transmit_ldpc
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ When set, use LDPC transmission rates
+
+transmit_sgi
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ <enum 0 0_8_us_sgi > Legacy normal GI. Can also be
+ used for HE
+
+ <enum 1 0_4_us_sgi > Legacy short GI. Can also be
+ used for HE
+
+ <enum 2 1_6_us_sgi > HE related GI
+
+ <enum 3 3_2_us_sgi > HE related GI
+
+ <legal 0 - 3>
+
+transmit_mcs
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ For details, refer to MCS_TYPE description
+
+ <legal all>
+
+ofdma_transmission
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+
+
+ Set when the transmission was an OFDMA transmission (DL
+ or UL).
+
+ <legal all>
+
+tones_in_ru
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ The number of tones in the RU used.
+
+ <legal all>
+
+reserved_0a
+
+ <legal 0>
+
+ppdu_transmission_tsf
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Based on a HWSCH configuration register setting, this
+ field either contains:
+
+
+
+ Lower 32 bits of the TSF, snapshot of this value when
+ transmission of the PPDU containing the frame finished.
+
+ OR
+
+ Lower 32 bits of the TSF, snapshot of this value when
+ transmission of the PPDU containing the frame started
+
+
+
+ <legal all>
+*/
+
+
+/* Description TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID
+
+ When set all other fields in this STRUCT contain valid
+ info.
+
+
+
+
+ <legal all>
+*/
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
+
+/* Description TX_RATE_STATS_INFO_0_TRANSMIT_BW
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Indicates the BW of the upcoming transmission that shall
+ likely start in about 3 -4 us on the medium
+
+
+
+ <enum 0 transmit_bw_20_MHz>
+
+ <enum 1 transmit_bw_40_MHz>
+
+ <enum 2 transmit_bw_80_MHz>
+
+ <enum 3 transmit_bw_160_MHz>
+
+
+
+ <legal all>
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006
+
+/* Description TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ The packet type
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078
+
+/* Description TX_RATE_STATS_INFO_0_TRANSMIT_STBC
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ When set, STBC transmission rate was used.
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080
+
+/* Description TX_RATE_STATS_INFO_0_TRANSMIT_LDPC
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ When set, use LDPC transmission rates
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100
+
+/* Description TX_RATE_STATS_INFO_0_TRANSMIT_SGI
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ <enum 0 0_8_us_sgi > Legacy normal GI. Can also be
+ used for HE
+
+ <enum 1 0_4_us_sgi > Legacy short GI. Can also be
+ used for HE
+
+ <enum 2 1_6_us_sgi > HE related GI
+
+ <enum 3 3_2_us_sgi > HE related GI
+
+ <legal 0 - 3>
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600
+
+/* Description TX_RATE_STATS_INFO_0_TRANSMIT_MCS
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ For details, refer to MCS_TYPE description
+
+ <legal all>
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800
+
+/* Description TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+
+
+ Set when the transmission was an OFDMA transmission (DL
+ or UL).
+
+ <legal all>
+*/
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000
+
+/* Description TX_RATE_STATS_INFO_0_TONES_IN_RU
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ The number of tones in the RU used.
+
+ <legal all>
+*/
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000
+
+/* Description TX_RATE_STATS_INFO_0_RESERVED_0A
+
+ <legal 0>
+*/
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000
+
+/* Description TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Based on a HWSCH configuration register setting, this
+ field either contains:
+
+
+
+ Lower 32 bits of the TSF, snapshot of this value when
+ transmission of the PPDU containing the frame finished.
+
+ OR
+
+ Lower 32 bits of the TSF, snapshot of this value when
+ transmission of the PPDU containing the frame started
+
+
+
+ <legal all>
+*/
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_LSB 0
+#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
+
+
+#endif // _TX_RATE_STATS_INFO_H_
diff --git a/hw/qca5018/uniform_descriptor_header.h b/hw/qca5018/uniform_descriptor_header.h
new file mode 100644
index 0000000..17dc95a
--- /dev/null
+++ b/hw/qca5018/uniform_descriptor_header.h
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 owner[3:0], buffer_type[7:4], reserved_0a[31:8]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+ uint32_t owner : 4, //[3:0]
+ buffer_type : 4, //[7:4]
+ reserved_0a : 24; //[31:8]
+};
+
+/*
+
+owner
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ The owner of this data structure:
+
+ <enum 0 WBM_owned> Buffer Manager currently owns this
+ data structure.
+
+ <enum 1 SW_OR_FW_owned> Software of FW currently owns
+ this data structure.
+
+ <enum 2 TQM_owned> Transmit Queue Manager currently owns
+ this data structure.
+
+ <enum 3 RXDMA_owned> Receive DMA currently owns this
+ data structure.
+
+ <enum 4 REO_owned> Reorder currently owns this data
+ structure.
+
+ <enum 5 SWITCH_owned> SWITCH currently owns this data
+ structure.
+
+
+
+ <legal 0-5>
+
+buffer_type
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ Field describing what contents format is of this
+ descriptor
+
+
+
+ <enum 0 Transmit_MSDU_Link_descriptor >
+
+ <enum 1 Transmit_MPDU_Link_descriptor >
+
+ <enum 2 Transmit_MPDU_Queue_head_descriptor>
+
+ <enum 3 Transmit_MPDU_Queue_ext_descriptor>
+
+ <enum 4 Transmit_flow_descriptor>
+
+ <enum 5 Transmit_buffer > NOT TO BE USED:
+
+
+
+ <enum 6 Receive_MSDU_Link_descriptor >
+
+ <enum 7 Receive_MPDU_Link_descriptor >
+
+ <enum 8 Receive_REO_queue_descriptor >
+
+ <enum 9 Receive_REO_queue_ext_descriptor >
+
+
+
+ <enum 10 Receive_buffer >
+
+
+
+ <enum 11 Idle_link_list_entry>
+
+
+
+ <legal 0-11>
+
+reserved_0a
+
+ <legal 0>
+*/
+
+
+/* Description UNIFORM_DESCRIPTOR_HEADER_0_OWNER
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ The owner of this data structure:
+
+ <enum 0 WBM_owned> Buffer Manager currently owns this
+ data structure.
+
+ <enum 1 SW_OR_FW_owned> Software of FW currently owns
+ this data structure.
+
+ <enum 2 TQM_owned> Transmit Queue Manager currently owns
+ this data structure.
+
+ <enum 3 RXDMA_owned> Receive DMA currently owns this
+ data structure.
+
+ <enum 4 REO_owned> Reorder currently owns this data
+ structure.
+
+ <enum 5 SWITCH_owned> SWITCH currently owns this data
+ structure.
+
+
+
+ <legal 0-5>
+*/
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f
+
+/* Description UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE
+
+ Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+ Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+
+
+
+ Field describing what contents format is of this
+ descriptor
+
+
+
+ <enum 0 Transmit_MSDU_Link_descriptor >
+
+ <enum 1 Transmit_MPDU_Link_descriptor >
+
+ <enum 2 Transmit_MPDU_Queue_head_descriptor>
+
+ <enum 3 Transmit_MPDU_Queue_ext_descriptor>
+
+ <enum 4 Transmit_flow_descriptor>
+
+ <enum 5 Transmit_buffer > NOT TO BE USED:
+
+
+
+ <enum 6 Receive_MSDU_Link_descriptor >
+
+ <enum 7 Receive_MPDU_Link_descriptor >
+
+ <enum 8 Receive_REO_queue_descriptor >
+
+ <enum 9 Receive_REO_queue_ext_descriptor >
+
+
+
+ <enum 10 Receive_buffer >
+
+
+
+ <enum 11 Idle_link_list_entry>
+
+
+
+ <legal 0-11>
+*/
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0
+
+/* Description UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A
+
+ <legal 0>
+*/
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00
+
+
+#endif // _UNIFORM_DESCRIPTOR_HEADER_H_
diff --git a/hw/qca5018/uniform_reo_cmd_header.h b/hw/qca5018/uniform_reo_cmd_header.h
new file mode 100644
index 0000000..79f7463
--- /dev/null
+++ b/hw/qca5018/uniform_reo_cmd_header.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _UNIFORM_REO_CMD_HEADER_H_
+#define _UNIFORM_REO_CMD_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 reo_cmd_number[15:0], reo_status_required[16], reserved_0a[31:17]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
+
+struct uniform_reo_cmd_header {
+ uint32_t reo_cmd_number : 16, //[15:0]
+ reo_status_required : 1, //[16]
+ reserved_0a : 15; //[31:17]
+};
+
+/*
+
+reo_cmd_number
+
+ Consumer: REO/SW/DEBUG
+
+ Producer: SW
+
+
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statusses
+
+
+
+
+
+ <legal all>
+
+reo_status_required
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ <enum 0 NoStatus> REO does not need to generate a status
+ TLV for the execution of this command
+
+ <enum 1 StatusRequired> REO shall generate a status TLV
+ for the execution of this command
+
+
+
+ <legal all>
+
+reserved_0a
+
+ <legal 0>
+*/
+
+
+/* Description UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER
+
+ Consumer: REO/SW/DEBUG
+
+ Producer: SW
+
+
+
+ This number can be used by SW to track, identify and
+ link the created commands with the command statusses
+
+
+
+
+
+ <legal all>
+*/
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff
+
+/* Description UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED
+
+ Consumer: REO
+
+ Producer: SW
+
+
+
+ <enum 0 NoStatus> REO does not need to generate a status
+ TLV for the execution of this command
+
+ <enum 1 StatusRequired> REO shall generate a status TLV
+ for the execution of this command
+
+
+
+ <legal all>
+*/
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000
+
+/* Description UNIFORM_REO_CMD_HEADER_0_RESERVED_0A
+
+ <legal 0>
+*/
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000
+
+
+#endif // _UNIFORM_REO_CMD_HEADER_H_
diff --git a/hw/qca5018/uniform_reo_status_header.h b/hw/qca5018/uniform_reo_status_header.h
new file mode 100644
index 0000000..e2465a0
--- /dev/null
+++ b/hw/qca5018/uniform_reo_status_header.h
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _UNIFORM_REO_STATUS_HEADER_H_
+#define _UNIFORM_REO_STATUS_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 reo_status_number[15:0], cmd_execution_time[25:16], reo_cmd_execution_status[27:26], reserved_0a[31:28]
+// 1 timestamp[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
+
+struct uniform_reo_status_header {
+ uint32_t reo_status_number : 16, //[15:0]
+ cmd_execution_time : 10, //[25:16]
+ reo_cmd_execution_status : 2, //[27:26]
+ reserved_0a : 4; //[31:28]
+ uint32_t timestamp : 32; //[31:0]
+};
+
+/*
+
+reo_status_number
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+
+cmd_execution_time
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+
+reo_cmd_execution_status
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+
+reserved_0a
+
+ <legal 0>
+
+timestamp
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+
+
+/* Description UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER
+
+ Consumer: SW , DEBUG
+
+ Producer: REO
+
+
+
+ The value in this field is equal to value of the
+ 'REO_CMD_Number' field the REO command
+
+
+
+ This field helps to correlate the statuses with the REO
+ commands.
+
+
+
+ <legal all>
+*/
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff
+
+/* Description UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ The amount of time REO took to excecute the command.
+ Note that this time does not include the duration of the
+ command waiting in the command ring, before the execution
+ started.
+
+
+
+ In us.
+
+
+
+ <legal all>
+*/
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000
+
+/* Description UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS
+
+ Consumer: DEBUG
+
+ Producer: REO
+
+
+
+ Execution status of the command.
+
+
+
+ <enum 0 reo_successful_execution> Command has
+ successfully be executed
+
+ <enum 1 reo_blocked_execution> Command could not be
+ executed as the queue or cache was blocked
+
+ <enum 2 reo_failed_execution> Command has encountered
+ problems when executing, like the queue descriptor not being
+ valid. None of the status fields in the entire STATUS TLV
+ are valid.
+
+ <enum 3 reo_resource_blocked> Command is NOT executed
+ because one or more descriptors were blocked. This is SW
+ programming mistake.
+
+ None of the status fields in the entire STATUS TLV are
+ valid.
+
+
+
+ <legal 0-3>
+*/
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000
+
+/* Description UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A
+
+ <legal 0>
+*/
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000
+
+/* Description UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP
+
+ Timestamp at the moment that this status report is
+ written.
+
+
+
+ <legal all>
+*/
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff
+
+
+#endif // _UNIFORM_REO_STATUS_HEADER_H_
diff --git a/hw/qca5018/vht_sig_a_info.h b/hw/qca5018/vht_sig_a_info.h
new file mode 100644
index 0000000..8e1c343
--- /dev/null
+++ b/hw/qca5018/vht_sig_a_info.h
@@ -0,0 +1,628 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _VHT_SIG_A_INFO_H_
+#define _VHT_SIG_A_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 bandwidth[1:0], vhta_reserved_0[2], stbc[3], group_id[9:4], n_sts[21:10], txop_ps_not_allowed[22], vhta_reserved_0b[23], reserved_0[31:24]
+// 1 gi_setting[1:0], su_mu_coding[2], ldpc_extra_symbol[3], mcs[7:4], beamformed[8], vhta_reserved_1[9], crc[17:10], tail[23:18], reserved_1[31:24]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2
+
+struct vht_sig_a_info {
+ uint32_t bandwidth : 2, //[1:0]
+ vhta_reserved_0 : 1, //[2]
+ stbc : 1, //[3]
+ group_id : 6, //[9:4]
+ n_sts : 12, //[21:10]
+ txop_ps_not_allowed : 1, //[22]
+ vhta_reserved_0b : 1, //[23]
+ reserved_0 : 8; //[31:24]
+ uint32_t gi_setting : 2, //[1:0]
+ su_mu_coding : 1, //[2]
+ ldpc_extra_symbol : 1, //[3]
+ mcs : 4, //[7:4]
+ beamformed : 1, //[8]
+ vhta_reserved_1 : 1, //[9]
+ crc : 8, //[17:10]
+ tail : 6, //[23:18]
+ reserved_1 : 8; //[31:24]
+};
+
+/*
+
+bandwidth
+
+ Packet bandwidth
+
+
+
+ <enum 0 20_MHZ_11AC>
+
+ <enum 1 40_MHZ_11AC>
+
+ <enum 2 80_MHZ_11AC>
+
+ <enum 3 160_MHZ_11AC>
+
+
+
+ <legal 0-3>
+
+vhta_reserved_0
+
+ Reserved. Set to 1 by MAC, PHY should ignore
+
+ <legal 1>
+
+stbc
+
+ Space time block coding:
+
+ <enum 0 stbc_disabled> Indicates STBC is disabled
+
+ <enum 1 stbc_enabled> Indicates STBC is enabled on
+ all streams
+
+ <legal 0-1>
+
+group_id
+
+ In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed
+ to an AP or to a mesh STA, the Group ID field is set to 0,
+ otherwise it is set to 63. In an NDP PPDU the Group ID is
+ set according to IEEE 802.11ac_D1.0 Section 9.30.6
+ (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID
+ is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID).
+ <legal all>
+
+n_sts
+
+ For MU:
+
+ 3 bits/user with maximum of 4 users (user u uses
+
+ vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2,
+ 3)
+
+ Set to 0 for 0 space time streams
+
+ Set to 1 for 1 space time stream
+
+ Set to 2 for 2 space time streams
+
+ Set to 3 for 3 space time streams
+
+ Set to 4 for 4 space time streams (not supported in Wifi
+ 3.0)
+
+ Values 5-7 are reserved
+
+ In this field, references to user u should be
+ interpreted as MU user u. As described in the previous
+ chapter in this document (see chapter on User number), the
+ MU user value for a given client is defined for each MU
+ group that the client participates in. The MU user number is
+ not related to the internal user number that is used within
+ the BFer.
+
+
+
+
+
+ For SU:
+
+ vht_sig_a[0][12:10]
+
+ Set to 0 for 1 space time stream
+
+ Set to 1 for 2 space time streams
+
+ Set to 2 for 3 space time streams
+
+ Set to 3 for 4 space time streams
+
+ Set to 4 for 5 space time streams
+
+ Set to 5 for 6 space time streams
+
+ Set to 6 for 7 space time streams
+
+ Set to 7 for 8 space time streams
+
+
+
+ vht_sig_a[0][21:13]
+
+ Partial AID:
+
+ Set to the value of the TXVECTOR parameter PARTIAL_AID.
+ Partial AID provides an abbreviated indication of the
+ intended recipient(s) of the frame (see IEEE802.11ac_D1.0
+ Section 9.17a (Partial AID in VHT PPDUs)).
+
+ <legal all>
+
+txop_ps_not_allowed
+
+ E_num 0 txop_ps_allowed Not supported: If set to by
+ VHT AP if it allows non-AP VHT STAs in TXOP power save mode
+ to enter Doze state during a TXOP
+
+ <enum 1 no_txop_ps_allowed> Otherwise
+
+ <legal 1>
+
+vhta_reserved_0b
+
+ Reserved: Should be set to 1 by the MAC and ignored by
+ the PHY <legal 1>
+
+reserved_0
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+
+gi_setting
+
+ <enum 0 normal_gi> Indicates short guard interval
+ is not used in the data field
+
+ <enum 1 short_gi> Indicates short guard interval is
+ used in the data field
+
+ <enum 3 short_gi_ambiguity> Indicates short guard
+ interval is used in the data field and NSYM mod 10 = 9
+
+ NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3
+ (TXTIME and PSDU_LENGTH calculation).
+
+ <legal 0,1,3>
+
+su_mu_coding
+
+ For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For
+ an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then
+ B2 indicates the coding used for user 0; set to 0 for BCC
+ and 1 for LDPC. If the MU[0] NSTS field is 0, then this
+ field is reserved and set to 1
+
+ldpc_extra_symbol
+
+ Set to 1 if the LDPC PPDU encoding process (if an SU
+ PPDU), or at least one LDPC user's PPDU encoding process (if
+ an MU PPDU), results in an extra OFDM symbol (or symbols) as
+ described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
+ (Encoding process for MU PPDUs). Set to 0 otherwise.
+
+mcs
+
+ For SU:
+
+ Set to 0 for BPSK 1/2
+
+ Set to 1 for QPSK 1/2
+
+ Set to 2 for QPSK 3/4
+
+ Set to 3 for 16-QAM 1/2
+
+ Set to 4 for 16-QAM 3/4
+
+ Set to 5 for 64-QAM 2/3
+
+ Set to 6 for 64-QAM 3/4
+
+ Set to 7 for 64-QAM 5/6
+
+ Set to 8 for 256-QAM 3/4
+
+ Set to 9 for 256-QAM 5/6
+
+ For MU:
+
+ If NSTS for user 1 is non-zero, then vht_sig_a[1][4]
+ indicates coding for user 1: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is
+ reserved and set to 1.
+
+ If NSTS for user 2 is non-zero, then vht_sig_a[1][5]
+ indicates coding for user 2: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is
+ reserved and set to 1.
+
+ If NSTS for user 3 is non-zero, then vht_sig_a[1][6]
+ indicates coding for user 3: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is
+ reserved and set to 1.
+
+ vht_sig_a[1][7] is reserved and set to 1
+
+ <legal 0-15>
+
+beamformed
+
+ For SU:
+
+ Set to 1 if a Beamforming steering matrix is applied to
+ the waveform in an SU transmission as described in
+ IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping),
+ set to 0 otherwise.
+
+ For MU:
+
+ Reserved and set to 1
+
+ <legal 0-1>
+
+vhta_reserved_1
+
+ Reserved and set to 1. <legal 1>
+
+crc
+
+ CRC calculated as in IEEE802.11ac_D1.0 Section
+ 19.3.9.4.4 (CRC calculation for HTSIG) with C7 in
+ vht_sig_a[1][10], etc. <legal all>
+
+tail
+
+ Used to terminate the trellis of the convolutional
+ decoder. Set to 0. <legal 0>
+
+reserved_1
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+*/
+
+
+/* Description VHT_SIG_A_INFO_0_BANDWIDTH
+
+ Packet bandwidth
+
+
+
+ <enum 0 20_MHZ_11AC>
+
+ <enum 1 40_MHZ_11AC>
+
+ <enum 2 80_MHZ_11AC>
+
+ <enum 3 160_MHZ_11AC>
+
+
+
+ <legal 0-3>
+*/
+#define VHT_SIG_A_INFO_0_BANDWIDTH_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_BANDWIDTH_LSB 0
+#define VHT_SIG_A_INFO_0_BANDWIDTH_MASK 0x00000003
+
+/* Description VHT_SIG_A_INFO_0_VHTA_RESERVED_0
+
+ Reserved. Set to 1 by MAC, PHY should ignore
+
+ <legal 1>
+*/
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_LSB 2
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_MASK 0x00000004
+
+/* Description VHT_SIG_A_INFO_0_STBC
+
+ Space time block coding:
+
+ <enum 0 stbc_disabled> Indicates STBC is disabled
+
+ <enum 1 stbc_enabled> Indicates STBC is enabled on
+ all streams
+
+ <legal 0-1>
+*/
+#define VHT_SIG_A_INFO_0_STBC_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_STBC_LSB 3
+#define VHT_SIG_A_INFO_0_STBC_MASK 0x00000008
+
+/* Description VHT_SIG_A_INFO_0_GROUP_ID
+
+ In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed
+ to an AP or to a mesh STA, the Group ID field is set to 0,
+ otherwise it is set to 63. In an NDP PPDU the Group ID is
+ set according to IEEE 802.11ac_D1.0 Section 9.30.6
+ (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID
+ is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID).
+ <legal all>
+*/
+#define VHT_SIG_A_INFO_0_GROUP_ID_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_GROUP_ID_LSB 4
+#define VHT_SIG_A_INFO_0_GROUP_ID_MASK 0x000003f0
+
+/* Description VHT_SIG_A_INFO_0_N_STS
+
+ For MU:
+
+ 3 bits/user with maximum of 4 users (user u uses
+
+ vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2,
+ 3)
+
+ Set to 0 for 0 space time streams
+
+ Set to 1 for 1 space time stream
+
+ Set to 2 for 2 space time streams
+
+ Set to 3 for 3 space time streams
+
+ Set to 4 for 4 space time streams (not supported in Wifi
+ 3.0)
+
+ Values 5-7 are reserved
+
+ In this field, references to user u should be
+ interpreted as MU user u. As described in the previous
+ chapter in this document (see chapter on User number), the
+ MU user value for a given client is defined for each MU
+ group that the client participates in. The MU user number is
+ not related to the internal user number that is used within
+ the BFer.
+
+
+
+
+
+ For SU:
+
+ vht_sig_a[0][12:10]
+
+ Set to 0 for 1 space time stream
+
+ Set to 1 for 2 space time streams
+
+ Set to 2 for 3 space time streams
+
+ Set to 3 for 4 space time streams
+
+ Set to 4 for 5 space time streams
+
+ Set to 5 for 6 space time streams
+
+ Set to 6 for 7 space time streams
+
+ Set to 7 for 8 space time streams
+
+
+
+ vht_sig_a[0][21:13]
+
+ Partial AID:
+
+ Set to the value of the TXVECTOR parameter PARTIAL_AID.
+ Partial AID provides an abbreviated indication of the
+ intended recipient(s) of the frame (see IEEE802.11ac_D1.0
+ Section 9.17a (Partial AID in VHT PPDUs)).
+
+ <legal all>
+*/
+#define VHT_SIG_A_INFO_0_N_STS_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_N_STS_LSB 10
+#define VHT_SIG_A_INFO_0_N_STS_MASK 0x003ffc00
+
+/* Description VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED
+
+ E_num 0 txop_ps_allowed Not supported: If set to by
+ VHT AP if it allows non-AP VHT STAs in TXOP power save mode
+ to enter Doze state during a TXOP
+
+ <enum 1 no_txop_ps_allowed> Otherwise
+
+ <legal 1>
+*/
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_LSB 22
+#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_MASK 0x00400000
+
+/* Description VHT_SIG_A_INFO_0_VHTA_RESERVED_0B
+
+ Reserved: Should be set to 1 by the MAC and ignored by
+ the PHY <legal 1>
+*/
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_LSB 23
+#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_MASK 0x00800000
+
+/* Description VHT_SIG_A_INFO_0_RESERVED_0
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+*/
+#define VHT_SIG_A_INFO_0_RESERVED_0_OFFSET 0x00000000
+#define VHT_SIG_A_INFO_0_RESERVED_0_LSB 24
+#define VHT_SIG_A_INFO_0_RESERVED_0_MASK 0xff000000
+
+/* Description VHT_SIG_A_INFO_1_GI_SETTING
+
+ <enum 0 normal_gi> Indicates short guard interval
+ is not used in the data field
+
+ <enum 1 short_gi> Indicates short guard interval is
+ used in the data field
+
+ <enum 3 short_gi_ambiguity> Indicates short guard
+ interval is used in the data field and NSYM mod 10 = 9
+
+ NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3
+ (TXTIME and PSDU_LENGTH calculation).
+
+ <legal 0,1,3>
+*/
+#define VHT_SIG_A_INFO_1_GI_SETTING_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_GI_SETTING_LSB 0
+#define VHT_SIG_A_INFO_1_GI_SETTING_MASK 0x00000003
+
+/* Description VHT_SIG_A_INFO_1_SU_MU_CODING
+
+ For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For
+ an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then
+ B2 indicates the coding used for user 0; set to 0 for BCC
+ and 1 for LDPC. If the MU[0] NSTS field is 0, then this
+ field is reserved and set to 1
+*/
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_LSB 2
+#define VHT_SIG_A_INFO_1_SU_MU_CODING_MASK 0x00000004
+
+/* Description VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL
+
+ Set to 1 if the LDPC PPDU encoding process (if an SU
+ PPDU), or at least one LDPC user's PPDU encoding process (if
+ an MU PPDU), results in an extra OFDM symbol (or symbols) as
+ described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5
+ (Encoding process for MU PPDUs). Set to 0 otherwise.
+*/
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_LSB 3
+#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000008
+
+/* Description VHT_SIG_A_INFO_1_MCS
+
+ For SU:
+
+ Set to 0 for BPSK 1/2
+
+ Set to 1 for QPSK 1/2
+
+ Set to 2 for QPSK 3/4
+
+ Set to 3 for 16-QAM 1/2
+
+ Set to 4 for 16-QAM 3/4
+
+ Set to 5 for 64-QAM 2/3
+
+ Set to 6 for 64-QAM 3/4
+
+ Set to 7 for 64-QAM 5/6
+
+ Set to 8 for 256-QAM 3/4
+
+ Set to 9 for 256-QAM 5/6
+
+ For MU:
+
+ If NSTS for user 1 is non-zero, then vht_sig_a[1][4]
+ indicates coding for user 1: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is
+ reserved and set to 1.
+
+ If NSTS for user 2 is non-zero, then vht_sig_a[1][5]
+ indicates coding for user 2: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is
+ reserved and set to 1.
+
+ If NSTS for user 3 is non-zero, then vht_sig_a[1][6]
+ indicates coding for user 3: set to 0 for BCC, 1 for LDPC.
+
+ If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is
+ reserved and set to 1.
+
+ vht_sig_a[1][7] is reserved and set to 1
+
+ <legal 0-15>
+*/
+#define VHT_SIG_A_INFO_1_MCS_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_MCS_LSB 4
+#define VHT_SIG_A_INFO_1_MCS_MASK 0x000000f0
+
+/* Description VHT_SIG_A_INFO_1_BEAMFORMED
+
+ For SU:
+
+ Set to 1 if a Beamforming steering matrix is applied to
+ the waveform in an SU transmission as described in
+ IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping),
+ set to 0 otherwise.
+
+ For MU:
+
+ Reserved and set to 1
+
+ <legal 0-1>
+*/
+#define VHT_SIG_A_INFO_1_BEAMFORMED_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_BEAMFORMED_LSB 8
+#define VHT_SIG_A_INFO_1_BEAMFORMED_MASK 0x00000100
+
+/* Description VHT_SIG_A_INFO_1_VHTA_RESERVED_1
+
+ Reserved and set to 1. <legal 1>
+*/
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_LSB 9
+#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_MASK 0x00000200
+
+/* Description VHT_SIG_A_INFO_1_CRC
+
+ CRC calculated as in IEEE802.11ac_D1.0 Section
+ 19.3.9.4.4 (CRC calculation for HTSIG) with C7 in
+ vht_sig_a[1][10], etc. <legal all>
+*/
+#define VHT_SIG_A_INFO_1_CRC_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_CRC_LSB 10
+#define VHT_SIG_A_INFO_1_CRC_MASK 0x0003fc00
+
+/* Description VHT_SIG_A_INFO_1_TAIL
+
+ Used to terminate the trellis of the convolutional
+ decoder. Set to 0. <legal 0>
+*/
+#define VHT_SIG_A_INFO_1_TAIL_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_TAIL_LSB 18
+#define VHT_SIG_A_INFO_1_TAIL_MASK 0x00fc0000
+
+/* Description VHT_SIG_A_INFO_1_RESERVED_1
+
+ This field is not part of HT-SIG:
+
+ Reserved: Should be set to 0 by the MAC and ignored by
+ the PHY <legal 0>
+*/
+#define VHT_SIG_A_INFO_1_RESERVED_1_OFFSET 0x00000004
+#define VHT_SIG_A_INFO_1_RESERVED_1_LSB 24
+#define VHT_SIG_A_INFO_1_RESERVED_1_MASK 0xff000000
+
+
+#endif // _VHT_SIG_A_INFO_H_
diff --git a/hw/qca5018/wbm_buffer_ring.h b/hw/qca5018/wbm_buffer_ring.h
new file mode 100644
index 0000000..50fec1d
--- /dev/null
+++ b/hw/qca5018/wbm_buffer_ring.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct buffer_addr_info buf_addr_info;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+ struct buffer_addr_info buf_addr_info;
+};
+
+/*
+
+struct buffer_addr_info buf_addr_info
+
+ Consumer: WBM
+
+ Producer: WBM
+
+
+
+ Details of the physical address of the buffer + source
+ buffer owner + some SW meta data.
+
+ All modules getting this buffer address info, shall keep
+ all the 64 bits of info in this descriptor together and
+ eventually all 64 bits shall be given back to WMB when the
+ buffer is released.
+*/
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info buf_addr_info */
+
+
+/* Description WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+
+#endif // _WBM_BUFFER_RING_H_
diff --git a/hw/qca5018/wbm_link_descriptor_ring.h b/hw/qca5018/wbm_link_descriptor_ring.h
new file mode 100644
index 0000000..afeba40
--- /dev/null
+++ b/hw/qca5018/wbm_link_descriptor_ring.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct buffer_addr_info desc_addr_info;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+ struct buffer_addr_info desc_addr_info;
+};
+
+/*
+
+struct buffer_addr_info desc_addr_info
+
+ Consumer: WBM
+
+ Producer: WBM
+
+
+
+ Details of the physical address of the buffer + source
+ buffer owner + some SW meta data
+
+ All modules getting this link descriptor address info,
+ shall keep all the 64 bits in this descriptor together and
+ eventually all 64 bits shall be given back to WBM when the
+ link descriptor is released.
+*/
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info desc_addr_info */
+
+
+/* Description WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+
+#endif // _WBM_LINK_DESCRIPTOR_RING_H_
diff --git a/hw/qca5018/wbm_reg_seq_hwiobase.h b/hw/qca5018/wbm_reg_seq_hwiobase.h
new file mode 100644
index 0000000..39a7bba
--- /dev/null
+++ b/hw/qca5018/wbm_reg_seq_hwiobase.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
+// User Name:c_landav
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WBM_REG_SEQ_BASE_H__
+#define __WBM_REG_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+#endif
+
diff --git a/hw/qca5018/wbm_reg_seq_hwioreg.h b/hw/qca5018/wbm_reg_seq_hwioreg.h
new file mode 100644
index 0000000..a4d50a5
--- /dev/null
+++ b/hw/qca5018/wbm_reg_seq_hwioreg.h
@@ -0,0 +1,12235 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 2/21/2020
+// User Name:c_landav
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WBM_REG_SEQ_REG_H__
+#define __WBM_REG_SEQ_REG_H__
+
+#include "seq_hwio.h"
+#include "wbm_reg_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block WBM_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register WBM_R0_GENERAL_ENABLE ////
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000)
+#define HWIO_WBM_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000)
+#define HWIO_WBM_R0_GENERAL_ENABLE_RMSK 0x000000ff
+#define HWIO_WBM_R0_GENERAL_ENABLE_SHFT 0
+#define HWIO_WBM_R0_GENERAL_ENABLE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), HWIO_WBM_R0_GENERAL_ENABLE_RMSK)
+#define HWIO_WBM_R0_GENERAL_ENABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask)
+#define HWIO_WBM_R0_GENERAL_ENABLE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_GENERAL_ENABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_GENERAL_ENABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x00000080
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 0x7
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_BMSK 0x00000020
+#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_SHFT 0x5
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_BMSK 0x00000010
+#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_SHFT 0x4
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000008
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_SHFT 0x3
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000004
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_SHFT 0x2
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_SHFT 0x0
+
+//// Register WBM_R0_RELEASE_RING_ENABLE ////
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x) (x+0x00000004)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PHYS(x) (x+0x00000004)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK 0x000000ff
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SHFT 0
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA2_RELEASE_RING_ENABLE_BMSK 0x00000080
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA2_RELEASE_RING_ENABLE_SHFT 0x7
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA1_RELEASE_RING_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA1_RELEASE_RING_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA0_RELEASE_RING_ENABLE_BMSK 0x00000020
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA0_RELEASE_RING_ENABLE_SHFT 0x5
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_FW_RELEASE_RING_ENABLE_BMSK 0x00000010
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_FW_RELEASE_RING_ENABLE_SHFT 0x4
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SW_RELEASE_RING_ENABLE_BMSK 0x00000008
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SW_RELEASE_RING_ENABLE_SHFT 0x3
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00000004
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x2
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_TQM_RELEASE_RING_ENABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_TQM_RELEASE_RING_ENABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PPE_RELEASE_RING_ENABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PPE_RELEASE_RING_ENABLE_SHFT 0x0
+
+//// Register WBM_R0_MSDU_BUFFER_RING_ENABLE ////
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x) (x+0x00000008)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_PHYS(x) (x+0x00000008)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK 0x0000003f
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_SHFT 0
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA2_BUF_RING_ENABLE_BMSK 0x00000020
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA2_BUF_RING_ENABLE_SHFT 0x5
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA1_BUF_RING_ENABLE_BMSK 0x00000010
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA1_BUF_RING_ENABLE_SHFT 0x4
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA0_BUF_RING_ENABLE_BMSK 0x00000008
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA0_BUF_RING_ENABLE_SHFT 0x3
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2FW_BUF_RING_ENABLE_BMSK 0x00000004
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2FW_BUF_RING_ENABLE_SHFT 0x2
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2SW_BUF_RING_ENABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2SW_BUF_RING_ENABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2PPE_BUF_RING_ENABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2PPE_BUF_RING_ENABLE_SHFT 0x0
+
+//// Register WBM_R0_LINK_DESC_RING_ENABLE ////
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x) (x+0x0000000c)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_PHYS(x) (x+0x0000000c)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK 0x0000007f
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_SHFT 0
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA2_LINK_RING_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA2_LINK_RING_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA1_LINK_RING_ENABLE_BMSK 0x00000020
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA1_LINK_RING_ENABLE_SHFT 0x5
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA0_LINK_RING_ENABLE_BMSK 0x00000010
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA0_LINK_RING_ENABLE_SHFT 0x4
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2FW_LINK_RING_ENABLE_BMSK 0x00000008
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2FW_LINK_RING_ENABLE_SHFT 0x3
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2SW_LINK_RING_ENABLE_BMSK 0x00000004
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2SW_LINK_RING_ENABLE_SHFT 0x2
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2TQM_LINK_RING_ENABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2TQM_LINK_RING_ENABLE_SHFT 0x0
+
+//// Register WBM_R0_MISC_RING_ENABLE ////
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x) (x+0x00000010)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_PHYS(x) (x+0x00000010)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_RMSK 0x0000003f
+#define HWIO_WBM_R0_MISC_RING_ENABLE_SHFT 0
+#define HWIO_WBM_R0_MISC_RING_ENABLE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MISC_RING_ENABLE_RMSK)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW4_RELEASE_RING_ENABLE_BMSK 0x00000020
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW4_RELEASE_RING_ENABLE_SHFT 0x5
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW3_RELEASE_RING_ENABLE_BMSK 0x00000010
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW3_RELEASE_RING_ENABLE_SHFT 0x4
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW2_RELEASE_RING_ENABLE_BMSK 0x00000008
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW2_RELEASE_RING_ENABLE_SHFT 0x3
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW1_RELEASE_RING_ENABLE_BMSK 0x00000004
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW1_RELEASE_RING_ENABLE_SHFT 0x2
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW0_RELEASE_RING_ENABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW0_RELEASE_RING_ENABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2FW_RELEASE_RING_ENABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2FW_RELEASE_RING_ENABLE_SHFT 0x0
+
+//// Register WBM_R0_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x) (x+0x00000014)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_PHYS(x) (x+0x00000014)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK 0x000000ff
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA2_RELEASE_RING_NOT_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA2_RELEASE_RING_NOT_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA1_RELEASE_RING_NOT_IDLE_BMSK 0x00000040
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA1_RELEASE_RING_NOT_IDLE_SHFT 0x6
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA0_RELEASE_RING_NOT_IDLE_BMSK 0x00000020
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA0_RELEASE_RING_NOT_IDLE_SHFT 0x5
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_FW_RELEASE_RING_NOT_IDLE_BMSK 0x00000010
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_FW_RELEASE_RING_NOT_IDLE_SHFT 0x4
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_SW_RELEASE_RING_NOT_IDLE_BMSK 0x00000008
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_SW_RELEASE_RING_NOT_IDLE_SHFT 0x3
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_REO_RELEASE_RING_NOT_IDLE_BMSK 0x00000004
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_REO_RELEASE_RING_NOT_IDLE_SHFT 0x2
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_TQM_RELEASE_RING_NOT_IDLE_BMSK 0x00000002
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_TQM_RELEASE_RING_NOT_IDLE_SHFT 0x1
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_PPE_RELEASE_RING_NOT_IDLE_BMSK 0x00000001
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_PPE_RELEASE_RING_NOT_IDLE_SHFT 0x0
+
+//// Register WBM_R0_MSDU_BUFFER_RING_STATUS ////
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x) (x+0x00000018)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_PHYS(x) (x+0x00000018)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK 0x0000003f
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA2_BUF_RING_NOT_IDLE_BMSK 0x00000020
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA2_BUF_RING_NOT_IDLE_SHFT 0x5
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA1_BUF_RING_NOT_IDLE_BMSK 0x00000010
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA1_BUF_RING_NOT_IDLE_SHFT 0x4
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA0_BUF_RING_NOT_IDLE_BMSK 0x00000008
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA0_BUF_RING_NOT_IDLE_SHFT 0x3
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2FW_BUF_RING_NOT_IDLE_BMSK 0x00000004
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2FW_BUF_RING_NOT_IDLE_SHFT 0x2
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2SW_BUF_RING_NOT_IDLE_BMSK 0x00000002
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2SW_BUF_RING_NOT_IDLE_SHFT 0x1
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2PPE_BUF_RING_NOT_IDLE_BMSK 0x00000001
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2PPE_BUF_RING_NOT_IDLE_SHFT 0x0
+
+//// Register WBM_R0_LINK_DESC_RING_STATUS ////
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x) (x+0x0000001c)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_PHYS(x) (x+0x0000001c)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK 0x0000007f
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA2_LINK_RING_NOT_IDLE_BMSK 0x00000040
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA2_LINK_RING_NOT_IDLE_SHFT 0x6
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA1_LINK_RING_NOT_IDLE_BMSK 0x00000020
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA1_LINK_RING_NOT_IDLE_SHFT 0x5
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA0_LINK_RING_NOT_IDLE_BMSK 0x00000010
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA0_LINK_RING_NOT_IDLE_SHFT 0x4
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2FW_LINK_RING_NOT_IDLE_BMSK 0x00000008
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2FW_LINK_RING_NOT_IDLE_SHFT 0x3
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2SW_LINK_RING_NOT_IDLE_BMSK 0x00000004
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2SW_LINK_RING_NOT_IDLE_SHFT 0x2
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2REO_LINK_RING_NOT_IDLE_BMSK 0x00000002
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2REO_LINK_RING_NOT_IDLE_SHFT 0x1
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2TQM_LINK_RING_NOT_IDLE_BMSK 0x00000001
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2TQM_LINK_RING_NOT_IDLE_SHFT 0x0
+
+//// Register WBM_R0_MISC_RING_STATUS ////
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x) (x+0x00000020)
+#define HWIO_WBM_R0_MISC_RING_STATUS_PHYS(x) (x+0x00000020)
+#define HWIO_WBM_R0_MISC_RING_STATUS_RMSK 0x000003ff
+#define HWIO_WBM_R0_MISC_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_MISC_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), HWIO_WBM_R0_MISC_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_MISC_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_MISC_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_MISC_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW4_BUFFER_RING_NOT_IDLE_BMSK 0x00000200
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW4_BUFFER_RING_NOT_IDLE_SHFT 0x9
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_BMSK 0x00000100
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_SHFT 0x8
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_BMSK 0x00000040
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_SHFT 0x6
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_BMSK 0x00000020
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_SHFT 0x5
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_BMSK 0x00000010
+#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_SHFT 0x4
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000008
+#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 0x3
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000004
+#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0x2
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000002
+#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 0x1
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000001
+#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0x0
+
+//// Register WBM_R0_RELEASE_RING_FLUSH ////
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x) (x+0x00000024)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_PHYS(x) (x+0x00000024)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK 0x00013fff
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SHFT 0
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), val)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x00010000
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 0x10
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK 0x00002000
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT 0xd
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x00001000
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT 0xc
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0x00000fff
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT 0x0
+
+//// Register WBM_R0_IDLE_STATUS ////
+
+#define HWIO_WBM_R0_IDLE_STATUS_ADDR(x) (x+0x00000028)
+#define HWIO_WBM_R0_IDLE_STATUS_PHYS(x) (x+0x00000028)
+#define HWIO_WBM_R0_IDLE_STATUS_RMSK 0x0000ffff
+#define HWIO_WBM_R0_IDLE_STATUS_SHFT 0
+#define HWIO_WBM_R0_IDLE_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), HWIO_WBM_R0_IDLE_STATUS_RMSK)
+#define HWIO_WBM_R0_IDLE_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_IDLE_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_IDLE_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_BMSK 0x00008000
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_SHFT 0xf
+
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_BMSK 0x00004000
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_SHFT 0xe
+
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_BMSK 0x00002000
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_SHFT 0xd
+
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_BMSK 0x00001000
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_SHFT 0xc
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW4_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000800
+#define HWIO_WBM_R0_IDLE_STATUS_SW4_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0xb
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000400
+#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0xa
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000200
+#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x9
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000100
+#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x8
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000040
+#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x6
+
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_BMSK 0x00000020
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_SHFT 0x5
+
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000010
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 0x4
+
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000008
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 0x3
+
+#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000004
+#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 0x2
+
+#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000002
+#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 0x1
+
+#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_BMSK 0x00000001
+#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_SHFT 0x0
+
+//// Register WBM_R0_IDLE_SEQUENCE ////
+
+#define HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x) (x+0x0000002c)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_PHYS(x) (x+0x0000002c)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_RMSK 0x0000003f
+#define HWIO_WBM_R0_IDLE_SEQUENCE_SHFT 0
+#define HWIO_WBM_R0_IDLE_SEQUENCE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), HWIO_WBM_R0_IDLE_SEQUENCE_RMSK)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), val)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_SEQUENCE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_BMSK 0x00000020
+#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_SHFT 0x5
+
+#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_BMSK 0x00000010
+#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_SHFT 0x4
+
+#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_BMSK 0x0000000f
+#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_SHFT 0x0
+
+//// Register WBM_R0_MSDU_PARSER_CONTROL ////
+
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x) (x+0x00000030)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_PHYS(x) (x+0x00000030)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK 0x00000007
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_SHFT 0
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x00000004
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 0x2
+
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK 0x00000002
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT 0x1
+
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK 0x00000001
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT 0x0
+
+//// Register WBM_R0_MSDU_PARSER_STATUS ////
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x) (x+0x00000034)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x) (x+0x00000034)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0x00000fff
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_SHFT 0
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_BMSK 0x00000800
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_SHFT 0xb
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK 0x00000400
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT 0xa
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x000003c0
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 0x6
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x00000020
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT 0x5
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK 0x0000001f
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT 0x0
+
+//// Register WBM_R0_MISC_CONTROL ////
+
+#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) (x+0x00000038)
+#define HWIO_WBM_R0_MISC_CONTROL_PHYS(x) (x+0x00000038)
+#define HWIO_WBM_R0_MISC_CONTROL_RMSK 0xffffffff
+#define HWIO_WBM_R0_MISC_CONTROL_SHFT 0
+#define HWIO_WBM_R0_MISC_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_MISC_CONTROL_RMSK)
+#define HWIO_WBM_R0_MISC_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask)
+#define HWIO_WBM_R0_MISC_CONTROL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_MISC_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MISC_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc
+#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2
+
+#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_BMSK 0x00000002
+#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_SHFT 0x1
+
+#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_BMSK 0x00000001
+#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_SHFT 0x0
+
+//// Register WBM_R0_WATCHDOG_TIMEOUT ////
+
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000003c)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000003c)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK 0x00003fff
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_SHFT 0
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), val)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x00003000
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 0xc
+
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_BMSK 0x00000fff
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_SHFT 0x0
+
+//// Register WBM_R0_INTERRUPT_DATA_CAPTURE ////
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x) (x+0x00000040)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_PHYS(x) (x+0x00000040)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK 0xffffffff
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SHFT 0
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), val)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask, val, HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_BMSK 0x80000000
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_SHFT 0x1f
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_BMSK 0x40000000
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_SHFT 0x1e
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_BMSK 0x30000000
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_SHFT 0x1c
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_BMSK 0x0fffff00
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_SHFT 0x8
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BM_ACTION_BMSK 0x000000c0
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BM_ACTION_SHFT 0x6
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_BMSK 0x00000038
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_SHFT 0x3
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_BMSK 0x00000007
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_SHFT 0x0
+
+//// Register WBM_R0_INVALID_APB_ACC_ADDR ////
+
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x00000044)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x00000044)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK 0x0007ffff
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_SHFT 0
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), val)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_TYPE_BMSK 0x00060000
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_TYPE_SHFT 0x11
+
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_BMSK 0x0001ffff
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_SHFT 0x0
+
+//// Register WBM_R0_IDLE_LIST_CONTROL ////
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) (x+0x00000048)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_PHYS(x) (x+0x00000048)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK 0x000007ff
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SHFT 0
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x000007fc
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 0x2
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x00000002
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 0x1
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_BMSK 0x00000001
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_SHFT 0x0
+
+//// Register WBM_R0_IDLE_LIST_SIZE ////
+
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) (x+0x0000004c)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_PHYS(x) (x+0x0000004c)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK 0xffffffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SHFT 0
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), val)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 0x10
+
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0x0000ffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_LSB ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x) (x+0x00000050)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_PHYS(x) (x+0x00000050)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_MSB ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x) (x+0x00000054)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_PHYS(x) (x+0x00000054)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) (x+0x00000058)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_PHYS(x) (x+0x00000058)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) (x+0x0000005c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_PHYS(x) (x+0x0000005c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0 ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x) (x+0x00000060)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_PHYS(x) (x+0x00000060)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1 ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x) (x+0x00000064)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_PHYS(x) (x+0x00000064)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK 0x001fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0 ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) (x+0x00000068)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_PHYS(x) (x+0x00000068)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1 ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) (x+0x0000006c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_PHYS(x) (x+0x0000006c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK 0x001fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0 ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x) (x+0x00000070)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_PHYS(x) (x+0x00000070)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1 ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x) (x+0x00000074)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_PHYS(x) (x+0x00000074)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK 0x001fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0 ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) (x+0x00000078)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_PHYS(x) (x+0x00000078)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1 ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) (x+0x0000007c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_PHYS(x) (x+0x0000007c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK 0x001fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_HP ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x) (x+0x00000080)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_PHYS(x) (x+0x00000080)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK 0x000fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HP ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) (x+0x00000084)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_PHYS(x) (x+0x00000084)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK 0x000fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_TP ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x) (x+0x00000088)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_PHYS(x) (x+0x00000088)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK 0x000fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TP ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x) (x+0x0000008c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_PHYS(x) (x+0x0000008c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK 0x000fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SHFT 0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_CLK_GATE_CTRL ////
+
+#define HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000090)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000090)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_RMSK 0x0003ffff
+#define HWIO_WBM_R0_CLK_GATE_CTRL_SHFT 0
+#define HWIO_WBM_R0_CLK_GATE_CTRL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), HWIO_WBM_R0_CLK_GATE_CTRL_RMSK)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), val)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_BMSK 0x00020000
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_SHFT 0x11
+
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_BMSK 0x00010000
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_SHFT 0x10
+
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_GXI_TESTBUS_LOWER ////
+
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000094)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000094)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_SHFT 0
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_GXI_TESTBUS_UPPER ////
+
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000098)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000098)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_SHFT 0
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_GXI_SM_STATES_IX_0 ////
+
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000009c)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000009c)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SHFT 0
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9
+
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4
+
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0
+
+//// Register WBM_R0_GXI_END_OF_TEST_CHECK ////
+
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000000a0)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000000a0)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_SHFT 0
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+//// Register WBM_R0_GXI_CLOCK_GATE_DISABLE ////
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000000a4)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000000a4)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_ERR_INTS ////
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000000a8)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000000a8)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_ERR_STATS ////
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000000ac)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000000ac)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_DEFAULT_CONTROL ////
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000000b0)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000000b0)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_REDUCED_CONTROL ////
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000000b4)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000000b4)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_MISC_CONTROL ////
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000000b8)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000000b8)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_WDOG_CONTROL ////
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000000bc)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000000bc)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_WDOG_STATUS ////
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000000c0)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000000c0)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_IDLE_COUNTERS ////
+
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000000c4)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000000c4)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10
+
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_RD_LATENCY_CTRL ////
+
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x000000c8)
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x000000c8)
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11
+
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10
+
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff
+#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_WR_LATENCY_CTRL ////
+
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x000000cc)
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x000000cc)
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11
+
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10
+
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff
+#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 ////
+
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000000d0)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000000d0)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 ////
+
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000000d4)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000000d4)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 ////
+
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000000d8)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000000d8)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 ////
+
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000000dc)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000000dc)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0
+
+//// Register WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL ////
+
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000000e0)
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000000e0)
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask)
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf
+
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8
+
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7
+
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f
+#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000000e4)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000000e4)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000000e8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000000e8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x) (x+0x000000ec)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_PHYS(x) (x+0x000000ec)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x) (x+0x000000f0)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_PHYS(x) (x+0x000000f0)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x) (x+0x000000f4)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_PHYS(x) (x+0x000000f4)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK 0x003fffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000134)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000134)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x0000013c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x0000013c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000140)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000140)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x) (x+0x00000144)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x) (x+0x00000144)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x) (x+0x00000148)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_PHYS(x) (x+0x00000148)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x) (x+0x0000014c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_PHYS(x) (x+0x0000014c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK 0x003fffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000184)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000184)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000188)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000188)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x0000018c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x0000018c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000194)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000194)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000198)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000198)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x0000019c)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x0000019c)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x000001a0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x000001a0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x000001a4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x000001a4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK 0x003fffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000001e4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000001e4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000001ec)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000001ec)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000001f0)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000001f0)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) (x+0x000001f4)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) (x+0x000001f4)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x) (x+0x000001f8)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_PHYS(x) (x+0x000001f8)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x) (x+0x000001fc)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_PHYS(x) (x+0x000001fc)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK 0x003fffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000208)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000208)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000020c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000020c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000021c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000021c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000220)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000220)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000224)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000224)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000022c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000022c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000230)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000230)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x0000023c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x0000023c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000244)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000244)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000248)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000248)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x) (x+0x0000024c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x) (x+0x0000024c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x) (x+0x00000250)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_PHYS(x) (x+0x00000250)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x) (x+0x00000254)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_PHYS(x) (x+0x00000254)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK 0x003fffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000260)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000260)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000264)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000264)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000274)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000274)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000278)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000278)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000027c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000027c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000280)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000280)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000284)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000284)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000288)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000288)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000294)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000294)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x0000029c)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x0000029c)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000002a0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000002a0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x) (x+0x000002a4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x) (x+0x000002a4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x) (x+0x000002a8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_PHYS(x) (x+0x000002a8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x) (x+0x000002ac)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_PHYS(x) (x+0x000002ac)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK 0x003fffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000002b8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000002b8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000002bc)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000002bc)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000002cc)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000002cc)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000002d0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000002d0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000002d4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000002d4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000002d8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000002d8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000002dc)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000002dc)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000002e0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000002e0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000002ec)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000002ec)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x) (x+0x000003a4)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_PHYS(x) (x+0x000003a4)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x) (x+0x000003a8)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_PHYS(x) (x+0x000003a8)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x) (x+0x000003ac)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_PHYS(x) (x+0x000003ac)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x) (x+0x000003b0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_PHYS(x) (x+0x000003b0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x) (x+0x000003b4)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_PHYS(x) (x+0x000003b4)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x) (x+0x000003f4)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_PHYS(x) (x+0x000003f4)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x) (x+0x000003fc)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_PHYS(x) (x+0x000003fc)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000400)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000400)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x) (x+0x00000404)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_PHYS(x) (x+0x00000404)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x) (x+0x00000408)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_PHYS(x) (x+0x00000408)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x) (x+0x0000040c)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_PHYS(x) (x+0x0000040c)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x) (x+0x0000044c)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_PHYS(x) (x+0x0000044c)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000454)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000454)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000458)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000458)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x) (x+0x0000045c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_PHYS(x) (x+0x0000045c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x) (x+0x00000460)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_PHYS(x) (x+0x00000460)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x) (x+0x00000464)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_PHYS(x) (x+0x00000464)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000049c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000049c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004a0)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004a0)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x) (x+0x000004a4)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_PHYS(x) (x+0x000004a4)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x) (x+0x000004ac)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_PHYS(x) (x+0x000004ac)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x) (x+0x000004b0)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_PHYS(x) (x+0x000004b0)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x) (x+0x000004b4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_PHYS(x) (x+0x000004b4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x) (x+0x000004b8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_PHYS(x) (x+0x000004b8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x) (x+0x000004bc)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_PHYS(x) (x+0x000004bc)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x) (x+0x000004fc)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_PHYS(x) (x+0x000004fc)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) (x+0x000005b4)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x) (x+0x000005b4)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x) (x+0x000005b8)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x) (x+0x000005b8)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x) (x+0x000005bc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_PHYS(x) (x+0x000005bc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x) (x+0x000005c0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x) (x+0x000005c0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x) (x+0x000005c4)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x) (x+0x000005c4)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000005c8)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000005c8)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000005cc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000005cc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000005d8)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000005d8)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000005dc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000005dc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000005e0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000005e0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000005fc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000005fc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000600)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000600)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x) (x+0x00000604)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_PHYS(x) (x+0x00000604)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000608)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000608)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000060c)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000060c)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000610)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000610)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000614)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000614)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000618)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000618)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000061c)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000061c)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000620)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000620)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000624)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000624)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000630)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000630)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000634)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000634)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000638)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000638)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000654)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000654)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000658)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000658)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) (x+0x0000065c)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) (x+0x0000065c)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000660)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000660)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000664)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000664)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000668)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000668)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x) (x+0x0000066c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_PHYS(x) (x+0x0000066c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x) (x+0x00000670)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_PHYS(x) (x+0x00000670)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x) (x+0x00000674)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_PHYS(x) (x+0x00000674)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000678)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000678)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000067c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000067c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000688)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000688)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000068c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000068c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000690)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000690)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006ac)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006ac)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006b0)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006b0)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000006b4)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000006b4)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006b8)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006b8)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x) (x+0x000006bc)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_PHYS(x) (x+0x000006bc)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x) (x+0x000006c0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_PHYS(x) (x+0x000006c0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x) (x+0x000006c4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_PHYS(x) (x+0x000006c4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x) (x+0x000006c8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_PHYS(x) (x+0x000006c8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x) (x+0x000006cc)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_PHYS(x) (x+0x000006cc)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000006d0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000006d0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000006d4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000006d4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000006e0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000006e0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000006e4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000006e4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006e8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006e8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000704)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000704)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000708)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000708)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x) (x+0x0000070c)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_PHYS(x) (x+0x0000070c)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000710)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000710)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000714)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000714)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000718)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000718)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x) (x+0x0000071c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_PHYS(x) (x+0x0000071c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x) (x+0x00000720)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_PHYS(x) (x+0x00000720)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x) (x+0x00000724)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_PHYS(x) (x+0x00000724)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000728)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000728)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000072c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000072c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000738)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000738)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000073c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000073c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000740)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000740)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000075c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000075c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000760)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000760)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x) (x+0x00000764)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_PHYS(x) (x+0x00000764)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000768)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000768)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x) (x+0x0000081c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_PHYS(x) (x+0x0000081c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000820)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000820)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x) (x+0x00000824)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_PHYS(x) (x+0x00000824)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x) (x+0x00000828)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_PHYS(x) (x+0x00000828)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x) (x+0x0000082c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_PHYS(x) (x+0x0000082c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000830)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000830)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000834)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000834)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000838)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000838)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000083c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000083c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000840)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000840)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000844)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000844)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000848)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000848)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000084c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000084c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000850)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000850)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000854)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000854)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000858)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000858)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000085c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000085c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000860)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000860)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000864)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000864)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000868)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000868)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x) (x+0x0000086c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_PHYS(x) (x+0x0000086c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000870)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000870)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000874)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000874)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000878)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000878)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x) (x+0x0000087c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_PHYS(x) (x+0x0000087c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x) (x+0x00000880)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_PHYS(x) (x+0x00000880)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) (x+0x00000884)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_PHYS(x) (x+0x00000884)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000888)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000888)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000088c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000088c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000890)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000890)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000894)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000894)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000898)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000898)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000089c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000089c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008a0)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008a0)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000008a4)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000008a4)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000008a8)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000008a8)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000008ac)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000008ac)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000008b0)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000008b0)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000008b4)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000008b4)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000008b8)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000008b8)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008bc)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008bc)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008c0)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008c0)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000008c4)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000008c4)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008c8)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008c8)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000008cc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000008cc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000008d0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000008d0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x) (x+0x000008d4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_PHYS(x) (x+0x000008d4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x) (x+0x000008d8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_PHYS(x) (x+0x000008d8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x) (x+0x000008dc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_PHYS(x) (x+0x000008dc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008e0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008e0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008e4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008e4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008f0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008f0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008f4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008f4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008f8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008f8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000914)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000914)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000918)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000918)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x0000091c)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x0000091c)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000920)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000920)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000924)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000924)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000928)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000928)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x) (x+0x0000092c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_PHYS(x) (x+0x0000092c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x) (x+0x00000930)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_PHYS(x) (x+0x00000930)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x) (x+0x00000934)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_PHYS(x) (x+0x00000934)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000938)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000938)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000093c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000093c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000948)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000948)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000094c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000094c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000950)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000950)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000096c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000096c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000970)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000970)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000974)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000974)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000978)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000978)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x0000097c)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x0000097c)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000980)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000980)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x) (x+0x00000984)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_PHYS(x) (x+0x00000984)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x) (x+0x00000988)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_PHYS(x) (x+0x00000988)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x) (x+0x0000098c)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_PHYS(x) (x+0x0000098c)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000990)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000990)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000994)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000994)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000009a0)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000009a0)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000009a4)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000009a4)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000009a8)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000009a8)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000009c4)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000009c4)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000009c8)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000009c8)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000009cc)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000009cc)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009d0)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009d0)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000009d4)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000009d4)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000009d8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000009d8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x) (x+0x000009dc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_PHYS(x) (x+0x000009dc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x) (x+0x000009e0)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_PHYS(x) (x+0x000009e0)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x) (x+0x000009e4)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_PHYS(x) (x+0x000009e4)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000009e8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000009e8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000009ec)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000009ec)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000009f8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000009f8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000009fc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000009fc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a00)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a00)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000a1c)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000a1c)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000a20)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000a20)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000a24)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000a24)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a28)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a28)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000a2c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000a2c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000a30)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000a30)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x) (x+0x00000a34)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_PHYS(x) (x+0x00000a34)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x) (x+0x00000a38)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_PHYS(x) (x+0x00000a38)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x) (x+0x00000a3c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_PHYS(x) (x+0x00000a3c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000a40)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000a40)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000a44)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000a44)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000a50)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000a50)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000a54)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000a54)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a58)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a58)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000a74)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000a74)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000a78)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000a78)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000a7c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000a7c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a80)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a80)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000a84)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000a84)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000a88)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000a88)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x) (x+0x00000a8c)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_PHYS(x) (x+0x00000a8c)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x) (x+0x00000a90)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_PHYS(x) (x+0x00000a90)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x) (x+0x00000a94)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_PHYS(x) (x+0x00000a94)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RMSK 0x03ffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000a98)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000a98)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000a9c)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000a9c)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000aa8)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000aa8)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000aac)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000aac)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000ab0)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000ab0)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000acc)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000acc)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000ad0)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000ad0)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000ad4)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000ad4)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+//// Register WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000ad8)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000ad8)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+ out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+//// Register WBM_R1_END_OF_TEST_CHECK ////
+
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002000)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002000)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK 0x00000001
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_SHFT 0
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+//// Register WBM_R1_TESTBUS_CTRL ////
+
+#define HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002004)
+#define HWIO_WBM_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002004)
+#define HWIO_WBM_R1_TESTBUS_CTRL_RMSK 0x00001f3f
+#define HWIO_WBM_R1_TESTBUS_CTRL_SHFT 0
+#define HWIO_WBM_R1_TESTBUS_CTRL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), HWIO_WBM_R1_TESTBUS_CTRL_RMSK)
+#define HWIO_WBM_R1_TESTBUS_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask)
+#define HWIO_WBM_R1_TESTBUS_CTRL_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), val)
+#define HWIO_WBM_R1_TESTBUS_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_BMSK 0x00001f00
+#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_SHFT 0x8
+
+#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_BMSK 0x0000003f
+#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_SHFT 0x0
+
+//// Register WBM_R1_TESTBUS_LOWER ////
+
+#define HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x) (x+0x00002008)
+#define HWIO_WBM_R1_TESTBUS_LOWER_PHYS(x) (x+0x00002008)
+#define HWIO_WBM_R1_TESTBUS_LOWER_RMSK 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_LOWER_SHFT 0
+#define HWIO_WBM_R1_TESTBUS_LOWER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R1_TESTBUS_LOWER_RMSK)
+#define HWIO_WBM_R1_TESTBUS_LOWER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask)
+#define HWIO_WBM_R1_TESTBUS_LOWER_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_WBM_R1_TESTBUS_LOWER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_LOWER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_SHFT 0x0
+
+//// Register WBM_R1_TESTBUS_HIGHER ////
+
+#define HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x) (x+0x0000200c)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_PHYS(x) (x+0x0000200c)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_RMSK 0x000000ff
+#define HWIO_WBM_R1_TESTBUS_HIGHER_SHFT 0
+#define HWIO_WBM_R1_TESTBUS_HIGHER_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), HWIO_WBM_R1_TESTBUS_HIGHER_RMSK)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), val)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_HIGHER_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff
+#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0
+
+//// Register WBM_R1_SM_STATES_IX_0 ////
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002010)
+#define HWIO_WBM_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002010)
+#define HWIO_WBM_R1_SM_STATES_IX_0_RMSK 0x7fffffff
+#define HWIO_WBM_R1_SM_STATES_IX_0_SHFT 0
+#define HWIO_WBM_R1_SM_STATES_IX_0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_0_RMSK)
+#define HWIO_WBM_R1_SM_STATES_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask)
+#define HWIO_WBM_R1_SM_STATES_IX_0_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_WBM_R1_SM_STATES_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_BMSK 0x60000000
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_SHFT 0x1d
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_BMSK 0x18000000
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_SHFT 0x1b
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_BMSK 0x06000000
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_SHFT 0x19
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_BMSK 0x01800000
+#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_SHFT 0x17
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_BMSK 0x00600000
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_SHFT 0x15
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_BMSK 0x00180000
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_SHFT 0x13
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_BMSK 0x00060000
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_SHFT 0x11
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_BMSK 0x00018000
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_SHFT 0xf
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_BMSK 0x00007000
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_SHFT 0xc
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_BMSK 0x00000c00
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_SHFT 0xa
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_BMSK 0x00000380
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_SHFT 0x7
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_BMSK 0x00000060
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_SHFT 0x5
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_BMSK 0x0000001c
+#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_SHFT 0x2
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_BMSK 0x00000003
+#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_SHFT 0x0
+
+//// Register WBM_R1_SM_STATES_IX_1 ////
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002014)
+#define HWIO_WBM_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002014)
+#define HWIO_WBM_R1_SM_STATES_IX_1_RMSK 0xffffffff
+#define HWIO_WBM_R1_SM_STATES_IX_1_SHFT 0
+#define HWIO_WBM_R1_SM_STATES_IX_1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_1_RMSK)
+#define HWIO_WBM_R1_SM_STATES_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask)
+#define HWIO_WBM_R1_SM_STATES_IX_1_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), val)
+#define HWIO_WBM_R1_SM_STATES_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_SW4_BUFFER_P_STATE_BMSK 0xc0000000
+#define HWIO_WBM_R1_SM_STATES_IX_1_SW4_BUFFER_P_STATE_SHFT 0x1e
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_DIST_NULL_PTR_BMSK 0x20000000
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_DIST_NULL_PTR_SHFT 0x1d
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_DIST_NULL_PTR_BMSK 0x10000000
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_DIST_NULL_PTR_SHFT 0x1c
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_BMSK 0x0e000000
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_SHFT 0x19
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_BMSK 0x01c00000
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_SHFT 0x16
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_BMSK 0x00380000
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_SHFT 0x13
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_BMSK 0x00070000
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_SHFT 0x10
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_C_STATE_BMSK 0x0000e000
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_C_STATE_SHFT 0xd
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_P_STATE_BMSK 0x00001c00
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_P_STATE_SHFT 0xa
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_C_STATE_BMSK 0x00000380
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_C_STATE_SHFT 0x7
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_P_STATE_BMSK 0x00000070
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_P_STATE_SHFT 0x4
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_BMSK 0x0000000c
+#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_SHFT 0x2
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_BMSK 0x00000003
+#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_SHFT 0x0
+
+//// Register WBM_R1_EVENTMASK_IX_0 ////
+
+#define HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00002018)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00002018)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_RMSK 0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_0_SHFT 0
+#define HWIO_WBM_R1_EVENTMASK_IX_0_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_0_RMSK)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), val)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_SHFT 0x0
+
+//// Register WBM_R1_EVENTMASK_IX_1 ////
+
+#define HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x) (x+0x0000201c)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_PHYS(x) (x+0x0000201c)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_RMSK 0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_1_SHFT 0
+#define HWIO_WBM_R1_EVENTMASK_IX_1_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_1_RMSK)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), val)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_SHFT 0x0
+
+//// Register WBM_R1_EVENTMASK_IX_2 ////
+
+#define HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00002020)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00002020)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_RMSK 0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_2_SHFT 0
+#define HWIO_WBM_R1_EVENTMASK_IX_2_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_2_RMSK)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), val)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_BMSK 0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_SHFT 0x0
+
+//// Register WBM_R1_EVENTMASK_IX_3 ////
+
+#define HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00002024)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00002024)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_RMSK 0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_3_SHFT 0
+#define HWIO_WBM_R1_EVENTMASK_IX_3_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_3_RMSK)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), val)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_BMSK 0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_SHFT 0x0
+
+//// Register WBM_R1_REG_ACCESS_EVENT_GEN_CTRL ////
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00002028)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00002028)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \
+ in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \
+ out_dword( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0
+
+//// Register WBM_R2_PPE_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x) (x+0x00003000)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_PHYS(x) (x+0x00003000)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_PPE_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x) (x+0x00003004)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_PHYS(x) (x+0x00003004)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_TQM_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x) (x+0x00003008)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_PHYS(x) (x+0x00003008)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_TQM_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x) (x+0x0000300c)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_PHYS(x) (x+0x0000300c)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_REO_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003010)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003010)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_REO_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x00003014)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x00003014)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_SW_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) (x+0x00003018)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_PHYS(x) (x+0x00003018)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_SW_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x) (x+0x0000301c)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_PHYS(x) (x+0x0000301c)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_FW_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x) (x+0x00003020)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_PHYS(x) (x+0x00003020)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_FW_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x) (x+0x00003024)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_PHYS(x) (x+0x00003024)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_RXDMA0_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x) (x+0x00003028)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_PHYS(x) (x+0x00003028)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_RXDMA0_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x) (x+0x0000302c)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_PHYS(x) (x+0x0000302c)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2PPE_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x) (x+0x00003040)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_PHYS(x) (x+0x00003040)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2PPE_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x) (x+0x00003044)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_PHYS(x) (x+0x00003044)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x) (x+0x00003048)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_PHYS(x) (x+0x00003048)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x) (x+0x0000304c)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_PHYS(x) (x+0x0000304c)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2FW_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x) (x+0x00003050)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_PHYS(x) (x+0x00003050)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2FW_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x) (x+0x00003054)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_PHYS(x) (x+0x00003054)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2RXDMA0_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x) (x+0x00003058)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_PHYS(x) (x+0x00003058)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2RXDMA0_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x) (x+0x0000305c)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_PHYS(x) (x+0x0000305c)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2TQM_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) (x+0x00003070)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_PHYS(x) (x+0x00003070)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2TQM_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x) (x+0x00003074)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_PHYS(x) (x+0x00003074)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2REO_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003078)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003078)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2REO_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000307c)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000307c)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x) (x+0x00003080)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_PHYS(x) (x+0x00003080)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x) (x+0x00003084)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_PHYS(x) (x+0x00003084)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2FW_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x) (x+0x00003088)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_PHYS(x) (x+0x00003088)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2FW_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x) (x+0x0000308c)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_PHYS(x) (x+0x0000308c)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2RXDMA0_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x) (x+0x00003090)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_PHYS(x) (x+0x00003090)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2RXDMA0_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x) (x+0x00003094)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_PHYS(x) (x+0x00003094)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM_IDLE_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x) (x+0x000030a8)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_PHYS(x) (x+0x000030a8)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM_IDLE_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x) (x+0x000030ac)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_PHYS(x) (x+0x000030ac)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM_IDLE_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) (x+0x000030b0)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_PHYS(x) (x+0x000030b0)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM_IDLE_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x) (x+0x000030b4)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_PHYS(x) (x+0x000030b4)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2FW_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x) (x+0x000030b8)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_PHYS(x) (x+0x000030b8)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2FW_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x) (x+0x000030bc)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_PHYS(x) (x+0x000030bc)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW0_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) (x+0x000030c0)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_PHYS(x) (x+0x000030c0)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW0_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x) (x+0x000030c4)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_PHYS(x) (x+0x000030c4)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW1_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) (x+0x000030c8)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_PHYS(x) (x+0x000030c8)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW1_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x) (x+0x000030cc)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_PHYS(x) (x+0x000030cc)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW2_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x) (x+0x000030d0)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_PHYS(x) (x+0x000030d0)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW2_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x) (x+0x000030d4)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_PHYS(x) (x+0x000030d4)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW3_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x) (x+0x000030d8)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_PHYS(x) (x+0x000030d8)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW3_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x) (x+0x000030dc)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_PHYS(x) (x+0x000030dc)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW4_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x) (x+0x000030e0)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_PHYS(x) (x+0x000030e0)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0
+
+//// Register WBM_R2_WBM2SW4_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x) (x+0x000030e4)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_PHYS(x) (x+0x000030e4)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_RMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_SHFT 0
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_INM(x, mask) \
+ in_dword_masked ( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), mask)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUT(x, val) \
+ out_dword( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUTM(x, mask, val) \
+ do {\
+ HWIO_INTLOCK(); \
+ out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x)); \
+ HWIO_INTFREE();\
+ } while (0)
+
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff
+#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0
+
+
+#endif
+
diff --git a/hw/qca5018/wbm_release_ring.h b/hw/qca5018/wbm_release_ring.h
new file mode 100644
index 0000000..56cad44
--- /dev/null
+++ b/hw/qca5018/wbm_release_ring.h
@@ -0,0 +1,2085 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "tx_rate_stats_info.h"
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0-1 struct buffer_addr_info released_buff_or_desc_addr_info;
+// 2 release_source_module[2:0], bm_action[5:3], buffer_or_desc_type[8:6], first_msdu_index[12:9], tqm_release_reason[16:13], rxdma_push_reason[18:17], rxdma_error_code[23:19], reo_push_reason[25:24], reo_error_code[30:26], wbm_internal_error[31]
+// 3 tqm_status_number[23:0], transmit_count[30:24], msdu_continuation[31]
+// 4 ack_frame_rssi[7:0], sw_release_details_valid[8], first_msdu[9], last_msdu[10], msdu_part_of_amsdu[11], fw_tx_notify_frame[12], buffer_timestamp[31:13]
+// 5-6 struct tx_rate_stats_info tx_rate_stats;
+// 7 sw_peer_id[15:0], tid[19:16], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+ struct buffer_addr_info released_buff_or_desc_addr_info;
+ uint32_t release_source_module : 3, //[2:0]
+ bm_action : 3, //[5:3]
+ buffer_or_desc_type : 3, //[8:6]
+ first_msdu_index : 4, //[12:9]
+ tqm_release_reason : 4, //[16:13]
+ rxdma_push_reason : 2, //[18:17]
+ rxdma_error_code : 5, //[23:19]
+ reo_push_reason : 2, //[25:24]
+ reo_error_code : 5, //[30:26]
+ wbm_internal_error : 1; //[31]
+ uint32_t tqm_status_number : 24, //[23:0]
+ transmit_count : 7, //[30:24]
+ msdu_continuation : 1; //[31]
+ uint32_t ack_frame_rssi : 8, //[7:0]
+ sw_release_details_valid : 1, //[8]
+ first_msdu : 1, //[9]
+ last_msdu : 1, //[10]
+ msdu_part_of_amsdu : 1, //[11]
+ fw_tx_notify_frame : 1, //[12]
+ buffer_timestamp : 19; //[31:13]
+ struct tx_rate_stats_info tx_rate_stats;
+ uint32_t sw_peer_id : 16, //[15:0]
+ tid : 4, //[19:16]
+ ring_id : 8, //[27:20]
+ looping_count : 4; //[31:28]
+};
+
+/*
+
+struct buffer_addr_info released_buff_or_desc_addr_info
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ Details of the physical address of the buffer or link
+ descriptor that is being released. Note that within this
+ descriptor, WBM will look at the 'owner' of the released
+ buffer/descriptor and forward it to SW/FW is WBM is not the
+ owner.
+
+
+
+ In case of TQM releasing Tx MSDU link descriptors with
+ Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime
+ WBM can optionally release the MSDU buffers pointed to by
+ the MSDU link descriptors to FW and override the
+ tx_rate_stats field, for FW reinjection of these MSDUs
+ (FR54309). This is not supported in Pine.
+
+release_source_module
+
+ Indicates which module initiated the release of this
+ buffer or descriptor
+
+
+
+ <enum 0 release_source_TQM> TQM released this buffer or
+ descriptor
+
+ <enum 1 release_source_RXDMA> RXDMA released this buffer
+ or descriptor
+
+ <enum 2 release_source_REO> REO released this buffer or
+ descriptor
+
+ <enum 3 release_source_FW> FW released this buffer or
+ descriptor
+
+ <enum 4 release_source_SW> SW released this buffer or
+ descriptor
+
+ <legal 0-4>
+
+bm_action
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ Field only valid when the field return_buffer_manager in
+ the Released_buff_or_desc_addr_info indicates:
+
+ WBM_IDLE_BUF_LIST or
+
+ WBM_IDLE_DESC_LIST
+
+
+
+ An MSDU extension descriptor shall never be marked as
+
+
+
+ <enum 0 Put_in_idle_list> Put the buffer or descriptor
+ back in the idle list. In case of MSDU or MDPU link
+ descriptor, BM does not need to check to release any
+ individual MSDU buffers
+
+
+
+ <enum 1 release_msdu_list > This BM action can only be
+ used in combination with buffer_or_desc_type being
+ msdu_link_descriptor. Field first_msdu_index points out
+ which MSDU pointer in the MSDU link descriptor is the first
+ of an MPDU that is released.
+
+ BM shall release all the MSDU buffers linked to this
+ first MSDU buffer pointer. All related MSDU buffer pointer
+ entries shall be set to value 0, which represents the 'NULL
+ pointer. When all MSDU buffer pointers in the MSDU link
+ descriptor are 'NULL', the MSDU link descriptor itself shall
+ also be released.
+
+
+
+ <enum 2 Put_in_idle_list_expanded> CURRENTLY NOT
+ IMPLEMENTED....
+
+ Put the buffer or descriptor back in the idle list. Only
+ valid in combination with buffer_or_desc_type indicating
+ MDPU_link_descriptor.
+
+ BM shall release the MPDU link descriptor as well as all
+ MSDUs that are linked to the MPDUs in this descriptor.
+
+
+
+ <legal 0-2>
+
+buffer_or_desc_type
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ Field only valid when WBM is marked as the
+ return_buffer_manager in the Released_Buffer_address_info
+
+
+
+ Indicates that type of buffer or descriptor is being
+ released
+
+
+
+ <enum 0 MSDU_rel_buffer> The address points to an MSDU
+ buffer
+
+ <enum 1 msdu_link_descriptor> The address points to an
+ TX MSDU link descriptor
+
+ <enum 2 mpdu_link_descriptor> The address points to an
+ MPDU link descriptor
+
+ <enum 3 msdu_ext_descriptor > The address points to an
+ MSDU extension descriptor.
+
+ In case BM finds this one in a release ring, it passes
+ it on to FW...
+
+ <enum 4 queue_ext_descriptor> The address points to an
+ TQM queue extension descriptor. WBM should treat this is the
+ same way as a link descriptor. That is, put the 128 byte
+ buffer back in the link buffer idle list.
+
+
+
+ <legal 0-4>
+
+first_msdu_index
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ Field only valid for the bm_action release_msdu_list.
+
+
+
+ The index of the first MSDU in an MSDU link descriptor
+ all belonging to the same MPDU.
+
+
+
+ <legal 0-6>
+
+tqm_release_reason
+
+ Consumer: WBM/SW/FW
+
+ Producer: TQM
+
+
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ (rr = Release Reason)
+
+ <enum 0 tqm_rr_frame_acked> frame is removed because an
+ ACK of BA for it was received
+
+ <enum 1 tqm_rr_rem_cmd_rem> frame is removed because a
+ remove command of type Remove_mpdus initiated by SW
+
+ <enum 2 tqm_rr_rem_cmd_tx> frame is removed because a
+ remove command of type Remove_transmitted_mpdus initiated by
+ SW
+
+ <enum 3 tqm_rr_rem_cmd_notx> frame is removed because a
+ remove command of type Remove_untransmitted_mpdus initiated
+ by SW
+
+ <enum 4 tqm_rr_rem_cmd_aged> frame is removed because a
+ remove command of type Remove_aged_mpdus or
+ Remove_aged_msdus initiated by SW
+
+ <enum 5 tqm_fw_reason1> frame is removed because a
+ remove command where fw indicated that remove reason is
+ fw_reason1
+
+ <enum 6 tqm_fw_reason2> frame is removed because a
+ remove command where fw indicated that remove reason is
+ fw_reason1
+
+ <enum 7 tqm_fw_reason3> frame is removed because a
+ remove command where fw indicated that remove reason is
+ fw_reason1
+
+ <enum 8 tqm_rr_rem_cmd_disable_queue> frame is removed
+ because a remove command of type
+ remove_mpdus_and_disable_queue or
+ remove_msdus_and_disable_flow initiated by SW
+
+
+
+ <legal 0-8>
+
+
+
+ In case of TQM releasing Tx MSDU link descriptors with
+ Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime
+ WBM can optionally release the MSDU buffers pointed to by
+ the MSDU link descriptors to FW and override the
+ tx_rate_stats field, for FW reinjection of these MSDUs
+ (FR54309). This is not supported in Pine.
+
+rxdma_push_reason
+
+ Field only valid when Release_source_module is set to
+ release_source_RXDMA
+
+
+
+ Indicates why rxdma pushed the frame to this ring
+
+
+
+ <enum 0 rxdma_error_detected> RXDMA detected an error an
+ pushed this frame to this queue
+
+ <enum 1 rxdma_routing_instruction> RXDMA pushed the
+ frame to this queue per received routing instructions. No
+ error within RXDMA was detected
+
+ <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
+ result the MSDU link descriptor might not have the
+ last_msdu_in_mpdu_flag set, but instead WBM might just see a
+ NULL pointer in the MSDU link descriptor. This is to be
+ considered a normal condition for this scenario.
+
+
+
+ <legal 0 - 2>
+
+
+
+ In case of RXDMA releasing Rx MSDU link descriptors,'
+ Maple/Spruce WBM can optionally override the tx_rate_stats
+ field with Rx_msdu_desc_info_details (FR59859). This is not
+ supported in HastingsPrime, Pine or Moselle.
+
+rxdma_error_code
+
+ Field only valid when 'rxdma_push_reason' set to
+ 'rxdma_error_detected'.
+
+
+
+ <enum 0 rxdma_overflow_err>MPDU frame is not complete
+ due to a FIFO overflow error in RXPCU.
+
+ <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+ due to receiving incomplete MPDU from the PHY
+
+
+ <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+ error or CRYPTO received an encrypted frame, but did not get
+ a valid corresponding key id in the peer entry.
+
+ <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+ error
+
+ <enum 5 rxdma_unecrypted_err>CRYPTO reported an
+ unencrypted frame error when encrypted was expected
+
+ <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+ length error
+
+ <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+ number of MSDUs allowed in an MPDU got exceeded
+
+ <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+ error
+
+ <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+ parsing error
+
+ <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+ during SA search
+
+ <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+ during DA search
+
+ <enum 12 rxdma_flow_timeout_err>RX OLE reported a
+ timeout during flow search
+
+ <enum 13 rxdma_flush_request>RXDMA received a flush
+ request
+
+ <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
+ present as well as a fragmented MPDU. A-MSDU defragmentation
+ is not supported in Lithium SW so this is treated as an
+ error.
+
+reo_push_reason
+
+ Field only valid when Release_source_module is set to
+ release_source_REO
+
+
+
+ Indicates why REO pushed the frame to this release ring
+
+
+
+ <enum 0 reo_error_detected> Reo detected an error an
+ pushed this frame to this queue
+
+ <enum 1 reo_routing_instruction> Reo pushed the frame to
+ this queue per received routing instructions. No error
+ within REO was detected
+
+
+
+ <legal 0 - 1>
+
+
+
+ In case of REO releasing Rx MSDU link descriptors,'
+ Maple/Spruce WBM can optionally override
+ the tx_rate_stats field with
+ Rx_msdu_desc_info_details (FR59859). This is not supported
+ in HastingsPrime, Pine or Moselle.
+
+reo_error_code
+
+ Field only valid when 'Reo_push_reason' set to
+ 'reo_error_detected'.
+
+
+
+ <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+ provided in the REO_ENTRANCE ring is set to 0
+
+ <enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+ valid bit is NOT set
+
+ <enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+ session having been setup.
+
+ <enum 3 non_ba_duplicate> Non-BA session, SN equal to
+ SSN, Retry bit set: duplicate frame
+
+ <enum 4 ba_duplicate> BA session, duplicate frame
+
+ <enum 5 regular_frame_2k_jump> A normal (management/data
+ frame) received with 2K jump in SN
+
+ <enum 6 bar_frame_2k_jump> A bar received with 2K jump
+ in SSN
+
+ <enum 7 regular_frame_OOR> A normal (management/data
+ frame) received with SN falling within the OOR window
+
+ <enum 8 bar_frame_OOR> A bar received with SSN falling
+ within the OOR window
+
+ <enum 9 bar_frame_no_ba_session> A bar received without
+ a BA session
+
+ <enum 10 bar_frame_sn_equals_ssn> A bar received with
+ SSN equal to SN
+
+ <enum 11 pn_check_failed> PN Check Failed packet.
+
+ <enum 12 2k_error_handling_flag_set> Frame is forwarded
+ as a result of the 'Seq_2k_error_detected_flag' been set in
+ the REO Queue descriptor
+
+ <enum 13 pn_error_handling_flag_set> Frame is forwarded
+ as a result of the 'pn_error_detected_flag' been set in the
+ REO Queue descriptor
+
+ <enum 14 queue_descriptor_blocked_set> Frame is
+ forwarded as a result of the queue descriptor(address) being
+ blocked as SW/FW seems to be currently in the process of
+ making updates to this descriptor...
+
+
+
+ <legal 0-14>
+
+wbm_internal_error
+
+ Can only be set by WBM.
+
+
+
+ Is set when WBM got a buffer pointer but the action was
+ to push it to the idle link descriptor ring or do link
+ related activity
+
+ OR
+
+ Is set when WBM got a link buffer pointer but the action
+ was to push it to the buffer descriptor ring
+
+
+
+ <legal all>
+
+tqm_status_number
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ The value in this field is equal to value of the
+ 'TQM_CMD_Number' field the TQM command or the
+ 'TQM_add_cmd_Number' field from the TQM entrance ring
+ descriptor
+
+
+
+ This field helps to correlate the statuses with the TQM
+ commands.
+
+
+
+ NOTE that SW could program this number to be equal to
+ the PPDU_ID number in case direct correlation with the PPDU
+ ID is desired
+
+
+
+ <legal all>
+
+transmit_count
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ The number of times this frame has been transmitted
+
+msdu_continuation
+
+ FR53947 requests MSDU_continuation reporting for Rx
+ MSDUs in Pine and HastingsPrime for which
+ SW_release_details_valid may not be set.
+
+ <legal all>
+
+ack_frame_rssi
+
+ This field is only valid when the source is TQM.
+
+
+
+ If this frame is removed as the result of the reception
+ of an ACK or BA, this field indicates the RSSI of the
+ received ACK or BA frame.
+
+
+
+ When the frame is removed as result of a direct remove
+ command from the SW, this field is set to 0x0 (which is
+ never a valid value when real RSSI is available)
+
+
+
+ <legal all>
+
+sw_release_details_valid
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ When set, some WBM specific release info for SW is
+ valid.
+
+ This is set when WMB got a 'release_msdu_list' command
+ from TQM and the return buffer manager is not WMB. WBM will
+ then de-aggregate all the MSDUs and pass them one at a time
+ on to the 'buffer owner'
+
+
+
+ <legal all>
+
+first_msdu
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ When set, this MSDU is the first MSDU pointed to in the
+ 'release_msdu_list' command.
+
+
+
+ FR53947 extends this to Rx MSDUs in Pine and
+ HastingsPrime for which SW_release_details_valid may not be
+ set.
+
+ <legal all>
+
+last_msdu
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ When set, this MSDU is the last MSDU pointed to in the
+ 'release_msdu_list' command.
+
+
+
+ FR53947 extends this to Rx MSDUs in Pine and
+ HastingsPrime for which SW_release_details_valid may not be
+ set.
+
+ <legal all>
+
+msdu_part_of_amsdu
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ When set, this MSDU was part of an A-MSDU in MPDU
+
+ <legal all>
+
+fw_tx_notify_frame
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ This is the FW_tx_notify_frame field from the
+
+ <legal all>
+
+buffer_timestamp
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ This is the Buffer_timestamp field from the
+ TX_MSDU_DETAILS for this frame from the MSDU link
+ descriptor.
+
+
+
+ Timestamp in units of 1024 µs
+
+ <legal all>
+
+struct tx_rate_stats_info tx_rate_stats
+
+ Consumer: TQM/SW
+
+ Producer: SW/SCH(from TXPCU, PDG) /WBM (from RXDMA)
+
+
+
+ Details for command execution tracking purposes.
+
+
+
+ In case of TQM releasing Tx MSDU link descriptors with
+ Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime
+ WBM can optionally release the MSDU buffers pointed to by
+ the MSDU link descriptors to FW and override the
+ tx_rate_stats field with words 2 and 3 of the
+ 'TX_MSDU_DETAILS' structure, for FW reinjection of these
+ MSDUs (FR54309). This is not supported in Pine.
+
+
+
+ In case of RXDMA or REO releasing Rx MSDU link
+ descriptors,' Maple/Spruce WBM can optionally override
+ the tx_rate_stats field
+ with Rx_msdu_desc_info_details (FR59859). This is not
+ supported in HastingsPrime, Pine or Moselle.
+
+sw_peer_id
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ 1) Release of msdu buffer due to drop_frame = 1. Flow is
+ not fetched and hence sw_peer_id and tid = 0
+
+ buffer_or_desc_type = e_num 0
+ MSDU_rel_buffertqm_release_reason = e_num 1
+ tqm_rr_rem_cmd_rem
+
+
+
+
+
+ 2) Release of msdu buffer due to Flow is not fetched and
+ hence sw_peer_id and tid = 0
+
+ buffer_or_desc_type = e_num 0
+ MSDU_rel_buffertqm_release_reason = e_num 1
+ tqm_rr_rem_cmd_rem
+
+
+
+
+
+ 3) Release of msdu link due to remove_mpdu or acked_mpdu
+ command.
+
+ buffer_or_desc_type = e_num1
+ msdu_link_descriptortqm_release_reason can be:e_num 1
+ tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx
+
+ e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged
+
+
+
+ Sw_peer_id from the TX_MSDU_FLOW descriptor or
+ TX_MPDU_QUEUE descriptor
+
+ <legal all>
+
+tid
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ 1) Release of msdu buffer due to drop_frame = 1. Flow is
+ not fetched and hence sw_peer_id and tid = 0
+
+ buffer_or_desc_type = e_num 0
+ MSDU_rel_buffertqm_release_reason = e_num 1
+ tqm_rr_rem_cmd_rem
+
+
+
+
+
+ 2) Release of msdu buffer due to Flow is not fetched and
+ hence sw_peer_id and tid = 0
+
+ buffer_or_desc_type = e_num 0
+ MSDU_rel_buffertqm_release_reason = e_num 1
+ tqm_rr_rem_cmd_rem
+
+
+
+
+
+ 3) Release of msdu link due to remove_mpdu or acked_mpdu
+ command.
+
+ buffer_or_desc_type = e_num1
+ msdu_link_descriptortqm_release_reason can be:e_num 1
+ tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx
+
+ e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged
+
+
+
+
+
+ This field represents the TID from the TX_MSDU_FLOW
+ descriptor or TX_MPDU_QUEUE descriptor
+
+
+
+ <legal all>
+
+ring_id
+
+ Consumer: TQM/REO/RXDMA/SW
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+ It help to identify the ring that is being looked <legal
+ all>
+
+looping_count
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ A count value that indicates the number of times the
+ producer of entries into the Buffer Manager Ring has looped
+ around the ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+
+
+ /* EXTERNAL REFERENCE : struct buffer_addr_info released_buff_or_desc_addr_info */
+
+
+/* Description WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0
+
+ Address (lower 32 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0
+#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff
+
+/* Description WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32
+
+ Address (upper 8 bits) of the MSDU buffer OR
+ MSDU_EXTENSION descriptor OR Link Descriptor
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff
+
+/* Description WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER
+
+ Consumer: WBM
+
+ Producer: SW/FW
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ Indicates to which buffer manager the buffer OR
+ MSDU_EXTENSION descriptor OR link descriptor that is being
+ pointed to shall be returned after the frame has been
+ processed. It is used by WBM for routing purposes.
+
+
+
+ <enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+ to the WMB buffer idle list
+
+ <enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+ returned to the WMB idle link descriptor idle list
+
+ <enum 2 FW_BM> This buffer shall be returned to the FW
+
+ <enum 3 SW0_BM> This buffer shall be returned to the SW,
+ ring 0
+
+ <enum 4 SW1_BM> This buffer shall be returned to the SW,
+ ring 1
+
+ <enum 5 SW2_BM> This buffer shall be returned to the SW,
+ ring 2
+
+ <enum 6 SW3_BM> This buffer shall be returned to the SW,
+ ring 3
+
+ <enum 7 SW4_BM> This buffer shall be returned to the SW,
+ ring 4
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700
+
+/* Description WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE
+
+ Cookie field exclusively used by SW.
+
+
+
+ In case of 'NULL' pointer, this field is set to 0
+
+
+
+ HW ignores the contents, accept that it passes the
+ programmed value on to other descriptors together with the
+ physical address
+
+
+
+ Field can be used by SW to for example associate the
+ buffers physical address with the virtual address
+
+ The bit definitions as used by SW are within SW HLD
+ specification
+
+
+
+ NOTE1:
+
+ The three most significant bits can have a special
+ meaning in case this struct is embedded in a TX_MPDU_DETAILS
+ STRUCT, and field transmit_bw_restriction is set
+
+
+
+ In case of NON punctured transmission:
+
+ Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+
+ Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+
+
+
+ In case of punctured transmission:
+
+ Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only
+
+ Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only
+
+ Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only
+
+ Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only
+
+ Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only
+
+ Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only
+
+ Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only
+
+ Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only
+
+
+
+ Note: a punctured transmission is indicated by the
+ presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
+ TLV
+
+
+
+ NOTE 2:The five most significant bits can have a special
+ meaning in case this struct is embedded in an
+ RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
+ configured for passing on the additional info
+ from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
+ (FR56821). This is not supported in HastingsPrime, Pine or
+ Moselle.
+
+
+
+ Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
+ control field
+
+
+
+ Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
+ indicates MPDUs with a QoS control field.
+
+
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11
+#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800
+
+/* Description WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE
+
+ Indicates which module initiated the release of this
+ buffer or descriptor
+
+
+
+ <enum 0 release_source_TQM> TQM released this buffer or
+ descriptor
+
+ <enum 1 release_source_RXDMA> RXDMA released this buffer
+ or descriptor
+
+ <enum 2 release_source_REO> REO released this buffer or
+ descriptor
+
+ <enum 3 release_source_FW> FW released this buffer or
+ descriptor
+
+ <enum 4 release_source_SW> SW released this buffer or
+ descriptor
+
+ <legal 0-4>
+*/
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007
+
+/* Description WBM_RELEASE_RING_2_BM_ACTION
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ Field only valid when the field return_buffer_manager in
+ the Released_buff_or_desc_addr_info indicates:
+
+ WBM_IDLE_BUF_LIST or
+
+ WBM_IDLE_DESC_LIST
+
+
+
+ An MSDU extension descriptor shall never be marked as
+
+
+
+ <enum 0 Put_in_idle_list> Put the buffer or descriptor
+ back in the idle list. In case of MSDU or MDPU link
+ descriptor, BM does not need to check to release any
+ individual MSDU buffers
+
+
+
+ <enum 1 release_msdu_list > This BM action can only be
+ used in combination with buffer_or_desc_type being
+ msdu_link_descriptor. Field first_msdu_index points out
+ which MSDU pointer in the MSDU link descriptor is the first
+ of an MPDU that is released.
+
+ BM shall release all the MSDU buffers linked to this
+ first MSDU buffer pointer. All related MSDU buffer pointer
+ entries shall be set to value 0, which represents the 'NULL
+ pointer. When all MSDU buffer pointers in the MSDU link
+ descriptor are 'NULL', the MSDU link descriptor itself shall
+ also be released.
+
+
+
+ <enum 2 Put_in_idle_list_expanded> CURRENTLY NOT
+ IMPLEMENTED....
+
+ Put the buffer or descriptor back in the idle list. Only
+ valid in combination with buffer_or_desc_type indicating
+ MDPU_link_descriptor.
+
+ BM shall release the MPDU link descriptor as well as all
+ MSDUs that are linked to the MPDUs in this descriptor.
+
+
+
+ <legal 0-2>
+*/
+#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_BM_ACTION_LSB 3
+#define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038
+
+/* Description WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ Field only valid when WBM is marked as the
+ return_buffer_manager in the Released_Buffer_address_info
+
+
+
+ Indicates that type of buffer or descriptor is being
+ released
+
+
+
+ <enum 0 MSDU_rel_buffer> The address points to an MSDU
+ buffer
+
+ <enum 1 msdu_link_descriptor> The address points to an
+ TX MSDU link descriptor
+
+ <enum 2 mpdu_link_descriptor> The address points to an
+ MPDU link descriptor
+
+ <enum 3 msdu_ext_descriptor > The address points to an
+ MSDU extension descriptor.
+
+ In case BM finds this one in a release ring, it passes
+ it on to FW...
+
+ <enum 4 queue_ext_descriptor> The address points to an
+ TQM queue extension descriptor. WBM should treat this is the
+ same way as a link descriptor. That is, put the 128 byte
+ buffer back in the link buffer idle list.
+
+
+
+ <legal 0-4>
+*/
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0
+
+/* Description WBM_RELEASE_RING_2_FIRST_MSDU_INDEX
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ Field only valid for the bm_action release_msdu_list.
+
+
+
+ The index of the first MSDU in an MSDU link descriptor
+ all belonging to the same MPDU.
+
+
+
+ <legal 0-6>
+*/
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00
+
+/* Description WBM_RELEASE_RING_2_TQM_RELEASE_REASON
+
+ Consumer: WBM/SW/FW
+
+ Producer: TQM
+
+
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ (rr = Release Reason)
+
+ <enum 0 tqm_rr_frame_acked> frame is removed because an
+ ACK of BA for it was received
+
+ <enum 1 tqm_rr_rem_cmd_rem> frame is removed because a
+ remove command of type Remove_mpdus initiated by SW
+
+ <enum 2 tqm_rr_rem_cmd_tx> frame is removed because a
+ remove command of type Remove_transmitted_mpdus initiated by
+ SW
+
+ <enum 3 tqm_rr_rem_cmd_notx> frame is removed because a
+ remove command of type Remove_untransmitted_mpdus initiated
+ by SW
+
+ <enum 4 tqm_rr_rem_cmd_aged> frame is removed because a
+ remove command of type Remove_aged_mpdus or
+ Remove_aged_msdus initiated by SW
+
+ <enum 5 tqm_fw_reason1> frame is removed because a
+ remove command where fw indicated that remove reason is
+ fw_reason1
+
+ <enum 6 tqm_fw_reason2> frame is removed because a
+ remove command where fw indicated that remove reason is
+ fw_reason1
+
+ <enum 7 tqm_fw_reason3> frame is removed because a
+ remove command where fw indicated that remove reason is
+ fw_reason1
+
+ <enum 8 tqm_rr_rem_cmd_disable_queue> frame is removed
+ because a remove command of type
+ remove_mpdus_and_disable_queue or
+ remove_msdus_and_disable_flow initiated by SW
+
+
+
+ <legal 0-8>
+
+
+
+ In case of TQM releasing Tx MSDU link descriptors with
+ Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime
+ WBM can optionally release the MSDU buffers pointed to by
+ the MSDU link descriptors to FW and override the
+ tx_rate_stats field, for FW reinjection of these MSDUs
+ (FR54309). This is not supported in Pine.
+*/
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0001e000
+
+/* Description WBM_RELEASE_RING_2_RXDMA_PUSH_REASON
+
+ Field only valid when Release_source_module is set to
+ release_source_RXDMA
+
+
+
+ Indicates why rxdma pushed the frame to this ring
+
+
+
+ <enum 0 rxdma_error_detected> RXDMA detected an error an
+ pushed this frame to this queue
+
+ <enum 1 rxdma_routing_instruction> RXDMA pushed the
+ frame to this queue per received routing instructions. No
+ error within RXDMA was detected
+
+ <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a
+ result the MSDU link descriptor might not have the
+ last_msdu_in_mpdu_flag set, but instead WBM might just see a
+ NULL pointer in the MSDU link descriptor. This is to be
+ considered a normal condition for this scenario.
+
+
+
+ <legal 0 - 2>
+
+
+
+ In case of RXDMA releasing Rx MSDU link descriptors,'
+ Maple/Spruce WBM can optionally override the tx_rate_stats
+ field with Rx_msdu_desc_info_details (FR59859). This is not
+ supported in HastingsPrime, Pine or Moselle.
+*/
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 17
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00060000
+
+/* Description WBM_RELEASE_RING_2_RXDMA_ERROR_CODE
+
+ Field only valid when 'rxdma_push_reason' set to
+ 'rxdma_error_detected'.
+
+
+
+ <enum 0 rxdma_overflow_err>MPDU frame is not complete
+ due to a FIFO overflow error in RXPCU.
+
+ <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+ due to receiving incomplete MPDU from the PHY
+
+
+ <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+ error or CRYPTO received an encrypted frame, but did not get
+ a valid corresponding key id in the peer entry.
+
+ <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+ error
+
+ <enum 5 rxdma_unecrypted_err>CRYPTO reported an
+ unencrypted frame error when encrypted was expected
+
+ <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+ length error
+
+ <enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+ number of MSDUs allowed in an MPDU got exceeded
+
+ <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+ error
+
+ <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+ parsing error
+
+ <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+ during SA search
+
+ <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+ during DA search
+
+ <enum 12 rxdma_flow_timeout_err>RX OLE reported a
+ timeout during flow search
+
+ <enum 13 rxdma_flush_request>RXDMA received a flush
+ request
+
+ <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU
+ present as well as a fragmented MPDU. A-MSDU defragmentation
+ is not supported in Lithium SW so this is treated as an
+ error.
+*/
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 19
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x00f80000
+
+/* Description WBM_RELEASE_RING_2_REO_PUSH_REASON
+
+ Field only valid when Release_source_module is set to
+ release_source_REO
+
+
+
+ Indicates why REO pushed the frame to this release ring
+
+
+
+ <enum 0 reo_error_detected> Reo detected an error an
+ pushed this frame to this queue
+
+ <enum 1 reo_routing_instruction> Reo pushed the frame to
+ this queue per received routing instructions. No error
+ within REO was detected
+
+
+
+ <legal 0 - 1>
+
+
+
+ In case of REO releasing Rx MSDU link descriptors,'
+ Maple/Spruce WBM can optionally override
+ the tx_rate_stats field with
+ Rx_msdu_desc_info_details (FR59859). This is not supported
+ in HastingsPrime, Pine or Moselle.
+*/
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 24
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x03000000
+
+/* Description WBM_RELEASE_RING_2_REO_ERROR_CODE
+
+ Field only valid when 'Reo_push_reason' set to
+ 'reo_error_detected'.
+
+
+
+ <enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+ provided in the REO_ENTRANCE ring is set to 0
+
+ <enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+ valid bit is NOT set
+
+ <enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+ session having been setup.
+
+ <enum 3 non_ba_duplicate> Non-BA session, SN equal to
+ SSN, Retry bit set: duplicate frame
+
+ <enum 4 ba_duplicate> BA session, duplicate frame
+
+ <enum 5 regular_frame_2k_jump> A normal (management/data
+ frame) received with 2K jump in SN
+
+ <enum 6 bar_frame_2k_jump> A bar received with 2K jump
+ in SSN
+
+ <enum 7 regular_frame_OOR> A normal (management/data
+ frame) received with SN falling within the OOR window
+
+ <enum 8 bar_frame_OOR> A bar received with SSN falling
+ within the OOR window
+
+ <enum 9 bar_frame_no_ba_session> A bar received without
+ a BA session
+
+ <enum 10 bar_frame_sn_equals_ssn> A bar received with
+ SSN equal to SN
+
+ <enum 11 pn_check_failed> PN Check Failed packet.
+
+ <enum 12 2k_error_handling_flag_set> Frame is forwarded
+ as a result of the 'Seq_2k_error_detected_flag' been set in
+ the REO Queue descriptor
+
+ <enum 13 pn_error_handling_flag_set> Frame is forwarded
+ as a result of the 'pn_error_detected_flag' been set in the
+ REO Queue descriptor
+
+ <enum 14 queue_descriptor_blocked_set> Frame is
+ forwarded as a result of the queue descriptor(address) being
+ blocked as SW/FW seems to be currently in the process of
+ making updates to this descriptor...
+
+
+
+ <legal 0-14>
+*/
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 26
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x7c000000
+
+/* Description WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR
+
+ Can only be set by WBM.
+
+
+
+ Is set when WBM got a buffer pointer but the action was
+ to push it to the idle link descriptor ring or do link
+ related activity
+
+ OR
+
+ Is set when WBM got a link buffer pointer but the action
+ was to push it to the buffer descriptor ring
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 31
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x80000000
+
+/* Description WBM_RELEASE_RING_3_TQM_STATUS_NUMBER
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ The value in this field is equal to value of the
+ 'TQM_CMD_Number' field the TQM command or the
+ 'TQM_add_cmd_Number' field from the TQM entrance ring
+ descriptor
+
+
+
+ This field helps to correlate the statuses with the TQM
+ commands.
+
+
+
+ NOTE that SW could program this number to be equal to
+ the PPDU_ID number in case direct correlation with the PPDU
+ ID is desired
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff
+
+/* Description WBM_RELEASE_RING_3_TRANSMIT_COUNT
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ The number of times this frame has been transmitted
+*/
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000
+
+/* Description WBM_RELEASE_RING_3_MSDU_CONTINUATION
+
+ FR53947 requests MSDU_continuation reporting for Rx
+ MSDUs in Pine and HastingsPrime for which
+ SW_release_details_valid may not be set.
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET 0x0000000c
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB 31
+#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK 0x80000000
+
+/* Description WBM_RELEASE_RING_4_ACK_FRAME_RSSI
+
+ This field is only valid when the source is TQM.
+
+
+
+ If this frame is removed as the result of the reception
+ of an ACK or BA, this field indicates the RSSI of the
+ received ACK or BA frame.
+
+
+
+ When the frame is removed as result of a direct remove
+ command from the SW, this field is set to 0x0 (which is
+ never a valid value when real RSSI is available)
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff
+
+/* Description WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ When set, some WBM specific release info for SW is
+ valid.
+
+ This is set when WMB got a 'release_msdu_list' command
+ from TQM and the return buffer manager is not WMB. WBM will
+ then de-aggregate all the MSDUs and pass them one at a time
+ on to the 'buffer owner'
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100
+
+/* Description WBM_RELEASE_RING_4_FIRST_MSDU
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ When set, this MSDU is the first MSDU pointed to in the
+ 'release_msdu_list' command.
+
+
+
+ FR53947 extends this to Rx MSDUs in Pine and
+ HastingsPrime for which SW_release_details_valid may not be
+ set.
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9
+#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200
+
+/* Description WBM_RELEASE_RING_4_LAST_MSDU
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ When set, this MSDU is the last MSDU pointed to in the
+ 'release_msdu_list' command.
+
+
+
+ FR53947 extends this to Rx MSDUs in Pine and
+ HastingsPrime for which SW_release_details_valid may not be
+ set.
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10
+#define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400
+
+/* Description WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ When set, this MSDU was part of an A-MSDU in MPDU
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800
+
+/* Description WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ This is the FW_tx_notify_frame field from the
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000
+
+/* Description WBM_RELEASE_RING_4_BUFFER_TIMESTAMP
+
+ Field only valid when SW_release_details_valid is set.
+
+
+
+ Consumer: SW
+
+ Producer: WBM
+
+
+
+ This is the Buffer_timestamp field from the
+ TX_MSDU_DETAILS for this frame from the MSDU link
+ descriptor.
+
+
+
+ Timestamp in units of 1024 µs
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000
+
+ /* EXTERNAL REFERENCE : struct tx_rate_stats_info tx_rate_stats */
+
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID
+
+ When set all other fields in this STRUCT contain valid
+ info.
+
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Indicates the BW of the upcoming transmission that shall
+ likely start in about 3 -4 us on the medium
+
+
+
+ <enum 0 transmit_bw_20_MHz>
+
+ <enum 1 transmit_bw_40_MHz>
+
+ <enum 2 transmit_bw_80_MHz>
+
+ <enum 3 transmit_bw_160_MHz>
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_LSB 1
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_MASK 0x00000006
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ The packet type
+
+ <enum 0 dot11a>802.11a PPDU type
+
+ <enum 1 dot11b>802.11b PPDU type
+
+ <enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+
+ <enum 3 dot11ac>802.11ac PPDU type
+
+ <enum 4 dot11ax>802.11ax PPDU type
+
+ <enum 5 dot11ba>802.11ba (WUR) PPDU type
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 3
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x00000078
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ When set, STBC transmission rate was used.
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_LSB 7
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000080
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ When set, use LDPC transmission rates
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_LSB 8
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000100
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ <enum 0 0_8_us_sgi > Legacy normal GI. Can also be
+ used for HE
+
+ <enum 1 0_4_us_sgi > Legacy short GI. Can also be
+ used for HE
+
+ <enum 2 1_6_us_sgi > HE related GI
+
+ <enum 3 3_2_us_sgi > HE related GI
+
+ <legal 0 - 3>
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_LSB 9
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000600
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ For details, refer to MCS_TYPE description
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_LSB 11
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x00007800
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+
+
+ Set when the transmission was an OFDMA transmission (DL
+ or UL).
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 15
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00008000
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Field filled in by PDG.
+
+ Not valid when in SW transmit mode
+
+
+
+ The number of tones in the RU used.
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_LSB 16
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_MASK 0x0fff0000
+
+/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A
+
+ <legal 0>
+*/
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_LSB 28
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_MASK 0xf0000000
+
+/* Description WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF
+
+ Field only valid when Tx_rate_stats_info_valid is set
+
+
+
+ Based on a HWSCH configuration register setting, this
+ field either contains:
+
+
+
+ Lower 32 bits of the TSF, snapshot of this value when
+ transmission of the PPDU containing the frame finished.
+
+ OR
+
+ Lower 32 bits of the TSF, snapshot of this value when
+ transmission of the PPDU containing the frame started
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff
+
+/* Description WBM_RELEASE_RING_7_SW_PEER_ID
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ 1) Release of msdu buffer due to drop_frame = 1. Flow is
+ not fetched and hence sw_peer_id and tid = 0
+
+ buffer_or_desc_type = e_num 0
+ MSDU_rel_buffertqm_release_reason = e_num 1
+ tqm_rr_rem_cmd_rem
+
+
+
+
+
+ 2) Release of msdu buffer due to Flow is not fetched and
+ hence sw_peer_id and tid = 0
+
+ buffer_or_desc_type = e_num 0
+ MSDU_rel_buffertqm_release_reason = e_num 1
+ tqm_rr_rem_cmd_rem
+
+
+
+
+
+ 3) Release of msdu link due to remove_mpdu or acked_mpdu
+ command.
+
+ buffer_or_desc_type = e_num1
+ msdu_link_descriptortqm_release_reason can be:e_num 1
+ tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx
+
+ e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged
+
+
+
+ Sw_peer_id from the TX_MSDU_FLOW descriptor or
+ TX_MPDU_QUEUE descriptor
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0
+#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff
+
+/* Description WBM_RELEASE_RING_7_TID
+
+ Field only valid when Release_source_module is set to
+ release_source_TQM
+
+
+
+ 1) Release of msdu buffer due to drop_frame = 1. Flow is
+ not fetched and hence sw_peer_id and tid = 0
+
+ buffer_or_desc_type = e_num 0
+ MSDU_rel_buffertqm_release_reason = e_num 1
+ tqm_rr_rem_cmd_rem
+
+
+
+
+
+ 2) Release of msdu buffer due to Flow is not fetched and
+ hence sw_peer_id and tid = 0
+
+ buffer_or_desc_type = e_num 0
+ MSDU_rel_buffertqm_release_reason = e_num 1
+ tqm_rr_rem_cmd_rem
+
+
+
+
+
+ 3) Release of msdu link due to remove_mpdu or acked_mpdu
+ command.
+
+ buffer_or_desc_type = e_num1
+ msdu_link_descriptortqm_release_reason can be:e_num 1
+ tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx
+
+ e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged
+
+
+
+
+
+ This field represents the TID from the TX_MSDU_FLOW
+ descriptor or TX_MPDU_QUEUE descriptor
+
+
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_7_TID_LSB 16
+#define WBM_RELEASE_RING_7_TID_MASK 0x000f0000
+
+/* Description WBM_RELEASE_RING_7_RING_ID
+
+ Consumer: TQM/REO/RXDMA/SW
+
+ Producer: SRNG (of RXDMA)
+
+
+
+ For debugging.
+
+ This field is filled in by the SRNG module.
+
+ It help to identify the ring that is being looked <legal
+ all>
+*/
+#define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_7_RING_ID_LSB 20
+#define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000
+
+/* Description WBM_RELEASE_RING_7_LOOPING_COUNT
+
+ Consumer: WBM/SW/FW
+
+ Producer: SW/TQM/RXDMA/REO/SWITCH
+
+
+
+ A count value that indicates the number of times the
+ producer of entries into the Buffer Manager Ring has looped
+ around the ring.
+
+ At initialization time, this value is set to 0. On the
+ first loop, this value is set to 1. After the max value is
+ reached allowed by the number of bits for this field, the
+ count value continues with 0 again.
+
+
+
+ In case SW is the consumer of the ring entries, it can
+ use this field to figure out up to where the producer of
+ entries has created new entries. This eliminates the need to
+ check where the head pointer' of the ring is located once
+ the SW starts processing an interrupt indicating that new
+ entries have been put into this ring...
+
+
+
+ Also note that SW if it wants only needs to look at the
+ LSB bit of this count value.
+
+ <legal all>
+*/
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000
+
+
+#endif // _WBM_RELEASE_RING_H_
diff --git a/hw/qca5018/wcss_seq_hwiobase.h b/hw/qca5018/wcss_seq_hwiobase.h
new file mode 100644
index 0000000..5138e5a
--- /dev/null
+++ b/hw/qca5018/wcss_seq_hwiobase.h
@@ -0,0 +1,619 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/21/2020
+// User Name:c_landav
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WCSS_SEQ_BASE_H__
+#define __WCSS_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wcss
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WCSS_ECAHB_OFFSET 0x00008400
+#define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000
+#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000
+#define SEQ_WCSS_PHYA_OFFSET 0x00300000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400
+#define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00381800
+#define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00
+#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00382c00
+#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00383000
+#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000
+#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000
+#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000
+#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000
+#define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000
+#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00400000
+#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000
+#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_OFFSET 0x004c0000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x004d4000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x004d4000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x004d4240
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x004d42c0
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_CAL_OFFSET 0x004d42e0
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x004d4300
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x004d4400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x004d4480
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x004d4800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_DPLL_OFFSET 0x004d4c00
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x004d6000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x004d6040
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x004d6100
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x004d6140
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x004d6180
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x004d61c0
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x004d6240
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x004d7c00
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_OFFSET 0x004da000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_PMU_PMU_OFFSET 0x004da000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x004dc000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_CH2_OFFSET 0x004dc000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_HLS_BT_REGFILE_OFFSET 0x004dc400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x004dc800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x004dc840
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x004dc880
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x004dc8c0
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x004e0000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH0_OFFSET 0x004e0000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x004e0400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x004e0800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH0_OFFSET 0x004e1000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH0_OFFSET 0x004e1300
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x004e1600
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH0_OFFSET 0x004e1640
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH0_OFFSET 0x004e2000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH0_OFFSET 0x004e4000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_CH1_OFFSET 0x004e8000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x004e8400
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x004e8800
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE2_CH1_OFFSET 0x004e9000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE2_CH1_OFFSET 0x004e9300
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x004e9600
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_LO_CH1_OFFSET 0x004e9640
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_CH1_OFFSET 0x004ea000
+#define SEQ_WCSS_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_CH1_OFFSET 0x004ec000
+#define SEQ_WCSS_UMAC_OFFSET 0x00a00000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000
+#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000
+#define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000
+#define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000
+#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000
+#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000
+#define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000
+#define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET 0x00a47000
+#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000
+#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000
+#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000
+#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000
+#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000
+#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000
+#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000
+#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000
+#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000
+#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000
+#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000
+#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000
+#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000
+#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000
+#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000
+#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000
+#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000
+#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000
+#define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000
+#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000
+#define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000
+#define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000
+#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000
+#define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000
+#define SEQ_WCSS_WL_MSIP_OFFSET 0x00b80000
+#define SEQ_WCSS_WL_MSIP_RBIST_TX_CH0_OFFSET 0x00b80000
+#define SEQ_WCSS_WL_MSIP_WL_DAC_CH0_OFFSET 0x00b80180
+#define SEQ_WCSS_WL_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00b80190
+#define SEQ_WCSS_WL_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00b80200
+#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x00b802c0
+#define SEQ_WCSS_WL_MSIP_WL_ADC_CH0_OFFSET 0x00b80400
+#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00b80428
+#define SEQ_WCSS_WL_MSIP_RBIST_TX_CH1_OFFSET 0x00b81000
+#define SEQ_WCSS_WL_MSIP_WL_DAC_CH1_OFFSET 0x00b81180
+#define SEQ_WCSS_WL_MSIP_WL_DAC_CALIB_CH1_OFFSET 0x00b81190
+#define SEQ_WCSS_WL_MSIP_WL_DAC_REGARRAY_CH1_OFFSET 0x00b81200
+#define SEQ_WCSS_WL_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x00b812c0
+#define SEQ_WCSS_WL_MSIP_WL_ADC_CH1_OFFSET 0x00b81400
+#define SEQ_WCSS_WL_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00b81428
+#define SEQ_WCSS_WL_MSIP_MSIP_TMUX_OFFSET 0x00b8d000
+#define SEQ_WCSS_WL_MSIP_MSIP_OTP_OFFSET 0x00b8d080
+#define SEQ_WCSS_WL_MSIP_MSIP_LDO_CTRL_OFFSET 0x00b8d0ac
+#define SEQ_WCSS_WL_MSIP_MSIP_CLKGEN_OFFSET 0x00b8d100
+#define SEQ_WCSS_WL_MSIP_MSIP_BIAS_OFFSET 0x00b8e000
+#define SEQ_WCSS_WL_MSIP_BBPLL_OFFSET 0x00b8f000
+#define SEQ_WCSS_WL_MSIP_WL_TOP_CLKGEN_OFFSET 0x00b8f100
+#define SEQ_WCSS_WL_MSIP_MSIP_DRM_REG_OFFSET 0x00b8fc00
+#define SEQ_WCSS_DBG_OFFSET 0x00b90000
+#define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000
+#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000
+#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000
+#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000
+#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000
+#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000
+#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000
+#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000
+#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000
+#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000
+#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000
+#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000
+#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000
+#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000
+#define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000
+#define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000
+#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000
+#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000
+#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000
+#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000
+#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000
+#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000
+#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000
+#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280
+#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000
+#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000
+#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280
+#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000
+#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000
+#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000
+#define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000
+#define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000
+#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_OFFSET 0x00be0000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_PHYB_NOC_OFFSET 0x00be0000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_ITM_OFFSET 0x00be8000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_DWT_OFFSET 0x00be9000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_FPB_OFFSET 0x00bea000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_SCS_OFFSET 0x00beb000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_ETM_OFFSET 0x00bec000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000
+#define SEQ_WCSS_DBG_PHYA_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000
+#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000
+#define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000
+#define SEQ_WCSS_WCSS_ACMT_OFFSET 0x00c9f000
+#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000
+#define SEQ_WCSS_CC_OFFSET 0x00cb0000
+#define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000
+#define SEQ_WCSS_Q6SS_WLAN_OFFSET 0x00d00000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_OFFSET 0x00d00000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00d00000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00d00000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00d80000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00d80000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00d90000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00da0000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00da1000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00da2000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00da3000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00db0000
+#define SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00db0000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wfax_top
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000
+#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400
+#define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800
+#define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00
+#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00082c00
+#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00083000
+#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000
+#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000
+#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000
+#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000
+#define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000
+#define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET 0x00100000
+#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000
+#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_from_wsi
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_CAL_OFFSET 0x000142e0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400
+#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480
+#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800
+#define SEQ_RFA_FROM_WSI_RFA_CMN_DPLL_OFFSET 0x00014c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0
+#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016240
+#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00
+#define SEQ_RFA_FROM_WSI_RFA_PMU_OFFSET 0x0001a000
+#define SEQ_RFA_FROM_WSI_RFA_PMU_PMU_OFFSET 0x0001a000
+#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_CH2_OFFSET 0x0001c000
+#define SEQ_RFA_FROM_WSI_RFA_BT_HLS_BT_REGFILE_OFFSET 0x0001c400
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001c800
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001c840
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001c880
+#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001c8c0
+#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH0_OFFSET 0x00020000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00020400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00020800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00021000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00021300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00021600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH0_OFFSET 0x00021640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH0_OFFSET 0x00022000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH0_OFFSET 0x00024000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_CH1_OFFSET 0x00028000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00028400
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00028800
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00029000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00029300
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00029600
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_LO_CH1_OFFSET 0x00029640
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_CH1_OFFSET 0x0002a000
+#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_CH1_OFFSET 0x0002c000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_cmn
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_CMN_AON_OFFSET 0x00000000
+#define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240
+#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0
+#define SEQ_RFA_CMN_AON_COEX_CAL_OFFSET 0x000002e0
+#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300
+#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400
+#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480
+#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800
+#define SEQ_RFA_CMN_DPLL_OFFSET 0x00000c00
+#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000
+#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040
+#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100
+#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140
+#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180
+#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0
+#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002240
+#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_pmu
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_PMU_PMU_OFFSET 0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_bt
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_BT_BT_CH2_OFFSET 0x00000000
+#define SEQ_RFA_BT_HLS_BT_REGFILE_OFFSET 0x00000400
+#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00000800
+#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00000840
+#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00000880
+#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x000008c0
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_wl
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_WL_WL_MC_CH0_OFFSET 0x00000000
+#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00000400
+#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00000800
+#define SEQ_RFA_WL_WL_RXFE2_CH0_OFFSET 0x00001000
+#define SEQ_RFA_WL_WL_TXFE2_CH0_OFFSET 0x00001300
+#define SEQ_RFA_WL_WL_LO_PAL_CH0_OFFSET 0x00001600
+#define SEQ_RFA_WL_WL_LO_CH0_OFFSET 0x00001640
+#define SEQ_RFA_WL_WL_TPC_CH0_OFFSET 0x00002000
+#define SEQ_RFA_WL_WL_MEM_CH0_OFFSET 0x00004000
+#define SEQ_RFA_WL_WL_MC_CH1_OFFSET 0x00008000
+#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00008400
+#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00008800
+#define SEQ_RFA_WL_WL_RXFE2_CH1_OFFSET 0x00009000
+#define SEQ_RFA_WL_WL_TXFE2_CH1_OFFSET 0x00009300
+#define SEQ_RFA_WL_WL_LO_PAL_CH1_OFFSET 0x00009600
+#define SEQ_RFA_WL_WL_LO_CH1_OFFSET 0x00009640
+#define SEQ_RFA_WL_WL_TPC_CH1_OFFSET 0x0000a000
+#define SEQ_RFA_WL_WL_MEM_CH1_OFFSET 0x0000c000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block umac_top_reg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000
+#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000
+#define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000
+#define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000
+#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000
+#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000
+#define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000
+#define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET 0x00047000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block cxc_top_reg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000
+#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000
+#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000
+#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000
+#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000
+#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wmac_top_reg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000
+#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000
+#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000
+#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000
+#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000
+#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000
+#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000
+#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000
+#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000
+#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000
+#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000
+#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000
+#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000
+#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000
+#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000
+#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000
+#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000
+#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET 0x00036000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block msip
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_MSIP_RBIST_TX_CH0_OFFSET 0x00000000
+#define SEQ_MSIP_WL_DAC_CH0_OFFSET 0x00000180
+#define SEQ_MSIP_WL_DAC_CALIB_CH0_OFFSET 0x00000190
+#define SEQ_MSIP_WL_DAC_REGARRAY_CH0_OFFSET 0x00000200
+#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH0_OFFSET 0x000002c0
+#define SEQ_MSIP_WL_ADC_CH0_OFFSET 0x00000400
+#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH0_OFFSET 0x00000428
+#define SEQ_MSIP_RBIST_TX_CH1_OFFSET 0x00001000
+#define SEQ_MSIP_WL_DAC_CH1_OFFSET 0x00001180
+#define SEQ_MSIP_WL_DAC_CALIB_CH1_OFFSET 0x00001190
+#define SEQ_MSIP_WL_DAC_REGARRAY_CH1_OFFSET 0x00001200
+#define SEQ_MSIP_WL_DAC_BBCLKGEN_CH1_OFFSET 0x000012c0
+#define SEQ_MSIP_WL_ADC_CH1_OFFSET 0x00001400
+#define SEQ_MSIP_WL_ADC_BBCLKGEN_CH1_OFFSET 0x00001428
+#define SEQ_MSIP_MSIP_TMUX_OFFSET 0x0000d000
+#define SEQ_MSIP_MSIP_OTP_OFFSET 0x0000d080
+#define SEQ_MSIP_MSIP_LDO_CTRL_OFFSET 0x0000d0ac
+#define SEQ_MSIP_MSIP_CLKGEN_OFFSET 0x0000d100
+#define SEQ_MSIP_MSIP_BIAS_OFFSET 0x0000e000
+#define SEQ_MSIP_BBPLL_OFFSET 0x0000f000
+#define SEQ_MSIP_WL_TOP_CLKGEN_OFFSET 0x0000f100
+#define SEQ_MSIP_MSIP_DRM_REG_OFFSET 0x0000fc00
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wcssdbg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000
+#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000
+#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000
+#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000
+#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000
+#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000
+#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000
+#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000
+#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000
+#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000
+#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000
+#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000
+#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000
+#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000
+#define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000
+#define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000
+#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000
+#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000
+#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000
+#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000
+#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000
+#define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000
+#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000
+#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280
+#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000
+#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000
+#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280
+#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000
+#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000
+#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000
+#define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000
+#define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000
+#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_OFFSET 0x00050000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_PHYB_NOC_OFFSET 0x00050000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_ITM_OFFSET 0x00058000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_DWT_OFFSET 0x00059000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_FPB_OFFSET 0x0005a000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_SCS_OFFSET 0x0005b000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_ETM_OFFSET 0x0005c000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000
+#define SEQ_WCSSDBG_PHYA_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000
+#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
+#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block tpdm_atb128_cmb64
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280
+#define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block phyb_dbg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_PHYB_DBG_PHYB_NOC_OFFSET 0x00000000
+#define SEQ_PHYB_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000
+#define SEQ_PHYB_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000
+#define SEQ_PHYB_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000
+#define SEQ_PHYB_DBG_ITM_OFFSET 0x00008000
+#define SEQ_PHYB_DBG_DWT_OFFSET 0x00009000
+#define SEQ_PHYB_DBG_FPB_OFFSET 0x0000a000
+#define SEQ_PHYB_DBG_SCS_OFFSET 0x0000b000
+#define SEQ_PHYB_DBG_ETM_OFFSET 0x0000c000
+#define SEQ_PHYB_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000
+#define SEQ_PHYB_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block qdsp6v67ss_wlan
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_OFFSET 0x00000000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000
+#define SEQ_QDSP6V67SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block qdsp6v67ss
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET 0x00000000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET 0x00080000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00080000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00090000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x000a0000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x000a1000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x000a2000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x000a3000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x000b0000
+#define SEQ_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x000b0000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block qdsp6v67ss_public
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_QDSP6V67SS_PUBLIC_QDSP6V67SS_PUB_OFFSET 0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block qdsp6v67ss_private
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET 0x00000000
+#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET 0x00010000
+#define SEQ_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET 0x00020000
+#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET 0x00021000
+#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET 0x00022000
+#define SEQ_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET 0x00023000
+#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET 0x00030000
+#define SEQ_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET 0x00030000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block q6ss_rscc
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_Q6SS_RSCC_RSCC_RSC_OFFSET 0x00000000
+
+
+#endif
+
diff --git a/hw/qca5018/wcss_seq_hwiobase_ext.h b/hw/qca5018/wcss_seq_hwiobase_ext.h
new file mode 100644
index 0000000..427b2d5
--- /dev/null
+++ b/hw/qca5018/wcss_seq_hwiobase_ext.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 2/8/2019
+// User Name:dsriniva
+//
+// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WCSS_SEQ_BASE_EXT_H__
+#define __WCSS_SEQ_BASE_EXT_H__
+
+#ifdef SCALE_INCLUDES
+ #include "HALhwio.h"
+#else
+ #include "msmhwio.h"
+#endif
+
+
+#define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6V67SS_CSR_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_CSR_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6V67SS_L2VIC_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_L2VIC_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F0_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F1_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QTMR_F2_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6V67SS_RSCC_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_OFFSET
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PRIVATE_QDSP6V67SS_RSCC_RSCC_RSC_OFFSET
+#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6V67SS_PUB_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET
+#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET SEQ_WCSS_Q6SS_WLAN_QDSP6V67SS_QDSP6V67SS_PUBLIC_OFFSET
+
+#endif
diff --git a/hw/qca5018/wcss_version.h b/hw/qca5018/wcss_version.h
new file mode 100644
index 0000000..e59475d
--- /dev/null
+++ b/hw/qca5018/wcss_version.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#define WCSS_VERSION 55
diff --git a/hw/qca5018/wfss_ce_reg_seq_hwioreg.h b/hw/qca5018/wfss_ce_reg_seq_hwioreg.h
new file mode 100644
index 0000000..f62b82b
--- /dev/null
+++ b/hw/qca5018/wfss_ce_reg_seq_hwioreg.h
@@ -0,0 +1,15553 @@
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __WFSS_CE_REG_SEQ_HWIOREG_H__
+#define __WFSS_CE_REG_SEQ_HWIOREG_H__
+/*
+===========================================================================
+*/
+/**
+ @file wfss_ce_reg_seq_hwioreg.h
+ @brief Auto-generated HWIO interface include file.
+
+ Reference chip release:
+ IPQ5018/10/28 (Maple) [MAPLE_SOC_P3R16_20200308_wcss_62_0326]
+
+ This file contains HWIO register definitions for the following modules:
+ CE_.*
+
+ 'Exclude' filters applied: DUMMY RESERVED
+
+ Generation parameters:
+ { 'exclude-no-doc': True,
+ 'exclude-reserved': True,
+ 'explicit-addressing': True,
+ 'filename': 'wfss_ce_reg_seq_hwioreg.h',
+ 'ignore-prefixes': True,
+ 'module-filter-exclude': {},
+ 'module-filter-include': {},
+ 'modules': ['CE_.*'],
+ 'output-attrs': True,
+ 'output-fvals': True,
+ 'output-offsets': True,
+ 'output-phys': True,
+ 'output-resets': True,
+ 'rmsk-input': True,
+ 'unroll-array': True}
+
+ Attribute definitions for the HWIO_*_ATTR macros are as follows:
+ 0x0: Command register
+ 0x1: Read-Only
+ 0x2: Write-Only
+ 0x3: Read/Write
+*/
+/*
+ ===========================================================================
+
+ $Header: $
+ $DateTime: $
+ $Author: $
+
+ ===========================================================================
+*/
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_0_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+#define WFSS_CE_REG_BASE 0x08400000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x08400000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x08401000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x08402000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x08403000
+
+#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00000000)
+#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00000000)
+#define WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00000000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_0_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00001000)
+#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00001000)
+#define WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_OFFS 0x00001000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_1_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00002000)
+#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00002000)
+#define WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00002000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_1_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00003000)
+#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00003000)
+#define WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_OFFS 0x00003000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_2_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00004000)
+#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00004000)
+#define WFSS_CE_2_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00004000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_2_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00005000)
+#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00005000)
+#define WFSS_CE_2_CHANNEL_DST_REG_REG_BASE_OFFS 0x00005000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_3_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00006000)
+#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00006000)
+#define WFSS_CE_3_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00006000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_3_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00007000)
+#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00007000)
+#define WFSS_CE_3_CHANNEL_DST_REG_REG_BASE_OFFS 0x00007000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_4_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00008000)
+#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00008000)
+#define WFSS_CE_4_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00008000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_4_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00009000)
+#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00009000)
+#define WFSS_CE_4_CHANNEL_DST_REG_REG_BASE_OFFS 0x00009000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_5_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x0000a000)
+#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x0000a000)
+#define WFSS_CE_5_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000a000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_5_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x0000b000)
+#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x0000b000)
+#define WFSS_CE_5_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000b000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_6_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x0000c000)
+#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x0000c000)
+#define WFSS_CE_6_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000c000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_6_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x0000d000)
+#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x0000d000)
+#define WFSS_CE_6_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000d000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_7_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x0000e000)
+#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x0000e000)
+#define WFSS_CE_7_CHANNEL_SRC_REG_REG_BASE_OFFS 0x0000e000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_7_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x0000f000)
+#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x0000f000)
+#define WFSS_CE_7_CHANNEL_DST_REG_REG_BASE_OFFS 0x0000f000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_8_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00010000)
+#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00010000)
+#define WFSS_CE_8_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00010000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_8_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00011000)
+#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00011000)
+#define WFSS_CE_8_CHANNEL_DST_REG_REG_BASE_OFFS 0x00011000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_9_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00012000)
+#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00012000)
+#define WFSS_CE_9_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00012000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_9_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00013000)
+#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00013000)
+#define WFSS_CE_9_CHANNEL_DST_REG_REG_BASE_OFFS 0x00013000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_10_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00014000)
+#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00014000)
+#define WFSS_CE_10_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00014000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_10_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00015000)
+#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00015000)
+#define WFSS_CE_10_CHANNEL_DST_REG_REG_BASE_OFFS 0x00015000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_11_CHANNEL_SRC_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00016000)
+#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_USED 0x404
+#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00016000)
+#define WFSS_CE_11_CHANNEL_SRC_REG_REG_BASE_OFFS 0x00016000
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_11_CHANNEL_DST_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00017000)
+#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_USED 0x40c
+#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00017000)
+#define WFSS_CE_11_CHANNEL_DST_REG_REG_BASE_OFFS 0x00017000
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OFFS (0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OFFS (0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OFFS (0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OFFS (0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OFFS (0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OFFS (0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OFFS (0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OFFS (0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OFFS (0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR 0x00000003
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OFFS (0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OFFS (0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OFFS (0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OFFS (0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OFFS (0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OFFS (0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OFFS (0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OFFS (0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OFFS (0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OFFS (0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OFFS (0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) ((x) + 0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OFFS (0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) ((x) + 0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OFFS (0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x) ((x) + 0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OFFS (0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) ((x) + 0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OFFS (0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x) ((x) + 0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OFFS (0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR 0x00000080
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x) ((x) + 0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OFFS (0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x) ((x) + 0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OFFS (0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OFFS (0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OFFS (0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OFFS (0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR 0x00000000
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ATTR 0x3
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), m)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),v)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x),m,v,HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x))
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0
+
+/*----------------------------------------------------------------------------
+ * MODULE: WFSS_CE_COMMON_REG
+ *--------------------------------------------------------------------------*/
+
+#define WFSS_CE_COMMON_REG_REG_BASE (WFSS_CE_REG_BASE + 0x00018000)
+#define WFSS_CE_COMMON_REG_REG_BASE_SIZE 0x1000
+#define WFSS_CE_COMMON_REG_REG_BASE_USED 0x418
+#define WFSS_CE_COMMON_REG_REG_BASE_PHYS (WFSS_CE_REG_BASE_PHYS + 0x00018000)
+#define WFSS_CE_COMMON_REG_REG_BASE_OFFS 0x00018000
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x) ((x) + 0x00000000)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OFFS (0x00000000)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x) ((x) + 0x00000004)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OFFS (0x00000004)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0xff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0xff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x) ((x) + 0x00000008)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OFFS (0x00000008)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR 0x00000211
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xf
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x0000000c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OFFS (0x0000000c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x) ((x) + 0x00000010)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OFFS (0x00000010)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x800
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x) ((x) + 0x00000014)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x) ((x) + 0x00000014)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OFFS (0x00000014)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x1010101
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x1000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x10000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x100
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x) ((x) + 0x00000018)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x) ((x) + 0x00000018)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OFFS (0x00000018)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x3f3f3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x3f0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x3f00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x) ((x) + 0x0000001c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OFFS (0x0000001c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x) ((x) + 0x00000020)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OFFS (0x00000020)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x) ((x) + 0x00000024)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x) ((x) + 0x00000024)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OFFS (0x00000024)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0xfffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR 0x00240000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x8000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x4000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x2000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x1000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x800000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x700000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0xe0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1fe00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1fe
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x) ((x) + 0x00000028)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x) ((x) + 0x00000028)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OFFS (0x00000028)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR 0x00ff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x) ((x) + 0x0000002c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x) ((x) + 0x0000002c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OFFS (0x0000002c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0xffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0xffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x) ((x) + 0x00000030)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OFFS (0x00000030)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_PHYS(x) ((x) + 0x00000034)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OFFS (0x00000034)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK 0xfffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_PHYS(x) ((x) + 0x00000038)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OFFS (0x00000038)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK 0xfffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x0000003c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OFFS (0x0000003c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x00000040)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OFFS (0x00000040)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) ((x) + 0x00000044)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OFFS (0x00000044)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) ((x) + 0x00000048)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OFFS (0x00000048)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x) ((x) + 0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OFFS (0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x1ffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x1000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0xfff000
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x) ((x) + 0x00000050)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OFFS (0x00000050)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x) ((x) + 0x00000054)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OFFS (0x00000054)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0xffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0xfff000
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x) ((x) + 0x00000058)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OFFS (0x00000058)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x1ffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x1000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0xfff000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x) ((x) + 0x0000005c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OFFS (0x0000005c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x) ((x) + 0x00000060)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OFFS (0x00000060)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x) ((x) + 0x00000064)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OFFS (0x00000064)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_PHYS(x) ((x) + 0x00000068)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OFFS (0x00000068)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_PHYS(x) ((x) + 0x0000006c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OFFS (0x0000006c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_PHYS(x) ((x) + 0x00000070)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OFFS (0x00000070)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x) ((x) + 0x00000074)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_PHYS(x) ((x) + 0x00000074)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OFFS (0x00000074)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x) ((x) + 0x00000078)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x) ((x) + 0x00000078)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OFFS (0x00000078)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x) ((x) + 0x0000007c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OFFS (0x0000007c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x) ((x) + 0x00000080)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OFFS (0x00000080)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x) ((x) + 0x00000084)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OFFS (0x00000084)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x) ((x) + 0x00000088)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_PHYS(x) ((x) + 0x00000088)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OFFS (0x00000088)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK 0xfffdffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_BMSK 0x80000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_SHFT 0x1f
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_BMSK 0x40000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_SHFT 0x1e
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_BMSK 0x3ffc0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_SHFT 0x12
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK 0x10000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK 0xf000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT 0xc
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x) ((x) + 0x0000008c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_PHYS(x) ((x) + 0x0000008c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OFFS (0x0000008c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK 0xffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_BMSK 0xfff000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_SHFT 0xc
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x) ((x) + 0x00000090)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_PHYS(x) ((x) + 0x00000090)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OFFS (0x00000090)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK 0x1fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_BMSK 0x1000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_SHFT 0xc
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x) ((x) + 0x00000094)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_PHYS(x) ((x) + 0x00000094)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OFFS (0x00000094)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK 0xfff
+#define HWIO_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x) ((x) + 0x00000098)
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_PHYS(x) ((x) + 0x00000098)
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_OFFS (0x00000098)
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x) ((x) + 0x0000009c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_PHYS(x) ((x) + 0x0000009c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OFFS (0x0000009c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN(x))
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x) ((x) + 0x00000400)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OFFS (0x00000400)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x100ff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x10
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0xff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x) ((x) + 0x00000404)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OFFS (0x00000404)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x))
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x) ((x) + 0x00000408)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OFFS (0x00000408)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x))
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x) ((x) + 0x0000040c)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OFFS (0x0000040c)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x) ((x) + 0x00000410)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x) ((x) + 0x00000410)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OFFS (0x00000410)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0xff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ATTR 0x1
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0xff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) ((x) + 0x00000414)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) ((x) + 0x00000414)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OFFS (0x00000414)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR 0x7ffe0002
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x))
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0
+
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x) ((x) + 0x00000418)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x) ((x) + 0x00000418)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OFFS (0x00000418)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR 0x00000000
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_POR_RMSK 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ATTR 0x3
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, m) \
+ in_dword_masked(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), m)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, v) \
+ out_dword(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x),v)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x,m,v) \
+ out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x),m,v,HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x))
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0
+
+
+#endif /* __WFSS_CE_REG_SEQ_HWIOREG_H__ */
diff --git a/hw/qca5018/wfss_pmm_base_struct.h b/hw/qca5018/wfss_pmm_base_struct.h
new file mode 100644
index 0000000..fd97f7d
--- /dev/null
+++ b/hw/qca5018/wfss_pmm_base_struct.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//////////////////////////////////////////////////////////////////////////////
+// wfss_pmm_base_struct.h generated by: GenCStruct.pm
+//////////////////////////////////////////////////////////////////////////////
+// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
+//////////////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////////////
+// RCS File : -USE CVS LOG-
+// Revision : -USE CVS LOG-
+// Last Check In : -USE CVS LOG-
+//////////////////////////////////////////////////////////////////////////////
+// Description : Top C Struct file
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
+ #ifdef _LSB_TO_MSB_REGS
+ #ifdef _MSB_TO_LSB_REGS
+ #error You can not define both _LSB_TO_MSB_REGS and _MSB_TO_LSB_REGS!
+ #endif
+
+ #define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
+ #include "wfss_pmm_base_struct_ltm.h"
+ #endif
+
+ #ifdef _MSB_TO_LSB_REGS
+ #define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
+ #include "wfss_pmm_base_struct_mtl.h"
+ #endif
+
+ #ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
+ #error You have to define _LSB_TO_MSB_REGS or _MSB_TO_LSB_REGS
+ #endif
+
+#endif
+
diff --git a/hw/qca6750/v1/rx_flow_search_entry.h b/hw/qca6750/v1/rx_flow_search_entry.h
new file mode 100644
index 0000000..75a62b9
--- /dev/null
+++ b/hw/qca6750/v1/rx_flow_search_entry.h
@@ -0,0 +1,793 @@
+/*
+ * Copyright (c) 2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT! This file is automatically generated
+// These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_FLOW_SEARCH_ENTRY_H_
+#define _RX_FLOW_SEARCH_ENTRY_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+// Dword Fields
+// 0 src_ip_127_96[31:0]
+// 1 src_ip_95_64[31:0]
+// 2 src_ip_63_32[31:0]
+// 3 src_ip_31_0[31:0]
+// 4 dest_ip_127_96[31:0]
+// 5 dest_ip_95_64[31:0]
+// 6 dest_ip_63_32[31:0]
+// 7 dest_ip_31_0[31:0]
+// 8 src_port[15:0], dest_port[31:16]
+// 9 l4_protocol[7:0], valid[8], reserved_9[23:9], reo_destination_indication[28:24], msdu_drop[29], reo_destination_handler[31:30]
+// 10 metadata[31:0]
+// 11 aggregation_count[6:0], lro_eligible[7], msdu_count[31:8]
+// 12 msdu_byte_count[31:0]
+// 13 timestamp[31:0]
+// 14 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16]
+// 15 tcp_sequence_number[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16
+
+struct rx_flow_search_entry {
+ uint32_t src_ip_127_96 : 32; //[31:0]
+ uint32_t src_ip_95_64 : 32; //[31:0]
+ uint32_t src_ip_63_32 : 32; //[31:0]
+ uint32_t src_ip_31_0 : 32; //[31:0]
+ uint32_t dest_ip_127_96 : 32; //[31:0]
+ uint32_t dest_ip_95_64 : 32; //[31:0]
+ uint32_t dest_ip_63_32 : 32; //[31:0]
+ uint32_t dest_ip_31_0 : 32; //[31:0]
+ uint32_t src_port : 16, //[15:0]
+ dest_port : 16; //[31:16]
+ uint32_t l4_protocol : 8, //[7:0]
+ valid : 1, //[8]
+ reserved_9 : 15, //[23:9]
+ reo_destination_indication : 5, //[28:24]
+ msdu_drop : 1, //[29]
+ reo_destination_handler : 2; //[31:30]
+ uint32_t metadata : 32; //[31:0]
+ uint32_t aggregation_count : 7, //[6:0]
+ lro_eligible : 1, //[7]
+ msdu_count : 24; //[31:8]
+ uint32_t msdu_byte_count : 32; //[31:0]
+ uint32_t timestamp : 32; //[31:0]
+ uint32_t cumulative_l4_checksum : 16, //[15:0]
+ cumulative_ip_length : 16; //[31:16]
+ uint32_t tcp_sequence_number : 32; //[31:0]
+};
+
+/*
+
+src_ip_127_96
+
+ Uppermost 32 bits of source IPv6 address or prefix as
+ per Common Parser register field IP_DA_SA_PREFIX (with the
+ first byte in the MSB and the last byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order in an IPv6 packet)
+
+ <legal all>
+
+src_ip_95_64
+
+ Next 32 bits of source IPv6 address or prefix (requiring
+ a byte-swap for little-endian SW) <legal all>
+
+src_ip_63_32
+
+ Next 32 bits of source IPv6 address or lowest 32 bits of
+ prefix (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+
+src_ip_31_0
+
+ Lowest 32 bits of source IPv6 address, or source IPv4
+ address (requiring a byte-swap for little-endian SW w.r.t.
+ the byte order in an IPv6 or IPv4 packet)
+
+ <legal all>
+
+dest_ip_127_96
+
+ Uppermost 32 bits of destination IPv6 address or prefix
+ as per Common Parser register field IP_DA_SA_PREFIX (with
+ the first byte in the MSB and the last byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order as in an IPv6 packet)
+
+ <legal all>
+
+dest_ip_95_64
+
+ Next 32 bits of destination IPv6 address or prefix
+ (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+
+dest_ip_63_32
+
+ Next 32 bits of destination IPv6 address or lowest 32
+ bits of prefix (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+
+dest_ip_31_0
+
+ Lowest 32 bits of destination IPv6 address, or
+ destination IPv4 address (requiring a byte-swap for
+ little-endian SW w.r.t. the byte order in an IPv6 or IPv4
+ packet)
+
+ <legal all>
+
+src_port
+
+ LSB of SPI in case of ESP/AH
+
+ else source port in case of TCP/UDP without IPsec,
+
+ else zeros in case of ICMP (with the first/third byte in
+ the MSB and the second/fourth byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order as in an IPv6 or IPv4 packet) <legal all>
+
+dest_port
+
+ MSB of SPI in case of ESP/AH
+
+ else destination port in case of TCP/UDP without IPsec,
+
+ else zeros in case of ICMP (with the first byte in the
+ MSB and the second byte in the LSB, i.e. requiring a
+ byte-swap for little-endian SW w.r.t. the byte order as in
+ an IPv6 or IPv4 packet)
+
+ <legal all>
+
+l4_protocol
+
+ IPsec or L4 protocol
+
+
+
+ <enum 1 ICMPV4>
+
+ <enum 6 TCP>
+
+ <enum 17 UDP>
+
+ <enum 50 ESP>
+
+ <enum 51 AH>
+
+ <enum 58 ICMPV6>
+
+ <legal 1, 6, 17, 50, 51, 58>
+
+valid
+
+ Indicates validity of entry
+
+ <legal all>
+
+reserved_9
+
+ <legal 0>
+
+reo_destination_indication
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+
+msdu_drop
+
+ Overriding indication to REO to forward to REO release
+ ring
+
+ <legal all>
+
+reo_destination_handler
+
+ Indicates how to decide the REO destination indication
+
+ <enum 0 RXFT_USE_FT> Follow this entry
+
+ <enum 1 RXFT_USE_ASPT> Use address search+peer table
+ entry
+
+ <enum 2 RXFT_USE_FT2> Follow this entry
+
+ <enum 3 RXFT_USE_CCE> Use CCE super-rule
+
+ <legal all>
+
+metadata
+
+ Value to be passed to SW if this flow search entry
+ matches
+
+ <legal all>
+
+aggregation_count
+
+ FISA: Number'of MSDU's aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+lro_eligible
+
+ FISA: To indicate whether the previous MSDU for this
+ flow is eligible for LRO/FISA
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+msdu_count
+
+ Number of Rx MSDUs matching this flow
+
+ <legal all>
+
+msdu_byte_count
+
+ Number of bytes in Rx MSDUs matching this flow
+
+ <legal all>
+
+timestamp
+
+ Time of last reception (as measured at Rx OLE) matching
+ this flow
+
+ <legal all>
+
+cumulative_l4_checksum
+
+ FISA: checksum 'or MSDU's that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+cumulative_ip_length
+
+ FISA: Total MSDU length that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+
+tcp_sequence_number
+
+ FISA: TCP Sequence number of the last packet in this
+ flow to detect sequence number jump
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+
+
+/* Description RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96
+
+ Uppermost 32 bits of source IPv6 address or prefix as
+ per Common Parser register field IP_DA_SA_PREFIX (with the
+ first byte in the MSB and the last byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order in an IPv6 packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64
+
+ Next 32 bits of source IPv6 address or prefix (requiring
+ a byte-swap for little-endian SW) <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32
+
+ Next 32 bits of source IPv6 address or lowest 32 bits of
+ prefix (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0
+
+ Lowest 32 bits of source IPv6 address, or source IPv4
+ address (requiring a byte-swap for little-endian SW w.r.t.
+ the byte order in an IPv6 or IPv4 packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96
+
+ Uppermost 32 bits of destination IPv6 address or prefix
+ as per Common Parser register field IP_DA_SA_PREFIX (with
+ the first byte in the MSB and the last byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order as in an IPv6 packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64
+
+ Next 32 bits of destination IPv6 address or prefix
+ (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32
+
+ Next 32 bits of destination IPv6 address or lowest 32
+ bits of prefix (requiring a byte-swap for little-endian SW)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0
+
+ Lowest 32 bits of destination IPv6 address, or
+ destination IPv4 address (requiring a byte-swap for
+ little-endian SW w.r.t. the byte order in an IPv6 or IPv4
+ packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_8_SRC_PORT
+
+ LSB of SPI in case of ESP/AH
+
+ else source port in case of TCP/UDP without IPsec,
+
+ else zeros in case of ICMP (with the first/third byte in
+ the MSB and the second/fourth byte in the LSB, i.e.
+ requiring a byte-swap for little-endian SW w.r.t. the byte
+ order as in an IPv6 or IPv4 packet) <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_8_DEST_PORT
+
+ MSB of SPI in case of ESP/AH
+
+ else destination port in case of TCP/UDP without IPsec,
+
+ else zeros in case of ICMP (with the first byte in the
+ MSB and the second byte in the LSB, i.e. requiring a
+ byte-swap for little-endian SW w.r.t. the byte order as in
+ an IPv6 or IPv4 packet)
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16
+#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL
+
+ IPsec or L4 protocol
+
+
+
+ <enum 1 ICMPV4>
+
+ <enum 6 TCP>
+
+ <enum 17 UDP>
+
+ <enum 50 ESP>
+
+ <enum 51 AH>
+
+ <enum 58 ICMPV6>
+
+ <legal 1, 6, 17, 50, 51, 58>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_VALID
+
+ Indicates validity of entry
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8
+#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_RESERVED_9
+
+ <legal 0>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9
+#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION
+
+ The ID of the REO exit ring where the MSDU frame shall
+ push after (MPDU level) reordering has finished.
+
+
+
+ <enum 0 reo_destination_tcl> Reo will push the frame
+ into the REO2TCL ring
+
+ <enum 1 reo_destination_sw1> Reo will push the frame
+ into the REO2SW1 ring
+
+ <enum 2 reo_destination_sw2> Reo will push the frame
+ into the REO2SW2 ring
+
+ <enum 3 reo_destination_sw3> Reo will push the frame
+ into the REO2SW3 ring
+
+ <enum 4 reo_destination_sw4> Reo will push the frame
+ into the REO2SW4 ring
+
+ <enum 5 reo_destination_release> Reo will push the frame
+ into the REO_release ring
+
+ <enum 6 reo_destination_fw> Reo will push the frame into
+ the REO2FW ring
+
+ <enum 7 reo_destination_sw5> Reo will push the frame
+ into the REO2SW5 ring (REO remaps this in chips without
+ REO2SW5 ring, e.g. Pine)
+
+ <enum 8 reo_destination_sw6> Reo will push the frame
+ into the REO2SW6 ring (REO remaps this in chips without
+ REO2SW6 ring, e.g. Pine)
+
+ <enum 9 reo_destination_9> REO remaps this <enum 10
+ reo_destination_10> REO remaps this
+
+ <enum 11 reo_destination_11> REO remaps this
+
+ <enum 12 reo_destination_12> REO remaps this <enum 13
+ reo_destination_13> REO remaps this
+
+ <enum 14 reo_destination_14> REO remaps this
+
+ <enum 15 reo_destination_15> REO remaps this
+
+ <enum 16 reo_destination_16> REO remaps this
+
+ <enum 17 reo_destination_17> REO remaps this
+
+ <enum 18 reo_destination_18> REO remaps this
+
+ <enum 19 reo_destination_19> REO remaps this
+
+ <enum 20 reo_destination_20> REO remaps this
+
+ <enum 21 reo_destination_21> REO remaps this
+
+ <enum 22 reo_destination_22> REO remaps this
+
+ <enum 23 reo_destination_23> REO remaps this
+
+ <enum 24 reo_destination_24> REO remaps this
+
+ <enum 25 reo_destination_25> REO remaps this
+
+ <enum 26 reo_destination_26> REO remaps this
+
+ <enum 27 reo_destination_27> REO remaps this
+
+ <enum 28 reo_destination_28> REO remaps this
+
+ <enum 29 reo_destination_29> REO remaps this
+
+ <enum 30 reo_destination_30> REO remaps this
+
+ <enum 31 reo_destination_31> REO remaps this
+
+
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP
+
+ Overriding indication to REO to forward to REO release
+ ring
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29
+#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000
+
+/* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER
+
+ Indicates how to decide the REO destination indication
+
+ <enum 0 RXFT_USE_FT> Follow this entry
+
+ <enum 1 RXFT_USE_ASPT> Use address search+peer table
+ entry
+
+ <enum 2 RXFT_USE_FT2> Follow this entry
+
+ <enum 3 RXFT_USE_CCE> Use CCE super-rule
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30
+#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000
+
+/* Description RX_FLOW_SEARCH_ENTRY_10_METADATA
+
+ Value to be passed to SW if this flow search entry
+ matches
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT
+
+ FISA: Number'of MSDU's aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f
+
+/* Description RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE
+
+ FISA: To indicate whether the previous MSDU for this
+ flow is eligible for LRO/FISA
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7
+#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080
+
+/* Description RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT
+
+ Number of Rx MSDUs matching this flow
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8
+#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00
+
+/* Description RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT
+
+ Number of bytes in Rx MSDUs matching this flow
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP
+
+ Time of last reception (as measured at Rx OLE) matching
+ this flow
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM
+
+ FISA: checksum 'or MSDU's that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff
+
+/* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH
+
+ FISA: Total MSDU length that is part of this flow
+ aggregated so far
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16
+#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000
+
+/* Description RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER
+
+ FISA: TCP Sequence number of the last packet in this
+ flow to detect sequence number jump
+
+
+
+ Set to zero in chips not supporting FISA, e.g. Pine
+
+ <legal all>
+*/
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0
+#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff
+
+
+#endif // _RX_FLOW_SEARCH_ENTRY_H_
