| /* |
| * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. |
| * |
| * Permission to use, copy, modify, and/or distribute this software for |
| * any purpose with or without fee is hereby granted, provided that the |
| * above copyright notice and this permission notice appear in all |
| * copies. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| * PERFORMANCE OF THIS SOFTWARE. |
| */ |
| #include "hal_hw_headers.h" |
| #include "hal_internal.h" |
| #include "hal_api.h" |
| #include "target_type.h" |
| #include "wcss_version.h" |
| #include "qdf_module.h" |
| |
| #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ |
| RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET |
| #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ |
| RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK |
| #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ |
| RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB |
| #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ |
| PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET |
| #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ |
| PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET |
| #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ |
| PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET |
| #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ |
| PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET |
| #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ |
| PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET |
| #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ |
| PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET |
| #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ |
| PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET |
| #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ |
| PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET |
| #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ |
| PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET |
| #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ |
| PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET |
| #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ |
| PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET |
| #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ |
| RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET |
| #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ |
| RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET |
| #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ |
| RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET |
| #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ |
| RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET |
| #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ |
| REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET |
| #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ |
| STATUS_HEADER_REO_STATUS_NUMBER |
| #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ |
| STATUS_HEADER_TIMESTAMP |
| #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ |
| RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET |
| #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ |
| RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET |
| #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ |
| TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET |
| #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ |
| TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET |
| #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ |
| TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET |
| #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ |
| BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB |
| #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ |
| BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK |
| #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ |
| BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB |
| #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ |
| BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK |
| #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ |
| BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB |
| #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ |
| BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK |
| #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ |
| BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB |
| #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ |
| BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK |
| #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ |
| TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB |
| #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ |
| TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK |
| #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ |
| WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK |
| #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ |
| WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET |
| #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ |
| WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB |
| #include "hal_6018_tx.h" |
| #include "hal_6018_rx.h" |
| #include <hal_generic_api.h> |
| #include <hal_wbm.h> |
| |
| struct hal_hw_txrx_ops qca6018_hal_hw_txrx_ops = { |
| /* init and setup */ |
| hal_srng_dst_hw_init_generic, |
| hal_srng_src_hw_init_generic, |
| hal_get_hw_hptp_generic, |
| hal_reo_setup_generic, |
| hal_setup_link_idle_list_generic, |
| NULL, |
| |
| /* tx */ |
| hal_tx_desc_set_dscp_tid_table_id_6018, |
| hal_tx_set_dscp_tid_map_6018, |
| hal_tx_update_dscp_tid_6018, |
| hal_tx_desc_set_lmac_id_6018, |
| hal_tx_desc_set_buf_addr_generic, |
| hal_tx_desc_set_search_type_generic, |
| hal_tx_desc_set_search_index_generic, |
| hal_tx_comp_get_status_generic, |
| hal_tx_comp_get_release_reason_generic, |
| |
| /* rx */ |
| hal_rx_msdu_start_nss_get_6018, |
| hal_rx_mon_hw_desc_get_mpdu_status_6018, |
| hal_rx_get_tlv_6018, |
| hal_rx_proc_phyrx_other_receive_info_tlv_6018, |
| hal_rx_dump_msdu_start_tlv_6018, |
| hal_rx_dump_msdu_end_tlv_6018, |
| hal_get_link_desc_size_6018, |
| hal_rx_mpdu_start_tid_get_6018, |
| hal_rx_msdu_start_reception_type_get_6018, |
| hal_rx_msdu_end_da_idx_get_6018, |
| hal_rx_msdu_desc_info_get_ptr_generic, |
| hal_rx_link_desc_msdu0_ptr_generic, |
| hal_reo_status_get_header_generic, |
| hal_rx_status_get_tlv_info_generic, |
| hal_rx_wbm_err_info_get_generic, |
| hal_rx_dump_mpdu_start_tlv_generic, |
| |
| hal_tx_set_pcp_tid_map_generic, |
| hal_tx_update_pcp_tid_generic, |
| hal_tx_update_tidmap_prty_generic, |
| }; |
| |
| struct hal_hw_srng_config hw_srng_table_6018[] = { |
| /* TODO: max_rings can populated by querying HW capabilities */ |
| { /* REO_DST */ |
| .start_ring_id = HAL_SRNG_REO2SW1, |
| .max_rings = 4, |
| .entry_size = sizeof(struct reo_destination_ring) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_DST_RING, |
| .reg_start = { |
| HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| HWIO_REO_R2_REO2SW1_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET) |
| }, |
| .reg_size = { |
| HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - |
| HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), |
| HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - |
| HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), |
| }, |
| .max_size = |
| HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* REO_EXCEPTION */ |
| /* Designating REO2TCL ring as exception ring. This ring is |
| * similar to other REO2SW rings though it is named as REO2TCL. |
| * Any of theREO2SW rings can be used as exception ring. |
| */ |
| .start_ring_id = HAL_SRNG_REO2TCL, |
| .max_rings = 1, |
| .entry_size = sizeof(struct reo_destination_ring) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_DST_RING, |
| .reg_start = { |
| HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| HWIO_REO_R2_REO2TCL_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET) |
| }, |
| /* Single ring - provide ring size if multiple rings of this |
| * type are supported |
| */ |
| .reg_size = {}, |
| .max_size = |
| HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* REO_REINJECT */ |
| .start_ring_id = HAL_SRNG_SW2REO, |
| .max_rings = 1, |
| .entry_size = sizeof(struct reo_entrance_ring) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| .reg_start = { |
| HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| HWIO_REO_R2_SW2REO_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET) |
| }, |
| /* Single ring - provide ring size if multiple rings of this |
| * type are supported |
| */ |
| .reg_size = {}, |
| .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* REO_CMD */ |
| .start_ring_id = HAL_SRNG_REO_CMD, |
| .max_rings = 1, |
| .entry_size = (sizeof(struct tlv_32_hdr) + |
| sizeof(struct reo_get_queue_stats)) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| .reg_start = { |
| HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| HWIO_REO_R2_REO_CMD_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| }, |
| /* Single ring - provide ring size if multiple rings of this |
| * type are supported |
| */ |
| .reg_size = {}, |
| .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* REO_STATUS */ |
| .start_ring_id = HAL_SRNG_REO_STATUS, |
| .max_rings = 1, |
| .entry_size = (sizeof(struct tlv_32_hdr) + |
| sizeof(struct reo_get_queue_stats_status)) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_DST_RING, |
| .reg_start = { |
| HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_REO_REG_OFFSET), |
| }, |
| /* Single ring - provide ring size if multiple rings of this |
| * type are supported |
| */ |
| .reg_size = {}, |
| .max_size = |
| HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* TCL_DATA */ |
| .start_ring_id = HAL_SRNG_SW2TCL1, |
| .max_rings = 3, |
| .entry_size = (sizeof(struct tlv_32_hdr) + |
| sizeof(struct tcl_data_cmd)) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| .reg_start = { |
| HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| }, |
| .reg_size = { |
| HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - |
| HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), |
| HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - |
| HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), |
| }, |
| .max_size = |
| HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* TCL_CMD */ |
| .start_ring_id = HAL_SRNG_SW2TCL_CMD, |
| .max_rings = 1, |
| .entry_size = (sizeof(struct tlv_32_hdr) + |
| sizeof(struct tcl_gse_cmd)) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| .reg_start = { |
| HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| }, |
| /* Single ring - provide ring size if multiple rings of this |
| * type are supported |
| */ |
| .reg_size = {}, |
| .max_size = |
| HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* TCL_STATUS */ |
| .start_ring_id = HAL_SRNG_TCL_STATUS, |
| .max_rings = 1, |
| .entry_size = (sizeof(struct tlv_32_hdr) + |
| sizeof(struct tcl_status_ring)) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_DST_RING, |
| .reg_start = { |
| HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), |
| }, |
| /* Single ring - provide ring size if multiple rings of this |
| * type are supported |
| */ |
| .reg_size = {}, |
| .max_size = |
| HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* CE_SRC */ |
| .start_ring_id = HAL_SRNG_CE_0_SRC, |
| .max_rings = 12, |
| .entry_size = sizeof(struct ce_src_desc) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| .reg_start = { |
| HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), |
| HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), |
| }, |
| .reg_size = { |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, |
| }, |
| .max_size = |
| HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* CE_DST */ |
| .start_ring_id = HAL_SRNG_CE_0_DST, |
| .max_rings = 12, |
| .entry_size = 8 >> 2, |
| /*TODO: entry_size above should actually be |
| * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition |
| * of struct ce_dst_desc in HW header files |
| */ |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| .reg_start = { |
| HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), |
| HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), |
| }, |
| .reg_size = { |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, |
| }, |
| .max_size = |
| HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* CE_DST_STATUS */ |
| .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, |
| .max_rings = 12, |
| .entry_size = sizeof(struct ce_stat_desc) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_DST_RING, |
| .reg_start = { |
| HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), |
| HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), |
| }, |
| /* TODO: check destination status ring registers */ |
| .reg_size = { |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - |
| SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, |
| }, |
| .max_size = |
| HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* WBM_IDLE_LINK */ |
| .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, |
| .max_rings = 1, |
| .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| .reg_start = { |
| HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| }, |
| /* Single ring - provide ring size if multiple rings of this |
| * type are supported |
| */ |
| .reg_size = {}, |
| .max_size = |
| HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* SW2WBM_RELEASE */ |
| .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, |
| .max_rings = 1, |
| .entry_size = sizeof(struct wbm_release_ring) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| .reg_start = { |
| HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| }, |
| /* Single ring - provide ring size if multiple rings of this |
| * type are supported |
| */ |
| .reg_size = {}, |
| .max_size = |
| HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* WBM2SW_RELEASE */ |
| .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, |
| .max_rings = 4, |
| .entry_size = sizeof(struct wbm_release_ring) >> 2, |
| .lmac_ring = FALSE, |
| .ring_dir = HAL_SRNG_DST_RING, |
| .reg_start = { |
| HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| }, |
| .reg_size = { |
| HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - |
| HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - |
| HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), |
| }, |
| .max_size = |
| HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> |
| HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, |
| }, |
| { /* RXDMA_BUF */ |
| .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, |
| #ifdef IPA_OFFLOAD |
| .max_rings = 3, |
| #else |
| .max_rings = 2, |
| #endif |
| .entry_size = sizeof(struct wbm_buffer_ring) >> 2, |
| .lmac_ring = TRUE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| /* reg_start is not set because LMAC rings are not accessed |
| * from host |
| */ |
| .reg_start = {}, |
| .reg_size = {}, |
| .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| }, |
| { /* RXDMA_DST */ |
| .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, |
| .max_rings = 1, |
| .entry_size = sizeof(struct reo_entrance_ring) >> 2, |
| .lmac_ring = TRUE, |
| .ring_dir = HAL_SRNG_DST_RING, |
| /* reg_start is not set because LMAC rings are not accessed |
| * from host |
| */ |
| .reg_start = {}, |
| .reg_size = {}, |
| .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| }, |
| { /* RXDMA_MONITOR_BUF */ |
| .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, |
| .max_rings = 1, |
| .entry_size = sizeof(struct wbm_buffer_ring) >> 2, |
| .lmac_ring = TRUE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| /* reg_start is not set because LMAC rings are not accessed |
| * from host |
| */ |
| .reg_start = {}, |
| .reg_size = {}, |
| .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| }, |
| { /* RXDMA_MONITOR_STATUS */ |
| .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, |
| .max_rings = 1, |
| .entry_size = sizeof(struct wbm_buffer_ring) >> 2, |
| .lmac_ring = TRUE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| /* reg_start is not set because LMAC rings are not accessed |
| * from host |
| */ |
| .reg_start = {}, |
| .reg_size = {}, |
| .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| }, |
| { /* RXDMA_MONITOR_DST */ |
| .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, |
| .max_rings = 1, |
| .entry_size = sizeof(struct reo_entrance_ring) >> 2, |
| .lmac_ring = TRUE, |
| .ring_dir = HAL_SRNG_DST_RING, |
| /* reg_start is not set because LMAC rings are not accessed |
| * from host |
| */ |
| .reg_start = {}, |
| .reg_size = {}, |
| .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| }, |
| { /* RXDMA_MONITOR_DESC */ |
| .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, |
| .max_rings = 1, |
| .entry_size = sizeof(struct wbm_buffer_ring) >> 2, |
| .lmac_ring = TRUE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| /* reg_start is not set because LMAC rings are not accessed |
| * from host |
| */ |
| .reg_start = {}, |
| .reg_size = {}, |
| .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| }, |
| { /* DIR_BUF_RX_DMA_SRC */ |
| .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, |
| .max_rings = 1, |
| .entry_size = 2, |
| .lmac_ring = TRUE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| /* reg_start is not set because LMAC rings are not accessed |
| * from host |
| */ |
| .reg_start = {}, |
| .reg_size = {}, |
| .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| }, |
| #ifdef WLAN_FEATURE_CIF_CFR |
| { /* WIFI_POS_SRC */ |
| .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, |
| .max_rings = 1, |
| .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, |
| .lmac_ring = TRUE, |
| .ring_dir = HAL_SRNG_SRC_RING, |
| /* reg_start is not set because LMAC rings are not accessed |
| * from host |
| */ |
| .reg_start = {}, |
| .reg_size = {}, |
| .max_size = HAL_RXDMA_MAX_RING_SIZE, |
| }, |
| #endif |
| }; |
| |
| int32_t hal_hw_reg_offset_qca6018[] = { |
| /* dst */ |
| REG_OFFSET(DST, HP), |
| REG_OFFSET(DST, TP), |
| REG_OFFSET(DST, ID), |
| REG_OFFSET(DST, MISC), |
| REG_OFFSET(DST, HP_ADDR_LSB), |
| REG_OFFSET(DST, HP_ADDR_MSB), |
| REG_OFFSET(DST, MSI1_BASE_LSB), |
| REG_OFFSET(DST, MSI1_BASE_MSB), |
| REG_OFFSET(DST, MSI1_DATA), |
| REG_OFFSET(DST, BASE_LSB), |
| REG_OFFSET(DST, BASE_MSB), |
| REG_OFFSET(DST, PRODUCER_INT_SETUP), |
| /* src */ |
| REG_OFFSET(SRC, HP), |
| REG_OFFSET(SRC, TP), |
| REG_OFFSET(SRC, ID), |
| REG_OFFSET(SRC, MISC), |
| REG_OFFSET(SRC, TP_ADDR_LSB), |
| REG_OFFSET(SRC, TP_ADDR_MSB), |
| REG_OFFSET(SRC, MSI1_BASE_LSB), |
| REG_OFFSET(SRC, MSI1_BASE_MSB), |
| REG_OFFSET(SRC, MSI1_DATA), |
| REG_OFFSET(SRC, BASE_LSB), |
| REG_OFFSET(SRC, BASE_MSB), |
| REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0), |
| REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1), |
| }; |
| |
| /** |
| * hal_qca6018_attach() - Attach 6018 target specific hal_soc ops, |
| * offset and srng table |
| */ |
| void hal_qca6018_attach(struct hal_soc *hal_soc) |
| { |
| hal_soc->hw_srng_table = hw_srng_table_6018; |
| hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6018; |
| hal_soc->ops = &qca6018_hal_hw_txrx_ops; |
| } |
