| /* |
| * Copyright (c) 2015-2016 The Linux Foundation. All rights reserved. |
| * |
| * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| * |
| * |
| * Permission to use, copy, modify, and/or distribute this software for |
| * any purpose with or without fee is hereby granted, provided that the |
| * above copyright notice and this permission notice appear in all |
| * copies. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| * PERFORMANCE OF THIS SOFTWARE. |
| */ |
| |
| /* |
| * This file was originally distributed by Qualcomm Atheros, Inc. |
| * under proprietary terms before Copyright ownership was assigned |
| * to the Linux Foundation. |
| */ |
| |
| #ifndef ADRASTEA_REG_DEF_H |
| #define ADRASTEA_REG_DEF_H |
| |
| /* |
| * Start auto-generated headers from register parser |
| * |
| * DO NOT CHANGE MANUALLY |
| */ |
| |
| |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___S 1 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW (0x00241000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___M 0x00000001 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2 (0x00030028) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___POR 0x000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW (0x00244000) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___M 0x00000001 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___M 0x000003FF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_DIRTY___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE (0x00032060) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6 (0x00030038) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH (0x00032064) |
| #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_DIRTY___M 0x00FFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___S 1 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___M 0x00000010 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___M 0x00000080 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___M 0x00000010 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___S 17 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___M 0x0003FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___M 0x00000002 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___M 0x00FFF000 |
| #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___M 0x00FFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4 (0x00030030) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___M 0x00000100 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___S 4 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___M 0x00000001 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX (0x00240040) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS (0x00240038) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR (0x002F1008) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___M 0x00000080 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___M 0x00000010 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___M 0x00000FFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___M 0x00000002 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20 (0x00030070) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12 (0x00032030) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___M 0x00000002 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___POR 0x000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___S 18 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___M 0x00000FFF |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB (0x00032070) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___M 0x00000080 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___S 9 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13 (0x00032034) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3 (0x0003002C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID (0x000300E0) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22 (0x00032058) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___M 0x00000020 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14 (0x00030058) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___M 0x0000007F |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___S 19 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1 (0x00032004) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___S 5 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___M 0x00000004 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___M 0x00000FFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14 (0x00032038) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___M 0x00000010 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___M 0x00000FFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___M 0x00000001 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___S 1 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___M 0x00000010 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___S 4 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___M 0x0000001F |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23 (0x0003205C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE (0x00240034) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY (0x0024D000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15 (0x0003005C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE (0x0024002C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___S 4 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN2_HW2SW_GRANT___S 7 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___M 0x0000001F |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___M 0x00000010 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___M 0x01FFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___POR 0x000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___POR 0x0000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___S 24 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0 (0x00032000) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___M 0xFFFF0000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR (0x00030014) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___M 0x00000080 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20 (0x00032050) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___S 3 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___S 2 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___M 0x00008000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___POR 0x0000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___M 0x00020000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW (0x0024B000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET (0x002F1004) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2 (0x00032008) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___S 5 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___M 0xFFFF0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___POR 0x00 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___M 0x00000002 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___M 0x00000001 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___S 2 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___M 0x00000060 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___S 6 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__EXTERNAL_INTR___M 0x0FFC0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___POR 0x0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___S 6 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___S 8 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW (0x00245000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22 (0x00030078) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___M 0x00000040 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___POR 0x00000005 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___S 3 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___POR 0x000 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___S 1 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__ADDRESS_BITS_17_TO_2___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___POR 0x1 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK (0x0024004C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___M 0x00000004 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___S 11 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17 (0x00030064) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW (0x0024000C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___M 0x00FFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__DESC_SKIP_DWORD___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW (0x0024A000) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___S 4 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___M 0x00000003 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___M 0x00000040 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS (0x00030008) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___S 3 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___M 0x00010000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___M 0x000FF800 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___S 8 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___M 0x00000010 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19 (0x0003204C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___S 3 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5 (0x00030034) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___M 0x00000020 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___M 0x00000FFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___M 0x00FFF000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___S 4 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__MSI_EN___S 16 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE___M 0x000FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___M 0x000FF800 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___M 0x00010000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___POR 0x0000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___S 8 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___M 0x00000080 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__SIZE___POR 0x0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5 (0x00032014) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS (0x0003000C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH__BASE_ADDR_HIGH___M 0x0000001F |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__SRC_FLUSH___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___S 16 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9 (0x00032024) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___M 0x00000001 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___M 0x0000001F |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___M 0x00000001 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__PARSER_INT___S 11 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___POR 0x000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_OVERFLOW___S 6 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___M 0x00004000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___M 0x00000004 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___M 0x00020000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT_STATUS___M 0x00000008 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___M 0x00000008 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___POR 0x00000080 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_DIRTY___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18 (0x00032048) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___M 0x00001000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK (0x00240050) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__DIRTY_BIT_SET___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW (0x00243000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___S 16 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_DIRTY (0x00030080) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW (0x00248000) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___S 2 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16 (0x00032040) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_HIGH_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___M 0x0000000F |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___S 16 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY (0x0024C000) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___M 0x00000800 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___S 18 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS (0x00032078) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID__BITS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___S 2 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_ADDRESS_VALID___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12 (0x00030050) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS__SELECT___M 0x00000007 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___M 0x00000020 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___M 0x00000004 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN1_SLP_TMR_INTR___S 14 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___M 0x00000004 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___M 0x00040000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___S 8 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___M 0x00000100 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7 (0x0003003C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI__CURRENT_DRRI___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET (0x002F0084) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET__CE_INTR_LINE_HOST_P___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__SIZE___POR 0x0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___S 2 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___POR 0x000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY__ENABLE___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8 (0x00030040) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS (0x00240030) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___M 0x00000010 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15 (0x0003203C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___M 0x00000002 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH (0x00240004) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__WRITE_ACCESS___S 17 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___S 6 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ECAHB_TIMEOUT___S 4 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___POR 0x0080 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___POR 0x0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___S 3 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___S 3 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW (0x00240000) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13 (0x00030054) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___S 15 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH (0x00240010) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___S 11 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ERR_RESP_CLEAR___S 2 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4 (0x00032010) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY___M 0x00000001 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___S 7 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_MAX_LEN_VIO___S 7 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW (0x00246000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_2_INTR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_WCSS_WAKEUP_IRQ_ACK___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___POR 0x000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___S 12 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__PARSER_INT___POR 0x000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___M 0x00000004 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23 (0x0003007C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___M 0x0000001F |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___M 0x00000040 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SMH_INT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__SW_SLP_TMR_INTR___S 16 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___S 12 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___POR 0x00 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___M 0x00000100 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__VALUE_REG_UPDATED_WITH_INVALID_ADDR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH__SPARE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX__SRC_WR_INDEX___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___POR 0x1 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1 (0x00240018) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19 (0x0003006C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX (0x0024003C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___M 0x0000000F |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___POR 0x0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_RF_XO_MUX_SEL___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___M 0x0000000F |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET___M 0x0FFFDDFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7 (0x0003201C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___M 0x00000004 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___S 3 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__DST_AXI_MAX_LEN___M 0x0000000C |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__MISC___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__COPY_COMPLETE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___POR 0x0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__CLOCK_GATE_DISABLE___S 1 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__DIRTY_BIT_SET_CLEAR___M 0x00000001 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___S 1 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB__STATUS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_SR_XO_SETTLE_TIMEOUT___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___S 5 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB__STATUS___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_MISC_P___S 7 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___S 3 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR___RWC QCSR_REG_WO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__PMM_SR_XO_SETTLE_TIMEOUT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___M 0x00000FFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___S 16 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___M 0x00000002 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16 (0x00030060) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS (0x00030144) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___POR 0x0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SR_PLL_REF_MUX_SEL___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17 (0x00032044) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___M 0x000003FF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___M 0x00020000 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB__STATUS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__ENABLE_APSS_FULL_ACCESS___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___M 0x00000002 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE__START_OFFSET___M 0xFFFF0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___S 1 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__CE_INTR_TIMEOUT_P___S 8 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___M 0x00000001 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___POR 0x0000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS___M 0x000FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ECAHB_TIMEOUT___S 4 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1___M 0x000FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__FORCE_WAKE_ENABLE___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__INVALID_ADDR___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___M 0x00000007 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___S 6 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_HIGH_WATERMARK___S 1 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW (0x00242000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN2_HW2SW_GRANT___S 7 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___S 4 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE (0x00030010) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__FORCE_WAKE_CLEAR___M 0x00000002 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8 (0x00032020) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___M 0x00000FFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M 0x00080000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__BMH_INT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL__SOFT_RESET___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___S 6 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0 (0x00030020) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___S 5 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___M 0x00FFF000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX__DST_WR_INDEX___POR 0x0000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__ILL_REG___M 0x01000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WLAN2_SLP_TMR_INTR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11 (0x0003004C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__PMH_INT___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__INVALID_BB_1_INTR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___POR 0x0000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB (0x0003206C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__PMM_WCSS_WAKEUP_IRQ_ACK___M 0x00000100 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__DIRTY_BIT_SET_ENABLE___M 0x00000001 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE (0x00240014) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__STATE___M 0x00000007 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11 (0x0003202C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI (0x00240048) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW__BASE_ADDR_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___S 3 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW (0x00249000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__DST_RING_LOW_WATERMARK___S 4 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___S 8 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_MISC_IS__AXI_TIMEOUT_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__ERR_RESP_ENABLE___M 0x00000004 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___S 2 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___M 0x00000001 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_HIGH_WATERMARK___S 1 |
| #define ADRASTEA_A_WCSS_SR_APSS_DIRTY___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS__WCSS_CORE_WAKE_SLEEP_STATE___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___S 16 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_TESTBUS___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_INVALID_ADDR_ACCESS__READ_ACCESS___M 0x00010000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_HIGH_WATERMARK___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_CLEAR__CE_INTR_LINE_HOST_P___POR 0x000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL (0x00030000) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI (0x00240044) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___M 0x00FFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___M 0x000003FF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD (0x00240020) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_LOW_WATERMARK___M 0x00000004 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__NOC_WCMN_INTR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_SECURE_WRAPPER_CE_WRAPPER_INTERRUPT_SUMMARY__HOST___S 12 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_LSB___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOWREG_STATUS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB__STATUS___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES (0x002F1000) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_MISC_IS__AXI_TIMEOUT_ERR___M 0x00000400 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9 (0x00030044) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6 (0x00032018) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21 (0x00032054) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH__BASE_ADDR_HIGH___M 0x0000001F |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___S 12 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__HALT___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW (0x00247000) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18 (0x00030068) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN1_HW2SW_GRANT___M 0x00000040 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_LOW_WATERMARK___M 0x00000010 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__INVALID_ADDR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___S 2 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE (0x00240008) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_CONTROL___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_HIGH_WATERMARK___S 3 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__WLAN1_HW2SW_GRANT___M 0x00000040 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LMH_INT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___M 0x00000080 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1 (0x00030024) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2 (0x0024001C) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES__CE_INTR_LINE_HOST_P___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0__ADDRESS_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES_SET___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_STROBE_INTERRUPT___M 0x00000002 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__VALUE_REG_UPDATED_WITH_INVALID_ADDR___M 0x00000020 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__MCIM_INT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__FORCE_WAKE___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_MSB___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21 (0x00030074) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_DIRTY__BITS___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__AXI_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__WLAN2_HW2SW_GRANT___S 7 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12__VALUE_REGISTER___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_LEN_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_WCSSAON_SR_MSB (0x00032074) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE__FORCE_WAKE_ENABLE___M 0x00000001 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD__DST_FLUSH___S 2 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_LOW_WATERMARK___S 2 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE__START_OFFSET___M 0xFFFF0000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10 (0x00030048) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_OVERFLOW___S 5 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI__CURRENT_SRRI___M 0x0000FFFF |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4__ADDRESS_REGISTER___M 0x003FFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__SRC_RING_HIGH_WATERMARK___M 0x00000002 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__ERR_RESP___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__COPY_COMPLETE___M 0x00000001 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20__VALUE_REGISTER___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW__BASE_ADDR_LOW___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_TIMEOUT_ERR___S 10 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW__BASE_ADDR_LOW___M 0xFFFFFFFF |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___S 3 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1___RWC QCSR_REG_RO |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__ECAHB_TIMEOUT___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SW_SCRATCH___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_BUS_ERR___S 9 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3__ADDRESS_REGISTER___POR 0x000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_LOW_WATERMARK___S 2 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL2__SRC_AXI_MAX_LEN___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_PMM_SR_LSB (0x00032068) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__WFSS_DBG_INTR___S 17 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_CLEAR__PMM_SR_XO_SETTLE_TIMEOUT___M 0x00000200 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH___S 0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_ENABLE__WLAN1_HW2SW_GRANT___M 0x00000040 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___M 0x00000200 |
| #define ADRASTEA_A_WCSS_SR_APSS_COMMIT_REPLAY (0x00030004) |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW___RWC QCSR_REG_RW |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21___S 0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_MISC_IS__AXI_BUS_ERR___POR 0x0 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_3_A_WCMN_QDSP_ERROR_INTR_ENABLES_SET__LCMH_WCI2_INTERRUPT___M 0x00000004 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__DST_RING_LOW_WATERMARK___POR 0x0 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10 (0x00032028) |
| #define ADRASTEA_A_WCSS_SR_APSS_SR_INTERRUPT_STATUS__INVALID_ADDR___M 0x00000008 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3 (0x0003200C) |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16__VALUE_REGISTER___POR 0x00000000 |
| #define ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE__SRC_RING_HIGH_WATERMARK___S 1 |
| #define ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12__ADDRESS_REGISTER___S 0 |
| |
| |
| /* End auto-generated headers from register parser */ |
| |
| #define A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW 0x0024C004 |
| #define A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH 0x0024C008 |
| |
| #define MISSING 0 |
| #define MISSING_FOR_ADRASTEA MISSING |
| #define ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS 0 |
| #define ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS 0x45000 |
| #define ADRASTEA_RTC_SOC_REG_BASE_ADDRESS 0x113000 |
| #define ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS 0x85000 |
| #define ADRASTEA_SI_REG_BASE_ADDRESS 0x84000 |
| #define ADRASTEA_SOC_CORE_REG_BASE_ADDRESS 0x113000 |
| #define ADRASTEA_CE_WRAPPER_REG_CSR_BASE_ADDRESS 0xC000 |
| #define ADRASTEA_MAC_WIFICMN_REG_BASE_ADDRESS MISSING |
| |
| /* Base Addresses */ |
| #define ADRASTEA_RTC_SOC_BASE_ADDRESS 0x00000000 |
| #define ADRASTEA_RTC_WMAC_BASE_ADDRESS 0x00000000 |
| #define ADRASTEA_MAC_COEX_BASE_ADDRESS 0x0000f000 |
| #define ADRASTEA_BT_COEX_BASE_ADDRESS 0x00002000 |
| #define ADRASTEA_SOC_PCIE_BASE_ADDRESS 0x00130000 |
| #define ADRASTEA_SOC_CORE_BASE_ADDRESS 0x00000000 |
| #define ADRASTEA_WLAN_UART_BASE_ADDRESS 0x00111000 |
| #define ADRASTEA_WLAN_SI_BASE_ADDRESS 0x00010000 |
| #define ADRASTEA_WLAN_GPIO_BASE_ADDRESS 0x00000000 |
| #define ADRASTEA_WLAN_ANALOG_INTF_BASE_ADDRESS 0x00000000 |
| #define ADRASTEA_WLAN_MAC_BASE_ADDRESS 0x00000000 |
| #define ADRASTEA_EFUSE_BASE_ADDRESS 0x00024000 |
| #define ADRASTEA_FPGA_REG_BASE_ADDRESS 0x00039000 |
| #define ADRASTEA_WLAN_UART2_BASE_ADDRESS 0x00054c00 |
| |
| #define ADRASTEA_CE_WRAPPER_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY |
| #define ADRASTEA_CE0_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW |
| #define ADRASTEA_CE1_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE1_SR_BA_LOW |
| #define ADRASTEA_CE2_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE2_SR_BA_LOW |
| #define ADRASTEA_CE3_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE3_SR_BA_LOW |
| #define ADRASTEA_CE4_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE4_SR_BA_LOW |
| #define ADRASTEA_CE5_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE5_SR_BA_LOW |
| #define ADRASTEA_CE6_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE6_SR_BA_LOW |
| #define ADRASTEA_CE7_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE7_SR_BA_LOW |
| #define ADRASTEA_CE8_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE8_SR_BA_LOW |
| #define ADRASTEA_CE9_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE9_SR_BA_LOW |
| #define ADRASTEA_CE10_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE10_SR_BA_LOW |
| #define ADRASTEA_CE11_BASE_ADDRESS \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE11_SR_BA_LOW |
| |
| #define ADRASTEA_A_SOC_PCIE_SOC_PCIE_REG MISSING |
| #define ADRASTEA_DBI_BASE_ADDRESS MISSING |
| #define ADRASTEA_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS MISSING |
| #define ADRASTEA_WIFICMN_BASE_ADDRESS MISSING |
| #define ADRASTEA_BOARD_DATA_SZ MISSING |
| #define ADRASTEA_BOARD_EXT_DATA_SZ MISSING |
| #define ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START MISSING |
| #define ADRASTEA_A_SOC_CORE_SCRATCH_0_ADDRESS MISSING |
| #define ADRASTEA_A_SOC_CORE_SPARE_0_REGISTER MISSING |
| #define ADRASTEA_PCIE_INTR_FIRMWARE_ROUTE_MASK MISSING |
| #define ADRASTEA_SCRATCH_3_ADDRESS MISSING |
| #define ADRASTEA_TARG_DRAM_START 0x00400000 |
| #define ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET 0x000000c0 |
| #define ADRASTEA_SOC_RESET_CONTROL_OFFSET \ |
| (0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS) |
| #define ADRASTEA_SOC_CLOCK_CONTROL_OFFSET \ |
| (0x00000028 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS) |
| #define ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 |
| #define ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK 0x00000001 |
| #define ADRASTEA_WLAN_GPIO_PIN0_ADDRESS \ |
| (0x50 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS) |
| #define ADRASTEA_WLAN_GPIO_PIN1_ADDRESS \ |
| (0x54 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS) |
| #define ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 |
| #define ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 |
| #define ADRASTEA_SOC_CPU_CLOCK_OFFSET 0x00000020 |
| #define ADRASTEA_SOC_LPO_CAL_OFFSET \ |
| (0xe0 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS) |
| #define ADRASTEA_WLAN_GPIO_PIN10_ADDRESS \ |
| (0x78 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS) |
| #define ADRASTEA_WLAN_GPIO_PIN11_ADDRESS \ |
| (0x7c + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS) |
| #define ADRASTEA_WLAN_GPIO_PIN12_ADDRESS \ |
| (0x80 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS) |
| #define ADRASTEA_WLAN_GPIO_PIN13_ADDRESS \ |
| (0x84 + ADRASTEA_GPIO_ATHR_WLAN_REG_BASE_ADDRESS) |
| #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB 0 |
| #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 |
| #define ADRASTEA_SOC_LPO_CAL_ENABLE_LSB 20 |
| #define ADRASTEA_SOC_LPO_CAL_ENABLE_MASK 0x00100000 |
| |
| #define ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 |
| #define ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 |
| #define ADRASTEA_WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000002 |
| #define ADRASTEA_WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000001 |
| #define ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_LSB 18 |
| #define ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 |
| #define ADRASTEA_SI_CONFIG_I2C_LSB 16 |
| #define ADRASTEA_SI_CONFIG_I2C_MASK 0x00010000 |
| #define ADRASTEA_SI_CONFIG_POS_SAMPLE_LSB 7 |
| #define ADRASTEA_SI_CONFIG_POS_SAMPLE_MASK 0x00000080 |
| #define ADRASTEA_SI_CONFIG_INACTIVE_CLK_LSB 4 |
| #define ADRASTEA_SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 |
| #define ADRASTEA_SI_CONFIG_INACTIVE_DATA_LSB 5 |
| #define ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 |
| #define ADRASTEA_SI_CONFIG_DIVIDER_LSB 0 |
| #define ADRASTEA_SI_CONFIG_DIVIDER_MASK 0x0000000f |
| #define ADRASTEA_SI_CONFIG_OFFSET (0x00000000 + ADRASTEA_SI_REG_BASE_ADDRESS) |
| #define ADRASTEA_SI_TX_DATA0_OFFSET (0x00000008 + ADRASTEA_SI_REG_BASE_ADDRESS) |
| #define ADRASTEA_SI_TX_DATA1_OFFSET (0x0000000c + ADRASTEA_SI_REG_BASE_ADDRESS) |
| #define ADRASTEA_SI_RX_DATA0_OFFSET (0x00000010 + ADRASTEA_SI_REG_BASE_ADDRESS) |
| #define ADRASTEA_SI_RX_DATA1_OFFSET (0x00000014 + ADRASTEA_SI_REG_BASE_ADDRESS) |
| #define ADRASTEA_SI_CS_OFFSET (0x00000004 + ADRASTEA_SI_REG_BASE_ADDRESS) |
| #define ADRASTEA_SI_CS_DONE_ERR_MASK 0x00000400 |
| #define ADRASTEA_SI_CS_DONE_INT_MASK 0x00000200 |
| #define ADRASTEA_SI_CS_START_LSB 8 |
| #define ADRASTEA_SI_CS_START_MASK 0x00000100 |
| #define ADRASTEA_SI_CS_RX_CNT_LSB 4 |
| #define ADRASTEA_SI_CS_RX_CNT_MASK 0x000000f0 |
| #define ADRASTEA_SI_CS_TX_CNT_LSB 0 |
| #define ADRASTEA_SI_CS_TX_CNT_MASK 0x0000000f |
| #define ADRASTEA_CE_COUNT 12 |
| #define ADRASTEA_SR_WR_INDEX_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WR_INDEX \ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| #define ADRASTEA_DST_WATERMARK_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK \ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| #define ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_LSB 14 |
| #define ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_MASK 0x00004000 |
| #define ADRASTEA_RX_MPDU_START_0_SEQ_NUM_LSB 16 |
| #define ADRASTEA_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000 |
| #define ADRASTEA_RX_MPDU_START_2_PN_47_32_LSB 0 |
| #define ADRASTEA_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff |
| #define ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB 16 |
| #define ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK 0xffff0000 |
| #define ADRASTEA_RX_MSDU_END_4_LAST_MSDU_LSB 15 |
| #define ADRASTEA_RX_MSDU_END_4_LAST_MSDU_MASK 0x00008000 |
| #define ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_LSB 2 |
| #define ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_MASK 0x00000004 |
| #define ADRASTEA_RX_ATTENTION_0_FRAGMENT_LSB 13 |
| #define ADRASTEA_RX_ATTENTION_0_FRAGMENT_MASK 0x00002000 |
| #define ADRASTEA_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK 0x08000000 |
| #define ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB 16 |
| #define ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK 0x00ff0000 |
| #define ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_LSB 0 |
| #define ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_MASK 0x00003fff |
| |
| #define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 |
| #define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_LSB 8 |
| #define ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 |
| #define ADRASTEA_RX_MPDU_START_0_ENCRYPTED_LSB 13 |
| #define ADRASTEA_RX_MPDU_START_0_ENCRYPTED_MASK 0x00002000 |
| #define ADRASTEA_RX_ATTENTION_0_MORE_DATA_MASK 0x00000400 |
| #define ADRASTEA_RX_ATTENTION_0_MSDU_DONE_MASK 0x80000000 |
| #define ADRASTEA_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 |
| |
| #define ADRASTEA_DST_WR_INDEX_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WR_INDEX\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_SRC_WATERMARK_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_SRC_WATERMARK_LOW_MASK 0xffff0000 |
| #define ADRASTEA_SRC_WATERMARK_HIGH_MASK 0x0000ffff |
| #define ADRASTEA_DST_WATERMARK_LOW_MASK 0xffff0000 |
| #define ADRASTEA_DST_WATERMARK_HIGH_MASK 0x0000ffff |
| |
| #define ADRASTEA_CURRENT_SRRI_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_SRRI\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_CURRENT_DRRI_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CURRENT_DRRI\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK 0x00000002 |
| #define ADRASTEA_HOST_IS_SRC_RING_LOW_WATERMARK_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__SRC_RING_LOW_WATERMARK___M |
| |
| #define ADRASTEA_HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_HIGH_WATERMARK___M |
| |
| #define ADRASTEA_HOST_IS_DST_RING_LOW_WATERMARK_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__DST_RING_LOW_WATERMARK___M |
| |
| #define ADRASTEA_HOST_IS_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS \ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_MISC_IS_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS \ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_HOST_IS_COPY_COMPLETE_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IS__COPY_COMPLETE___M |
| |
| #define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET \ |
| (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY\ |
| - ADRASTEA_CE_WRAPPER_BASE_ADDRESS) |
| |
| /* |
| * Base address where the CE source and destination ring read |
| * indices are written to be viewed by host. |
| */ |
| |
| #define ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW \ |
| (A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW\ |
| - ADRASTEA_CE_WRAPPER_BASE_ADDRESS) |
| |
| #define ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH \ |
| (A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH - ADRASTEA_CE_WRAPPER_BASE_ADDRESS) |
| |
| #define ADRASTEA_HOST_IE_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_HOST_IE_COPY_COMPLETE_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_HOST_IE__COPY_COMPLETE___M |
| |
| #define ADRASTEA_SR_BA_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_LOW\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_SR_BA_HIGH_OFFSET \ |
| (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_BA_HIGH \ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_SR_SIZE_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SR_SIZE \ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_CE_CTRL1_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1 \ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_CE_CTRL1_DMAX_LENGTH_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___M |
| |
| #define ADRASTEA_DR_BA_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_LOW\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_DR_BA_HIGH_OFFSET \ |
| (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_BA_HIGH\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_DR_SIZE_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DR_SIZE\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_CE_CMD_REGISTER_OFFSET (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CMD\ |
| - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_MISC_IE_OFFSET \ |
| (ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IE - ADRASTEA_CE0_BASE_ADDRESS) |
| |
| #define ADRASTEA_MISC_IS_AXI_ERR_MASK 0x00000100 |
| |
| #define ADRASTEA_MISC_IS_DST_ADDR_ERR_MASK 0x00000200 |
| |
| #define ADRASTEA_MISC_IS_AXI_TIMEOUT_ERR \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__AXI_TIMEOUT_ERR___M |
| |
| #define ADRASTEA_MISC_IS_SRC_LEN_ERR_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_LEN_ERR___M |
| |
| #define ADRASTEA_MISC_IS_DST_MAX_LEN_VIO_MASK\ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_MAX_LEN_VIO___M |
| |
| #define ADRASTEA_MISC_IS_DST_RING_OVERFLOW_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__DST_RING_OVERFLOW___M |
| |
| #define ADRASTEA_MISC_IS_SRC_RING_OVERFLOW_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_MISC_IS__SRC_RING_OVERFLOW___M |
| |
| #define ADRASTEA_SRC_WATERMARK_LOW_LSB \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_LOW_WATER_MARK_THRESOLD___S |
| |
| #define ADRASTEA_SRC_WATERMARK_HIGH_LSB \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_SRC_WATERMARK__SR_HIGH_WATER_MARK_THRESHOLD___S |
| |
| #define ADRASTEA_DST_WATERMARK_LOW_LSB \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_LOW_WATER_MARK_THRESHOLD___S |
| |
| #define ADRASTEA_DST_WATERMARK_HIGH_LSB \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_DST_WATERMARK__DR_HIGH_WATER_MARK_THRESHOLD___S |
| |
| #define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___M |
| |
| #define ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY__HOST___S |
| |
| #define ADRASTEA_CE_CTRL1_DMAX_LENGTH_LSB \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DEST_MAX_LENGTH___S |
| |
| #define ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___M |
| |
| #define ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___M |
| |
| #define ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__SRC_RING_BYTE_SWAP_EN___S |
| |
| #define ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__DST_RING_BYTE_SWAP_EN___S |
| |
| #define ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x0000004 |
| #define ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2 |
| #define ADRASTEA_SOC_GLOBAL_RESET_ADDRESS \ |
| (0x0008 + ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS) |
| #define ADRASTEA_RTC_STATE_ADDRESS \ |
| (0x0000 + ADRASTEA_PCIE_LOCAL_REG_BASE_ADDRESS) |
| #define ADRASTEA_RTC_STATE_COLD_RESET_MASK 0x400 |
| |
| #define ADRASTEA_PCIE_SOC_WAKE_RESET 0x00000000 |
| #define ADRASTEA_PCIE_SOC_WAKE_ADDRESS (ADRASTEA_A_WCSS_SR_APSS_FORCE_WAKE) |
| #define ADRASTEA_PCIE_SOC_WAKE_V_MASK 0x00000001 |
| |
| #define ADRASTEA_RTC_STATE_V_MASK 0x00000007 |
| #define ADRASTEA_RTC_STATE_V_LSB 0 |
| #define ADRASTEA_RTC_STATE_V_ON 5 |
| #define ADRASTEA_PCIE_LOCAL_BASE_ADDRESS 0x0 |
| #define ADRASTEA_FW_IND_EVENT_PENDING 1 |
| #define ADRASTEA_FW_IND_INITIALIZED 2 |
| #define ADRASTEA_FW_IND_HELPER 4 |
| |
| #define ADRASTEA_PCIE_INTR_FIRMWARE_MASK 0x00000000 |
| #define ADRASTEA_PCIE_INTR_CE0_MASK 0x00000100 |
| #define ADRASTEA_PCIE_INTR_CE_MASK_ALL 0x00001ffe |
| |
| #define ADRASTEA_CPU_INTR_ADDRESS 0xffffffff |
| #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS 0xffffffff |
| #define ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0xffffffff |
| #define ADRASTEA_SOC_RESET_CONTROL_ADDRESS \ |
| (0x00000000 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS) |
| #define ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK 0x0100 |
| #define ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 |
| #define ADRASTEA_CORE_CTRL_ADDRESS (0x0000 + ADRASTEA_SOC_CORE_REG_BASE_ADDRESS) |
| #define ADRASTEA_CORE_CTRL_CPU_INTR_MASK 0x00002000 |
| #define ADRASTEA_LOCAL_SCRATCH_OFFSET 0x00000018 |
| #define ADRASTEA_CLOCK_GPIO_OFFSET 0xffffffff |
| #define ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 |
| #define ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 |
| #define ADRASTEA_SOC_CHIP_ID_ADDRESS 0x000000f0 |
| #define ADRASTEA_SOC_CHIP_ID_VERSION_MASK 0xfffc0000 |
| #define ADRASTEA_SOC_CHIP_ID_VERSION_LSB 18 |
| #define ADRASTEA_SOC_CHIP_ID_REVISION_MASK 0x00000f00 |
| #define ADRASTEA_SOC_CHIP_ID_REVISION_LSB 8 |
| #define ADRASTEA_SOC_POWER_REG_OFFSET 0x0000010c |
| |
| /* Copy Engine Debug */ |
| #define ADRASTEA_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c |
| #define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3 |
| #define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_LSB 0 |
| #define ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f |
| #define ADRASTEA_WLAN_DEBUG_CONTROL_OFFSET 0x00000108 |
| #define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MSB 0 |
| #define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_LSB 0 |
| #define ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001 |
| #define ADRASTEA_WLAN_DEBUG_OUT_OFFSET 0x00000110 |
| #define ADRASTEA_WLAN_DEBUG_OUT_DATA_MSB 19 |
| #define ADRASTEA_WLAN_DEBUG_OUT_DATA_LSB 0 |
| #define ADRASTEA_WLAN_DEBUG_OUT_DATA_MASK 0x000fffff |
| #define ADRASTEA_AMBA_DEBUG_BUS_OFFSET 0x0000011c |
| #define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB 13 |
| #define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB 8 |
| #define ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK 0x00003f00 |
| #define ADRASTEA_AMBA_DEBUG_BUS_SEL_MSB 4 |
| #define ADRASTEA_AMBA_DEBUG_BUS_SEL_LSB 0 |
| #define ADRASTEA_AMBA_DEBUG_BUS_SEL_MASK 0x0000001f |
| #define ADRASTEA_CE_WRAPPER_DEBUG_OFFSET 0x0008 |
| #define ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB 4 |
| #define ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB 0 |
| #define ADRASTEA_CE_WRAPPER_DEBUG_SEL_MASK 0x0000001f |
| #define ADRASTEA_CE_DEBUG_OFFSET 0x0054 |
| #define ADRASTEA_CE_DEBUG_SEL_MSB 5 |
| #define ADRASTEA_CE_DEBUG_SEL_LSB 0 |
| #define ADRASTEA_CE_DEBUG_SEL_MASK 0x0000003f |
| /* End */ |
| |
| /* PLL start */ |
| #define ADRASTEA_EFUSE_OFFSET 0x0000032c |
| #define ADRASTEA_EFUSE_XTAL_SEL_MSB 10 |
| #define ADRASTEA_EFUSE_XTAL_SEL_LSB 8 |
| #define ADRASTEA_EFUSE_XTAL_SEL_MASK 0x00000700 |
| #define ADRASTEA_BB_PLL_CONFIG_OFFSET 0x000002f4 |
| #define ADRASTEA_BB_PLL_CONFIG_OUTDIV_MSB 20 |
| #define ADRASTEA_BB_PLL_CONFIG_OUTDIV_LSB 18 |
| #define ADRASTEA_BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000 |
| #define ADRASTEA_BB_PLL_CONFIG_FRAC_MSB 17 |
| #define ADRASTEA_BB_PLL_CONFIG_FRAC_LSB 0 |
| #define ADRASTEA_BB_PLL_CONFIG_FRAC_MASK 0x0003ffff |
| #define ADRASTEA_WLAN_PLL_SETTLE_TIME_MSB 10 |
| #define ADRASTEA_WLAN_PLL_SETTLE_TIME_LSB 0 |
| #define ADRASTEA_WLAN_PLL_SETTLE_TIME_MASK 0x000007ff |
| #define ADRASTEA_WLAN_PLL_SETTLE_OFFSET 0x0018 |
| #define ADRASTEA_WLAN_PLL_SETTLE_SW_MASK 0x000007ff |
| #define ADRASTEA_WLAN_PLL_SETTLE_RSTMASK 0xffffffff |
| #define ADRASTEA_WLAN_PLL_SETTLE_RESET 0x00000400 |
| #define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MSB 18 |
| #define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_LSB 18 |
| #define ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000 |
| #define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MSB 16 |
| #define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_LSB 16 |
| #define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000 |
| #define ADRASTEA_WLAN_PLL_CONTROL_BYPASS_RESET 0x1 |
| #define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MSB 15 |
| #define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_LSB 14 |
| #define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MASK 0x0000c000 |
| #define ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_RESET 0x0 |
| #define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MSB 13 |
| #define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_LSB 10 |
| #define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00 |
| #define ADRASTEA_WLAN_PLL_CONTROL_REFDIV_RESET 0x0 |
| #define ADRASTEA_WLAN_PLL_CONTROL_DIV_MSB 9 |
| #define ADRASTEA_WLAN_PLL_CONTROL_DIV_LSB 0 |
| #define ADRASTEA_WLAN_PLL_CONTROL_DIV_MASK 0x000003ff |
| #define ADRASTEA_WLAN_PLL_CONTROL_DIV_RESET 0x11 |
| #define ADRASTEA_WLAN_PLL_CONTROL_OFFSET 0x0014 |
| #define ADRASTEA_WLAN_PLL_CONTROL_SW_MASK 0x001fffff |
| #define ADRASTEA_WLAN_PLL_CONTROL_RSTMASK 0xffffffff |
| #define ADRASTEA_WLAN_PLL_CONTROL_RESET 0x00010011 |
| #define ADRASTEA_SOC_CORE_CLK_CTRL_OFFSET 0x00000114 |
| #define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MSB 2 |
| #define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_LSB 0 |
| #define ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007 |
| #define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MSB 5 |
| #define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_LSB 5 |
| #define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020 |
| #define ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_RESET 0x0 |
| #define ADRASTEA_RTC_SYNC_STATUS_OFFSET 0x0244 |
| #define ADRASTEA_SOC_CPU_CLOCK_OFFSET 0x00000020 |
| #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MSB 1 |
| #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB 0 |
| #define ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 |
| /* PLL end */ |
| |
| #define ADRASTEA_PCIE_INTR_CE_MASK(n) (ADRASTEA_PCIE_INTR_CE0_MASK << (n)) |
| #define ADRASTEA_DRAM_BASE_ADDRESS ADRASTEA_TARG_DRAM_START |
| #define ADRASTEA_FW_INDICATOR_ADDRESS \ |
| (ADRASTEA_WIFICMN_BASE_ADDRESS + ADRASTEA_SCRATCH_3_ADDRESS) |
| #define ADRASTEA_SYSTEM_SLEEP_OFFSET ADRASTEA_SOC_SYSTEM_SLEEP_OFFSET |
| #define ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET (0x002c + ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS) |
| #define ADRASTEA_WLAN_RESET_CONTROL_OFFSET (0x0000 + ADRASTEA_WIFI_RTC_REG_BASE_ADDRESS) |
| #define ADRASTEA_CLOCK_CONTROL_OFFSET ADRASTEA_SOC_CLOCK_CONTROL_OFFSET |
| #define ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK \ |
| ADRASTEA_SOC_CLOCK_CONTROL_SI0_CLK_MASK |
| #define ADRASTEA_RESET_CONTROL_MBOX_RST_MASK 0x00000004 |
| #define ADRASTEA_RESET_CONTROL_SI0_RST_MASK \ |
| ADRASTEA_SOC_RESET_CONTROL_SI0_RST_MASK |
| #define ADRASTEA_GPIO_BASE_ADDRESS ADRASTEA_WLAN_GPIO_BASE_ADDRESS |
| #define ADRASTEA_GPIO_PIN0_OFFSET ADRASTEA_WLAN_GPIO_PIN0_ADDRESS |
| #define ADRASTEA_GPIO_PIN1_OFFSET ADRASTEA_WLAN_GPIO_PIN1_ADDRESS |
| #define ADRASTEA_GPIO_PIN0_CONFIG_MASK ADRASTEA_WLAN_GPIO_PIN0_CONFIG_MASK |
| #define ADRASTEA_GPIO_PIN1_CONFIG_MASK ADRASTEA_WLAN_GPIO_PIN1_CONFIG_MASK |
| #define ADRASTEA_SI_BASE_ADDRESS 0x00000000 |
| #define ADRASTEA_CPU_CLOCK_OFFSET (0x20 + ADRASTEA_RTC_SOC_REG_BASE_ADDRESS) |
| #define ADRASTEA_LPO_CAL_OFFSET ADRASTEA_SOC_LPO_CAL_OFFSET |
| #define ADRASTEA_GPIO_PIN10_OFFSET ADRASTEA_WLAN_GPIO_PIN10_ADDRESS |
| #define ADRASTEA_GPIO_PIN11_OFFSET ADRASTEA_WLAN_GPIO_PIN11_ADDRESS |
| #define ADRASTEA_GPIO_PIN12_OFFSET ADRASTEA_WLAN_GPIO_PIN12_ADDRESS |
| #define ADRASTEA_GPIO_PIN13_OFFSET ADRASTEA_WLAN_GPIO_PIN13_ADDRESS |
| #define ADRASTEA_CPU_CLOCK_STANDARD_LSB 0 |
| #define ADRASTEA_CPU_CLOCK_STANDARD_MASK 0x1 |
| #define ADRASTEA_LPO_CAL_ENABLE_LSB ADRASTEA_SOC_LPO_CAL_ENABLE_LSB |
| #define ADRASTEA_LPO_CAL_ENABLE_MASK ADRASTEA_SOC_LPO_CAL_ENABLE_MASK |
| #define ADRASTEA_ANALOG_INTF_BASE_ADDRESS ADRASTEA_WLAN_ANALOG_INTF_BASE_ADDRESS |
| #define ADRASTEA_MBOX_BASE_ADDRESS 0x00008000 |
| #define ADRASTEA_INT_STATUS_ENABLE_ERROR_LSB MISSING |
| #define ADRASTEA_INT_STATUS_ENABLE_ERROR_MASK MISSING |
| #define ADRASTEA_INT_STATUS_ENABLE_CPU_LSB MISSING |
| #define ADRASTEA_INT_STATUS_ENABLE_CPU_MASK MISSING |
| #define ADRASTEA_INT_STATUS_ENABLE_COUNTER_LSB MISSING |
| #define ADRASTEA_INT_STATUS_ENABLE_COUNTER_MASK MISSING |
| #define ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING |
| #define ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING |
| #define ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING |
| #define ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING |
| #define ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING |
| #define ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING |
| #define ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING |
| #define ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING |
| #define ADRASTEA_INT_STATUS_ENABLE_ADDRESS MISSING |
| #define ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_LSB MISSING |
| #define ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_MASK MISSING |
| #define ADRASTEA_HOST_INT_STATUS_ADDRESS MISSING |
| #define ADRASTEA_CPU_INT_STATUS_ADDRESS MISSING |
| #define ADRASTEA_ERROR_INT_STATUS_ADDRESS MISSING |
| #define ADRASTEA_ERROR_INT_STATUS_WAKEUP_MASK MISSING |
| #define ADRASTEA_ERROR_INT_STATUS_WAKEUP_LSB MISSING |
| #define ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING |
| #define ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING |
| #define ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING |
| #define ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING |
| #define ADRASTEA_COUNT_DEC_ADDRESS MISSING |
| #define ADRASTEA_HOST_INT_STATUS_CPU_MASK MISSING |
| #define ADRASTEA_HOST_INT_STATUS_CPU_LSB MISSING |
| #define ADRASTEA_HOST_INT_STATUS_ERROR_MASK MISSING |
| #define ADRASTEA_HOST_INT_STATUS_ERROR_LSB MISSING |
| #define ADRASTEA_HOST_INT_STATUS_COUNTER_MASK MISSING |
| #define ADRASTEA_HOST_INT_STATUS_COUNTER_LSB MISSING |
| #define ADRASTEA_RX_LOOKAHEAD_VALID_ADDRESS MISSING |
| #define ADRASTEA_WINDOW_DATA_ADDRESS MISSING |
| #define ADRASTEA_WINDOW_READ_ADDR_ADDRESS MISSING |
| #define ADRASTEA_WINDOW_WRITE_ADDR_ADDRESS MISSING |
| |
| /* Shadow Registers - Start */ |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE0 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_1 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE1 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_2 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE2 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_3 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE3 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_4 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE4 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_5 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE5 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_6 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE6 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_7 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE7 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_8 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE8 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_9 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE9 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_10 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE10 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_11 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE11 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_12 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE12 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_13 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE13 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_14 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE14 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_15 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE15 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_16 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE16 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_17 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE17 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_18 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE18 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_19 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE19 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_20 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE20 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_21 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE21 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_22 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE22 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_23 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_VALUE23 |
| |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_0 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS0 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_1 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS1 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_2 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS2 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_3 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS3 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_4 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS4 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_5 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS5 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_6 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS6 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_7 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS7 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_8 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS8 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_9 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS9 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_10 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS10 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_11 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS11 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_12 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS12 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_13 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS13 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_14 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS14 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_15 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS15 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_16 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS16 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_17 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS17 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_18 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS18 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_19 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS19 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_20 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS20 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_21 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS21 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_22 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS22 |
| #define ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23 \ |
| ADRASTEA_A_WCSS_SR_APSS_SHADOW_ADDRESS23 |
| |
| /* Q6 iHelium emulation registers */ |
| #define ADRASTEA_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 0x00113018 |
| #define ADRASTEA_A_SOC_CORE_SPARE_1_REGISTER 0x00113184 |
| #define ADRASTEA_A_SOC_CORE_PCIE_INTR_CLR_GRP1 0x00113020 |
| #define ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 0x00113010 |
| #define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_0 0x00130040 |
| #define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_1 0x00130044 |
| |
| #define ADRASTEA_HOST_ENABLE_REGISTER 0x00188000 |
| #define ADRASTEA_Q6_ENABLE_REGISTER_0 0x00188004 |
| #define ADRASTEA_Q6_ENABLE_REGISTER_1 0x00188008 |
| #define ADRASTEA_HOST_CAUSE_REGISTER 0x0018800c |
| #define ADRASTEA_Q6_CAUSE_REGISTER_0 0x00188010 |
| #define ADRASTEA_Q6_CAUSE_REGISTER_1 0x00188014 |
| #define ADRASTEA_HOST_CLEAR_REGISTER 0x00188018 |
| #define ADRASTEA_Q6_CLEAR_REGISTER_0 0x0018801c |
| #define ADRASTEA_Q6_CLEAR_REGISTER_1 0x00188020 |
| |
| #define ADRASTEA_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA 0x08 |
| #define ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_2 0x0013005C |
| #define ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK 0x0 |
| /* end: Q6 iHelium emulation registers */ |
| |
| #define ADRASTEA_BYPASS_QMI_TEMP_REGISTER 0x00032064 |
| |
| struct targetdef_s adrastea_targetdef = { |
| .d_RTC_SOC_BASE_ADDRESS = ADRASTEA_RTC_SOC_BASE_ADDRESS, |
| .d_RTC_WMAC_BASE_ADDRESS = ADRASTEA_RTC_WMAC_BASE_ADDRESS, |
| .d_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET, |
| .d_WLAN_SYSTEM_SLEEP_OFFSET = ADRASTEA_WLAN_SYSTEM_SLEEP_OFFSET, |
| .d_WLAN_SYSTEM_SLEEP_DISABLE_LSB = |
| ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_LSB, |
| .d_WLAN_SYSTEM_SLEEP_DISABLE_MASK = |
| ADRASTEA_WLAN_SYSTEM_SLEEP_DISABLE_MASK, |
| .d_CLOCK_CONTROL_OFFSET = ADRASTEA_CLOCK_CONTROL_OFFSET, |
| .d_CLOCK_CONTROL_SI0_CLK_MASK = ADRASTEA_CLOCK_CONTROL_SI0_CLK_MASK, |
| .d_RESET_CONTROL_OFFSET = ADRASTEA_SOC_RESET_CONTROL_OFFSET, |
| .d_RESET_CONTROL_MBOX_RST_MASK = ADRASTEA_RESET_CONTROL_MBOX_RST_MASK, |
| .d_RESET_CONTROL_SI0_RST_MASK = ADRASTEA_RESET_CONTROL_SI0_RST_MASK, |
| .d_WLAN_RESET_CONTROL_OFFSET = ADRASTEA_WLAN_RESET_CONTROL_OFFSET, |
| .d_WLAN_RESET_CONTROL_COLD_RST_MASK = |
| ADRASTEA_WLAN_RESET_CONTROL_COLD_RST_MASK, |
| .d_WLAN_RESET_CONTROL_WARM_RST_MASK = |
| ADRASTEA_WLAN_RESET_CONTROL_WARM_RST_MASK, |
| .d_GPIO_BASE_ADDRESS = ADRASTEA_GPIO_BASE_ADDRESS, |
| .d_GPIO_PIN0_OFFSET = ADRASTEA_GPIO_PIN0_OFFSET, |
| .d_GPIO_PIN1_OFFSET = ADRASTEA_GPIO_PIN1_OFFSET, |
| .d_GPIO_PIN0_CONFIG_MASK = ADRASTEA_GPIO_PIN0_CONFIG_MASK, |
| .d_GPIO_PIN1_CONFIG_MASK = ADRASTEA_GPIO_PIN1_CONFIG_MASK, |
| .d_SI_CONFIG_BIDIR_OD_DATA_LSB = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_LSB, |
| .d_SI_CONFIG_BIDIR_OD_DATA_MASK = ADRASTEA_SI_CONFIG_BIDIR_OD_DATA_MASK, |
| .d_SI_CONFIG_I2C_LSB = ADRASTEA_SI_CONFIG_I2C_LSB, |
| .d_SI_CONFIG_I2C_MASK = ADRASTEA_SI_CONFIG_I2C_MASK, |
| .d_SI_CONFIG_POS_SAMPLE_LSB = ADRASTEA_SI_CONFIG_POS_SAMPLE_LSB, |
| .d_SI_CONFIG_POS_SAMPLE_MASK = ADRASTEA_SI_CONFIG_POS_SAMPLE_MASK, |
| .d_SI_CONFIG_INACTIVE_CLK_LSB = ADRASTEA_SI_CONFIG_INACTIVE_CLK_LSB, |
| .d_SI_CONFIG_INACTIVE_CLK_MASK = ADRASTEA_SI_CONFIG_INACTIVE_CLK_MASK, |
| .d_SI_CONFIG_INACTIVE_DATA_LSB = ADRASTEA_SI_CONFIG_INACTIVE_DATA_LSB, |
| .d_SI_CONFIG_INACTIVE_DATA_MASK = ADRASTEA_SI_CONFIG_INACTIVE_DATA_MASK, |
| .d_SI_CONFIG_DIVIDER_LSB = ADRASTEA_SI_CONFIG_DIVIDER_LSB, |
| .d_SI_CONFIG_DIVIDER_MASK = ADRASTEA_SI_CONFIG_DIVIDER_MASK, |
| .d_SI_BASE_ADDRESS = ADRASTEA_SI_BASE_ADDRESS, |
| .d_SI_CONFIG_OFFSET = ADRASTEA_SI_CONFIG_OFFSET, |
| .d_SI_TX_DATA0_OFFSET = ADRASTEA_SI_TX_DATA0_OFFSET, |
| .d_SI_TX_DATA1_OFFSET = ADRASTEA_SI_TX_DATA1_OFFSET, |
| .d_SI_RX_DATA0_OFFSET = ADRASTEA_SI_RX_DATA0_OFFSET, |
| .d_SI_RX_DATA1_OFFSET = ADRASTEA_SI_RX_DATA1_OFFSET, |
| .d_SI_CS_OFFSET = ADRASTEA_SI_CS_OFFSET, |
| .d_SI_CS_DONE_ERR_MASK = ADRASTEA_SI_CS_DONE_ERR_MASK, |
| .d_SI_CS_DONE_INT_MASK = ADRASTEA_SI_CS_DONE_INT_MASK, |
| .d_SI_CS_START_LSB = ADRASTEA_SI_CS_START_LSB, |
| .d_SI_CS_START_MASK = ADRASTEA_SI_CS_START_MASK, |
| .d_SI_CS_RX_CNT_LSB = ADRASTEA_SI_CS_RX_CNT_LSB, |
| .d_SI_CS_RX_CNT_MASK = ADRASTEA_SI_CS_RX_CNT_MASK, |
| .d_SI_CS_TX_CNT_LSB = ADRASTEA_SI_CS_TX_CNT_LSB, |
| .d_SI_CS_TX_CNT_MASK = ADRASTEA_SI_CS_TX_CNT_MASK, |
| .d_BOARD_DATA_SZ = ADRASTEA_BOARD_DATA_SZ, |
| .d_BOARD_EXT_DATA_SZ = ADRASTEA_BOARD_EXT_DATA_SZ, |
| .d_MBOX_BASE_ADDRESS = ADRASTEA_MBOX_BASE_ADDRESS, |
| .d_LOCAL_SCRATCH_OFFSET = ADRASTEA_LOCAL_SCRATCH_OFFSET, |
| .d_CPU_CLOCK_OFFSET = ADRASTEA_CPU_CLOCK_OFFSET, |
| .d_LPO_CAL_OFFSET = ADRASTEA_LPO_CAL_OFFSET, |
| .d_GPIO_PIN10_OFFSET = ADRASTEA_GPIO_PIN10_OFFSET, |
| .d_GPIO_PIN11_OFFSET = ADRASTEA_GPIO_PIN11_OFFSET, |
| .d_GPIO_PIN12_OFFSET = ADRASTEA_GPIO_PIN12_OFFSET, |
| .d_GPIO_PIN13_OFFSET = ADRASTEA_GPIO_PIN13_OFFSET, |
| .d_CLOCK_GPIO_OFFSET = ADRASTEA_CLOCK_GPIO_OFFSET, |
| .d_CPU_CLOCK_STANDARD_LSB = ADRASTEA_CPU_CLOCK_STANDARD_LSB, |
| .d_CPU_CLOCK_STANDARD_MASK = ADRASTEA_CPU_CLOCK_STANDARD_MASK, |
| .d_LPO_CAL_ENABLE_LSB = ADRASTEA_LPO_CAL_ENABLE_LSB, |
| .d_LPO_CAL_ENABLE_MASK = ADRASTEA_LPO_CAL_ENABLE_MASK, |
| .d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB = ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_LSB, |
| .d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK = |
| ADRASTEA_CLOCK_GPIO_BT_CLK_OUT_EN_MASK, |
| .d_ANALOG_INTF_BASE_ADDRESS = ADRASTEA_ANALOG_INTF_BASE_ADDRESS, |
| .d_WLAN_MAC_BASE_ADDRESS = ADRASTEA_WLAN_MAC_BASE_ADDRESS, |
| .d_FW_INDICATOR_ADDRESS = ADRASTEA_FW_INDICATOR_ADDRESS, |
| .d_DRAM_BASE_ADDRESS = ADRASTEA_DRAM_BASE_ADDRESS, |
| .d_SOC_CORE_BASE_ADDRESS = ADRASTEA_SOC_CORE_BASE_ADDRESS, |
| .d_CORE_CTRL_ADDRESS = ADRASTEA_CORE_CTRL_ADDRESS, |
| .d_CE_COUNT = ADRASTEA_CE_COUNT, |
| .d_MSI_NUM_REQUEST = MSI_NUM_REQUEST, |
| .d_MSI_ASSIGN_FW = MSI_ASSIGN_FW, |
| .d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL, |
| .d_PCIE_INTR_ENABLE_ADDRESS = ADRASTEA_HOST_ENABLE_REGISTER, |
| .d_PCIE_INTR_CLR_ADDRESS = ADRASTEA_HOST_CLEAR_REGISTER, |
| .d_PCIE_INTR_FIRMWARE_MASK = ADRASTEA_PCIE_INTR_FIRMWARE_MASK, |
| .d_PCIE_INTR_CE_MASK_ALL = ADRASTEA_PCIE_INTR_CE_MASK_ALL, |
| .d_CORE_CTRL_CPU_INTR_MASK = ADRASTEA_CORE_CTRL_CPU_INTR_MASK, |
| .d_SR_WR_INDEX_ADDRESS = ADRASTEA_SR_WR_INDEX_OFFSET, |
| .d_DST_WATERMARK_ADDRESS = ADRASTEA_DST_WATERMARK_OFFSET, |
| /* htt_rx.c */ |
| .d_RX_MSDU_END_4_FIRST_MSDU_MASK = |
| ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_MASK, |
| .d_RX_MSDU_END_4_FIRST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_FIRST_MSDU_LSB, |
| .d_RX_MPDU_START_0_SEQ_NUM_MASK = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_MASK, |
| .d_RX_MPDU_START_0_SEQ_NUM_LSB = ADRASTEA_RX_MPDU_START_0_SEQ_NUM_LSB, |
| .d_RX_MPDU_START_2_PN_47_32_LSB = ADRASTEA_RX_MPDU_START_2_PN_47_32_LSB, |
| .d_RX_MPDU_START_2_PN_47_32_MASK = |
| ADRASTEA_RX_MPDU_START_2_PN_47_32_MASK, |
| .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK = |
| ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK, |
| .d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB = |
| ADRASTEA_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB, |
| .d_RX_MSDU_END_4_LAST_MSDU_MASK = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_MASK, |
| .d_RX_MSDU_END_4_LAST_MSDU_LSB = ADRASTEA_RX_MSDU_END_4_LAST_MSDU_LSB, |
| .d_RX_ATTENTION_0_MCAST_BCAST_MASK = |
| ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_MASK, |
| .d_RX_ATTENTION_0_MCAST_BCAST_LSB = |
| ADRASTEA_RX_ATTENTION_0_MCAST_BCAST_LSB, |
| .d_RX_ATTENTION_0_FRAGMENT_MASK = ADRASTEA_RX_ATTENTION_0_FRAGMENT_MASK, |
| .d_RX_ATTENTION_0_FRAGMENT_LSB = ADRASTEA_RX_ATTENTION_0_FRAGMENT_LSB, |
| .d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK = |
| ADRASTEA_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK, |
| .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK = |
| ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK, |
| .d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB = |
| ADRASTEA_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB, |
| .d_RX_MSDU_START_0_MSDU_LENGTH_MASK = |
| ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_MASK, |
| .d_RX_MSDU_START_0_MSDU_LENGTH_LSB = |
| ADRASTEA_RX_MSDU_START_0_MSDU_LENGTH_LSB, |
| .d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET = |
| ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_OFFSET, |
| .d_RX_MSDU_START_2_DECAP_FORMAT_MASK = |
| ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_MASK, |
| .d_RX_MSDU_START_2_DECAP_FORMAT_LSB = |
| ADRASTEA_RX_MSDU_START_2_DECAP_FORMAT_LSB, |
| .d_RX_MPDU_START_0_ENCRYPTED_MASK = |
| ADRASTEA_RX_MPDU_START_0_ENCRYPTED_MASK, |
| .d_RX_MPDU_START_0_ENCRYPTED_LSB = |
| ADRASTEA_RX_MPDU_START_0_ENCRYPTED_LSB, |
| .d_RX_ATTENTION_0_MORE_DATA_MASK = |
| ADRASTEA_RX_ATTENTION_0_MORE_DATA_MASK, |
| .d_RX_ATTENTION_0_MSDU_DONE_MASK = |
| ADRASTEA_RX_ATTENTION_0_MSDU_DONE_MASK, |
| .d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK = |
| ADRASTEA_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK, |
| |
| /* PLL start */ |
| .d_EFUSE_OFFSET = ADRASTEA_EFUSE_OFFSET, |
| .d_EFUSE_XTAL_SEL_MSB = ADRASTEA_EFUSE_XTAL_SEL_MSB, |
| .d_EFUSE_XTAL_SEL_LSB = ADRASTEA_EFUSE_XTAL_SEL_LSB, |
| .d_EFUSE_XTAL_SEL_MASK = ADRASTEA_EFUSE_XTAL_SEL_MASK, |
| .d_BB_PLL_CONFIG_OFFSET = ADRASTEA_BB_PLL_CONFIG_OFFSET, |
| .d_BB_PLL_CONFIG_OUTDIV_MSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MSB, |
| .d_BB_PLL_CONFIG_OUTDIV_LSB = ADRASTEA_BB_PLL_CONFIG_OUTDIV_LSB, |
| .d_BB_PLL_CONFIG_OUTDIV_MASK = ADRASTEA_BB_PLL_CONFIG_OUTDIV_MASK, |
| .d_BB_PLL_CONFIG_FRAC_MSB = ADRASTEA_BB_PLL_CONFIG_FRAC_MSB, |
| .d_BB_PLL_CONFIG_FRAC_LSB = ADRASTEA_BB_PLL_CONFIG_FRAC_LSB, |
| .d_BB_PLL_CONFIG_FRAC_MASK = ADRASTEA_BB_PLL_CONFIG_FRAC_MASK, |
| .d_WLAN_PLL_SETTLE_TIME_MSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_MSB, |
| .d_WLAN_PLL_SETTLE_TIME_LSB = ADRASTEA_WLAN_PLL_SETTLE_TIME_LSB, |
| .d_WLAN_PLL_SETTLE_TIME_MASK = ADRASTEA_WLAN_PLL_SETTLE_TIME_MASK, |
| .d_WLAN_PLL_SETTLE_OFFSET = ADRASTEA_WLAN_PLL_SETTLE_OFFSET, |
| .d_WLAN_PLL_SETTLE_SW_MASK = ADRASTEA_WLAN_PLL_SETTLE_SW_MASK, |
| .d_WLAN_PLL_SETTLE_RSTMASK = ADRASTEA_WLAN_PLL_SETTLE_RSTMASK, |
| .d_WLAN_PLL_SETTLE_RESET = ADRASTEA_WLAN_PLL_SETTLE_RESET, |
| .d_WLAN_PLL_CONTROL_NOPWD_MSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MSB, |
| .d_WLAN_PLL_CONTROL_NOPWD_LSB = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_LSB, |
| .d_WLAN_PLL_CONTROL_NOPWD_MASK = ADRASTEA_WLAN_PLL_CONTROL_NOPWD_MASK, |
| .d_WLAN_PLL_CONTROL_BYPASS_MSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MSB, |
| .d_WLAN_PLL_CONTROL_BYPASS_LSB = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_LSB, |
| .d_WLAN_PLL_CONTROL_BYPASS_MASK = ADRASTEA_WLAN_PLL_CONTROL_BYPASS_MASK, |
| .d_WLAN_PLL_CONTROL_BYPASS_RESET = |
| ADRASTEA_WLAN_PLL_CONTROL_BYPASS_RESET, |
| .d_WLAN_PLL_CONTROL_CLK_SEL_MSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MSB, |
| .d_WLAN_PLL_CONTROL_CLK_SEL_LSB = ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_LSB, |
| .d_WLAN_PLL_CONTROL_CLK_SEL_MASK = |
| ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_MASK, |
| .d_WLAN_PLL_CONTROL_CLK_SEL_RESET = |
| ADRASTEA_WLAN_PLL_CONTROL_CLK_SEL_RESET, |
| .d_WLAN_PLL_CONTROL_REFDIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MSB, |
| .d_WLAN_PLL_CONTROL_REFDIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_LSB, |
| .d_WLAN_PLL_CONTROL_REFDIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_REFDIV_MASK, |
| .d_WLAN_PLL_CONTROL_REFDIV_RESET = |
| ADRASTEA_WLAN_PLL_CONTROL_REFDIV_RESET, |
| .d_WLAN_PLL_CONTROL_DIV_MSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_MSB, |
| .d_WLAN_PLL_CONTROL_DIV_LSB = ADRASTEA_WLAN_PLL_CONTROL_DIV_LSB, |
| .d_WLAN_PLL_CONTROL_DIV_MASK = ADRASTEA_WLAN_PLL_CONTROL_DIV_MASK, |
| .d_WLAN_PLL_CONTROL_DIV_RESET = ADRASTEA_WLAN_PLL_CONTROL_DIV_RESET, |
| .d_WLAN_PLL_CONTROL_OFFSET = ADRASTEA_WLAN_PLL_CONTROL_OFFSET, |
| .d_WLAN_PLL_CONTROL_SW_MASK = ADRASTEA_WLAN_PLL_CONTROL_SW_MASK, |
| .d_WLAN_PLL_CONTROL_RSTMASK = ADRASTEA_WLAN_PLL_CONTROL_RSTMASK, |
| .d_WLAN_PLL_CONTROL_RESET = ADRASTEA_WLAN_PLL_CONTROL_RESET, |
| .d_SOC_CORE_CLK_CTRL_OFFSET = ADRASTEA_SOC_CORE_CLK_CTRL_OFFSET, |
| .d_SOC_CORE_CLK_CTRL_DIV_MSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MSB, |
| .d_SOC_CORE_CLK_CTRL_DIV_LSB = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_LSB, |
| .d_SOC_CORE_CLK_CTRL_DIV_MASK = ADRASTEA_SOC_CORE_CLK_CTRL_DIV_MASK, |
| .d_RTC_SYNC_STATUS_PLL_CHANGING_MSB = |
| ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MSB, |
| .d_RTC_SYNC_STATUS_PLL_CHANGING_LSB = |
| ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_LSB, |
| .d_RTC_SYNC_STATUS_PLL_CHANGING_MASK = |
| ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_MASK, |
| .d_RTC_SYNC_STATUS_PLL_CHANGING_RESET = |
| ADRASTEA_RTC_SYNC_STATUS_PLL_CHANGING_RESET, |
| .d_RTC_SYNC_STATUS_OFFSET = ADRASTEA_RTC_SYNC_STATUS_OFFSET, |
| .d_SOC_CPU_CLOCK_OFFSET = ADRASTEA_SOC_CPU_CLOCK_OFFSET, |
| .d_SOC_CPU_CLOCK_STANDARD_MSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MSB, |
| .d_SOC_CPU_CLOCK_STANDARD_LSB = ADRASTEA_SOC_CPU_CLOCK_STANDARD_LSB, |
| .d_SOC_CPU_CLOCK_STANDARD_MASK = ADRASTEA_SOC_CPU_CLOCK_STANDARD_MASK, |
| /* PLL end */ |
| .d_SOC_POWER_REG_OFFSET = ADRASTEA_SOC_POWER_REG_OFFSET, |
| .d_PCIE_INTR_CAUSE_ADDRESS = ADRASTEA_HOST_CAUSE_REGISTER, |
| .d_SOC_RESET_CONTROL_ADDRESS = ADRASTEA_SOC_RESET_CONTROL_ADDRESS, |
| .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK = |
| ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK, |
| .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB = |
| ADRASTEA_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB, |
| .d_SOC_RESET_CONTROL_CE_RST_MASK = |
| ADRASTEA_SOC_RESET_CONTROL_CE_RST_MASK, |
| .d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK = |
| ADRASTEA_SOC_RESET_CONTROL_CPU_WARM_RST_MASK, |
| .d_CPU_INTR_ADDRESS = ADRASTEA_CPU_INTR_ADDRESS, |
| .d_SOC_LF_TIMER_CONTROL0_ADDRESS = |
| ADRASTEA_SOC_LF_TIMER_CONTROL0_ADDRESS, |
| .d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK = |
| ADRASTEA_SOC_LF_TIMER_CONTROL0_ENABLE_MASK, |
| /* chip id start */ |
| .d_SOC_CHIP_ID_ADDRESS = ADRASTEA_SOC_CHIP_ID_ADDRESS, |
| .d_SOC_CHIP_ID_VERSION_MASK = ADRASTEA_SOC_CHIP_ID_VERSION_MASK, |
| .d_SOC_CHIP_ID_VERSION_LSB = ADRASTEA_SOC_CHIP_ID_VERSION_LSB, |
| .d_SOC_CHIP_ID_REVISION_MASK = ADRASTEA_SOC_CHIP_ID_REVISION_MASK, |
| .d_SOC_CHIP_ID_REVISION_LSB = ADRASTEA_SOC_CHIP_ID_REVISION_LSB, |
| /* chip id end */ |
| .d_A_SOC_CORE_SCRATCH_0_ADDRESS = ADRASTEA_A_SOC_CORE_SCRATCH_0_ADDRESS, |
| .d_A_SOC_CORE_SPARE_0_REGISTER = ADRASTEA_A_SOC_CORE_SPARE_0_REGISTER, |
| .d_PCIE_INTR_FIRMWARE_ROUTE_MASK = |
| ADRASTEA_PCIE_INTR_FIRMWARE_ROUTE_MASK, |
| .d_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1 = |
| ADRASTEA_A_SOC_CORE_PCIE_INTR_CAUSE_GRP1, |
| .d_A_SOC_CORE_SPARE_1_REGISTER = |
| ADRASTEA_A_SOC_CORE_SPARE_1_REGISTER, |
| .d_A_SOC_CORE_PCIE_INTR_CLR_GRP1 = |
| ADRASTEA_A_SOC_CORE_PCIE_INTR_CLR_GRP1, |
| .d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1 = |
| ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP1, |
| .d_A_SOC_PCIE_PCIE_SCRATCH_0 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_0, |
| .d_A_SOC_PCIE_PCIE_SCRATCH_1 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_1, |
| .d_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA = |
| ADRASTEA_A_WIFI_APB_1_A_WFSS_CE_TARGET_HOST_DELTA, |
| .d_A_SOC_PCIE_PCIE_SCRATCH_2 = ADRASTEA_A_SOC_PCIE_PCIE_SCRATCH_2, |
| .d_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK = |
| ADRASTEA_A_SOC_CORE_PCIE_INTR_ENABLE_GRP0_Q6_MASK, |
| .d_WLAN_DEBUG_INPUT_SEL_OFFSET = ADRASTEA_WLAN_DEBUG_INPUT_SEL_OFFSET, |
| .d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MSB, |
| .d_WLAN_DEBUG_INPUT_SEL_SRC_LSB = ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_LSB, |
| .d_WLAN_DEBUG_INPUT_SEL_SRC_MASK = |
| ADRASTEA_WLAN_DEBUG_INPUT_SEL_SRC_MASK, |
| .d_WLAN_DEBUG_CONTROL_OFFSET = ADRASTEA_WLAN_DEBUG_CONTROL_OFFSET, |
| .d_WLAN_DEBUG_CONTROL_ENABLE_MSB = |
| ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MSB, |
| .d_WLAN_DEBUG_CONTROL_ENABLE_LSB = |
| ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_LSB, |
| .d_WLAN_DEBUG_CONTROL_ENABLE_MASK = |
| ADRASTEA_WLAN_DEBUG_CONTROL_ENABLE_MASK, |
| .d_WLAN_DEBUG_OUT_OFFSET = ADRASTEA_WLAN_DEBUG_OUT_OFFSET, |
| .d_WLAN_DEBUG_OUT_DATA_MSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_MSB, |
| .d_WLAN_DEBUG_OUT_DATA_LSB = ADRASTEA_WLAN_DEBUG_OUT_DATA_LSB, |
| .d_WLAN_DEBUG_OUT_DATA_MASK = ADRASTEA_WLAN_DEBUG_OUT_DATA_MASK, |
| .d_AMBA_DEBUG_BUS_OFFSET = ADRASTEA_AMBA_DEBUG_BUS_OFFSET, |
| .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB = |
| ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB, |
| .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB = |
| ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB, |
| .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK = |
| ADRASTEA_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK, |
| .d_AMBA_DEBUG_BUS_SEL_MSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_MSB, |
| .d_AMBA_DEBUG_BUS_SEL_LSB = ADRASTEA_AMBA_DEBUG_BUS_SEL_LSB, |
| .d_AMBA_DEBUG_BUS_SEL_MASK = ADRASTEA_AMBA_DEBUG_BUS_SEL_MASK, |
| |
| #ifdef QCA_WIFI_3_0_ADRASTEA |
| .d_Q6_ENABLE_REGISTER_0 = ADRASTEA_Q6_ENABLE_REGISTER_0, |
| .d_Q6_ENABLE_REGISTER_1 = ADRASTEA_Q6_ENABLE_REGISTER_1, |
| .d_Q6_CAUSE_REGISTER_0 = ADRASTEA_Q6_CAUSE_REGISTER_0, |
| .d_Q6_CAUSE_REGISTER_1 = ADRASTEA_Q6_CAUSE_REGISTER_1, |
| .d_Q6_CLEAR_REGISTER_0 = ADRASTEA_Q6_CLEAR_REGISTER_0, |
| .d_Q6_CLEAR_REGISTER_1 = ADRASTEA_Q6_CLEAR_REGISTER_1, |
| #endif |
| |
| #ifdef CONFIG_BYPASS_QMI |
| .d_BYPASS_QMI_TEMP_REGISTER = ADRASTEA_BYPASS_QMI_TEMP_REGISTER, |
| #endif |
| }; |
| |
| struct hostdef_s adrastea_hostdef = { |
| .d_INT_STATUS_ENABLE_ERROR_LSB = ADRASTEA_INT_STATUS_ENABLE_ERROR_LSB, |
| .d_INT_STATUS_ENABLE_ERROR_MASK = ADRASTEA_INT_STATUS_ENABLE_ERROR_MASK, |
| .d_INT_STATUS_ENABLE_CPU_LSB = ADRASTEA_INT_STATUS_ENABLE_CPU_LSB, |
| .d_INT_STATUS_ENABLE_CPU_MASK = ADRASTEA_INT_STATUS_ENABLE_CPU_MASK, |
| .d_INT_STATUS_ENABLE_COUNTER_LSB = |
| ADRASTEA_INT_STATUS_ENABLE_COUNTER_LSB, |
| .d_INT_STATUS_ENABLE_COUNTER_MASK = |
| ADRASTEA_INT_STATUS_ENABLE_COUNTER_MASK, |
| .d_INT_STATUS_ENABLE_MBOX_DATA_LSB = |
| ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_LSB, |
| .d_INT_STATUS_ENABLE_MBOX_DATA_MASK = |
| ADRASTEA_INT_STATUS_ENABLE_MBOX_DATA_MASK, |
| .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB = |
| ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB, |
| .d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK = |
| ADRASTEA_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK, |
| .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB = |
| ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB, |
| .d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK = |
| ADRASTEA_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK, |
| .d_COUNTER_INT_STATUS_ENABLE_BIT_LSB = |
| ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_LSB, |
| .d_COUNTER_INT_STATUS_ENABLE_BIT_MASK = |
| ADRASTEA_COUNTER_INT_STATUS_ENABLE_BIT_MASK, |
| .d_INT_STATUS_ENABLE_ADDRESS = ADRASTEA_INT_STATUS_ENABLE_ADDRESS, |
| .d_CPU_INT_STATUS_ENABLE_BIT_LSB = |
| ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_LSB, |
| .d_CPU_INT_STATUS_ENABLE_BIT_MASK = |
| ADRASTEA_CPU_INT_STATUS_ENABLE_BIT_MASK, |
| .d_HOST_INT_STATUS_ADDRESS = ADRASTEA_HOST_INT_STATUS_ADDRESS, |
| .d_CPU_INT_STATUS_ADDRESS = ADRASTEA_CPU_INT_STATUS_ADDRESS, |
| .d_ERROR_INT_STATUS_ADDRESS = ADRASTEA_ERROR_INT_STATUS_ADDRESS, |
| .d_ERROR_INT_STATUS_WAKEUP_MASK = ADRASTEA_ERROR_INT_STATUS_WAKEUP_MASK, |
| .d_ERROR_INT_STATUS_WAKEUP_LSB = ADRASTEA_ERROR_INT_STATUS_WAKEUP_LSB, |
| .d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK = |
| ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_MASK, |
| .d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB = |
| ADRASTEA_ERROR_INT_STATUS_RX_UNDERFLOW_LSB, |
| .d_ERROR_INT_STATUS_TX_OVERFLOW_MASK = |
| ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_MASK, |
| .d_ERROR_INT_STATUS_TX_OVERFLOW_LSB = |
| ADRASTEA_ERROR_INT_STATUS_TX_OVERFLOW_LSB, |
| .d_COUNT_DEC_ADDRESS = ADRASTEA_COUNT_DEC_ADDRESS, |
| .d_HOST_INT_STATUS_CPU_MASK = ADRASTEA_HOST_INT_STATUS_CPU_MASK, |
| .d_HOST_INT_STATUS_CPU_LSB = ADRASTEA_HOST_INT_STATUS_CPU_LSB, |
| .d_HOST_INT_STATUS_ERROR_MASK = ADRASTEA_HOST_INT_STATUS_ERROR_MASK, |
| .d_HOST_INT_STATUS_ERROR_LSB = ADRASTEA_HOST_INT_STATUS_ERROR_LSB, |
| .d_HOST_INT_STATUS_COUNTER_MASK = ADRASTEA_HOST_INT_STATUS_COUNTER_MASK, |
| .d_HOST_INT_STATUS_COUNTER_LSB = ADRASTEA_HOST_INT_STATUS_COUNTER_LSB, |
| .d_RX_LOOKAHEAD_VALID_ADDRESS = ADRASTEA_RX_LOOKAHEAD_VALID_ADDRESS, |
| .d_WINDOW_DATA_ADDRESS = ADRASTEA_WINDOW_DATA_ADDRESS, |
| .d_WINDOW_READ_ADDR_ADDRESS = ADRASTEA_WINDOW_READ_ADDR_ADDRESS, |
| .d_WINDOW_WRITE_ADDR_ADDRESS = ADRASTEA_WINDOW_WRITE_ADDR_ADDRESS, |
| .d_SOC_GLOBAL_RESET_ADDRESS = ADRASTEA_SOC_GLOBAL_RESET_ADDRESS, |
| .d_RTC_STATE_ADDRESS = ADRASTEA_RTC_STATE_ADDRESS, |
| .d_RTC_STATE_COLD_RESET_MASK = ADRASTEA_RTC_STATE_COLD_RESET_MASK, |
| .d_PCIE_LOCAL_BASE_ADDRESS = ADRASTEA_PCIE_LOCAL_BASE_ADDRESS, |
| .d_PCIE_SOC_WAKE_RESET = ADRASTEA_PCIE_SOC_WAKE_RESET, |
| .d_PCIE_SOC_WAKE_ADDRESS = ADRASTEA_PCIE_SOC_WAKE_ADDRESS, |
| .d_PCIE_SOC_WAKE_V_MASK = ADRASTEA_PCIE_SOC_WAKE_V_MASK, |
| .d_RTC_STATE_V_MASK = ADRASTEA_RTC_STATE_V_MASK, |
| .d_RTC_STATE_V_LSB = ADRASTEA_RTC_STATE_V_LSB, |
| .d_FW_IND_EVENT_PENDING = ADRASTEA_FW_IND_EVENT_PENDING, |
| .d_FW_IND_INITIALIZED = ADRASTEA_FW_IND_INITIALIZED, |
| .d_FW_IND_HELPER = ADRASTEA_FW_IND_HELPER, |
| .d_RTC_STATE_V_ON = ADRASTEA_RTC_STATE_V_ON, |
| #if defined(SDIO_3_0) |
| .d_HOST_INT_STATUS_MBOX_DATA_MASK = |
| ADRASTEA_HOST_INT_STATUS_MBOX_DATA_MASK, |
| .d_HOST_INT_STATUS_MBOX_DATA_LSB = |
| ADRASTEA_HOST_INT_STATUS_MBOX_DATA_LSB, |
| #endif |
| .d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS, |
| .d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK, |
| .d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS, |
| .d_MSI_MAGIC_ADR_ADDRESS = MSI_MAGIC_ADR_ADDRESS, |
| .d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS, |
| .d_HOST_CE_COUNT = ADRASTEA_CE_COUNT, |
| .d_ENABLE_MSI = 0, |
| .d_MUX_ID_MASK = 0xf000, |
| .d_TRANSACTION_ID_MASK = 0x0fff, |
| .d_DESC_DATA_FLAG_MASK = 0x1FFFE3E0, |
| .d_A_SOC_PCIE_PCIE_BAR0_START = ADRASTEA_A_SOC_PCIE_PCIE_BAR0_START, |
| }; |
| |
| |
| struct ce_reg_def adrastea_ce_targetdef = { |
| /* copy_engine.c */ |
| .d_DST_WR_INDEX_ADDRESS = ADRASTEA_DST_WR_INDEX_OFFSET, |
| .d_SRC_WATERMARK_ADDRESS = ADRASTEA_SRC_WATERMARK_OFFSET, |
| .d_SRC_WATERMARK_LOW_MASK = ADRASTEA_SRC_WATERMARK_LOW_MASK, |
| .d_SRC_WATERMARK_HIGH_MASK = ADRASTEA_SRC_WATERMARK_HIGH_MASK, |
| .d_DST_WATERMARK_LOW_MASK = ADRASTEA_DST_WATERMARK_LOW_MASK, |
| .d_DST_WATERMARK_HIGH_MASK = ADRASTEA_DST_WATERMARK_HIGH_MASK, |
| .d_CURRENT_SRRI_ADDRESS = ADRASTEA_CURRENT_SRRI_OFFSET, |
| .d_CURRENT_DRRI_ADDRESS = ADRASTEA_CURRENT_DRRI_OFFSET, |
| .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK = |
| ADRASTEA_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, |
| .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK = |
| ADRASTEA_HOST_IS_SRC_RING_LOW_WATERMARK_MASK, |
| .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK = |
| ADRASTEA_HOST_IS_DST_RING_HIGH_WATERMARK_MASK, |
| .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK = |
| ADRASTEA_HOST_IS_DST_RING_LOW_WATERMARK_MASK, |
| .d_HOST_IS_ADDRESS = ADRASTEA_HOST_IS_OFFSET, |
| .d_MISC_IS_ADDRESS = ADRASTEA_MISC_IS_OFFSET, |
| .d_HOST_IS_COPY_COMPLETE_MASK = ADRASTEA_HOST_IS_COPY_COMPLETE_MASK, |
| .d_CE_WRAPPER_BASE_ADDRESS = ADRASTEA_CE_WRAPPER_BASE_ADDRESS, |
| .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS = |
| ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET, |
| .d_CE_DDR_ADDRESS_FOR_RRI_LOW = |
| ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_LOW, |
| .d_CE_DDR_ADDRESS_FOR_RRI_HIGH = |
| ADRASTEA_CE_DDR_ADDRESS_FOR_RRI_HIGH, |
| .d_HOST_IE_ADDRESS = ADRASTEA_HOST_IE_OFFSET, |
| .d_HOST_IE_COPY_COMPLETE_MASK = ADRASTEA_HOST_IE_COPY_COMPLETE_MASK, |
| .d_SR_BA_ADDRESS = ADRASTEA_SR_BA_OFFSET, |
| .d_SR_BA_ADDRESS_HIGH = ADRASTEA_SR_BA_HIGH_OFFSET, |
| .d_SR_SIZE_ADDRESS = ADRASTEA_SR_SIZE_OFFSET, |
| .d_CE_CTRL1_ADDRESS = ADRASTEA_CE_CTRL1_OFFSET, |
| .d_CE_CTRL1_DMAX_LENGTH_MASK = ADRASTEA_CE_CTRL1_DMAX_LENGTH_MASK, |
| .d_DR_BA_ADDRESS = ADRASTEA_DR_BA_OFFSET, |
| .d_DR_BA_ADDRESS_HIGH = ADRASTEA_DR_BA_HIGH_OFFSET, |
| .d_DR_SIZE_ADDRESS = ADRASTEA_DR_SIZE_OFFSET, |
| .d_CE_CMD_REGISTER = ADRASTEA_CE_CMD_REGISTER_OFFSET, |
| .d_CE_MSI_ADDRESS = MISSING_FOR_ADRASTEA, |
| .d_CE_MSI_ADDRESS_HIGH = MISSING_FOR_ADRASTEA, |
| .d_CE_MSI_DATA = MISSING_FOR_ADRASTEA, |
| .d_CE_MSI_ENABLE_BIT = MISSING_FOR_ADRASTEA, |
| .d_MISC_IE_ADDRESS = ADRASTEA_MISC_IE_OFFSET, |
| .d_MISC_IS_AXI_ERR_MASK = ADRASTEA_MISC_IS_AXI_ERR_MASK, |
| .d_MISC_IS_DST_ADDR_ERR_MASK = ADRASTEA_MISC_IS_DST_ADDR_ERR_MASK, |
| .d_MISC_IS_SRC_LEN_ERR_MASK = ADRASTEA_MISC_IS_SRC_LEN_ERR_MASK, |
| .d_MISC_IS_DST_MAX_LEN_VIO_MASK = ADRASTEA_MISC_IS_DST_MAX_LEN_VIO_MASK, |
| .d_MISC_IS_DST_RING_OVERFLOW_MASK = |
| ADRASTEA_MISC_IS_DST_RING_OVERFLOW_MASK, |
| .d_MISC_IS_SRC_RING_OVERFLOW_MASK = |
| ADRASTEA_MISC_IS_SRC_RING_OVERFLOW_MASK, |
| .d_SRC_WATERMARK_LOW_LSB = ADRASTEA_SRC_WATERMARK_LOW_LSB, |
| .d_SRC_WATERMARK_HIGH_LSB = ADRASTEA_SRC_WATERMARK_HIGH_LSB, |
| .d_DST_WATERMARK_LOW_LSB = ADRASTEA_DST_WATERMARK_LOW_LSB, |
| .d_DST_WATERMARK_HIGH_LSB = ADRASTEA_DST_WATERMARK_HIGH_LSB, |
| .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK = |
| ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, |
| .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB = |
| ADRASTEA_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, |
| .d_CE_CTRL1_DMAX_LENGTH_LSB = ADRASTEA_CE_CTRL1_DMAX_LENGTH_LSB, |
| .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK = |
| ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, |
| .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK = |
| ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, |
| .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB = |
| ADRASTEA_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, |
| .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB = |
| ADRASTEA_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, |
| .d_CE_CTRL1_IDX_UPD_EN_MASK = |
| ADRASTEA_A_WCSS_HM_A_WIFI_APB_1_A_WFSS_CE0_CE_CTRL1__IDX_UPD_EN___M, |
| .d_CE_WRAPPER_DEBUG_OFFSET = ADRASTEA_CE_WRAPPER_DEBUG_OFFSET, |
| .d_CE_WRAPPER_DEBUG_SEL_MSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MSB, |
| .d_CE_WRAPPER_DEBUG_SEL_LSB = ADRASTEA_CE_WRAPPER_DEBUG_SEL_LSB, |
| .d_CE_WRAPPER_DEBUG_SEL_MASK = ADRASTEA_CE_WRAPPER_DEBUG_SEL_MASK, |
| .d_CE_DEBUG_OFFSET = ADRASTEA_CE_DEBUG_OFFSET, |
| .d_CE_DEBUG_SEL_MSB = ADRASTEA_CE_DEBUG_SEL_MSB, |
| .d_CE_DEBUG_SEL_LSB = ADRASTEA_CE_DEBUG_SEL_LSB, |
| .d_CE_DEBUG_SEL_MASK = ADRASTEA_CE_DEBUG_SEL_MASK, |
| .d_CE0_BASE_ADDRESS = ADRASTEA_CE0_BASE_ADDRESS, |
| .d_CE1_BASE_ADDRESS = ADRASTEA_CE1_BASE_ADDRESS, |
| .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES = |
| MISSING_FOR_ADRASTEA, |
| .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS = |
| MISSING_FOR_ADRASTEA, |
| }; |
| |
| |
| struct host_shadow_regs_s adrastea_host_shadow_regs = { |
| .d_A_LOCAL_SHADOW_REG_VALUE_0 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_0, |
| .d_A_LOCAL_SHADOW_REG_VALUE_1 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_1, |
| .d_A_LOCAL_SHADOW_REG_VALUE_2 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_2, |
| .d_A_LOCAL_SHADOW_REG_VALUE_3 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_3, |
| .d_A_LOCAL_SHADOW_REG_VALUE_4 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_4, |
| .d_A_LOCAL_SHADOW_REG_VALUE_5 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_5, |
| .d_A_LOCAL_SHADOW_REG_VALUE_6 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_6, |
| .d_A_LOCAL_SHADOW_REG_VALUE_7 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_7, |
| .d_A_LOCAL_SHADOW_REG_VALUE_8 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_8, |
| .d_A_LOCAL_SHADOW_REG_VALUE_9 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_9, |
| .d_A_LOCAL_SHADOW_REG_VALUE_10 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_10, |
| .d_A_LOCAL_SHADOW_REG_VALUE_11 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_11, |
| .d_A_LOCAL_SHADOW_REG_VALUE_12 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_12, |
| .d_A_LOCAL_SHADOW_REG_VALUE_13 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_13, |
| .d_A_LOCAL_SHADOW_REG_VALUE_14 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_14, |
| .d_A_LOCAL_SHADOW_REG_VALUE_15 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_15, |
| .d_A_LOCAL_SHADOW_REG_VALUE_16 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_16, |
| .d_A_LOCAL_SHADOW_REG_VALUE_17 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_17, |
| .d_A_LOCAL_SHADOW_REG_VALUE_18 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_18, |
| .d_A_LOCAL_SHADOW_REG_VALUE_19 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_19, |
| .d_A_LOCAL_SHADOW_REG_VALUE_20 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_20, |
| .d_A_LOCAL_SHADOW_REG_VALUE_21 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_21, |
| .d_A_LOCAL_SHADOW_REG_VALUE_22 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_22, |
| .d_A_LOCAL_SHADOW_REG_VALUE_23 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_VALUE_23, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_0 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_0, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_1 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_1, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_2 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_2, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_3 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_3, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_4 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_4, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_5 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_5, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_6 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_6, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_7 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_7, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_8 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_8, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_9 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_9, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_10 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_10, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_11 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_11, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_12 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_12, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_13 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_13, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_14 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_14, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_15 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_15, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_16 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_16, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_17 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_17, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_18 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_18, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_19 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_19, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_20 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_20, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_21 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_21, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_22 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_22, |
| .d_A_LOCAL_SHADOW_REG_ADDRESS_23 = |
| ADRASTEA_A_LOCAL_SHADOW_REG_ADDRESS_23 |
| }; |
| |
| #endif /* ADRASTEA_REG_DEF_H */ |
