Merge branch 'LA.UM.8.13.R1.08.00.00.571.015' via branch 'qcom-msm-4.19-7250' into android-msm-pixel-4.19
Bug: 140357864
Change-Id: I756d0b95be2cccefe4f5acf5158cbee51ba56844
Signed-off-by: Alex Hong <rurumihong@google.com>
diff --git a/bindings/dpu.txt b/bindings/dpu.txt
new file mode 100644
index 0000000..ad2e883
--- /dev/null
+++ b/bindings/dpu.txt
@@ -0,0 +1,131 @@
+Qualcomm Technologies, Inc. DPU KMS
+
+Description:
+
+Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+sub-blocks like DPU display controller, DSI and DP interfaces etc.
+The DPU display controller is found in SDM845 SoC.
+
+MDSS:
+Required properties:
+- compatible: "qcom,sdm845-mdss"
+- reg: physical base address and length of contoller's registers.
+- reg-names: register region names. The following region is required:
+ * "mdss"
+- power-domains: a power domain consumer specifier according to
+ Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: list of clock specifiers for clocks needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required:
+ * "iface"
+ * "bus"
+ * "core"
+- interrupts: interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+ source, should be 1.
+- iommus: phandle of iommu device node.
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- assigned-clocks: list of clock specifiers for clocks needing rate assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+MDP:
+Required properties:
+- compatible: "qcom,sdm845-dpu"
+- reg: physical base address and length of controller's registers.
+- reg-names : register region names. The following region is required:
+ * "mdp"
+ * "vbif"
+- clocks: list of clock specifiers for clocks needed by the device.
+- clock-names: device clock names, must be in same order as clocks property.
+ The following clocks are required.
+ * "bus"
+ * "iface"
+ * "core"
+ * "vsync"
+- interrupts: interrupt line from DPU to MDSS.
+- ports: contains the list of output ports from DPU device. These ports connect
+ to interfaces that are external to the DPU hardware, such as DSI, DP etc.
+
+ Each output port contains an endpoint that describes how it is connected to an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ Port 0 -> DPU_INTF1 (DSI1)
+ Port 1 -> DPU_INTF2 (DSI2)
+
+Optional properties:
+- assigned-clocks: list of clock specifiers for clocks needing rate assignment
+- assigned-clock-rates: list of clock frequencies sorted in the same order as
+ the assigned-clocks property.
+
+Example:
+
+ mdss: mdss@ae00000 {
+ compatible = "qcom,sdm845-mdss";
+ reg = <0xae00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&clock_dispcc 0>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
+ assigned-clock-rates = <300000000>;
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_iommu 0>;
+
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0xae00000 0xb2008>;
+
+ mdss_mdp: mdp@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <0 0 300000000 19200000>;
+
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+ };
diff --git a/bindings/dsi.txt b/bindings/dsi.txt
new file mode 100644
index 0000000..577b3ce
--- /dev/null
+++ b/bindings/dsi.txt
@@ -0,0 +1,247 @@
+Qualcomm Technologies Inc. adreno/snapdragon DSI output
+
+DSI Controller:
+Required properties:
+- compatible:
+ * "qcom,mdss-dsi-ctrl"
+- reg: Physical base address and length of the registers of controller
+- reg-names: The names of register regions. The following regions are required:
+ * "dsi_ctrl"
+- interrupts: The interrupt signal from the DSI block.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: Phandles to device clocks.
+- clock-names: the following clocks are required:
+ * "mdp_core"
+ * "iface"
+ * "bus"
+ * "core_mmss"
+ * "byte"
+ * "pixel"
+ * "core"
+ For DSIv2, we need an additional clock:
+ * "src"
+ For DSI6G v2.0 onwards, we need also need the clock:
+ * "byte_intf"
+- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
+- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
+ by a DSI PHY block. See [1] for details on clock bindings.
+- vdd-supply: phandle to vdd regulator device node
+- vddio-supply: phandle to vdd-io regulator device node
+- vdda-supply: phandle to vdda regulator device node
+- phys: phandle to DSI PHY device node
+- phy-names: the name of the corresponding PHY device
+- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
+- ports: Contains 2 DSI controller ports as child nodes. Each port contains
+ an endpoint subnode as defined in [2] and [3].
+
+Optional properties:
+- panel@0: Node of panel connected to this DSI controller.
+ See files in [4] for each supported panel.
+- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
+ driving a panel which needs 2 DSI links.
+- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
+ the master link of the 2-DSI panel.
+- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
+ driving a 2-DSI panel whose 2 links need receive command simultaneously.
+- pinctrl-names: the pin control state names; should contain "default"
+- pinctrl-0: the default pinctrl state (active)
+- pinctrl-n: the "sleep" pinctrl state
+- ports: contains DSI controller input and output ports as children, each
+ containing one endpoint subnode.
+
+ DSI Endpoint properties:
+ - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
+ input endpoint. For port@1, set to the MDP interface output. See [2] for
+ device graph info.
+
+ - data-lanes: this describes how the physical DSI data lanes are mapped
+ to the logical lanes on the given platform. The value contained in
+ index n describes what physical lane is mapped to the logical lane n
+ (DATAn, where n lies between 0 and 3). The clock lane position is fixed
+ and can't be changed. Hence, they aren't a part of the DT bindings. See
+ [3] for more info on the data-lanes property.
+
+ For example:
+
+ data-lanes = <3 0 1 2>;
+
+ The above mapping describes that the logical data lane DATA0 is mapped to
+ the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
+ to phys DATA1 and logic DATA3 to phys DATA2.
+
+ There are only a limited number of physical to logical mappings possible:
+ <0 1 2 3>
+ <1 2 3 0>
+ <2 3 0 1>
+ <3 0 1 2>
+ <0 3 2 1>
+ <1 0 3 2>
+ <2 1 0 3>
+ <3 2 1 0>
+
+DSI PHY:
+Required properties:
+- compatible: Could be the following
+ * "qcom,dsi-phy-28nm-hpm"
+ * "qcom,dsi-phy-28nm-lp"
+ * "qcom,dsi-phy-20nm"
+ * "qcom,dsi-phy-28nm-8960"
+ * "qcom,dsi-phy-14nm"
+ * "qcom,dsi-phy-10nm"
+- reg: Physical base address and length of the registers of PLL, PHY. Some
+ revisions require the PHY regulator base address, whereas others require the
+ PHY lane base address. See below for each PHY revision.
+- reg-names: The names of register regions. The following regions are required:
+ For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
+ * "dsi_pll"
+ * "dsi_phy"
+ * "dsi_phy_regulator"
+ For DSI 14nm and 10nm PHYs:
+ * "dsi_pll"
+ * "dsi_phy"
+ * "dsi_phy_lane"
+- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
+ 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: Phandles to device clocks. See [1] for details on clock bindings.
+- clock-names: the following clocks are required:
+ * "iface"
+ For 28nm HPM/LP, 28nm 8960 PHYs:
+- vddio-supply: phandle to vdd-io regulator device node
+ For 20nm PHY:
+- vddio-supply: phandle to vdd-io regulator device node
+- vcca-supply: phandle to vcca regulator device node
+ For 14nm PHY:
+- vcca-supply: phandle to vcca regulator device node
+ For 10nm PHY:
+- vdds-supply: phandle to vdds regulator device node
+
+Optional properties:
+- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
+ regulator is wanted.
+- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
+ panels in microseconds. Driver uses this number to adjust
+ the clock rate according to the expected transfer time.
+ Increasing this value would slow down the mdp processing
+ and can result in slower performance.
+ Decreasing this value can speed up the mdp processing,
+ but this can also impact power consumption.
+ As a rule this time should not be higher than the time
+ that would be expected with the processing at the
+ dsi link rate since anyways this would be the maximum
+ transfer time that could be achieved.
+ If ping pong split is enabled, this time should not be higher
+ than two times the dsi link rate time.
+ If the property is not specified, then the default value is 14000 us.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/graph.txt
+[3] Documentation/devicetree/bindings/media/video-interfaces.txt
+[4] Documentation/devicetree/bindings/display/panel/
+
+Example:
+ dsi0: dsi@fd922800 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ qcom,dsi-host-index = <0>;
+ interrupt-parent = <&mdp>;
+ interrupts = <4 0>;
+ reg-names = "dsi_ctrl";
+ reg = <0xfd922800 0x200>;
+ power-domains = <&mmcc MDSS_GDSC>;
+ clock-names =
+ "bus",
+ "byte",
+ "core",
+ "core_mmss",
+ "iface",
+ "mdp_core",
+ "pixel";
+ clocks =
+ <&mmcc MDSS_AXI_CLK>,
+ <&mmcc MDSS_BYTE0_CLK>,
+ <&mmcc MDSS_ESC0_CLK>,
+ <&mmcc MMSS_MISC_AHB_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_MDP_CLK>,
+ <&mmcc MDSS_PCLK0_CLK>;
+
+ assigned-clocks =
+ <&mmcc BYTE0_CLK_SRC>,
+ <&mmcc PCLK0_CLK_SRC>;
+ assigned-clock-parents =
+ <&dsi_phy0 0>,
+ <&dsi_phy0 1>;
+
+ vdda-supply = <&pma8084_l2>;
+ vdd-supply = <&pma8084_l22>;
+ vddio-supply = <&pma8084_l12>;
+
+ phys = <&dsi_phy0>;
+ phy-names ="dsi-phy";
+
+ qcom,dual-dsi-mode;
+ qcom,master-dsi;
+ qcom,sync-dual-dsi;
+
+ qcom,mdss-mdp-transfer-time-us = <12000>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dsi_active>;
+ pinctrl-1 = <&dsi_suspend>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+
+ panel: panel@0 {
+ compatible = "sharp,lq101r1sx01";
+ reg = <0>;
+ link2 = <&secondary>;
+
+ power-supply = <...>;
+ backlight = <...>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+
+ dsi_phy0: dsi-phy@fd922a00 {
+ compatible = "qcom,dsi-phy-28nm-hpm";
+ qcom,dsi-phy-index = <0>;
+ reg-names =
+ "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+ reg = <0xfd922a00 0xd4>,
+ <0xfd922b00 0x2b0>,
+ <0xfd922d80 0x7b>;
+ clock-names = "iface";
+ clocks = <&mmcc MDSS_AHB_CLK>;
+ #clock-cells = <1>;
+ vddio-supply = <&pma8084_l12>;
+
+ qcom,dsi-phy-regulator-ldo-mode;
+ qcom,panel-allow-phy-poweroff;
+ qcom,dsi-phy-regulator-min-datarate-bps = <1200000000>;
+ qcom,panel-force-clock-lane-hs;
+ };
diff --git a/bindings/edp.txt b/bindings/edp.txt
new file mode 100644
index 0000000..186ee23
--- /dev/null
+++ b/bindings/edp.txt
@@ -0,0 +1,56 @@
+Qualcomm Technologies Inc. snapdragon eDP output
+
+Required properties:
+- compatible:
+ * "qcom,mdss-edp"
+- reg: Physical base address and length of the registers of controller and PLL
+- reg-names: The names of register regions. The following regions are required:
+ * "edp"
+ * "pll_base"
+- interrupts: The interrupt signal from the eDP block.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: the following clocks are required:
+ * "core"
+ * "iface"
+ * "mdp_core"
+ * "pixel"
+ * "link"
+- #clock-cells: The value should be 1.
+- vdda-supply: phandle to vdda regulator device node
+- lvl-vdd-supply: phandle to regulator device node which is used to supply power
+ to HPD receiving chip
+- panel-en-gpios: GPIO pin to supply power to panel.
+- panel-hpd-gpios: GPIO pin used for eDP hpd.
+
+
+Example:
+ mdss_edp: qcom,mdss_edp@fd923400 {
+ compatible = "qcom,mdss-edp";
+ reg-names =
+ "edp",
+ "pll_base";
+ reg = <0xfd923400 0x700>,
+ <0xfd923a00 0xd4>;
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <12 0>;
+ power-domains = <&mmcc MDSS_GDSC>;
+ clock-names =
+ "core",
+ "pixel",
+ "iface",
+ "link",
+ "mdp_core";
+ clocks =
+ <&mmcc MDSS_EDPAUX_CLK>,
+ <&mmcc MDSS_EDPPIXEL_CLK>,
+ <&mmcc MDSS_AHB_CLK>,
+ <&mmcc MDSS_EDPLINK_CLK>,
+ <&mmcc MDSS_MDP_CLK>;
+ #clock-cells = <1>;
+ vdda-supply = <&pma8084_l12>;
+ lvl-vdd-supply = <&lvl_vreg>;
+ panel-en-gpios = <&tlmm 137 0>;
+ panel-hpd-gpios = <&tlmm 103 0>;
+ };
diff --git a/bindings/hdmi.txt b/bindings/hdmi.txt
new file mode 100644
index 0000000..66a123b
--- /dev/null
+++ b/bindings/hdmi.txt
@@ -0,0 +1,99 @@
+Qualcomm Technologies, Inc. adreno/snapdragon hdmi output
+
+Required properties:
+- compatible: one of the following
+ * "qcom,hdmi-tx-8996"
+ * "qcom,hdmi-tx-8994"
+ * "qcom,hdmi-tx-8084"
+ * "qcom,hdmi-tx-8974"
+ * "qcom,hdmi-tx-8660"
+ * "qcom,hdmi-tx-8960"
+- reg: Physical base address and length of the controller's registers
+- reg-names: "core_physical"
+- interrupts: The interrupt signal from the hdmi block.
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: device clocks
+ See ../clocks/clock-bindings.txt for details.
+- core-vdda-supply: phandle to supply regulator
+- hdmi-mux-supply: phandle to mux regulator
+- phys: the phandle for the HDMI PHY device
+- phy-names: the name of the corresponding PHY device
+
+Optional properties:
+- hpd-gpios: hpd pin
+- qcom,hdmi-tx-mux-en-gpios: hdmi mux enable pin
+- qcom,hdmi-tx-mux-sel-gpios: hdmi mux select pin
+- qcom,hdmi-tx-mux-lpm-gpios: hdmi mux lpm pin
+- power-domains: reference to the power domain(s), if available.
+- pinctrl-names: the pin control state names; should contain "default"
+- pinctrl-0: the default pinctrl state (active)
+- pinctrl-1: the "sleep" pinctrl state
+
+HDMI PHY:
+Required properties:
+- compatible: Could be the following
+ * "qcom,hdmi-phy-8660"
+ * "qcom,hdmi-phy-8960"
+ * "qcom,hdmi-phy-8974"
+ * "qcom,hdmi-phy-8084"
+ * "qcom,hdmi-phy-8996"
+- #phy-cells: Number of cells in a PHY specifier; Should be 0.
+- reg: Physical base address and length of the registers of the PHY sub blocks.
+- reg-names: The names of register regions. The following regions are required:
+ * "hdmi_phy"
+ * "hdmi_pll"
+ For HDMI PHY on msm8996, these additional register regions are required:
+ * "hdmi_tx_l0"
+ * "hdmi_tx_l1"
+ * "hdmi_tx_l3"
+ * "hdmi_tx_l4"
+- power-domains: Should be <&mmcc MDSS_GDSC>.
+- clocks: device clocks
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- core-vdda-supply: phandle to vdda regulator device node
+
+Example:
+
+/ {
+ ...
+
+ hdmi: hdmi@4a00000 {
+ compatible = "qcom,hdmi-tx-8960";
+ reg-names = "core_physical";
+ reg = <0x04a00000 0x2f0>;
+ interrupts = <GIC_SPI 79 0>;
+ power-domains = <&mmcc MDSS_GDSC>;
+ clock-names =
+ "core",
+ "master_iface",
+ "slave_iface";
+ clocks =
+ <&mmcc HDMI_APP_CLK>,
+ <&mmcc HDMI_M_AHB_CLK>,
+ <&mmcc HDMI_S_AHB_CLK>;
+ qcom,hdmi-tx-ddc-clk = <&msmgpio 70 GPIO_ACTIVE_HIGH>;
+ qcom,hdmi-tx-ddc-data = <&msmgpio 71 GPIO_ACTIVE_HIGH>;
+ qcom,hdmi-tx-hpd = <&msmgpio 72 GPIO_ACTIVE_HIGH>;
+ core-vdda-supply = <&pm8921_hdmi_mvs>;
+ hdmi-mux-supply = <&ext_3p3v>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&hpd_active &ddc_active &cec_active>;
+ pinctrl-1 = <&hpd_suspend &ddc_suspend &cec_suspend>;
+
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi_phy";
+ };
+
+ hdmi_phy: phy@4a00400 {
+ compatible = "qcom,hdmi-phy-8960";
+ reg-names = "hdmi_phy",
+ "hdmi_pll";
+ reg = <0x4a00400 0x60>,
+ <0x4a00500 0x100>;
+ #phy-cells = <0>;
+ power-domains = <&mmcc MDSS_GDSC>;
+ clock-names = "slave_iface";
+ clocks = <&mmcc HDMI_S_AHB_CLK>;
+ core-vdda-supply = <&pm8921_hdmi_mvs>;
+ };
+};
diff --git a/bindings/mdp4.txt b/bindings/mdp4.txt
new file mode 100644
index 0000000..1d9cf35
--- /dev/null
+++ b/bindings/mdp4.txt
@@ -0,0 +1,112 @@
+Qualcomm Technologies, Inc. adreno/snapdragon MDP4 display controller
+
+Description:
+
+This is the bindings documentation for the MDP4 display controller found in
+SoCs like MSM8960, APQ8064 and MSM8660.
+
+Required properties:
+- compatible:
+ * "qcom,mdp4" - mdp4
+- reg: Physical base address and length of the controller's registers.
+- interrupts: The interrupt signal from the display controller.
+- clocks: device clocks
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required.
+ * "core_clk"
+ * "iface_clk"
+ * "bus_clk"
+ * "lut_clk"
+ * "hdmi_clk"
+ * "tv_clk"
+- ports: contains the list of output ports from MDP. These connect to interfaces
+ that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
+ special case since it is a part of the MDP block itself).
+
+ Each output port contains an endpoint that describes how it is connected to an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ The output port mappings are:
+ Port 0 -> LCDC/LVDS
+ Port 1 -> DSI1 Cmd/Video
+ Port 2 -> DSI2 Cmd/Video
+ Port 3 -> DTV
+
+Optional properties:
+- clock-names: the following clocks are optional:
+ * "lut_clk"
+
+Example:
+
+/ {
+ ...
+
+ hdmi: hdmi@4a00000 {
+ ...
+ ports {
+ ...
+ port@0 {
+ reg = <0>;
+ hdmi_in: endpoint {
+ remote-endpoint = <&mdp_dtv_out>;
+ };
+ };
+ ...
+ };
+ ...
+ };
+
+ ...
+
+ mdp: mdp@5100000 {
+ compatible = "qcom,mdp4";
+ reg = <0x05100000 0xf0000>;
+ interrupts = <GIC_SPI 75 0>;
+ clock-names =
+ "core_clk",
+ "iface_clk",
+ "lut_clk",
+ "hdmi_clk",
+ "tv_clk";
+ clocks =
+ <&mmcc MDP_CLK>,
+ <&mmcc MDP_AHB_CLK>,
+ <&mmcc MDP_AXI_CLK>,
+ <&mmcc MDP_LUT_CLK>,
+ <&mmcc HDMI_TV_CLK>,
+ <&mmcc MDP_TV_CLK>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp_lvds_out: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ mdp_dsi1_out: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ mdp_dsi2_out: endpoint {
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ mdp_dtv_out: endpoint {
+ remote-endpoint = <&hdmi_in>;
+ };
+ };
+ };
+ };
+};
diff --git a/bindings/mdp5.txt b/bindings/mdp5.txt
new file mode 100644
index 0000000..fcad35c
--- /dev/null
+++ b/bindings/mdp5.txt
@@ -0,0 +1,158 @@
+Qualcomm Technologies, Inc. adreno/snapdragon MDP5 display controller
+
+Description:
+
+This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
+encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
+controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
+
+MDSS:
+Required properties:
+- compatible:
+ * "qcom,mdss" - MDSS
+- reg: Physical base address and length of the controller's registers.
+- reg-names: The names of register regions. The following regions are required:
+ * "mdss_phys"
+ * "vbif_phys"
+- interrupts: The interrupt signal from MDSS.
+- interrupt-controller: identifies the node as an interrupt controller.
+- #interrupt-cells: specifies the number of cells needed to encode an interrupt
+ source, should be 1.
+- power-domains: a power domain consumer specifier according to
+ Documentation/devicetree/bindings/power/power_domain.txt
+- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required.
+ * "iface"
+ * "bus"
+ * "vsync"
+- #address-cells: number of address cells for the MDSS children. Should be 1.
+- #size-cells: Should be 1.
+- ranges: parent bus address space is the same as the child bus address space.
+
+Optional properties:
+- clock-names: the following clocks are optional:
+ * "lut"
+
+MDP5:
+Required properties:
+- compatible:
+ * "qcom,mdp5" - MDP5
+- reg: Physical base address and length of the controller's registers.
+- reg-names: The names of register regions. The following regions are required:
+ * "mdp_phys"
+- interrupts: Interrupt line from MDP5 to MDSS interrupt controller.
+- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
+- clock-names: the following clocks are required.
+- * "bus"
+- * "iface"
+- * "core"
+- * "vsync"
+- ports: contains the list of output ports from MDP. These connect to interfaces
+ that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
+ special case since it is a part of the MDP block itself).
+
+ Each output port contains an endpoint that describes how it is connected to an
+ external interface. These are described by the standard properties documented
+ here:
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ The availability of output ports can vary across SoC revisions:
+
+ For MSM8974 and APQ8084:
+ Port 0 -> MDP_INTF0 (eDP)
+ Port 1 -> MDP_INTF1 (DSI1)
+ Port 2 -> MDP_INTF2 (DSI2)
+ Port 3 -> MDP_INTF3 (HDMI)
+
+ For MSM8916:
+ Port 0 -> MDP_INTF1 (DSI1)
+
+ For MSM8994 and MSM8996:
+ Port 0 -> MDP_INTF1 (DSI1)
+ Port 1 -> MDP_INTF2 (DSI2)
+ Port 2 -> MDP_INTF3 (HDMI)
+
+Optional properties:
+- clock-names: the following clocks are optional:
+ * "lut"
+
+Example:
+
+/ {
+ ...
+
+ mdss: mdss@1a00000 {
+ compatible = "qcom,mdss";
+ reg = <0x1a00000 0x1000>,
+ <0x1ac8000 0x3000>;
+ reg-names = "mdss_phys", "vbif_phys";
+
+ power-domains = <&gcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "vsync"
+
+ interrupts = <0 72 0>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ mdp: mdp@1a01000 {
+ compatible = "qcom,mdp5";
+ reg = <0x1a01000 0x90000>;
+ reg-names = "mdp_phys";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0 0>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface",
+ "bus",
+ "core",
+ "vsync";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdp5_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+ };
+
+ dsi0: dsi@1a98000 {
+ ...
+ ports {
+ ...
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&mdp5_intf1_out>;
+ };
+ };
+ ...
+ };
+ ...
+ };
+
+ dsi_phy0: dsi-phy@1a98300 {
+ ...
+ };
+ };
+};
diff --git a/bindings/mdss-dsi-panel.txt b/bindings/mdss-dsi-panel.txt
new file mode 100644
index 0000000..338ea8d
--- /dev/null
+++ b/bindings/mdss-dsi-panel.txt
@@ -0,0 +1,810 @@
+QTI mdss-dsi-panel
+
+mdss-dsi-panel is a dsi panel device which supports panels that
+are compatible with MIPI display serial interface specification.
+
+Required properties:
+- compatible: This property applies to DSI V2 panels only.
+ This property should not be added for panels
+ that work based on version "V6.0"
+ DSI panels that are of different versions
+ are initialized by the drivers for dsi controller.
+ This property specifies the version
+ for DSI HW that this panel will work with
+ "qcom,dsi-panel-v2" = DSI V2.0
+- status: This property applies to DSI V2 panels only.
+ This property should not be added for panels
+ that work based on version "V6.0"
+ DSI panels that are of different versions
+ are initialized by the drivers for dsi controller.
+ A string that has to be set to "okay/ok"
+ to enable the panel driver. By default this property
+ will be set to "disable". Will be set to "ok/okay"
+ status for specific platforms.
+- qcom,mdss-dsi-panel-controller: Specifies the phandle for the DSI controller that
+ this panel will be mapped to.
+- qcom,mdss-dsi-panel-width: Specifies panel width in pixels.
+- qcom,mdss-dsi-panel-height: Specifies panel height in pixels.
+- qcom,mdss-dsi-bpp: Specifies the panel bits per pixel.
+ 3 = for rgb111
+ 8 = for rgb332
+ 12 = for rgb444
+ 16 = for rgb565
+ 18 = for rgb666
+ 24 = for rgb888
+- qcom,mdss-dsi-panel-destination: A string that specifies the destination display for the panel.
+ "display_1" = DISPLAY_1
+ "display_2" = DISPLAY_2
+- qcom,mdss-dsi-panel-timings: An array of length 12 that specifies the PHY
+ timing settings for the panel.
+- qcom,mdss-dsi-panel-timings-8996: An array of length 40 char that specifies the 8996 PHY lane
+ timing settings for the panel.
+- qcom,mdss-dsi-on-command: A byte stream formed by multiple dcs packets base on
+ qcom dsi controller protocol.
+ byte 0: dcs data type
+ byte 1: set to indicate this is an individual packet
+ (no chain)
+ byte 2: virtual channel number
+ byte 3: expect ack from client (dcs read command)
+ byte 4: wait number of specified ms after dcs command
+ transmitted
+ byte 5, 6: 16 bits length in network byte order
+ byte 7 and beyond: number byte of payload
+- qcom,mdss-dsi-off-command: A byte stream formed by multiple dcs packets base on
+ qcom dsi controller protocol.
+ byte 0: dcs data type
+ byte 1: set to indicate this is an individual packet
+ (no chain)
+ byte 2: virtual channel number
+ byte 3: expect ack from client (dcs read command)
+ byte 4: wait number of specified ms after dcs command
+ transmitted
+ byte 5, 6: 16 bits length in network byte order
+ byte 7 and beyond: number byte of payload
+- qcom,mdss-dsi-post-panel-on-command: same as "qcom,mdss-dsi-on-command" except commands are
+ sent after displaying an image.
+
+Note, if a short DCS packet(i.e packet with Byte 0:dcs data type as 05) mentioned in
+qcom,mdss-dsi-on-command/qcom,mdss-dsi-off-command stream fails to transmit,
+then 3 options can be tried.
+ 1. Send the packet as a long packet instead
+ Byte 0: dcs data type = 05 (DCS short Packet)
+ Byte 0: dcs data type = 29 (DCS long Packet)
+ 2. Send the packet in one burst by prepending with the next packet in packet stream
+ Byte 1 = 01 (indicates this is an individual packet)
+ Byte 1 = 00 (indicates this will be appended to the next
+ individual packet in the packet stream)
+ 3. Prepend a NULL packet to the short packet and send both in one burst instead of
+ combining multiple short packets and sending them in one burst.
+
+Optional properties:
+- qcom,mdss-dsi-panel-name: A string used as a descriptive name of the panel
+- qcom,mdss-dsi-panel-phy-timings: An array of length 'n' char that specifies the DSI PHY lane
+ timing settings for the panel. This is specific to SDE DRM driver.
+ The value of 'n' depends on the DSI PHY h/w revision and parsing this
+ property properly will be taken care in the DSI PHY DRM driver.
+- qcom,cmd-sync-wait-broadcast: Boolean used to broadcast dcs command to panels.
+- qcom,mdss-dsi-fbc-enable: Boolean used to enable frame buffer compression mode.
+- qcom,mdss-dsi-panel-mode-switch: Boolean used to enable panel operating mode switch.
+- qcom,mdss-dsi-fbc-slice-height: Slice height(in lines) of compressed block.
+ Expressed as power of 2. To set as 128 lines,
+ this should be set to 7.
+- qcom,mdss-dsi-fbc-2d-pred-mode: Boolean to enable 2D map prediction.
+- qcom,mdss-dsi-fbc-ver2-mode: Boolean to enable FBC 2.0 that supports 1/3
+ compression.
+- qcom,mdss-dsi-fbc-bpp: Compressed bpp supported by the panel.
+ Specified color order is used as default value.
+- qcom,mdss-dsi-fbc-packing: Component packing.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-quant-error: Boolean used to enable quantization error calculation.
+- qcom,mdss-dsi-fbc-bias: Bias for CD.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-pat-mode: Boolean used to enable PAT mode.
+- qcom,mdss-dsi-fbc-vlc-mode: Boolean used to enable VLC mode.
+- qcom,mdss-dsi-fbc-bflc-mode: Boolean used to enable BFLC mode.
+- qcom,mdss-dsi-fbc-h-line-budget: Per line extra budget.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-budget-ctrl: Extra budget level.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-block-budget: Per block budget.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-lossless-threshold: Lossless mode threshold.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-lossy-threshold: Lossy mode threshold.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-rgb-threshold: Lossy RGB threshold.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-lossy-mode-idx: Lossy mode index value.
+ 0 = default value.
+- qcom,mdss-dsi-fbc-max-pred-err: Max quantization prediction error.
+ 0 = default value
+- qcom,mdss-dsi-h-back-porch: Horizontal back porch value in pixel.
+ 6 = default value.
+- qcom,mdss-dsi-h-front-porch: Horizontal front porch value in pixel.
+ 6 = default value.
+- qcom,mdss-dsi-h-pulse-width: Horizontal pulse width.
+ 2 = default value.
+- qcom,mdss-dsi-h-sync-skew: Horizontal sync skew value.
+ 0 = default value.
+- qcom,mdss-dsi-v-back-porch: Vertical back porch value in pixel.
+ 6 = default value.
+- qcom,mdss-dsi-v-front-porch: Vertical front porch value in pixel.
+ 6 = default value.
+- qcom,mdss-dsi-v-pulse-width: Vertical pulse width.
+ 2 = default value.
+- qcom,mdss-dsi-h-left-border: Horizontal left border in pixel.
+ 0 = default value
+- qcom,mdss-dsi-h-right-border: Horizontal right border in pixel.
+ 0 = default value
+- qcom,mdss-dsi-v-top-border: Vertical top border in pixel.
+ 0 = default value
+- qcom,mdss-dsi-v-bottom-border: Vertical bottom border in pixel.
+ 0 = default value
+- qcom,mdss-dsi-underflow-color: Specifies the controller settings for the
+ panel under flow color.
+ 0xff = default value.
+- qcom,mdss-dsi-border-color: Defines the border color value if border is present.
+ 0 = default value.
+- qcom,mdss-dsi-panel-jitter: Panel jitter value is expressed in terms of numerator
+ and denominator. It contains two u32 values - numerator
+ followed by denominator. The jitter configurition causes
+ the early wakeup if panel needs to adjust before vsync.
+ Default jitter value is 2.0%. Max allowed value is 10%.
+- qcom,mdss-dsi-panel-prefill-lines: An integer value defines the panel prefill lines required to
+ calculate the backoff time of rsc.
+ Default value is 16 lines. Max allowed value is vtotal.
+- qcom,mdss-dsi-pan-enable-dynamic-fps: Boolean used to enable change in frame rate dynamically.
+- qcom,mdss-dsi-pan-fps-update: A string that specifies when to change the frame rate.
+ "dfps_suspend_resume_mode"= FPS change request is
+ implemented during suspend/resume.
+ "dfps_immediate_clk_mode" = FPS change request is
+ implemented immediately using DSI clocks.
+ "dfps_immediate_porch_mode_hfp" = FPS change request is
+ implemented immediately by changing panel horizontal
+ front porch values.
+ "dfps_immediate_porch_mode_vfp" = FPS change request is
+ implemented immediately by changing panel vertical
+ front porch values.
+- qcom,min-refresh-rate: Minimum refresh rate supported by the panel.
+- qcom,max-refresh-rate: Maximum refresh rate supported by the panel. If max refresh
+ rate is not specified, then the frame rate of the panel in
+ qcom,mdss-dsi-panel-framerate is used.
+- qcom,mdss-dsi-bl-pmic-control-type: A string that specifies the implementation of backlight
+ control for this panel.
+ "bl_ctrl_pwm" = Backlight controlled by PWM gpio.
+ "bl_ctrl_wled" = Backlight controlled by WLED.
+ "bl_ctrl_dcs" = Backlight controlled by DCS commands.
+ "bl_ctrl_external" = Backlight controlled by externally
+ other: Unknown backlight control. (default)
+- qcom,mdss-dsi-sec-bl-pmic-control-type: A string that specifies the implementation of backlight
+ control for secondary panel.
+ "bl_ctrl_pwm" = Backlight controlled by PWM gpio.
+ "bl_ctrl_wled" = Backlight controlled by WLED.
+ "bl_ctrl_dcs" = Backlight controlled by DCS commands.
+ "bl_ctrl_external" = Backlight controlled by externally
+ other: Unknown backlight control. (default)
+- qcom,mdss-dsi-bl-pwm-pmi: Boolean to indicate that PWM control is through second pmic chip.
+- qcom,mdss-dsi-bl-pmic-bank-select: LPG channel for backlight.
+ Required if backlight pmic control type is PWM
+- qcom,mdss-dsi-bl-pmic-pwm-frequency: PWM period in microseconds.
+ Required if backlight pmic control type is PWM
+- qcom,mdss-dsi-pwm-gpio: PMIC gpio binding to backlight.
+ Required if backlight pmic control type is PWM
+- qcom,mdss-dsi-bl-min-level: Specifies the min backlight level supported by the panel.
+ 0 = default value.
+- qcom,mdss-dsi-bl-max-level: Specifies the max backlight level supported by the panel.
+ 255 = default value.
+- qcom,mdss-brightness-max-level: Specifies the max brightness level supported.
+ 255 = default value.
+- qcom,bl-update-flag: A string that specifies controls for backlight update of the panel.
+ "delay_until_first_frame" = Delay backlight update of the panel
+ until the first frame is received from the HW.
+- qcom,mdss-dsi-interleave-mode: Specifies interleave mode.
+ 0 = default value.
+- qcom,mdss-dsi-panel-type: Specifies the panel operating mode.
+ "dsi_video_mode" = enable video mode (default).
+ "dsi_cmd_mode" = enable command mode.
+- qcom,5v-boost-gpio: Specifies the panel gpio for display 5v boost.
+- qcom,mdss-dsi-te-check-enable: Boolean to enable Tear Check configuration.
+- qcom,mdss-dsi-te-using-wd: Boolean entry enables the watchdog timer support to generate the vsync signal
+ for command mode panel. By default, panel TE will be used to generate the vsync.
+- qcom,mdss-dsi-te-using-te-pin: Boolean to specify whether using hardware vsync.
+- qcom,mdss-dsi-qsync-min-refresh-rate: A u32 entry to specify minimum refresh rate supported by the panel to enable qsync feature.
+- qcom,mdss-dsi-qsync-on-commands: String that specifies the commands to enable qsync feature.
+- qcom,mdss-dsi-qsync-on-commands-state: String that specifies the ctrl state for sending qsync on commands.
+ "dsi_lp_mode" = DSI low power mode (default)
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-dsi-qsync-off-commands: String that specifies the commands to disable qsync feature.
+- qcom,mdss-dsi-qsync-off-commands-state: String that specifies the ctrl state for sending qsync off commands.
+ "dsi_lp_mode" = DSI low power mode (default)
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-dsi-te-pin-select: Specifies TE operating mode.
+ 0 = TE through embedded dcs command
+ 1 = TE through TE gpio pin. (default)
+- qcom,mdss-dsi-te-dcs-command: Inserts the dcs command.
+ 1 = default value.
+- qcom,mdss-dsi-wr-mem-start: DCS command for write_memory_start.
+ 0x2c = default value.
+- qcom,mdss-dsi-wr-mem-continue: DCS command for write_memory_continue.
+ 0x3c = default value.
+- qcom,mdss-dsi-h-sync-pulse: Specifies the pulse mode option for the panel.
+ 0 = Don't send hsa/he following vs/ve packet(default)
+ 1 = Send hsa/he following vs/ve packet
+- qcom,mdss-dsi-hfp-power-mode: Boolean to determine DSI lane state during
+ horizontal front porch (HFP) blanking period.
+- qcom,mdss-dsi-hbp-power-mode: Boolean to determine DSI lane state during
+ horizontal back porch (HBP) blanking period.
+- qcom,mdss-dsi-hsa-power-mode: Boolean to determine DSI lane state during
+ horizontal sync active (HSA) mode.
+- qcom,mdss-dsi-last-line-interleave Boolean to determine if last line
+ interleave flag needs to be enabled.
+- qcom,mdss-dsi-bllp-eof-power-mode: Boolean to determine DSI lane state during
+ blanking low power period (BLLP) EOF mode.
+- qcom,mdss-dsi-bllp-power-mode: Boolean to determine DSI lane state during
+ blanking low power period (BLLP) mode.
+- qcom,mdss-dsi-traffic-mode: Specifies the panel traffic mode.
+ "non_burst_sync_pulse" = non burst with sync pulses (default).
+ "non_burst_sync_event" = non burst with sync start event.
+ "burst_mode" = burst mode.
+- qcom,mdss-dsi-pixel-packing: Specifies if pixel packing is used (in case of RGB666).
+ "tight" = Tight packing (default value).
+ "loose" = Loose packing.
+- qcom,mdss-dsi-virtual-channel-id: Specifies the virtual channel identefier.
+ 0 = default value.
+- qcom,mdss-dsi-color-order: Specifies the R, G and B channel ordering.
+ "rgb_swap_rgb" = DSI_RGB_SWAP_RGB (default value)
+ "rgb_swap_rbg" = DSI_RGB_SWAP_RBG
+ "rgb_swap_brg" = DSI_RGB_SWAP_BRG
+ "rgb_swap_grb" = DSI_RGB_SWAP_GRB
+ "rgb_swap_gbr" = DSI_RGB_SWAP_GBR
+- qcom,mdss-dsi-lane-0-state: Boolean that specifies whether data lane 0 is enabled.
+- qcom,mdss-dsi-lane-1-state: Boolean that specifies whether data lane 1 is enabled.
+- qcom,mdss-dsi-lane-2-state: Boolean that specifies whether data lane 2 is enabled.
+- qcom,mdss-dsi-lane-3-state: Boolean that specifies whether data lane 3 is enabled.
+- qcom,mdss-dsi-t-clk-post: Specifies the byte clock cycles after mode switch.
+ 0x00 = default value.
+- qcom,mdss-dsi-t-clk-pre: Specifies the byte clock cycles before mode switch.
+ 0x00 = default value.
+- qcom,mdss-dsi-stream: Specifies the packet stream to be used.
+ 0 = stream 0 (default)
+ 1 = stream 1
+- qcom,mdss-dsi-mdp-trigger: Specifies the trigger mechanism to be used for MDP path.
+ "none" = no trigger
+ "trigger_te" = Tear check signal line used for trigger
+ "trigger_sw" = Triggered by software (default)
+ "trigger_sw_te" = Software trigger and TE
+- qcom,mdss-dsi-dma-trigger: Specifies the trigger mechanism to be used for DMA path.
+ "none" = no trigger
+ "trigger_te" = Tear check signal line used for trigger
+ "trigger_sw" = Triggered by software (default)
+ "trigger_sw_seof" = Software trigger and start/end of frame trigger.
+ "trigger_sw_te" = Software trigger and TE
+- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel.
+ 60 = 60 frames per second (default)
+- qcom,mdss-dsi-panel-clockrate: A 64 bit value specifies the panel clock speed in Hz.
+ 0 = default value.
+- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
+ panels in microseconds. Driver uses this number to adjust
+ the clock rate according to the expected transfer time.
+ Increasing this value would slow down the mdp processing
+ and can result in slower performance.
+ Decreasing this value can speed up the mdp processing,
+ but this can also impact power consumption.
+ As a rule this time should not be higher than the time
+ that would be expected with the processing at the
+ dsi link rate since anyways this would be the maximum
+ transfer time that could be achieved.
+ If ping pong split enabled, this time should not be higher
+ than two times the dsi link rate time.
+ 14000 = default value.
+- qcom,mdss-dsi-on-command-state: String that specifies the ctrl state for sending ON commands.
+ "dsi_lp_mode" = DSI low power mode (default)
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-dsi-off-command-state: String that specifies the ctrl state for sending OFF commands.
+ "dsi_lp_mode" = DSI low power mode (default)
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-dsi-post-mode-switch-on-command-state: String that specifies the ctrl state for sending ON commands post mode switch.
+ "dsi_lp_mode" = DSI low power mode (default)
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-pan-physical-width-dimension: Specifies panel physical width in mm which corresponds
+ to the physical width in the framebuffer information.
+- qcom,mdss-pan-physical-height-dimension: Specifies panel physical height in mm which corresponds
+ to the physical height in the framebuffer information.
+- qcom,mdss-dsi-mode-sel-gpio-state: String that specifies the lcd mode for panel
+ (such as single-port/dual-port), if qcom,panel-mode-gpio
+ binding is defined in dsi controller.
+ "dual_port" = Set GPIO to LOW
+ "single_port" = Set GPIO to HIGH
+ "high" = Set GPIO to HIGH
+ "low" = Set GPIO to LOW
+ The default value is "dual_port".
+- qcom,mdss-tear-check-disable: Boolean to disable mdp tear check. Tear check is enabled by default to avoid
+ tearing. Other tear-check properties are ignored if this property is present.
+ The below tear check configuration properties can be individually tuned if
+ tear check is enabled.
+- qcom,mdss-tear-check-sync-cfg-height: Specifies the vertical total number of lines.
+ The default value is 0xfff0.
+- qcom,mdss-tear-check-sync-init-val: Specifies the init value at which the read pointer gets loaded
+ at vsync edge. The reader pointer refers to the line number of
+ panel buffer that is currently being updated.
+ The default value is panel height.
+- qcom,mdss-tear-check-sync-threshold-start:
+ Allows the first ROI line write to an panel when read pointer is
+ between the range of ROI start line and ROI start line plus this
+ setting.
+ The default value is 4.
+- qcom,mdss-tear-check-sync-threshold-continue:
+ The minimum number of lines the write pointer needs to be
+ above the read pointer so that it is safe to write to the panel.
+ (This check is not done for the first ROI line write of an update)
+ The default value is 4.
+- qcom,mdss-tear-check-start-pos: Specify the y position from which the start_threshold value is
+ added and write is kicked off if the read pointer falls within that
+ region.
+ The default value is panel height.
+- qcom,mdss-tear-check-rd-ptr-trigger-intr:
+ Specify the read pointer value at which an interrupt has to be
+ generated.
+ The default value is panel height + 1.
+- qcom,mdss-tear-check-frame-rate: Specify the value to be a real frame rate(fps) x 100 factor to tune the
+ timing of TE simulation with more precision.
+ The default value is 6000 with 60 fps.
+- qcom,mdss-dsi-reset-sequence: An array that lists the
+ sequence of reset gpio values and sleeps
+ Each command will have the format defined
+ as below:
+ --> Reset GPIO value
+ --> Sleep value (in ms)
+- qcom,partial-update-enabled: String used to enable partial
+ panel update for command mode panels.
+ "none": partial update is disabled
+ "single_roi": default enable mode, only single roi is sent to panel
+ "dual_roi": two rois are merged into one big roi. Panel ddic should be able
+ to process two roi's along with the DCS command to send two rois.
+ disabled if property is not specified. This property is specified
+ per timing node to support resolution restrictions.
+- qcom,mdss-dsi-horizontal-line-idle: List of width ranges (EC - SC) in pixels indicating
+ additional idle time in dsi clock cycles that is needed
+ to compensate for smaller line width.
+- qcom,partial-update-roi-merge: Boolean indicates roi combination is need
+ and function has been provided for dcs
+ 2A/2B command. This property is specified per timing node to support
+ resolution restrictions.
+- qcom,dcs-cmd-by-left: Boolean to indicate that dcs command are sent
+ through the left DSI controller only in a dual-dsi configuration
+- qcom,mdss-dsi-panel-hdr-enabled: Boolean to indicate HDR support in panel.
+- qcom,mdss-dsi-panel-hdr-color-primaries:
+ Array of 8 unsigned integers denoting chromaticity of panel.These
+ values are specified in nits units. The value range is 0 through 50000.
+ To obtain real chromacity, these values should be divided by factor of
+ 50000. The structure of array is defined in below order
+ value 1: x value of white chromaticity of display panel
+ value 2: y value of white chromaticity of display panel
+ value 3: x value of red chromaticity of display panel
+ value 4: y value of red chromaticity of display panel
+ value 5: x value of green chromaticity of display panel
+ value 6: y value of green chromaticity of display panel
+ value 7: x value of blue chromaticity of display panel
+ value 8: y value of blue chromaticity of display panel
+- qcom,mdss-dsi-panel-peak-brightness: Maximum brightness supported by panel.In absence of maximum value
+ typical value becomes peak brightness. Value is specified in nits units.
+ To obtain real peak brightness, this value should be divided by factor of
+ 10000.
+- qcom,mdss-dsi-panel-blackness-level: Blackness level supported by panel. Blackness level is defined as
+ ratio of peak brightness to contrast. Value is specified in nits units.
+ To obtain real blackness level, this value should be divided by factor of
+ 10000.
+- qcom,mdss-dsi-lp11-init: Boolean used to enable the DSI clocks and data lanes (low power 11)
+ before issuing hardware reset line.
+- qcom,mdss-dsi-init-delay-us: Delay in microseconds(us) before performing any DSI activity in lp11
+ mode. This master delay (t_init_delay as per DSI spec) should be sum
+ of DSI internal delay to reach fuctional after power up and minimum
+ delay required by panel to reach functional.
+- qcom,mdss-dsi-rx-eot-ignore: Boolean used to enable ignoring end of transmission packets.
+- qcom,mdss-dsi-tx-eot-append: Boolean used to enable appending end of transmission packets.
+- qcom,ulps-enabled: Boolean to enable support for Ultra Low Power State (ULPS) mode.
+- qcom,suspend-ulps-enabled: Boolean to enable support for ULPS mode for panels during suspend state.
+- qcom,panel-roi-alignment: Specifies the panel ROI alignment restrictions on its
+ left, top, width, height alignments and minimum width and
+ height values. This property is specified per timing node to support
+ resolution's alignment restrictions.
+- qcom,esd-check-enabled: Boolean used to enable ESD recovery feature.
+- qcom,mdss-dsi-panel-status-command: A byte stream formed by multiple dcs packets based on
+ qcom dsi controller protocol, to read the panel status.
+ This value is used to kick in the ESD recovery.
+ byte 0: dcs data type
+ byte 1: set to indicate this is an individual packet
+ (no chain)
+ byte 2: virtual channel number
+ byte 3: expect ack from client (dcs read command)
+ byte 4: wait number of specified ms after dcs command
+ transmitted
+ byte 5, 6: 16 bits length in network byte order
+ byte 7 and beyond: number byte of payload
+- qcom,mdss-dsi-panel-status-command-mode:
+ String that specifies the ctrl state for reading the panel status.
+ "dsi_lp_mode" = DSI low power mode
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-dsi-lp1-command: An optional byte stream to request low
+ power mode on a panel
+- qcom,mdss-dsi-lp1-command-mode: String that specifies the ctrl state for
+ setting the panel power mode.
+ "dsi_lp_mode" = DSI low power mode
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-dsi-lp2-command: An optional byte stream to request ultra
+ low power mode on a panel
+- qcom,mdss-dsi-lp2-command-mode: String that specifies the ctrl state for
+ setting the panel power mode.
+ "dsi_lp_mode" = DSI low power mode
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-dsi-nolp-command: An optional byte stream to disable low
+ power and ultra low power panel modes
+- qcom,mdss-dsi-nolp-command-mode: String that specifies the ctrl state for
+ setting the panel power mode.
+ "dsi_lp_mode" = DSI low power mode
+ "dsi_hs_mode" = DSI high speed mode
+- qcom,mdss-dsi-panel-status-check-mode:Specifies the panel status check method for ESD recovery.
+ "bta_check" = Uses BTA to check the panel status
+ "reg_read" = Reads panel status register to check the panel status
+ "reg_read_nt35596" = Reads panel status register to check the panel
+ status for NT35596 panel.
+ "te_signal_check" = Uses TE signal behaviour to check the panel status
+- qcom,mdss-dsi-panel-status-read-length: Integer array that specify the expected read-back length of values
+ for each of panel registers. Each length is corresponding to number of
+ returned parameters of register introduced in specification.
+- qcom,mdss-dsi-panel-status-valid-params: Integer array that specify the valid returned values which need to check
+ for each of register.
+ Some panel need only check the first few values returned from panel.
+ So: if this property is the same to qcom,mdss-dsi-panel-status-read-length,
+ then just ignore this one.
+- qcom,mdss-dsi-panel-status-value: Multiple integer arrays, each specifies the values of the panel status register
+ which is used to check the panel status. The size of each array is the sum of
+ length specified in qcom,mdss-dsi-panel-status-read-length, and must be equal.
+ This can cover that Some panel may return several alternative values.
+- qcom,mdss-dsi-panel-max-error-count: Integer value that specifies the maximum number of errors from register
+ read that can be ignored before treating that the panel has gone bad.
+- qcom,dynamic-mode-switch-enabled: Boolean used to mention whether panel supports
+ dynamic switching from video mode to command mode
+ and vice versa.
+- qcom,dynamic-mode-switch-type: A string specifies how to perform dynamic mode switch.
+ If qcom,dynamic-mode-switch-enabled is set and no string specified, default value is
+ dynamic-switch-suspend-resume.
+ "dynamic-switch-suspend-resume"= Switch using suspend/resume. Panel will
+ go blank during transition.
+ "dynamic-switch-immediate"= Switch on next frame update. Panel will
+ not go blank for this transition.
+ "dynamic-resolution-switch-immediate"= Switch the panel resolution. Panel will
+ not go blank for this transition.
+- qcom,mdss-dsi-post-mode-switch-on-command: Multiple dcs packets used for turning on DSI panel
+ after panel has switch modes.
+ Refer to "qcom,mdss-dsi-on-command" section for adding commands.
+- qcom,video-to-cmd-mode-switch-commands: List of commands that need to be sent
+ to panel in order to switch from video mode to command mode dynamically.
+ Refer to "qcom,mdss-dsi-on-command" section for adding commands.
+- qcom,cmd-to-video-mode-switch-commands: List of commands that need to be sent
+ to panel in order to switch from command mode to video mode dynamically.
+ Refer to "qcom,mdss-dsi-on-command" section for adding commands.
+- qcom,send-pps-before-switch: Boolean propety to indicate when PPS commands should be sent,
+ either before or after switch commands during dynamic resolution
+ switch in DSC panels. If the property is not present, the default
+ behavior is to send PPS commands after the switch commands.
+- qcom,mdss-dsi-panel-orientation: String used to indicate orientation of panel
+ "180" = panel is flipped in both horizontal and vertical directions
+ "hflip" = panel is flipped in horizontal direction
+ "vflip" = panel is flipped in vertical direction
+- qcom,panel-ack-disabled: A boolean property to indicate, whether we need to wait for any ACK from the panel
+ for any commands that we send.
+- qcom,mdss-dsi-force-clock-lane-hs: Boolean to force dsi clock lanes to HS mode always.
+
+- qcom,compression-mode: Select compression mode for panel.
+ "fbc" - frame buffer compression
+ "dsc" - display stream compression.
+ If "dsc" compression is used then config subnodes needs to be defined.
+- qcom,panel-supply-entries: A node that lists the elements of the supply used to
+ power the DSI panel. There can be more than one instance
+ of this binding, in which case the entry would be appended
+ with the supply entry index. For a detailed description of
+ fields in the supply entry, refer to the qcom,ctrl-supply-entries
+ binding above.
+- qcom,mdss-dsc-version: An 8 bit value indicates the DSC version supported by panel. Bits[0.3]
+ provides information about minor version while Bits[4.7] provides
+ major version information. It supports only DSC rev 1(Major).1(Minor)
+ right now.
+- qcom,mdss-dsc-scr-version: Each DSC version can have multiple SCR. This 8 bit value indicates
+ current SCR revision information supported by panel.
+- qcom,mdss-dsc-encoders: An integer value indicating how many DSC encoders should be used
+ to drive data stream to DSI.
+ Default value is 1 and max value is 2.
+ 2 encoder should be used only if qcom,mdss-lm-split or
+ qcom,split-mode with pingpong-split is used.
+- qcom,mdss-dsc-slice-height: An integer value indicates the dsc slice height.
+- qcom,mdss-dsc-slice-width: An integer value indicates the dsc slice width.
+ Multiple of slice width should be equal to panel-width.
+ Maximum 2 slices per DSC encoder can be used so if 2 DSC encoders
+ are used then minimum slice width is equal to panel-width/4.
+- qcom,mdss-dsc-slice-per-pkt: An integer value indicates the slice per dsi packet.
+- qcom,mdss-dsc-bit-per-component: An integer value indicates the bits per component before compression.
+- qcom,mdss-dsc-bit-per-pixel: An integer value indicates the bits per pixel after compression.
+- qcom,mdss-dsc-block-prediction-enable: A boolean value to enable/disable the block prediction at decoder.
+- qcom,mdss-dsc-config-by-manufacture-cmd: A boolean to indicates panel use manufacture command to setup pps
+ instead of standard dcs type 0x0A.
+- qcom,display-topology: Array of u32 values which specifies the list of topologies available
+ for the display. A display topology is defined by a
+ set of 3 values in the order:
+ - number of mixers
+ - number of compression encoders
+ - number of interfaces
+ Therefore, the array should always contain a tuple of 3 elements.
+- qcom,default-topology-index: An u32 value which indexes the topology set
+ specified by the node "qcom,display-topology"
+ to identify the default topology for the
+ display. The first set is indexed by the
+ value 0.
+- qcom,mdss-dsi-ext-bridge-mode: External bridge chip is connected instead of panel.
+- qcom,mdss-dsi-dma-schedule-line: An integer value indicates the line number after vertical active
+ region, at which command DMA needs to be triggered.
+
+Required properties for sub-nodes: None
+Optional properties:
+- qcom,dba-panel: Indicates whether the current panel is used as a display bridge
+ to a non-DSI interface.
+- qcom,bridge-name: A string to indicate the name of the bridge chip connected to DSI. qcom,bridge-name
+ is required if qcom,dba-panel is defined for the panel.
+- qcom,adjust-timer-wakeup-ms: An integer value to indicate the timer delay(in ms) to accommodate
+ s/w delay while configuring the event timer wakeup logic.
+
+- qcom,mdss-dsi-display-timings: Parent node that lists the different resolutions that the panel supports.
+ Each child represents timings settings for a specific resolution.
+- qcom,mdss-dsi-post-init-delay: Specifies required number of frames to wait so that panel can be functional
+ to show proper display.
+- qcom,mdss-dsi-video-mode: A boolean to indicates current timing can only work in video mode.
+- qcom,mdss-dsi-cmd-mode: A boolean to indicates current timing can only work in command mode.
+
+Additional properties added to the second level nodes that represent timings properties:
+- qcom,mdss-dsi-timing-default: Property that specifies the current child as the default
+ timing configuration that will be used.
+- qcom,mdss-dsi-timing-switch-command: List of commands that need to be sent
+ to panel when the resolution/timing switch happens dynamically.
+ Refer to "qcom,mdss-dsi-on-command" section for adding commands.
+- qcom,mdss-dsi-timing-switch-command-state: String that specifies the ctrl state for sending resolution switch
+ commands.
+ "dsi_lp_mode" = DSI low power mode (default)
+ "dsi_hs_mode" = DSI high speed mode
+
+Note, if a given optional qcom,* binding is not present, then the driver will configure
+the default values specified.
+
+Example:
+&mdss_mdp {
+ dsi_sim_vid: qcom,mdss_dsi_sim_video {
+ qcom,mdss-dsi-panel-name = "simulator video mode dsi panel";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-pixel-packing = <0>;
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-fbc-enable;
+ qcom,mdss-dsi-panel-mode-switch;
+ qcom,mdss-dsi-fbc-slice-height = <5>;
+ qcom,mdss-dsi-fbc-2d-pred-mode;
+ qcom,mdss-dsi-fbc-ver2-mode;
+ qcom,mdss-dsi-fbc-bpp = <0>;
+ qcom,mdss-dsi-fbc-packing = <0>;
+ qcom,mdss-dsi-fbc-quant-error;
+ qcom,mdss-dsi-fbc-bias = <0>;
+ qcom,mdss-dsi-fbc-pat-mode;
+ qcom,mdss-dsi-fbc-vlc-mode;
+ qcom,mdss-dsi-fbc-bflc-mode;
+ qcom,mdss-dsi-fbc-h-line-budget = <0>;
+ qcom,mdss-dsi-fbc-budget-ctrl = <0>;
+ qcom,mdss-dsi-fbc-block-budget = <0>;
+ qcom,mdss-dsi-fbc-lossless-threshold = <0>;
+ qcom,mdss-dsi-fbc-lossy-threshold = <0>;
+ qcom,mdss-dsi-fbc-rgb-threshold = <0>;
+ qcom,mdss-dsi-fbc-lossy-mode-idx = <0>;
+ qcom,mdss-dsi-fbc-max-pred-err = <2>;
+ qcom,mdss-dsi-h-front-porch = <140>;
+ qcom,mdss-dsi-h-back-porch = <164>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <6>;
+ qcom,mdss-dsi-v-front-porch = <1>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = < 15>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,bl-update-flag = "delay_until_first_frame";
+ qcom,mdss-dsi-interleave-mode = <0>;
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <30>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-hfp-power-mode;
+ qcom,mdss-dsi-hbp-power-mode;
+ qcom,mdss-dsi-hsa-power-mode;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-last-line-interleave;
+ qcom,mdss-dsi-traffic-mode = <0>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-color-order = <0>;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-t-clk-post = <0x20>;
+ qcom,mdss-dsi-t-clk-pre = <0x2c>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-mdp-trigger = <0>;
+ qcom,mdss-dsi-dma-trigger = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33
+ 22 27 1e 03 04 00];
+ qcom,mdss-dsi-panel-timings-8996 = [23 20 06 09 05 03 04 a0
+ 23 20 06 09 05 03 04 a0
+ 23 20 06 09 05 03 04 a0
+ 23 20 06 09 05 03 04 a0
+ 23 2e 06 08 05 03 04 a0];
+ qcom,mdss-dsi-on-command = [32 01 00 00 00 00 02 00 00
+ 29 01 00 00 10 00 02 FF 99];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [22 01 00 00 00 00 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_suspend_resume_mode";
+ qcom,min-refresh-rate = <30>;
+ qcom,max-refresh-rate = <60>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8941_mpps 5 0>;
+ qcom,5v-boost-gpio = <&pm8994_gpios 14 0>;
+ qcom,mdss-pan-physical-width-dimension = <60>;
+ qcom,mdss-pan-physical-height-dimension = <140>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dsc_mode";
+ qcom,mdss-tear-check-sync-cfg-height = <0xfff0>;
+ qcom,mdss-tear-check-sync-init-val = <1280>;
+ qcom,mdss-tear-check-sync-threshold-start = <4>;
+ qcom,mdss-tear-check-sync-threshold-continue = <4>;
+ qcom,mdss-tear-check-start-pos = <1280>;
+ qcom,mdss-tear-check-rd-ptr-trigger-intr = <1281>;
+ qcom,mdss-tear-check-frame-rate = <6000>;
+ qcom,mdss-dsi-reset-sequence = <1 2>, <0 10>, <1 10>;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-init-delay-us = <100>;
+ mdss-dsi-rx-eot-ignore;
+ mdss-dsi-tx-eot-append;
+ qcom,ulps-enabled;
+ qcom,suspend-ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-read-length = <8>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-panel-status-value = <0x1c 0x00 0x05 0x02 0x40 0x84 0x06 0x01>;
+ qcom,dynamic-mode-switch-enabled;
+ qcom,dynamic-mode-switch-type = "dynamic-switch-immediate";
+ qcom,mdss-dsi-post-mode-switch-on-command = [32 01 00 00 00 00 02 00 00
+ 29 01 00 00 10 00 02 B0 03];
+ qcom,video-to-cmd-mode-switch-commands = [15 01 00 00 00 00 02 C2 0B
+ 15 01 00 00 00 00 02 C2 08];
+ qcom,cmd-to-video-mode-switch-commands = [15 01 00 00 00 00 02 C2 03];
+ qcom,send-pps-before-switch;
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-horizontal-line-idle = <0 40 256>,
+ <40 120 128>,
+ <128 240 64>;
+ qcom,mdss-dsi-panel-orientation = "180"
+ qcom,mdss-dsi-panel-jitter = <0x8 0x10>;
+ qcom,mdss-dsi-panel-prefill-lines = <0x10>;
+ qcom,mdss-dsi-force-clock-lane-hs;
+ qcom,compression-mode = "dsc";
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ wqhd {
+ qcom,mdss-dsi-cmd-mode;
+ qcom,mdss-dsi-timing-default;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <8>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <728>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-clockrate = <424000000>;
+ qcom,mdss-mdp-transfer-time-us = <12500>;
+ qcom,mdss-dsi-panel-timings = [E6 38 26 00 68 6E 2A 3C 2C 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2a>;
+ qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00
+ 05 01 00 00 02 00 02 29 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-timing-switch-command = [
+ 29 00 00 00 00 00 02 B0 04
+ 29 00 00 00 00 00 02 F1 00];
+ qcom,mdss-dsi-timing-switch-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-qsync-on-commands = [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands = [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state = "dsi_hs_mode";
+
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ qcom,mdss-dsc-config-by-manufacture-cmd;
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <4 4 2 2 20 20>;
+ };
+ };
+ qcom,panel-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <2800000>;
+ qcom,supply-max-voltage = <2800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-pre-on-sleep = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ qcom,supply-pre-off-sleep = <0>;
+ qcom,supply-post-off-sleep = <0>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-pre-on-sleep = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ qcom,supply-pre-off-sleep = <0>;
+ qcom,supply-post-off-sleep = <0>;
+ };
+ };
+
+ qcom,dba-panel;
+ qcom,bridge-name = "adv7533";
+ qcom,mdss-dsc-version = <0x11>;
+ qcom,mdss-dsc-scr-version = <0x1>;
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ qcom,mdss-dsc-config-by-manufacture-cmd;
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,mdss-dsi-dma-schedule-line = <5>;
+ };
+};
diff --git a/bindings/mdss-pll.txt b/bindings/mdss-pll.txt
new file mode 100644
index 0000000..a935297
--- /dev/null
+++ b/bindings/mdss-pll.txt
@@ -0,0 +1,108 @@
+Qualcomm Technologies, Inc. MDSS pll for DSI/EDP/HDMI
+
+mdss-pll is a pll controller device which supports pll devices that
+are compatible with MIPI display serial interface specification,
+HDMI and edp.
+
+Required properties:
+- compatible: Compatible name used in the driver. Should be one of:
+ "qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939",
+ "qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994",
+ "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909",
+ "qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994",
+ "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992",
+ "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996",
+ "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2",
+ "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8",
+ "qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8",
+ "qcom,mdss_dsi_pll_10nm", "qcom,mdss_dp_pll_8998",
+ "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm",
+ "qcom,mdss_dsi_pll_7nm", "qcom,mdss_dp_pll_7nm",
+ "qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm",
+ "qcom,mdss_dp_pll_14nm", "qcom,mdss_dsi_pll_7nm_v2",
+ "qcom,mdss_hdmi_pll_28lpm","qcom,mdss_dsi_pll_7nm_v4_1",
+ "qcom,mdss_dp_pll_7nm_v2"
+- cell-index: Specifies the controller used
+- reg: offset and length of the register set for the device.
+- reg-names : names to refer to register sets related to this device
+- gdsc-supply: Phandle for gdsc regulator device node.
+- vddio-supply: Phandle for vddio regulator device node.
+- clocks: List of Phandles for clock device nodes
+ needed by the device.
+- clock-names: List of clock names needed by the device.
+- clock-rate: List of clock rates in Hz.
+
+Optional properties:
+- label: A string used to describe the driver used.
+- vcca-supply: Phandle for vcca regulator device node.
+
+
+- qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled.
+- qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread"
+ or "center-spread". Default is "down-spread" if it is not specified.
+- qcom,ssc-frequency-hz: Integer property to specify the spread frequency
+ to be programmed for the SSC.
+- qcom,ssc-ppm: Integer property to specify the Parts per Million
+ value of SSC.
+
+- qcom,platform-supply-entries: A node that lists the elements of the supply. There
+ can be more than one instance of this binding,
+ in which case the entry would be appended with
+ the supply entry index.
+ e.g. qcom,platform-supply-entry@0
+ - reg: offset and length of the register set for the device.
+ -- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+ -- qcom,supply-min-voltage: minimum voltage level (uV)
+ -- qcom,supply-max-voltage: maximum voltage level (uV)
+ -- qcom,supply-enable-load: load drawn (uA) from enabled supply
+ -- qcom,supply-disable-load: load drawn (uA) from disabled supply
+ -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+ -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+ -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+ -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+
+Example:
+ mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 {
+ compatible = "qcom,mdss_dsi_pll_8974";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+
+ reg = <0xfd922A00 0xD4>,
+ <0xfd922900 0x64>,
+ <0xfd8c2300 0x8>;
+ reg-names = "pll_base", "dynamic_pll_base", "gdsc_base";
+ gdsc-supply = <&gdsc_mdss>;
+ vddio-supply = <&pm8941_l12>;
+ vcca-supply = <&pm8941_l28>;
+
+ clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,
+ <&clock_gcc clk_gcc_mdss_ahb_clk>,
+ <&clock_gcc clk_gcc_mdss_axi_clk>;
+ clock-names = "mdp_core_clk", "iface_clk", "bus_clk";
+ clock-rate = <0>, <0>, <0>;
+
+ qcom,dsi-pll-slave;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,ssc-frequency-hz = <30000>;
+ qcom,ssc-ppm = <5000>;
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-pre-on-sleep = <0>;
+ qcom,supply-post-on-sleep = <20>;
+ qcom,supply-pre-off-sleep = <0>;
+ qcom,supply-post-off-sleep = <0>;
+ };
+ };
+ };
+
diff --git a/bindings/sde-dp.txt b/bindings/sde-dp.txt
new file mode 100644
index 0000000..7881230
--- /dev/null
+++ b/bindings/sde-dp.txt
@@ -0,0 +1,237 @@
+Qualcomm Technologies, Inc.
+sde-dp is the master Display Port device which supports DP host controllers that are compatible with VESA Display Port interface specification.
+DP Controller: Required properties:
+- compatible: Should be "qcom,dp-display".
+- reg: Base address and length of DP hardware's memory mapped regions.
+- reg-names: A list of strings that name the list of regs. "dp_ctrl" - DP controller memory region.
+ "dp_phy" - DP PHY memory region.
+ "dp_ln_tx0" - USB3 DP PHY combo TX-0 lane memory region.
+ "dp_ln_tx1" - USB3 DP PHY combo TX-1 lane memory region.
+ "dp_mmss_cc" - Display Clock Control memory region.
+ "qfprom_physical" - QFPROM Phys memory region.
+ "dp_pll" - USB3 DP combo PLL memory region.
+ "usb3_dp_com" - USB3 DP PHY combo memory region.
+ "hdcp_physical" - DP HDCP memory region.
+- cell-index: Specifies the controller instance.
+- clocks: Clocks required for Display Port operation.
+- clock-names: Names of the clocks corresponding to handles. Following clocks are required:
+ "core_aux_clk", "core_usb_ref_clk_src","core_usb_ref_clk", "core_usb_cfg_ahb_clk",
+ "core_usb_pipe_clk", "ctrl_link_clk", "ctrl_link_iface_clk", "ctrl_crypto_clk",
+ "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent".
+- gdsc-supply: phandle to gdsc regulator node.
+- vdda-1p2-supply: phandle to vdda 1.2V regulator node.
+- vdda-0p9-supply: phandle to vdda 0.9V regulator node.
+- interrupt-parent phandle to the interrupt parent device node.
+- interrupts: The interrupt signal from the DSI block.
+- qcom,aux-en-gpio: Specifies the aux-channel enable gpio.
+- qcom,aux-sel-gpio: Specifies the aux-channel select gpio.
+- qcom,usbplug-cc-gpio: Specifies the usbplug orientation gpio.
+- qcom,aux-cfg0-settings: Specifies the DP AUX configuration 0 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg1-settings: Specifies the DP AUX configuration 1 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg2-settings: Specifies the DP AUX configuration 2 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg3-settings: Specifies the DP AUX configuration 3 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg4-settings: Specifies the DP AUX configuration 4 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg5-settings: Specifies the DP AUX configuration 5 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg6-settings: Specifies the DP AUX configuration 6 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg7-settings: Specifies the DP AUX configuration 7 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg8-settings: Specifies the DP AUX configuration 8 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,aux-cfg9-settings: Specifies the DP AUX configuration 9 settings. The first
+ entry in this array corresponds to the register offset
+ within DP AUX, while the remaining entries indicate the
+ programmable values.
+- qcom,max-pclk-frequency-khz: An integer specifying the max. pixel clock in KHz supported by Display Port.
+- qcom,mst-enable: MST feature enable control node.
+- qcom,dsc-feature-enable: DSC feature enable control node.
+- qcom,fec-feature-enable: FEC feature enable control node.
+- qcom,max-dp-dsc-blks: An integer specifying the max. DSC blocks available for Display port.
+- qcom,max-dp-dsc-input-width-pixs: An integer specifying the max. input width of pixels for each DSC block.
+- qcom,dp-usbpd-detection: Phandle for the PMI regulator node for USB PHY PD detection.
+- qcom,dp-aux-switch: Phandle for the driver used to program the AUX switch for Display Port orientation.
+- qcom,dp-hpd-gpio: HPD gpio for direct DP connector without USB PHY or AUX switch.
+- qcom,dp-gpio-aux-switch: Gpio DP AUX switch chipset support.
+- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the a particular "type" of DSI module. The module "types"
+ can be "core", "ctrl", and "phy". Within the same type,
+ there can be more than one instance of this binding,
+ in which case the entry would be appended with the
+ supply entry index.
+ e.g. qcom,ctrl-supply-entry@0
+ -- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+ -- qcom,supply-min-voltage: minimum voltage level (uV)
+ -- qcom,supply-max-voltage: maximum voltage level (uV)
+ -- qcom,supply-enable-load: load drawn (uA) from enabled supply
+ -- qcom,supply-disable-load: load drawn (uA) from disabled supply
+ -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+ -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+ -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+ -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+
+msm_ext_disp is a device which manages the interaction between external
+display interfaces, e.g. Display Port, and the audio subsystem.
+
+Optional properties:
+- qcom,ext-disp: phandle for msm-ext-display module
+- compatible: Must be "qcom,msm-ext-disp"
+- qcom,dp-low-power-hw-hpd: Low power hardware HPD feature enable control node
+- qcom,phy-version: Phy version
+- qcom,pn-swap-lane-map: P/N swap configuration of each lane
+- pinctrl-names: List of names to assign mdss pin states defined in pinctrl device node
+ Refer to pinctrl-bindings.txt
+- pinctrl-<0..n>: Lists phandles each pointing to the pin configuration node within a pin
+ controller. These pin configurations are installed in the pinctrl
+ device node. Refer to pinctrl-bindings.txt
+- qcom,max-lclk-frequency-khz: An integer specifying the max. link clock in KHz supported by Display Port.
+- qcom,mst-fixed-topology-ports: u32 values of which MST output port to reserve, start from one
+
+[Optional child nodes]: These nodes are for devices which are
+dependent on msm_ext_disp. If msm_ext_disp is disabled then
+these devices will be disabled as well. Ex. Audio Codec device.
+
+- ext_disp_audio_codec: Node for Audio Codec.
+- compatible : "qcom,msm-ext-disp-audio-codec-rx";
+
+Example:
+ ext_disp: qcom,msm-ext-disp {
+ compatible = "qcom,msm-ext-disp";
+ ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+ compatible = "qcom,msm-ext-disp-audio-codec-rx";
+ };
+ };
+
+ sde_dp: qcom,dp_display@0{
+ cell-index = <0>;
+ compatible = "qcom,dp-display";
+
+ gdsc-supply = <&mdss_core_gdsc>;
+ vdda-1p2-supply = <&pm8998_l26>;
+ vdda-0p9-supply = <&pm8998_l1>;
+
+ reg = <0xae90000 0xa84>,
+ <0x88eaa00 0x200>,
+ <0x88ea200 0x200>,
+ <0x88ea600 0x200>,
+ <0xaf02000 0x1a0>,
+ <0x780000 0x621c>,
+ <0x88ea030 0x10>,
+ <0x88e8000 0x621c>,
+ <0x0aee1000 0x034>;
+ reg-names = "dp_ctrl", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+ "dp_mmss_cc", "qfprom_physical", "dp_pll",
+ "usb3_dp_com", "hdcp_physical";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <12 0>;
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_CRYPTO_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>;
+ clock-names = "core_aux_clk", "core_usb_ref_clk_src",
+ "core_usb_ref_clk", "core_usb_cfg_ahb_clk",
+ "core_usb_pipe_clk", "ctrl_link_clk",
+ "ctrl_link_iface_clk", "ctrl_crypto_clk",
+ "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent";
+
+ qcom,dp-usbpd-detection = <&pm8150b_pdphy>;
+ qcom,ext-disp = <&ext_disp>;
+ qcom,phy-version = <0x420>;
+ qcom,dp-aux-switch = <&fsa4480>;
+
+ qcom,aux-cfg0-settings = [1c 00];
+ qcom,aux-cfg1-settings = [20 13 23 1d];
+ qcom,aux-cfg2-settings = [24 00];
+ qcom,aux-cfg3-settings = [28 00];
+ qcom,aux-cfg4-settings = [2c 0a];
+ qcom,aux-cfg5-settings = [30 26];
+ qcom,aux-cfg6-settings = [34 0a];
+ qcom,aux-cfg7-settings = [38 03];
+ qcom,aux-cfg8-settings = [3c bb];
+ qcom,aux-cfg9-settings = [40 03];
+ qcom,max-pclk-frequency-khz = <593470>;
+ qcom,mst-enable;
+ qcom,dsc-feature-enable;
+ qcom,fec-feature-enable;
+ qcom,max-dp-dsc-blks = <2>;
+ qcom,max-dp-dsc-input-width-pixs = <2048>;
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
+ pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
+ qcom,aux-en-gpio = <&tlmm 43 0>;
+ qcom,aux-sel-gpio = <&tlmm 51 0>;
+ qcom,usbplug-cc-gpio = <&tlmm 38 0>;
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <4>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <36000>;
+ qcom,supply-disable-load = <32>;
+ };
+ };
+ };
+};
diff --git a/bindings/sde-dsi.txt b/bindings/sde-dsi.txt
new file mode 100644
index 0000000..e09261d
--- /dev/null
+++ b/bindings/sde-dsi.txt
@@ -0,0 +1,118 @@
+Qualcomm Technologies, Inc.
+
+mdss-dsi is the master DSI device which supports multiple DSI host controllers
+that are compatible with MIPI display serial interface specification.
+
+DSI Controller:
+Required properties:
+- compatible: Should be "qcom,dsi-ctrl-hw-v<version>". Supported
+ versions include 1.4, 2.0 and 2.2.
+ eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0,
+ qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3,
+ qcom,dsi-ctrl-hw-v2.4
+ And for dsi phy driver:
+ qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm,
+ qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0,
+ qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1
+- reg: Base address and length of DSI controller's memory
+ mapped regions.
+- reg-names: A list of strings that name the list of regs.
+ "dsi_ctrl" - DSI controller memory region.
+ "mmss_misc" - MMSS misc memory region.
+- cell-index: Specifies the controller instance.
+- clocks: Clocks required for DSI controller operation.
+- clock-names: Names of the clocks corresponding to handles. Following
+ clocks are required:
+ "mdp_core_clk"
+ "iface_clk"
+ "core_mmss_clk"
+ "bus_clk"
+ "byte_clk"
+ "pixel_clk"
+ "core_clk"
+ "byte_clk_rcg"
+ "pixel_clk_rcg"
+- gdsc-supply: phandle to gdsc regulator node.
+- vdda-supply: phandle to vdda regulator node.
+- vcca-supply: phandle to vcca regulator node.
+- interrupt-parent phandle to the interrupt parent device node.
+- interrupts: The interrupt signal from the DSI block.
+- qcom,dsi-default-panel: Specifies the default panel.
+- qcom,mdp: Specifies the mdp node which can find panel node from this.
+
+Bus Scaling Data:
+- qcom,msm-bus,name: String property describing MDSS client.
+- qcom,msm-bus,num-cases: This is the number of bus scaling use cases
+ defined in the vectors property. This must be
+ set to <2> for MDSS DSI driver where use-case 0
+ is used to remove BW votes from the system. Use
+ case 1 is used to generate bandwidth requestes
+ when sending command packets.
+- qcom,msm-bus,num-paths: This represents number of paths in each bus
+ scaling usecase. This value depends on number of
+ AXI master ports dedicated to MDSS for
+ particular chipset.
+- qcom,msm-bus,vectors-KBps: A series of 4 cell properties, with a format
+ of (src, dst, ab, ib) which is defined at
+ Documentation/devicetree/bindings/arm/msm/msm_bus.txt.
+ DSI driver should always set average bandwidth
+ (ab) to 0 and always use instantaneous
+ bandwidth(ib) values.
+
+Optional properties:
+- label: String to describe controller.
+- qcom,platform-te-gpio: Specifies the gpio used for TE.
+- qcom,panel-te-source: Specifies the source pin for Vsync from panel or WD Timer.
+- qcom,dsi-ctrl: handle to dsi controller device
+- qcom,dsi-phy: handle to dsi phy device
+- qcom,dsi-ctrl-num: Specifies the DSI controllers to use for primary panel
+- qcom,dsi-sec-ctrl-num: Specifies the DSI controllers to use for secondary panel
+- qcom,dsi-phy-num: Specifies the DSI PHYs to use for primary panel
+- qcom,dsi-sec-phy-num: Specifies the DSI PHYs to use for secondary panel
+- qcom,dsi-select-clocks: Specifies the required clocks to use for primary panel
+- qcom,dsi-select-sec-clocks: Specifies the required clocks to use for secondary panel
+- qcom,dsi-display-list: Specifies the list of supported displays.
+- qcom,dsi-manager: Specifies dsi manager is present
+- qcom,dsi-display: Specifies dsi display is present
+- qcom,hdmi-display: Specifies hdmi is present
+- qcom,dp-display: Specified dp is present
+- qcom,<type>-supply-entries: A node that lists the elements of the supply used by the
+ a particular "type" of DSI module. The module "types"
+ can be "core", "ctrl", and "phy". Within the same type,
+ there can be more than one instance of this binding,
+ in which case the entry would be appended with the
+ supply entry index.
+ e.g. qcom,ctrl-supply-entry@0
+ -- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+ -- qcom,supply-min-voltage: minimum voltage level (uV)
+ -- qcom,supply-max-voltage: maximum voltage level (uV)
+ -- qcom,supply-enable-load: load drawn (uA) from enabled supply
+ -- qcom,supply-disable-load: load drawn (uA) from disabled supply
+ -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+ -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+ -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+ -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
+ panels in microseconds. Driver uses this number to adjust
+ the clock rate according to the expected transfer time.
+ Increasing this value would slow down the mdp processing
+ and can result in slower performance.
+ Decreasing this value can speed up the mdp processing,
+ but this can also impact power consumption.
+ As a rule this time should not be higher than the time
+ that would be expected with the processing at the
+ dsi link rate since anyways this would be the maximum
+ transfer time that could be achieved.
+ If ping pong split enabled, this time should not be higher
+ than two times the dsi link rate time.
+ If the property is not specified, then the default value is 14000 us.
+- qcom,dsi-phy-isolation-enabled: A boolean property enables the phy isolation from dsi
+ controller. This must be enabled for debugging purpose
+ only with simulator panel. It should not be enabled for
+ normal DSI panels.
+- - qcom,null-insertion-enabled: A boolean to enable NULL packet insertion feature for DSI controller.
+- ports: This video port is used when external bridge is present.
+ The connection is modeled using the OF graph bindings
+ specified in Documentation/devicetree/bindings/graph.txt.
+ Video port 0 reg 0 is for the bridge output. The remote
+ endpoint phandle should be mipi_dsi_device device node.
diff --git a/bindings/sde-rsc.txt b/bindings/sde-rsc.txt
new file mode 100644
index 0000000..3af5629
--- /dev/null
+++ b/bindings/sde-rsc.txt
@@ -0,0 +1,97 @@
+Qualcomm Technologies, Inc. SDE RSC
+
+Snapdragon Display Engine implements display rsc to driver
+display core to different modes for power saving
+
+Required properties
+- compatible: "qcom,sde-rsc"
+ "qcom,sde-rsc-rpmh"
+- reg: Offset and length of the register set for
+ the device.
+- reg-names: Names to refer to register sets related
+ to this device
+
+Optional properties:
+- clocks: List of phandles for clock device nodes
+ needed by the device.
+- clock-names: List of clock names needed by the device.
+- vdd-supply: phandle for vdd regulator device node.
+- qcom,sde-rsc-version: U32 property represents the rsc version. It helps to
+ select correct sequence for sde rsc based on version.
+- qcom,sde-dram-channels: U32 property represents the number of channels in the
+ Bus memory controller.
+- qcom,sde-num-nrt-paths: U32 property represents the number of non-realtime
+ paths in each Bus Scaling Usecase. This value depends on
+ number of AXI ports that are dedicated to non-realtime VBIF
+ for particular chipset.
+ These paths must be defined after rt-paths in
+ "qcom,msm-bus,vectors-KBps" vector request.
+
+Bus Scaling Subnodes:
+- qcom,sde-data-bus: Property to provide Bus scaling for data bus access for
+ sde blocks.
+- qcom,sde-llcc-bus: Property to provide Bus scaling for data bus access for
+ mnoc to llcc.
+- qcom,sde-ebi-bus: Property to provide Bus scaling for data bus access for
+ llcc to ebi.
+
+Bus Scaling Data:
+- qcom,msm-bus,name: String property describing client name.
+- qcom,msm-bus,active-only: Boolean context flag for requests in active or
+ dual (active & sleep) contex
+- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases
+ defined in the vectors property.
+- qcom,msm-bus,num-paths: This represents the number of paths in each
+ Bus Scaling Usecase.
+- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format
+ of (src, dst, ab, ib) which is defined at
+ Documentation/devicetree/bindings/arm/msm/msm_bus.txt
+ * Current values of src & dst are defined at
+ include/linux/msm-bus-board.h
+Example:
+ sde_rscc {
+ cell-index = <0>;
+ compatible = "qcom,sde-rsc";
+ reg = <0xaf20000 0x1c44>,
+ <0xaf30000 0x3fd4>;
+ reg-names = "drv", "wrapper";
+ clocks = <&clock_mmss clk_mdss_ahb_clk>,
+ <&clock_mmss clk_mdss_axi_clk>;
+ clock-names = "iface_clk", "bus_clk";
+ vdd-supply = <&gdsc_mdss>;
+
+ qcom,sde-rsc-version = <1>;
+ qcom,sde-dram-channels = <2>;
+ qcom,sde-num-nrt-paths = <1>;
+
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "sde_rsc";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>,
+ <22 512 0 6400000>, <23 512 0 6400000>,
+ <22 512 0 6400000>, <23 512 0 6400000>;
+ };
+ qcom,sde-llcc-bus {
+ qcom,msm-bus,name = "sde_rsc_llcc";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <20001 20513 0 0>,
+ <20001 20513 0 6400000>,
+ <20001 20513 0 6400000>;
+ };
+ qcom,sde-ebi-bus {
+ qcom,msm-bus,name = "sde_rsc_ebi";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <20000 20512 0 0>,
+ <20000 20512 0 6400000>,
+ <20000 20512 0 6400000>;
+ };
+ };
diff --git a/bindings/sde-wb.txt b/bindings/sde-wb.txt
new file mode 100644
index 0000000..90093e4
--- /dev/null
+++ b/bindings/sde-wb.txt
@@ -0,0 +1,23 @@
+Qualcomm Technologies, Inc. Snapdragon Display Engine (SDE) writeback display
+
+Required properties:
+- compatible: "qcom,wb-display"
+
+Optional properties:
+- cell-index: Index of writeback device instance.
+ Default to 0 if not specified.
+- label: String to describe this writeback display.
+ Default to "unknown" if not specified.
+
+Example:
+
+/ {
+ ...
+
+ sde_wb: qcom,wb-display {
+ compatible = "qcom,wb-display";
+ cell-index = <2>;
+ label = "wb_display";
+ };
+
+};
diff --git a/bindings/sde.txt b/bindings/sde.txt
new file mode 100644
index 0000000..c4c6698
--- /dev/null
+++ b/bindings/sde.txt
@@ -0,0 +1,888 @@
+Qualcomm Technologies, Inc. SDE KMS
+
+Snapdragon Display Engine implements Linux DRM/KMS APIs to drive user
+interface to different panel interfaces. SDE driver is the core of
+display subsystem which manage all data paths to different panel interfaces.
+
+Required properties
+- compatible: Must be "qcom,sde-kms"
+- compatible: "msm-hdmi-audio-codec-rx";
+- reg: Offset and length of the register set for the device.
+- reg-names : Names to refer to register sets related to this device
+- clocks: List of Phandles for clock device nodes
+ needed by the device.
+- clock-names: List of clock names needed by the device.
+- mmagic-supply: Phandle for mmagic mdss supply regulator device node.
+- vdd-supply: Phandle for vdd regulator device node.
+- interrupt-parent: Must be core interrupt controller.
+- interrupts: Interrupt associated with MDSS.
+- interrupt-controller: Mark the device node as an interrupt controller.
+- #interrupt-cells: Should be one. The first cell is interrupt number.
+- iommus: Specifies the SID's used by this context bank.
+- qcom,sde-sspp-type: Array of strings for SDE source surface pipes type information.
+ A source pipe can be "vig", "rgb", "dma" or "cursor" type.
+ Number of xin ids defined should match the number of offsets
+ defined in property: qcom,sde-sspp-off.
+- qcom,sde-sspp-off: Array of offset for SDE source surface pipes. The offsets
+ are calculated from register "mdp_phys" defined in
+ reg property + "sde-off". The number of offsets defined here should
+ reflect the amount of pipes that can be active in SDE for
+ this configuration.
+- qcom,sde-sspp-xin-id: Array of VBIF clients ids (xins) corresponding
+ to the respective source pipes. Number of xin ids
+ defined should match the number of offsets
+ defined in property: qcom,sde-sspp-off.
+- qcom,sde-ctl-off: Array of offset addresses for the available ctl
+ hw blocks within SDE, these offsets are
+ calculated from register "mdp_phys" defined in
+ reg property. The number of ctl offsets defined
+ here should reflect the number of control paths
+ that can be configured concurrently on SDE for
+ this configuration.
+- qcom,sde-wb-off: Array of offset addresses for the programmable
+ writeback blocks within SDE.
+- qcom,sde-wb-xin-id: Array of VBIF clients ids (xins) corresponding
+ to the respective writeback. Number of xin ids
+ defined should match the number of offsets
+ defined in property: qcom,sde-wb-off.
+- qcom,sde-mixer-off: Array of offset addresses for the available
+ mixer blocks that can drive data to panel
+ interfaces. These offsets are be calculated from
+ register "mdp_phys" defined in reg property.
+ The number of offsets defined should reflect the
+ amount of mixers that can drive data to a panel
+ interface.
+- qcom,sde-dspp-top-off: Offset address for the dspp top block.
+ The offset is calculated from register "mdp_phys"
+ defined in reg property.
+- qcom,sde-dspp-off: Array of offset addresses for the available dspp
+ blocks. These offsets are calculated from
+ register "mdp_phys" defined in reg property.
+- qcom,sde-pp-off: Array of offset addresses for the available
+ pingpong blocks. These offsets are calculated
+ from register "mdp_phys" defined in reg property.
+- qcom,sde-pp-slave: Array of flags indicating whether each ping pong
+ block may be configured as a pp slave.
+- qcom,sde-pp-merge-3d-id: Array of index ID values for the merge 3d block
+ connected to each pingpong, starting at 0.
+- qcom,sde-merge-3d-off: Array of offset addresses for the available
+ merge 3d blocks. These offsets are calculated
+ from register "mdp_phys" defined in reg property.
+- qcom,sde-intf-off: Array of offset addresses for the available SDE
+ interface blocks that can drive data to a
+ panel controller. The offsets are calculated
+ from "mdp_phys" defined in reg property. The number
+ of offsets defined should reflect the number of
+ programmable interface blocks available in hardware.
+- qcom,sde-mixer-blend-op-off Array of offset addresses for the available
+ blending stages. The offsets are relative to
+ qcom,sde-mixer-off.
+- qcom,sde-mixer-pair-mask Array of mixer numbers that can be paired with
+ mixer number corresponding to the array index.
+
+Optional properties:
+- clock-rate: List of clock rates in Hz.
+- clock-max-rate: List of maximum clock rate in Hz that this device supports.
+- qcom,platform-supply-entries: A node that lists the elements of the supply. There
+ can be more than one instance of this binding,
+ in which case the entry would be appended with
+ the supply entry index.
+ e.g. qcom,platform-supply-entry@0
+ -- reg: offset and length of the register set for the device.
+ -- qcom,supply-name: name of the supply (vdd/vdda/vddio)
+ -- qcom,supply-min-voltage: minimum voltage level (uV)
+ -- qcom,supply-max-voltage: maximum voltage level (uV)
+ -- qcom,supply-enable-load: load drawn (uA) from enabled supply
+ -- qcom,supply-disable-load: load drawn (uA) from disabled supply
+ -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on
+ -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on
+ -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off
+ -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off
+- qcom,sde-sspp-src-size: A u32 value indicates the address range for each sspp.
+- qcom,sde-mixer-size: A u32 value indicates the address range for each mixer.
+- qcom,sde-ctl-size: A u32 value indicates the address range for each ctl.
+- qcom,sde-dspp-size: A u32 value indicates the address range for each dspp.
+- qcom,sde-intf-size: A u32 value indicates the address range for each intf.
+- qcom,sde-dsc-size: A u32 value indicates the address range for each dsc.
+- qcom,sde-cdm-size: A u32 value indicates the address range for each cdm.
+- qcom,sde-pp-size: A u32 value indicates the address range for each pingpong.
+- qcom,sde-merge-3d-size: A u32 value indicates the address range for each merge 3d.
+- qcom,sde-wb-size: A u32 value indicates the address range for each writeback.
+- qcom,sde-len: A u32 entry for SDE address range.
+- qcom,sde-intf-max-prefetch-lines: Array of u32 values for max prefetch lines on
+ each interface.
+- qcom,sde-sspp-linewidth: A u32 value indicates the max sspp line width.
+- qcom,sde-mixer-linewidth: A u32 value indicates the max mixer line width.
+- qcom,sde-wb-linewidth: A u32 value indicates the max writeback line width.
+- qcom,sde-sspp-scale-size: A u32 value indicates the scaling block size on sspp.
+- qcom,sde-mixer-blendstages: A u32 value indicates the max mixer blend stages for
+ alpha blending.
+- qcom,sde-qseed-type: A string entry indiates qseed support on sspp and wb.
+ It supports "qssedv3" and "qseedv2" entries for qseed
+ type. By default "qseedv2" is used if this optional property
+ is not defined.
+- qcom,sde-csc-type: A string entry indicates csc support on sspp and wb.
+ It supports "csc" and "csc-10bit" entries for csc
+ type.
+- qcom,sde-highest-bank-bit: A u32 property to indicate GPU/Camera/Video highest memory
+ bank bit used for tile format buffers.
+- qcom,sde-ubwc-version: Property to specify the UBWC feature version.
+- qcom,sde-ubwc-static: Property to specify the default UBWC static
+ configuration value.
+- qcom,sde-ubwc-bw-calc-version: A u32 property to specify version of UBWC bandwidth
+ calculation algorithm
+- qcom,sde-ubwc-swizzle: Property to specify the default UBWC swizzle
+ configuration value.
+- qcom,sde-smart-panel-align-mode: A u32 property to specify the align mode for
+ split display on smart panel. Possible values:
+ 0x0 - no alignment
+ 0xc - align at start of frame
+ 0xd - align at start of line
+- qcom,sde-panic-per-pipe: Boolean property to indicate if panic signal
+ control feature is available on each source pipe.
+- qcom,sde-has-src-split: Boolean property to indicate if source split
+ feature is available or not.
+- qcom,sde-has-dim-layer: Boolean property to indicate if mixer has dim layer
+ feature is available or not.
+- qcom,sde-has-idle-pc: Boolean property to indicate if target has idle
+ power collapse feature available or not.
+- qcom,fullsize-va-map: Boolean property to indicate smmu mapping range
+ for mdp should be full range (4GB).
+- qcom,sde-has-mixer-gc: Boolean property to indicate if mixer has gamma correction
+ feature available or not.
+- qcom,sde-has-dest-scaler: Boolean property to indicate if destination scaler
+ feature is available or not.
+- qcom,sde-max-dest-scaler-input-linewidth: A u32 value indicates the
+ maximum input line width to destination scaler.
+- qcom,sde-max-dest-scaler-output-linewidth: A u32 value indicates the
+ maximum output line width of destination scaler.
+- qcom,sde-dest-scaler-top-off: A u32 value provides the
+ offset from mdp base to destination scaler block.
+- qcom,sde-dest-scaler-top-size: A u32 value indicates the address range for ds top
+- qcom,sde-dest-scaler-off: Array of u32 offsets indicate the qseed3 scaler blocks
+ offset from destination scaler top offset.
+- qcom,sde-dest-scaler-size: A u32 value indicates the address range for each scaler block
+- qcom,sde-sspp-clk-ctrl: Array of offsets describing clk control
+ offsets for dynamic clock gating. 1st value
+ in the array represents offset of the control
+ register. 2nd value represents bit offset within
+ control register. Number of offsets defined should
+ match the number of offsets defined in
+ property: qcom,sde-sspp-off
+- qcom,sde-sspp-clk-status: Array of offsets describing clk status
+ offsets for dynamic clock gating. 1st value
+ in the array represents offset of the status
+ register. 2nd value represents bit offset within
+ control register. Number of offsets defined should
+ match the number of offsets defined in
+ property: qcom,sde-sspp-off.
+- qcom,sde-sspp-excl-rect: Array of u32 values indicating exclusion rectangle
+ support on each sspp.
+- qcom,sde-sspp-smart-dma-priority: Array of u32 values indicating hw pipe
+ priority of secondary rectangles when smart dma
+ is supported. Number of priority values should
+ match the number of offsets defined in
+ qcom,sde-sspp-off node. Zero indicates no support
+ for smart dma for the sspp.
+- qcom,sde-smart-dma-rev: A string entry indicating the smart dma version
+ supported on the device. Supported entries are
+ "smart_dma_v1" and "smart_dma_v2".
+- qcom,sde-intf-type: Array of string provides the interface type information.
+ Possible string values
+ "dsi" - dsi display interface
+ "dp" - Display Port interface
+ "hdmi" - HDMI display interface
+ An interface is considered as "none" if interface type
+ is not defined.
+- qcom,sde-off: SDE offset from "mdp_phys" defined in reg property.
+- qcom,sde-cdm-off: Array of offset addresses for the available
+ cdm blocks. These offsets will be calculated from
+ register "mdp_phys" defined in reg property.
+- qcom,sde-vbif-off: Array of offset addresses for the available
+ vbif blocks. These offsets will be calculated from
+ register "vbif_phys" defined in reg property.
+- qcom,sde-vbif-size: A u32 value indicates the vbif block address range.
+- qcom,sde-uidle-off: A u32 value with the offset for the uidle
+ block, from the "mdp_phys".
+- qcom,sde-uidle-size: A u32 value indicates the uidle block address range.
+- qcom,sde-te-off: A u32 offset indicates the te block offset on pingpong.
+ This offset is 0x0 by default.
+- qcom,sde-te2-off: A u32 offset indicates the te2 block offset on pingpong.
+- qcom,sde-te-size: A u32 value indicates the te block address range.
+- qcom,sde-te2-size: A u32 value indicates the te2 block address range.
+- qcom,sde-dsc-off: A u32 offset indicates the dsc block offset on pingpong.
+- qcom,sde-qdss-off: A u32 offset indicates the qdss block offset.
+- qcom,sde-dither-off: A u32 offset indicates the dither block offset on pingpong.
+- qcom,sde-dither-version: A u32 value indicates the dither block version.
+- qcom,sde-dither-size: A u32 value indicates the dither block address range.
+- qcom,sde-sspp-vig-blocks: A node that lists the blocks inside the VIG hardware. The
+ block entries will contain the offset and version (if needed)
+ of each feature block. The presence of a block entry
+ indicates that the SSPP VIG contains that feature hardware.
+ e.g. qcom,sde-sspp-vig-blocks
+ -- qcom,sde-vig-csc-off: offset of CSC hardware
+ -- qcom,sde-vig-qseed-off: offset of QSEED hardware
+ -- qcom,sde-vig-qseed-size: A u32 address range for qseed scaler.
+ -- qcom,sde-vig-pcc: offset and version of PCC hardware
+ -- qcom,sde-vig-hsic: offset and version of global PA adjustment
+ -- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware
+ -- qcom,sde-vig-gamut: offset and version of 3D LUT Gamut hardware
+ -- qcom,sde-vig-igc: offset and version of 1D LUT IGC hardware
+ -- qcom,sde-vig-inverse-pma: Boolean property to indicate if
+ inverse PMA feature is available on VIG pipe
+- qcom,sde-sspp-dma-blocks: A node that lists the blocks inside the DMA hardware. There
+ can be more than one instance of this binding, in which case the
+ entry would be appended with dgm entry index. Each entry will
+ contain the offset and version (if needed) of each feature block.
+ The presence of a block entry indicates that the SSPP DMA contains
+ that feature hardware.
+ e.g. qcom,sde-sspp-dma-blocks
+ -- dgm@0
+ -- qcom,sde-dma-igc: offset and version of DMA IGC
+ -- qcom,sde-dma-gc: offset and version of DMA GC
+ -- qcom,sde-dma-inverse-pma: Boolean property to indicate if
+ inverse PMA feature is available on DMA pipe
+ -- qcom,sde-dma-csc-off: offset of CSC hardware
+- qcom,sde-sspp-rgb-blocks: A node that lists the blocks inside the RGB hardware. The
+ block entries will contain the offset and version (if needed)
+ of each feature block. The presence of a block entry
+ indicates that the SSPP RGB contains that feature hardware.
+ e.g. qcom,sde-sspp-rgb-blocks
+ -- qcom,sde-rgb-scaler-off: offset of RGB scaler hardware
+ -- qcom,sde-rgb-scaler-size: A u32 address range for scaler.
+ -- qcom,sde-rgb-pcc: offset and version of PCC hardware
+- qcom,sde-dspp-blocks: A node that lists the blocks inside the DSPP hardware. The
+ block entries will contain the offset and version of each
+ feature block. The presence of a block entry indicates that
+ the DSPP contains that feature hardware.
+ e.g. qcom,sde-dspp-blocks
+ -- qcom,sde-dspp-pcc: offset and version of PCC hardware
+ -- qcom,sde-dspp-gc: offset and version of GC hardware
+ -- qcom,sde-dspp-igc: offset and version of IGC hardware
+ -- qcom,sde-dspp-hsic: offset and version of global PA adjustment
+ -- qcom,sde-dspp-memcolor: offset and version of PA memcolor hardware
+ -- qcom,sde-dspp-sixzone: offset and version of PA sixzone hardware
+ -- qcom,sde-dspp-gamut: offset and version of Gamut mapping hardware
+ -- qcom,sde-dspp-dither: offset and version of dither hardware
+ -- qcom,sde-dspp-hist: offset and version of histogram hardware
+ -- qcom,sde-dspp-vlut: offset and version of PA vLUT hardware
+- qcom,sde-mixer-blocks: A node that lists the blocks inside the layer mixer hardware. The
+ block entries will contain the offset and version (if needed)
+ of each feature block. The presence of a block entry
+ indicates that the layer mixer contains that feature hardware.
+ e.g. qcom,sde-mixer-blocks
+ -- qcom,sde-mixer-gc: offset and version of mixer GC hardware
+- qcom,sde-dspp-ad-off: Array of u32 offsets indicate the ad block offset from the
+ DSPP offset. Since AD hardware is represented as part of
+ DSPP block, the AD offsets must be offset from the
+ corresponding DSPP base.
+- qcom,sde-dspp-ad-version A u32 value indicating the version of the AD hardware
+- qcom,sde-dspp-ltm-version A u32 value indicating the major(upper 16 bits) and minor(lower 16 bits)
+ version of the LTM hardware
+- qcom,sde-dspp-ltm-off: Array of u32 offsets indicate the LTM block offsets from the
+ DSPP offsets. Since LTM hardware is represented as part of
+ DSPP block, the LTM offsets are calculated based on the
+ corresponding DSPP base.
+- qcom,sde-vbif-id: Array of vbif ids corresponding to the
+ offsets defined in property: qcom,sde-vbif-off.
+- qcom,sde-vbif-default-ot-rd-limit: A u32 value indicates the default read OT limit
+- qcom,sde-vbif-default-ot-wr-limit: A u32 value indicates the default write OT limit
+- qcom,sde-vbif-dynamic-ot-rd-limit: A series of 2 cell property, with a format
+ of (pps, OT limit), where pps is pixel per second and
+ OT limit is the read limit to apply if the given
+ pps is not exceeded.
+- qcom,sde-vbif-dynamic-ot-wr-limit: A series of 2 cell property, with a format
+ of (pps, OT limit), where pps is pixel per second and
+ OT limit is the write limit to apply if the given
+ pps is not exceeded.
+- qcom,sde-vbif-memtype-0: Array of u32 vbif memory type settings, group 0
+- qcom,sde-vbif-memtype-1: Array of u32 vbif memory type settings, group 1
+- qcom,sde-wb-id: Array of writeback ids corresponding to the
+ offsets defined in property: qcom,sde-wb-off.
+- qcom,sde-wb-clk-ctrl: Array of 2 cell property describing clk control
+ offsets for dynamic clock gating. 1st value
+ in the array represents offset of the control
+ register. 2nd value represents bit offset within
+ control register. Number of offsets defined should
+ match the number of offsets defined in
+ property: qcom,sde-wb-off
+- qcom,sde-reg-dma-off: Offset of the register dma hardware block from
+ "regdma_phys" defined in reg property.
+- qcom,sde-reg-dma-version: Version of the reg dma hardware block.
+- qcom,sde-reg-dma-trigger-off: Offset of the lut dma trigger reg from "mdp_phys"
+ defined in reg property.
+- qcom,sde-reg-dma-broadcast-disabled: Boolean property to indicate if broadcast
+ functionality in the register dma hardware block should be used.
+- qcom,sde-reg-dma-xin-id: VBIF clients id (xin) corresponding
+ to the LUTDMA block.
+- qcom,sde-reg-dma-clk-ctrl: Array of 2 cell property describing clk control
+ offsets for dynamic clock gating. 1st value
+ in the array represents offset of the control
+ register. 2nd value represents bit offset within
+ control register.
+- qcom,sde-dram-channels: This represents the number of channels in the
+ Bus memory controller.
+- qcom,sde-num-nrt-paths: Integer property represents the number of non-realtime
+ paths in each Bus Scaling Usecase. This value depends on
+ number of AXI ports that are dedicated to non-realtime VBIF
+ for particular chipset.
+ These paths must be defined after rt-paths in
+ "qcom,msm-bus,vectors-KBps" vector request.
+- qcom,sde-max-bw-low-kbps: This value indicates the max bandwidth in Kbps
+ that can be supported without underflow.
+ This is a low bandwidth threshold which should
+ be applied in most scenarios to be safe from
+ underflows when unable to satisfy bandwidth
+ requirements.
+- qcom,sde-max-bw-high-kbps: This value indicates the max bandwidth in Kbps
+ that can be supported without underflow in the
+ event where there is no VFE.
+ This is a high bandwidth threshold which can be
+ applied in scenarios where panel interface can
+ be more tolerant to memory latency such as
+ command mode panels.
+- qcom,sde-core-ib-ff: A string entry indicating the fudge factor for
+ core ib calculation.
+- qcom,sde-core-clk-ff: A string entry indicating the fudge factor for
+ core clock calculation.
+- qcom,sde-min-core-ib-kbps: This u32 value indicates the minimum mnoc ib
+ vote in Kbps that can be reduced without hitting underflow.
+ BW calculation logic will choose the IB bandwidth requirement
+ based on usecase if this floor value is not defined.
+- qcom,sde-min-llcc-ib-kbps: This u32 value indicates the minimum llcc ib
+ vote in Kbps that can be reduced without hitting underflow.
+ BW calculation logic will choose the IB bandwidth requirement
+ based on usecase if this floor value is not defined.
+- qcom,sde-min-dram-ib-kbps: This u32 value indicates the minimum dram ib
+ vote in Kbps that can be reduced without hitting underflow.
+ BW calculation logic will choose the IB bandwidth requirement
+ based on usecase if this floor value is not defined.
+- qcom,sde-comp-ratio-rt: A string entry indicating the compression ratio
+ for each supported compressed format on realtime interface.
+ The string is composed of one or more of
+ <fourcc code>/<vendor code>/<modifier>/<compression ratio>
+ separated with spaces.
+- qcom,sde-comp-ratio-nrt: A string entry indicating the compression ratio
+ for each supported compressed format on non-realtime interface.
+ The string is composed of one or more of
+ <fourcc code>/<vendor code>/<modifier>/<compression ratio>
+ separated with spaces.
+- qcom,sde-undersized-prefill-lines: A u32 value indicates the size of undersized prefill in lines.
+- qcom,sde-xtra-prefill-lines: A u32 value indicates the extra prefill in lines.
+- qcom,sde-dest-scale-prefill-lines: A u32 value indicates the latency of destination scaler in lines.
+- qcom,sde-macrotile-prefill-lines: A u32 value indicates the latency of macrotile in lines.
+- qcom,sde-yuv-nv12-prefill-lines: A u32 value indicates the latency of yuv/nv12 in lines.
+- qcom,sde-linear-prefill-lines: A u32 value indicates the latency of linear in lines.
+- qcom,sde-downscaling-prefill-lines: A u32 value indicates the latency of downscaling in lines.
+- qcom,sde-max-per-pipe-bw-kbps: Array of u32 value indicates the max per pipe bandwidth in Kbps.
+- qcom,sde-amortizable-threshold: This value indicates the min for traffic shaping in lines.
+- qcom,sde-vbif-qos-rt-remap: This array is used to program vbif qos remapper register
+ priority for realtime clients.
+- qcom,sde-vbif-qos-nrt-remap: This array is used to program vbif qos remapper register
+ priority for non-realtime clients.
+- qcom,sde-vbif-qos-cwb-remap: This array is used to program vbif qos remapper register
+ priority for concurrent writeback clients.
+- qcom,sde-vbif-qos-lutdma-remap: This array is used to program vbif qos remapper register
+ priority for lutdma client.
+- qcom,sde-danger-lut: Array of 5 cell property, with a format of
+ <linear, tile, nrt, cwb, tile-qseed>,
+ indicating the danger luts on sspp.
+- qcom,sde-safe-lut-linear: Array of 2 cell property, with a format of
+ <fill level, lut> in ascending fill level
+ indicating the safe luts for linear format on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-safe-lut-macrotile: Array of 2 cell property, with a format of
+ <fill level, lut> in ascending fill level
+ indicating the safe luts for macrotile format on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-safe-lut-macrotile-qseed: Array of 2 cell property, with a format of
+ <fill level, lut> in ascending fill level
+ indicating the safe luts for macrotile format
+ with qseed3 on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-safe-lut-nrt: Array of 2 cell property, with a format of
+ <fill level, lut> in ascending fill level
+ indicating the safe luts for nrt (e.g wfd) on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-safe-lut-cwb: Array of 2 cell property, with a format of
+ <fill level, lut> in ascending fill level
+ indicating the safe luts for cwb on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-qos-lut-linear: Array of 3 cell property, with a format of
+ <fill level, lut hi, lut lo> in ascending fill level
+ indicating the qos luts for linear format on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-qos-lut-macrotile: Array of 3 cell property, with a format of
+ <fill level, lut hi, lut lo> in ascending fill level
+ indicating the qos luts for macrotile format on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-qos-lut-macrotile-qseed: Array of 3 cell property, with a format of
+ <fill level, lut hi, lut lo> in ascending fill level
+ indicating the qos luts for macrotile format
+ with qseed3 enabled on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-qos-lut-nrt: Array of 3 cell property, with a format of
+ <fill level, lut hi, lut lo> in ascending fill level
+ indicating the qos luts for nrt (e.g wfd) on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-qos-lut-cwb: Array of 3 cell property, with a format of
+ <fill level, lut hi, lut lo> in ascending fill level
+ indicating the qos luts for cwb on sspp.
+ Zero fill level on the last entry identifies the default lut.
+- qcom,sde-cdp-setting: Array of 2 cell property, with a format of
+ <read enable, write enable> for cdp use cases in
+ order of <real_time>, and <non_real_time>.
+- qcom,sde-qos-cpu-mask: A u32 value indicating desired PM QoS CPU affine mask.
+- qcom,sde-qos-cpu-dma-latency: A u32 value indicating desired PM QoS CPU DMA latency in usec.
+- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
+ rotation.
+- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
+ namely sspp or wb. Number of entries should match
+ the number of xin-ids defined in
+ property: qcom,sde-inline-rot-xin
+- qcom,sde-inline-rot-clk-ctrl: Array of offsets describing clk control
+ offsets for dynamic clock gating. 1st value
+ in the array represents offset of the control
+ register. 2nd value represents bit offset within
+ control register. Number of offsets defined should
+ match the number of xin-ids defined in
+ property: qcom,sde-inline-rot-xin
+- qcom,sde-secure-sid-mask: Array of secure SID masks used during
+ secure-camera/secure-display usecases.
+- #power-domain-cells: Number of cells in a power-domain specifier and should contain 0.
+- #list-cells: Number of mdp cells, must be 1.
+- qcom,sde-mixer-display-pref: A string array indicating the preferred display type
+ for the mixer block. Possible values:
+ "primary" - preferred for primary display
+ "none" - no preference on display
+- qcom,sde-mixer-cwb-pref: A string array indicating the preferred mixer block.
+ for CWB. Possible values:
+ "cwb" - preferred for cwb
+ "none" - no preference on display
+- qcom,sde-ctl-display-pref: A string array indicating the preferred display type
+ for the ctl block. Possible values:
+ "primary" - preferred for primary display
+ "none" - no preference on display
+- qcom,sde-pipe-order-version: A u32 property to indicate version of pipe
+ ordering block
+ 0: lower priority pipe has to be on the left for a given pair of pipes.
+ 1: priority have to be explicitly configured for a given pair of pipes.
+
+Bus Scaling Subnodes:
+- qcom,sde-reg-bus: Property to provide Bus scaling for register access for
+ mdss blocks.
+- qcom,sde-data-bus: Property to provide Bus scaling for data bus access for
+ mdss blocks.
+- qcom,sde-llcc-bus: Property to provide Bus scaling for data bus access for
+ mnoc to llcc.
+- qcom,sde-ebi-bus: Property to provide Bus scaling for data bus access for
+ llcc to ebi.
+
+- qcom,sde-inline-rotator: A 2 cell property, with format of (rotator phandle,
+ instance id), of inline rotator device.
+
+Bus Scaling Data:
+- qcom,msm-bus,name: String property describing client name.
+- qcom,msm-bus,num-cases: This is the number of Bus Scaling use cases
+ defined in the vectors property.
+- qcom,msm-bus,num-paths: This represents the number of paths in each
+ Bus Scaling Usecase.
+- qcom,msm-bus,vectors-KBps: * A series of 4 cell properties, with a format
+ of (src, dst, ab, ib) which is defined at
+ Documentation/devicetree/bindings/arm/msm/msm_bus.txt
+ * Current values of src & dst are defined at
+ include/linux/msm-bus-board.h
+
+SMMU Subnodes:
+- smmu_sde_****: Child nodes representing sde smmu virtual
+ devices
+
+Subnode properties:
+- compatible: Compatible names used for smmu devices.
+ names should be:
+ "qcom,smmu_sde_unsec": smmu context bank device
+ for unsecure sde real time domain.
+ "qcom,smmu_sde_sec": smmu context bank device
+ for secure sde real time domain.
+ "qcom,smmu_sde_nrt_unsec": smmu context bank device
+ for unsecure sde non-real time domain.
+ "qcom,smmu_sde_nrt_sec": smmu context bank device
+ for secure sde non-real time domain.
+
+
+Please refer to ../../interrupt-controller/interrupts.txt for a general
+description of interrupt bindings.
+
+Example:
+ mdss_mdp: qcom,mdss_mdp@900000 {
+ compatible = "qcom,sde-kms";
+ reg = <0x00900000 0x90000>,
+ <0x009b0000 0x1040>,
+ <0x009b8000 0x1040>,
+ <0x0aeac000 0x00f0>;
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "vbif_nrt_phys",
+ "regdma_phys";
+ clocks = <&clock_mmss clk_mdss_ahb_clk>,
+ <&clock_mmss clk_mdss_axi_clk>,
+ <&clock_mmss clk_mdp_clk_src>,
+ <&clock_mmss clk_mdss_mdp_vote_clk>,
+ <&clock_mmss clk_smmu_mdp_axi_clk>,
+ <&clock_mmss clk_mmagic_mdss_axi_clk>,
+ <&clock_mmss clk_mdss_vsync_clk>;
+ clock-names = "iface_clk",
+ "bus_clk",
+ "core_clk_src",
+ "core_clk",
+ "iommu_clk",
+ "mmagic_clk",
+ "vsync_clk";
+ clock-rate = <0>, <0>, <0>;
+ clock-max-rate= <0 320000000 0>;
+ mmagic-supply = <&gdsc_mmagic_mdss>;
+ vdd-supply = <&gdsc_mdss>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 83 0>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ iommus = <&mdp_smmu 0>;
+ #power-domain-cells = <0>;
+
+ qcom,sde-off = <0x1000>;
+ qcom,sde-ctl-off = <0x00002000 0x00002200 0x00002400
+ 0x00002600 0x00002800>;
+ qcom,sde-ctl-display-pref = "primary", "none", "none",
+ "none", "none";
+ qcom,sde-mixer-off = <0x00045000 0x00046000
+ 0x00047000 0x0004a000>;
+ qcom,sde-mixer-display-pref = "primary", "none",
+ "none", "none";
+ qcom,sde-mixer-cwb-pref = "none", "none",
+ "cwb", "none";
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-off = <0x00055000 0x00057000>;
+ qcom,sde-dspp-ad-off = <0x24000 0x22800>;
+ qcom,sde-dspp-ad-version = <0x00030000>;
+ qcom,sde-dest-scaler-top-off = <0x00061000>;
+ qcom,sde-dest-scaler-off = <0x800 0x1000>;
+ qcom,sde-wb-off = <0x00066000>;
+ qcom,sde-wb-xin-id = <6>;
+ qcom,sde-intf-off = <0x0006b000 0x0006b800
+ 0x0006c000 0x0006c800>;
+ qcom,sde-intf-type = "none", "dsi", "dsi", "hdmi";
+ qcom,sde-pp-off = <0x00071000 0x00071800
+ 0x00072000 0x00072800>;
+ qcom,sde-pp-slave = <0x0 0x0 0x0 0x0>;
+ qcom,sde-cdm-off = <0x0007a200>;
+ qcom,sde-dsc-off = <0x00081000 0x00081400>;
+ qcom,sde-intf-max-prefetch-lines = <0x15 0x15 0x15 0x15>;
+
+ qcom,sde-mixer-pair-mask = <2 1 6 0 0 3>;
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0 0xf8 0x110>;
+
+ qcom,sde-qdss-off = <0x81a00>;
+
+ qcom,sde-sspp-type = "vig", "vig", "vig",
+ "vig", "rgb", "rgb",
+ "rgb", "rgb", "dma",
+ "dma", "cursor", "cursor";
+
+ qcom,sde-sspp-off = <0x00005000 0x00007000 0x00009000
+ 0x0000b000 0x00015000 0x00017000
+ 0x00019000 0x0001b000 0x00025000
+ 0x00027000 0x00035000 0x00037000>;
+
+ qcom,sde-sspp-xin-id = <0 4 8
+ 12 1 5
+ 9 13 2
+ 10 7 7>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
+ <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
+ <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
+ <0x3b0 16>;
+ qcom,sde-sspp-clk-status = <0x2ac 0>, <0x2b4 0>, <0x2bc 0>,
+ <0x2c4 0>, <0x2ac 4>, <0x2b4 4>, <0x2bc 4>,
+ <0x2c4 4>, <0x2ac 8>, <0x2b4 8>, <0x3a8 16>,
+ <0x3b0 16>;
+ qcom,sde-mixer-linewidth = <2560>;
+ qcom,sde-sspp-linewidth = <2560>;
+ qcom,sde-mixer-blendstages = <0x7>;
+ qcom,sde-highest-bank-bit = <0x2>;
+ qcom,sde-ubwc-version = <0x100>;
+ qcom,sde-ubwc-static = <0x100>;
+ qcom,sde-ubwc-swizzle = <0>;
+ qcom,sde-ubwc-bw-calc-version = <0x1>;
+ qcom,sde-smart-panel-align-mode = <0xd>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-src-split;
+ qcom,sde-pipe-order-version = <0x1>;
+ qcom,sde-has-dim-layer;
+ qcom,sde-sspp-src-size = <0x100>;
+ qcom,sde-mixer-size = <0x100>;
+ qcom,sde-ctl-size = <0x100>;
+ qcom,sde-dspp-top-size = <0xc>;
+ qcom,sde-dspp-size = <0x100>;
+ qcom,sde-intf-size = <0x100>;
+ qcom,sde-dsc-size = <0x100>;
+ qcom,sde-cdm-size = <0x100>;
+ qcom,sde-pp-size = <0x100>;
+ qcom,sde-wb-size = <0x100>;
+ qcom,sde-dest-scaler-top-size = <0xc>;
+ qcom,sde-dest-scaler-size = <0x800>;
+ qcom,sde-len = <0x100>;
+ qcom,sde-wb-linewidth = <2560>;
+ qcom,sde-sspp-scale-size = <0x100>;
+ qcom,sde-mixer-blendstages = <0x8>;
+ qcom,sde-qseed-type = "qseedv2";
+ qcom,sde-csc-type = "csc-10bit";
+ qcom,sde-highest-bank-bit = <15>;
+ qcom,sde-has-mixer-gc;
+ qcom,sde-has-idle-pc;
+ qcom,fullsize-va-map;
+ qcom,sde-has-dest-scaler;
+ qcom,sde-max-dest-scaler-input-linewidth = <2048>;
+ qcom,sde-max-dest-scaler-output-linewidth = <2560>;
+ qcom,sde-sspp-max-rects = <1 1 1 1
+ 1 1 1 1
+ 1 1
+ 1 1>;
+ qcom,sde-sspp-excl-rect = <1 1 1 1
+ 1 1 1 1
+ 1 1
+ 1 1>;
+ qcom,sde-sspp-smart-dma-priority = <0 0 0 0
+ 0 0 0 0
+ 0 0
+ 1 2>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2";
+ qcom,sde-te-off = <0x100>;
+ qcom,sde-te2-off = <0x100>;
+ qcom,sde-te-size = <0xffff>;
+ qcom,sde-te2-size = <0xffff>;
+
+ qcom,sde-wb-id = <2>;
+ qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+
+ qcom,sde-danger-lut = <0x0000000f 0x0000ffff 0x00000000
+ 0x00000000 0x0000ffff>;
+ qcom,sde-safe-lut-linear = <0 0xfff8>;
+ qcom,sde-safe-lut-macrotile = <0 0xf000>;
+ qcom,sde-safe-lut-macrotile-qseed = <0 0xf000>;
+ qcom,sde-safe-lut-nrt = <0 0xffff>;
+ qcom,sde-safe-lut-cwb = <0 0xffff>;
+
+ qcom,sde-qos-lut-linear =
+ <4 0x00000000 0x00000357>,
+ <5 0x00000000 0x00003357>,
+ <6 0x00000000 0x00023357>,
+ <7 0x00000000 0x00223357>,
+ <8 0x00000000 0x02223357>,
+ <9 0x00000000 0x22223357>,
+ <10 0x00000002 0x22223357>,
+ <11 0x00000022 0x22223357>,
+ <12 0x00000222 0x22223357>,
+ <13 0x00002222 0x22223357>,
+ <14 0x00012222 0x22223357>,
+ <0 0x00112222 0x22223357>;
+ qcom,sde-qos-lut-macrotile =
+ <10 0x00000003 0x44556677>,
+ <11 0x00000033 0x44556677>,
+ <12 0x00000233 0x44556677>,
+ <13 0x00002233 0x44556677>,
+ <14 0x00012233 0x44556677>,
+ <0 0x00112233 0x44556677>;
+ qcom,sde-qos-lut-macrotile-qseed =
+ <0 0x00112233 0x66777777>;
+ qcom,sde-qos-lut-nrt =
+ <0 0x00000000 0x00000000>;
+ qcom,sde-qos-lut-cwb =
+ <0 0x75300000 0x00000000>;
+
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+
+ qcom,sde-vbif-off = <0 0>;
+ qcom,sde-vbif-id = <0 1>;
+ qcom,sde-vbif-default-ot-rd-limit = <32>;
+ qcom,sde-vbif-default-ot-wr-limit = <16>;
+ qcom,sde-vbif-dynamic-ot-rd-limit = <62208000 2>,
+ <124416000 4>, <248832000 16>;
+ qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2>,
+ <124416000 4>, <248832000 16>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-uidle-off = <0x80000>;
+ qcom,sde-uidle-size = <0x70>;
+
+ qcom,sde-dram-channels = <2>;
+ qcom,sde-num-nrt-paths = <1>;
+
+ qcom,sde-max-bw-high-kbps = <9000000>;
+ qcom,sde-max-bw-low-kbps = <9000000>;
+
+ qcom,sde-core-ib-ff = "1.1";
+ qcom,sde-core-clk-ff = "1.0";
+ qcom,sde-min-core-ib-kbps = <2400000>;
+ qcom,sde-min-llcc-ib-kbps = <800000>;
+ qcom,sde-min-dram-ib-kbps = <800000>;
+ qcom,sde-comp-ratio-rt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3";
+ qcom,sde-comp-ratio-nrt = "NV12/5/1/1.1 AB24/5/1/1.2 XB24/5/1/1.3";
+ qcom,sde-undersized-prefill-lines = <4>;
+ qcom,sde-xtra-prefill-lines = <5>;
+ qcom,sde-dest-scale-prefill-lines = <6>;
+ qcom,sde-macrotile-prefill-lines = <7>;
+ qcom,sde-yuv-nv12-prefill-lines = <8>;
+ qcom,sde-linear-prefill-lines = <9>;
+ qcom,sde-downscaling-prefill-lines = <10>;
+ qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000
+ 2400000 2400000 2400000 2400000>;
+ qcom,sde-amortizable-threshold = <11>;
+ qcom,sde-secure-sid-mask = <0x200801 0x200c01>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
+ qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
+
+ qcom,sde-reg-dma-off = <0>;
+ qcom,sde-reg-dma-version = <0x00010002>;
+ qcom,sde-reg-dma-trigger-off = <0x119c>;
+ qcom,sde-reg-dma-broadcast-disabled = <0>;
+ qcom,sde-reg-dma-xin-id = <7>;
+ qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
+
+ qcom,sde-sspp-vig-blocks {
+ qcom,sde-vig-csc-off = <0x320>;
+ qcom,sde-vig-qseed-off = <0x200>;
+ qcom,sde-vig-qseed-size = <0x74>;
+ /* Offset from vig top, version of HSIC */
+ qcom,sde-vig-hsic = <0x200 0x00010000>;
+ qcom,sde-vig-memcolor = <0x200 0x00010000>;
+ qcom,sde-vig-pcc = <0x1780 0x00010000>;
+ qcom,sde-vig-inverse-pma;
+ };
+
+ qcom,sde-sspp-dma-blocks {
+ dgm@0 {
+ qcom,sde-dma-igc = <0x400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x200>;
+ }
+ dgm@1 {
+ qcom,sde-dma-igc = <0x1400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x1200>;
+ }
+ };
+
+ qcom,sde-sspp-rgb-blocks {
+ qcom,sde-rgb-scaler-off = <0x200>;
+ qcom,sde-rgb-scaler-size = <0x74>;
+ qcom,sde-rgb-pcc = <0x380 0x00010000>;
+ };
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00010000>;
+ qcom,sde-dspp-pcc = <0x1700 0x00010000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010000>;
+ qcom,sde-dspp-hsic = <0x0 0x00010000>;
+ qcom,sde-dspp-memcolor = <0x0 0x00010000>;
+ qcom,sde-dspp-sixzone = <0x0 0x00010000>;
+ qcom,sde-dspp-gamut = <0x1600 0x00010000>;
+ qcom,sde-dspp-dither = <0x0 0x00010000>;
+ qcom,sde-dspp-hist = <0x0 0x00010000>;
+ qcom,sde-dspp-vlut = <0x0 0x00010000>;
+ };
+
+ qcom,sde-mixer-blocks {
+ qcom,sde-mixer-gc = <0x3c0 0x00010000>;
+ };
+
+ qcom,msm-hdmi-audio-rx {
+ compatible = "qcom,msm-hdmi-audio-codec-rx";
+ };
+
+ qcom,sde-inline-rotator = <&mdss_rotator 0>;
+ qcom,sde-inline-rot-xin = <10 11>;
+ qcom,sde-inline-rot-xin-type = "sspp", "wb";
+ qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ qcom,supply-pre-on-sleep = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ qcom,supply-pre-off-sleep = <0>;
+ qcom,supply-post-off-sleep = <0>;
+ };
+ };
+
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>, <25 512 0 0>,
+ <22 512 0 6400000>, <23 512 0 6400000>,
+ <25 512 0 6400000>,
+ <22 512 0 6400000>, <23 512 0 6400000>,
+ <25 512 0 6400000>;
+ };
+ qcom,sde-llcc-bus {
+ qcom,msm-bus,name = "mdss_sde_llcc";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <132 770 0 0>,
+ <132 770 0 6400000>,
+ <132 770 0 6400000>;
+ };
+ qcom,sde-ebi-bus {
+ qcom,msm-bus,name = "mdss_sde_ebi";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <129 512 0 0>,
+ <129 512 0 6400000>,
+ <129 512 0 6400000>;
+ };
+
+ qcom,sde-reg-bus {
+ /* Reg Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 160000>,
+ <1 590 0 320000>;
+ };
+
+ smmu_kms_unsec: qcom,smmu_kms_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&mmss_smmu 0>;
+ };
+
+ smmu_kms_sec: qcom,smmu_kms_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&mmss_smmu 1>;
+ };
+ };
diff --git a/display/dsi-panel-ext-bridge-1080p.dtsi b/display/dsi-panel-ext-bridge-1080p.dtsi
new file mode 100644
index 0000000..07d398e
--- /dev/null
+++ b/display/dsi-panel-ext-bridge-1080p.dtsi
@@ -0,0 +1,46 @@
+&mdss_mdp {
+ dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p {
+ qcom,mdss-dsi-panel-name = "ext video mode dsi bridge";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-t-clk-post = <0x03>;
+ qcom,mdss-dsi-t-clk-pre = <0x24>;
+ qcom,mdss-dsi-force-clock-lane-hs;
+ qcom,mdss-dsi-ext-bridge-mode;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1920>;
+ qcom,mdss-dsi-panel-height = <1080>;
+ qcom,mdss-dsi-h-front-porch = <88>;
+ qcom,mdss-dsi-h-back-porch = <148>;
+ qcom,mdss-dsi-h-pulse-width = <44>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <36>;
+ qcom,mdss-dsi-v-front-porch = <4>;
+ qcom,mdss-dsi-v-pulse-width = <5>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi b/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi
new file mode 100644
index 0000000..9dc1a26
--- /dev/null
+++ b/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi
@@ -0,0 +1,151 @@
+&mdss_mdp {
+ dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video {
+ qcom,mdss-dsi-panel-name =
+ "hx83112a video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <65>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <42>;
+ qcom,mdss-dsi-h-back-porch = <42>;
+ qcom,mdss-dsi-h-pulse-width = <10>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <15>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <3>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04 B9 83 11 2A
+ 39 01 00 00 00 00 09 B1 08 29 29 00 00 4F 54
+ 33
+ 39 01 00 00 00 00 11 B2 00 02 00 80 70 00 08
+ 26 FC 01 00 03 15 A3 87 09
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 03 D2 2C 2C
+ 39 01 00 00 00 00 1C B4 01 CE 01 CE 01 CE 0A
+ CE 0A CE 0A CE 00 FF 00 FF 00 00 22 23 00
+ 28 0A 13 14 00 8A
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0A B4 00 92 12 22 88 12 12
+ 00 53
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 04 B6 82 82 E3
+ 39 01 00 00 00 00 02 CC 08
+ 39 01 00 00 00 00 2B D3 40 00 00 00 00 01 01
+ 0A 0A 07 07 00 08 09 09 09 09 32 10 09 00
+ 09 32 21 0A 00 0A 32 10 08 00 00 00 00 00
+ 00 00 00 00 0B 08 82
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 09 D3 00 00 19 00 00 0A 00
+ 81
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18
+ 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
+ 18 40 40 01 00 07 06 05 04 03 02 21 20 18
+ 18 19 19 18 18 03 03 18 18 18 18 18 18
+ 39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18
+ 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
+ 18 40 40 02 03 04 05 06 07 00 01 20 21 18
+ 18 18 18 19 19 20 20 18 18 18 18 18 18
+ 39 01 00 00 00 00 19 D8 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
+ AA AA AA AA AA AA AA AA AA AA AA AA AA AA
+ AA AA AA
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0D D8 AF FF FA AA BA AA AA
+ FF FA AA BA AA
+ 39 01 00 00 00 00 02 BD 03
+ 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
+ AA AA AA AA AA AA AA AA AA AA AA AA AA AA
+ AA AA AA
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 18 E7 0E 0E 1E 6A 1D 6A 00
+ 32 02 02 00 00 02 02 02 05 14 14 32 B9 23
+ B9 08
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 0A E7 02 00 98 01 9A 0D A8
+ 0E 01
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 04 00 00 00 00 02 00
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 C1 01
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 03
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 E9 C3
+ 39 01 00 00 00 00 03 CB 92 01
+ 39 01 00 00 00 00 02 E9 3F
+ 39 01 00 00 00 00 07 C7 70 00 04 E0 33 00
+ 39 01 00 00 00 00 03 51 0F FF
+ 39 01 00 00 00 00 02 53 24
+ 39 01 00 00 00 00 02 55 00
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-hx8394d-720p-video.dtsi b/display/dsi-panel-hx8394d-720p-video.dtsi
new file mode 100644
index 0000000..6de6c6c
--- /dev/null
+++ b/display/dsi-panel-hx8394d-720p-video.dtsi
@@ -0,0 +1,87 @@
+&mdss_mdp {
+ dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video {
+ qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <52>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <24>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04 b9 ff 83 94
+ 39 01 00 00 00 00 03 ba 33 83
+ 39 01 00 00 00 00 10 b1 6c 12 12
+ 37 04 11 f1 80 ec 94 23 80 c0
+ d2 18
+ 39 01 00 00 00 00 0c b2 00 64 0e
+ 0d 32 23 08 08 1c 4d 00
+ 39 01 00 00 00 00 0d b4 00 ff 03
+ 50 03 50 03 50 01 6a 01 6a
+ 39 01 00 00 00 00 02 bc 07
+ 39 01 00 00 00 00 04 bf 41 0e 01
+ 39 01 00 00 00 00 1f d3 00 07 00
+ 00 00 10 00 32 10 05 00 00 32
+ 10 00 00 00 32 10 00 00 00 36
+ 03 09 09 37 00 00 37
+ 39 01 00 00 00 00 2d d5 02 03 00
+ 01 06 07 04 05 20 21 22 23 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 24 25 18 18 19
+ 19
+ 39 01 00 00 00 00 2d d6 05 04 07
+ 06 01 00 03 02 23 22 21 20 18
+ 18 18 18 18 18 58 58 18 18 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 25 24 19 19 18
+ 18
+ 39 01 00 00 00 00 02 cc 09
+ 39 01 00 00 00 00 03 c0 30 14
+ 39 01 00 00 00 00 05 c7 00 c0 40 c0
+ 39 01 00 00 00 00 03 b6 43 43
+ 05 01 00 00 c8 00 02 11 00
+ 05 01 00 00 0a 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [
+ 79 1a 12 00 3e 42
+ 16 1e 15 03 04 00
+ ];
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1b>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <59>;
+ qcom,mdss-pan-physical-height-dimension = <104>;
+
+ };
+};
diff --git a/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi b/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi
new file mode 100644
index 0000000..8a05258
--- /dev/null
+++ b/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi
@@ -0,0 +1,240 @@
+&mdss_mdp {
+ dsi_nt35597_truly_dsc_cmd: qcom,mdss_dsi_nt35597_dsc_cmd_truly {
+ qcom,mdss-dsi-panel-name =
+ "nt35597 cmd mode dsi truly panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <1>;
+ qcom,dsi-phy-num = <1>;
+ qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x1 0x1>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f ae
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6D
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c D8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 C0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi
new file mode 100644
index 0000000..2d888cb
--- /dev/null
+++ b/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi
@@ -0,0 +1,226 @@
+&mdss_mdp {
+ dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_video_truly {
+ qcom,mdss-dsi-panel-name =
+ "nt35597 video mode dsi truly panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <1>;
+ qcom,dsi-phy-num = <1>;
+ qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-dma-schedule-line = <5>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x00(2 Port SDC);
+ * 0x01(1 PortA FBC);
+ * 0x02(MTK); 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 39 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 03
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi
new file mode 100644
index 0000000..cddf916
--- /dev/null
+++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi
@@ -0,0 +1,219 @@
+&mdss_mdp {
+ dsi_dual_nt35597_truly_cmd: qcom,mdss_dsi_nt35597_truly_wqxga_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt35597 cmd mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x1 0x1>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi
new file mode 100644
index 0000000..aff6950
--- /dev/null
+++ b/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi
@@ -0,0 +1,206 @@
+&mdss_mdp {
+ dsi_dual_nt35597_truly_video: qcom,mdss_dsi_nt35597_wqxga_video_truly {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt35597 video mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-underflow-color = <0x3ff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 FF 24
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 FF 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 03
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi b/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi
new file mode 100644
index 0000000..ffefa6a
--- /dev/null
+++ b/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi
@@ -0,0 +1,185 @@
+&mdss_mdp {
+ dsi_nt35695b_truly_fhd_cmd: qcom,mdss_dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "nt35695b truly fhd command mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,dsi-sec-ctrl-num = <1>;
+ qcom,dsi-sec-phy-num = <1>;
+ qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14
+ 00 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-nt35695b-truly-fhd-video.dtsi b/display/dsi-panel-nt35695b-truly-fhd-video.dtsi
new file mode 100644
index 0000000..fe84525
--- /dev/null
+++ b/display/dsi-panel-nt35695b-truly-fhd-video.dtsi
@@ -0,0 +1,177 @@
+&mdss_mdp {
+ dsi_nt35695b_truly_fhd_video: qcom,mdss_dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-panel-name =
+ "nt35695b truly fhd video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 03
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00
+ 14 00 02 28 00 05 01 00 00 78 00
+ 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi b/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
new file mode 100644
index 0000000..d066925
--- /dev/null
+++ b/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
@@ -0,0 +1,80 @@
+&mdss_mdp {
+ dsi_dual_nt36850_truly_cmd: qcom,mdss_dsi_nt36850_truly_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt36850 cmd mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 50>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <140>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 03 44 03 e8
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 2c
+ 15 01 00 00 00 00 02 55 01
+ 05 01 00 00 0a 00 02 20 00
+ 15 01 00 00 00 00 02 bb 10
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi b/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi
new file mode 100644
index 0000000..11eb3a3
--- /dev/null
+++ b/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi
@@ -0,0 +1,129 @@
+&mdss_mdp {
+ dsi_dual_s6e3ha3_amoled_cmd: qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual s6e3ha3 amoled cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <31>;
+ qcom,mdss-dsi-v-front-porch = <30>;
+ qcom,mdss-dsi-v-pulse-width = <8>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00
+ 39 01 00 00 00 00 05 2a 00 00 05 9f
+ 39 01 00 00 00 00 05 2b 00 00 09 ff
+ 39 01 00 00 00 00 03 f0 5a 5a
+ 39 01 00 00 00 00 02 b0 10
+ 39 01 00 00 00 00 02 b5 a0
+ 39 01 00 00 00 00 02 c4 03
+ 39 01 00 00 00 00 0a
+ f6 42 57 37 00 aa cc d0 00 00
+ 39 01 00 00 00 00 02 f9 03
+ 39 01 00 00 00 00 14
+ c2 00 00 d8 d8 00 80 2b 05 08
+ 0e 07 0b 05 0d 0a 15 13 20 1e
+ 39 01 00 00 78 00 03 f0 a5 a5
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 53 20
+ 39 01 00 00 00 00 02 51 60
+ 05 01 00 00 05 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00
+ 05 01 00 00 b4 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a
+ 39 00 00 00 05 00 03 f1 5a 5a
+ 39 00 00 00 05 00 03 fc 5a 5a
+ 39 00 00 00 05 00 02 b0 17
+ 39 00 00 00 05 00 02 cb 10
+ 39 00 00 00 05 00 02 b0 2d
+ 39 00 00 00 05 00 02 cb cd
+ 39 00 00 00 05 00 02 b0 0e
+ 39 00 00 00 05 00 02 cb 02
+ 39 00 00 00 05 00 02 b0 0f
+ 39 00 00 00 05 00 02 cb 09
+ 39 00 00 00 05 00 02 b0 02
+ 39 00 00 00 05 00 02 f2 c9
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f2 c0
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f4 aa
+ 39 00 00 00 05 00 02 b0 08
+ 39 00 00 00 05 00 02 b1 30
+ 39 00 00 00 05 00 02 b0 09
+ 39 00 00 00 05 00 02 b1 0a
+ 39 00 00 00 05 00 02 b0 0d
+ 39 00 00 00 05 00 02 b1 10
+ 39 00 00 00 05 00 02 b0 00
+ 39 00 00 00 05 00 02 f7 03
+ 39 00 00 00 05 00 02 fe 30
+ 39 01 00 00 05 00 02 fe b0];
+ qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a
+ 39 00 00 00 05 00 03 f1 5a 5a
+ 39 00 00 00 05 00 03 fc 5a 5a
+ 39 00 00 00 05 00 02 b0 2d
+ 39 00 00 00 05 00 02 cb 4d
+ 39 00 00 00 05 00 02 b0 17
+ 39 00 00 00 05 00 02 cb 04
+ 39 00 00 00 05 00 02 b0 0e
+ 39 00 00 00 05 00 02 cb 06
+ 39 00 00 00 05 00 02 b0 0f
+ 39 00 00 00 05 00 02 cb 05
+ 39 00 00 00 05 00 02 b0 02
+ 39 00 00 00 05 00 02 f2 b8
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f2 80
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f4 8a
+ 39 00 00 00 05 00 02 b0 08
+ 39 00 00 00 05 00 02 b1 10
+ 39 00 00 00 05 00 02 b0 09
+ 39 00 00 00 05 00 02 b1 0a
+ 39 00 00 00 05 00 02 b0 0d
+ 39 00 00 00 05 00 02 b1 80
+ 39 00 00 00 05 00 02 b0 00
+ 39 00 00 00 05 00 02 f7 03
+ 39 00 00 00 05 00 02 fe 30
+ 39 01 00 00 05 00 02 fe b0];
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <122>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ };
+};
diff --git a/display/dsi-panel-sharp-1080p-cmd.dtsi b/display/dsi-panel-sharp-1080p-cmd.dtsi
new file mode 100644
index 0000000..8ffa0eb
--- /dev/null
+++ b/display/dsi-panel-sharp-1080p-cmd.dtsi
@@ -0,0 +1,79 @@
+&mdss_mdp {
+ dsi_sharp_1080_cmd: qcom,mdss_dsi_sharp_1080p_cmd {
+ qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,mdss-dsi-panel-clockrate = <850000000>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <64>;
+ qcom,mdss-pan-physical-height-dimension = <117>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi
new file mode 100644
index 0000000..89df5ff
--- /dev/null
+++ b/display/dsi-panel-sharp-dsc-4k-cmd.dtsi
@@ -0,0 +1,96 @@
+&mdss_mdp {
+ dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd {
+ qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
+ qcom,mdss-pan-physical-width-dimension = <71>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x8 0xa>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sharp-dsc-4k-video.dtsi b/display/dsi-panel-sharp-dsc-4k-video.dtsi
new file mode 100644
index 0000000..feb5540
--- /dev/null
+++ b/display/dsi-panel-sharp-dsc-4k-video.dtsi
@@ -0,0 +1,89 @@
+&mdss_mdp {
+ dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video {
+ qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
+ qcom,mdss-pan-physical-width-dimension = <71>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+ qcom,mdss-dsi-tx-eot-append;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 10
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi b/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi
new file mode 100644
index 0000000..c909864
--- /dev/null
+++ b/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi
@@ -0,0 +1,86 @@
+&mdss_mdp {
+ dsi_dual_sharp_wqhd_cmd: qcom,mdss_dsi_sharp_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual Sharp WQHD cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <121>;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09
+ 20 00 20 02 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ 15 01 00 00 00 00 02 90 01
+ 15 01 00 00 00 00 02 03 00
+ 15 01 00 00 00 00 02 58 01
+ 15 01 00 00 00 00 02 c9 00
+ 15 01 00 00 00 00 02 c0 15
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi b/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi
new file mode 100644
index 0000000..3733007
--- /dev/null
+++ b/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi
@@ -0,0 +1,82 @@
+&mdss_mdp {
+ dsi_dual_sharp_wqhd_video: qcom,mdss_dsi_sharp_wqhd_video {
+ qcom,mdss-dsi-panel-name =
+ "Dual Sharp wqhd video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <121>;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09
+ 20 00 20 02 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 10
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ 15 01 00 00 00 00 02 90 01
+ 15 01 00 00 00 00 02 03 00
+ 15 01 00 00 00 00 02 58 01
+ 15 01 00 00 00 00 02 c9 00
+ 15 01 00 00 00 00 02 c0 15
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ };
+ };
+ };
+};
+
diff --git a/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi b/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
new file mode 100644
index 0000000..06a95ca
--- /dev/null
+++ b/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
@@ -0,0 +1,626 @@
+&mdss_mdp {
+ dsi_dual_sharp_1080_120hz_cmd: qcom,mdss_dual_sharp_1080p_120hz_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sharp 1080p 120hz dual dsi cmd mode panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 10>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,cmd-sync-wait-trigger;
+ qcom,mdss-tear-check-frame-rate = <12000>;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <28>;
+ qcom,mdss-dsi-h-back-porch = <4>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ba 07
+ 15 01 00 00 00 00 02 c0 00
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 d9 00
+ 15 01 00 00 00 00 02 ef 70
+ 15 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 06 3b 03 0e 0c 08 1c
+ 15 01 00 00 00 00 02 e9 0e
+ 15 01 00 00 00 00 02 ea 0c
+ 15 01 00 00 00 00 02 35 00
+ 15 01 00 00 00 00 02 c0 00
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 59 6a
+ 15 01 00 00 00 00 02 0b 1b
+ 15 01 00 00 00 00 02 61 f7
+ 15 01 00 00 00 00 02 62 6c
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 04 c8
+ 15 01 00 00 00 00 02 05 1a
+ 15 01 00 00 00 00 02 0d 93
+ 15 01 00 00 00 00 02 0e 93
+ 15 01 00 00 00 00 02 0f 7e
+ 15 01 00 00 00 00 02 06 69
+ 15 01 00 00 00 00 02 07 bc
+ 15 01 00 00 00 00 02 10 03
+ 15 01 00 00 00 00 02 11 64
+ 15 01 00 00 00 00 02 12 5a
+ 15 01 00 00 00 00 02 13 40
+ 15 01 00 00 00 00 02 14 40
+ 15 01 00 00 00 00 02 15 00
+ 15 01 00 00 00 00 02 33 13
+ 15 01 00 00 00 00 02 5a 40
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+ 15 01 00 00 00 00 02 5e 80
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 80
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+ 15 01 00 00 00 00 02 04 06
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+ 15 01 00 00 00 00 02 af 00
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+ 15 01 00 00 00 00 02 b3 00
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+ 15 01 00 00 00 00 02 b5 00
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+ 15 01 00 00 00 00 02 bb 00
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+ 15 01 00 00 00 00 02 c3 01
+ 15 01 00 00 00 00 02 c4 5b
+ 15 01 00 00 00 00 02 c5 01
+ 15 01 00 00 00 00 02 c6 95
+ 15 01 00 00 00 00 02 c7 01
+ 15 01 00 00 00 00 02 c8 c4
+ 15 01 00 00 00 00 02 c9 02
+ 15 01 00 00 00 00 02 ca 0d
+ 15 01 00 00 00 00 02 cb 02
+ 15 01 00 00 00 00 02 cc 4a
+ 15 01 00 00 00 00 02 cd 02
+ 15 01 00 00 00 00 02 ce 4c
+ 15 01 00 00 00 00 02 cf 02
+ 15 01 00 00 00 00 02 d0 85
+ 15 01 00 00 00 00 02 d1 02
+ 15 01 00 00 00 00 02 d2 c3
+ 15 01 00 00 00 00 02 d3 02
+ 15 01 00 00 00 00 02 d4 e9
+ 15 01 00 00 00 00 02 d5 03
+ 15 01 00 00 00 00 02 d6 16
+ 15 01 00 00 00 00 02 d7 03
+ 15 01 00 00 00 00 02 d8 34
+ 15 01 00 00 00 00 02 d9 03
+ 15 01 00 00 00 00 02 da 56
+ 15 01 00 00 00 00 02 db 03
+ 15 01 00 00 00 00 02 dc 62
+ 15 01 00 00 00 00 02 dd 03
+ 15 01 00 00 00 00 02 de 6c
+ 15 01 00 00 00 00 02 df 03
+ 15 01 00 00 00 00 02 e0 74
+ 15 01 00 00 00 00 02 e1 03
+ 15 01 00 00 00 00 02 e2 80
+ 15 01 00 00 00 00 02 e3 03
+ 15 01 00 00 00 00 02 e4 89
+ 15 01 00 00 00 00 02 e5 03
+ 15 01 00 00 00 00 02 e6 8b
+ 15 01 00 00 00 00 02 e7 03
+ 15 01 00 00 00 00 02 e8 8d
+ 15 01 00 00 00 00 02 e9 03
+ 15 01 00 00 00 00 02 ea 8e
+ 15 01 00 00 00 00 02 FF 10
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-off-command =
+ [15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 10 00 01 28
+ 15 01 00 00 00 00 02 b0 00
+ 05 01 00 00 40 00 01 10
+ 15 01 00 00 00 00 02 4f 01];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sim-cmd.dtsi b/display/dsi-panel-sim-cmd.dtsi
new file mode 100644
index 0000000..f62ce3b
--- /dev/null
+++ b/display/dsi-panel-sim-cmd.dtsi
@@ -0,0 +1,347 @@
+&mdss_mdp {
+ dsi_sim_cmd: qcom,mdss_dsi_sim_cmd {
+ qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-mode-switch;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-t-clk-post = <0x03>;
+ qcom,mdss-dsi-t-clk-pre = <0x27>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-cmd-mode;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,cmd-to-video-mode-switch-commands = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 10
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 0c
+ ];
+ qcom,cmd-to-video-mode-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-video-mode;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,video-to-cmd-mode-switch-commands = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 11
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 0b
+ ];
+ qcom,video-to-cmd-mode-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <460>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <740>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <840>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <1380>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi
new file mode 100644
index 0000000..310ce40
--- /dev/null
+++ b/display/dsi-panel-sim-dsc-10bit-cmd.dtsi
@@ -0,0 +1,474 @@
+&mdss_mdp {
+ dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Simulator cmd mode DSC3:1 10bit dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <30>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sim-dsc375-cmd.dtsi b/display/dsi-panel-sim-dsc375-cmd.dtsi
new file mode 100644
index 0000000..ef40a2e
--- /dev/null
+++ b/display/dsi-panel-sim-dsc375-cmd.dtsi
@@ -0,0 +1,280 @@
+&mdss_mdp {
+ dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Simulator cmd mode DSC 3.75:1 dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sim-dualmipi-cmd.dtsi b/display/dsi-panel-sim-dualmipi-cmd.dtsi
new file mode 100644
index 0000000..5f4be88
--- /dev/null
+++ b/display/dsi-panel-sim-dualmipi-cmd.dtsi
@@ -0,0 +1,141 @@
+&mdss_mdp {
+ dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd {
+ qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-hor-line-idle = <0 40 256>,
+ <40 120 128>,
+ <120 240 64>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <45>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <28>;
+ qcom,mdss-dsi-h-back-porch = <4>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1280>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <44>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <40>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi
new file mode 100644
index 0000000..87b4a76
--- /dev/null
+++ b/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi
@@ -0,0 +1,327 @@
+&mdss_mdp {
+ dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Sim dual cmd mode DSC 3.75:1 dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-hor-line-idle = <0 40 256>,
+ <40 120 128>,
+ <120 240 64>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <2520>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <1080>;
+ qcom,mdss-dsc-slice-width = <1260>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sim-dualmipi-video.dtsi b/display/dsi-panel-sim-dualmipi-video.dtsi
new file mode 100644
index 0000000..3bee9f6
--- /dev/null
+++ b/display/dsi-panel-sim-dualmipi-video.dtsi
@@ -0,0 +1,63 @@
+&mdss_mdp {
+ dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video {
+ qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-panel-broadcast-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <45>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1280>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <44>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sim-sec-hd-cmd.dtsi b/display/dsi-panel-sim-sec-hd-cmd.dtsi
new file mode 100644
index 0000000..e9d3135
--- /dev/null
+++ b/display/dsi-panel-sim-sec-hd-cmd.dtsi
@@ -0,0 +1,68 @@
+&mdss_mdp {
+ dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sim hd command mode secondary dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-sec-ctrl-num = <1>;
+ qcom,dsi-sec-phy-num = <1>;
+ qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sim-video.dtsi b/display/dsi-panel-sim-video.dtsi
new file mode 100644
index 0000000..5a2ac01
--- /dev/null
+++ b/display/dsi-panel-sim-video.dtsi
@@ -0,0 +1,62 @@
+&mdss_mdp {
+ dsi_sim_vid: qcom,mdss_dsi_sim_video {
+ qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1b>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <640>;
+ qcom,mdss-dsi-panel-height = <480>;
+ qcom,mdss-dsi-h-front-porch = <8>;
+ qcom,mdss-dsi-h-back-porch = <8>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <6>;
+ qcom,mdss-dsi-v-front-porch = <6>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 00 00 00 00 00 00 00 00 00 00 00];
+ qcom,mdss-dsi-on-command =
+ [32 01 00 00 00 00 02 00 00];
+ qcom,mdss-dsi-off-command =
+ [22 01 00 00 00 00 02 00 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi
new file mode 100644
index 0000000..6195f8c
--- /dev/null
+++ b/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi
@@ -0,0 +1,103 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_fhd_plus_cmd: qcom,mdss_dsi_sw43404_fhd_plus_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled boe fhd+ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <138>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <160>;
+ qcom,mdss-dsi-h-back-porch = <72>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 08 70 04 38 02 1c 02 1c 02 1c 02 00
+ 02 0e 00 20 34 29 00 07 00 0C 00 2e
+ 00 31 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 5e 10
+ 39 01 00 00 00 00 06 b9 bf 11 40 00 30
+ 39 01 00 00 00 00 09 F8 00 08 10 08 2D
+ 00 00 2D
+ 15 01 00 00 00 00 02 55 08
+ 05 01 00 00 1e 00 02 11 00
+ 15 01 00 00 78 00 02 3d 01
+ 39 01 00 00 00 00 03 b0 a5 00
+ 05 01 00 00 78 00 02 35 00
+ 05 01 00 00 3c 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <270>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi
new file mode 100644
index 0000000..032fc39
--- /dev/null
+++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi
@@ -0,0 +1,121 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_cmd: qcom,mdss_dsi_sw43404_amoled_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled cmd mode dsi boe panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2880>;
+ qcom,mdss-dsi-h-front-porch = <60>;
+ qcom,mdss-dsi-h-back-porch = <30>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 03 5c 42 00
+ 07 01 00 00 00 00 02 01 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 0B 40 05 A0 05 A0 02 D0 02 D0 02 00
+ 02 68 00 20 9A DB 00 0A 00 0C 00 12
+ 00 0E 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 09 F8 00 08 10 08 2D
+ 00 00 2D
+ 15 01 00 00 00 00 02 55 08
+ 05 01 00 00 1e 00 02 11 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 e0 18
+ 39 01 00 00 00 00 0c c0 00 53 6f 51 50
+ 51 34 4f 5a 33 19
+ 05 01 00 00 78 00 02 35 00
+ 05 01 00 00 3c 00 02 29 00
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 5a 01];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 5a 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-lp1-command = [
+ 05 01 00 00 00 00 02 39 00
+ ];
+ qcom,mdss-dsi-lp1-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command = [
+ 05 01 00 00 00 00 02 38 00
+ ];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <180>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi
new file mode 100644
index 0000000..37c0dfc
--- /dev/null
+++ b/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi
@@ -0,0 +1,101 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_video: qcom,mdss_dsi_sw43404_amoled_wqhd_video {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled video mode dsi boe panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2880>;
+ qcom,mdss-dsi-h-front-porch = <10>;
+ qcom,mdss-dsi-h-back-porch = <10>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 10
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 08
+ 39 01 00 00 00 00 09 f8 00 08 10 08 2d
+ 00 00 2d
+ 39 01 00 00 3c 00 03 51 00 00
+ 05 01 00 00 50 00 02 11 00
+ 39 01 00 00 00 00 03 b0 34 04
+ 39 01 00 00 00 00 05 c1 00 00 00 46
+ 39 01 00 00 00 00 03 b0 a5 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 0B 40 05 A0 02 d0 02 D0 02 D0 02 00
+ 02 68 00 20 4e a8 00 0A 00 0C 00 23
+ 00 1c 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 e0 18
+ 39 01 00 00 00 00 0c c0 00 53 6f 51 50
+ 51 34 4f 5a 33 19
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-lp1-command = [
+ 05 01 00 00 00 00 02 39 00
+ ];
+ qcom,mdss-dsi-lp1-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command = [
+ 05 01 00 00 00 00 02 38 00
+ ];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <180>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-td4328-1080p-cmd.dtsi b/display/dsi-panel-td4328-1080p-cmd.dtsi
new file mode 100644
index 0000000..476c34c
--- /dev/null
+++ b/display/dsi-panel-td4328-1080p-cmd.dtsi
@@ -0,0 +1,169 @@
+&mdss_mdp {
+ dsi_td4328_truly_cmd: qcom,mdss_dsi_td4328_truly_cmd {
+ qcom,mdss-dsi-panel-name =
+ "td4328 cmd mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <70>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <5>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 04 B3 00 00 06
+ 29 01 00 00 00 00 02 B4 00
+ 29 01 00 00 00 00 06 B6 33 DB 80 12 00
+ 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A
+ 50 50
+ 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14
+ C8 C8
+ 29 01 00 00 00 00 08 BA B5 33 41 64 23
+ A0 A0
+ 29 01 00 00 00 00 03 BB 14 14
+ 29 01 00 00 00 00 03 BC 37 32
+ 29 01 00 00 00 00 03 BD 64 32
+ 29 01 00 00 00 00 02 BE 04
+ 29 01 00 00 00 00 02 C0 00
+ 29 01 00 00 00 00 2E C1 04 48 00 00 26
+ 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C
+ 6B 93 4D 22 18 8B 2A 41 00 00 00 00
+ 00 00 00 00 00 40 02 22 1B 06 03 00
+ 07 FF 00 01
+ 29 01 00 00 00 00 18 C2 01 F8 70 08 68
+ 08 0C 10 00 08 30 00 00 00 00 00 00
+ 20 02 43 00 00 00
+ 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0
+ 00 00 00 00 00 00 04 3A 00 00 00 04
+ 44 00 00 01 01 03 28 00 01 00 01 00
+ 00 19 00 0C 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 32 00 19 00 5A
+ 02 32 00 19 00 5A 02 40 00
+ 29 01 00 00 00 00 15 C4 70 00 00 00 11
+ 11 00 00 00 02 02 31 01 00 00 00 02
+ 01 01 01
+ 29 01 00 00 00 00 08 C5 08 00 00 00 00
+ 70 00
+ 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54
+ 07 54 01 02 01 02 07 07 00 00 07 07
+ 0F 11 07 5B 00 5B 5B C2 C2 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F
+ 5A 71 80 8B 95 45 4F 5C 71 7B 88 98
+ A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95
+ 45 4F 5C 71 7B 88 98 A6 BE
+ 29 01 00 00 00 00 38 C8 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 14 C9 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 2C CA 1C FC FC FC 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 1C CB FF FF FF FF 0F
+ 00 08 00 01 00 31 F0 40 08 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 CC 02
+ 29 01 00 00 00 00 27 CD 10 80 37 C0 1A
+ 00 5C 02 19 90 11 88 D8 6C D8 6C 01
+ 00 00 00 32 00 32 00 5D 02 32 32 01
+ 33 00 33 00 5E 02 32 32 AF
+ 29 01 00 00 00 00 1A CE 5D 40 49 53 59
+ 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF
+ 04 00 04 04 42 00 69 5A
+ 29 01 00 00 00 00 03 CF 4A 1D
+ 29 01 00 00 00 00 12 D0 33 57 D4 31 01
+ 10 10 10 19 19 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 D1 00
+ 29 01 00 00 00 00 20 D2 10 00 00 10 75
+ 0F 03 25 20 00 00 00 00 00 00 00 00
+ 04 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 17 D3 1B 3B BB 77 77
+ 77 BB B3 33 00 00 6D 6E C7 C7 33 BB
+ F2 FD C6 0B 07
+ 29 01 00 00 00 00 08 D4 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 08 D5 03 00 00 02 2B
+ 02 2B
+ 29 01 00 00 00 00 02 D6 01
+ 29 01 00 00 00 00 22 D7 F6 FF 03 05 41
+ 24 80 1F C7 1F 1B 00 0C 07 20 00 00
+ 00 00 00 0C 00 1F 00 FC 00 00 AA 67
+ 7E 5D 06 00
+ 29 01 00 00 00 00 03 D9 20 14
+ 29 01 00 00 00 00 05 DD 30 06 23 65
+ 29 01 00 00 00 00 05 DE 00 3F FF 50
+ 29 01 00 00 00 00 06 E7 00 00 00 46 61
+ 29 01 00 00 00 00 02 EA 1F
+ 29 01 00 00 00 00 04 EE 41 51 00
+ 29 01 00 00 00 00 03 F1 00 00
+ 39 01 00 00 00 00 05 2A 00 00 04 37
+ 39 01 00 00 00 00 05 2B 00 00 08 6F
+ 39 01 00 00 00 00 01 2C
+ 29 01 00 00 00 00 02 B0 00
+ 39 01 00 00 00 00 02 51 FF
+ 39 01 00 00 00 00 02 53 0C
+ 39 01 00 00 00 00 02 55 00
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 96 00 01 11
+ 05 01 00 00 32 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/display/dsi-panel-td4328-1080p-video.dtsi b/display/dsi-panel-td4328-1080p-video.dtsi
new file mode 100644
index 0000000..e9b7bac
--- /dev/null
+++ b/display/dsi-panel-td4328-1080p-video.dtsi
@@ -0,0 +1,164 @@
+&mdss_mdp {
+ dsi_td4328_truly_video: qcom,mdss_dsi_td4328_truly_video {
+ qcom,mdss-dsi-panel-name =
+ "td4328 video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <70>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <5>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 04 B3 31 00 06
+ 29 01 00 00 00 00 02 B4 00
+ 29 01 00 00 00 00 06 B6 33 DB 80 12 00
+ 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A
+ 50 50
+ 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14
+ C8 C8
+ 29 01 00 00 00 00 08 BA B5 33 41 64 23
+ A0 A0
+ 29 01 00 00 00 00 03 BB 14 14
+ 29 01 00 00 00 00 03 BC 37 32
+ 29 01 00 00 00 00 03 BD 64 32
+ 29 01 00 00 00 00 02 BE 04
+ 29 01 00 00 00 00 02 C0 00
+ 29 01 00 00 00 00 2E C1 04 48 00 00 26
+ 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C
+ 6B 93 4D 22 18 8B 2A 41 00 00 00 00
+ 00 00 00 00 00 40 02 22 1B 06 03 00
+ 07 FF 00 01
+ 29 01 00 00 00 00 18 C2 01 F8 70 08 68
+ 08 0C 10 00 08 30 00 00 00 00 00 00
+ 20 02 43 00 00 00
+ 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0
+ 00 00 00 00 00 00 04 3A 00 00 00 04
+ 44 00 00 01 01 03 28 00 01 00 01 00
+ 00 19 00 0C 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 32 00 19 00 5A
+ 02 32 00 19 00 5A 02 40 00
+ 29 01 00 00 00 00 15 C4 70 00 00 00 11
+ 11 00 00 00 02 02 31 01 00 00 00 02
+ 01 01 01
+ 29 01 00 00 00 00 08 C5 08 00 00 00 00
+ 70 00
+ 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54
+ 07 54 01 02 01 02 07 07 00 00 07 07
+ 0F 11 07 5B 00 5B 5B C2 C2 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F
+ 5A 71 80 8B 95 45 4F 5C 71 7B 88 98
+ A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95
+ 45 4F 5C 71 7B 88 98 A6 BE
+ 29 01 00 00 00 00 38 C8 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 14 C9 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 2C CA 1C FC FC FC 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 1C CB FF FF FF FF 0F
+ 00 08 00 01 00 31 F0 40 08 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 CC 02
+ 29 01 00 00 00 00 27 CD 10 80 37 C0 1A
+ 00 5C 02 19 90 11 88 D8 6C D8 6C 01
+ 00 00 00 32 00 32 00 5D 02 32 32 01
+ 33 00 33 00 5E 02 32 32 AF
+ 29 01 00 00 00 00 1A CE 5D 40 49 53 59
+ 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF
+ 04 00 04 04 42 00 69 5A
+ 29 01 00 00 00 00 03 CF 4A 1D
+ 29 01 00 00 00 00 12 D0 33 57 D4 31 01
+ 10 10 10 19 19 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 D1 00
+ 29 01 00 00 00 00 20 D2 10 00 00 10 75
+ 0F 03 25 20 00 00 00 00 00 00 00 00
+ 04 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 17 D3 1B 3B BB 77 77
+ 77 BB B3 33 00 00 6D 6E DB DB 33 BB
+ F2 FD C6 0B 07
+ 29 01 00 00 00 00 08 D4 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 08 D5 03 00 00 02 40
+ 02 40
+ 29 01 00 00 00 00 02 D6 01
+ 29 01 00 00 00 00 22 D7 F6 FF 03 05 41
+ 24 80 1F C7 1F 1B 00 0C 07 20 00 00
+ 00 00 00 0C 00 1F 00 FC 00 00 AA 67
+ 7E 5D 06 00
+ 29 01 00 00 00 00 03 D9 20 14
+ 29 01 00 00 00 00 05 DD 30 06 23 65
+ 29 01 00 00 00 00 05 DE 00 3F FF 90
+ 29 01 00 00 00 00 06 E7 00 00 00 46 61
+ 29 01 00 00 00 00 02 EA 1F
+ 29 01 00 00 00 00 04 EE 41 51 00
+ 29 01 00 00 00 00 03 F1 00 00
+ 39 01 00 00 00 00 05 2A 00 00 04 37
+ 39 01 00 00 00 00 05 2B 00 00 08 6F
+ 39 01 00 00 00 00 01 2C
+ 39 01 00 00 00 00 02 51 FF
+ 39 01 00 00 00 00 02 53 0C
+ 39 01 00 00 00 00 02 55 00
+ 05 01 00 00 96 00 01 11
+ 05 01 00 00 32 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/display/kona-sde-display-cdp-lcd.dtsi b/display/kona-sde-display-cdp-lcd.dtsi
new file mode 100644
index 0000000..a7d85df
--- /dev/null
+++ b/display/kona-sde-display-cdp-lcd.dtsi
@@ -0,0 +1,36 @@
+&dsi_sharp_4k_dsc_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&sde_dsi {
+ /delete-property/ avdd-supply;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>;
+};
diff --git a/display/kona-sde-display-cdp.dtsi b/display/kona-sde-display-cdp.dtsi
new file mode 100644
index 0000000..fadbce6
--- /dev/null
+++ b/display/kona-sde-display-cdp.dtsi
@@ -0,0 +1,152 @@
+#include "kona-sde-display.dtsi"
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
diff --git a/display/kona-sde-display-mtp.dtsi b/display/kona-sde-display-mtp.dtsi
new file mode 100644
index 0000000..b81aad8
--- /dev/null
+++ b/display/kona-sde-display-mtp.dtsi
@@ -0,0 +1,87 @@
+#include "kona-sde-display.dtsi"
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
diff --git a/display/kona-sde-display-qrd.dtsi b/display/kona-sde-display-qrd.dtsi
new file mode 100644
index 0000000..1f6e32a
--- /dev/null
+++ b/display/kona-sde-display-qrd.dtsi
@@ -0,0 +1,76 @@
+#include "kona-sde-display.dtsi"
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
diff --git a/display/kona-sde-display-rumi.dtsi b/display/kona-sde-display-rumi.dtsi
new file mode 100644
index 0000000..3eb83e4
--- /dev/null
+++ b/display/kona-sde-display-rumi.dtsi
@@ -0,0 +1 @@
+#include "kona-sde-display.dtsi"
diff --git a/display/kona-sde-display.dtsi b/display/kona-sde-display.dtsi
new file mode 100644
index 0000000..6257b55
--- /dev/null
+++ b/display/kona-sde-display.dtsi
@@ -0,0 +1,528 @@
+#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
+#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
+#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"
+#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
+#include "dsi-panel-sharp-dsc-4k-video.dtsi"
+#include "dsi-panel-sharp-1080p-cmd.dtsi"
+#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
+#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
+#include "dsi-panel-sim-cmd.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-sim-dsc375-cmd.dtsi"
+#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-video.dtsi"
+#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
+#include "dsi-panel-sim-sec-hd-cmd.dtsi"
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&tlmm {
+ display_panel_avdd_default: display_panel_avdd_default {
+ mux {
+ pins = "gpio61";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio61";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+};
+
+&soc {
+ ext_disp: qcom,msm-ext-disp {
+ compatible = "qcom,msm-ext-disp";
+
+ ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+ compatible = "qcom,msm-ext-disp-audio-codec-rx";
+ };
+ };
+
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <3300000>;
+ qcom,supply-max-voltage = <3300000>;
+ qcom,supply-enable-load = <857000>;
+ qcom,supply-disable-load = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ };
+ };
+
+ dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "avdd";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+
+ display_panel_avdd: display_gpio_regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "display_panel_avdd";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ regulator-enable-ramp-delay = <233>;
+ gpio = <&tlmm 61 0>;
+ enable-active-high;
+ regulator-boot-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_panel_avdd_default>;
+ };
+
+ sde_dsi: qcom,dsi-display-primary {
+ compatible = "qcom,dsi-display";
+ label = "primary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
+ clock-names = "src_byte_clk0", "src_pixel_clk0",
+ "src_byte_clk1", "src_pixel_clk1";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,panel-te-source = <0>;
+
+ vddio-supply = <&pm8150_l14>;
+ vdd-supply = <&pm8150a_l11>;
+ avdd-supply = <&display_panel_avdd>;
+
+ qcom,mdp = <&mdss_mdp>;
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+ };
+
+ sde_dsi1: qcom,dsi-display-secondary {
+ compatible = "qcom,dsi-display";
+ label = "secondary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
+ clock-names = "src_byte_clk0", "src_pixel_clk0",
+ "src_byte_clk1", "src_pixel_clk1";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
+ pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 67 0>;
+ qcom,panel-te-source = <1>;
+
+ vddio-supply = <&pm8150_l14>;
+ vdd-supply = <&pm8150a_l11>;
+ avdd-supply = <&display_panel_avdd>;
+
+ qcom,mdp = <&mdss_mdp>;
+ };
+
+ sde_wb: qcom,wb-display@0 {
+ compatible = "qcom,wb-display";
+ cell-index = <0>;
+ label = "wb_display";
+ };
+};
+
+&sde_dp {
+ qcom,dp-usbpd-detection = <&pm8150b_pdphy>;
+ qcom,ext-disp = <&ext_disp>;
+ qcom,dp-aux-switch = <&fsa4480>;
+
+ qcom,usbplug-cc-gpio = <&tlmm 65 0>;
+
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&sde_dp_usbplug_cc_active>;
+ pinctrl-1 = <&sde_dp_usbplug_cc_suspend>;
+};
+
+&mdss_mdp {
+ connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+/* PHY TIMINGS REVISION W */
+&dsi_sw43404_amoled_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-supported-dfps-list = <60 57 55>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
+ qcom,mdss-dsi-min-refresh-rate = <55>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
+ 05 02 03 04 00 11 14];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 270 270 270 1080 270>;
+ };
+ };
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,mdss-dsi-panel-clockrate = <900000000>;
+ };
+ };
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <540 40 540 40 540 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <360 40 360 40 360 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
+
+&dsi_sim_vid {
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 0 1>,
+ <2 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* 1080p */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* qhd */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>, /* dsc merge */
+ <2 1 1>; /* 3d mux */
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* QHD 60fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* 1080 60fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>, /* dsc merge */
+ <2 1 1>; /* 3d mux */
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* QHD 90fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
+ 09 06 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_vid {
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* qhd */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* 4k */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* 5k */
+ qcom,mdss-dsi-panel-phy-timings = [00 46 13 14 33 30 12
+ 14 0e 02 04 00 37 22];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
diff --git a/display/kona-sde-pll.dtsi b/display/kona-sde-pll.dtsi
new file mode 100644
index 0000000..e6bda66
--- /dev/null
+++ b/display/kona-sde-pll.dtsi
@@ -0,0 +1,82 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+ reg = <0xae94900 0x260>,
+ <0xae94400 0x800>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base", "gdsc_base";
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ gdsc-supply = <&mdss_core_gdsc>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 1 PLL";
+ cell-index = <1>;
+ #clock-cells = <1>;
+ reg = <0xae96900 0x260>,
+ <0xae96400 0x800>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base", "gdsc_base";
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ gdsc-supply = <&mdss_core_gdsc>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
+ compatible = "qcom,mdss_dp_pll_7nm";
+ label = "MDSS DP PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+
+ reg = <0x088ea000 0x200>,
+ <0x088eaa00 0x200>,
+ <0x088ea200 0x200>,
+ <0x088ea600 0x200>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base", "ln_tx0_base",
+ "ln_tx1_base", "gdsc_base";
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "iface_clk", "ref_clk_src",
+ "gcc_iface", "pipe_clk";
+ clock-rate = <0>;
+ };
+};
diff --git a/display/kona-sde.dtsi b/display/kona-sde.dtsi
new file mode 100644
index 0000000..d6a849e
--- /dev/null
+++ b/display/kona-sde.dtsi
@@ -0,0 +1,688 @@
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&soc {
+ mdss_mdp: qcom,mdss_mdp@ae00000 {
+ compatible = "qcom,sde-kms";
+ reg = <0x0ae00000 0x84208>,
+ <0x0aeb0000 0x2008>,
+ <0x0aeac000 0x214>,
+ <0x0ae8f000 0x02c>,
+ <0x0af50000 0x038>;
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "regdma_phys",
+ "sid_phys",
+ "swfuse_phys";
+
+ clocks =
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_DISP_HF_AXI_CLK>,
+ <&clock_gcc GCC_DISP_SF_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
+ "iface_clk", "core_clk", "vsync_clk",
+ "lut_clk", "rot_clk";
+ clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>;
+ clock-max-rate = <0 0 0 0 460000000 19200000 460000000
+ 460000000>;
+
+ mmcx-supply = <&VDD_MMCX_LEVEL>;
+
+ /* interrupt config */
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #power-domain-cells = <0>;
+
+ /* hw blocks */
+ qcom,sde-off = <0x1000>;
+ qcom,sde-len = <0x494>;
+
+ qcom,sde-ctl-off = <0x2000 0x2200 0x2400
+ 0x2600 0x2800 0x2a00>;
+ qcom,sde-ctl-size = <0x1dc>;
+ qcom,sde-ctl-display-pref = "primary", "none", "none",
+ "none", "none";
+
+ qcom,sde-mixer-off = <0x45000 0x46000 0x47000
+ 0x48000 0x49000 0x4a000>;
+ qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary", "primary", "none",
+ "none", "none", "none";
+
+ qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
+ "cwb", "cwb", "cwb";
+
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-top-size = <0x80>;
+ qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
+ qcom,sde-dspp-size = <0x1800>;
+
+ qcom,sde-dest-scaler-top-off = <0x00061000>;
+ qcom,sde-dest-scaler-top-size = <0x1c>;
+ qcom,sde-dest-scaler-off = <0x800 0x1000>;
+ qcom,sde-dest-scaler-size = <0x800>;
+
+ qcom,sde-wb-off = <0x66000>;
+ qcom,sde-wb-size = <0x2c8>;
+ qcom,sde-wb-xin-id = <6>;
+ qcom,sde-wb-id = <2>;
+ qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+
+ qcom,sde-intf-off = <0x6b000 0x6b800
+ 0x6c000 0x6c800>;
+ qcom,sde-intf-size = <0x2b8>;
+ qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
+
+ qcom,sde-pp-off = <0x71000 0x71800
+ 0x72000 0x72800 0x73000 0x73800>;
+ qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
+ qcom,sde-pp-size = <0xd4>;
+ qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
+
+ qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>;
+ qcom,sde-merge-3d-size = <0x100>;
+
+ qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>;
+
+ qcom,sde-cdm-off = <0x7a200>;
+ qcom,sde-cdm-size = <0x224>;
+
+ qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
+ qcom,sde-dsc-size = <0x140>;
+
+ qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
+ 0x30e0 0x30e0 0x30e0>;
+ qcom,sde-dither-version = <0x00010000>;
+ qcom,sde-dither-size = <0x20>;
+
+ qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
+ "dma", "dma", "dma", "dma";
+
+ qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
+ 0x25000 0x27000 0x29000 0x2b000>;
+ qcom,sde-sspp-src-size = <0x1f8>;
+
+ qcom,sde-sspp-xin-id = <0 4 8 12
+ 1 5 9 13>;
+ qcom,sde-sspp-excl-rect = <1 1 1 1
+ 1 1 1 1>;
+ qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+ qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
+
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0 0xf8 0x110>;
+
+ qcom,sde-max-per-pipe-bw-kbps = <4400000 4400000
+ 4400000 4400000
+ 4400000 4400000
+ 4400000 4400000>;
+
+ qcom,sde-max-per-pipe-bw-high-kbps = <5300000 5300000
+ 5300000 5300000
+ 5300000 5300000
+ 5300000 5300000>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl =
+ <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
+ <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
+ qcom,sde-sspp-csc-off = <0x1a00>;
+ qcom,sde-csc-type = "csc-10bit";
+ qcom,sde-qseed-type = "qseedv3lite";
+ qcom,sde-sspp-qseed-off = <0xa00>;
+ qcom,sde-mixer-linewidth = <2560>;
+ qcom,sde-sspp-linewidth = <4096>;
+ qcom,sde-wb-linewidth = <4096>;
+ qcom,sde-mixer-blendstages = <0xb>;
+ qcom,sde-highest-bank-bit = <0x3>;
+ qcom,sde-ubwc-version = <0x400>;
+ qcom,sde-ubwc-swizzle = <0x6>;
+ qcom,sde-ubwc-bw-calc-version = <0x1>;
+ qcom,sde-ubwc-static = <0x1>;
+ qcom,sde-macrotile-mode = <0x1>;
+ qcom,sde-smart-panel-align-mode = <0xc>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-cdp;
+ qcom,sde-has-src-split;
+ qcom,sde-pipe-order-version = <0x1>;
+ qcom,sde-has-dim-layer;
+ qcom,sde-has-dest-scaler;
+ qcom,sde-has-idle-pc;
+ qcom,sde-max-dest-scaler-input-linewidth = <2048>;
+ qcom,sde-max-dest-scaler-output-linewidth = <2560>;
+ qcom,sde-max-bw-low-kbps = <13700000>;
+ qcom,sde-max-bw-high-kbps = <16600000>;
+ qcom,sde-min-core-ib-kbps = <2400000>;
+ qcom,sde-min-llcc-ib-kbps = <800000>;
+ qcom,sde-min-dram-ib-kbps = <800000>;
+ qcom,sde-dram-channels = <2>;
+ qcom,sde-num-nrt-paths = <0>;
+ qcom,sde-dspp-ltm-version = <0x00010000>;
+ /* offsets are based off dspp 0 and dspp 1 */
+ qcom,sde-dspp-ltm-off = <0x2a000 0x28100>;
+
+ qcom,sde-uidle-off = <0x80000>;
+ qcom,sde-uidle-size = <0x70>;
+
+ qcom,sde-vbif-off = <0>;
+ qcom,sde-vbif-size = <0x1040>;
+ qcom,sde-vbif-id = <0>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
+ qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
+
+ /* macrotile & macrotile-qseed has the same configs */
+ qcom,sde-danger-lut = <0x000000ff 0x0000ffff
+ 0x00000000 0x00000000 0x0000ffff>;
+
+ qcom,sde-safe-lut-linear = <0 0xfff0>;
+ qcom,sde-safe-lut-macrotile = <0 0xff00>;
+ /* same as safe-lut-macrotile */
+ qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
+ qcom,sde-safe-lut-nrt = <0 0xffff>;
+ qcom,sde-safe-lut-cwb = <0 0x3ff>;
+
+ qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+ qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
+ qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
+ qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
+ qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>;
+
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+
+ qcom,sde-reg-dma-off = <0>;
+ qcom,sde-reg-dma-version = <0x00010002>;
+ qcom,sde-reg-dma-trigger-off = <0x119c>;
+ qcom,sde-reg-dma-xin-id = <7>;
+ qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
+
+ qcom,sde-secure-sid-mask = <0x4000821>;
+
+ qcom,sde-sspp-vig-blocks {
+ qcom,sde-vig-csc-off = <0x1a00>;
+ qcom,sde-vig-qseed-off = <0xa00>;
+ qcom,sde-vig-qseed-size = <0xa0>;
+ qcom,sde-vig-gamut = <0x1d00 0x00060000>;
+ qcom,sde-vig-igc = <0x1d00 0x00060000>;
+ qcom,sde-vig-inverse-pma;
+ };
+
+ qcom,sde-sspp-dma-blocks {
+ dgm@0 {
+ qcom,sde-dma-igc = <0x400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x200>;
+ };
+
+ dgm@1 {
+ qcom,sde-dma-igc = <0x1400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x1200>;
+ };
+ };
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-hist = <0x800 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+ qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+ qcom,sde-dspp-gamut = <0x1000 0x00040001>;
+ qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+ qcom,sde-dspp-dither = <0x82c 0x00010007>;
+ };
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "mmcx";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&apps_smmu 0x820 0x402>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-earlymap; /* for cont-splash */
+ };
+
+ smmu_sde_sec: qcom,smmu_sde_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&apps_smmu 0x821 0x400>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>,
+ <22 512 0 6400000>, <23 512 0 6400000>,
+ <22 512 0 6400000>, <23 512 0 6400000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+ };
+
+ sde_dp: qcom,dp_display@ae90000 {
+ cell-index = <0>;
+ compatible = "qcom,dp-display";
+
+ vdda-1p2-supply = <&pm8150_l9>;
+ vdda-0p9-supply = <&pm8150_l18>;
+
+ reg = <0xae90000 0x0dc>,
+ <0xae90200 0x0c0>,
+ <0xae90400 0x508>,
+ <0xae91000 0x094>,
+ <0x88eaa00 0x200>,
+ <0x88ea200 0x200>,
+ <0x88ea600 0x200>,
+ <0xaf02000 0x1a0>,
+ <0x780000 0x621c>,
+ <0x88ea040 0x10>,
+ <0x88e8000 0x20>,
+ <0x0aee1000 0x034>,
+ <0xae91400 0x094>;
+ /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
+ reg-names = "dp_ahb", "dp_aux", "dp_link",
+ "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+ "dp_mmss_cc", "qfprom_physical", "dp_pll",
+ "usb3_dp_com", "hdcp_physical", "dp_p1";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <12 0>;
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
+ clock-names = "core_aux_clk", "core_usb_ref_clk_src",
+ "core_usb_pipe_clk", "link_clk", "link_iface_clk",
+ "pixel_clk_rcg", "pixel_parent",
+ "pixel1_clk_rcg", "pixel1_parent",
+ "strm0_pixel_clk", "strm1_pixel_clk";
+
+ qcom,phy-version = <0x420>;
+ qcom,aux-cfg0-settings = [20 00];
+ qcom,aux-cfg1-settings = [24 13];
+ qcom,aux-cfg2-settings = [28 A4];
+ qcom,aux-cfg3-settings = [2c 00];
+ qcom,aux-cfg4-settings = [30 0a];
+ qcom,aux-cfg5-settings = [34 26];
+ qcom,aux-cfg6-settings = [38 0a];
+ qcom,aux-cfg7-settings = [3c 03];
+ qcom,aux-cfg8-settings = [40 b7];
+ qcom,aux-cfg9-settings = [44 03];
+
+ qcom,max-pclk-frequency-khz = <675000>;
+
+ qcom,mst-enable;
+ qcom,widebus-enable;
+ qcom,dsc-feature-enable;
+ qcom,fec-feature-enable;
+ qcom,max-dp-dsc-blks = <2>;
+ qcom,max-dp-dsc-input-width-pixs = <2048>;
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <33000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <912000>;
+ qcom,supply-max-voltage = <912000>;
+ qcom,supply-enable-load = <126000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ sde_rscc: qcom,sde_rscc@af20000 {
+ cell-index = <0>;
+ compatible = "qcom,sde-rsc";
+ reg = <0xaf20000 0x3c50>,
+ <0xaf30000 0x3fd4>;
+ reg-names = "drv", "wrapper";
+ qcom,sde-rsc-version = <3>;
+
+ qcom,sde-dram-channels = <2>;
+
+ vdd-supply = <&mdss_core_gdsc>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+ clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "disp_rsc_mnoc_llcc";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <20003 20513 0 0>, <20004 20513 0 0>,
+ <20003 20513 0 6400000>, <20004 20513 0 6400000>,
+ <20003 20513 0 6400000>, <20004 20513 0 6400000>;
+ };
+
+ qcom,sde-ebi-bus {
+ qcom,msm-bus,name = "disp_rsc_ebi";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <20000 20512 0 0>,
+ <20000 20512 0 6400000>,
+ <20000 20512 0 6400000>;
+ };
+ };
+
+ mdss_rotator: qcom,mdss_rotator@aea8800 {
+ compatible = "qcom,sde_rotator";
+ reg = <0x0ae00000 0xac000>,
+ <0x0aeb8000 0x3000>;
+ reg-names = "mdp_phys",
+ "rot_vbif_phys";
+ status = "disabled";
+
+ #list-cells = <1>;
+
+ qcom,mdss-rot-mode = <1>;
+ qcom,mdss-highest-bank-bit = <0x3>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rotator";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <25 512 0 0>,
+ <25 512 0 6400000>,
+ <25 512 0 6400000>;
+
+ rot-vdd-supply = <&mdss_core_gdsc>;
+ qcom,supply-names = "rot-vdd";
+
+ clocks =
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_DISP_SF_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus",
+ "iface_clk", "rot_clk";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <2 0>;
+
+ power-domains = <&mdss_mdp>;
+
+ /* Offline rotator QoS setting */
+ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+ qcom,mdss-rot-vbif-memtype = <3 3>;
+ qcom,mdss-rot-cdp-setting = <1 1>;
+ qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
+ qcom,mdss-rot-danger-lut = <0x0 0x0>;
+ qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
+
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <32>;
+
+ qcom,mdss-sbuf-headroom = <20>;
+
+ /* reg bus scale settings */
+ rot_reg: qcom,rot-reg-bus {
+ qcom,msm-bus,name = "mdss_rot_reg";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>;
+ };
+
+ smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+ compatible = "qcom,smmu_sde_rot_unsec";
+ iommus = <&apps_smmu 0x215C 0x0400>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-0";
+ cell-index = <0>;
+ reg = <0xae94000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <4 0>;
+ vdda-1p2-supply = <&pm8150_l9>;
+ refgen-supply = <&refgen>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <26700>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-1";
+ cell-index = <1>;
+ reg = <0xae96000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <5 0>;
+ vdda-1p2-supply = <&pm8150_l9>;
+ refgen-supply = <&refgen>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <26700>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-0";
+ cell-index = <0>;
+ reg = <0xae94400 0x760>;
+ reg-names = "dsi_phy";
+ vdda-0p9-supply = <&pm8150_l5>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <46000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-1";
+ cell-index = <1>;
+ reg = <0xae96400 0x760>;
+ reg-names = "dsi_phy";
+ vdda-0p9-supply = <&pm8150_l5>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <46000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+};
