| #include "skeleton64.dtsi" |
| #include <dt-bindings/clock/qcom,gcc-sdm660.h> |
| #include <dt-bindings/clock/qcom,gpu-sdm660.h> |
| #include <dt-bindings/clock/qcom,mmcc-sdm660.h> |
| #include <dt-bindings/clock/qcom,rpmcc.h> |
| #include <dt-bindings/clock/qcom,audio-ext-clk.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h> |
| #include <dt-bindings/msm/msm-bus-ids.h> |
| #include <dt-bindings/clock/qcom,cpu-osm.h> |
| #include <dt-bindings/thermal/thermal.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/input/input.h> |
| |
| #define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024)) |
| #define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;} |
| #define DDR_TYPE_LPDDR3 5 |
| #define DDR_TYPE_LPDDR4X 7 |
| |
| / { |
| model = "Qualcomm Technologies, Inc. SDM 660"; |
| compatible = "qcom,sdm660"; |
| qcom,msm-id = <317 0x0>; |
| interrupt-parent = <&wakegic>; |
| |
| aliases { |
| serial0 = &uartblsp1dm1; |
| sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ |
| sdhc2 = &sdhc_2; /* SDC2 for SD card */ |
| }; |
| |
| chosen { |
| stdout-path = "serial0"; |
| bootargs = "rcupdate.rcu_expedited=1"; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| sched-energy-costs = <&CPU_COST_0>; |
| qcom,lmh-dcvs = <&lmh_dcvs0>; |
| efficiency = <1024>; |
| next-level-cache = <&L2_0>; |
| #cooling-cells = <2>; |
| L2_0: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-level = <2>; |
| /* A53 L2 dump not supported */ |
| qcom,dump-size = <0x0>; |
| }; |
| |
| L1_I_0: l1-icache { |
| compatible = "arm,arch-cache"; |
| }; |
| |
| L1_D_0: l1-dcache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| CPU1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| sched-energy-costs = <&CPU_COST_0>; |
| qcom,lmh-dcvs = <&lmh_dcvs0>; |
| #cooling-cells = <2>; |
| efficiency = <1024>; |
| next-level-cache = <&L2_0>; |
| L1_I_1: l1-icache { |
| compatible = "arm,arch-cache"; |
| }; |
| L1_D_1: l1-dcache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| CPU2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| sched-energy-costs = <&CPU_COST_0>; |
| qcom,lmh-dcvs = <&lmh_dcvs0>; |
| efficiency = <1024>; |
| next-level-cache = <&L2_0>; |
| #cooling-cells = <2>; |
| L1_I_2: l1-icache { |
| compatible = "arm,arch-cache"; |
| }; |
| L1_D_2: l1-dcache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| CPU3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| sched-energy-costs = <&CPU_COST_0>; |
| qcom,lmh-dcvs = <&lmh_dcvs0>; |
| efficiency = <1024>; |
| next-level-cache = <&L2_0>; |
| #cooling-cells = <2>; |
| L1_I_3: l1-icache { |
| compatible = "arm,arch-cache"; |
| }; |
| L1_D_3: l1-dcache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| CPU4: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1638>; |
| sched-energy-costs = <&CPU_COST_1>; |
| qcom,lmh-dcvs = <&lmh_dcvs1>; |
| efficiency = <1638>; |
| next-level-cache = <&L2_1>; |
| #cooling-cells = <2>; |
| L2_1: l2-cache { |
| compatible = "arm,arch-cache"; |
| cache-level = <2>; |
| }; |
| L1_I_100: l1-icache { |
| compatible = "arm,arch-cache"; |
| }; |
| L1_D_100: l1-dcache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| CPU5: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x101>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1638>; |
| sched-energy-costs = <&CPU_COST_1>; |
| qcom,lmh-dcvs = <&lmh_dcvs1>; |
| #cooling-cells = <2>; |
| efficiency = <1638>; |
| next-level-cache = <&L2_1>; |
| L1_I_101: l1-icache { |
| compatible = "arm,arch-cache"; |
| }; |
| L1_D_101: l1-dcache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| CPU6: cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x102>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1638>; |
| sched-energy-costs = <&CPU_COST_1>; |
| qcom,lmh-dcvs = <&lmh_dcvs1>; |
| #cooling-cells = <2>; |
| efficiency = <1638>; |
| next-level-cache = <&L2_1>; |
| L1_I_102: l1-icache { |
| compatible = "arm,arch-cache"; |
| }; |
| L1_D_102: l1-dcache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| CPU7: cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| reg = <0x0 0x103>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1638>; |
| sched-energy-costs = <&CPU_COST_1>; |
| qcom,lmh-dcvs = <&lmh_dcvs1>; |
| #cooling-cells = <2>; |
| efficiency = <1638>; |
| next-level-cache = <&L2_1>; |
| L1_I_103: l1-icache { |
| compatible = "arm,arch-cache"; |
| }; |
| L1_D_103: l1-dcache { |
| compatible = "arm,arch-cache"; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| }; |
| |
| cluster1 { |
| core0 { |
| cpu = <&CPU4>; |
| }; |
| |
| core1 { |
| cpu = <&CPU5>; |
| }; |
| |
| core2 { |
| cpu = <&CPU6>; |
| }; |
| |
| core3 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| }; |
| |
| energy_costs: energy-costs { |
| compatible = "sched-energy"; |
| |
| CPU_COST_0: core-cost0 { |
| busy-cost-data = < |
| 633600 41 |
| 902400 70 |
| 1113600 83 |
| 1401600 146 |
| 1536000 158 |
| 1747200 228 |
| 1843200 285 |
| >; |
| }; |
| |
| CPU_COST_1: core-cost1 { |
| busy-cost-data = < |
| 1113600 307 |
| 1401600 485 |
| 1747200 857 |
| 1804800 883 |
| 1958400 1222 |
| 2150400 1592 |
| 2208000 1632 |
| 2457600 2080 |
| >; |
| }; |
| }; |
| |
| clocks { |
| xo_board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <19200000>; |
| clock-output-names = "xo_board"; |
| }; |
| |
| sleep_clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32764>; |
| clock-output-names = "sleep_clk"; |
| }; |
| }; |
| |
| soc: soc { }; |
| |
| vendor: vendor { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| }; |
| |
| firmware: firmware { |
| android { |
| compatible = "android,firmware"; |
| |
| vbmeta { |
| compatible = "android,vbmeta"; |
| parts = "vbmeta,boot,system,vendor,dtbo"; |
| }; |
| |
| fstab { |
| compatible = "android,fstab"; |
| vendor { |
| compatible = "android,vendor"; |
| dev = "/dev/block/platform/soc/c0c4000.sdhci/by-name/vendor"; |
| type = "ext4"; |
| mnt_flags = "ro,barrier=1,discard"; |
| fsmgr_flags = "wait,slotselect,avb"; |
| status = "ok"; |
| }; |
| }; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| wlan_msa_guard: wlan_msa_guard@85600000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x85600000 0x0 0x100000>; |
| }; |
| |
| wlan_msa_mem: wlan_msa_mem@85700000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x85700000 0x0 0x100000>; |
| }; |
| |
| smem_mem: smem-mem@86000000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x86000000 0x0 0x200000>; |
| }; |
| |
| removed_regions: removed_regions@85800000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x85800000 0x0 0x800000>; |
| }; |
| |
| removed_regions1: removed_regions@86200000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x86200000 0x0 0x2d00000>; |
| }; |
| |
| modem_fw_mem: modem_fw_region@8ac00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x8ac00000 0x0 0x7e00000>; |
| }; |
| |
| adsp_fw_mem: adsp_fw_region@92a00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x92a00000 0x0 0x1e00000>; |
| }; |
| |
| pil_mba_mem: pil_mba_region@94800000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x94800000 0x0 0x200000>; |
| }; |
| |
| cdsp_fw_mem: cdsp_fw_region@94a00000 { |
| compatible = "removed-dma-pool"; |
| no-map; |
| reg = <0x0 0x94a00000 0x0 0x600000>; |
| }; |
| |
| dump_mem: mem_dump_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x140000>; |
| }; |
| |
| venus_fw_mem: venus_fw_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x80000000 0x0 0x20000000>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x800000>; |
| }; |
| |
| adsp_mem: adsp_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x800000>; |
| }; |
| |
| qseecom_mem: qseecom_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x1400000>; |
| }; |
| |
| secure_display_memory: secure_region { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; |
| reusable; |
| alignment = <0x0 0x400000>; |
| size = <0x0 0x5c00000>; |
| }; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| alloc-ranges = <0 0x00000000 0 0xffffffff>; |
| reusable; |
| alignment = <0 0x400000>; |
| size = <0 0x2c00000>; |
| linux,cma-default; |
| }; |
| |
| cont_splash_mem: splash_region@9d400000 { |
| reg = <0x0 0x9d400000 0x0 0x2300000>; |
| label = "cont_splash_mem"; |
| }; |
| |
| dfps_data_mem: dfps_data_mem@0x9f700000 { |
| reg = <0x0 0x9f700000 0x0 0x00100000>; |
| label = "dfps_data_mem"; |
| }; |
| }; |
| |
| |
| bluetooth: bt_wcn3990 { |
| compatible = "qca,wcn3990"; |
| qca,bt-vdd-core-supply = <&pm660_l9>; |
| qca,bt-vdd-pa-supply = <&pm660_l6>; |
| qca,bt-vdd-ldo-supply = <&pm660_l19>; |
| qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>; |
| clocks = <&clock_rpmcc RPM_SMD_RF_CLK1_PIN>; |
| clock-names = "rf_clk1"; |
| |
| qca,bt-vdd-core-voltage-level = <1800000 1900000>; |
| qca,bt-vdd-pa-voltage-level = <1304000 1370000>; |
| qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; |
| qca,bt-chip-pwd-voltage-level = <3600000 3600000>; |
| |
| qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ |
| qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ |
| qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ |
| }; |
| }; |
| |
| #include "sdm660-coresight.dtsi" |
| &soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0 0xffffffff>; |
| compatible = "simple-bus"; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x17a00000 0x10000>, /* GICD */ |
| <0x17b00000 0x100000>; /* GICR * 8 */ |
| #interrupt-cells = <3>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| interrupt-controller; |
| interrupt-parent = <&intc>; |
| #redistributor-regions = <1>; |
| redistributor-stride = <0x0 0x20000>; |
| interrupts = <1 9 4>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 1 0xf08>, |
| <1 2 0xf08>, |
| <1 3 0xf08>, |
| <1 0 0xf08>; |
| clock-frequency = <19200000>; |
| }; |
| |
| dma_blsp1: qcom,sps-dma@0xc144000{ /* BLSP1 */ |
| #dma-cells = <4>; |
| compatible = "qcom,sps-dma"; |
| reg = <0xc144000 0x1F000>; |
| interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,summing-threshold = <0x10>; |
| }; |
| |
| dma_blsp2: qcom,sps-dma@0xc184000{ /* BLSP2 */ |
| #dma-cells = <4>; |
| compatible = "qcom,sps-dma"; |
| reg = <0xc184000 0x1F000>; |
| interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,summing-threshold = <0x10>; |
| }; |
| |
| restart@10ac000 { |
| compatible = "qcom,pshold"; |
| reg = <0x10ac000 0x4>, |
| <0x1fd3000 0x4>; |
| reg-names = "pshold-base", "tcsr-boot-misc-detect"; |
| }; |
| |
| spmi_bus: qcom,spmi@800f000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0x800f000 0x1000>, |
| <0x8400000 0x1000000>, |
| <0x9400000 0x1000000>, |
| <0xa400000 0x220000>, |
| <0x800a000 0x3000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| qcom,reserved-chan = <511>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| cell-index = <0>; |
| status = "ok"; |
| }; |
| |
| mem_dump { |
| compatible = "qcom,mem-dump"; |
| memory-region = <&dump_mem>; |
| |
| c_scandump { |
| qcom,dump-size = <0x40000>; |
| qcom,dump-id = <0xeb>; |
| }; |
| |
| c0_context { |
| qcom,dump-size = <0x800>; |
| qcom,dump-id = <0x0>; |
| }; |
| |
| c100_context { |
| qcom,dump-size = <0x800>; |
| qcom,dump-id = <0x1>; |
| }; |
| |
| c200_context { |
| qcom,dump-size = <0x800>; |
| qcom,dump-id = <0x2>; |
| }; |
| |
| c300_context { |
| qcom,dump-size = <0x800>; |
| qcom,dump-id = <0x3>; |
| }; |
| |
| c400_context { |
| qcom,dump-size = <0x800>; |
| qcom,dump-id = <0x4>; |
| }; |
| |
| c500_context { |
| qcom,dump-size = <0x800>; |
| qcom,dump-id = <0x5>; |
| }; |
| |
| c600_context { |
| qcom,dump-size = <0x800>; |
| qcom,dump-id = <0x6>; |
| }; |
| |
| c700_context { |
| qcom,dump-size = <0x800>; |
| qcom,dump-id = <0x7>; |
| }; |
| |
| l1_i_cache0 { |
| qcom,dump-size = <0x9040>; |
| qcom,dump-id = <0x60>; |
| }; |
| |
| l1_i_cache1 { |
| qcom,dump-size = <0x9040>; |
| qcom,dump-id = <0x61>; |
| }; |
| |
| l1_i_cache2 { |
| qcom,dump-size = <0x9040>; |
| qcom,dump-id = <0x62>; |
| }; |
| |
| l1_i_cache3 { |
| qcom,dump-size = <0x9040>; |
| qcom,dump-id = <0x63>; |
| }; |
| |
| l1_i_cache100 { |
| qcom,dump-size = <0x12000>; |
| qcom,dump-id = <0x64>; |
| }; |
| |
| l1_i_cache101 { |
| qcom,dump-size = <0x12000>; |
| qcom,dump-id = <0x65>; |
| }; |
| |
| l1_i_cache102 { |
| qcom,dump-size = <0x12000>; |
| qcom,dump-id = <0x66>; |
| }; |
| |
| l1_i_cache103 { |
| qcom,dump-size = <0x12000>; |
| qcom,dump-id = <0x67>; |
| }; |
| |
| l1_d_cache0 { |
| qcom,dump-size = <0x9040>; |
| qcom,dump-id = <0x80>; |
| }; |
| |
| l1_d_cache1 { |
| qcom,dump-size = <0x9040>; |
| qcom,dump-id = <0x81>; |
| }; |
| |
| l1_d_cache2 { |
| qcom,dump-size = <0x9040>; |
| qcom,dump-id = <0x82>; |
| }; |
| |
| l1_d_cache3 { |
| qcom,dump-size = <0x9040>; |
| qcom,dump-id = <0x83>; |
| }; |
| |
| l1_d_cache100 { |
| qcom,dump-size = <0x12000>; |
| qcom,dump-id = <0x84>; |
| }; |
| |
| l1_d_cache101 { |
| qcom,dump-size = <0x12000>; |
| qcom,dump-id = <0x85>; |
| }; |
| |
| l1_d_cache102 { |
| qcom,dump-size = <0x12000>; |
| qcom,dump-id = <0x86>; |
| }; |
| |
| l1_d_cache103 { |
| qcom,dump-size = <0x12000>; |
| qcom,dump-id = <0x87>; |
| }; |
| |
| l1_tlb_dump0 { |
| qcom,dump-size = <0x2800>; |
| qcom,dump-id = <0x20>; |
| }; |
| |
| l1_tlb_dump1 { |
| qcom,dump-size = <0x2800>; |
| qcom,dump-id = <0x21>; |
| }; |
| |
| l1_tlb_dump2 { |
| qcom,dump-size = <0x2800>; |
| qcom,dump-id = <0x22>; |
| }; |
| |
| l1_tlb_dump3 { |
| qcom,dump-size = <0x2800>; |
| qcom,dump-id = <0x23>; |
| }; |
| |
| l1_tlb_dump100 { |
| qcom,dump-size = <0x4800>; |
| qcom,dump-id = <0x24>; |
| }; |
| |
| l1_tlb_dump101 { |
| qcom,dump-size = <0x4800>; |
| qcom,dump-id = <0x25>; |
| }; |
| |
| l1_tlb_dump102 { |
| qcom,dump-size = <0x4800>; |
| qcom,dump-id = <0x26>; |
| }; |
| |
| l1_tlb_dump103 { |
| qcom,dump-size = <0x4800>; |
| qcom,dump-id = <0x27>; |
| }; |
| }; |
| |
| wdog: qcom,wdt@17817000 { |
| compatible = "qcom,msm-watchdog"; |
| reg = <0x17817000 0x1000>; |
| reg-names = "wdt-base"; |
| interrupts = <0 3 IRQ_TYPE_EDGE_RISING>, |
| <0 4 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,bark-time = <11000>; |
| qcom,pet-time = <10000>; |
| qcom,ipi-ping; |
| qcom,wakeup-enable; |
| }; |
| |
| qcom,sps { |
| compatible = "qcom,msm-sps-4k"; |
| qcom,pipe-attr-ee; |
| }; |
| |
| wakegic: wake-gic { |
| compatible = "qcom,mpm-gic-sdm660", "qcom,mpm-gic"; |
| interrupts-extended = <&wakegic GIC_SPI 171 |
| IRQ_TYPE_EDGE_RISING>; |
| reg = <0x7781b8 0x1000>, /* MSM_RPM_MPM_BASE 4K */ |
| <0x17911008 0x4>; /* MSM_APCS_GCC_BASE 4K */ |
| reg-names = "vmpm", "ipc"; |
| qcom,num-mpm-irqs = <96>; |
| interrupt-controller; |
| interrupt-parent = <&intc>; |
| #interrupt-cells = <3>; |
| }; |
| |
| wakegpio: wake-gpio { |
| compatible = "qcom,mpm-gpio"; |
| interrupt-controller; |
| interrupt-parent = <&intc>; |
| #interrupt-cells = <2>; |
| }; |
| |
| qcom,memshare { |
| compatible = "qcom,memshare"; |
| |
| qcom,client_1 { |
| compatible = "qcom,memshare-peripheral"; |
| qcom,peripheral-size = <0x200000>; |
| qcom,client-id = <0>; |
| qcom,allocate-boot-time; |
| label = "modem"; |
| }; |
| |
| qcom,client_2 { |
| compatible = "qcom,memshare-peripheral"; |
| qcom,peripheral-size = <0x300000>; |
| qcom,client-id = <2>; |
| label = "modem"; |
| }; |
| |
| mem_client_3_size: qcom,client_3 { |
| compatible = "qcom,memshare-peripheral"; |
| qcom,peripheral-size = <0x0>; |
| qcom,client-id = <1>; |
| qcom,allocate-on-request; |
| label = "modem"; |
| }; |
| }; |
| |
| tsens: tsens@10ad000 { |
| compatible = "qcom,sdm660-tsens"; |
| reg = <0x10ad000 0x8>, |
| <0x10ae000 0x1ff>; |
| reg-names = "tsens_srot_physical", |
| "tsens_tm_physical"; |
| interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>, |
| <0 430 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "tsens-upper-lower", "tsens-critical"; |
| #thermal-sensor-cells = <1>; |
| qcom,client-id = <0 1 2 3 4 5 6 7 8 9 10 11 12 13>; |
| qcom,sensor-id = <0 10 11 4 5 6 7 8 13 2 3 12 9 1>; |
| qcom,sensors = <14>; |
| qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200 |
| 3200 3200 3200 3200 3200 3200>; |
| }; |
| |
| thermal_zones: thermal-zones { }; |
| |
| uartblsp1dm1: serial@0c170000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0xc170000 0x1000>; |
| interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, |
| <&clock_gcc GCC_BLSP1_AHB_CLK>; |
| clock-names = "core", "iface"; |
| }; |
| |
| qcom,qbt1000 { |
| compatible = "qcom,qbt1000"; |
| clock-names = "core", "iface"; |
| clocks = <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, |
| <&clock_gcc GCC_BLSP1_AHB_CLK>; |
| clock-frequency = <15000000>; |
| qcom,ipc-gpio = <&tlmm 72 0>; |
| qcom,finger-detect-gpio = <&pm660_gpios 11 0>; |
| }; |
| |
| cx_ipeak_lm: cx_ipeak@1fe5040 { |
| compatible = "qcom,cx-ipeak-v1"; |
| reg = <0x1fe5040 0x28>; |
| }; |
| |
| uartblsp2dm1: serial@0c1b0000 { |
| compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
| reg = <0xc1b0000 0x1000>; |
| interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>, |
| <&clock_gcc GCC_BLSP2_AHB_CLK>; |
| clock-names = "core", "iface"; |
| }; |
| |
| slim_aud: slim@151c0000 { |
| cell-index = <1>; |
| compatible = "qcom,slim-ngd"; |
| reg = <0x151c0000 0x2c000>, |
| <0x15184000 0x2a000>; |
| reg-names = "slimbus_physical", "slimbus_bam_physical"; |
| interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>, |
| <0 164 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "slimbus_irq", "slimbus_bam_irq"; |
| qcom,apps-ch-pipes = <0x7e0000>; |
| qcom,ea-pc = <0x260>; |
| qcom,arm-smmu; |
| iommus = <&anoc2_smmu 0x188b 0x0>, |
| <&anoc2_smmu 0x188c 0x0>, |
| <&anoc2_smmu 0x1892 0x0>, |
| <&anoc2_smmu 0x1893 0x0>, |
| <&anoc2_smmu 0x1894 0x0>; |
| qcom,iommu-dma-addr-pool = <0x40000000 0xC0000000>; |
| qcom,use-64-bit-dma-mask; |
| qcom,iommu-dma = "bypass"; |
| qcom,iommu-s1-bypass; |
| status = "disabled"; |
| }; |
| |
| slim_qca: slim@15240000 { |
| cell-index = <3>; |
| compatible = "qcom,slim-ngd"; |
| reg = <0x15240000 0x2c000>, |
| <0x15204000 0x20000>; |
| reg-names = "slimbus_physical", "slimbus_bam_physical"; |
| interrupts = <0 291 IRQ_TYPE_LEVEL_HIGH>, |
| <0 292 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "slimbus_irq", "slimbus_bam_irq"; |
| qcom,apps-ch-pipes = <0x1800>; |
| |
| /* Slimbus Slave DT for WCN3990 */ |
| btfmslim_codec: wcn3990 { |
| compatible = "qcom,btfmslim_slave"; |
| elemental-addr = [00 01 20 02 17 02]; |
| qcom,btfm-slim-ifd = "btfmslim_slave_ifd"; |
| qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02]; |
| }; |
| }; |
| |
| timer@17920000 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0x17920000 0x1000>; |
| clock-frequency = <19200000>; |
| |
| frame@17921000 { |
| frame-number = <0>; |
| interrupts = <0 8 0x4>, |
| <0 7 0x4>; |
| reg = <0x17921000 0x1000>, |
| <0x17922000 0x1000>; |
| }; |
| |
| frame@17923000 { |
| frame-number = <1>; |
| interrupts = <0 9 0x4>; |
| reg = <0x17923000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17924000 { |
| frame-number = <2>; |
| interrupts = <0 10 0x4>; |
| reg = <0x17924000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17925000 { |
| frame-number = <3>; |
| interrupts = <0 11 0x4>; |
| reg = <0x17925000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17926000 { |
| frame-number = <4>; |
| interrupts = <0 12 0x4>; |
| reg = <0x17926000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17927000 { |
| frame-number = <5>; |
| interrupts = <0 13 0x4>; |
| reg = <0x17927000 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17928000 { |
| frame-number = <6>; |
| interrupts = <0 14 0x4>; |
| reg = <0x17928000 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| arm64-cpu-erp { |
| compatible = "arm,arm64-cpu-erp"; |
| interrupts = <0 43 4>, |
| <0 44 4>, |
| <0 41 4>, |
| <0 42 4>; |
| |
| interrupt-names = "pri-dbe-irq", |
| "sec-dbe-irq", |
| "pri-ext-irq", |
| "sec-ext-irq"; |
| |
| poll-delay-ms = <5000>; |
| }; |
| |
| clock_rpmcc: qcom,rpmcc { |
| compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; |
| #clock-cells = <1>; |
| }; |
| |
| clock_gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sdm660", "syscon"; |
| reg = <0x100000 0x94000>; |
| vdd_dig-supply = <&pm660l_s3_level>; |
| vdd_dig_ao-supply = <&pm660l_s3_level_ao>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_mmss: clock-controller@c8c0000 { |
| compatible = "qcom,mmcc-sdm660", "syscon"; |
| reg = <0xc8c0000 0x40000>; |
| vdd_mx_mmss-supply = <&pm660l_s5_level>; |
| vdd_dig_mmss-supply = <&pm660l_s3_level>; |
| vdda-supply = <&pm660_l10>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_gpu: clock-controller@5065000 { |
| compatible = "qcom,gpu-sdm660", "syscon"; |
| reg = <0x5065000 0x10000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| clock_gfx: gfx@5065000 { |
| compatible = "qcom,gpucc-sdm660", "syscon"; |
| reg = <0x5065000 0x10000>; |
| vdd_dig_gfx-supply = <&pm660l_s3_level>; |
| vdd_mx_gfx-supply = <&pm660l_s5_level>; |
| vdd_gfx-supply = <&gfx_vreg_corner>; |
| qcom,gpucc_gfx3d_clk-opp-handle = <&msm_gpu>; |
| qcom,gfxfreq-corner = |
| < 0 0>, |
| < 160000000 1>, /* MinSVS */ |
| < 266000000 2>, /* LowSVS */ |
| < 370000000 3>, /* SVS */ |
| < 465000000 4>, /* SVS_L1 */ |
| < 588000000 5>, /* NOM */ |
| < 647000000 6>, /* NOM_L1 */ |
| < 700000000 7>, /* TURBO */ |
| < 750000000 7>; /* TURBO */ |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| cpu_debug: syscon@1791101c { |
| compatible = "syscon"; |
| reg = <0x1791101c 0x4>; |
| }; |
| |
| gpu_debug: syscon@05065120 { |
| compatible = "syscon"; |
| reg = <0x05065120 0x4>; |
| }; |
| |
| mmss_debug: syscon@c8c0900 { |
| compatible = "syscon"; |
| reg = <0xc8c0900 0x4>; |
| }; |
| |
| clock_debug: qcom,cc-debug@62000 { |
| compatible = "qcom,sdm660-debugcc"; |
| qcom,gcc = <&clock_gcc>; |
| qcom,cpu = <&cpu_debug>; |
| qcom,mmss = <&clock_mmss>; |
| qcom,gpu = <&clock_gfx>; |
| clock-names = "xo_clk_src"; |
| clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>; |
| #clock-cells = <1>; |
| }; |
| |
| generic_bw_opp_table: generic-bw-opp-table { |
| compatible = "operating-points-v2"; |
| BW_OPP_ENTRY( 100, 4); /* 381 MB/s */ |
| BW_OPP_ENTRY( 150, 4); /* 572 MB/s */ |
| BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ |
| BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */ |
| BW_OPP_ENTRY( 412, 4); /* 1571 MB/s */ |
| BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */ |
| BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */ |
| BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */ |
| BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */ |
| BW_OPP_ENTRY(1296, 4); /* 4943 MB/s */ |
| BW_OPP_ENTRY(1353, 4); /* 5163 MB/s */ |
| BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */ |
| BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */ |
| }; |
| |
| cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw { |
| compatible = "qcom,devbw"; |
| governor = "performance"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&generic_bw_opp_table>; |
| }; |
| |
| cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01008000 { |
| compatible = "qcom,bimc-bwmon4"; |
| reg = <0x01008000 0x300>, <0x01001000 0x200>; |
| reg-names = "base", "global_base"; |
| interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,mport = <0>; |
| qcom,hw-timer-hz = <19200000>; |
| qcom,target-dev = <&cpu_cpu_ddr_bw>; |
| qcom,count-unit = <0x10000>; |
| }; |
| |
| cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor { |
| compatible = "qcom,devbw"; |
| governor = "powersave"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&generic_bw_opp_table>; |
| }; |
| |
| cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor { |
| compatible = "qcom,devbw"; |
| governor = "powersave"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&generic_bw_opp_table>; |
| }; |
| |
| cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat { |
| compatible = "qcom,devbw"; |
| governor = "powersave"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&generic_bw_opp_table>; |
| }; |
| |
| cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat { |
| compatible = "qcom,devbw"; |
| governor = "powersave"; |
| qcom,src-dst-ports = |
| <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>; |
| qcom,active-only; |
| operating-points-v2 = <&generic_bw_opp_table>; |
| }; |
| |
| cpu0_memlat_cpugrp: qcom,cpu0-cpugrp { |
| compatible = "qcom,arm-memlat-cpugrp"; |
| qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| |
| cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon { |
| compatible = "qcom,arm-memlat-mon"; |
| qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| qcom,target-dev = <&cpu0_cpu_ddr_lat>; |
| qcom,cachemiss-ev = <0x17>; |
| qcom,core-dev-table = |
| < 902400 MHZ_TO_MBPS(200, 4) >, |
| < 1401600 MHZ_TO_MBPS(547, 4) >, |
| < 1881600 MHZ_TO_MBPS(1017, 4) >; |
| }; |
| |
| cpu0_computemon: qcom,cpu0-computemon { |
| compatible = "qcom,arm-compute-mon"; |
| qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; |
| qcom,target-dev = <&cpu0_cpu_ddr_latfloor>; |
| qcom,core-dev-table = |
| < 633600 MHZ_TO_MBPS(200, 4) >, |
| < 1401600 MHZ_TO_MBPS(412, 4) >, |
| < 1881600 MHZ_TO_MBPS(768, 4) >; |
| }; |
| }; |
| |
| cpu4_memlat_cpugrp: qcom,cpu4-cpugrp { |
| compatible = "qcom,arm-memlat-cpugrp"; |
| qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| |
| cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon { |
| compatible = "qcom,arm-memlat-mon"; |
| qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| qcom,target-dev = <&cpu4_cpu_ddr_lat>; |
| qcom,cachemiss-ev = <0x17>; |
| qcom,core-dev-table = |
| < 1113600 MHZ_TO_MBPS(200, 4) >, |
| < 1401600 MHZ_TO_MBPS(1017, 4) >, |
| < 2150400 MHZ_TO_MBPS(1555, 4) >, |
| < 2457600 MHZ_TO_MBPS(1804, 4) >; |
| }; |
| |
| cpu4_computemon: qcom,cpu4-computemon { |
| compatible = "qcom,arm-compute-mon"; |
| qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; |
| qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; |
| qcom,core-dev-table = |
| < 1113600 MHZ_TO_MBPS(200, 4) >, |
| < 1401600 MHZ_TO_MBPS(547, 4) >, |
| < 1747200 MHZ_TO_MBPS(768, 4) >, |
| < 2150400 MHZ_TO_MBPS(1017, 4) >, |
| < 2457600 MHZ_TO_MBPS(1804, 4) >; |
| }; |
| }; |
| |
| |
| clock_cpu: qcom,clk-cpu-660@179c0000 { |
| compatible = "qcom,clk-cpu-osm"; |
| reg = <0x179c0000 0x4000>, <0x17916000 0x1000>, |
| <0x17816000 0x1000>, <0x179d1000 0x1000>, |
| <0x00784130 0x8>, <0x00784130 0x8>; |
| reg-names = "osm", "pwrcl_pll", "perfcl_pll", |
| "apcs_common", "pwrcl_efuse", |
| "perfcl_efuse"; |
| |
| vdd-pwrcl-supply = <&apc0_pwrcl_vreg>; |
| vdd-perfcl-supply = <&apc1_perfcl_vreg>; |
| |
| interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "pwrcl-irq", "perfcl-irq"; |
| |
| qcom,pwrcl-speedbin0-v0 = |
| < 300000000 0x0004000f 0x01200020 0x1 1 >, |
| < 633600000 0x05040021 0x03200020 0x1 2 >, |
| < 902400000 0x0404002f 0x04260026 0x1 3 >, |
| < 1113600000 0x0404003a 0x052e002e 0x2 4 >, |
| < 1401600000 0x04040049 0x073a003a 0x2 5 >, |
| < 1536000000 0x04040050 0x08400040 0x2 6 >, |
| < 1747200000 0x0404005b 0x09480048 0x2 7 >, |
| < 1843200000 0x04040060 0x094c004c 0x3 8 >; |
| |
| qcom,pwrcl-speedbin1-v0 = |
| < 300000000 0x0004000f 0x01200020 0x1 1 >, |
| < 633600000 0x05040021 0x03200020 0x1 2 >, |
| < 902400000 0x0404002f 0x04260026 0x1 3 >, |
| < 1113600000 0x0404003a 0x052e002e 0x2 4 >, |
| < 1401600000 0x04040049 0x073a003a 0x2 5 >, |
| < 1536000000 0x04040050 0x08400040 0x2 6 >, |
| < 1747200000 0x0404005b 0x09480048 0x2 7 >, |
| < 1843200000 0x04040060 0x094c004c 0x3 8 >; |
| |
| qcom,pwrcl-speedbin3-v0 = |
| < 300000000 0x0004000f 0x01200020 0x1 1 >, |
| < 633600000 0x05040021 0x03200020 0x1 2 >, |
| < 902400000 0x0404002f 0x04260026 0x1 3 >, |
| < 1113600000 0x0404003a 0x052e002e 0x2 4 >, |
| < 1401600000 0x04040049 0x073a003a 0x2 5 >, |
| < 1536000000 0x04040050 0x08400040 0x2 6 >, |
| < 1612800000 0x04040054 0x09430043 0x2 7 >; |
| |
| qcom,pwrcl-speedbin4-v0 = |
| < 300000000 0x0004000f 0x01200020 0x1 1 >, |
| < 633600000 0x05040021 0x03200020 0x1 2 >, |
| < 902400000 0x0404002f 0x04260026 0x1 3 >, |
| < 1113600000 0x0404003a 0x052e002e 0x2 4 >, |
| < 1401600000 0x04040049 0x073a003a 0x2 5 >, |
| < 1536000000 0x04040050 0x08400040 0x2 6 >, |
| < 1747200000 0x0404005b 0x09480048 0x2 7 >, |
| < 1843200000 0x04040060 0x094c004c 0x3 8 >; |
| |
| qcom,perfcl-speedbin0-v0 = |
| < 300000000 0x0004000f 0x01200020 0x1 1 >, |
| < 1113600000 0x0404003a 0x052e002e 0x1 2 >, |
| < 1401600000 0x04040049 0x073a003a 0x2 3 >, |
| < 1747200000 0x0404005b 0x09480048 0x2 4 >, |
| < 1958400000 0x04040066 0x0a510051 0x2 5 >, |
| < 2150400000 0x04040070 0x0b590059 0x2 6 >, |
| < 2457600000 0x04040080 0x0c660066 0x3 7 >; |
| |
| qcom,perfcl-speedbin1-v0 = |
| < 300000000 0x0004000f 0x01200020 0x1 1 >, |
| < 1113600000 0x0404003a 0x052e002e 0x1 2 >, |
| < 1401600000 0x04040049 0x073a003a 0x2 3 >, |
| < 1747200000 0x0404005b 0x09480048 0x2 4 >, |
| < 1958400000 0x04040066 0x0a510051 0x2 5 >, |
| < 2150400000 0x04040070 0x0b590059 0x2 6 >, |
| < 2208000000 0x04040073 0x0b5c005c 0x3 7 >; |
| |
| qcom,perfcl-speedbin3-v0 = |
| < 300000000 0x0004000f 0x01200020 0x1 1 >, |
| < 1113600000 0x0404003a 0x052e002e 0x1 2 >, |
| < 1401600000 0x04040049 0x073a003a 0x2 3 >, |
| < 1747200000 0x0404005b 0x09480048 0x2 4 >, |
| < 1804800000 0x0404005e 0x094b004b 0x2 5 >; |
| |
| qcom,perfcl-speedbin4-v0 = |
| < 300000000 0x0004000f 0x01200020 0x1 1 >, |
| < 1113600000 0x0404003a 0x052e002e 0x1 2 >, |
| < 1401600000 0x04040049 0x073a003a 0x2 3 >, |
| < 1747200000 0x0404005b 0x09480048 0x2 4 >, |
| < 1958400000 0x04040066 0x0a510051 0x2 5 >; |
| |
| qcom,up-timer = <1000 1000>; |
| qcom,down-timer = <1000 1000>; |
| qcom,set-ret-inactive; |
| qcom,enable-llm-freq-vote; |
| qcom,llm-freq-up-timer = <327675 327675>; |
| qcom,llm-freq-down-timer = <327675 327675>; |
| qcom,enable-llm-volt-vote; |
| qcom,llm-volt-up-timer = <327675 327675>; |
| qcom,llm-volt-down-timer = <327675 327675>; |
| qcom,cc-reads = <10>; |
| qcom,cc-delay = <5>; |
| qcom,cc-factor = <100>; |
| qcom,osm-clk-rate = <200000000>; |
| qcom,xo-clk-rate = <19200000>; |
| |
| qcom,l-val-base = <0x17916004 0x17816004>; |
| qcom,apcs-itm-present = <0x179d143c 0x179d143c>; |
| qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>; |
| qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>; |
| qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>; |
| qcom,apm-mode-ctl = <0x179d0004 0x179d0010>; |
| qcom,apm-ctrl-status = <0x179d000c 0x179d0018>; |
| |
| qcom,apm-threshold-voltage = <872000>; |
| qcom,boost-fsm-en; |
| qcom,safe-fsm-en; |
| qcom,ps-fsm-en; |
| qcom,droop-fsm-en; |
| qcom,wfx-fsm-en; |
| qcom,pc-fsm-en; |
| |
| clock-names = "aux_clk", "xo_a"; |
| clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>, |
| <&clock_rpmcc RPM_SMD_XO_A_CLK_SRC>; |
| |
| #clock-cells = <1>; |
| }; |
| |
| msm_cpufreq: qcom,msm-cpufreq { |
| compatible = "qcom,msm-cpufreq"; |
| clock-names = "cpu0_clk", "cpu4_clk"; |
| clocks = <&clock_cpu PWRCL_CLK>, |
| <&clock_cpu PERFCL_CLK>; |
| |
| qcom,governor-per-policy; |
| |
| qcom,cpufreq-table-0 = |
| < 633600 >, |
| < 902400 >, |
| < 1113600 >, |
| < 1401600 >, |
| < 1536000 >, |
| < 1612800 >, |
| < 1747200 >, |
| < 1843200 >; |
| |
| qcom,cpufreq-table-4 = |
| < 1113600 >, |
| < 1401600 >, |
| < 1747200 >, |
| < 1804800 >, |
| < 1958400 >, |
| < 2150400 >, |
| < 2208000 >, |
| < 2457600 >; |
| }; |
| |
| sdhc_1: sdhci@c0c4000 { |
| compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe"; |
| reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>, |
| <0xc0c8000 0x8000>; |
| reg-names = "hc_mem", "cqhci_mem", "cqhci_ice"; |
| |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| qcom,bus-width = <8>; |
| qcom,large-address-bus; |
| |
| qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000 |
| 384000000>; |
| |
| qcom,nonremovable; |
| qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v"; |
| qcom,devfreq,freq-table = <50000000 200000000>; |
| |
| qcom,msm-bus,name = "sdhc1"; |
| qcom,msm-bus,num-cases = <9>; |
| qcom,msm-bus,num-paths = <2>; |
| qcom,msm-bus,vectors-KBps = |
| /* No vote */ |
| <78 512 0 0>, <1 606 0 0>, |
| /* 400 KB/s*/ |
| <78 512 1046 1600>, |
| <1 606 1600 1600>, |
| /* 20 MB/s */ |
| <78 512 52286 80000>, |
| <1 606 80000 80000>, |
| /* 25 MB/s */ |
| <78 512 65360 100000>, |
| <1 606 100000 100000>, |
| /* 50 MB/s */ |
| <78 512 130718 200000>, |
| <1 606 133320 133320>, |
| /* 100 MB/s */ |
| <78 512 130718 200000>, |
| <1 606 150000 150000>, |
| /* 200 MB/s */ |
| <78 512 261438 400000>, |
| <1 606 300000 300000>, |
| /* 400 MB/s */ |
| <78 512 261438 400000>, |
| <1 606 300000 300000>, |
| /* Max. bandwidth */ |
| <78 512 1338562 4096000>, |
| <1 606 1338562 4096000>; |
| qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 100000000 200000000 400000000 4294967295>; |
| |
| clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>, |
| <&clock_gcc GCC_SDCC1_APPS_CLK>, |
| <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>; |
| clock-names = "iface_clk", "core_clk", "ice_core_clk"; |
| qcom,ice-clk-rates = <300000000 75000000>; |
| |
| status = "disabled"; |
| }; |
| |
| sdhc_2: sdhci@c084000 { |
| compatible = "qcom,sdhci-msm-v5"; |
| reg = <0xc084000 0x1000>; |
| reg-names = "hc_mem"; |
| |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| qcom,bus-width = <4>; |
| qcom,large-address-bus; |
| |
| qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 |
| 200000000>; |
| qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104"; |
| |
| qcom,msm-bus,name = "sdhc2"; |
| qcom,msm-bus,num-cases = <8>; |
| qcom,msm-bus,num-paths = <2>; |
| qcom,msm-bus,vectors-KBps = |
| /* No vote */ |
| <81 512 0 0>, <1 608 0 0>, |
| /* 400 KB/s*/ |
| <81 512 1046 1600>, |
| <1 608 1600 1600>, |
| /* 20 MB/s */ |
| <81 512 52286 80000>, |
| <1 608 80000 80000>, |
| /* 25 MB/s */ |
| <81 512 65360 100000>, |
| <1 608 100000 100000>, |
| /* 50 MB/s */ |
| <81 512 130718 200000>, |
| <1 608 133320 133320>, |
| /* 100 MB/s */ |
| <81 512 261438 200000>, |
| <1 608 150000 150000>, |
| /* 200 MB/s */ |
| <81 512 261438 400000>, |
| <1 608 300000 300000>, |
| /* Max. bandwidth */ |
| <81 512 1338562 4096000>, |
| <1 608 1338562 4096000>; |
| qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000 |
| 100000000 200000000 4294967295>; |
| |
| qcom,devfreq,freq-table = <50000000 200000000>; |
| clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>, |
| <&clock_gcc GCC_SDCC2_APPS_CLK>; |
| clock-names = "iface_clk", "core_clk"; |
| |
| status = "disabled"; |
| }; |
| |
| ipa_hw: qcom,ipa@14780000 { |
| compatible = "qcom,ipa"; |
| reg = <0x14780000 0x4effc>, <0x14784000 0x26934>; |
| reg-names = "ipa-base", "bam-base"; |
| interrupts = <0 333 IRQ_TYPE_LEVEL_HIGH>, |
| <0 432 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ipa-irq", "bam-irq"; |
| qcom,ipa-hw-ver = <6>; /* IPA core version = IPAv2.6L */ |
| qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */ |
| qcom,wan-rx-ring-size = <192>; /* IPA WAN-rx-ring-size*/ |
| qcom,lan-rx-ring-size = <192>; /* IPA LAN-rx-ring-size*/ |
| clocks = <&clock_rpmcc RPM_SMD_IPA_CLK>, |
| <&clock_rpmcc AGGR2_NOC_SMMU_CLK>; |
| clock-names = "core_clk", "smmu_clk"; |
| qcom,arm-smmu; |
| qcom,smmu-disable-htw; |
| qcom,smmu-s1-bypass; |
| qcom,ee = <0>; |
| qcom,use-ipa-tethering-bridge; |
| qcom,modem-cfg-emb-pipe-flt; |
| qcom,ipa-wdi2; |
| qcom,use-dma-zone; |
| qcom,msm-bus,name = "ipa"; |
| qcom,msm-bus,num-cases = <4>; |
| qcom,msm-bus,num-paths = <2>; |
| qcom,msm-bus,vectors-KBps = |
| /* No vote */ |
| <90 512 0 0>, |
| <1 676 0 0>, |
| /* SVS */ |
| <90 512 80000 640000>, |
| <1 676 80000 80000>, |
| /* NOMINAL */ |
| <90 512 206000 960000>, |
| <1 676 206000 160000>, |
| /* TURBO */ |
| <90 512 206000 960000>, |
| <1 676 206000 160000>; |
| qcom,bus-vector-names = "MIN", "SVS", "PERF", "TURBO"; |
| qcom,rx-polling-sleep-ms = <1>; /* Polling sleep interval */ |
| qcom,ipa-polling-iteration = <40>; /* Polling Iteration */ |
| ipa_smmu_ap: ipa_smmu_ap { |
| compatible = "qcom,ipa-smmu-ap-cb"; |
| iommus = <&anoc2_smmu 0x19C0 0x0>; |
| qcom,iommu-dma-addr-pool = <0x10000000 0x40000000>; |
| qcom,iommu-dma = "bypass"; |
| }; |
| |
| ipa_smmu_wlan: ipa_smmu_wlan { |
| status = "disabled"; |
| compatible = "qcom,ipa-smmu-wlan-cb"; |
| iommus = <&anoc2_smmu 0x19C1 0x0>; |
| qcom,iommu-dma = "bypass"; |
| }; |
| |
| ipa_smmu_uc: ipa_smmu_uc { |
| compatible = "qcom,ipa-smmu-uc-cb"; |
| iommus = <&anoc2_smmu 0x19C2 0x0>; |
| qcom,iommu-dma-addr-pool = <0x40000000 0x20000000>; |
| qcom,iommu-dma = "bypass"; |
| }; |
| }; |
| |
| qcom,rmtfs_sharedmem@0 { |
| compatible = "qcom,sharedmem-uio"; |
| reg = <0x0 0x200000>; |
| reg-names = "rmtfs"; |
| qcom,client-id = <0x00000001>; |
| qcom,guard-memory; |
| }; |
| |
| qcom,rmnet-ipa { |
| compatible = "qcom,rmnet-ipa"; |
| qcom,rmnet-ipa-ssr; |
| qcom,ipa-platform-type-msm; |
| qcom,ipa-advertise-sg-support; |
| qcom,ipa-napi-enable; |
| }; |
| |
| qcom,ipc-spinlock@1f40000 { |
| compatible = "qcom,ipc-spinlock-sfpb"; |
| reg = <0x1f40000 0x8000>; |
| qcom,num-locks = <8>; |
| }; |
| |
| qcom,msm-cdsp-loader { |
| compatible = "qcom,cdsp-loader"; |
| qcom,proc-img-to-load = "cdsp"; |
| }; |
| |
| qcom,msm-adsprpc-mem { |
| compatible = "qcom,msm-adsprpc-mem-region"; |
| memory-region = <&adsp_mem>; |
| restrict-access; |
| }; |
| |
| qcom,msm_fastrpc { |
| compatible = "qcom,msm-fastrpc-compute"; |
| qcom,adsp-remoteheap-vmid = <33>; |
| qcom,rpc-latency-us = <611>; |
| qcom,fastrpc-adsp-audio-pdr; |
| qcom,fastrpc-adsp-sensors-pdr; |
| |
| qcom,msm_fastrpc_compute_cb1 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&lpass_q6_smmu 3>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb2 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&lpass_q6_smmu 7>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb3 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&lpass_q6_smmu 8>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb4 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "adsprpc-smd"; |
| iommus = <&lpass_q6_smmu 9>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb5 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 3>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb6 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 4>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb7 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 5>; |
| dma-coherent; |
| }; |
| |
| qcom,msm_fastrpc_compute_cb8 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 6>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb9 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 7>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb10 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 8>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb11 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 9>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb12 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 10>; |
| dma-coherent; |
| }; |
| qcom,msm_fastrpc_compute_cb13 { |
| compatible = "qcom,msm-fastrpc-compute-cb"; |
| label = "cdsprpc-smd"; |
| iommus = <&turing_q6_smmu 11>; |
| dma-coherent; |
| }; |
| }; |
| |
| |
| dcc: dcc@10b3000 { |
| compatible = "qcom,dcc"; |
| reg = <0x10b3000 0x1000>, |
| <0x10b4000 0x2000>; |
| reg-names = "dcc-base", "dcc-ram-base"; |
| |
| clocks = <&clock_gcc GCC_DCC_AHB_CLK>; |
| clock-names = "dcc_clk"; |
| }; |
| |
| tcsr_mutex_block: syscon@1f40000 { |
| compatible = "syscon"; |
| reg = <0x1f40000 0x20000>; |
| }; |
| |
| tcsr_mutex: hwlock { |
| compatible = "qcom,tcsr-mutex"; |
| syscon = <&tcsr_mutex_block 0 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_mem>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| apcs_glb: mailbox@17911000 { |
| compatible = "qcom,sdm660-apcs-hmss-global"; |
| reg = <0x17911000 0x1000>; |
| #mbox-cells = <1>; |
| }; |
| |
| rpm-glink { |
| compatible = "qcom,glink-rpm"; |
| interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; |
| qcom,rpm-msg-ram = <&rpm_msg_ram>; |
| mboxes = <&apcs_glb 0>; |
| |
| qcom,rpm_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_modem>, |
| <&glink_adsp>, |
| <&glink_cdsp>; |
| }; |
| |
| }; |
| |
| qcom,glink { |
| compatible = "qcom,glink"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| glink_modem: modem { |
| qcom,remote-pid = <1>; |
| transport = "smem"; |
| mboxes = <&apcs_glb 15>; |
| mbox-names = "mpss_smem"; |
| interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "modem"; |
| qcom,glink-label = "mpss"; |
| |
| qcom,modem_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,low-latency; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,msm_fastrpc_rpmsg { |
| compatible = "qcom,msm-fastrpc-rpmsg"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| qcom,intents = <0x64 64>; |
| }; |
| |
| qcom,modem_ds { |
| qcom,glink-channels = "DS"; |
| qcom,intents = <0x4000 0x2>; |
| }; |
| |
| qcom,modem_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_adsp>, |
| <&glink_cdsp>; |
| }; |
| }; |
| |
| glink_adsp: adsp { |
| qcom,remote-pid = <2>; |
| transport = "smem"; |
| mboxes = <&apcs_glb 9>; |
| mbox-names = "adsp_smem"; |
| interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "adsp"; |
| qcom,glink-label = "lpass"; |
| cpu-affinity = <1 2>; |
| |
| qcom,adsp_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,apr_tal_rpmsg { |
| qcom,glink-channels = "apr_audio_svc"; |
| qcom,intents = <0x200 20>; |
| }; |
| |
| qcom,msm_fastrpc_rpmsg { |
| compatible = "qcom,msm-fastrpc-rpmsg"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| qcom,intents = <0x64 64>; |
| }; |
| |
| qcom,adsp_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_modem>, |
| <&glink_cdsp>; |
| }; |
| }; |
| |
| |
| glink_cdsp: cdsp { |
| qcom,remote-pid = <5>; |
| transport = "smem"; |
| mboxes = <&apcs_glb 29>; |
| mbox-names = "cdsp_smem"; |
| interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>; |
| |
| label = "cdsp"; |
| qcom,glink-label = "cdsp"; |
| |
| qcom,cdsp_qrtr { |
| qcom,glink-channels = "IPCRTR"; |
| qcom,intents = <0x800 5 |
| 0x2000 3 |
| 0x4400 2>; |
| }; |
| |
| qcom,msm_fastrpc_rpmsg { |
| compatible = "qcom,msm-fastrpc-rpmsg"; |
| qcom,glink-channels = "fastrpcglink-apps-dsp"; |
| qcom,intents = <0x64 64>; |
| }; |
| |
| qcom,msm_cdsprm_rpmsg { |
| compatible = "qcom,msm-cdsprm-rpmsg"; |
| qcom,glink-channels = "cdsprmglink-apps-dsp"; |
| qcom,intents = <0x20 12>; |
| |
| msm_cdsp_rm: qcom,msm_cdsp_rm { |
| compatible = "qcom,msm-cdsp-rm"; |
| qcom,qos-latency-us = <44>; |
| qcom,qos-maxhold-ms = <20>; |
| #cooling-cells = <2>; |
| }; |
| |
| msm_hvx_rm: qcom,msm_hvx_rm { |
| compatible = "qcom,msm-hvx-rm"; |
| #cooling-cells = <2>; |
| }; |
| }; |
| |
| qcom,cdsp_glink_ssr { |
| qcom,glink-channels = "glink_ssr"; |
| qcom,notify-edges = <&glink_modem>, |
| <&glink_adsp>; |
| }; |
| }; |
| |
| glink_spi_xprt_wdsp: wdsp { |
| transport = "spi"; |
| tx-descriptors = <0x12000 0x12004>; |
| rx-descriptors = <0x1200c 0x12010>; |
| |
| label = "wdsp"; |
| qcom,glink-label = "wdsp"; |
| |
| qcom,wdsp_ctrl { |
| qcom,glink-channels = "g_glink_ctrl"; |
| qcom,intents = <0x400 1>; |
| }; |
| |
| qcom,wdsp_ild { |
| qcom,glink-channels = |
| "g_glink_persistent_data_ild"; |
| }; |
| |
| qcom,wdsp_nild { |
| qcom,glink-channels = |
| "g_glink_persistent_data_nild"; |
| }; |
| |
| qcom,wdsp_data { |
| qcom,glink-channels = "g_glink_audio_data"; |
| qcom,intents = <0x1000 2>; |
| }; |
| |
| qcom,diag_data { |
| qcom,glink-channels = "DIAG_DATA"; |
| qcom,intents = <0x4000 2>; |
| }; |
| |
| qcom,diag_ctrl { |
| qcom,glink-channels = "DIAG_CTRL"; |
| qcom,intents = <0x4000 1>; |
| }; |
| |
| qcom,diag_cmd { |
| qcom,glink-channels = "DIAG_CMD"; |
| qcom,intents = <0x4000 1 >; |
| }; |
| }; |
| }; |
| |
| qcom,glink_pkt { |
| compatible = "qcom,glinkpkt"; |
| |
| qcom,glinkpkt-at-mdm0 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DS"; |
| qcom,glinkpkt-dev-name = "at_mdm0"; |
| }; |
| |
| qcom,glinkpkt-loopback_cntl { |
| qcom,glinkpkt-transport = "lloop"; |
| qcom,glinkpkt-edge = "local"; |
| qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT"; |
| qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl"; |
| }; |
| |
| qcom,glinkpkt-loopback_data { |
| qcom,glinkpkt-transport = "lloop"; |
| qcom,glinkpkt-edge = "local"; |
| qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT"; |
| qcom,glinkpkt-dev-name = "glink_pkt_loopback"; |
| }; |
| |
| qcom,glinkpkt-apr-apps2 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "adsp"; |
| qcom,glinkpkt-ch-name = "apr_apps2"; |
| qcom,glinkpkt-dev-name = "apr_apps2"; |
| }; |
| |
| qcom,glinkpkt-data40-cntl { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA40_CNTL"; |
| qcom,glinkpkt-dev-name = "smdcntl8"; |
| }; |
| |
| qcom,glinkpkt-data1 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA1"; |
| qcom,glinkpkt-dev-name = "smd7"; |
| }; |
| |
| qcom,glinkpkt-data4 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA4"; |
| qcom,glinkpkt-dev-name = "smd8"; |
| }; |
| |
| qcom,glinkpkt-data11 { |
| qcom,glinkpkt-transport = "smem"; |
| qcom,glinkpkt-edge = "mpss"; |
| qcom,glinkpkt-ch-name = "DATA11"; |
| qcom,glinkpkt-dev-name = "smd11"; |
| }; |
| }; |
| |
| qcom,smp2p_sleepstate { |
| compatible = "qcom,smp2p-sleepstate"; |
| qcom,smem-states = <&sleepstate_smp2p_out 0>; |
| interrupt-parent = <&sleepstate_smp2p_in>; |
| interrupts = <0 0>; |
| interrupt-names = "smp2p-sleepstate-in"; |
| }; |
| |
| qcom,smp2p-modem { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <435>, <428>; |
| interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apcs_glb 14>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <1>; |
| |
| modem_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| modem_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| smp2p_ipa_1_out: qcom,smp2p-ipa-1-out { |
| qcom,entry-name = "ipa"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| /* ipa - inbound entry from mss */ |
| smp2p_ipa_1_in: qcom,smp2p-ipa-1-in { |
| qcom,entry-name = "ipa"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| smp2p_wlan_1_in: qcom,smp2p-wlan-1-in { |
| qcom,entry-name = "wlan"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| qcom,smp2p-adsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <443>, <429>; |
| interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apcs_glb 10>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <2>; |
| |
| adsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| adsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| smp2p_rdbg2_out: qcom,smp2p-rdbg2-out { |
| qcom,entry-name = "rdbg"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| smp2p_rdbg2_in: qcom,smp2p-rdbg2-in { |
| qcom,entry-name = "rdbg"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| sleepstate_smp2p_out: sleepstate-out { |
| qcom,entry-name = "sleepstate"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| sleepstate_smp2p_in: qcom,sleepstate-in { |
| qcom,entry-name = "sleepstate_see"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| qcom,smp2p-cdsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <94>, <432>; |
| interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apcs_glb 30>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <5>; |
| |
| cdsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| cdsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| smp2p_rdbg5_out: qcom,smp2p-rdbg5-out { |
| qcom,entry-name = "rdbg"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| smp2p_rdbg5_in: qcom,smp2p-rdbg5-in { |
| qcom,entry-name = "rdbg"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| rpm_bus: qcom,rpm-smd { |
| compatible = "qcom,rpm-smd"; |
| rpm-channel-name = "rpm_requests"; |
| interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; |
| rpm-channel-type = <15>; /* SMD_APPS_RPM */ |
| }; |
| |
| qcom,venus@cce0000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0xcce0000 0x4000>; |
| |
| vdd-supply = <&gdsc_venus>; |
| qcom,proxy-reg-names = "vdd"; |
| |
| clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>, |
| <&clock_mmss MMSS_MNOC_AHB_CLK>, |
| <&clock_mmss MMSS_VIDEO_AHB_CLK>, |
| <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, |
| <&clock_mmss MMSS_VIDEO_AXI_CLK>; |
| clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", |
| "noc_axi_clk", "bus_clk"; |
| qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk", |
| "iface_clk", "noc_axi_clk", "bus_clk"; |
| |
| qcom,msm-bus,name = "pil-venus"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <63 512 0 0>, |
| <63 512 0 304000>; |
| |
| qcom,pas-id = <9>; |
| qcom,mas-crypto = <&mas_crypto_c0>; |
| qcom,proxy-timeout-ms = <100>; |
| qcom,firmware-name = "venus"; |
| memory-region = <&venus_fw_mem>; |
| status = "ok"; |
| }; |
| |
| qcom,icnss@18800000 { |
| compatible = "qcom,icnss"; |
| reg = <0x18800000 0x800000>, |
| <0xb0000000 0x10000>; |
| reg-names = "membase", "smmu_iova_ipa"; |
| iommus = <&anoc2_smmu 0x1a00>, |
| <&anoc2_smmu 0x1a01>; |
| clocks = <&clock_rpmcc RPM_SMD_RF_CLK1_PIN>; |
| clock-names = "cxo_ref_clk_pin"; |
| interrupts = <0 413 IRQ_TYPE_LEVEL_HIGH>, /* CE0 */ |
| <0 414 IRQ_TYPE_LEVEL_HIGH>, /* CE1 */ |
| <0 415 IRQ_TYPE_LEVEL_HIGH>, /* CE2 */ |
| <0 416 IRQ_TYPE_LEVEL_HIGH>, /* CE3 */ |
| <0 417 IRQ_TYPE_LEVEL_HIGH>, /* CE4 */ |
| <0 418 IRQ_TYPE_LEVEL_HIGH>, /* CE5 */ |
| <0 420 IRQ_TYPE_LEVEL_HIGH>, /* CE6 */ |
| <0 421 IRQ_TYPE_LEVEL_HIGH>, /* CE7 */ |
| <0 422 IRQ_TYPE_LEVEL_HIGH>, /* CE8 */ |
| <0 423 IRQ_TYPE_LEVEL_HIGH>, /* CE9 */ |
| <0 424 IRQ_TYPE_LEVEL_HIGH>, /* CE10 */ |
| <0 425 IRQ_TYPE_LEVEL_HIGH>; /* CE11 */ |
| qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>; |
| qcom,iommu-dma = "bypass"; |
| qcom,iommu-faults = "stall-disable"; |
| qcom,hyp_enabled; |
| vdd-cx-mx-supply = <&pm660_l5>; |
| vdd-1.8-xo-supply = <&pm660_l9_pin_ctrl>; |
| vdd-1.3-rfa-supply = <&pm660_l6_pin_ctrl>; |
| vdd-3.3-ch0-supply = <&pm660_l19_pin_ctrl>; |
| qcom,vdd-cx-mx-config = <848000 848000>; |
| qcom,vdd-1.8-xo-config = <1750000 1900000>; |
| qcom,vdd-1.3-rfa-config = <1200000 1370000>; |
| qcom,vdd-3.3-ch0-config = <3200000 3400000>; |
| qcom,wlan-msa-memory = <0x100000>; |
| qcom,wlan-msa-fixed-region = <&wlan_msa_mem>; |
| qcom,smp2p_map_wlan_1_in { |
| interrupts-extended = <&smp2p_wlan_1_in 0 0>, |
| <&smp2p_wlan_1_in 1 0>; |
| interrupt-names = "qcom,smp2p-force-fatal-error", |
| "qcom,smp2p-early-crash-ind"; |
| }; |
| }; |
| |
| qcom,lpass@15700000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x15700000 0x00100>; |
| reg-names = "base_reg"; |
| |
| vdd_cx-supply = <&pm660l_l9_level>; |
| qcom,proxy-reg-names = "vdd_cx"; |
| qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; |
| |
| clocks = <&clock_rpmcc CXO_SMD_PIL_LPASS_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <1>; |
| qcom,mas-crypto = <&mas_crypto_c0>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <423>; |
| qcom,sysmon-id = <1>; |
| qcom,ssctl-instance-id = <0x14>; |
| qcom,firmware-name = "adsp"; |
| memory-region = <&adsp_fw_mem>; |
| |
| /* GPIO inputs from lpass */ |
| interrupts-extended = <&wakegic 0 162 1>, |
| <&adsp_smp2p_in 0 0>, |
| <&adsp_smp2p_in 2 0>, |
| <&adsp_smp2p_in 1 0>, |
| <&adsp_smp2p_in 3 0>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,proxy-unvote", |
| "qcom,err-ready", |
| "qcom,stop-ack"; |
| |
| /* GPIO output to lpass */ |
| qcom,smem-states = <&adsp_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| status = "ok"; |
| }; |
| |
| qcom,turing@1a300000 { |
| compatible = "qcom,pil-tz-generic"; |
| reg = <0x1a300000 0x00100>; |
| reg-names = "base_reg"; |
| |
| vdd_cx-supply = <&pm660l_s3_level>; |
| qcom,proxy-reg-names = "vdd_cx"; |
| qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>; |
| |
| clocks = <&clock_rpmcc CXO_SMD_PIL_CDSP_CLK>; |
| clock-names = "xo"; |
| qcom,proxy-clock-names = "xo"; |
| |
| qcom,pas-id = <18>; |
| qcom,mas-crypto = <&mas_crypto_c0>; |
| qcom,proxy-timeout-ms = <10000>; |
| qcom,smem-id = <601>; |
| qcom,sysmon-id = <7>; |
| qcom,ssctl-instance-id = <0x17>; |
| qcom,firmware-name = "cdsp"; |
| memory-region = <&cdsp_fw_mem>; |
| |
| /* Inputs from turing */ |
| interrupts-extended = <&wakegic 0 518 1>, |
| <&cdsp_smp2p_in 0 0>, |
| <&cdsp_smp2p_in 2 0>, |
| <&cdsp_smp2p_in 1 0>, |
| <&cdsp_smp2p_in 3 0>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,proxy-unvote", |
| "qcom,err-ready", |
| "qcom,stop-ack"; |
| |
| /* Outputs to turing */ |
| qcom,smem-states = <&cdsp_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| status = "ok"; |
| }; |
| |
| pil_modem: qcom,mss@4080000 { |
| compatible = "qcom,pil-q6v55-mss"; |
| reg = <0x4080000 0x100>, |
| <0x1f63000 0x008>, |
| <0x1f65000 0x008>, |
| <0x1f64000 0x008>, |
| <0x4180000 0x040>, |
| <0x00179000 0x004>, |
| <0x01fe5048 0x004>; |
| reg-names = "qdsp6_base", "halt_q6", "halt_modem", |
| "halt_nc", "rmb_base", "restart_reg", |
| "cxip_lm_vote_clear"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>, |
| <&clock_gcc GCC_MSS_CFG_AHB_CLK>, |
| <&clock_gcc GCC_BIMC_MSS_Q6_AXI_CLK>, |
| <&clock_gcc GCC_BOOT_ROM_AHB_CLK>, |
| <&clock_gcc GPLL0_OUT_MSSCC>, |
| <&clock_gcc GCC_MSS_SNOC_AXI_CLK>, |
| <&clock_gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_CLK>; |
| clock-names = "xo", "iface_clk", "bus_clk", |
| "mem_clk", "gpll0_mss_clk", "snoc_axi_clk", |
| "mnoc_axi_clk", "qdss_clk"; |
| qcom,proxy-clock-names = "xo", "qdss_clk"; |
| qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk", |
| "gpll0_mss_clk", "snoc_axi_clk", |
| "mnoc_axi_clk"; |
| |
| qcom,sequential-fw-load; |
| vdd_cx-supply = <&pm660l_s3_level>; |
| vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>; |
| vdd_mx-supply = <&pm660l_s5_level>; |
| vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>; |
| qcom,firmware-name = "modem"; |
| qcom,pil-self-auth; |
| qcom,sysmon-id = <0>; |
| qcom,ssctl-instance-id = <0x12>; |
| qcom,qdsp6v62-1-5; |
| memory-region = <&modem_fw_mem>; |
| qcom,mem-protect-id = <0xF>; |
| qcom,complete-ramdump; |
| qcom,cx-ipeak-vote; |
| |
| /* Inputs from mss */ |
| interrupts-extended = <&wakegic 0 448 1>, |
| <&modem_smp2p_in 0 0>, |
| <&modem_smp2p_in 2 0>, |
| <&modem_smp2p_in 1 0>, |
| <&modem_smp2p_in 3 0>, |
| <&modem_smp2p_in 7 0>; |
| |
| interrupt-names = "qcom,wdog", |
| "qcom,err-fatal", |
| "qcom,proxy-unvote", |
| "qcom,err-ready", |
| "qcom,stop-ack", |
| "qcom,shutdown-ack"; |
| |
| /* Outputs to mss */ |
| qcom,smem-states = <&modem_smp2p_out 0>; |
| qcom,smem-state-names = "qcom,force-stop"; |
| |
| status = "ok"; |
| qcom,mba-mem@0 { |
| compatible = "qcom,pil-mba-mem"; |
| memory-region = <&pil_mba_mem>; |
| }; |
| }; |
| |
| qcom,msm-rtb { |
| compatible = "qcom,msm-rtb"; |
| qcom,rtb-size = <0x100000>; |
| }; |
| |
| qcom,mpm2-sleep-counter@10a3000 { |
| compatible = "qcom,mpm2-sleep-counter"; |
| reg = <0x10a3000 0x1000>; |
| clock-frequency = <32768>; |
| }; |
| |
| qcom,msm-imem@146bf000 { |
| compatible = "qcom,msm-imem"; |
| reg = <0x146bf000 0x1000>; |
| ranges = <0x0 0x146bf000 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| mem_dump_table@10 { |
| compatible = "qcom,msm-imem-mem_dump_table"; |
| reg = <0x10 8>; |
| }; |
| |
| dload_type@1c { |
| compatible = "qcom,msm-imem-dload-type"; |
| reg = <0x1c 4>; |
| }; |
| |
| restart_reason@65c { |
| compatible = "qcom,msm-imem-restart_reason"; |
| reg = <0x65c 4>; |
| }; |
| |
| boot_stats@6b0 { |
| compatible = "qcom,msm-imem-boot_stats"; |
| reg = <0x6b0 32>; |
| }; |
| |
| kaslr_offset@6d0 { |
| compatible = "qcom,msm-imem-kaslr_offset"; |
| reg = <0x6d0 12>; |
| }; |
| |
| pil@94c { |
| compatible = "qcom,msm-imem-pil"; |
| reg = <0x94c 200>; |
| }; |
| |
| diag_dload@c8 { |
| compatible = "qcom,msm-imem-diag-dload"; |
| reg = <0xc8 200>; |
| }; |
| |
| ss_mdump@b88 { |
| compatible = "qcom,msm-imem-minidump"; |
| reg = <0xb88 28>; |
| }; |
| }; |
| |
| qcom,ghd { |
| compatible = "qcom,gladiator-hang-detect"; |
| qcom,threshold-arr = <0x179d141c 0x179d1420 |
| 0x179d1424 0x179d1428 |
| 0x179d142c 0x179d1430>; |
| qcom,config-reg = <0x179d1434>; |
| }; |
| |
| qcom,msm-gladiator-v2@17900000 { |
| compatible = "qcom,msm-gladiator-v2"; |
| reg = <0x17900000 0xe000>; |
| reg-names = "gladiator_base"; |
| interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| clock-names = "atb_clk"; |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>; |
| }; |
| |
| cpu_pmu: cpu-pmu { |
| compatible = "arm,armv8-pmuv3"; |
| qcom,irq-is-percpu; |
| interrupts = <1 6 4>; |
| }; |
| |
| qcom_seecom: qseecom@86d00000 { |
| compatible = "qcom,qseecom"; |
| reg = <0x86d00000 0x2200000>; |
| reg-names = "secapp-region"; |
| qcom,hlos-num-ce-hw-instances = <1>; |
| qcom,hlos-ce-hw-instance = <0>; |
| qcom,qsee-ce-hw-instance = <0>; |
| qcom,disk-encrypt-pipe-pair = <2>; |
| qcom,support-fde; |
| qcom,fde-key-size; |
| qcom,no-clock-support; |
| qcom,msm-bus,name = "qseecom-noc"; |
| qcom,msm-bus,num-cases = <4>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <55 512 0 0>, |
| <55 512 200000 400000>, |
| <55 512 300000 800000>, |
| <55 512 400000 1000000>; |
| clock-names = "core_clk_src", "core_clk", |
| "iface_clk", "bus_clk"; |
| clocks = <&clock_rpmcc QSEECOM_CE1_CLK>, |
| <&clock_rpmcc QSEECOM_CE1_CLK>, |
| <&clock_rpmcc QSEECOM_CE1_CLK>, |
| <&clock_rpmcc QSEECOM_CE1_CLK>; |
| qcom,ce-opp-freq = <171430000>; |
| qcom,qsee-reentrancy-support = <2>; |
| }; |
| |
| qcom_cedev: qcedev@1de0000{ |
| compatible = "qcom,qcedev"; |
| reg = <0x1de0000 0x20000>, |
| <0x1dc4000 0x24000>; |
| reg-names = "crypto-base","crypto-bam-base"; |
| interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,bam-pipe-pair = <1>; |
| qcom,ce-hw-instance = <0>; |
| qcom,ce-device = <0>; |
| qcom,ce-hw-shared; |
| qcom,bam-ee = <0>; |
| qcom,msm-bus,name = "qcedev-noc"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <55 512 0 0>, |
| <55 512 393600 393600>; |
| clock-names = "core_clk_src", "core_clk", |
| "iface_clk", "bus_clk"; |
| clocks = <&clock_rpmcc QCEDEV_CE1_CLK>, |
| <&clock_rpmcc QCEDEV_CE1_CLK>, |
| <&clock_rpmcc QCEDEV_CE1_CLK>, |
| <&clock_rpmcc QCEDEV_CE1_CLK>; |
| qcom,ce-opp-freq = <171430000>; |
| }; |
| |
| qcom_crypto: qcrypto@1de0000 { |
| compatible = "qcom,qcrypto"; |
| reg = <0x1de0000 0x20000>, |
| <0x1dc4000 0x24000>; |
| reg-names = "crypto-base","crypto-bam-base"; |
| interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,bam-pipe-pair = <2>; |
| qcom,ce-hw-instance = <0>; |
| qcom,ce-device = <0>; |
| qcom,bam-ee = <0>; |
| qcom,ce-hw-shared; |
| qcom,clk-mgmt-sus-res; |
| qcom,msm-bus,name = "qcrypto-noc"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <55 512 0 0>, |
| <55 512 393600 393600>; |
| clock-names = "core_clk_src", "core_clk", |
| "iface_clk", "bus_clk"; |
| clocks = <&clock_rpmcc QCRYPTO_CE1_CLK>, |
| <&clock_rpmcc QCRYPTO_CE1_CLK>, |
| <&clock_rpmcc QCRYPTO_CE1_CLK>, |
| <&clock_rpmcc QCRYPTO_CE1_CLK>; |
| qcom,ce-opp-freq = <171430000>; |
| qcom,use-sw-aes-cbc-ecb-ctr-algo; |
| qcom,use-sw-aes-xts-algo; |
| qcom,use-sw-aes-ccm-algo; |
| qcom,use-sw-ahash-algo; |
| qcom,use-sw-aead-algo; |
| qcom,use-sw-hmac-algo; |
| }; |
| |
| qcom_tzlog: tz-log@146bf720 { |
| compatible = "qcom,tz-log"; |
| reg = <0x146bf720 0x3000>; |
| qcom,hyplog-enabled; |
| hyplog-address-offset = <0x410>; |
| hyplog-size-offset = <0x414>; |
| }; |
| |
| qcom_rng: qrng@793000 { |
| compatible = "qcom,msm-rng"; |
| reg = <0x793000 0x1000>; |
| qcom,msm-rng-iface-clk; |
| qcom,no-qrng-config; |
| qcom,msm-bus,name = "msm-rng-noc"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <1 618 0 0>, /* No vote */ |
| <1 618 0 800>; /* 100 KHz */ |
| clocks = <&clock_gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "iface_clk"; |
| }; |
| |
| qcom,chd_silver { |
| compatible = "qcom,core-hang-detect"; |
| label = "silver"; |
| qcom,threshold-arr = <0x179880b0 0x179980b0 |
| 0x179a80b0 0x179b80b0>; |
| qcom,config-arr = <0x179880b8 0x179980b8 |
| 0x179a80b8 0x179b80b8>; |
| }; |
| |
| qcom,chd_gold { |
| compatible = "qcom,core-hang-detect"; |
| label = "gold"; |
| qcom,threshold-arr = <0x178880b0 0x178980b0 |
| 0x178a80b0 0x178b80b0>; |
| qcom,config-arr = <0x178880b8 0x178980b8 |
| 0x178a80b8 0x178b80b8>; |
| }; |
| |
| ufsphy1: ufsphy@1da7000 { |
| compatible = "qcom,ufs-phy-qmp-v3-660"; |
| reg = <0x1da7000 0xdb8>; |
| reg-names = "phy_mem"; |
| #phy-cells = <0>; |
| clock-names = "ref_clk_src", |
| "ref_clk", |
| "ref_aux_clk"; |
| clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK1>, |
| <&clock_gcc GCC_UFS_CLKREF_CLK>, |
| <&clock_gcc GCC_UFS_PHY_AUX_CLK>; |
| status = "disabled"; |
| }; |
| |
| ufs1: ufshc@1da4000 { |
| compatible = "qcom,ufshc"; |
| reg = <0x1da4000 0x3000>, <0x1db0000 0x8000>; |
| reg-names = "ufs_mem", "ufs_ice"; |
| interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&ufsphy1>; |
| phy-names = "ufsphy"; |
| |
| clock-names = |
| "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "core_clk_ice", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk"; |
| clocks = |
| <&clock_gcc GCC_UFS_AXI_CLK>, |
| <&clock_gcc GCC_AGGRE2_UFS_AXI_CLK>, |
| <&clock_gcc GCC_UFS_AHB_CLK>, |
| <&clock_gcc GCC_UFS_UNIPRO_CORE_CLK>, |
| <&clock_gcc GCC_UFS_ICE_CORE_CLK>, |
| <&clock_rpmcc RPM_SMD_LN_BB_CLK1>, |
| <&clock_gcc GCC_UFS_TX_SYMBOL_0_CLK>, |
| <&clock_gcc GCC_UFS_RX_SYMBOL_0_CLK>; |
| freq-table-hz = |
| <50000000 200000000>, |
| <0 0>, |
| <0 0>, |
| <37500000 150000000>, |
| <75000000 300000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| |
| lanes-per-direction = <1>; |
| spm-level = <5>; |
| dev-ref-clk-freq = <0>; /* 19.2 MHz */ |
| |
| non-removable; |
| qcom,msm-bus,name = "ufs1"; |
| qcom,msm-bus,num-cases = <12>; |
| qcom,msm-bus,num-paths = <2>; |
| qcom,msm-bus,vectors-KBps = |
| <95 512 0 0>, <1 650 0 0>, /* No vote */ |
| <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */ |
| <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ |
| <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ |
| <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ |
| <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ |
| <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ |
| <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */ |
| <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ |
| <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ |
| <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */ |
| <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */ |
| qcom,bus-vector-names = "MIN", |
| "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", |
| "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", |
| "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", |
| "MAX"; |
| |
| pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; |
| pinctrl-0 = <&ufs_dev_reset_assert>; |
| pinctrl-1 = <&ufs_dev_reset_deassert>; |
| |
| resets = <&clock_gcc GCC_UFS_BCR>; |
| reset-names = "core_reset"; |
| |
| status = "disabled"; |
| }; |
| |
| jtag_fuse: jtagfuse@786040 { |
| compatible = "qcom,jtag-fuse-v4"; |
| reg = <0x786040 0x8>; |
| reg-names = "fuse-base"; |
| }; |
| |
| jtag_mm0: jtagmm@7840000 { |
| compatible = "qcom,jtagv8-mm"; |
| reg = <0x7840000 0x1000>; |
| reg-names = "etm-base"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| |
| qcom,coresight-jtagmm-cpu = <&CPU0>; |
| }; |
| |
| jtag_mm1: jtagmm@7940000 { |
| compatible = "qcom,jtagv8-mm"; |
| reg = <0x7940000 0x1000>; |
| reg-names = "etm-base"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| |
| qcom,coresight-jtagmm-cpu = <&CPU1>; |
| }; |
| |
| jtag_mm2: jtagmm@7a40000 { |
| compatible = "qcom,jtagv8-mm"; |
| reg = <0x7a40000 0x1000>; |
| reg-names = "etm-base"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| |
| qcom,coresight-jtagmm-cpu = <&CPU2>; |
| }; |
| |
| jtag_mm3: jtagmm@7b40000 { |
| compatible = "qcom,jtagv8-mm"; |
| reg = <0x7b40000 0x1000>; |
| reg-names = "etm-base"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| |
| qcom,coresight-jtagmm-cpu = <&CPU3>; |
| }; |
| |
| jtag_mm4: jtagmm@7c40000 { |
| compatible = "qcom,jtagv8-mm"; |
| reg = <0x7c40000 0x1000>; |
| reg-names = "etm-base"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| |
| qcom,coresight-jtagmm-cpu = <&CPU4>; |
| }; |
| |
| jtag_mm5: jtagmm@7d40000 { |
| compatible = "qcom,jtagv8-mm"; |
| reg = <0x7d40000 0x1000>; |
| reg-names = "etm-base"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| |
| qcom,coresight-jtagmm-cpu = <&CPU5>; |
| }; |
| |
| jtag_mm6: jtagmm@7e40000 { |
| compatible = "qcom,jtagv8-mm"; |
| reg = <0x7e40000 0x1000>; |
| reg-names = "etm-base"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| |
| qcom,coresight-jtagmm-cpu = <&CPU6>; |
| }; |
| |
| jtag_mm7: jtagmm@7f40000 { |
| compatible = "qcom,jtagv8-mm"; |
| reg = <0x7f40000 0x1000>; |
| reg-names = "etm-base"; |
| |
| clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>, |
| <&clock_rpmcc RPM_SMD_QDSS_A_CLK>; |
| clock-names = "core_clk", "core_a_clk"; |
| |
| qcom,coresight-jtagmm-cpu = <&CPU7>; |
| }; |
| }; |
| |
| #include "sdm660-ion.dtsi" |
| #include "sdm660-bus.dtsi" |
| #include "pm660.dtsi" |
| #include "pm660l.dtsi" |
| #include "pm660-rpm-regulator.dtsi" |
| #include "pm660l-rpm-regulator.dtsi" |
| #include "sdm660-regulator.dtsi" |
| #include "msm-gdsc-660.dtsi" |
| #include "sdm660-gpu.dtsi" |
| #include "sdm660-pm.dtsi" |
| #include "sdm660-thermal.dtsi" |
| |
| &gdsc_usb30 { |
| status = "ok"; |
| }; |
| |
| &gdsc_ufs { |
| status = "ok"; |
| }; |
| |
| &gdsc_bimc_smmu { |
| clock-names = "bus_clk"; |
| clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>; |
| proxy-supply = <&gdsc_bimc_smmu>; |
| qcom,proxy-consumer-enable; |
| status = "ok"; |
| }; |
| |
| &gdsc_hlos1_vote_lpass_adsp { |
| status = "ok"; |
| }; |
| |
| &gdsc_hlos1_vote_turing_adsp { |
| status = "ok"; |
| }; |
| |
| &gdsc_hlos2_vote_turing_adsp { |
| status = "ok"; |
| }; |
| |
| &gdsc_venus { |
| status = "ok"; |
| }; |
| |
| &gdsc_venus_core0 { |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &gdsc_camss_top { |
| status = "ok"; |
| }; |
| |
| &gdsc_vfe0 { |
| parent-supply = <&gdsc_camss_top>; |
| status = "ok"; |
| }; |
| |
| &gdsc_vfe1 { |
| parent-supply = <&gdsc_camss_top>; |
| status = "ok"; |
| }; |
| |
| &gdsc_cpp { |
| parent-supply = <&gdsc_camss_top>; |
| qcom,support-hw-trigger; |
| status = "ok"; |
| }; |
| |
| &gdsc_mdss { |
| proxy-supply = <&gdsc_mdss>; |
| qcom,proxy-consumer-enable; |
| status = "ok"; |
| }; |
| |
| &gdsc_gpu_gx { |
| clock-names = "core_root_clk"; |
| clocks = <&clock_gfx GFX3D_CLK_SRC>; |
| qcom,force-enable-root-clk; |
| parent-supply = <&gfx_vreg_corner>; |
| status = "ok"; |
| }; |
| |
| &gdsc_gpu_cx { |
| status = "ok"; |
| }; |
| |
| |
| #include "msm-arm-smmu-660.dtsi" |
| #include "msm-arm-smmu-impl-defs-660.dtsi" |
| #include "sdm660-common.dtsi" |
| #include "sdm660-blsp.dtsi" |
| #include "msm-rdbg.dtsi" |
| #include "sdm660-camera.dtsi" |
| #include "sdm660-vidc.dtsi" |
| #include "msm-audio.dtsi" |
| #include "sdm660-audio.dtsi" |
| |
| &pm660l_gpios { |
| /* GPIO 7 for VOL_UP */ |
| key_vol_up { |
| key_vol_up_default: key_vol_up_default { |
| pins = "gpio7"; |
| function = "normal"; |
| input-enable; |
| bias-pull-up; |
| power-source = <0>; |
| }; |
| }; |
| }; |
| |
| &msm_vidc { |
| qcom,cx-ipeak-data = <&cx_ipeak_lm 4>; |
| qcom,clock-freq-threshold = <518400000>; |
| }; |
| |
| &soc { |
| gpio_keys { |
| status = "okay"; |
| compatible = "gpio-keys"; |
| input-name = "gpio-keys"; |
| pinctrl-names = "tlmm_gpio_key_active","tlmm_gpio_key_suspend", |
| "default"; |
| pinctrl-0 = <&gpio_key_active &key_vol_up_default>; |
| pinctrl-1 = <&gpio_key_suspend>; |
| |
| camera_focus { |
| label = "camera_focus"; |
| gpios = <&tlmm 64 0x1>; |
| linux,input-type = <1>; |
| linux,code = <0x210>; |
| debounce-interval = <15>; |
| }; |
| |
| camera_snapshot { |
| label = "camera_snapshot"; |
| gpios = <&tlmm 113 0x1>; |
| linux,input-type = <1>; |
| linux,code = <0x2fe>; |
| debounce-interval = <15>; |
| }; |
| |
| vol_up { |
| label = "volume_up"; |
| gpios = <&pm660l_gpios 7 0x1>; |
| linux,input-type = <1>; |
| linux,code = <115>; |
| linux,can-disable; |
| gpio-key,wakeup; |
| debounce-interval = <15>; |
| }; |
| }; |
| }; |
| |
| &blsp2_uart1_hs { |
| status = "ok"; |
| }; |
| |
| &pm660_adc_tm { |
| io-channels = <&pm660_vadc ADC_XO_THERM_PU2>, |
| <&pm660_vadc ADC_AMUX_THM1_PU2>, |
| <&pm660_vadc ADC_AMUX_THM5_PU2>; |
| |
| /* Channel nodes */ |
| xo_therm { |
| reg = <ADC_XO_THERM_PU2>; |
| qcom,ratiometric; |
| qcom,hw-settle-time = <200>; |
| }; |
| |
| msm_therm{ |
| reg = <ADC_AMUX_THM1_PU2>; |
| qcom,ratiometric; |
| qcom,hw-settle-time = <200>; |
| }; |
| |
| quiet_therm{ |
| reg = <ADC_AMUX_THM5_PU2>; |
| qcom,ratiometric; |
| qcom,hw-settle-time = <200>; |
| }; |
| }; |
| |
| #include "sdm660-mdss.dtsi" |
| #include "sdm660-mdss-pll.dtsi" |
