| &soc { |
| msm_npu: qcom,msm_npu@9800000 { |
| compatible = "qcom,msm-npu"; |
| status = "ok"; |
| reg = <0x9900000 0x20000>, |
| <0x99F0000 0x10000>, |
| <0x9980000 0x10000>, |
| <0x17c00000 0x10000>, |
| <0x01F40000 0x40000>, |
| <0x780000 0x7000>; |
| reg-names = "tcm", "core", "cc", "apss_shared", "tcsr", |
| "qfprom_physical"; |
| interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq", |
| "general_irq"; |
| iommus = <&apps_smmu 0x1861 0x400>, <&apps_smmu 0x1862 0x400>, |
| <&apps_smmu 0x1881 0x400>, <&apps_smmu 0x1882 0x400>; |
| |
| clocks = <&npucc NPU_CC_XO_CLK>, |
| <&npucc NPU_CC_CORE_CLK>, |
| <&npucc NPU_CC_CAL_HM0_CLK>, |
| <&npucc NPU_CC_CAL_HM0_CDC_CLK>, |
| <&npucc NPU_CC_NOC_AXI_CLK>, |
| <&npucc NPU_CC_NOC_AHB_CLK>, |
| <&npucc NPU_CC_NOC_DMA_CLK>, |
| <&npucc NPU_CC_LLM_CLK>, |
| <&npucc NPU_CC_LLM_XO_CLK>, |
| <&npucc NPU_CC_LLM_TEMP_CLK>, |
| <&npucc NPU_CC_LLM_CURR_CLK>, |
| <&npucc NPU_CC_DL_LLM_CLK>, |
| <&npucc NPU_CC_ISENSE_CLK>, |
| <&npucc NPU_CC_DPM_CLK>, |
| <&npucc NPU_CC_DPM_XO_CLK>, |
| <&npucc NPU_CC_DL_DPM_CLK>, |
| <&npucc NPU_CC_RSC_XO_CLK>, |
| <&npucc NPU_CC_DPM_TEMP_CLK>, |
| <&npucc NPU_CC_CAL_HM0_DPM_IP_CLK>, |
| <&npucc NPU_CC_S2P_CLK>, |
| <&npucc NPU_CC_BWMON_CLK>, |
| <&npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>, |
| <&npucc NPU_CC_BTO_CORE_CLK>, |
| <&npucc NPU_DSP_CORE_CLK_SRC>; |
| clock-names = "xo_clk", |
| "npu_core_clk", |
| "cal_hm0_clk", |
| "cal_hm0_cdc_clk", |
| "axi_clk", |
| "ahb_clk", |
| "dma_clk", |
| "llm_clk", |
| "llm_xo_clk", |
| "llm_temp_clk", |
| "llm_curr_clk", |
| "dl_llm_clk", |
| "isense_clk", |
| "dpm_clk", |
| "dpm_xo_clk", |
| "dl_dpm_clk", |
| "rsc_xo_clk", |
| "dpm_temp_clk", |
| "cal_hm0_dpm_ip_clk", |
| "s2p_clk", |
| "bwmon_clk", |
| "cal_hm0_perf_cnt_clk", |
| "bto_core_clk", |
| "dsp_core_clk_src"; |
| |
| vdd-supply = <&npu_core_gdsc>; |
| vdd_cx-supply = <&VDD_CX_LEVEL>; |
| qcom,proxy-reg-names ="vdd", "vdd_cx"; |
| qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>; |
| resets = <&npucc NPU_CC_DPM_TEMP_CLK_ARES>, |
| <&npucc NPU_CC_LLM_CURR_CLK_ARES>, |
| <&npucc NPU_CC_LLM_TEMP_CLK_ARES>; |
| reset-names = "dpm_temp_clk", "llm_curr_clk", "llm_temp_clk"; |
| #cooling-cells = <2>; |
| mboxes = <&ipcc_mproc IPCC_CLIENT_NPU |
| IPCC_MPROC_SIGNAL_GLINK_QMP>, |
| <&ipcc_mproc IPCC_CLIENT_NPU |
| IPCC_MPROC_SIGNAL_SMP2P>, |
| <&ipcc_mproc IPCC_CLIENT_NPU |
| IPCC_MPROC_SIGNAL_PING>; |
| mbox-names = "ipcc-glink", "ipcc-smp2p", "ipcc-ping"; |
| #mbox-cells = <2>; |
| qcom,npubw-devs = <&npu_npu_llcc_bw &npu_llcc_ddr_bw &npudsp_npu_ddr_bw>; |
| qcom,npubw-dev-names = "npu_llcc_bw", "llcc_ddr_bw", "dsp_ddr_bw"; |
| qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>, |
| <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CLK_CTL>; |
| qcom,npu-pwrlevels { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "qcom,npu-pwrlevels"; |
| initial-pwrlevel = <5>; |
| qcom,npu-pwrlevel@0 { |
| reg = <0>; |
| vreg = <1>; |
| clk-freq = <19200000 |
| 100000000 |
| 230000000 |
| 230000000 |
| 150000000 |
| 40000000 |
| 300000000 |
| 100000000 |
| 19200000 |
| 50000000 |
| 50000000 |
| 100000000 |
| 100000000 |
| 100000000 |
| 19200000 |
| 100000000 |
| 19200000 |
| 50000000 |
| 230000000 |
| 50000000 |
| 19200000 |
| 230000000 |
| 19200000 |
| 300000000>; |
| }; |
| |
| qcom,npu-pwrlevel@1 { |
| reg = <1>; |
| vreg = <2>; |
| clk-freq = <19200000 |
| 200000000 |
| 422000000 |
| 422000000 |
| 207000000 |
| 40000000 |
| 403000000 |
| 200000000 |
| 19200000 |
| 50000000 |
| 50000000 |
| 200000000 |
| 200000000 |
| 200000000 |
| 19200000 |
| 200000000 |
| 19200000 |
| 50000000 |
| 422000000 |
| 50000000 |
| 19200000 |
| 422000000 |
| 19200000 |
| 400000000>; |
| }; |
| |
| qcom,npu-pwrlevel@2 { |
| reg = <2>; |
| vreg = <3>; |
| clk-freq = <19200000 |
| 333000000 |
| 557000000 |
| 557000000 |
| 300000000 |
| 75000000 |
| 533000000 |
| 214000000 |
| 19200000 |
| 50000000 |
| 100000000 |
| 214000000 |
| 214000000 |
| 214000000 |
| 19200000 |
| 214000000 |
| 19200000 |
| 50000000 |
| 557000000 |
| 50000000 |
| 19200000 |
| 557000000 |
| 19200000 |
| 500000000>; |
| }; |
| |
| qcom,npu-pwrlevel@3 { |
| reg = <3>; |
| vreg = <4>; |
| clk-freq = <19200000 |
| 428000000 |
| 729000000 |
| 729000000 |
| 403000000 |
| 75000000 |
| 700000000 |
| 300000000 |
| 19200000 |
| 100000000 |
| 200000000 |
| 300000000 |
| 300000000 |
| 300000000 |
| 19200000 |
| 300000000 |
| 19200000 |
| 100000000 |
| 729000000 |
| 100000000 |
| 19200000 |
| 729000000 |
| 19200000 |
| 660000000>; |
| }; |
| |
| qcom,npu-pwrlevel@4 { |
| reg = <4>; |
| vreg = <6>; |
| clk-freq = <19200000 |
| 500000000 |
| 844000000 |
| 844000000 |
| 533000000 |
| 75000000 |
| 806000000 |
| 300000000 |
| 19200000 |
| 100000000 |
| 200000000 |
| 300000000 |
| 300000000 |
| 300000000 |
| 19200000 |
| 300000000 |
| 19200000 |
| 100000000 |
| 844000000 |
| 100000000 |
| 19200000 |
| 844000000 |
| 19200000 |
| 800000000>; |
| }; |
| |
| qcom,npu-pwrlevel@5 { |
| reg = <5>; |
| vreg = <7>; |
| clk-freq = <19200000 |
| 500000000 |
| 1000000000 |
| 1000000000 |
| 533000000 |
| 75000000 |
| 806000000 |
| 300000000 |
| 19200000 |
| 100000000 |
| 200000000 |
| 300000000 |
| 300000000 |
| 300000000 |
| 19200000 |
| 300000000 |
| 19200000 |
| 100000000 |
| 1000000000 |
| 100000000 |
| 19200000 |
| 1000000000 |
| 19200000 |
| 800000000>; |
| }; |
| }; |
| }; |
| }; |
