| /* |
| * This file is part of the UWB stack for linux. |
| * |
| * Copyright (c) 2020 Qorvo US, Inc. |
| * |
| * This software is provided under the GNU General Public License, version 2 |
| * (GPLv2), as well as under a Qorvo commercial license. |
| * |
| * You may choose to use this software under the terms of the GPLv2 License, |
| * version 2 ("GPLv2"), as published by the Free Software Foundation. |
| * You should have received a copy of the GPLv2 along with this program. If |
| * not, see <http://www.gnu.org/licenses/>. |
| * |
| * This program is distributed under the GPLv2 in the hope that it will be |
| * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GPLv2 for more |
| * details. |
| * |
| * If you cannot meet the requirements of the GPLv2, you may not use this |
| * software for any purpose without first obtaining a commercial license from |
| * Qorvo. |
| * Please contact Qorvo to inquire about licensing terms. |
| */ |
| #ifndef __DW3000_CORE_REG_H |
| #define __DW3000_CORE_REG_H |
| |
| #include "dw3000_compat_reg.h" |
| |
| /* |
| * Please, keep registers defines ordered by address. |
| * This will ease finding duplicate or renaming. |
| */ |
| |
| /* register DEV_ID */ |
| #define DW3000_DEV_ID_ID 0x0 |
| |
| /* register EUI_64 */ |
| #define DW3000_EUI_64_ID 0x4 |
| #define DW3000_EUI_64_LEN (8U) |
| |
| /* register SYS_CFG */ |
| #define DW3000_SYS_CFG_ID 0x10 |
| #define DW3000_SYS_CFG_LEN (4U) |
| #define DW3000_SYS_CFG_MASK 0xFFFFFFFFUL |
| #define DW3000_SYS_CFG_COEX_OUT_MODE_BIT_OFFSET (23U) |
| #define DW3000_SYS_CFG_COEX_OUT_MODE_BIT_LEN (2U) |
| #define DW3000_SYS_CFG_COEX_OUT_MODE_BIT_MASK 0x1800000UL |
| #define DW3000_SYS_CFG_DS_IE2_BIT_OFFSET (20U) |
| #define DW3000_SYS_CFG_DS_IE2_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_DS_IE2_BIT_MASK 0x100000UL |
| #define DW3000_SYS_CFG_FAST_AAT_EN_BIT_OFFSET (18U) |
| #define DW3000_SYS_CFG_FAST_AAT_EN_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_FAST_AAT_EN_BIT_MASK 0x40000UL |
| #define DW3000_SYS_CFG_PDOA_MODE_BIT_OFFSET (16U) |
| #define DW3000_SYS_CFG_PDOA_MODE_BIT_LEN (2U) |
| #define DW3000_SYS_CFG_PDOA_MODE_BIT_MASK 0x30000UL |
| #define DW3000_SYS_CFG_CP_SDC_BIT_OFFSET (15U) |
| #define DW3000_SYS_CFG_CP_SDC_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_CP_SDC_BIT_MASK 0x8000U |
| #define DW3000_SYS_CFG_CP_TYPE_BIT_OFFSET (14U) |
| #define DW3000_SYS_CFG_CP_TYPE_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_CP_TYPE_BIT_MASK 0x4000U |
| #define DW3000_SYS_CFG_CP_PROTOCOL_BIT_OFFSET (12U) |
| #define DW3000_SYS_CFG_CP_PROTOCOL_BIT_LEN (2U) |
| #define DW3000_SYS_CFG_CP_PROTOCOL_BIT_MASK 0x3000U |
| #define DW3000_SYS_CFG_AUTO_ACK_BIT_OFFSET (11U) |
| #define DW3000_SYS_CFG_AUTO_ACK_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_AUTO_ACK_BIT_MASK 0x800U |
| #define DW3000_SYS_CFG_RXAUTR_BIT_OFFSET (10U) |
| #define DW3000_SYS_CFG_RXAUTR_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_RXAUTR_BIT_MASK 0x400U |
| #define DW3000_SYS_CFG_RXWTOE_BIT_OFFSET (9U) |
| #define DW3000_SYS_CFG_RXWTOE_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_RXWTOE_BIT_MASK 0x200U |
| #define DW3000_SYS_CFG_CIA_STS_BIT_OFFSET (8U) |
| #define DW3000_SYS_CFG_CIA_STS_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_CIA_STS_BIT_MASK 0x100U |
| #define DW3000_SYS_CFG_CIA_IPATOV_BIT_OFFSET (7U) |
| #define DW3000_SYS_CFG_CIA_IPATOV_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_CIA_IPATOV_BIT_MASK 0x80U |
| #define DW3000_SYS_CFG_SPI_CRC_BIT_OFFSET (6U) |
| #define DW3000_SYS_CFG_SPI_CRC_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_SPI_CRC_BIT_MASK 0x40U |
| #define DW3000_SYS_CFG_PHR_6M8_BIT_OFFSET (5U) |
| #define DW3000_SYS_CFG_PHR_6M8_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_PHR_6M8_BIT_MASK 0x20U |
| #define DW3000_SYS_CFG_PHR_MODE_BIT_OFFSET (4U) |
| #define DW3000_SYS_CFG_PHR_MODE_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_PHR_MODE_BIT_MASK 0x10U |
| #define DW3000_SYS_CFG_EN_DRXB_BIT_OFFSET (3U) |
| #define DW3000_SYS_CFG_EN_DRXB_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_EN_DRXB_BIT_MASK 0x8U |
| #define DW3000_SYS_CFG_DIS_FCE_BIT_OFFSET (2U) |
| #define DW3000_SYS_CFG_DIS_FCE_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_DIS_FCE_BIT_MASK 0x4U |
| #define DW3000_SYS_CFG_DIS_FCS_TX_BIT_OFFSET (1U) |
| #define DW3000_SYS_CFG_DIS_FCS_TX_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_DIS_FCS_TX_BIT_MASK 0x2U |
| #define DW3000_SYS_CFG_FFEN_BIT_OFFSET (0U) |
| #define DW3000_SYS_CFG_FFEN_BIT_LEN (1U) |
| #define DW3000_SYS_CFG_FFEN_BIT_MASK 0x1U |
| |
| /* register PANADR */ |
| #define DW3000_PANADR_ID 0xc |
| #define DW3000_PANADR_SHORT_ADDR_BIT_OFFSET (0U) |
| #define DW3000_PANADR_SHORT_ADDR_BIT_LEN (2U) |
| #define DW3000_PANADR_PAN_ID_BIT_OFFSET (16U) |
| #define DW3000_PANADR_PAN_ID_BIT_LEN (2U) |
| |
| /* register ADR_FILT_CFG */ |
| #define DW3000_ADR_FILT_CFG_ID 0x14 |
| #define DW3000_ADR_FILT_CFG_FFBC_BIT_LEN (1U) |
| /* DW3000 as pan coordinator */ |
| #define DW3000_AS_PANCOORD 0x01 |
| |
| /* register SPICRC_CFG */ |
| #define DW3000_SPICRC_CFG_ID 0x18 |
| |
| /* register SYS_TIME */ |
| #define DW3000_SYS_TIME_ID 0x1c |
| |
| /* register TX_FCTRL_HI 0x24, 0x20 */ |
| #define DW3000_TX_FCTRL_LEN (4U) |
| #define DW3000_TX_FCTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_TX_FCTRL_TXB_OFFSET_BIT_OFFSET (16U) |
| #define DW3000_TX_FCTRL_TXB_OFFSET_BIT_LEN (10U) |
| #define DW3000_TX_FCTRL_TXB_OFFSET_BIT_MASK 0x3ff0000UL |
| #define DW3000_TX_FCTRL_TXPSR_PE_BIT_OFFSET (12U) |
| #define DW3000_TX_FCTRL_TXPSR_PE_BIT_LEN (4U) |
| #define DW3000_TX_FCTRL_TXPSR_PE_BIT_MASK 0xf000U |
| #define DW3000_TX_FCTRL_TR_BIT_OFFSET (11U) |
| #define DW3000_TX_FCTRL_TR_BIT_LEN (1U) |
| #define DW3000_TX_FCTRL_TR_BIT_MASK 0x800U |
| #define DW3000_TX_FCTRL_TXBR_BIT_OFFSET (10U) |
| #define DW3000_TX_FCTRL_TXBR_BIT_LEN (1U) |
| #define DW3000_TX_FCTRL_TXBR_BIT_MASK 0x400U |
| #define DW3000_TX_FCTRL_TXFLEN_BIT_OFFSET (0U) |
| #define DW3000_TX_FCTRL_TXFLEN_BIT_LEN (10U) |
| #define DW3000_TX_FCTRL_TXFLEN_BIT_MASK 0x3ffU |
| |
| /* register SYS_ENABLE_LO */ |
| #define DW3000_SYS_ENABLE_LO_ID 0x3c |
| #define DW3000_SYS_ENABLE_LO_LEN (4U) |
| #define DW3000_SYS_ENABLE_LO_MASK 0xFFFFFFFFUL |
| #define DW3000_SYS_ENABLE_LO_ARFE_ENABLE_BIT_OFFSET (29U) |
| #define DW3000_SYS_ENABLE_LO_ARFE_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_ARFE_ENABLE_BIT_MASK 0x20000000UL |
| #define DW3000_SYS_ENABLE_LO_CPERR_ENABLE_BIT_OFFSET (28U) |
| #define DW3000_SYS_ENABLE_LO_CPERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_CPERR_ENABLE_BIT_MASK 0x10000000UL |
| #define DW3000_SYS_ENABLE_LO_HPDWARN_ENABLE_BIT_OFFSET (27U) |
| #define DW3000_SYS_ENABLE_LO_HPDWARN_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_HPDWARN_ENABLE_BIT_MASK 0x8000000UL |
| #define DW3000_SYS_ENABLE_LO_RXSTO_ENABLE_BIT_OFFSET (26U) |
| #define DW3000_SYS_ENABLE_LO_RXSTO_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXSTO_ENABLE_BIT_MASK 0x4000000UL |
| #define DW3000_SYS_ENABLE_LO_PLL_HILO_ENABLE_BIT_OFFSET (25U) |
| #define DW3000_SYS_ENABLE_LO_PLL_HILO_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_PLL_HILO_ENABLE_BIT_MASK 0x2000000UL |
| #define DW3000_SYS_ENABLE_LO_RCINIT_ENABLE_BIT_OFFSET (24U) |
| #define DW3000_SYS_ENABLE_LO_RCINIT_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RCINIT_ENABLE_BIT_MASK 0x1000000UL |
| #define DW3000_SYS_ENABLE_LO_SPIRDY_ENABLE_BIT_OFFSET (23U) |
| #define DW3000_SYS_ENABLE_LO_SPIRDY_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_SPIRDY_ENABLE_BIT_MASK 0x800000UL |
| #define DW3000_SYS_ENABLE_LO_LCSSERR_ENABLE_BIT_OFFSET (22U) |
| #define DW3000_SYS_ENABLE_LO_LCSSERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_LCSSERR_ENABLE_BIT_MASK 0x400000UL |
| #define DW3000_SYS_ENABLE_LO_RXPTO_ENABLE_BIT_OFFSET (21U) |
| #define DW3000_SYS_ENABLE_LO_RXPTO_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXPTO_ENABLE_BIT_MASK 0x200000UL |
| #define DW3000_SYS_ENABLE_LO_RXOVRR_ENABLE_BIT_OFFSET (20U) |
| #define DW3000_SYS_ENABLE_LO_RXOVRR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXOVRR_ENABLE_BIT_MASK 0x100000UL |
| #define DW3000_SYS_ENABLE_LO_VWARN_ENABLE_BIT_OFFSET (19U) |
| #define DW3000_SYS_ENABLE_LO_VWARN_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_VWARN_ENABLE_BIT_MASK 0x80000UL |
| #define DW3000_SYS_ENABLE_LO_CIAERR_ENABLE_BIT_OFFSET (18U) |
| #define DW3000_SYS_ENABLE_LO_CIAERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_CIAERR_ENABLE_BIT_MASK 0x40000UL |
| #define DW3000_SYS_ENABLE_LO_RXFTO_ENABLE_BIT_OFFSET (17U) |
| #define DW3000_SYS_ENABLE_LO_RXFTO_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXFTO_ENABLE_BIT_MASK 0x20000UL |
| #define DW3000_SYS_ENABLE_LO_RXFSL_ENABLE_BIT_OFFSET (16U) |
| #define DW3000_SYS_ENABLE_LO_RXFSL_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXFSL_ENABLE_BIT_MASK 0x10000UL |
| #define DW3000_SYS_ENABLE_LO_RXFCE_ENABLE_BIT_OFFSET (15U) |
| #define DW3000_SYS_ENABLE_LO_RXFCE_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXFCE_ENABLE_BIT_MASK 0x8000U |
| #define DW3000_SYS_ENABLE_LO_RXFCG_ENABLE_BIT_OFFSET (14U) |
| #define DW3000_SYS_ENABLE_LO_RXFCG_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXFCG_ENABLE_BIT_MASK 0x4000U |
| #define DW3000_SYS_ENABLE_LO_RXFR_ENABLE_BIT_OFFSET (13U) |
| #define DW3000_SYS_ENABLE_LO_RXFR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXFR_ENABLE_BIT_MASK 0x2000U |
| #define DW3000_SYS_ENABLE_LO_RXPHE_ENABLE_BIT_OFFSET (12U) |
| #define DW3000_SYS_ENABLE_LO_RXPHE_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXPHE_ENABLE_BIT_MASK 0x1000U |
| #define DW3000_SYS_ENABLE_LO_RXPHD_ENABLE_BIT_OFFSET (11U) |
| #define DW3000_SYS_ENABLE_LO_RXPHD_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXPHD_ENABLE_BIT_MASK 0x800U |
| #define DW3000_SYS_ENABLE_LO_CIA_DONE_ENABLE_BIT_OFFSET (10U) |
| #define DW3000_SYS_ENABLE_LO_CIA_DONE_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_CIA_DONE_ENABLE_BIT_MASK 0x400U |
| #define DW3000_SYS_ENABLE_LO_RXSFDD_ENABLE_BIT_OFFSET (9U) |
| #define DW3000_SYS_ENABLE_LO_RXSFDD_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXSFDD_ENABLE_BIT_MASK 0x200U |
| #define DW3000_SYS_ENABLE_LO_RXPRD_ENABLE_BIT_OFFSET (8U) |
| #define DW3000_SYS_ENABLE_LO_RXPRD_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_RXPRD_ENABLE_BIT_MASK 0x100U |
| #define DW3000_SYS_ENABLE_LO_TXFRS_ENABLE_BIT_OFFSET (7U) |
| #define DW3000_SYS_ENABLE_LO_TXFRS_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_TXFRS_ENABLE_BIT_MASK 0x80U |
| #define DW3000_SYS_ENABLE_LO_TXPHS_ENABLE_BIT_OFFSET (6U) |
| #define DW3000_SYS_ENABLE_LO_TXPHS_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_TXPHS_ENABLE_BIT_MASK 0x40U |
| #define DW3000_SYS_ENABLE_LO_TXPRS_ENABLE_BIT_OFFSET (5U) |
| #define DW3000_SYS_ENABLE_LO_TXPRS_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_TXPRS_ENABLE_BIT_MASK 0x20U |
| #define DW3000_SYS_ENABLE_LO_TXFRB_ENABLE_BIT_OFFSET (4U) |
| #define DW3000_SYS_ENABLE_LO_TXFRB_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_TXFRB_ENABLE_BIT_MASK 0x10U |
| #define DW3000_SYS_ENABLE_LO_AAT_ENABLE_BIT_OFFSET (3U) |
| #define DW3000_SYS_ENABLE_LO_AAT_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_AAT_ENABLE_BIT_MASK 0x8U |
| #define DW3000_SYS_ENABLE_LO_SPICRCERR_ENABLE_BIT_OFFSET (2U) |
| #define DW3000_SYS_ENABLE_LO_SPICRCERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_SPICRCERR_ENABLE_BIT_MASK 0x4U |
| #define DW3000_SYS_ENABLE_LO_CLK_PLL_LOCK_ENABLE_BIT_OFFSET (1U) |
| #define DW3000_SYS_ENABLE_LO_CLK_PLL_LOCK_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_LO_CLK_PLL_LOCK_ENABLE_BIT_MASK 0x2U |
| |
| /* register SYS_ENABLE_HI */ |
| #define DW3000_SYS_ENABLE_HI_ID 0x40 |
| #define DW3000_SYS_ENABLE_HI_LEN (4U) |
| #define DW3000_SYS_ENABLE_HI_MASK 0xFFFFFFFFUL |
| #define DW3000_SYS_ENABLE_HI_RXSTS_ENABLE_BIT_OFFSET (17U) |
| #define DW3000_SYS_ENABLE_HI_RXSTS_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_RXSTS_ENABLE_BIT_MASK 0x20000UL |
| #define DW3000_SYS_ENABLE_HI_TXSTS_ENABLE_BIT_OFFSET (16U) |
| #define DW3000_SYS_ENABLE_HI_TXSTS_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_TXSTS_ENABLE_BIT_MASK 0x10000UL |
| #define DW3000_SYS_ENABLE_HI_SEMA_ERR_ENABLE_BIT_OFFSET (15U) |
| #define DW3000_SYS_ENABLE_HI_SEMA_ERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_SEMA_ERR_ENABLE_BIT_MASK 0x8000U |
| #define DW3000_SYS_ENABLE_HI_COEX_CLR_ENABLE_BIT_OFFSET (14U) |
| #define DW3000_SYS_ENABLE_HI_COEX_CLR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_COEX_CLR_ENABLE_BIT_MASK 0x4000U |
| #define DW3000_SYS_ENABLE_HI_COEX_ERR_ENABLE_BIT_OFFSET (13U) |
| #define DW3000_SYS_ENABLE_HI_COEX_ERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_COEX_ERR_ENABLE_BIT_MASK 0x2000U |
| #define DW3000_SYS_ENABLE_HI_CCA_FAIL_ENABLE_BIT_OFFSET (12U) |
| #define DW3000_SYS_ENABLE_HI_CCA_FAIL_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_CCA_FAIL_ENABLE_BIT_MASK 0x1000U |
| #define DW3000_SYS_ENABLE_HI_SPIERR_ENABLE_BIT_OFFSET (11U) |
| #define DW3000_SYS_ENABLE_HI_SPIERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_SPIERR_ENABLE_BIT_MASK 0x800U |
| #define DW3000_SYS_ENABLE_HI_SPI_UNF_ENABLE_BIT_OFFSET (10U) |
| #define DW3000_SYS_ENABLE_HI_SPI_UNF_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_SPI_UNF_ENABLE_BIT_MASK 0x400U |
| #define DW3000_SYS_ENABLE_HI_SPI_OVF_ENABLE_BIT_OFFSET (9U) |
| #define DW3000_SYS_ENABLE_HI_SPI_OVF_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_SPI_OVF_ENABLE_BIT_MASK 0x200U |
| #define DW3000_SYS_ENABLE_HI_CMD_ERR_ENABLE_BIT_OFFSET (8U) |
| #define DW3000_SYS_ENABLE_HI_CMD_ERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_CMD_ERR_ENABLE_BIT_MASK 0x100U |
| #define DW3000_SYS_ENABLE_HI_AES_ERR_ENABLE_BIT_OFFSET (7U) |
| #define DW3000_SYS_ENABLE_HI_AES_ERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_AES_ERR_ENABLE_BIT_MASK 0x80U |
| #define DW3000_SYS_ENABLE_HI_AES_DONE_ENABLE_BIT_OFFSET (6U) |
| #define DW3000_SYS_ENABLE_HI_AES_DONE_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_AES_DONE_ENABLE_BIT_MASK 0x40U |
| #define DW3000_SYS_ENABLE_HI_GPIOIRQ_ENABLE_BIT_OFFSET (5U) |
| #define DW3000_SYS_ENABLE_HI_GPIOIRQ_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_GPIOIRQ_ENABLE_BIT_MASK 0x20U |
| #define DW3000_SYS_ENABLE_HI_VT_DET_ENABLE_BIT_OFFSET (4U) |
| #define DW3000_SYS_ENABLE_HI_VT_DET_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_VT_DET_ENABLE_BIT_MASK 0x10U |
| #define DW3000_SYS_ENABLE_HI_PGFCAL_ERR_ENABLE_BIT_OFFSET (2U) |
| #define DW3000_SYS_ENABLE_HI_PGFCAL_ERR_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_PGFCAL_ERR_ENABLE_BIT_MASK 0x4U |
| #define DW3000_SYS_ENABLE_HI_RXPREJ_ENABLE_BIT_OFFSET (1U) |
| #define DW3000_SYS_ENABLE_HI_RXPREJ_ENABLE_BIT_LEN (1U) |
| #define DW3000_SYS_ENABLE_HI_RXPREJ_ENABLE_BIT_MASK 0x2U |
| |
| /* register SYS_STATUS */ |
| #define DW3000_SYS_STATUS_ID 0x44 |
| #define DW3000_SYS_STATUS_LEN (4U) |
| #define DW3000_SYS_STATUS_MASK 0xFFFFFFFFUL |
| #define DW3000_SYS_STATUS_TIMER1_BIT_OFFSET (31U) |
| #define DW3000_SYS_STATUS_TIMER1_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_TIMER1_BIT_MASK 0x80000000UL |
| #define DW3000_SYS_STATUS_TIMER0_BIT_OFFSET (30U) |
| #define DW3000_SYS_STATUS_TIMER0_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_TIMER0_BIT_MASK 0x40000000UL |
| #define DW3000_SYS_STATUS_ARFE_BIT_OFFSET (29U) |
| #define DW3000_SYS_STATUS_ARFE_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_ARFE_BIT_MASK 0x20000000UL |
| #define DW3000_SYS_STATUS_CPERR_BIT_OFFSET (28U) |
| #define DW3000_SYS_STATUS_CPERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_CPERR_BIT_MASK 0x10000000UL |
| #define DW3000_SYS_STATUS_HPDWARN_BIT_OFFSET (27U) |
| #define DW3000_SYS_STATUS_HPDWARN_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HPDWARN_BIT_MASK 0x8000000UL |
| #define DW3000_SYS_STATUS_RXSTO_BIT_OFFSET (26U) |
| #define DW3000_SYS_STATUS_RXSTO_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXSTO_BIT_MASK 0x4000000UL |
| #define DW3000_SYS_STATUS_PLL_HILO_BIT_OFFSET (25U) |
| #define DW3000_SYS_STATUS_PLL_HILO_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_PLL_HILO_BIT_MASK 0x2000000UL |
| #define DW3000_SYS_STATUS_RCINIT_BIT_OFFSET (24U) |
| #define DW3000_SYS_STATUS_RCINIT_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RCINIT_BIT_MASK 0x1000000UL |
| #define DW3000_SYS_STATUS_SPIRDY_BIT_OFFSET (23U) |
| #define DW3000_SYS_STATUS_SPIRDY_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_SPIRDY_BIT_MASK 0x800000UL |
| #define DW3000_SYS_STATUS_LCSSERR_BIT_OFFSET (22U) |
| #define DW3000_SYS_STATUS_LCSSERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_LCSSERR_BIT_MASK 0x400000UL |
| #define DW3000_SYS_STATUS_RXPTO_BIT_OFFSET (21U) |
| #define DW3000_SYS_STATUS_RXPTO_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXPTO_BIT_MASK 0x200000UL |
| #define DW3000_SYS_STATUS_RXOVRR_BIT_OFFSET (20U) |
| #define DW3000_SYS_STATUS_RXOVRR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXOVRR_BIT_MASK 0x100000UL |
| #define DW3000_SYS_STATUS_VWARN_BIT_OFFSET (19U) |
| #define DW3000_SYS_STATUS_VWARN_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_VWARN_BIT_MASK 0x80000UL |
| #define DW3000_SYS_STATUS_CIAERR_BIT_OFFSET (18U) |
| #define DW3000_SYS_STATUS_CIAERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_CIAERR_BIT_MASK 0x40000UL |
| #define DW3000_SYS_STATUS_RXFTO_BIT_OFFSET (17U) |
| #define DW3000_SYS_STATUS_RXFTO_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXFTO_BIT_MASK 0x20000UL |
| #define DW3000_SYS_STATUS_RXFSL_BIT_OFFSET (16U) |
| #define DW3000_SYS_STATUS_RXFSL_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXFSL_BIT_MASK 0x10000UL |
| #define DW3000_SYS_STATUS_RXFCE_BIT_OFFSET (15U) |
| #define DW3000_SYS_STATUS_RXFCE_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXFCE_BIT_MASK 0x8000U |
| #define DW3000_SYS_STATUS_RXFCG_BIT_OFFSET (14U) |
| #define DW3000_SYS_STATUS_RXFCG_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXFCG_BIT_MASK 0x4000U |
| #define DW3000_SYS_STATUS_RXFR_BIT_OFFSET (13U) |
| #define DW3000_SYS_STATUS_RXFR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXFR_BIT_MASK 0x2000U |
| #define DW3000_SYS_STATUS_RXPHE_BIT_OFFSET (12U) |
| #define DW3000_SYS_STATUS_RXPHE_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXPHE_BIT_MASK 0x1000U |
| #define DW3000_SYS_STATUS_RXPHD_BIT_OFFSET (11U) |
| #define DW3000_SYS_STATUS_RXPHD_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXPHD_BIT_MASK 0x800U |
| #define DW3000_SYS_STATUS_CIA_DONE_BIT_OFFSET (10U) |
| #define DW3000_SYS_STATUS_CIA_DONE_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_CIA_DONE_BIT_MASK 0x400U |
| #define DW3000_SYS_STATUS_RXSFDD_BIT_OFFSET (9U) |
| #define DW3000_SYS_STATUS_RXSFDD_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXSFDD_BIT_MASK 0x200U |
| #define DW3000_SYS_STATUS_RXPRD_BIT_OFFSET (8U) |
| #define DW3000_SYS_STATUS_RXPRD_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_RXPRD_BIT_MASK 0x100U |
| #define DW3000_SYS_STATUS_TXFRS_BIT_OFFSET (7U) |
| #define DW3000_SYS_STATUS_TXFRS_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_TXFRS_BIT_MASK 0x80U |
| #define DW3000_SYS_STATUS_TXPHS_BIT_OFFSET (6U) |
| #define DW3000_SYS_STATUS_TXPHS_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_TXPHS_BIT_MASK 0x40U |
| #define DW3000_SYS_STATUS_TXPRS_BIT_OFFSET (5U) |
| #define DW3000_SYS_STATUS_TXPRS_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_TXPRS_BIT_MASK 0x20U |
| #define DW3000_SYS_STATUS_TXFRB_BIT_OFFSET (4U) |
| #define DW3000_SYS_STATUS_TXFRB_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_TXFRB_BIT_MASK 0x10U |
| #define DW3000_SYS_STATUS_AAT_BIT_OFFSET (3U) |
| #define DW3000_SYS_STATUS_AAT_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_AAT_BIT_MASK 0x8U |
| #define DW3000_SYS_STATUS_SPICRCERR_BIT_OFFSET (2U) |
| #define DW3000_SYS_STATUS_SPICRCERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_SPICRCERR_BIT_MASK 0x4U |
| #define DW3000_SYS_STATUS_CLK_PLL_LOCK_BIT_OFFSET (1U) |
| #define DW3000_SYS_STATUS_CLK_PLL_LOCK_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_CLK_PLL_LOCK_BIT_MASK 0x2U |
| #define DW3000_SYS_STATUS_IRQS_BIT_OFFSET (0U) |
| #define DW3000_SYS_STATUS_IRQS_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_IRQS_BIT_MASK 0x1U |
| |
| /* register SYS_STATUS_HI */ |
| #define DW3000_SYS_STATUS_HI_ID 0x48 |
| #define DW3000_SYS_STATUS_HI_LEN (4U) |
| #define DW3000_SYS_STATUS_HI_MASK 0xFFFFFFFFUL |
| #define DW3000_SYS_STATUS_HI_RXSTS_BIT_OFFSET (17U) |
| #define DW3000_SYS_STATUS_HI_RXSTS_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_RXSTS_BIT_MASK 0x20000UL |
| #define DW3000_SYS_STATUS_HI_TXSTS_BIT_OFFSET (16U) |
| #define DW3000_SYS_STATUS_HI_TXSTS_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_TXSTS_BIT_MASK 0x10000UL |
| #define DW3000_SYS_STATUS_HI_SEMA_ERR_BIT_OFFSET (15U) |
| #define DW3000_SYS_STATUS_HI_SEMA_ERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_SEMA_ERR_BIT_MASK 0x8000U |
| #define DW3000_SYS_STATUS_HI_COEX_CLR_BIT_OFFSET (14U) |
| #define DW3000_SYS_STATUS_HI_COEX_CLR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_COEX_CLR_BIT_MASK 0x4000U |
| #define DW3000_SYS_STATUS_HI_COEX_ERR_BIT_OFFSET (13U) |
| #define DW3000_SYS_STATUS_HI_COEX_ERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_COEX_ERR_BIT_MASK 0x2000U |
| #define DW3000_SYS_STATUS_HI_CCA_FAIL_BIT_OFFSET (12U) |
| #define DW3000_SYS_STATUS_HI_CCA_FAIL_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_CCA_FAIL_BIT_MASK 0x1000U |
| #define DW3000_SYS_STATUS_HI_SPIERR_BIT_OFFSET (11U) |
| #define DW3000_SYS_STATUS_HI_SPIERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_SPIERR_BIT_MASK 0x800U |
| #define DW3000_SYS_STATUS_HI_SPI_UNF_BIT_OFFSET (10U) |
| #define DW3000_SYS_STATUS_HI_SPI_UNF_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_SPI_UNF_BIT_MASK 0x400U |
| #define DW3000_SYS_STATUS_HI_SPI_OVF_BIT_OFFSET (9U) |
| #define DW3000_SYS_STATUS_HI_SPI_OVF_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_SPI_OVF_BIT_MASK 0x200U |
| #define DW3000_SYS_STATUS_HI_CMD_ERR_BIT_OFFSET (8U) |
| #define DW3000_SYS_STATUS_HI_CMD_ERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_CMD_ERR_BIT_MASK 0x100U |
| #define DW3000_SYS_STATUS_HI_AES_ERR_BIT_OFFSET (7U) |
| #define DW3000_SYS_STATUS_HI_AES_ERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_AES_ERR_BIT_MASK 0x80U |
| #define DW3000_SYS_STATUS_HI_AES_DONE_BIT_OFFSET (6U) |
| #define DW3000_SYS_STATUS_HI_AES_DONE_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_AES_DONE_BIT_MASK 0x40U |
| #define DW3000_SYS_STATUS_HI_GPIO_IRQ_BIT_OFFSET (5U) |
| #define DW3000_SYS_STATUS_HI_GPIO_IRQ_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_GPIO_IRQ_BIT_MASK 0x20U |
| #define DW3000_SYS_STATUS_HI_VT_DET_BIT_OFFSET (4U) |
| #define DW3000_SYS_STATUS_HI_VT_DET_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_VT_DET_BIT_MASK 0x10U |
| #define DW3000_SYS_STATUS_HI_PGFCAL_ERR_BIT_OFFSET (2U) |
| #define DW3000_SYS_STATUS_HI_PGFCAL_ERR_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_PGFCAL_ERR_BIT_MASK 0x4U |
| #define DW3000_SYS_STATUS_HI_RXPREJ_BIT_OFFSET (1U) |
| #define DW3000_SYS_STATUS_HI_RXPREJ_BIT_LEN (1U) |
| #define DW3000_SYS_STATUS_HI_RXPREJ_BIT_MASK 0x2U |
| |
| /* register RX_FINFO */ |
| #define DW3000_RX_FINFO_ID 0x4c |
| #define DW3000_RX_FINFO_LEN (4U) |
| #define DW3000_RX_FINFO_MASK 0xFFFFFFFFUL |
| #define DW3000_RX_FINFO_RXP2SS_BIT_OFFSET (20U) |
| #define DW3000_RX_FINFO_RXP2SS_BIT_LEN (12U) |
| #define DW3000_RX_FINFO_RXP2SS_BIT_MASK 0xfff00000UL |
| #define DW3000_RX_FINFO_RXPSR_BIT_OFFSET (18U) |
| #define DW3000_RX_FINFO_RXPSR_BIT_LEN (2U) |
| #define DW3000_RX_FINFO_RXPSR_BIT_MASK 0xc0000UL |
| #define DW3000_RX_FINFO_RXPRF_BIT_OFFSET (16U) |
| #define DW3000_RX_FINFO_RXPRF_BIT_LEN (2U) |
| #define DW3000_RX_FINFO_RXPRF_BIT_MASK 0x30000UL |
| #define DW3000_RX_FINFO_RNG_BIT_OFFSET (15U) |
| #define DW3000_RX_FINFO_RNG_BIT_LEN (1U) |
| #define DW3000_RX_FINFO_RNG_BIT_MASK 0x8000U |
| #define DW3000_RX_FINFO_RXBR_BIT_OFFSET (13U) |
| #define DW3000_RX_FINFO_RXBR_BIT_LEN (1U) |
| #define DW3000_RX_FINFO_RXBR_BIT_MASK 0x2000U |
| #define DW3000_RX_FINFO_RXNSPL_BIT_OFFSET (11U) |
| #define DW3000_RX_FINFO_RXNSPL_BIT_LEN (2U) |
| #define DW3000_RX_FINFO_RXNSPL_BIT_MASK 0x1800U |
| #define DW3000_RX_FINFO_RXFLEN_BIT_OFFSET (0U) |
| #define DW3000_RX_FINFO_RXFLEN_BIT_LEN (10U) |
| #define DW3000_RX_FINFO_RXFLEN_BIT_MASK 0x3ffU |
| |
| /* register RX_TIME_0 0x64/060 */ |
| #define DW3000_RX_TIME_RX_STAMP_LEN 5 |
| |
| /* Register ACK_RESP. 0x10008/0x10000 */ |
| #define DW3000_ACK_RESP_LEN (4U) |
| #define DW3000_ACK_RESP_MASK 0xFFFFFFFFUL |
| #define DW3000_ACK_RESP_ACK_TIM_BIT_OFFSET (24U) |
| #define DW3000_ACK_RESP_ACK_TIM_BIT_LEN (8U) |
| #define DW3000_ACK_RESP_ACK_TIM_BIT_MASK 0xff000000UL |
| #define DW3000_ACK_RESP_WAIT4RESP_TIM_BIT_OFFSET (0U) |
| #define DW3000_ACK_RESP_WAIT4RESP_TIM_BIT_LEN (20U) |
| #define DW3000_ACK_RESP_WAIT4RESP_TIM_BIT_MASK 0xfffffUL |
| |
| /* register CHAN_CTRL 0x10014/0x10008 */ |
| #define DW3000_CHAN_CTRL_LEN (4U) |
| #define DW3000_CHAN_CTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_CHAN_CTRL_RX_PCODE_BIT_OFFSET (8U) |
| #define DW3000_CHAN_CTRL_RX_PCODE_BIT_LEN (5U) |
| #define DW3000_CHAN_CTRL_RX_PCODE_BIT_MASK 0x1f00U |
| #define DW3000_CHAN_CTRL_TX_PCODE_BIT_OFFSET (3U) |
| #define DW3000_CHAN_CTRL_TX_PCODE_BIT_LEN (5U) |
| #define DW3000_CHAN_CTRL_TX_PCODE_BIT_MASK 0xf8U |
| #define DW3000_CHAN_CTRL_SFD_TYPE_BIT_OFFSET (1U) |
| #define DW3000_CHAN_CTRL_SFD_TYPE_BIT_LEN (2U) |
| #define DW3000_CHAN_CTRL_SFD_TYPE_BIT_MASK 0x6U |
| #define DW3000_CHAN_CTRL_RF_CHAN_BIT_OFFSET (0U) |
| #define DW3000_CHAN_CTRL_RF_CHAN_BIT_LEN (1U) |
| #define DW3000_CHAN_CTRL_RF_CHAN_BIT_MASK 0x1U |
| |
| /* register SPI_COLLISION 0x10020/0x10014 */ |
| #define DW3000_SPI_COLLISION_STATUS_BIT_MASK 0x1fU |
| |
| /* register RDB_STATUS 0x10024/0x10018 */ |
| #define DW3000_RDB_STATUS_LEN (4U) |
| #define DW3000_RDB_STATUS_MASK 0xFFFFFFFFUL |
| #define DW3000_RDB_STATUS_CP_ERR1_BIT_OFFSET (7U) |
| #define DW3000_RDB_STATUS_CP_ERR1_BIT_LEN (1U) |
| #define DW3000_RDB_STATUS_CP_ERR1_BIT_MASK 0x80U |
| #define DW3000_RDB_STATUS_CIADONE1_BIT_OFFSET (6U) |
| #define DW3000_RDB_STATUS_CIADONE1_BIT_LEN (1U) |
| #define DW3000_RDB_STATUS_CIADONE1_BIT_MASK 0x40U |
| #define DW3000_RDB_STATUS_RXFR1_BIT_OFFSET (5U) |
| #define DW3000_RDB_STATUS_RXFR1_BIT_LEN (1U) |
| #define DW3000_RDB_STATUS_RXFR1_BIT_MASK 0x20U |
| #define DW3000_RDB_STATUS_RXFCG1_BIT_OFFSET (4U) |
| #define DW3000_RDB_STATUS_RXFCG1_BIT_LEN (1U) |
| #define DW3000_RDB_STATUS_RXFCG1_BIT_MASK 0x10U |
| #define DW3000_RDB_STATUS_CP_ERR0_BIT_OFFSET (3U) |
| #define DW3000_RDB_STATUS_CP_ERR0_BIT_LEN (1U) |
| #define DW3000_RDB_STATUS_CP_ERR0_BIT_MASK 0x8U |
| #define DW3000_RDB_STATUS_CIADONE0_BIT_OFFSET (2U) |
| #define DW3000_RDB_STATUS_CIADONE0_BIT_LEN (1U) |
| #define DW3000_RDB_STATUS_CIADONE0_BIT_MASK 0x4U |
| #define DW3000_RDB_STATUS_RXFR0_BIT_OFFSET (1U) |
| #define DW3000_RDB_STATUS_RXFR0_BIT_LEN (1U) |
| #define DW3000_RDB_STATUS_RXFR0_BIT_MASK 0x2U |
| #define DW3000_RDB_STATUS_RXFCG0_BIT_OFFSET (0U) |
| #define DW3000_RDB_STATUS_RXFCG0_BIT_LEN (1U) |
| #define DW3000_RDB_STATUS_RXFCG0_BIT_MASK 0x1U |
| |
| /* register RDB_DIAG_MODE 0x10028/0x10020 */ |
| #define DW3000_RDB_DIAG_MODE_LEN (4U) |
| |
| /* register AES_START */ |
| #define DW3000_AES_START_ID 0x1004c |
| #define DW3000_AES_START_LEN (4U) |
| #define DW3000_AES_START_MASK 0xFFFFFFFFUL |
| #define DW3000_AES_START_AES_START_BIT_OFFSET (0U) |
| #define DW3000_AES_START_AES_START_BIT_LEN (1U) |
| #define DW3000_AES_START_AES_START_BIT_MASK 0x1U |
| |
| /* register AES_STS */ |
| #define DW3000_AES_STS_ID 0x10050 |
| #define DW3000_AES_STS_LEN (4U) |
| #define DW3000_AES_STS_MASK 0xFFFFFFFFUL |
| #define DW3000_AES_STS_RAM_FULL_BIT_OFFSET (5U) |
| #define DW3000_AES_STS_RAM_FULL_BIT_LEN (1U) |
| #define DW3000_AES_STS_RAM_FULL_BIT_MASK 0x20U |
| #define DW3000_AES_STS_RAM_EMPTY_BIT_OFFSET (4U) |
| #define DW3000_AES_STS_RAM_EMPTY_BIT_LEN (1U) |
| #define DW3000_AES_STS_RAM_EMPTY_BIT_MASK 0x10U |
| #define DW3000_AES_STS_MEM_CONF_BIT_OFFSET (3U) |
| #define DW3000_AES_STS_MEM_CONF_BIT_LEN (1U) |
| #define DW3000_AES_STS_MEM_CONF_BIT_MASK 0x8U |
| #define DW3000_AES_STS_TRANS_ERR_BIT_OFFSET (2U) |
| #define DW3000_AES_STS_TRANS_ERR_BIT_LEN (1U) |
| #define DW3000_AES_STS_TRANS_ERR_BIT_MASK 0x4U |
| #define DW3000_AES_STS_AUTH_ERR_BIT_OFFSET (1U) |
| #define DW3000_AES_STS_AUTH_ERR_BIT_LEN (1U) |
| #define DW3000_AES_STS_AUTH_ERR_BIT_MASK 0x2U |
| #define DW3000_AES_STS_AES_DONE_BIT_OFFSET (0U) |
| #define DW3000_AES_STS_AES_DONE_BIT_LEN (1U) |
| #define DW3000_AES_STS_AES_DONE_BIT_MASK 0x1U |
| |
| /* register STS_CFG0/CP_CFG0 */ |
| #define DW3000_CP_CFG0_ID 0x20000 |
| #define DW3000_STS_CFG0_ID DW3000_CP_CFG0_ID |
| #define DW3000_STS_CFG0_LEN (4U) |
| #define DW3000_STS_CFG0_MASK 0xFFFFFFFFUL |
| #define DW3000_STS_CFG0_CPS_LEN_BIT_OFFSET (0U) |
| #define DW3000_STS_CFG0_CPS_LEN_BIT_LEN (8U) |
| #define DW3000_STS_CFG0_CPS_LEN_BIT_MASK 0xffU |
| |
| /* register STS_CTRL */ |
| #define DW3000_STS_CTRL_ID 0x20004 |
| #define DW3000_STS_CTRL_LEN (4U) |
| #define DW3000_STS_CTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_STS_CTRL_RST_LAST_BIT_OFFSET (1U) |
| #define DW3000_STS_CTRL_RST_LAST_BIT_LEN (1U) |
| #define DW3000_STS_CTRL_RST_LAST_BIT_MASK 0x2U |
| #define DW3000_STS_CTRL_LOAD_IV_BIT_OFFSET (0U) |
| #define DW3000_STS_CTRL_LOAD_IV_BIT_LEN (1U) |
| #define DW3000_STS_CTRL_LOAD_IV_BIT_MASK 0x1U |
| |
| /* register STS_STS */ |
| #define DW3000_STS_STS_ID 0x20008 |
| #define DW3000_STS_STS_LEN (4U) |
| #define DW3000_STS_STS_MASK 0xFFFFFFFFUL |
| #define DW3000_STS_STS_ACC_QUAL_BIT_OFFSET (0U) |
| #define DW3000_STS_STS_ACC_QUAL_BIT_LEN (12U) |
| #define DW3000_STS_STS_ACC_QUAL_BIT_MASK 0xfffU |
| |
| /* register STS_KEY0 */ |
| #define DW3000_STS_KEY0_ID 0x2000c |
| #define DW3000_STS_KEY0_LEN (4U) |
| #define DW3000_STS_KEY0_MASK 0xFFFFFFFFUL |
| |
| /* register STS_KEY1 */ |
| #define DW3000_STS_KEY1_ID 0x20010 |
| #define DW3000_STS_KEY1_LEN (4U) |
| #define DW3000_STS_KEY1_MASK 0xFFFFFFFFUL |
| |
| /* register STS_KEY2 */ |
| #define DW3000_STS_KEY2_ID 0x20014 |
| #define DW3000_STS_KEY2_LEN (4U) |
| #define DW3000_STS_KEY2_MASK 0xFFFFFFFFUL |
| |
| /* register STS_KEY3 */ |
| #define DW3000_STS_KEY3_ID 0x20018 |
| #define DW3000_STS_KEY3_LEN (4U) |
| #define DW3000_STS_KEY3_MASK 0xFFFFFFFFUL |
| |
| /* register STS_KEY */ |
| #define DW3000_STS_KEY_ID DW3000_STS_KEY0_ID |
| #define DW3000_STS_KEY_LEN (16U) |
| |
| /* register STS_IV0 */ |
| #define DW3000_STS_IV0_ID 0x2001c |
| #define DW3000_STS_IV0_LEN (4U) |
| #define DW3000_STS_IV0_MASK 0xFFFFFFFFUL |
| |
| /* register STS_IV1 */ |
| #define DW3000_STS_IV1_ID 0x20020 |
| #define DW3000_STS_IV1_LEN (4U) |
| #define DW3000_STS_IV1_MASK 0xFFFFFFFFUL |
| |
| /* register STS_IV2 */ |
| #define DW3000_STS_IV2_ID 0x20024 |
| #define DW3000_STS_IV2_LEN (4U) |
| #define DW3000_STS_IV2_MASK 0xFFFFFFFFUL |
| |
| /* register STS_IV3 */ |
| #define DW3000_STS_IV3_ID 0x20028 |
| #define DW3000_STS_IV3_LEN (4U) |
| #define DW3000_STS_IV3_MASK 0xFFFFFFFFUL |
| |
| /* register STS_IV0-STS_IV3 */ |
| #define DW3000_STS_IV_ID DW3000_STS_IV0_ID |
| #define DW3000_STS_IV_LEN (16U) |
| |
| /* register MRX_CFG */ |
| #define DW3000_MRX_CFG_ID 0x30000 |
| #define DW3000_MRX_CFG_LEN (2U) |
| #define DW3000_MRX_CFG_MASK 0x1FFFUL |
| |
| /* register ADC_THRESH_CFG */ |
| #define DW3000_ADC_THRESH_CFG_ID 0x30010 |
| #define DW3000_ADC_THRESH_CFG_LEN (4U) |
| #define DW3000_ADC_THRESH_CFG_MASK 0xFFFFFFFFUL |
| |
| /* register AGC_CFG */ |
| #define DW3000_AGC_CFG_ID 0x30014 |
| #define DW3000_AGC_CFG_LEN (4U) |
| #define DW3000_AGC_CFG_MASK 0xFFFFFFFFUL |
| |
| /* Register DGC_CFG. */ |
| #define DW3000_DGC_CFG_ID 0x30018 |
| #define DW3000_DGC_CFG_LEN (4U) |
| #define DW3000_DGC_CFG_MASK 0xffffffffUL |
| #define DW3000_DGC_CFG_THR_64_BIT_OFFSET (9U) |
| #define DW3000_DGC_CFG_THR_64_BIT_LEN (6U) |
| #define DW3000_DGC_CFG_THR_64_BIT_MASK 0x7e00U |
| #define DW3000_DGC_CFG_RX_TUNE_EN_BIT_OFFSET (0U) |
| #define DW3000_DGC_CFG_RX_TUNE_EN_BIT_LEN (1U) |
| #define DW3000_DGC_CFG_RX_TUNE_EN_BIT_MASK 0x1U |
| |
| /* register DGC_CFG0 */ |
| #define DW3000_DGC_CFG0_ID 0x3001c |
| |
| /* register DGC_CFG1 */ |
| #define DW3000_DGC_CFG1_ID 0x30020 |
| |
| /* register ADC_THRESH_DBG */ |
| #define DW3000_ADC_THRESH_DBG_ID 0x3004C |
| #define DW3000_ADC_THRESH_DBG_LEN (4U) |
| #define DW3000_ADC_THRESH_DBG_MASK 0xFFFFFFFFUL |
| |
| /* register PGF_CAL_CFG */ |
| #define DW3000_PGF_CAL_CFG_ID 0x4000c |
| #define DW3000_PGF_CAL_CFG_LEN (4U) |
| #define DW3000_PGF_CAL_CFG_MASK 0xFFFFFFFFUL |
| #define DW3000_PGF_CAL_CFG_COMP_DLY_BIT_OFFSET (16U) |
| #define DW3000_PGF_CAL_CFG_COMP_DLY_BIT_LEN (4U) |
| #define DW3000_PGF_CAL_CFG_COMP_DLY_BIT_MASK 0xf0000UL |
| #define DW3000_PGF_CAL_CFG_PGF_GAIN_BIT_OFFSET (8U) |
| #define DW3000_PGF_CAL_CFG_PGF_GAIN_BIT_LEN (5U) |
| #define DW3000_PGF_CAL_CFG_PGF_GAIN_BIT_MASK 0x1f00U |
| #define DW3000_PGF_CAL_CFG_CAL_EN_BIT_OFFSET (4U) |
| #define DW3000_PGF_CAL_CFG_CAL_EN_BIT_LEN (1U) |
| #define DW3000_PGF_CAL_CFG_CAL_EN_BIT_MASK 0x10U |
| #define DW3000_PGF_CAL_CFG_PGF_MODE_BIT_OFFSET (0U) |
| #define DW3000_PGF_CAL_CFG_PGF_MODE_BIT_LEN (2U) |
| #define DW3000_PGF_CAL_CFG_PGF_MODE_BIT_MASK 0x3U |
| |
| /* register RX_CAL_CFG (PGF_CAL_CFG renamed in E0) */ |
| #define DW3000_RX_CAL_CFG_ID DW3000_PGF_CAL_CFG_ID |
| #define DW3000_RX_CAL_CFG_LEN (4U) |
| #define DW3000_RX_CAL_CFG_MASK 0xFFFFFFFFUL |
| #define DW3000_RX_CAL_CFG_COMP_DLY_BIT_OFFSET (16U) |
| #define DW3000_RX_CAL_CFG_COMP_DLY_BIT_LEN (4U) |
| #define DW3000_RX_CAL_CFG_COMP_DLY_BIT_MASK 0xf0000UL |
| #define DW3000_RX_CAL_CFG_CAL_EN_BIT_OFFSET (4U) |
| #define DW3000_RX_CAL_CFG_CAL_EN_BIT_LEN (1U) |
| #define DW3000_RX_CAL_CFG_CAL_EN_BIT_MASK 0x10U |
| #define DW3000_RX_CAL_CFG_CAL_MODE_BIT_OFFSET (0U) |
| #define DW3000_RX_CAL_CFG_CAL_MODE_BIT_LEN (2U) |
| #define DW3000_RX_CAL_CFG_CAL_MODE_BIT_MASK 0x3U |
| |
| /* register PGF_I_CTRL0 */ |
| #define DW3000_PGF_I_CTRL0_ID 0x40010 |
| |
| /* register PGF_I_CTRL1 */ |
| #define DW3000_PGF_I_CTRL1_ID 0x40014 |
| |
| /* register RX_CAL_RESI (PGF_I_CTRL1 renamed in E0) */ |
| #define DW3000_RX_CAL_RESI_ID 0x40014 |
| #define DW3000_RX_CAL_RESI_LEN (4U) |
| #define DW3000_RX_CAL_RESI_MASK 0xFFFFFFFFUL |
| |
| /* register PGF_Q_CTRL1 */ |
| #define DW3000_PGF_Q_CTRL1_ID 0x4001c |
| |
| /* register RX_CAL_RESQ (PGF_Q_CTRL1_ID renamed in E0) */ |
| #define DW3000_RX_CAL_RESQ_ID DW3000_PGF_Q_CTRL1_ID |
| #define DW3000_RX_CAL_RESQ_LEN (4U) |
| #define DW3000_RX_CAL_RESQ_MASK 0xFFFFFFFFUL |
| |
| /* register PGF_CAL_STS */ |
| #define DW3000_PGF_CAL_STS_ID 0x40020 |
| #define DW3000_PGF_CAL_STS_LEN (4U) |
| #define DW3000_PGF_CAL_STS_MASK 0xFFFFFFFFUL |
| #define DW3000_PGF_CAL_STS_CAL_DONE_BIT_OFFSET (0U) |
| #define DW3000_PGF_CAL_STS_CAL_DONE_BIT_LEN (1U) |
| #define DW3000_PGF_CAL_STS_CAL_DONE_BIT_MASK 0x1U |
| |
| /* register RX_CAL_STS (PGF_CAL_STS renamed in E0) */ |
| #define RX_CAL_STS_ID DW3000_PGF_CAL_STS_ID |
| #define RX_CAL_STS_LEN (4U) |
| #define RX_CAL_STS_MASK 0xFFFFFFFFUL |
| |
| /* register GPIO_MODE */ |
| #define DW3000_GPIO_MODE_ID 0x50000 |
| #define DW3000_GPIO_MODE_LEN (4U) |
| #define DW3000_GPIO_MODE_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_MODE_COEX_IO_SWAP_BIT_OFFSET (27U) |
| #define DW3000_GPIO_MODE_COEX_IO_SWAP_BIT_LEN (1U) |
| #define DW3000_GPIO_MODE_COEX_IO_SWAP_BIT_MASK 0x8000000UL |
| #define DW3000_GPIO_MODE_MSGP8_MODE_BIT_OFFSET (24U) |
| #define DW3000_GPIO_MODE_MSGP8_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP8_MODE_BIT_MASK 0x7000000UL |
| #define DW3000_GPIO_MODE_MSGP7_MODE_BIT_OFFSET (21U) |
| #define DW3000_GPIO_MODE_MSGP7_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP7_MODE_BIT_MASK 0xe00000UL |
| #define DW3000_GPIO_MODE_MSGP6_MODE_BIT_OFFSET (18U) |
| #define DW3000_GPIO_MODE_MSGP6_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP6_MODE_BIT_MASK 0x1c0000UL |
| #define DW3000_GPIO_MODE_MSGP5_MODE_BIT_OFFSET (15U) |
| #define DW3000_GPIO_MODE_MSGP5_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP5_MODE_BIT_MASK 0x38000UL |
| #define DW3000_GPIO_MODE_MSGP4_MODE_BIT_OFFSET (12U) |
| #define DW3000_GPIO_MODE_MSGP4_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP4_MODE_BIT_MASK 0x7000U |
| #define DW3000_GPIO_MODE_MSGP3_MODE_BIT_OFFSET (9U) |
| #define DW3000_GPIO_MODE_MSGP3_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP3_MODE_BIT_MASK 0xe00U |
| #define DW3000_GPIO_MODE_MSGP2_MODE_BIT_OFFSET (6U) |
| #define DW3000_GPIO_MODE_MSGP2_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP2_MODE_BIT_MASK 0x1c0U |
| #define DW3000_GPIO_MODE_MSGP1_MODE_BIT_OFFSET (3U) |
| #define DW3000_GPIO_MODE_MSGP1_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP1_MODE_BIT_MASK 0x38U |
| #define DW3000_GPIO_MODE_MSGP0_MODE_BIT_OFFSET (0U) |
| #define DW3000_GPIO_MODE_MSGP0_MODE_BIT_LEN (3U) |
| #define DW3000_GPIO_MODE_MSGP0_MODE_BIT_MASK 0x7U |
| |
| /* register GPIO_DIR */ |
| #define DW3000_GPIO_DIR_ID 0x50008 |
| #define DW3000_GPIO_DIR_LEN (4U) |
| #define DW3000_GPIO_DIR_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_DIR_GDP8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_DIR_GDP8_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP8_BIT_MASK 0x100U |
| #define DW3000_GPIO_DIR_GDP7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_DIR_GDP7_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP7_BIT_MASK 0x80U |
| #define DW3000_GPIO_DIR_GDP6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_DIR_GDP6_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP6_BIT_MASK 0x40U |
| #define DW3000_GPIO_DIR_GDP5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_DIR_GDP5_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP5_BIT_MASK 0x20U |
| #define DW3000_GPIO_DIR_GDP4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_DIR_GDP4_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP4_BIT_MASK 0x10U |
| #define DW3000_GPIO_DIR_GDP3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_DIR_GDP3_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP3_BIT_MASK 0x8U |
| #define DW3000_GPIO_DIR_GDP2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_DIR_GDP2_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP2_BIT_MASK 0x4U |
| #define DW3000_GPIO_DIR_GDP1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_DIR_GDP1_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP1_BIT_MASK 0x2U |
| #define DW3000_GPIO_DIR_GDP0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_DIR_GDP0_BIT_LEN (1U) |
| #define DW3000_GPIO_DIR_GDP0_BIT_MASK 0x1U |
| |
| /* register GPIO_OUT */ |
| #define DW3000_GPIO_OUT_ID 0x5000c |
| #define DW3000_GPIO_OUT_LEN (4U) |
| #define DW3000_GPIO_OUT_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_OUT_GOP8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_OUT_GOP8_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP8_BIT_MASK 0x100U |
| #define DW3000_GPIO_OUT_GOP7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_OUT_GOP7_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP7_BIT_MASK 0x80U |
| #define DW3000_GPIO_OUT_GOP6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_OUT_GOP6_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP6_BIT_MASK 0x40U |
| #define DW3000_GPIO_OUT_GOP5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_OUT_GOP5_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP5_BIT_MASK 0x20U |
| #define DW3000_GPIO_OUT_GOP4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_OUT_GOP4_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP4_BIT_MASK 0x10U |
| #define DW3000_GPIO_OUT_GOP3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_OUT_GOP3_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP3_BIT_MASK 0x8U |
| #define DW3000_GPIO_OUT_GOP2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_OUT_GOP2_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP2_BIT_MASK 0x4U |
| #define DW3000_GPIO_OUT_GOP1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_OUT_GOP1_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP1_BIT_MASK 0x2U |
| #define DW3000_GPIO_OUT_GOP0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_OUT_GOP0_BIT_LEN (1U) |
| #define DW3000_GPIO_OUT_GOP0_BIT_MASK 0x1U |
| |
| /* register GPIO_IRQE - GPIO IRQ enable */ |
| #define DW3000_GPIO_IRQE_ID 0x50010 |
| #define DW3000_GPIO_IRQE_LEN (4U) |
| #define DW3000_GPIO_IRQE_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_IRQE_GIRQE8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_IRQE_GIRQE8_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE8_BIT_MASK 0x100U |
| #define DW3000_GPIO_IRQE_GIRQE7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_IRQE_GIRQE7_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE7_BIT_MASK 0x80U |
| #define DW3000_GPIO_IRQE_GIRQE6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_IRQE_GIRQE6_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE6_BIT_MASK 0x40U |
| #define DW3000_GPIO_IRQE_GIRQE5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_IRQE_GIRQE5_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE5_BIT_MASK 0x20U |
| #define DW3000_GPIO_IRQE_GIRQE4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_IRQE_GIRQE4_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE4_BIT_MASK 0x10U |
| #define DW3000_GPIO_IRQE_GIRQE3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_IRQE_GIRQE3_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE3_BIT_MASK 0x8U |
| #define DW3000_GPIO_IRQE_GIRQE2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_IRQE_GIRQE2_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE2_BIT_MASK 0x4U |
| #define DW3000_GPIO_IRQE_GIRQE1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_IRQE_GIRQE1_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE1_BIT_MASK 0x2U |
| #define DW3000_GPIO_IRQE_GIRQE0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_IRQE_GIRQE0_BIT_LEN (1U) |
| #define DW3000_GPIO_IRQE_GIRQE0_BIT_MASK 0x1U |
| |
| /* register GPIO_ISTS - GPIO IRQ status */ |
| #define DW3000_GPIO_ISTS_ID 0x50014 |
| #define DW3000_GPIO_ISTS_LEN (4U) |
| #define DW3000_GPIO_ISTS_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_ISTS_GISTS8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_ISTS_GISTS8_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS8_BIT_MASK 0x100U |
| #define DW3000_GPIO_ISTS_GISTS7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_ISTS_GISTS7_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS7_BIT_MASK 0x80U |
| #define DW3000_GPIO_ISTS_GISTS6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_ISTS_GISTS6_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS6_BIT_MASK 0x40U |
| #define DW3000_GPIO_ISTS_GISTS5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_ISTS_GISTS5_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS5_BIT_MASK 0x20U |
| #define DW3000_GPIO_ISTS_GISTS4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_ISTS_GISTS4_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS4_BIT_MASK 0x10U |
| #define DW3000_GPIO_ISTS_GISTS3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_ISTS_GISTS3_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS3_BIT_MASK 0x8U |
| #define DW3000_GPIO_ISTS_GISTS2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_ISTS_GISTS2_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS2_BIT_MASK 0x4U |
| #define DW3000_GPIO_ISTS_GISTS1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_ISTS_GISTS1_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS1_BIT_MASK 0x2U |
| #define DW3000_GPIO_ISTS_GISTS0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_ISTS_GISTS0_BIT_LEN (1U) |
| #define DW3000_GPIO_ISTS_GISTS0_BIT_MASK 0x1U |
| |
| /* register GPIO_ISEN */ |
| #define DW3000_GPIO_ISEN_ID 0x50018 |
| #define DW3000_GPIO_ISEN_LEN (4U) |
| #define DW3000_GPIO_ISEN_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_ISEN_GISEN8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_ISEN_GISEN8_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN8_BIT_MASK 0x100U |
| #define DW3000_GPIO_ISEN_GISEN7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_ISEN_GISEN7_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN7_BIT_MASK 0x80U |
| #define DW3000_GPIO_ISEN_GISEN6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_ISEN_GISEN6_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN6_BIT_MASK 0x40U |
| #define DW3000_GPIO_ISEN_GISEN5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_ISEN_GISEN5_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN5_BIT_MASK 0x20U |
| #define DW3000_GPIO_ISEN_GISEN4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_ISEN_GISEN4_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN4_BIT_MASK 0x10U |
| #define DW3000_GPIO_ISEN_GISEN3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_ISEN_GISEN3_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN3_BIT_MASK 0x8U |
| #define DW3000_GPIO_ISEN_GISEN2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_ISEN_GISEN2_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN2_BIT_MASK 0x4U |
| #define DW3000_GPIO_ISEN_GISEN1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_ISEN_GISEN1_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN1_BIT_MASK 0x2U |
| #define DW3000_GPIO_ISEN_GISEN0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_ISEN_GISEN0_BIT_LEN (1U) |
| #define DW3000_GPIO_ISEN_GISEN0_BIT_MASK 0x1U |
| |
| /* register GPIO_IMODE */ |
| #define DW3000_GPIO_IMODE_ID 0x5001c |
| #define DW3000_GPIO_IMODE_LEN (4U) |
| #define DW3000_GPIO_IMODE_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_IMODE_GIMOD8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_IMODE_GIMOD8_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD8_BIT_MASK 0x100U |
| #define DW3000_GPIO_IMODE_GIMOD7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_IMODE_GIMOD7_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD7_BIT_MASK 0x80U |
| #define DW3000_GPIO_IMODE_GIMOD6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_IMODE_GIMOD6_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD6_BIT_MASK 0x40U |
| #define DW3000_GPIO_IMODE_GIMOD5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_IMODE_GIMOD5_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD5_BIT_MASK 0x20U |
| #define DW3000_GPIO_IMODE_GIMOD4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_IMODE_GIMOD4_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD4_BIT_MASK 0x10U |
| #define DW3000_GPIO_IMODE_GIMOD3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_IMODE_GIMOD3_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD3_BIT_MASK 0x8U |
| #define DW3000_GPIO_IMODE_GIMOD2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_IMODE_GIMOD2_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD2_BIT_MASK 0x4U |
| #define DW3000_GPIO_IMODE_GIMOD1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_IMODE_GIMOD1_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD1_BIT_MASK 0x2U |
| #define DW3000_GPIO_IMODE_GIMOD0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_IMODE_GIMOD0_BIT_LEN (1U) |
| #define DW3000_GPIO_IMODE_GIMOD0_BIT_MASK 0x1U |
| |
| /* register GPIO_IBES */ |
| #define DW3000_GPIO_IBES_ID 0x50020 |
| #define DW3000_GPIO_IBES_LEN (4U) |
| #define DW3000_GPIO_IBES_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_IBES_GIBES8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_IBES_GIBES8_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES8_BIT_MASK 0x100U |
| #define DW3000_GPIO_IBES_GIBES7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_IBES_GIBES7_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES7_BIT_MASK 0x80U |
| #define DW3000_GPIO_IBES_GIBES6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_IBES_GIBES6_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES6_BIT_MASK 0x40U |
| #define DW3000_GPIO_IBES_GIBES5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_IBES_GIBES5_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES5_BIT_MASK 0x20U |
| #define DW3000_GPIO_IBES_GIBES4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_IBES_GIBES4_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES4_BIT_MASK 0x10U |
| #define DW3000_GPIO_IBES_GIBES3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_IBES_GIBES3_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES3_BIT_MASK 0x8U |
| #define DW3000_GPIO_IBES_GIBES2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_IBES_GIBES2_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES2_BIT_MASK 0x4U |
| #define DW3000_GPIO_IBES_GIBES1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_IBES_GIBES1_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES1_BIT_MASK 0x2U |
| #define DW3000_GPIO_IBES_GIBES0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_IBES_GIBES0_BIT_LEN (1U) |
| #define DW3000_GPIO_IBES_GIBES0_BIT_MASK 0x1U |
| |
| /* register GPIO_ICLR - GPIO IRQ clear */ |
| #define DW3000_GPIO_ICLR_ID 0x50024 |
| #define DW3000_GPIO_ICLR_LEN (4U) |
| #define DW3000_GPIO_ICLR_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_ICLR_GICLR8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_ICLR_GICLR8_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR8_BIT_MASK 0x100U |
| #define DW3000_GPIO_ICLR_GICLR7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_ICLR_GICLR7_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR7_BIT_MASK 0x80U |
| #define DW3000_GPIO_ICLR_GICLR6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_ICLR_GICLR6_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR6_BIT_MASK 0x40U |
| #define DW3000_GPIO_ICLR_GICLR5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_ICLR_GICLR5_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR5_BIT_MASK 0x20U |
| #define DW3000_GPIO_ICLR_GICLR4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_ICLR_GICLR4_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR4_BIT_MASK 0x10U |
| #define DW3000_GPIO_ICLR_GICLR3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_ICLR_GICLR3_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR3_BIT_MASK 0x8U |
| #define DW3000_GPIO_ICLR_GICLR2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_ICLR_GICLR2_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR2_BIT_MASK 0x4U |
| #define DW3000_GPIO_ICLR_GICLR1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_ICLR_GICLR1_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR1_BIT_MASK 0x2U |
| #define DW3000_GPIO_ICLR_GICLR0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_ICLR_GICLR0_BIT_LEN (1U) |
| #define DW3000_GPIO_ICLR_GICLR0_BIT_MASK 0x1U |
| |
| /* register GPIO_IDBE */ |
| #define DW3000_GPIO_IDBE_ID 0x50028 |
| #define DW3000_GPIO_IDBE_LEN (4U) |
| #define DW3000_GPIO_IDBE_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_IDBE_GIDBE8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_IDBE_GIDBE8_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE8_BIT_MASK 0x100U |
| #define DW3000_GPIO_IDBE_GIDBE7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_IDBE_GIDBE7_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE7_BIT_MASK 0x80U |
| #define DW3000_GPIO_IDBE_GIDBE6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_IDBE_GIDBE6_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE6_BIT_MASK 0x40U |
| #define DW3000_GPIO_IDBE_GIDBE5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_IDBE_GIDBE5_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE5_BIT_MASK 0x20U |
| #define DW3000_GPIO_IDBE_GIDBE4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_IDBE_GIDBE4_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE4_BIT_MASK 0x10U |
| #define DW3000_GPIO_IDBE_GIDBE3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_IDBE_GIDBE3_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE3_BIT_MASK 0x8U |
| #define DW3000_GPIO_IDBE_GIDBE2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_IDBE_GIDBE2_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE2_BIT_MASK 0x4U |
| #define DW3000_GPIO_IDBE_GIDBE1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_IDBE_GIDBE1_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE1_BIT_MASK 0x2U |
| #define DW3000_GPIO_IDBE_GIDBE0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_IDBE_GIDBE0_BIT_LEN (1U) |
| #define DW3000_GPIO_IDBE_GIDBE0_BIT_MASK 0x1U |
| |
| /* register GPIO_RAW */ |
| #define DW3000_GPIO_RAW_ID 0x5002c |
| #define DW3000_GPIO_RAW_LEN (4U) |
| #define DW3000_GPIO_RAW_MASK 0xFFFFFFFFUL |
| #define DW3000_GPIO_RAW_GRAWP8_BIT_OFFSET (8U) |
| #define DW3000_GPIO_RAW_GRAWP8_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP8_BIT_MASK 0x100U |
| #define DW3000_GPIO_RAW_GRAWP7_BIT_OFFSET (7U) |
| #define DW3000_GPIO_RAW_GRAWP7_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP7_BIT_MASK 0x80U |
| #define DW3000_GPIO_RAW_GRAWP6_BIT_OFFSET (6U) |
| #define DW3000_GPIO_RAW_GRAWP6_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP6_BIT_MASK 0x40U |
| #define DW3000_GPIO_RAW_GRAWP5_BIT_OFFSET (5U) |
| #define DW3000_GPIO_RAW_GRAWP5_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP5_BIT_MASK 0x20U |
| #define DW3000_GPIO_RAW_GRAWP4_BIT_OFFSET (4U) |
| #define DW3000_GPIO_RAW_GRAWP4_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP4_BIT_MASK 0x10U |
| #define DW3000_GPIO_RAW_GRAWP3_BIT_OFFSET (3U) |
| #define DW3000_GPIO_RAW_GRAWP3_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP3_BIT_MASK 0x8U |
| #define DW3000_GPIO_RAW_GRAWP2_BIT_OFFSET (2U) |
| #define DW3000_GPIO_RAW_GRAWP2_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP2_BIT_MASK 0x4U |
| #define DW3000_GPIO_RAW_GRAWP1_BIT_OFFSET (1U) |
| #define DW3000_GPIO_RAW_GRAWP1_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP1_BIT_MASK 0x2U |
| #define DW3000_GPIO_RAW_GRAWP0_BIT_OFFSET (0U) |
| #define DW3000_GPIO_RAW_GRAWP0_BIT_LEN (1U) |
| #define DW3000_GPIO_RAW_GRAWP0_BIT_MASK 0x1U |
| |
| /* register DRX_TUNE0 */ |
| #define DW3000_DRX_TUNE0_ID 0x60000 |
| #define DW3000_DRX_TUNE0_LEN (2U) |
| #define DW3000_DRX_TUNE0_MASK 0xFFFFUL |
| #define DW3000_DRX_TUNE0_PRE_PAC_SYM_BIT_OFFSET (0U) |
| #define DW3000_DRX_TUNE0_PRE_PAC_SYM_BIT_LEN (2U) |
| #define DW3000_DRX_TUNE0_PRE_PAC_SYM_BIT_MASK 0x3U |
| |
| /* register DRX_SFDTOC */ |
| #define DW3000_DRX_SFDTOC_ID 0x60002 |
| #define DW3000_DRX_SFDTOC_LEN (2U) |
| #define DW3000_DRX_SFDTOC_BIT_MASK 0xFFFFUL |
| |
| /* register DRX_PRETOC */ |
| #define DW3000_DRX_PRETOC_ID 0x60004 |
| #define DW3000_DRX_PRETOC_LEN (2U) |
| #define DW3000_DRX_PRETOC_BIT_MASK 0xFFFFUL |
| |
| /* register DRX_TUNE3 */ |
| #define DW3000_DRX_TUNE3_ID 0x6000c |
| |
| /* register RF_ENABLE */ |
| #define DW3000_RF_ENABLE_ID 0x70000 |
| #define DW3000_RF_ENABLE_LEN (4U) |
| #define DW3000_RF_ENABLE_MASK 0xFFFFFFFFUL |
| #define DW3000_RF_ENABLE_TX_SW_EN_BIT_OFFSET (25U) |
| #define DW3000_RF_ENABLE_TX_SW_EN_BIT_LEN (1U) |
| #define DW3000_RF_ENABLE_TX_SW_EN_BIT_MASK 0x2000000UL |
| #define DW3000_RF_ENABLE_TX_CH_ALL_EN_BIT_OFFSET (13U) |
| #define DW3000_RF_ENABLE_TX_CH_ALL_EN_BIT_LEN (1U) |
| #define DW3000_RF_ENABLE_TX_CH_ALL_EN_BIT_MASK 0x2000U |
| #define DW3000_RF_ENABLE_TX_EN_BIT_OFFSET (12U) |
| #define DW3000_RF_ENABLE_TX_EN_BIT_LEN (1U) |
| #define DW3000_RF_ENABLE_TX_EN_BIT_MASK 0x1000U |
| #define DW3000_RF_ENABLE_TX_EN_BUF_BIT_OFFSET (11U) |
| #define DW3000_RF_ENABLE_TX_EN_BUF_BIT_LEN (1U) |
| #define DW3000_RF_ENABLE_TX_EN_BUF_BIT_MASK 0x800U |
| #define DW3000_RF_ENABLE_TX_BIAS_EN_BIT_OFFSET (10U) |
| #define DW3000_RF_ENABLE_TX_BIAS_EN_BIT_LEN (1U) |
| #define DW3000_RF_ENABLE_TX_BIAS_EN_BIT_MASK 0x400U |
| |
| /* register RF_CTRL_MASK */ |
| #define DW3000_RF_CTRL_MASK_ID 0x70004 |
| #define DW3000_RF_CTRL_MASK_LEN (4U) |
| #define DW3000_RF_CTRL_MASK_MASK 0xFFFFFFFFUL |
| |
| /* register RX_CTRL_LO */ |
| #define DW3000_RX_CTRL_LO_ID 0x70008 |
| |
| /* register RX_CTRL_HI */ |
| #define DW3000_RX_CTRL_HI_ID 0x70010 |
| |
| /* register RX_SWITCH_CTRL */ |
| #define DW3000_RF_SWITCH_CTRL_ID 0x70014 |
| #define DW3000_RF_SWITCH_CTRL_LEN (4U) |
| #define DW3000_RF_SWITCH_CTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_RF_SWITCH_CTRL_TXRX_SW_OVR_CTRL_BIT_OFFSET (24U) |
| #define DW3000_RF_SWITCH_CTRL_TXRX_SW_OVR_CTRL_BIT_LEN (6U) |
| #define DW3000_RF_SWITCH_CTRL_TXRX_SW_OVR_CTRL_BIT_MASK 0x3F000000 |
| #define DW3000_RF_SWITCH_CTRL_TXRX_SW_OVR_EN_BIT_OFFSET (16U) |
| #define DW3000_RF_SWITCH_CTRL_TXRX_SW_OVR_EN_BIT_LEN (1U) |
| #define DW3000_RF_SWITCH_CTRL_TXRX_SW_OVR_EN_BIT_MASK 0x10000 |
| #define DW3000_RF_SWITCH_CTRL_ANTSWCTRL_BIT_OFFSET (12U) |
| #define DW3000_RF_SWITCH_CTRL_ANTSWCTRL_BIT_LEN (3U) |
| #define DW3000_RF_SWITCH_CTRL_ANTSWCTRL_BIT_MASK 0x7000U |
| #define DW3000_RF_SWITCH_CTRL_ANTSWEN_BIT_OFFSET (8U) |
| #define DW3000_RF_SWITCH_CTRL_ANTSWEN_BIT_LEN (1U) |
| #define DW3000_RF_SWITCH_CTRL_ANTSWEN_BIT_MASK 0x100U |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_TXPORT_BIT_OFFSET (6U) |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_TXPORT_BIT_LEN (1U) |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_TXPORT_BIT_MASK 0x40U |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_RXPORT_BIT_OFFSET (5U) |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_RXPORT_BIT_LEN (1U) |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_RXPORT_BIT_MASK 0x20U |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_MODE_OVR_BIT_OFFSET (4U) |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_MODE_OVR_BIT_LEN (1U) |
| #define DW3000_RF_SWITCH_CTRL_ANT_TXRX_MODE_OVR_BIT_MASK 0x10U |
| |
| /* register TX_CTRL_LO */ |
| #define DW3000_TX_CTRL_LO_ID 0x70018 |
| #define DW3000_TX_CTRL_LO_LEN (4U) |
| #define DW3000_TX_CTRL_LO_MASK 0xFFFFFFFFUL |
| #define DW3000_TX_CTRL_LO_TX_BLEED_CTRL_BIT_OFFSET (25U) |
| #define DW3000_TX_CTRL_LO_TX_BLEED_CTRL_BIT_LEN (3U) |
| #define DW3000_TX_CTRL_LO_TX_BLEED_CTRL_BIT_MASK 0xe000000UL |
| #define DW3000_TX_CTRL_LO_TX_LOBUF_CTRL_BIT_OFFSET (20U) |
| #define DW3000_TX_CTRL_LO_TX_LOBUF_CTRL_BIT_LEN (5U) |
| #define DW3000_TX_CTRL_LO_TX_LOBUF_CTRL_BIT_MASK 0x1f00000UL |
| #define DW3000_TX_CTRL_LO_TX_VBULK_CTRL_BIT_OFFSET (18U) |
| #define DW3000_TX_CTRL_LO_TX_VBULK_CTRL_BIT_LEN (2U) |
| #define DW3000_TX_CTRL_LO_TX_VBULK_CTRL_BIT_MASK 0xc0000UL |
| #define DW3000_TX_CTRL_LO_TX_VCASC_CTRL_BIT_OFFSET (16U) |
| #define DW3000_TX_CTRL_LO_TX_VCASC_CTRL_BIT_LEN (2U) |
| #define DW3000_TX_CTRL_LO_TX_VCASC_CTRL_BIT_MASK 0x30000UL |
| #define DW3000_TX_CTRL_LO_TX_VCM_CTRL_BIT_OFFSET (8U) |
| #define DW3000_TX_CTRL_LO_TX_VCM_CTRL_BIT_LEN (8U) |
| #define DW3000_TX_CTRL_LO_TX_VCM_CTRL_BIT_MASK 0xff00U |
| #define DW3000_TX_CTRL_LO_TX_DELAY_SEL_BIT_OFFSET (6U) |
| #define DW3000_TX_CTRL_LO_TX_DELAY_SEL_BIT_LEN (2U) |
| #define DW3000_TX_CTRL_LO_TX_DELAY_SEL_BIT_MASK 0xc0U |
| #define DW3000_TX_CTRL_LO_TX_CF_CTRL_BIT_OFFSET (1U) |
| #define DW3000_TX_CTRL_LO_TX_CF_CTRL_BIT_LEN (5U) |
| #define DW3000_TX_CTRL_LO_TX_CF_CTRL_BIT_MASK 0x3eU |
| #define DW3000_TX_CTRL_LO_TX_CF_FORCE_BIT_OFFSET (0U) |
| #define DW3000_TX_CTRL_LO_TX_CF_FORCE_BIT_LEN (1U) |
| #define DW3000_TX_CTRL_LO_TX_CF_FORCE_BIT_MASK 0x1U |
| |
| /* register TX_CTRL_HI */ |
| #define DW3000_TX_CTRL_HI_ID 0x7001c |
| #define DW3000_TX_CTRL_HI_LEN (4U) |
| #define DW3000_TX_CTRL_HI_MASK 0xFFFFFFFFUL |
| #define DW3000_TX_CTRL_HI_TX_PULSE_SHAPE_BIT_OFFSET (31U) |
| #define DW3000_TX_CTRL_HI_TX_PULSE_SHAPE_BIT_LEN (1U) |
| #define DW3000_TX_CTRL_HI_TX_PULSE_SHAPE_BIT_MASK 0x80000000UL |
| #define DW3000_TX_CTRL_HI_TX_OFF_SW_STATE_BIT_OFFSET (23U) |
| #define DW3000_TX_CTRL_HI_TX_OFF_SW_STATE_BIT_LEN (6U) |
| #define DW3000_TX_CTRL_HI_TX_OFF_SW_STATE_BIT_MASK 0x1f800000UL |
| #define DW3000_TX_CTRL_HI_TX_OFF_SW_DLY_BIT_OFFSET (21U) |
| #define DW3000_TX_CTRL_HI_TX_OFF_SW_DLY_BIT_LEN (2U) |
| #define DW3000_TX_CTRL_HI_TX_OFF_SW_DLY_BIT_MASK 0x600000UL |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LO_BIT_OFFSET (16U) |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LO_BIT_LEN (4U) |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LO_BIT_MASK 0xf0000UL |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LOAD_P_BIT_OFFSET (12U) |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LOAD_P_BIT_LEN (4U) |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LOAD_P_BIT_MASK 0xf000U |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LOAD_M_BIT_OFFSET (8U) |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LOAD_M_BIT_LEN (4U) |
| #define DW3000_TX_CTRL_HI_TX_CTUNE_LOAD_M_BIT_MASK 0xf00U |
| #define DW3000_TX_CTRL_HI_TX_PG_START_NUM_BIT_OFFSET (6U) |
| #define DW3000_TX_CTRL_HI_TX_PG_START_NUM_BIT_LEN (2U) |
| #define DW3000_TX_CTRL_HI_TX_PG_START_NUM_BIT_MASK 0xc0U |
| #define DW3000_TX_CTRL_HI_TX_PG_DELAY_BIT_OFFSET (0U) |
| #define DW3000_TX_CTRL_HI_TX_PG_DELAY_BIT_LEN (6U) |
| #define DW3000_TX_CTRL_HI_TX_PG_DELAY_BIT_MASK 0x3fU |
| |
| /* register TX_TEST */ |
| #define DW3000_TX_TEST_ID 0x70028 |
| #define DW3000_TX_TEST_LEN (4U) |
| #define DW3000_TX_TEST_MASK 0xFFFFFFFFUL |
| #define DW3000_TX_TEST_PGTEST_EN_CH4_BIT_OFFSET (27U) |
| #define DW3000_TX_TEST_PGTEST_EN_CH4_BIT_LEN (1U) |
| #define DW3000_TX_TEST_PGTEST_EN_CH4_BIT_MASK 0x8000000UL |
| #define DW3000_TX_TEST_PGTEST_EN_CH3_BIT_OFFSET (26U) |
| #define DW3000_TX_TEST_PGTEST_EN_CH3_BIT_LEN (1U) |
| #define DW3000_TX_TEST_PGTEST_EN_CH3_BIT_MASK 0x4000000UL |
| #define DW3000_TX_TEST_PGTEST_EN_CH2_BIT_OFFSET (25U) |
| #define DW3000_TX_TEST_PGTEST_EN_CH2_BIT_LEN (1U) |
| #define DW3000_TX_TEST_PGTEST_EN_CH2_BIT_MASK 0x2000000UL |
| #define DW3000_TX_TEST_PGTEST_EN_CH1_BIT_OFFSET (24U) |
| #define DW3000_TX_TEST_PGTEST_EN_CH1_BIT_LEN (1U) |
| #define DW3000_TX_TEST_PGTEST_EN_CH1_BIT_MASK 0x1000000UL |
| #define DW3000_TX_TEST_XTAL_ANATEST_EN_BIT_OFFSET (18U) |
| #define DW3000_TX_TEST_XTAL_ANATEST_EN_BIT_LEN (1U) |
| #define DW3000_TX_TEST_XTAL_ANATEST_EN_BIT_MASK 0x40000UL |
| #define DW3000_TX_TEST_XTAL_ANATEST_SEL_BIT_OFFSET (15U) |
| #define DW3000_TX_TEST_XTAL_ANATEST_SEL_BIT_LEN (3U) |
| #define DW3000_TX_TEST_XTAL_ANATEST_SEL_BIT_MASK 0x38000UL |
| #define DW3000_TX_TEST_TX_VCM_CTRL_HI_BIT_OFFSET (13U) |
| #define DW3000_TX_TEST_TX_VCM_CTRL_HI_BIT_LEN (2U) |
| #define DW3000_TX_TEST_TX_VCM_CTRL_HI_BIT_MASK 0x6000U |
| #define DW3000_TX_TEST_TX_VCM_CTRL_LO_BIT_OFFSET (9U) |
| #define DW3000_TX_TEST_TX_VCM_CTRL_LO_BIT_LEN (4U) |
| #define DW3000_TX_TEST_TX_VCM_CTRL_LO_BIT_MASK 0x1e00U |
| #define DW3000_TX_TEST_TX_DC_TEST_BIT_OFFSET (5U) |
| #define DW3000_TX_TEST_TX_DC_TEST_BIT_LEN (4U) |
| #define DW3000_TX_TEST_TX_DC_TEST_BIT_MASK 0x1e0U |
| #define DW3000_TX_TEST_TX_DC_TEST_EN_BIT_OFFSET (4U) |
| #define DW3000_TX_TEST_TX_DC_TEST_EN_BIT_LEN (1U) |
| #define DW3000_TX_TEST_TX_DC_TEST_EN_BIT_MASK 0x10U |
| #define DW3000_TX_TEST_TX_ENTEST_CH1_BIT_OFFSET (3U) |
| #define DW3000_TX_TEST_TX_ENTEST_CH1_BIT_LEN (1U) |
| #define DW3000_TX_TEST_TX_ENTEST_CH1_BIT_MASK 0x8U |
| #define DW3000_TX_TEST_TX_ENTEST_CH2_BIT_OFFSET (2U) |
| #define DW3000_TX_TEST_TX_ENTEST_CH2_BIT_LEN (1U) |
| #define DW3000_TX_TEST_TX_ENTEST_CH2_BIT_MASK 0x4U |
| #define DW3000_TX_TEST_TX_ENTEST_CH3_BIT_OFFSET (1U) |
| #define DW3000_TX_TEST_TX_ENTEST_CH3_BIT_LEN (1U) |
| #define DW3000_TX_TEST_TX_ENTEST_CH3_BIT_MASK 0x2U |
| #define DW3000_TX_TEST_TX_ENTEST_CH4_BIT_OFFSET (0U) |
| #define DW3000_TX_TEST_TX_ENTEST_CH4_BIT_LEN (1U) |
| #define DW3000_TX_TEST_TX_ENTEST_CH4_BIT_MASK 0x1U |
| |
| /* register LDO_TUNE_HI */ |
| #define DW3000_LDO_TUNE_HI_ID 0x70044 |
| #define DW3000_LDO_TUNE_HI_LDO_HVAUX_TUNE_BIT_MASK 0xf000U |
| |
| /* register LDO_CTRL */ |
| #define DW3000_LDO_CTRL_ID 0x70048 |
| #define DW3000_LDO_CTRL_LEN (4U) |
| #define DW3000_LDO_CTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_LDO_CTRL_LDO_VDDHVTX_VREF_BIT_OFFSET (27U) |
| #define DW3000_LDO_CTRL_LDO_VDDHVTX_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDHVTX_VREF_BIT_MASK 0x8000000UL |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH9_VREF_BIT_OFFSET (26U) |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH9_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH9_VREF_BIT_MASK 0x4000000UL |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH5_VREF_BIT_OFFSET (25U) |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH5_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH5_VREF_BIT_MASK 0x2000000UL |
| #define DW3000_LDO_CTRL_LDO_VDDIF2_VREF_BIT_OFFSET (24U) |
| #define DW3000_LDO_CTRL_LDO_VDDIF2_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDIF2_VREF_BIT_MASK 0x1000000UL |
| #define DW3000_LDO_CTRL_LDO_VDDIF1_VREF_BIT_OFFSET (23U) |
| #define DW3000_LDO_CTRL_LDO_VDDIF1_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDIF1_VREF_BIT_MASK 0x800000UL |
| #define DW3000_LDO_CTRL_LDO_VDDTX2_VREF_BIT_OFFSET (22U) |
| #define DW3000_LDO_CTRL_LDO_VDDTX2_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDTX2_VREF_BIT_MASK 0x400000UL |
| #define DW3000_LDO_CTRL_LDO_VDDTX1_VREF_BIT_OFFSET (21U) |
| #define DW3000_LDO_CTRL_LDO_VDDTX1_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDTX1_VREF_BIT_MASK 0x200000UL |
| #define DW3000_LDO_CTRL_LDO_VDDPLL_VREF_BIT_OFFSET (20U) |
| #define DW3000_LDO_CTRL_LDO_VDDPLL_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDPLL_VREF_BIT_MASK 0x100000UL |
| #define DW3000_LDO_CTRL_LDO_VDDVCO_VREF_BIT_OFFSET (19U) |
| #define DW3000_LDO_CTRL_LDO_VDDVCO_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDVCO_VREF_BIT_MASK 0x80000UL |
| #define DW3000_LDO_CTRL_LDO_VDDMS3_VREF_BIT_OFFSET (18U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS3_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS3_VREF_BIT_MASK 0x40000UL |
| #define DW3000_LDO_CTRL_LDO_VDDMS2_VREF_BIT_OFFSET (17U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS2_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS2_VREF_BIT_MASK 0x20000UL |
| #define DW3000_LDO_CTRL_LDO_VDDMS1_VREF_BIT_OFFSET (16U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS1_VREF_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS1_VREF_BIT_MASK 0x10000UL |
| #define DW3000_LDO_CTRL_LDO_VDDHVTX_EN_BIT_OFFSET (11U) |
| #define DW3000_LDO_CTRL_LDO_VDDHVTX_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDHVTX_EN_BIT_MASK 0x800U |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH9_EN_BIT_OFFSET (10U) |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH9_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH9_EN_BIT_MASK 0x400U |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH5_EN_BIT_OFFSET (9U) |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH5_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDRFCH5_EN_BIT_MASK 0x200U |
| #define DW3000_LDO_CTRL_LDO_VDDIF2_EN_BIT_OFFSET (8U) |
| #define DW3000_LDO_CTRL_LDO_VDDIF2_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDIF2_EN_BIT_MASK 0x100U |
| #define DW3000_LDO_CTRL_LDO_VDDIF1_EN_BIT_OFFSET (7U) |
| #define DW3000_LDO_CTRL_LDO_VDDIF1_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDIF1_EN_BIT_MASK 0x80U |
| #define DW3000_LDO_CTRL_LDO_VDDTX2_EN_BIT_OFFSET (6U) |
| #define DW3000_LDO_CTRL_LDO_VDDTX2_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDTX2_EN_BIT_MASK 0x40U |
| #define DW3000_LDO_CTRL_LDO_VDDTX1_EN_BIT_OFFSET (5U) |
| #define DW3000_LDO_CTRL_LDO_VDDTX1_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDTX1_EN_BIT_MASK 0x20U |
| #define DW3000_LDO_CTRL_LDO_VDDPLL_EN_BIT_OFFSET (4U) |
| #define DW3000_LDO_CTRL_LDO_VDDPLL_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDPLL_EN_BIT_MASK 0x10U |
| #define DW3000_LDO_CTRL_LDO_VDDVCO_EN_BIT_OFFSET (3U) |
| #define DW3000_LDO_CTRL_LDO_VDDVCO_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDVCO_EN_BIT_MASK 0x8U |
| #define DW3000_LDO_CTRL_LDO_VDDMS3_EN_BIT_OFFSET (2U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS3_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS3_EN_BIT_MASK 0x4U |
| #define DW3000_LDO_CTRL_LDO_VDDMS2_EN_BIT_OFFSET (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS2_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS2_EN_BIT_MASK 0x2U |
| #define DW3000_LDO_CTRL_LDO_VDDMS1_EN_BIT_OFFSET (0U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS1_EN_BIT_LEN (1U) |
| #define DW3000_LDO_CTRL_LDO_VDDMS1_EN_BIT_MASK 0x1U |
| |
| /* register LDO_RLOAD */ |
| #define DW3000_LDO_RLOAD_ID 0x70050 |
| |
| /* register PG_TEST */ |
| #define DW3000_PG_TEST_ID 0x80018 |
| #define DW3000_PG_TEST_LEN (4U) |
| #define DW3000_PG_TEST_MASK 0xFFFFFFFFUL |
| #define DW3000_PG_TEST_TX_TEST_CH4_BIT_OFFSET (12U) |
| #define DW3000_PG_TEST_TX_TEST_CH4_BIT_LEN (4U) |
| #define DW3000_PG_TEST_TX_TEST_CH4_BIT_MASK 0xf000U |
| #define DW3000_PG_TEST_TX_TEST_CH3_BIT_OFFSET (8U) |
| #define DW3000_PG_TEST_TX_TEST_CH3_BIT_LEN (4U) |
| #define DW3000_PG_TEST_TX_TEST_CH3_BIT_MASK 0xf00U |
| #define DW3000_PG_TEST_TX_TEST_CH2_BIT_OFFSET (4U) |
| #define DW3000_PG_TEST_TX_TEST_CH2_BIT_LEN (4U) |
| #define DW3000_PG_TEST_TX_TEST_CH2_BIT_MASK 0xf0U |
| #define DW3000_PG_TEST_TX_TEST_CH1_BIT_OFFSET (0U) |
| #define DW3000_PG_TEST_TX_TEST_CH1_BIT_LEN (4U) |
| #define DW3000_PG_TEST_TX_TEST_CH1_BIT_MASK 0xfU |
| |
| /* register PLL_CAL */ |
| #define DW3000_PLL_CAL_ID 0x90008 |
| #define DW3000_PLL_CAL_LEN (4U) |
| #define DW3000_PLL_CAL_MASK 0xFFFFFFFFUL |
| #define DW3000_PLL_CAL_PLL_CAL_EN_BIT_OFFSET (8U) |
| #define DW3000_PLL_CAL_PLL_CAL_EN_BIT_LEN (1U) |
| #define DW3000_PLL_CAL_PLL_CAL_EN_BIT_MASK 0x100U |
| #define DW3000_PLL_CAL_PLL_USE_OLD_BIT_OFFSET (1U) |
| #define DW3000_PLL_CAL_PLL_USE_OLD_BIT_LEN (1U) |
| #define DW3000_PLL_CAL_PLL_USE_OLD_BIT_MASK 0x2U |
| |
| /* register PLL_CFG */ |
| #define DW3000_PLL_CFG_ID 0x90000 |
| |
| /* register XTAL */ |
| #define DW3000_XTAL_ID 0x90014 |
| |
| /* register AON_DIG_CFG */ |
| #define DW3000_AON_DIG_CFG_ID 0xa0000 |
| #define DW3000_AON_DIG_CFG_LEN (3U) |
| #define DW3000_AON_DIG_CFG_MASK 0xFFFFFFUL |
| #define DW3000_AON_DIG_CFG_ONW_AONDLD_OFFSET (0U) |
| #define DW3000_AON_DIG_CFG_ONW_AONDLD_LEN (1U) |
| #define DW3000_AON_DIG_CFG_ONW_AONDLD_MASK 0x1U |
| #define DW3000_AON_DIG_CFG_ONW_GO2IDLE_OFFSET (8U) |
| #define DW3000_AON_DIG_CFG_ONW_GO2IDLE_LEN (1U) |
| #define DW3000_AON_DIG_CFG_ONW_GO2IDLE_MASK 0x100U |
| |
| /* register AON_CTRL */ |
| #define DW3000_AON_CTRL_ID 0xa0004 |
| #define DW3000_AON_CTRL_LEN (1U) |
| #define DW3000_AON_CTRL_MASK 0xFFUL |
| #define DW3000_AON_CTRL_OVERRIDE_EN_BIT_OFFSET (7U) |
| #define DW3000_AON_CTRL_OVERRIDE_EN_BIT_LEN (1U) |
| #define DW3000_AON_CTRL_OVERRIDE_EN_BIT_MASK 0x80U |
| #define DW3000_AON_CTRL_AON_CLK_EDGE_SEL_BIT_OFFSET (6U) |
| #define DW3000_AON_CTRL_AON_CLK_EDGE_SEL_BIT_LEN (1U) |
| #define DW3000_AON_CTRL_AON_CLK_EDGE_SEL_BIT_MASK 0x40U |
| #define DW3000_AON_CTRL_OVR_WR_CFG_EN_BIT_OFFSET (5U) |
| #define DW3000_AON_CTRL_OVR_WR_CFG_EN_BIT_LEN (1U) |
| #define DW3000_AON_CTRL_OVR_WR_CFG_EN_BIT_MASK 0x20U |
| #define DW3000_AON_CTRL_OVR_WRITE_EN_BIT_OFFSET (4U) |
| #define DW3000_AON_CTRL_OVR_WRITE_EN_BIT_LEN (1U) |
| #define DW3000_AON_CTRL_OVR_WRITE_EN_BIT_MASK 0x10U |
| #define DW3000_AON_CTRL_OVR_READ_EN_BIT_OFFSET (3U) |
| #define DW3000_AON_CTRL_OVR_READ_EN_BIT_LEN (1U) |
| #define DW3000_AON_CTRL_OVR_READ_EN_BIT_MASK 0x8U |
| #define DW3000_AON_CTRL_CONFIG_UPLOAD_BIT_OFFSET (2U) |
| #define DW3000_AON_CTRL_CONFIG_UPLOAD_BIT_LEN (1U) |
| #define DW3000_AON_CTRL_CONFIG_UPLOAD_BIT_MASK 0x4U |
| #define DW3000_AON_CTRL_ARRAY_UPLOAD_BIT_OFFSET (1U) |
| #define DW3000_AON_CTRL_ARRAY_UPLOAD_BIT_LEN (1U) |
| #define DW3000_AON_CTRL_ARRAY_UPLOAD_BIT_MASK 0x2U |
| #define DW3000_AON_CTRL_ARRAY_DOWNLOAD_BIT_OFFSET (0U) |
| #define DW3000_AON_CTRL_ARRAY_DOWNLOAD_BIT_LEN (1U) |
| #define DW3000_AON_CTRL_ARRAY_DOWNLOAD_BIT_MASK 0x1U |
| |
| /* register AON_CFG: AON configuration register */ |
| #define DW3000_AON_CFG_ID 0xa0014 |
| #define DW3000_AON_CFG_LEN (1U) |
| #define DW3000_AON_CFG_MASK 0xFFUL |
| #define DW3000_AON_WAKE_CSN_OFFSET (3U) |
| #define DW3000_AON_WAKE_CSN_LEN (1U) |
| #define DW3000_AON_WAKE_CSN_MASK 0x8U |
| #define DW3000_AON_SLEEP_EN_OFFSET (0U) |
| #define DW3000_AON_SLEEP_EN_LEN (1U) |
| #define DW3000_AON_SLEEP_EN_MASK 0x1U |
| |
| /* register NVM_WDATA */ |
| #define DW3000_NVM_WDATA_ID 0xb0000 |
| |
| /* register NVM_ADDR */ |
| #define DW3000_NVM_ADDR_ID 0xb0004 |
| |
| /* register NVM_CFG */ |
| #define DW3000_NVM_CFG_ID 0xb0008 |
| #define DW3000_NVM_CFG_LEN (4U) |
| #define DW3000_NVM_CFG_MASK 0xFFFFFFFFUL |
| #define DW3000_NVM_CFG_DGC_SEL_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_GEAR_ID_BIT_LEN (2U) |
| #define DW3000_NVM_CFG_GEAR_KICK_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_NVM_PD_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_LDO_KICK_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_DGC_KICK_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_ADDR_INC_BIT_OFFSET (5U) |
| #define DW3000_NVM_CFG_ADDR_INC_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_ADDR_INC_BIT_MASK 0x20U |
| #define DW3000_NVM_CFG_NVM_MODE_SEL_BIT_OFFSET (4U) |
| #define DW3000_NVM_CFG_NVM_MODE_SEL_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_NVM_MODE_SEL_BIT_MASK 0x10U |
| #define DW3000_NVM_CFG_NVM_WRITE_MR_BIT_OFFSET (3U) |
| #define DW3000_NVM_CFG_NVM_WRITE_MR_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_NVM_WRITE_MR_BIT_MASK 0x8U |
| #define DW3000_NVM_CFG_NVM_WRITE_BIT_OFFSET (2U) |
| #define DW3000_NVM_CFG_NVM_WRITE_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_NVM_WRITE_BIT_MASK 0x4U |
| #define DW3000_NVM_CFG_NVM_READ_BIT_OFFSET (1U) |
| #define DW3000_NVM_CFG_NVM_READ_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_NVM_READ_BIT_MASK 0x2U |
| #define DW3000_NVM_CFG_NVM_MAN_CTR_EN_BIT_OFFSET (0U) |
| #define DW3000_NVM_CFG_NVM_MAN_CTR_EN_BIT_LEN (1U) |
| #define DW3000_NVM_CFG_NVM_MAN_CTR_EN_BIT_MASK 0x1U |
| |
| /* register NVM_STATUS */ |
| #define DW3000_NVM_STATUS_ID 0xb000c |
| #define DW3000_NVM_STATUS_NVM_PROG_DONE_BIT_MASK 0x1U |
| |
| /* register NVM_RDATA */ |
| #define DW3000_NVM_RDATA_ID 0xb0010 |
| |
| /* register STS_TOA_LO */ |
| #define DW3000_STS_TOA_LO_ID 0xc0008 |
| #define DW3000_STS_TOA_LO_LEN (4U) |
| #define DW3000_STS_TOA_LO_MASK 0xFFFFFFFFUL |
| #define DW3000_STS_TOA_LO_STS_TOA_BIT_OFFSET (0U) |
| #define DW3000_STS_TOA_LO_STS_TOA_BIT_LEN (32U) |
| #define DW3000_STS_TOA_LO_STS_TOA_BIT_MASK 0xffffffffUL |
| |
| /* register STS_TOA_HI */ |
| #define DW3000_STS_TOA_HI_ID 0xc000c |
| #define DW3000_STS_TOA_HI_LEN (4U) |
| #define DW3000_STS_TOA_HI_MASK 0xFFFFFFFFUL |
| #define DW3000_STS_TOA_HI_STS_TOAST_BIT_OFFSET (23U) |
| #define DW3000_STS_TOA_HI_STS_TOAST_BIT_LEN (9U) |
| #define DW3000_STS_TOA_HI_STS_TOAST_BIT_MASK 0xff800000UL |
| #define DW3000_STS_TOA_HI_STS_POA_BIT_OFFSET (8U) |
| #define DW3000_STS_TOA_HI_STS_POA_BIT_LEN (14U) |
| #define DW3000_STS_TOA_HI_STS_POA_BIT_MASK 0x3fff00UL |
| #define DW3000_STS_TOA_HI_STS_TOA_BIT_OFFSET (0U) |
| #define DW3000_STS_TOA_HI_STS_TOA_BIT_LEN (8U) |
| #define DW3000_STS_TOA_HI_STS_TOA_BIT_MASK 0xffU |
| |
| /* register STS1_TOA_LO */ |
| #define DW3000_STS1_TOA_LO_ID 0xc0010 |
| #define DW3000_STS1_TOA_LO_LEN (4U) |
| #define DW3000_STS1_TOA_LO_MASK 0xFFFFFFFFUL |
| #define DW3000_STS1_TOA_LO_STS1_TOA_BIT_OFFSET (0U) |
| #define DW3000_STS1_TOA_LO_STS1_TOA_BIT_LEN (32U) |
| #define DW3000_STS1_TOA_LO_STS1_TOA_BIT_MASK 0xffffffffUL |
| |
| /* register STS1_TOA_HI */ |
| #define DW3000_STS1_TOA_HI_ID 0xc0014 |
| #define DW3000_STS1_TOA_HI_LEN (4U) |
| #define DW3000_STS1_TOA_HI_MASK 0xFFFFFFFFUL |
| #define DW3000_STS1_TOA_HI_STS1_TOAST_BIT_OFFSET (23U) |
| #define DW3000_STS1_TOA_HI_STS1_TOAST_BIT_LEN (9U) |
| #define DW3000_STS1_TOA_HI_STS1_TOAST_BIT_MASK 0xff800000UL |
| #define DW3000_STS1_TOA_HI_STS1_POA_BIT_OFFSET (8U) |
| #define DW3000_STS1_TOA_HI_STS1_POA_BIT_LEN (14U) |
| #define DW3000_STS1_TOA_HI_STS1_POA_BIT_MASK 0x3fff00UL |
| #define DW3000_STS1_TOA_HI_STS1_TOA_BIT_OFFSET (0U) |
| #define DW3000_STS1_TOA_HI_STS1_TOA_BIT_LEN (8U) |
| #define DW3000_STS1_TOA_HI_STS1_TOA_BIT_MASK 0xffU |
| |
| /* Register CIA_TDOA_1_PDOA */ |
| #define DW3000_CIA_TDOA_1_PDOA_ID 0xc001c |
| #define DW3000_CIA_TDOA_1_PDOA_LEN (4U) |
| #define DW3000_CIA_TDOA_1_PDOA_MASK 0xffffffffUL |
| #define DW3000_CIA_TDOA_1_PDOA_FP_AGREED_BIT_OFFSET (30U) |
| #define DW3000_CIA_TDOA_1_PDOA_FP_AGREED_BIT_LEN (1U) |
| #define DW3000_CIA_TDOA_1_PDOA_FP_AGREED_BIT_MASK 0x40000000UL |
| #define DW3000_CIA_TDOA_1_PDOA_RX_PDOA_BIT_OFFSET (16U) |
| #define DW3000_CIA_TDOA_1_PDOA_RX_PDOA_BIT_LEN (14U) |
| #define DW3000_CIA_TDOA_1_PDOA_RX_PDOA_BIT_MASK 0x3fff0000UL |
| #define DW3000_CIA_TDOA_1_PDOA_RX_TDOA_BIT_OFFSET (0U) |
| #define DW3000_CIA_TDOA_1_PDOA_RX_TDOA_BIT_LEN (9U) |
| #define DW3000_CIA_TDOA_1_PDOA_RX_TDOA_BIT_MASK 0x1ffU |
| |
| /* register IP_DIAG1 */ |
| #define DW3000_IP_DIAG1_ID 0xc002c |
| #define DW3000_IP_DIAG1_LEN (4U) |
| |
| /* register IP_DIAG12 */ |
| #define DW3000_IP_DIAG12_ID 0xc0058 |
| #define DW3000_IP_DIAG12_LEN (4U) |
| |
| /* register CP0_DIAG12 */ |
| #define DW3000_CP0_DIAG1_ID 0xc0060 |
| #define DW3000_CP0_DIAG1_LEN (4U) |
| |
| /* register CP0_DIAG12 */ |
| #define DW3000_CP0_DIAG12_ID 0xd0020 |
| #define DW3000_CP0_DIAG12_LEN (4U) |
| |
| /* register CP1_DIAG1 */ |
| #define DW3000_CP1_DIAG1_ID 0xd003c |
| #define DW3000_CP1_DIAG1_LEN (4U) |
| |
| /* register CP1_DIAG1 */ |
| #define DW3000_CP1_DIAG12_ID 0xd0068 |
| #define DW3000_CP1_DIAG12_LEN (4U) |
| |
| /* register STS_DIAG_0 */ |
| #define DW3000_STS_DIAG_0_ID 0xc005c |
| #define DW3000_STS_DIAG_0_LEN (4U) |
| #define DW3000_STS_DIAG_0_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_1 */ |
| #define DW3000_STS_DIAG_1_ID 0xc0060 |
| #define DW3000_STS_DIAG_1_LEN (4U) |
| #define DW3000_STS_DIAG_1_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_2 */ |
| #define DW3000_STS_DIAG_2_ID 0xc0064 |
| #define DW3000_STS_DIAG_2_LEN (4U) |
| #define DW3000_STS_DIAG_2_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_3 */ |
| #define DW3000_STS_DIAG_3_ID 0xc0068 |
| #define DW3000_STS_DIAG_3_LEN (4U) |
| #define DW3000_STS_DIAG_3_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_4 */ |
| #define DW3000_STS_DIAG_4_ID 0xd0000 |
| #define DW3000_STS_DIAG_4_LEN (4U) |
| #define DW3000_STS_DIAG_4_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_5 */ |
| #define DW3000_STS_DIAG_5_ID 0xd0004 |
| #define DW3000_STS_DIAG_5_LEN (4U) |
| #define DW3000_STS_DIAG_5_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_6 */ |
| #define DW3000_STS_DIAG_6_ID 0xd0008 |
| #define DW3000_STS_DIAG_6_LEN (4U) |
| #define DW3000_STS_DIAG_6_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_7 */ |
| #define DW3000_STS_DIAG_7_ID 0xd000c |
| #define DW3000_STS_DIAG_7_LEN (4U) |
| #define DW3000_STS_DIAG_7_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_8 */ |
| #define DW3000_STS_DIAG_8_ID 0xd0010 |
| #define DW3000_STS_DIAG_8_LEN (4U) |
| #define DW3000_STS_DIAG_8_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_9 */ |
| #define DW3000_STS_DIAG_9_ID 0xd0014 |
| #define DW3000_STS_DIAG_9_LEN (4U) |
| #define DW3000_STS_DIAG_9_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_10 */ |
| #define DW3000_STS_DIAG_10_ID 0xd0018 |
| #define DW3000_STS_DIAG_10_LEN (4U) |
| #define DW3000_STS_DIAG_10_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_11 */ |
| #define DW3000_STS_DIAG_11_ID 0xd001c |
| #define DW3000_STS_DIAG_11_LEN (4U) |
| #define DW3000_STS_DIAG_11_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_12 */ |
| #define DW3000_STS_DIAG_12_ID 0xd0020 |
| #define DW3000_STS_DIAG_12_LEN (4U) |
| #define DW3000_STS_DIAG_12_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_13 */ |
| #define DW3000_STS_DIAG_13_ID 0xd0024 |
| #define DW3000_STS_DIAG_13_LEN (4U) |
| #define DW3000_STS_DIAG_13_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_14 */ |
| #define DW3000_STS_DIAG_14_ID 0xd0028 |
| #define DW3000_STS_DIAG_14_LEN (4U) |
| #define DW3000_STS_DIAG_14_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_15 */ |
| #define DW3000_STS_DIAG_15_ID 0xd002c |
| #define DW3000_STS_DIAG_15_LEN (4U) |
| #define DW3000_STS_DIAG_15_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_16 */ |
| #define DW3000_STS_DIAG_16_ID 0xd0030 |
| #define DW3000_STS_DIAG_16_LEN (4U) |
| #define DW3000_STS_DIAG_16_MASK 0xFFFFFFFFUL |
| |
| /* register STS_DIAG_17 */ |
| #define DW3000_STS_DIAG_17_ID 0xd0034 |
| #define DW3000_STS_DIAG_17_LEN (4U) |
| #define DW3000_STS_DIAG_17_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_0 */ |
| #define DW3000_STS1_DIAG_0_ID 0xd0038 |
| #define DW3000_STS1_DIAG_0_LEN (4U) |
| #define DW3000_STS1_DIAG_0_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_1 */ |
| #define DW3000_STS1_DIAG_1_ID 0xd003c |
| #define DW3000_STS1_DIAG_1_LEN (4U) |
| #define DW3000_STS1_DIAG_1_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_2 */ |
| #define DW3000_STS1_DIAG_2_ID 0xd0040 |
| #define DW3000_STS1_DIAG_2_LEN (4U) |
| #define DW3000_STS1_DIAG_2_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_3 */ |
| #define DW3000_STS1_DIAG_3_ID 0xd0044 |
| #define DW3000_STS1_DIAG_3_LEN (4U) |
| #define DW3000_STS1_DIAG_3_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_4 */ |
| #define DW3000_STS1_DIAG_4_ID 0xd0048 |
| #define DW3000_STS1_DIAG_4_LEN (4U) |
| #define DW3000_STS1_DIAG_4_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_5 */ |
| #define DW3000_STS1_DIAG_5_ID 0xd004c |
| #define DW3000_STS1_DIAG_5_LEN (4U) |
| #define DW3000_STS1_DIAG_5_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_6 */ |
| #define DW3000_STS1_DIAG_6_ID 0xd0050 |
| #define DW3000_STS1_DIAG_6_LEN (4U) |
| #define DW3000_STS1_DIAG_6_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_7 */ |
| #define DW3000_STS1_DIAG_7_ID 0xd0054 |
| #define DW3000_STS1_DIAG_7_LEN (4U) |
| #define DW3000_STS1_DIAG_7_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_8 */ |
| #define DW3000_STS1_DIAG_8_ID 0xd0058 |
| #define DW3000_STS1_DIAG_8_LEN (4U) |
| #define DW3000_STS1_DIAG_8_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_9 */ |
| #define DW3000_STS1_DIAG_9_ID 0xd005c |
| #define DW3000_STS1_DIAG_9_LEN (4U) |
| #define DW3000_STS1_DIAG_9_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_10 */ |
| #define DW3000_STS1_DIAG_10_ID 0xd0060 |
| #define DW3000_STS1_DIAG_10_LEN (4U) |
| #define DW3000_STS1_DIAG_10_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_11 */ |
| #define DW3000_STS1_DIAG_11_ID 0xd0064 |
| #define DW3000_STS1_DIAG_11_LEN (4U) |
| #define DW3000_STS1_DIAG_11_MASK 0xFFFFFFFFUL |
| |
| /* register STS1_DIAG_12 */ |
| #define DW3000_STS1_DIAG_12_ID 0xd0068 |
| #define DW3000_STS1_DIAG_12_LEN (4U) |
| #define DW3000_STS1_DIAG_12_MASK 0xFFFFFFFFUL |
| |
| /* register CIA_CONF */ |
| #define DW3000_CIA_CONF_ID 0xe0000 |
| #define DW3000_CIA_CONF_LEN (4U) |
| |
| /* register RX_ANTENNA_DELAY */ |
| #define DW3000_RX_ANTENNA_DELAY_ID 0xe0000 |
| |
| /* register CY_CONFIG_LO_ID 0xe0012/0xe0014 */ |
| #define DW3000_CY_CONFIG_LO_MANUALLOWERBOUND_BIT_MASK 0x7f0000UL |
| |
| /* register STS_CONFIG_LO (CY_CONFIG_LO_ID renamed in E0) */ |
| #define DW3000_STS_CONFIG_LO_ID DW3000_CY_CONFIG_LO_ID |
| #define DW3000_STS_CONFIG_LO_LEN (4U) |
| #define DW3000_STS_CONFIG_LO_MASK 0xFFFFFFFFUL |
| #define DW3000_STS_CONFIG_LO_STS_MAN_TH_BIT_OFFSET (16U) |
| #define DW3000_STS_CONFIG_LO_STS_MAN_TH_BIT_LEN (7U) |
| #define DW3000_STS_CONFIG_LO_STS_MAN_TH_BIT_MASK 0x7f0000UL |
| #define DW3000_STS_CONFIG_LO_STS_PMULT_BIT_OFFSET (5U) |
| #define DW3000_STS_CONFIG_LO_STS_PMULT_BIT_LEN (2U) |
| #define DW3000_STS_CONFIG_LO_STS_PMULT_BIT_MASK 0x60U |
| #define DW3000_STS_CONFIG_LO_STS_NTM_BIT_OFFSET (0U) |
| #define DW3000_STS_CONFIG_LO_STS_NTM_BIT_LEN (5U) |
| #define DW3000_STS_CONFIG_LO_STS_NTM_BIT_MASK 0x1fU |
| |
| /* register STS_CONFIG_HI (CY_CONFIG_HI_ID renamed in E0) */ |
| #define DW3000_STS_CONFIG_HI_ID DW3000_CY_CONFIG_HI_ID |
| #define DW3000_STS_CONFIG_HI_LEN (4U) |
| #define DW3000_STS_CONFIG_HI_MASK 0xFFFFFFFFUL |
| #define DW3000_STS_CONFIG_HI_STS_PGR_EN_BIT_OFFSET (31U) |
| #define DW3000_STS_CONFIG_HI_STS_PGR_EN_BIT_LEN (1U) |
| #define DW3000_STS_CONFIG_HI_STS_PGR_EN_BIT_MASK 0x80000000UL |
| #define DW3000_STS_CONFIG_HI_STS_SS_EN_BIT_OFFSET (30U) |
| #define DW3000_STS_CONFIG_HI_STS_SS_EN_BIT_LEN (1U) |
| #define DW3000_STS_CONFIG_HI_STS_SS_EN_BIT_MASK 0x40000000UL |
| #define DW3000_STS_CONFIG_HI_STS_CQ_EN_BIT_OFFSET (29U) |
| #define DW3000_STS_CONFIG_HI_STS_CQ_EN_BIT_LEN (1U) |
| #define DW3000_STS_CONFIG_HI_STS_CQ_EN_BIT_MASK 0x20000000UL |
| #define DW3000_STS_CONFIG_HI_FP_AGREED_EN_BIT_OFFSET (28U) |
| #define DW3000_STS_CONFIG_HI_FP_AGREED_EN_BIT_LEN (1U) |
| #define DW3000_STS_CONFIG_HI_FP_AGREED_EN_BIT_MASK 0x10000000UL |
| #define DW3000_STS_CONFIG_HI_RES_B0_BIT_OFFSET (4U) |
| #define DW3000_STS_CONFIG_HI_RES_B0_BIT_LEN (4U) |
| #define DW3000_STS_CONFIG_HI_RES_B0_BIT_MASK 0xf0U |
| |
| /* register TEST_CTRL0 0xf0024/0xf0028 */ |
| #define DW3000_TEST_CTRL0_LEN (4U) |
| #define DW3000_TEST_CTRL0_MASK 0xFFFFFFFFUL |
| #define DW3000_TEST_CTRL0_FIXED_STS_BIT_OFFSET (29U) |
| #define DW3000_TEST_CTRL0_FIXED_STS_BIT_LEN (1U) |
| #define DW3000_TEST_CTRL0_FIXED_STS_BIT_MASK 0x20000000UL |
| #define DW3000_TEST_CTRL0_CIA_RUN_BIT_OFFSET (26U) |
| #define DW3000_TEST_CTRL0_CIA_RUN_BIT_LEN (1U) |
| #define DW3000_TEST_CTRL0_CIA_RUN_BIT_MASK 0x4000000UL |
| #define DW3000_TEST_CTRL0_CIA_WDEN_BIT_OFFSET (24U) |
| #define DW3000_TEST_CTRL0_CIA_WDEN_BIT_LEN (1U) |
| #define DW3000_TEST_CTRL0_CIA_WDEN_BIT_MASK 0x1000000UL |
| #define DW3000_TEST_CTRL0_HIRQ_POL_BIT_OFFSET (21U) |
| #define DW3000_TEST_CTRL0_HIRQ_POL_BIT_LEN (1U) |
| #define DW3000_TEST_CTRL0_HIRQ_POL_BIT_MASK 0x200000UL |
| #define DW3000_TEST_CTRL0_TX_PSTM_BIT_OFFSET (4U) |
| #define DW3000_TEST_CTRL0_TX_PSTM_BIT_LEN (1U) |
| #define DW3000_TEST_CTRL0_TX_PSTM_BIT_MASK 0x10U |
| |
| /* register SYS_STATE_LO */ |
| #define DW3000_SYS_STATE_LO_ID 0xf0030 |
| #define DW3000_SYS_STATE_LO_LEN (4U) |
| #define DW3000_SYS_STATE_LO_MASK 0xFFFFFFFFUL |
| |
| /* register SOFT_RST */ |
| #define DW3000_SOFT_RST_ID 0x110000 |
| #define DW3000_SOFT_RST_LEN (4U) |
| #define DW3000_SOFT_RST_MASK 0xFFFFFFFFUL |
| #define DW3000_SOFT_RST_DIGAON_RST_N_BIT_OFFSET (11U) |
| #define DW3000_SOFT_RST_DIGAON_RST_N_BIT_LEN (1U) |
| #define DW3000_SOFT_RST_DIGAON_RST_N_BIT_MASK 0x800U |
| #define DW3000_SOFT_RST_TIM_RST_N_BIT_OFFSET (10U) |
| #define DW3000_SOFT_RST_TIM_RST_N_BIT_LEN (1U) |
| #define DW3000_SOFT_RST_TIM_RST_N_BIT_MASK 0x400U |
| |
| /* register CLK_CTRL */ |
| #define DW3000_CLK_CTRL_ID 0x110004 |
| #define DW3000_CLK_CTRL_LEN (4U) |
| #define DW3000_CLK_CTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_CLK_CTRL_BIST_CLK_EN_BIT_OFFSET (26U) |
| #define DW3000_CLK_CTRL_BIST_CLK_EN_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_BIST_CLK_EN_BIT_MASK 0x4000000UL |
| #define DW3000_CLK_CTRL_PLL_LOCK_TIMER_EN_BIT_OFFSET (25U) |
| #define DW3000_CLK_CTRL_PLL_LOCK_TIMER_EN_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_PLL_LOCK_TIMER_EN_BIT_MASK 0x2000000UL |
| #define DW3000_CLK_CTRL_SLEEP_MODE_BIT_OFFSET (24U) |
| #define DW3000_CLK_CTRL_SLEEP_MODE_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_SLEEP_MODE_BIT_MASK 0x1000000UL |
| #define DW3000_CLK_CTRL_LP_CLK_EN_BIT_OFFSET (23U) |
| #define DW3000_CLK_CTRL_LP_CLK_EN_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_LP_CLK_EN_BIT_MASK 0x800000UL |
| #define DW3000_CLK_CTRL_RX_BUFF_AUTO_CLK_BIT_OFFSET (21U) |
| #define DW3000_CLK_CTRL_RX_BUFF_AUTO_CLK_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_RX_BUFF_AUTO_CLK_BIT_MASK 0x200000UL |
| #define DW3000_CLK_CTRL_CODE_MEM_AUTO_CLK_BIT_OFFSET (20U) |
| #define DW3000_CLK_CTRL_CODE_MEM_AUTO_CLK_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_CODE_MEM_AUTO_CLK_BIT_MASK 0x100000UL |
| #define DW3000_CLK_CTRL_GPIO_DBNC_RST_N_BIT_OFFSET (19U) |
| #define DW3000_CLK_CTRL_GPIO_DBNC_RST_N_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_GPIO_DBNC_RST_N_BIT_MASK 0x80000UL |
| #define DW3000_CLK_CTRL_GPIO_DBNC_CLK_EN_BIT_OFFSET (18U) |
| #define DW3000_CLK_CTRL_GPIO_DBNC_CLK_EN_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_GPIO_DBNC_CLK_EN_BIT_MASK 0x40000UL |
| #define DW3000_CLK_CTRL_GPIO_CLK_EN_BIT_OFFSET (16U) |
| #define DW3000_CLK_CTRL_GPIO_CLK_EN_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_GPIO_CLK_EN_BIT_MASK 0x10000UL |
| #define DW3000_CLK_CTRL_ACC_MEM_CLK_ON_BIT_OFFSET (15U) |
| #define DW3000_CLK_CTRL_ACC_MEM_CLK_ON_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_ACC_MEM_CLK_ON_BIT_MASK 0x8000U |
| #define DW3000_CLK_CTRL_RSD_CLK_ON_BIT_OFFSET (14U) |
| #define DW3000_CLK_CTRL_RSD_CLK_ON_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_RSD_CLK_ON_BIT_MASK 0x4000U |
| #define DW3000_CLK_CTRL_LOOPBACK_CLK_EN_BIT_OFFSET (13U) |
| #define DW3000_CLK_CTRL_LOOPBACK_CLK_EN_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_LOOPBACK_CLK_EN_BIT_MASK 0x2000U |
| #define DW3000_CLK_CTRL_TX_BUF_CLK_ON_BIT_OFFSET (12U) |
| #define DW3000_CLK_CTRL_TX_BUF_CLK_ON_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_TX_BUF_CLK_ON_BIT_MASK 0x1000U |
| #define DW3000_CLK_CTRL_RX_BUF_CLK_ON_BIT_OFFSET (11U) |
| #define DW3000_CLK_CTRL_RX_BUF_CLK_ON_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_RX_BUF_CLK_ON_BIT_MASK 0x800U |
| #define DW3000_CLK_CTRL_FORCE_NVM_CLK_EN_BIT_OFFSET (9U) |
| #define DW3000_CLK_CTRL_FORCE_NVM_CLK_EN_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_FORCE_NVM_CLK_EN_BIT_MASK 0x200U |
| #define DW3000_CLK_CTRL_FORCE_CIA_CLKS_ON_BIT_OFFSET (8U) |
| #define DW3000_CLK_CTRL_FORCE_CIA_CLKS_ON_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_FORCE_CIA_CLKS_ON_BIT_MASK 0x100U |
| #define DW3000_CLK_CTRL_RX_CLK_GATE_DISABLE_BIT_OFFSET (7U) |
| #define DW3000_CLK_CTRL_RX_CLK_GATE_DISABLE_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_RX_CLK_GATE_DISABLE_BIT_MASK 0x80U |
| #define DW3000_CLK_CTRL_FORCE_ACC_CLK_BIT_OFFSET (6U) |
| #define DW3000_CLK_CTRL_FORCE_ACC_CLK_BIT_LEN (1U) |
| #define DW3000_CLK_CTRL_FORCE_ACC_CLK_BIT_MASK 0x40U |
| #define DW3000_CLK_CTRL_TX_CLK_SEL_BIT_OFFSET (4U) |
| #define DW3000_CLK_CTRL_TX_CLK_SEL_BIT_LEN (2U) |
| #define DW3000_CLK_CTRL_TX_CLK_SEL_BIT_MASK 0x30U |
| #define DW3000_CLK_CTRL_RX_CLK_SEL_BIT_OFFSET (2U) |
| #define DW3000_CLK_CTRL_RX_CLK_SEL_BIT_LEN (2U) |
| #define DW3000_CLK_CTRL_RX_CLK_SEL_BIT_MASK 0xcU |
| #define DW3000_CLK_CTRL_SYS_CLK_SEL_BIT_OFFSET (0U) |
| #define DW3000_CLK_CTRL_SYS_CLK_SEL_BIT_LEN (2U) |
| #define DW3000_CLK_CTRL_SYS_CLK_SEL_BIT_MASK 0x3U |
| |
| /* register SEQ_CTRL */ |
| #define DW3000_SEQ_CTRL_ID 0x110008 |
| #define DW3000_SEQ_CTRL_LEN (4U) |
| #define DW3000_SEQ_CTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_SEQ_CTRL_LP_CLK_DIV_BIT_OFFSET (26U) |
| #define DW3000_SEQ_CTRL_LP_CLK_DIV_BIT_LEN (6U) |
| #define DW3000_SEQ_CTRL_LP_CLK_DIV_BIT_MASK 0xfc000000UL |
| #define DW3000_SEQ_CTRL_FORCE_SYNC_BIT_OFFSET (25U) |
| #define DW3000_SEQ_CTRL_FORCE_SYNC_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_FORCE_SYNC_BIT_MASK 0x2000000UL |
| #define DW3000_SEQ_CTRL_FORCE2RC_BIT_OFFSET (24U) |
| #define DW3000_SEQ_CTRL_FORCE2RC_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_FORCE2RC_BIT_MASK 0x1000000UL |
| #define DW3000_SEQ_CTRL_FORCE2INIT_BIT_OFFSET (23U) |
| #define DW3000_SEQ_CTRL_FORCE2INIT_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_FORCE2INIT_BIT_MASK 0x800000UL |
| #define DW3000_SEQ_CTRL_FORCE2IDLE_BIT_OFFSET (22U) |
| #define DW3000_SEQ_CTRL_FORCE2IDLE_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_FORCE2IDLE_BIT_MASK 0x400000UL |
| #define DW3000_SEQ_CTRL_RX_RST_MODE_BIT_OFFSET (21U) |
| #define DW3000_SEQ_CTRL_RX_RST_MODE_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_RX_RST_MODE_BIT_MASK 0x200000UL |
| #define DW3000_SEQ_CTRL_FORCE_RX_STATE_BIT_OFFSET (20U) |
| #define DW3000_SEQ_CTRL_FORCE_RX_STATE_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_FORCE_RX_STATE_BIT_MASK 0x100000UL |
| #define DW3000_SEQ_CTRL_FORCE_TX_STATE_BIT_OFFSET (19U) |
| #define DW3000_SEQ_CTRL_FORCE_TX_STATE_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_FORCE_TX_STATE_BIT_MASK 0x80000UL |
| #define DW3000_SEQ_CTRL_FORCE_CAL_MODE_BIT_OFFSET (18U) |
| #define DW3000_SEQ_CTRL_FORCE_CAL_MODE_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_FORCE_CAL_MODE_BIT_MASK 0x40000UL |
| #define DW3000_SEQ_CTRL_CIA_SEQ_EN_BIT_OFFSET (17U) |
| #define DW3000_SEQ_CTRL_CIA_SEQ_EN_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_CIA_SEQ_EN_BIT_MASK 0x20000UL |
| #define DW3000_SEQ_CTRL_RX_OFF_EARLY_EN_BIT_OFFSET (16U) |
| #define DW3000_SEQ_CTRL_RX_OFF_EARLY_EN_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_RX_OFF_EARLY_EN_BIT_MASK 0x10000UL |
| #define DW3000_SEQ_CTRL_PLL_SYNC_MODE_BIT_OFFSET (15U) |
| #define DW3000_SEQ_CTRL_PLL_SYNC_MODE_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_PLL_SYNC_MODE_BIT_MASK 0x8000U |
| #define DW3000_SEQ_CTRL_SNOOZE_REPEAT_BIT_OFFSET (14U) |
| #define DW3000_SEQ_CTRL_SNOOZE_REPEAT_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_SNOOZE_REPEAT_BIT_MASK 0x4000U |
| #define DW3000_SEQ_CTRL_SNOOZE_EN_BIT_OFFSET (13U) |
| #define DW3000_SEQ_CTRL_SNOOZE_EN_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_SNOOZE_EN_BIT_MASK 0x2000U |
| #define DW3000_SEQ_CTRL_AUTO_RX2SLP_BIT_OFFSET (12U) |
| #define DW3000_SEQ_CTRL_AUTO_RX2SLP_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AUTO_RX2SLP_BIT_MASK 0x1000U |
| #define DW3000_SEQ_CTRL_AUTO_TX2SLP_BIT_OFFSET (11U) |
| #define DW3000_SEQ_CTRL_AUTO_TX2SLP_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AUTO_TX2SLP_BIT_MASK 0x800U |
| #define DW3000_SEQ_CTRL_AUTO_RX_SEQ_BIT_OFFSET (10U) |
| #define DW3000_SEQ_CTRL_AUTO_RX_SEQ_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AUTO_RX_SEQ_BIT_MASK 0x400U |
| #define DW3000_SEQ_CTRL_AUTO_TX_SEQ_BIT_OFFSET (9U) |
| #define DW3000_SEQ_CTRL_AUTO_TX_SEQ_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AUTO_TX_SEQ_BIT_MASK 0x200U |
| #define DW3000_SEQ_CTRL_AUTO_INIT2IDLE_BIT_OFFSET (8U) |
| #define DW3000_SEQ_CTRL_AUTO_INIT2IDLE_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AUTO_INIT2IDLE_BIT_MASK 0x100U |
| #define DW3000_SEQ_CTRL_AUTOINIT_MODE_BIT_OFFSET (7U) |
| #define DW3000_SEQ_CTRL_AUTOINIT_MODE_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AUTOINIT_MODE_BIT_MASK 0x80U |
| #define DW3000_SEQ_CTRL_AON_CLK_CTRL_BIT_OFFSET (5U) |
| #define DW3000_SEQ_CTRL_AON_CLK_CTRL_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AON_CLK_CTRL_BIT_MASK 0x20U |
| #define DW3000_SEQ_CTRL_RF_CTRL_BIT_OFFSET (3U) |
| #define DW3000_SEQ_CTRL_RF_CTRL_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_RF_CTRL_BIT_MASK 0x8U |
| #define DW3000_SEQ_CTRL_AUTOTX2INIT_BIT_OFFSET (2U) |
| #define DW3000_SEQ_CTRL_AUTOTX2INIT_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AUTOTX2INIT_BIT_MASK 0x4U |
| #define DW3000_SEQ_CTRL_AUTORX2INIT_BIT_OFFSET (1U) |
| #define DW3000_SEQ_CTRL_AUTORX2INIT_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_AUTORX2INIT_BIT_MASK 0x2U |
| #define DW3000_SEQ_CTRL_SYS_TIME_ON_BIT_OFFSET (0U) |
| #define DW3000_SEQ_CTRL_SYS_TIME_ON_BIT_LEN (1U) |
| #define DW3000_SEQ_CTRL_SYS_TIME_ON_BIT_MASK 0x1U |
| |
| /* register PWR_UP_TIMES_LO */ |
| #define DW3000_PWR_UP_TIMES_LO_ID 0x110010 |
| #define DW3000_PWR_UP_TIMES_LO_LEN (4U) |
| #define DW3000_PWR_UP_TIMES_LO_MASK 0xFFFFFFFFUL |
| #define DW3000_PWR_UP_TIMES_TXFINESEQ_BIT_OFFSET (0U) |
| #define DW3000_PWR_UP_TIMES_TXFINESEQ_BIT_LEN (32U) |
| #define DW3000_PWR_UP_TIMES_TXFINESEQ_BIT_MASK 0xFFFFFFFFUL |
| |
| /* register LED_CTRL 0x110016/0x110018 */ |
| #define DW3000_LED_CTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_LED_CTRL_FORCE_TRIGGER_BIT_OFFSET (16U) |
| #define DW3000_LED_CTRL_FORCE_TRIGGER_BIT_LEN (4U) |
| #define DW3000_LED_CTRL_FORCE_TRIGGER_BIT_MASK 0xf0000UL |
| #define DW3000_LED_CTRL_BLINK_EN_BIT_OFFSET (8U) |
| #define DW3000_LED_CTRL_BLINK_EN_BIT_LEN (1U) |
| #define DW3000_LED_CTRL_BLINK_EN_BIT_MASK 0x100U |
| #define DW3000_LED_CTRL_BLINK_CNT_BIT_OFFSET (0U) |
| #define DW3000_LED_CTRL_BLINK_CNT_BIT_LEN (8U) |
| #define DW3000_LED_CTRL_BLINK_CNT_BIT_MASK 0xffU |
| |
| /* register BIAS_CTRL 0x11001f/0x110030 */ |
| #define DW3000_BIAS_CTRL_DIG_BIAS_DAC_ULV_BIT_MASK 0x1fU |
| |
| /* Dual SPI Semaphore events register DSS_STAT */ |
| #define DW3000_DSS_STAT_ID 0x110038 |
| #define DW3000_DSS_STAT_SPI1_AVAIL_BIT_OFFSET (0U) |
| #define DW3000_DSS_STAT_SPI1_AVAIL_BIT_LEN (1U) |
| #define DW3000_DSS_STAT_SPI1_AVAIL_BIT_MASK 0x1U |
| #define DW3000_DSS_STAT_SPI2_AVAIL_BIT_OFFSET (1U) |
| #define DW3000_DSS_STAT_SPI2_AVAIL_BIT_LEN (1U) |
| #define DW3000_DSS_STAT_SPI2_AVAIL_BIT_MASK 0x2U |
| |
| /* register TIMER_CTRL */ |
| #define DW3000_TIMER_CTRL_ID 0x11003c |
| #define DW3000_TIMER_CTRL_LEN (4U) |
| #define DW3000_TIMER_CTRL_MASK 0xFFFFFFFFUL |
| #define DW3000_TIMER_CTRL_TIMER_1_COEXOUT_BIT_OFFSET (22U) |
| #define DW3000_TIMER_CTRL_TIMER_1_COEXOUT_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_1_COEXOUT_BIT_MASK 0x400000UL |
| #define DW3000_TIMER_CTRL_TIMER_1_GPIO_BIT_OFFSET (21U) |
| #define DW3000_TIMER_CTRL_TIMER_1_GPIO_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_1_GPIO_BIT_MASK 0x200000UL |
| #define DW3000_TIMER_CTRL_TIMER_1_TRIG_BIT_OFFSET (20U) |
| #define DW3000_TIMER_CTRL_TIMER_1_TRIG_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_1_TRIG_BIT_MASK 0x100000UL |
| #define DW3000_TIMER_CTRL_TIMER_1_MODE_BIT_OFFSET (19U) |
| #define DW3000_TIMER_CTRL_TIMER_1_MODE_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_1_MODE_BIT_MASK 0x80000UL |
| #define DW3000_TIMER_CTRL_TIMER_1_DIV_BIT_OFFSET (16U) |
| #define DW3000_TIMER_CTRL_TIMER_1_DIV_BIT_LEN (3U) |
| #define DW3000_TIMER_CTRL_TIMER_1_DIV_BIT_MASK 0x70000UL |
| #define DW3000_TIMER_CTRL_TIMER_0_COEXOUT_BIT_OFFSET (14U) |
| #define DW3000_TIMER_CTRL_TIMER_0_COEXOUT_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_0_COEXOUT_BIT_MASK 0x4000U |
| #define DW3000_TIMER_CTRL_TIMER_0_GPIO_BIT_OFFSET (13U) |
| #define DW3000_TIMER_CTRL_TIMER_0_GPIO_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_0_GPIO_BIT_MASK 0x2000U |
| #define DW3000_TIMER_CTRL_TIMER_0_TRIG_BIT_OFFSET (12U) |
| #define DW3000_TIMER_CTRL_TIMER_0_TRIG_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_0_TRIG_BIT_MASK 0x1000U |
| #define DW3000_TIMER_CTRL_TIMER_0_MODE_BIT_OFFSET (11U) |
| #define DW3000_TIMER_CTRL_TIMER_0_MODE_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_0_MODE_BIT_MASK 0x800U |
| #define DW3000_TIMER_CTRL_TIMER_0_DIV_BIT_OFFSET (8U) |
| #define DW3000_TIMER_CTRL_TIMER_0_DIV_BIT_LEN (3U) |
| #define DW3000_TIMER_CTRL_TIMER_0_DIV_BIT_MASK 0x700U |
| #define DW3000_TIMER_CTRL_TIMER_1_RD_COUNT_BIT_OFFSET (3U) |
| #define DW3000_TIMER_CTRL_TIMER_1_RD_COUNT_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_1_RD_COUNT_BIT_MASK 0x8U |
| #define DW3000_TIMER_CTRL_TIMER_0_RD_COUNT_BIT_OFFSET (2U) |
| #define DW3000_TIMER_CTRL_TIMER_0_RD_COUNT_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_0_RD_COUNT_BIT_MASK 0x4U |
| #define DW3000_TIMER_CTRL_TIMER_1_EN_BIT_OFFSET (1U) |
| #define DW3000_TIMER_CTRL_TIMER_1_EN_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_1_EN_BIT_MASK 0x2U |
| #define DW3000_TIMER_CTRL_TIMER_0_EN_BIT_OFFSET (0U) |
| #define DW3000_TIMER_CTRL_TIMER_0_EN_BIT_LEN (1U) |
| #define DW3000_TIMER_CTRL_TIMER_0_EN_BIT_MASK 0x1U |
| |
| /* register TIMER0_CNT_SET */ |
| #define DW3000_TIMER0_CNT_SET_ID 0x110040 |
| #define DW3000_TIMER0_CNT_SET_LEN (4U) |
| #define DW3000_TIMER0_CNT_SET_MASK 0xFFFFFFFFUL |
| #define DW3000_TIMER0_CNT_SET_TIMER_0_SET_BIT_OFFSET (0U) |
| #define DW3000_TIMER0_CNT_SET_TIMER_0_SET_BIT_LEN (22U) |
| #define DW3000_TIMER0_CNT_SET_TIMER_0_SET_BIT_MASK 0x3fffffUL |
| |
| /* register TIMER1_CNT_SET */ |
| #define DW3000_TIMER1_CNT_SET_ID 0x110044 |
| #define DW3000_TIMER1_CNT_SET_LEN (4U) |
| #define DW3000_TIMER1_CNT_SET_MASK 0xFFFFFFFFUL |
| #define DW3000_TIMER1_CNT_SET_TIMER_1_SET_BIT_OFFSET (0U) |
| #define DW3000_TIMER1_CNT_SET_TIMER_1_SET_BIT_LEN (22U) |
| #define DW3000_TIMER1_CNT_SET_TIMER_1_SET_BIT_MASK 0x3fffffUL |
| |
| /* register TIMER_STATUS */ |
| #define DW3000_TIMER_STATUS_ID 0x110048 |
| #define DW3000_TIMER_STATUS_LEN (4U) |
| #define DW3000_TIMER_STATUS_MASK 0xFFFFFFFFUL |
| #define DW3000_TIMER_STATUS_TIMER1_STATUS_BIT_OFFSET (8U) |
| #define DW3000_TIMER_STATUS_TIMER1_STATUS_BIT_LEN (8U) |
| #define DW3000_TIMER_STATUS_TIMER1_STATUS_BIT_MASK 0xff00U |
| #define DW3000_TIMER_STATUS_TIMER0_STATUS_BIT_OFFSET (0U) |
| #define DW3000_TIMER_STATUS_TIMER0_STATUS_BIT_LEN (8U) |
| #define DW3000_TIMER_STATUS_TIMER0_STATUS_BIT_MASK 0xffU |
| |
| /* DW3000 scratch ram */ |
| #define DW3000_SCRATCH_RAM_ID 0x160000 |
| #define DW3000_SCRATCH_RAM_LEN (127U) |
| |
| /* Double buffer diagnostic register set */ |
| #define DW3000_DB_DIAG_SET_1 0x180000 |
| #define DW3000_DB_DIAG_SET_2 0x1800e8 |
| /* Double buffer diagnostic register offsets */ |
| /* RDB_DMODE = 1 || 2 || 4 */ |
| #define DW3000_DB_DIAG_RX_FINFO 0x0 |
| #define DW3000_DB_DIAG_RX_TIME 0x4 |
| #define DW3000_DB_DIAG_CIA_DIAG0 0xc |
| #define DW3000_DB_DIAG_TDOA 0x10 |
| #define DW3000_DB_DIAG_PDOA 0x14 |
| #define DW3000_DB_DIAG_Reserved1 0x18 |
| #define DW3000_DB_DIAG_IP_DIAG_12 0x1c |
| /* RDB_DMODE = 2 || 4 */ |
| #define DW3000_DB_DIAG_IP_TS 0x20 |
| #define DW3000_DB_DIAG_Reserved2 0x24 |
| #define DW3000_DB_DIAG_STS_TS 0x28 |
| #define DW3000_DB_DIAG_Reserved3 0x2c |
| #define DW3000_DB_DIAG_STS1_TS 0x30 |
| #define DW3000_DB_DIAG_Reserved4 0x34 |
| /* RDB_DMODE = 4 */ |
| #define DW3000_DB_DIAG_CIA_DIAG1 0x38 |
| #define DW3000_DB_DIAG_IP_DIAG0 0x3c |
| #define DW3000_DB_DIAG_IP_DIAG1 0x40 |
| #define DW3000_DB_DIAG_IP_DIAG2 0x44 |
| #define DW3000_DB_DIAG_IP_DIAG3 0x48 |
| #define DW3000_DB_DIAG_IP_DIAG4 0x4c |
| #define DW3000_DB_DIAG_IP_DIAG8 0x5c |
| #define DW3000_DB_DIAG_STS_DIAG0 0x6c |
| #define DW3000_DB_DIAG_STS_DIAG1 0x70 |
| #define DW3000_DB_DIAG_STS_DIAG2 0x74 |
| #define DW3000_DB_DIAG_STS_DIAG3 0x78 |
| #define DW3000_DB_DIAG_STS_DIAG4 0x7c |
| #define DW3000_DB_DIAG_STS_DIAG8 0x8c |
| #define DW3000_DB_DIAG_STS_DIAG12 0x9c |
| #define DW3000_DB_DIAG_STS1_DIAG0 0xb4 |
| #define DW3000_DB_DIAG_STS1_DIAG1 0xb8 |
| #define DW3000_DB_DIAG_STS1_DIAG2 0xbc |
| #define DW3000_DB_DIAG_STS1_DIAG3 0xc0 |
| #define DW3000_DB_DIAG_STS1_DIAG4 0xc4 |
| #define DW3000_DB_DIAG_STS1_DIAG8 0xd4 |
| #define DW3000_DB_DIAG_STS1_DIAG12 0xe4 |
| |
| /* Dual SPI Semaphore register SPI_SEM */ |
| #define DW3000_SPI_SEM_ID 0x1a0000 |
| #define DW3000_SPI_SEM_SPI1_RG_BIT_OFFSET (0U) |
| #define DW3000_SPI_SEM_SPI1_RG_BIT_LEN (1U) |
| #define DW3000_SPI_SEM_SPI1_RG_BIT_MASK 0x1U |
| #define DW3000_SPI_SEM_SPI2_RG_BIT_OFFSET (1U) |
| #define DW3000_SPI_SEM_SPI2_RG_BIT_LEN (1U) |
| #define DW3000_SPI_SEM_SPI2_RG_BIT_MASK 0x2U |
| #define DW3000_SPI_SEM_SPI1MAVAIL_BIT_OFFSET (9U) |
| #define DW3000_SPI_SEM_SPI1MAVAIL_BIT_LEN (1U) |
| #define DW3000_SPI_SEM_SPI1MAVAIL_BIT_MASK 0x200U |
| #define DW3000_SPI_SEM_SPI2MAVAIL_BIT_OFFSET (10U) |
| #define DW3000_SPI_SEM_SPI2MAVAIL_BIT_LEN (1U) |
| #define DW3000_SPI_SEM_SPI2MAVAIL_BIT_MASK 0x400U |
| |
| /* register INDIRECT_ADDR_A */ |
| #define DW3000_INDIRECT_ADDR_A_ID 0x1f0004 |
| |
| /* register ADDR_OFFSET_A */ |
| #define DW3000_ADDR_OFFSET_A_ID 0x1f0008 |
| |
| /* register INDIRECT_ADDR_B */ |
| #define DW3000_INDIRECT_ADDR_B_ID 0x1f000c |
| |
| /* register ADDR_OFFSET_B */ |
| #define DW3000_ADDR_OFFSET_B_ID 0x1f0010 |
| |
| #endif /* __DW3000_CORE_REG_H */ |
