arch/arm64/boot/dts/google/zuma-ufs.dtsi

// SPDX-License-Identifier: GPL-2.0-only
//
// Samsung's SoC UFS device tree source
//
// Copyright (C) 2022 Samsung Electronics Co., Ltd.

/ {
	sysreg_ufs: sysreg_ufs@13020000 {
			 compatible = "google,zuma-sysreg-ufs", "syscon";
			 reg = <0x0 0x13020000 0x1000>;
	};

	ufs: ufs@0x13200000 {
		/* ----------------------- */
		/* 1. SYSTEM CONFIGURATION */
		/* ----------------------- */
		compatible ="samsung,exynos-ufs";
		#address-cells = <2>;
		#size-cells = <1>;
		ranges;

		reg =
			<0x0 0x13200000 0x200>,	/* 0: HCI standard */
			<0x0 0x13201100 0x2000>,/* 1: Vendor specified */
			<0x0 0x13280000 0x8000>,/* 2: UNIPRO */
			<0x0 0x132a0000 0xA014>,/* 3: UFS protector */
			<0x0 0x13204000 0x4000>,/* phy */
			<0x0 0x13208000 0x804>;	/* 6: CPORT */
		interrupts = <GIC_SPI IRQ_UFS_EMBD_HSI2 IRQ_TYPE_LEVEL_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
		clocks =
			/* aclk clock */
			<&clock GATE_UFS_EMBD>,
			/* unipro clocks */
			<&clock UFS_EMBD>;

		clock-names =
			/* aclk clocks */
			"GATE_UFS_EMBD",
			/* unipro clocks */
			"UFS_EMBD";

		/* board type for UFS CAL */
		brd-for-cal = /bits/ 8 <1>;  /* (1:SMDK, 16:UNIV) board */

		/* ----------------------- */
		/* 2. UFS COMMON           */
		/* ----------------------- */
		freq-table-hz = <0 0>, <0 0>;

		vcc-supply = <&ufs_fixed_vcc>;
		vcc-fixed-regulator;

		/* ----------------------- */
		/* 3. UFS EXYNOS           */
		/* ----------------------- */

		/* power mode change */
		ufs,pmd-attr-lane = /bits/ 8 <2>;
		ufs,pmd-attr-gear = /bits/ 8 <4>;

		/* DMA coherent callback, should be coupled with 'ufs-sys' */
		dma-coherent;
		/* UFS PHY isolation and TCXO control */
		samsung,pmu-phandle = <&pmu_system_controller>;
		/* UFS IO coherency  */
		samsung,sysreg-phandle = <&sysreg_ufs>;
		/* UFS quirk managing flags */
		fixed-prdt-req_list-ocs;

		/* GSA (KDN) device  */
		gsa-device = <&gsa>;

		/* ----------------------- */
		/* 4. ADDITIONAL NODES     */
		/* ----------------------- */
		ufs-phy-iso {
			offset = <0x3ec0>;
			mask = <0x1>; /* (UFS_BIT(0)) */
			val = <0x1>;
		};

		ufs-iocc {
			offset = <0x710>;
			mask = <0x3>; /* (UFS_BIT(1) | UFS_BIT(0)) */
			val = <0x3>;
		};

		ufs-pm-qos {
			freq-int = <332000>;
		};
	};

	ufs_fixed_vcc: fixedregulator@0 {
		compatible = "regulator-fixed";
		regulator-name = "ufs-vcc";
		gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

};