| // SPDX-License-Identifier: GPL-2.0-only |
| /* |
| * debug device tree source code for gs101 SoC |
| * |
| * Copyright (C) 2020 Samsung Electronics Co., Ltd. |
| * http://www.samsung.com |
| */ |
| |
| #include <dt-bindings/interrupt-controller/gs101.h> |
| #include "gs101-dpm.dtsi" |
| #include "gs101-ppmu.dtsi" |
| / { |
| dss: dss { |
| compatible = "google,debug-snapshot"; |
| freq_names = "LIT", "MID", "BIG", "INT", "MIF", "ISP", |
| "DISP", "INTCAM", "TPU", "TNR", "MFC", |
| "BO"; |
| memory-region = <&header>, <&log_kevents>, <&log_bcm>, <&log_s2d>, |
| <&log_arrdumpreset>, <&log_arrdumppanic>, |
| <&log_slcdump>, <&log_preslcdump>, |
| <&log_itmon>; |
| panic-action = <GO_DEFAULT_ID>; |
| }; |
| |
| hardlockup-debugger { |
| compatible = "google,hardlockup-debug"; |
| use_multistage_wdt_irq = <798>; |
| }; |
| |
| hardlockup-watchdog { |
| compatible = "google,hardlockup-watchdog"; |
| sampling_time = <4>; |
| opportunity_count = <3>; |
| panic = <1>; |
| }; |
| |
| dss-built { |
| compatible = "google,debug-snapshot-built"; |
| memory-region = <&header>; |
| }; |
| |
| dss-qdump { |
| compatible = "google,debug-snapshot-qdump"; |
| }; |
| |
| dss-sfrdump { |
| compatible = "google,debug-snapshot-sfrdump"; |
| /* |
| * -----------<< Example >>------------------- |
| * dump-info { |
| * #address-cells = <1>; |
| * #size-cells = <1>; |
| * |
| * gic-setenable { |
| * reg = <0x11f01100 0x100>; |
| * }; |
| * gic-setpend { |
| * reg = <0x11f01200 0x100>; |
| * }; |
| * gic-setactive { |
| * reg = <0x11f01300 0x100>; |
| * }; |
| *}; |
| */ |
| }; |
| |
| dss-debug-kinfo { |
| compatible = "google,debug-snapshot-debug-kinfo"; |
| memory-region = <&debug_kinfo_reserved>; |
| }; |
| |
| exynos-debug-test { |
| compatible = "google,exynos-debug-test"; |
| ps_hold_control_offset = <0x3e9c>; |
| nr_cpu = <0x8>; |
| nr_little_cpu = <0x4>; |
| nr_mid_cpu = <0x2>; |
| nr_big_cpu = <0x2>; |
| little_cpu_start = <0x0>; |
| mid_cpu_start = <0x4>; |
| big_cpu_start = <0x6>; |
| }; |
| |
| keydebug { |
| compatible = "keydebug"; |
| key_down_delay = <6000>; |
| keys_down = <116>; |
| dbg_fn_delay = <2000>; |
| }; |
| |
| debug-kinfo { |
| compatible = "google,debug-kinfo"; |
| memory-region = <&debug_kinfo_reserved>; |
| }; |
| |
| boot-metrics { |
| compatible = "google,boot-metrics"; |
| |
| reg = <0x0 0x02038000 0x00001000>; |
| reg-names = "ns_sram_base"; |
| offset = <0x880>; |
| }; |
| |
| pixel-suspend-diag { |
| compatible = "google,pixel-suspend-diag"; |
| }; |
| |
| gs101-itmon { |
| compatible = "google,gs101-itmon"; |
| interrupts = |
| <GIC_SPI IRQ_TREX_D_BUS0_debugInterrupt_BUS0 |
| IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI IRQ_TREX_D0_BUS1_debugInterrupt_BUS1 |
| IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI IRQ_TREX_D_BUS2_debugInterrupt_BUS2 |
| IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI IRQ_TREX_D_CORE_debugInterrupt_CORE |
| IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI IRQ_TREX_P_CORE_debugInterrupt_CORE |
| IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI IRQ_TREX_P_BUS0_debugInterrupt_BUS0 |
| IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI IRQ_TREX_P_BUS1_debugInterrupt_BUS1 |
| IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI IRQ_TREX_P_BUS2_debugInterrupt_BUS2 |
| IRQ_TYPE_LEVEL_HIGH>; |
| panic_count = <2>; |
| err_fatal = <GO_S2D_ID>; |
| err_drex_tmout = <GO_S2D_ID>; |
| err_ip = <GO_DEFAULT_ID>; |
| err_cpu = <GO_S2D_ID>; |
| err_unhandled = <GO_PANIC_ID>; |
| }; |
| |
| coresight@25000000 { |
| compatible = "google,exynos-coresight"; |
| dbg_base = <0x25810000>, <0x25910000>, <0x25a10000>, <0x25b10000>, |
| <0x25c10000>, <0x25d10000>, <0x25e10000>, <0x25f10000>; |
| cti_base = <0x25820000>, <0x25920000>, <0x25a20000>, <0x25b20000>, |
| <0x25c20000>, <0x25d20000>, <0x25e20000>, <0x25f20000>; |
| pmu_base = <0x25830000>, <0x25930000>, <0x25a30000>, <0x25b30000>, |
| <0x25c30000>, <0x25d30000>, <0x25e30000>, <0x25f30000>; |
| gpr_base = <0x25001000>; |
| dbgack-mask = <0xff00000>; |
| halt = <1>; |
| retention = <1>; |
| }; |
| |
| ecc-handler { |
| compatible = "google,exynos-ecc-handler"; |
| interrupts = <GIC_SPI IRQ_CPUCL0_ERRIRQ_0_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* DSU */ |
| <GIC_SPI IRQ_CPUCL0_ERRIRQ_1_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE0 */ |
| <GIC_SPI IRQ_CPUCL0_ERRIRQ_2_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE1 */ |
| <GIC_SPI IRQ_CPUCL0_ERRIRQ_3_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE2 */ |
| <GIC_SPI IRQ_CPUCL0_ERRIRQ_4_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE3 */ |
| <GIC_SPI IRQ_CPUCL0_ERRIRQ_5_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE4 */ |
| <GIC_SPI IRQ_CPUCL0_ERRIRQ_6_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE5 */ |
| <GIC_SPI IRQ_CPUCL0_ERRIRQ_7_CPUCL0 IRQ_TYPE_LEVEL_HIGH>, /* CORE6 */ |
| <GIC_SPI IRQ_CPUCL0_ERRIRQ_8_CPUCL0 IRQ_TYPE_LEVEL_HIGH>; /* CORE7 */ |
| |
| interrupt-names ="DSU, L3 DATA or TAG or Snoop filter RAM", |
| "CORE0, L1,L2 DATA or TAG RAM", |
| "CORE1, L1,L2 DATA or TAG RAM", |
| "CORE2, L1,L2 DATA or TAG RAM", |
| "CORE3, L1,L2 DATA or TAG RAM", |
| "CORE4, L1,L2 DATA or TAG RAM", |
| "CORE5, L1,L2 DATA or TAG RAM", |
| "CORE6, L1,L2 DATA or TAG RAM", |
| "CORE7, L1,L2 DATA or TAG RAM"; |
| }; |
| |
| exynos-etm { |
| compatible = "google,exynos-etm"; |
| cs_base = <0x25000000>; |
| boot-start = <0>; |
| funnel-num = <3>; |
| etf-num = <2>; |
| trex-num = <4>; |
| /* funnel-port = <(funnel num) (port num)>; */ |
| etm0 { |
| device_type = "etm"; |
| offset = <0x840000>; |
| funnel-port = <0 0>; |
| }; |
| etm1 { |
| device_type = "etm"; |
| offset = <0x940000>; |
| funnel-port = <0 1>; |
| }; |
| etm2 { |
| device_type = "etm"; |
| offset = <0xa40000>; |
| funnel-port = <1 0>; |
| }; |
| etm3 { |
| device_type = "etm"; |
| offset = <0xb40000>; |
| funnel-port = <1 1>; |
| }; |
| etm4 { |
| device_type = "etm"; |
| offset = <0xc40000>; |
| funnel-port = <1 2>; |
| }; |
| etm5 { |
| device_type = "etm"; |
| offset = <0xd40000>; |
| funnel-port = <1 3>; |
| }; |
| etm6 { |
| device_type = "etm"; |
| offset = <0xe40000>; |
| funnel-port = <0 2>; |
| }; |
| etm7 { |
| device_type = "etm"; |
| offset = <0xf40000>; |
| funnel-port = <0 3>; |
| }; |
| etf0@4000 { |
| device_type = "etf"; |
| offset = <0x4000>; |
| funnel-port = <2 0>; |
| }; |
| etf1@5000 { |
| device_type = "etf"; |
| offset = <0x5000>; |
| funnel-port = <2 1>; |
| }; |
| funnel0@7000 { |
| device_type = "funnel"; |
| offset = <0x7000>; |
| }; |
| funnel1@8000 { |
| device_type = "funnel"; |
| offset = <0x8000>; |
| }; |
| funnel2@9000 { |
| device_type = "funnel"; |
| offset = <0x9000>; |
| }; |
| etr@A000 { |
| device_type = "etr"; |
| sfr_base = <0x2500c000 0x100>; |
| qch-offset = <0x2c>; |
| offset = <0xA000>; |
| buf-size = <0x100000>; |
| }; |
| bdu@10000 { |
| device_type = "bdu"; |
| offset = <0x10000>; |
| funnel-port = <1 5>; |
| }; |
| bdu_etf@11000 { |
| device_type = "bdu_etf"; |
| offset = <0x11000>; |
| }; |
| trex0 { |
| device_type = "trex"; |
| mux_ctrl = <0x66>; |
| dbg_trace_addr = <0x1ea83010>; |
| dbg_trace_val = <5>; |
| }; |
| trex1 { |
| device_type = "trex"; |
| mux_ctrl = <0x77>; |
| dbg_trace_addr = <0x1f603010>; |
| dbg_trace_val = <26>; |
| }; |
| trex2 { |
| device_type = "trex"; |
| mux_ctrl = <0x88>; |
| dbg_trace_addr = <0x204e3010>; |
| dbg_trace_val = <8>; |
| }; |
| trex3 { |
| device_type = "trex"; |
| mux_ctrl = <0x55>; |
| dbg_trace_addr = <0x1e503010>; |
| dbg_trace_val = <8>; |
| }; |
| }; |
| |
| etm0: etm@25840000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0 0x25840000 0x1000>; |
| cpu = <&cpu0>; |
| |
| coresight-name = "coresight-etm0"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| arm,coresight-loses-context-with-cpu; |
| |
| out-ports { |
| port { |
| etm0_out_port: endpoint { |
| remote-endpoint = <&funnel0_in_port0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm1: etm@25940000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0 0x25940000 0x1000>; |
| cpu = <&cpu1>; |
| |
| coresight-name = "coresight-etm1"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| arm,coresight-loses-context-with-cpu; |
| |
| out-ports { |
| port { |
| etm1_out_port: endpoint { |
| remote-endpoint = <&funnel0_in_port1>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm2: etm@25a40000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0 0x25a40000 0x1000>; |
| cpu = <&cpu2>; |
| |
| coresight-name = "coresight-etm2"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| arm,coresight-loses-context-with-cpu; |
| |
| out-ports { |
| port { |
| etm2_out_port: endpoint { |
| remote-endpoint = <&funnel1_in_port0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm3: etm@25b40000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0 0x25b40000 0x1000>; |
| cpu = <&cpu3>; |
| |
| coresight-name = "coresight-etm3"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| arm,coresight-loses-context-with-cpu; |
| |
| out-ports { |
| port { |
| etm3_out_port: endpoint { |
| remote-endpoint = <&funnel1_in_port1>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm4: etm@25c40000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0 0x25c40000 0x1000>; |
| cpu = <&cpu4>; |
| |
| coresight-name = "coresight-etm4"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| arm,coresight-loses-context-with-cpu; |
| |
| out-ports { |
| port { |
| etm4_out_port: endpoint { |
| remote-endpoint = <&funnel1_in_port2>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm5: etm@25d40000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0 0x25d40000 0x1000>; |
| cpu = <&cpu5>; |
| |
| coresight-name = "coresight-etm5"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| arm,coresight-loses-context-with-cpu; |
| |
| out-ports { |
| port { |
| etm5_out_port: endpoint { |
| remote-endpoint = <&funnel1_in_port3>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm6: etm@25e40000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0 0x25e40000 0x1000>; |
| cpu = <&cpu6>; |
| |
| coresight-name = "coresight-etm6"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| arm,coresight-loses-context-with-cpu; |
| |
| out-ports { |
| port { |
| etm6_out_port: endpoint { |
| remote-endpoint = <&funnel0_in_port2>; |
| }; |
| }; |
| }; |
| }; |
| |
| etm7: etm@25f40000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb95d>; |
| |
| reg = <0 0x25f40000 0x1000>; |
| cpu = <&cpu7>; |
| |
| coresight-name = "coresight-etm7"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| arm,coresight-loses-context-with-cpu; |
| |
| out-ports { |
| port { |
| etm7_out_port: endpoint { |
| remote-endpoint = <&funnel0_in_port3>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel0: funnel@25007000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb908>; |
| |
| reg = <0 0x25007000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel0"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel0_out_port: endpoint { |
| remote-endpoint = <&etf0_in_port>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel0_in_port0: endpoint { |
| remote-endpoint = <&etm0_out_port>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| funnel0_in_port1: endpoint { |
| remote-endpoint = <&etm1_out_port>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| funnel0_in_port2: endpoint { |
| remote-endpoint = <&etm6_out_port>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| funnel0_in_port3: endpoint { |
| remote-endpoint = <&etm7_out_port>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel1: funnel@25008000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb908>; |
| |
| reg = <0 0x25008000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel1"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel1_out_port: endpoint { |
| remote-endpoint = <&etf1_in_port>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel1_in_port0: endpoint { |
| remote-endpoint = <&etm2_out_port>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| funnel1_in_port1: endpoint { |
| remote-endpoint = <&etm3_out_port>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| funnel1_in_port2: endpoint { |
| remote-endpoint = <&etm4_out_port>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| funnel1_in_port3: endpoint { |
| remote-endpoint = <&etm5_out_port>; |
| }; |
| }; |
| }; |
| }; |
| |
| funnel2: funnel@25009000 { |
| compatible = "arm,primecell"; |
| arm,primecell-periphid = <0x000bb908>; |
| |
| reg = <0 0x25009000 0x1000>; |
| reg-names = "funnel-base"; |
| |
| coresight-name = "coresight-funnel2"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| out-ports { |
| port { |
| funnel2_out_port: endpoint { |
| remote-endpoint = <&etr_in_port>; |
| }; |
| }; |
| }; |
| |
| in-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| funnel2_in_port0: endpoint { |
| remote-endpoint = <&etf0_out_port>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| funnel2_in_port1: endpoint { |
| remote-endpoint = <&etf1_out_port>; |
| }; |
| }; |
| }; |
| }; |
| |
| etf0: etf@25004000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| arm,primecell-periphid = <0x001bb961>; |
| reg = <0 0x25004000 0x1000>; |
| |
| coresight-name = "coresight-etf0"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| in-ports { |
| port { |
| etf0_in_port: endpoint { |
| remote-endpoint = <&funnel0_out_port>; |
| }; |
| }; |
| }; |
| |
| out-ports { |
| port { |
| etf0_out_port: endpoint { |
| remote-endpoint = <&funnel2_in_port0>; |
| }; |
| }; |
| }; |
| }; |
| |
| etf1: etf@25005000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| arm,primecell-periphid = <0x001bb961>; |
| reg = <0 0x25005000 0x1000>; |
| |
| coresight-name = "coresight-etf1"; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| in-ports { |
| port { |
| etf1_in_port: endpoint { |
| remote-endpoint = <&funnel1_out_port>; |
| }; |
| }; |
| }; |
| |
| out-ports { |
| port { |
| etf1_out_port: endpoint { |
| remote-endpoint = <&funnel2_in_port1>; |
| }; |
| }; |
| }; |
| }; |
| |
| etr: etr@2500a000 { |
| compatible = "arm,coresight-tmc", "arm,primecell"; |
| arm,primecell-periphid = <0x001bb961>; |
| reg = <0 0x2500a000 0x1000>; |
| |
| coresight-name = "coresight-etr"; |
| arm,scatter-gather; |
| |
| clocks = <&clock ATCLK>; |
| clock-names = "apb_pclk"; |
| |
| in-ports { |
| port { |
| etr_in_port: endpoint { |
| remote-endpoint = <&funnel2_out_port>; |
| }; |
| }; |
| }; |
| }; |
| |
| etr-miu@11090000 { |
| compatible = "google,gs101-etr-miu"; |
| reg = <0x0 0x11090000 0x100>; |
| tmc_buf_addr = <0x00000010 0x00000000>; |
| tmc_buf_size = <0x80000000>; |
| }; |
| |
| exynos-adv_tracer { |
| compatible = "google,exynos-adv-tracer"; |
| reg = <0x0 0x176c0000 0x1000>; |
| reg-names = "mailbox"; |
| interrupts = <GIC_SPI IRQ_MAILBOX_DBGCORE2AP_ALIVE IRQ_TYPE_LEVEL_HIGH>; |
| pmu-dbgcore-config = <0x3080>; |
| pmu-dbgcore-status = <0x3084>; |
| intr-bitoffset = <0>; |
| status = "ok"; |
| }; |
| |
| exynos_adv_tracer_s2d { |
| compatible = "google,exynos-adv-tracer-s2d"; |
| plugin-len = <3>; |
| plugin-name = "S2D"; |
| pmu-burnin-ctrl = <0x3cd0>; |
| sel-scanmode-bit = <25>; |
| dbgsel-sw-bit = <4>; |
| blk-list = "AOC", "AOCCORE", "BO", "BOCORE", "BUS0", "BUS1", |
| "BUS2", "CMU", "CORE", "CPUCL0", "CLUSTER0", "CSIS", |
| "DISP", "DNS", "DPU", "EH", "G2D", "G3AA", |
| "G3D", "GPU", "GDC", "GSA", "HSI0", "HSI1", |
| "HSI2", "IPP", "ITP", "MCSC", "MFC", "MIF1", |
| "MIF2", "MIF3", "PDP", "PERIC0", "PERIC1", "TNR", |
| "TPU", "TPUCORE", "SLC0", "SLC1", "SLC2", "SLC3"; |
| status = "ok"; |
| }; |
| |
| exynos-ehld { |
| compatible = "google,exynos-ehld"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| cs_base = <0x25000000>; |
| status = "ok"; |
| |
| dbgc { |
| /* IPC */ |
| plugin-len = <4>; |
| plugin-name = "ELD"; |
| support = <1>; |
| interval = <1000>; |
| warn-count = <4>; |
| use-tick-timer = <0>; |
| }; |
| |
| cpu0 { |
| dbg-offset = <0x810000>; |
| }; |
| cpu1 { |
| dbg-offset = <0x910000>; |
| }; |
| cpu2 { |
| dbg-offset = <0xa10000>; |
| }; |
| cpu3 { |
| dbg-offset = <0xb10000>; |
| }; |
| cpu4 { |
| dbg-offset = <0xc10000>; |
| }; |
| cpu5 { |
| dbg-offset = <0xd10000>; |
| }; |
| cpu6 { |
| dbg-offset = <0xe10000>; |
| }; |
| cpu7 { |
| dbg-offset = <0xf10000>; |
| }; |
| }; |
| |
| sjtag_ap { |
| compatible = "google,sjtag"; |
| ms-per-tick = <5590>; |
| ipc-timeout-ms = <450>; |
| pubkey = /bits/ 8 <0xef 0x48 0x97 0xa2 0x57 0x8b 0xd1 0x2d 0x3a 0x18 0x7b 0x68 |
| 0x9f 0xd2 0xe6 0xf8 0x3c 0xf6 0xca 0xa5 0x52 0x9d 0x94 0x75 |
| 0x69 0xdf 0x98 0xd7 0x6f 0x3e 0xa1 0x0b 0x44 0x4e 0x51 0x1d |
| 0xac 0x5a 0x9e 0x0b 0x66 0x9e 0x40 0xfd 0x49 0x50 0x07 0xc0 |
| 0xc7 0x65 0x76 0x59 0xa6 0xce 0xf6 0x4a 0xb4 0x73 0x9f 0x18 |
| 0x50 0x01 0xaa 0x7d 0x5e 0x01 0x00 0x00 0x2b 0xeb 0x0b 0xf4 |
| 0x81 0xf9 0x20 0xb6 0x4c 0xe9 0xc7 0x0e 0x08 0xd7 0x4e 0xd4 |
| 0xf0 0x4f 0xcd 0xba 0x4b 0x69 0xca 0x15 0x26 0x6e 0x83 0xeb |
| 0x13 0x5c 0xd4 0x4d 0x3a 0xa2 0x81 0x9b 0x4c 0x69 0xdf 0x7e |
| 0x49 0xc8 0x77 0x0f 0x1c 0x22 0x5d 0x3a 0x33 0xb3 0x2a 0xc7 |
| 0x2f 0x90 0xf6 0x01 0x56 0x39 0x74 0xf4 0xec 0x82 0xd7 0x14 |
| 0x02 0x01 0x00 0x00>; |
| dbg-domain = <0x80282ff9>; |
| access-lvl = <0xc0000cc0 0x0cffffc3>; |
| dbg-itvl = <0>; |
| gsa-device = <&gsa>; |
| }; |
| |
| sjtag_gsa { |
| compatible = "google,sjtag"; |
| ms-per-tick = <5590>; |
| ipc-timeout-ms = <450>; |
| pubkey = /bits/ 8 <0x76 0xdb 0x26 0x6b 0x6b 0xe2 0x4e 0x09 0xc8 0xdf 0x0b 0x74 |
| 0x05 0xa0 0xb5 0x61 0x60 0x29 0x43 0xfa 0x36 0xc5 0x1b 0xc0 |
| 0xb6 0x25 0x3a 0x2b 0x2d 0x87 0x55 0x89 0x2c 0x05 0x73 0x6f |
| 0x20 0x54 0x48 0xff 0x9a 0xcd 0xc5 0x5f 0x0f 0xae 0xd2 0x4c |
| 0x2b 0x0b 0x84 0x95 0x16 0x12 0xbf 0x3a 0xe8 0x12 0x9d 0xaa |
| 0x3a 0x6b 0xa6 0xec 0x8d 0x00 0x00 0x00 0x29 0xab 0x75 0x37 |
| 0x51 0x5a 0x4e 0x04 0x7e 0x3e 0x44 0xe9 0x10 0x62 0x45 0x0d |
| 0x9a 0xbe 0x50 0xa8 0x85 0x5f 0xc1 0x7d 0x38 0x8a 0xa1 0x99 |
| 0xee 0xd0 0x35 0xc0 0x07 0x25 0xb0 0x80 0x1b 0x7c 0x18 0xfb |
| 0x38 0x59 0xca 0xb1 0x28 0xad 0xe3 0x39 0x95 0xc8 0x6c 0x29 |
| 0x4e 0x60 0x35 0x19 0x2d 0x3e 0x89 0x49 0x04 0xd6 0xd2 0xa8 |
| 0x0a 0x01 0x00 0x0>; |
| dbg-domain = <0x0000006f>; |
| access-lvl = <0x00000000 0x00003cff>; |
| dbg-itvl = <0>; |
| gsa-device = <&gsa>; |
| }; |
| }; |
