| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* machine generated DO NOT MODIFY |
| * source MW_regmap_ds_v0p54_091819.csv |
| * 2019-11-04 |
| */ |
| |
| #ifndef MAX_M5_REG_H_ |
| #define MAX_M5_REG_H_ |
| |
| /* Status,0x0,0b00000010,0x02 |
| * Br,Smx,Tmx,Vmx,Bi,Smn,Tmn |
| */ |
| #define MAX_M5_STATUS 0x0 |
| #define MAX_M5_STATUS_BR (0x1 << 15) |
| #define MAX_M5_STATUS_SMX (0x1 << 14) |
| #define MAX_M5_STATUS_TMX (0x1 << 13) |
| #define MAX_M5_STATUS_VMX (0x1 << 12) |
| #define MAX_M5_STATUS_BI (0x1 << 11) |
| #define MAX_M5_STATUS_SMN (0x1 << 10) |
| #define MAX_M5_STATUS_TMN (0x1 << 9) |
| #define MAX_M5_STATUS_VMN (0x1 << 8) |
| #define MAX_M5_STATUS_DSOCI (0x1 << 7) |
| #define MAX_M5_STATUS_THMHOT (0x1 << 6) |
| #define MAX_M5_STATUS_SPR_5 (0x1 << 5) |
| #define MAX_M5_STATUS_ISYSMX (0x1 << 4) |
| #define MAX_M5_STATUS_BST (0x1 << 3) |
| #define MAX_M5_STATUS_SPR_2 (0x1 << 2) |
| #define MAX_M5_STATUS_POR (0x1 << 1) |
| #define MAX_M5_STATUS_IMN (0x1 << 0) |
| |
| #define MAX_M5_STATUS_BR_MASK 0x1 |
| #define MAX_M5_STATUS_BR_SHIFT 15 |
| #define MAX_M5_STATUS_BR_CLEAR (~(0x1 << 15)) |
| #define MAX_M5_STATUS_BR_CLR(v) ((v) & MAX_M5_STATUS_BR_CLEAR) |
| #define MAX_M5_STATUS_BR_SET(v) \ |
| (MAX_M5_STATUS_BR_CLR(v) | MAX_M5_STATUS_BR) |
| #define MAX_M5_STATUS_SMX_MASK 0x1 |
| #define MAX_M5_STATUS_SMX_SHIFT 14 |
| #define MAX_M5_STATUS_SMX_CLEAR (~(0x1 << 14)) |
| #define MAX_M5_STATUS_SMX_CLR(v) ((v) & MAX_M5_STATUS_SMX_CLEAR) |
| #define MAX_M5_STATUS_SMX_SET(v) \ |
| (MAX_M5_STATUS_SMX_CLR(v) | MAX_M5_STATUS_SMX) |
| #define MAX_M5_STATUS_TMX_MASK 0x1 |
| #define MAX_M5_STATUS_TMX_SHIFT 13 |
| #define MAX_M5_STATUS_TMX_CLEAR (~(0x1 << 13)) |
| #define MAX_M5_STATUS_TMX_CLR(v) ((v) & MAX_M5_STATUS_TMX_CLEAR) |
| #define MAX_M5_STATUS_TMX_SET(v) \ |
| (MAX_M5_STATUS_TMX_CLR(v) | MAX_M5_STATUS_TMX) |
| #define MAX_M5_STATUS_VMX_MASK 0x1 |
| #define MAX_M5_STATUS_VMX_SHIFT 12 |
| #define MAX_M5_STATUS_VMX_CLEAR (~(0x1 << 12)) |
| #define MAX_M5_STATUS_VMX_CLR(v) ((v) & MAX_M5_STATUS_VMX_CLEAR) |
| #define MAX_M5_STATUS_VMX_SET(v) \ |
| (MAX_M5_STATUS_VMX_CLR(v) | MAX_M5_STATUS_VMX) |
| #define MAX_M5_STATUS_BI_MASK 0x1 |
| #define MAX_M5_STATUS_BI_SHIFT 11 |
| #define MAX_M5_STATUS_BI_CLEAR (~(0x1 << 11)) |
| #define MAX_M5_STATUS_BI_CLR(v) ((v) & MAX_M5_STATUS_BI_CLEAR) |
| #define MAX_M5_STATUS_BI_SET(v) \ |
| (MAX_M5_STATUS_BI_CLR(v) | MAX_M5_STATUS_BI) |
| #define MAX_M5_STATUS_SMN_MASK 0x1 |
| #define MAX_M5_STATUS_SMN_SHIFT 10 |
| #define MAX_M5_STATUS_SMN_CLEAR (~(0x1 << 10)) |
| #define MAX_M5_STATUS_SMN_CLR(v) ((v) & MAX_M5_STATUS_SMN_CLEAR) |
| #define MAX_M5_STATUS_SMN_SET(v) \ |
| (MAX_M5_STATUS_SMN_CLR(v) | MAX_M5_STATUS_SMN) |
| #define MAX_M5_STATUS_TMN_MASK 0x1 |
| #define MAX_M5_STATUS_TMN_SHIFT 9 |
| #define MAX_M5_STATUS_TMN_CLEAR (~(0x1 << 9)) |
| #define MAX_M5_STATUS_TMN_CLR(v) ((v) & MAX_M5_STATUS_TMN_CLEAR) |
| #define MAX_M5_STATUS_TMN_SET(v) \ |
| (MAX_M5_STATUS_TMN_CLR(v) | MAX_M5_STATUS_TMN) |
| #define MAX_M5_STATUS_VMN_MASK 0x1 |
| #define MAX_M5_STATUS_VMN_SHIFT 8 |
| #define MAX_M5_STATUS_VMN_CLEAR (~(0x1 << 8)) |
| #define MAX_M5_STATUS_VMN_CLR(v) ((v) & MAX_M5_STATUS_VMN_CLEAR) |
| #define MAX_M5_STATUS_VMN_SET(v) \ |
| (MAX_M5_STATUS_VMN_CLR(v) | MAX_M5_STATUS_VMN) |
| #define MAX_M5_STATUS_DSOCI_MASK 0x1 |
| #define MAX_M5_STATUS_DSOCI_SHIFT 7 |
| #define MAX_M5_STATUS_DSOCI_CLEAR (~(0x1 << 7)) |
| #define MAX_M5_STATUS_DSOCI_CLR(v) ((v) & MAX_M5_STATUS_DSOCI_CLEAR) |
| #define MAX_M5_STATUS_DSOCI_SET(v) \ |
| (MAX_M5_STATUS_DSOCI_CLR(v) | MAX_M5_STATUS_DSOCI) |
| #define MAX_M5_STATUS_THMHOT_MASK 0x1 |
| #define MAX_M5_STATUS_THMHOT_SHIFT 6 |
| #define MAX_M5_STATUS_THMHOT_CLEAR (~(0x1 << 6)) |
| #define MAX_M5_STATUS_THMHOT_CLR(v) \ |
| ((v) & MAX_M5_STATUS_THMHOT_CLEAR) |
| #define MAX_M5_STATUS_THMHOT_SET(v) \ |
| (MAX_M5_STATUS_THMHOT_CLR(v) | MAX_M5_STATUS_THMHOT) |
| #define MAX_M5_STATUS_SPR_5_MASK 0x1 |
| #define MAX_M5_STATUS_SPR_5_SHIFT 5 |
| #define MAX_M5_STATUS_SPR_5_CLEAR (~(0x1 << 5)) |
| #define MAX_M5_STATUS_SPR_5_CLR(v) ((v) & MAX_M5_STATUS_SPR_5_CLEAR) |
| #define MAX_M5_STATUS_SPR_5_SET(v) \ |
| (MAX_M5_STATUS_SPR_5_CLR(v) | MAX_M5_STATUS_SPR_5) |
| #define MAX_M5_STATUS_ISYSMX_MASK 0x1 |
| #define MAX_M5_STATUS_ISYSMX_SHIFT 4 |
| #define MAX_M5_STATUS_ISYSMX_CLEAR (~(0x1 << 4)) |
| #define MAX_M5_STATUS_ISYSMX_CLR(v) \ |
| ((v) & MAX_M5_STATUS_ISYSMX_CLEAR) |
| #define MAX_M5_STATUS_ISYSMX_SET(v) \ |
| (MAX_M5_STATUS_ISYSMX_CLR(v) | MAX_M5_STATUS_ISYSMX) |
| #define MAX_M5_STATUS_BST_MASK 0x1 |
| #define MAX_M5_STATUS_BST_SHIFT 3 |
| #define MAX_M5_STATUS_BST_CLEAR (~(0x1 << 3)) |
| #define MAX_M5_STATUS_BST_CLR(v) ((v) & MAX_M5_STATUS_BST_CLEAR) |
| #define MAX_M5_STATUS_BST_SET(v) \ |
| (MAX_M5_STATUS_BST_CLR(v) | MAX_M5_STATUS_BST) |
| #define MAX_M5_STATUS_SPR_2_MASK 0x1 |
| #define MAX_M5_STATUS_SPR_2_SHIFT 2 |
| #define MAX_M5_STATUS_SPR_2_CLEAR (~(0x1 << 2)) |
| #define MAX_M5_STATUS_SPR_2_CLR(v) ((v) & MAX_M5_STATUS_SPR_2_CLEAR) |
| #define MAX_M5_STATUS_SPR_2_SET(v) \ |
| (MAX_M5_STATUS_SPR_2_CLR(v) | MAX_M5_STATUS_SPR_2) |
| #define MAX_M5_STATUS_POR_MASK 0x1 |
| #define MAX_M5_STATUS_POR_SHIFT 1 |
| #define MAX_M5_STATUS_POR_CLEAR (~(0x1 << 1)) |
| #define MAX_M5_STATUS_POR_CLR(v) ((v) & MAX_M5_STATUS_POR_CLEAR) |
| #define MAX_M5_STATUS_POR_SET(v) \ |
| (MAX_M5_STATUS_POR_CLR(v) | MAX_M5_STATUS_POR) |
| #define MAX_M5_STATUS_IMN_MASK 0x1 |
| #define MAX_M5_STATUS_IMN_SHIFT 0 |
| #define MAX_M5_STATUS_IMN_CLEAR (~(0x1 << 0)) |
| #define MAX_M5_STATUS_IMN_CLR(v) ((v) & MAX_M5_STATUS_IMN_CLEAR) |
| #define MAX_M5_STATUS_IMN_SET(v) \ |
| (MAX_M5_STATUS_IMN_CLR(v) | MAX_M5_STATUS_IMN) |
| |
| /* VAlrtTh,0x1,0b1111111100000000,0xff00 |
| * MaxVoltageAlrt[7:0],,,,,, |
| */ |
| #define MAX_M5_VALRTTH 0x1 |
| #define MAX_M5_VALRTTH_MAXVOLTAGEALRT (0xff << 8) |
| #define MAX_M5_VALRTTH_MINVOLTAGEALRT (0xff << 0) |
| |
| #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_MASK 0xff |
| #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_SHIFT 8 |
| #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_CLEAR (~(0xff << 8)) |
| #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_CLR(v) \ |
| ((v) & MAX_M5_VALRTTH_MAXVOLTAGEALRT_CLEAR) |
| #define MAX_M5_VALRTTH_MAXVOLTAGEALRT_SET(v) \ |
| (MAX_M5_VALRTTH_MAXVOLTAGEALRT_CLR(v) | MAX_M5_VALRTTH_MAXVOLTAGEALRT) |
| #define MAX_M5_VALRTTH_MINVOLTAGEALRT_MASK 0xff |
| #define MAX_M5_VALRTTH_MINVOLTAGEALRT_SHIFT 0 |
| #define MAX_M5_VALRTTH_MINVOLTAGEALRT_CLEAR (~(0xff << 0)) |
| #define MAX_M5_VALRTTH_MINVOLTAGEALRT_CLR(v) \ |
| ((v) & MAX_M5_VALRTTH_MINVOLTAGEALRT_CLEAR) |
| #define MAX_M5_VALRTTH_MINVOLTAGEALRT_SET(v) \ |
| (MAX_M5_VALRTTH_MINVOLTAGEALRT_CLR(v) | MAX_M5_VALRTTH_MINVOLTAGEALRT) |
| |
| /* TAlrtTh,0x2,0b111111110000000,0x7f80 |
| * MaxTempAlrt[7:0],,,,,, |
| */ |
| #define MAX_M5_TALRTTH 0x2 |
| #define MAX_M5_TALRTTH_MAXTEMPALRT (0xff << 8) |
| #define MAX_M5_TALRTTH_MINTEMPALRT (0xff << 0) |
| |
| #define MAX_M5_TALRTTH_MAXTEMPALRT_MASK 0xff |
| #define MAX_M5_TALRTTH_MAXTEMPALRT_SHIFT 8 |
| #define MAX_M5_TALRTTH_MAXTEMPALRT_CLEAR (~(0xff << 8)) |
| #define MAX_M5_TALRTTH_MAXTEMPALRT_CLR(v) \ |
| ((v) & MAX_M5_TALRTTH_MAXTEMPALRT_CLEAR) |
| #define MAX_M5_TALRTTH_MAXTEMPALRT_SET(v) \ |
| (MAX_M5_TALRTTH_MAXTEMPALRT_CLR(v) | MAX_M5_TALRTTH_MAXTEMPALRT) |
| #define MAX_M5_TALRTTH_MINTEMPALRT_MASK 0xff |
| #define MAX_M5_TALRTTH_MINTEMPALRT_SHIFT 0 |
| #define MAX_M5_TALRTTH_MINTEMPALRT_CLEAR (~(0xff << 0)) |
| #define MAX_M5_TALRTTH_MINTEMPALRT_CLR(v) \ |
| ((v) & MAX_M5_TALRTTH_MINTEMPALRT_CLEAR) |
| #define MAX_M5_TALRTTH_MINTEMPALRT_SET(v) \ |
| (MAX_M5_TALRTTH_MINTEMPALRT_CLR(v) | MAX_M5_TALRTTH_MINTEMPALRT) |
| |
| /* SAlrtTh,0x3,0b1111111100000000,0xff00 |
| * MaxSocAlrt[7:0],,,,,, |
| */ |
| #define MAX_M5_SALRTTH 0x3 |
| #define MAX_M5_SALRTTH_MAXSOCALRT (0xff << 8) |
| #define MAX_M5_SALRTTH_MINSOCALRT (0xff << 0) |
| |
| #define MAX_M5_SALRTTH_MAXSOCALRT_MASK 0xff |
| #define MAX_M5_SALRTTH_MAXSOCALRT_SHIFT 8 |
| #define MAX_M5_SALRTTH_MAXSOCALRT_CLEAR (~(0xff << 8)) |
| #define MAX_M5_SALRTTH_MAXSOCALRT_CLR(v) \ |
| ((v) & MAX_M5_SALRTTH_MAXSOCALRT_CLEAR) |
| #define MAX_M5_SALRTTH_MAXSOCALRT_SET(v) \ |
| (MAX_M5_SALRTTH_MAXSOCALRT_CLR(v) | MAX_M5_SALRTTH_MAXSOCALRT) |
| #define MAX_M5_SALRTTH_MINSOCALRT_MASK 0xff |
| #define MAX_M5_SALRTTH_MINSOCALRT_SHIFT 0 |
| #define MAX_M5_SALRTTH_MINSOCALRT_CLEAR (~(0xff << 0)) |
| #define MAX_M5_SALRTTH_MINSOCALRT_CLR(v) \ |
| ((v) & MAX_M5_SALRTTH_MINSOCALRT_CLEAR) |
| #define MAX_M5_SALRTTH_MINSOCALRT_SET(v) \ |
| (MAX_M5_SALRTTH_MINSOCALRT_CLR(v) | MAX_M5_SALRTTH_MINSOCALRT) |
| |
| /* AtRate,0x4,0b00000000,0x00 |
| * AtRate[15:8],,,,,, |
| */ |
| #define MAX_M5_ATRATE 0x4 |
| |
| /* RepCap,0x5,0b10111011100,0x5dc |
| * RepCap[15:8],,,,,, |
| */ |
| #define MAX_M5_REPCAP 0x5 |
| |
| /* RepSOC,0x6,0b11001000000000,0x3200 |
| * RepSOC[15:8],,,,,, |
| */ |
| #define MAX_M5_REPSOC 0x6 |
| |
| /* Age,0x7,0b110010000000000,0x6400 |
| * Age[15:8],,,,,, |
| */ |
| #define MAX_M5_AGE 0x7 |
| |
| /* Temp,0x8,0b1011000000000,0x1600 |
| * TEMP[15:8],,,,,, |
| */ |
| #define MAX_M5_TEMP 0x8 |
| |
| /* Vcell,0x9,0b1011010000000000,0xb400 |
| * VCELL[15:8],,,,,, |
| */ |
| #define MAX_M5_VCELL 0x9 |
| |
| /* Current,0xA,0b00000000,0x00 |
| * Current[15:8],,,,,, |
| */ |
| #define MAX_M5_CURRENT 0xA |
| |
| /* AvgCurrent,0xB,0b00000000,0x00 |
| * AvgCurrent[15:8],,,,,, |
| */ |
| #define MAX_M5_AVGCURRENT 0xB |
| |
| /* QResidual,0xC,0b00000000,0x00 |
| * Qresidual[15:8],,,,,, |
| */ |
| #define MAX_M5_QRESIDUAL 0xC |
| |
| /* MixSOC,0xD,0b11001000000000,0x3200 |
| * MixSOC[15:8],,,,,, |
| */ |
| #define MAX_M5_MIXSOC 0xD |
| |
| /* AvSOC,0xE,0b11001000000000,0x3200 |
| * AvSOC[15:8],,,,,, |
| */ |
| #define MAX_M5_AVSOC 0xE |
| |
| /* MixCap,0xF,0b10111011100,0x5dc |
| * MixCapH[15:8],,,,,, |
| */ |
| #define MAX_M5_MIXCAP 0xF |
| |
| /* FullCap,0x10,0b101110111000,0xbb8 |
| * FullCAP[15:8],,,,,, |
| */ |
| #define MAX_M5_FULLCAP 0x10 |
| |
| /* TTE,0x11,0b00000000,0x00 |
| * hr[5:0],,,,,,mn[5:4] |
| */ |
| #define MAX_M5_TTE 0x11 |
| #define MAX_M5_TTE_HR (0x3f << 10) |
| #define MAX_M5_TTE_MN (0x3f << 4) |
| #define MAX_M5_TTE_SEC (0xf << 0) |
| |
| #define MAX_M5_TTE_HR_MASK 0x3f |
| #define MAX_M5_TTE_HR_SHIFT 10 |
| #define MAX_M5_TTE_HR_CLEAR (~(0x3f << 10)) |
| #define MAX_M5_TTE_HR_CLR(v) ((v) & MAX_M5_TTE_HR_CLEAR) |
| #define MAX_M5_TTE_HR_SET(v) (MAX_M5_TTE_HR_CLR(v) | MAX_M5_TTE_HR) |
| #define MAX_M5_TTE_MN_MASK 0x3f |
| #define MAX_M5_TTE_MN_SHIFT 4 |
| #define MAX_M5_TTE_MN_CLEAR (~(0x3f << 4)) |
| #define MAX_M5_TTE_MN_CLR(v) ((v) & MAX_M5_TTE_MN_CLEAR) |
| #define MAX_M5_TTE_MN_SET(v) (MAX_M5_TTE_MN_CLR(v) | MAX_M5_TTE_MN) |
| #define MAX_M5_TTE_SEC_MASK 0xf |
| #define MAX_M5_TTE_SEC_SHIFT 0 |
| #define MAX_M5_TTE_SEC_CLEAR (~(0xf << 0)) |
| #define MAX_M5_TTE_SEC_CLR(v) ((v) & MAX_M5_TTE_SEC_CLEAR) |
| #define MAX_M5_TTE_SEC_SET(v) \ |
| (MAX_M5_TTE_SEC_CLR(v) | MAX_M5_TTE_SEC) |
| |
| /* QRTable00,0x12,0b11110000000000,0x3c00 |
| * QRTable00[15:8],,,,,, |
| */ |
| #define MAX_M5_QRTABLE00 0x12 |
| |
| /* FullSocThr,0x13,0b101000000000000,0x5000 |
| * FullSOCThr[15:8],,,,,, |
| */ |
| #define MAX_M5_FULLSOCTHR 0x13 |
| |
| /* Rslow,0x14,0b1010010000,0x290 |
| * RSLOW[15:8],,,,,, |
| */ |
| #define MAX_M5_RSLOW 0x14 |
| |
| /* RFast,0x15,0b101001000,0x148 |
| * RFAST[15:8],,,,,, |
| */ |
| #define MAX_M5_RFAST 0x15 |
| |
| /* AvgTA,0x16,0b1011000000000,0x1600 |
| * AvgTA[15:8],,,,,, |
| */ |
| #define MAX_M5_AVGTA 0x16 |
| |
| /* Cycles,0x17,0b00000000,0x00 |
| * Cycles[15:8],,,,,, |
| */ |
| #define MAX_M5_CYCLES 0x17 |
| |
| /* DesignCap,0x18,0b101110111000,0xbb8 |
| * DesignCap[15:8],,,,,, |
| */ |
| #define MAX_M5_DESIGNCAP 0x18 |
| |
| /* AvgVCell,0x19,0b1011010000000000,0xb400 |
| * AvgVCELL[15:8],,,,,, |
| */ |
| #define MAX_M5_AVGVCELL 0x19 |
| |
| /* MaxMinTemp,0x1A,0b1000000001111111,0x807f |
| * MaxTemperature[7:0],,,,,, |
| */ |
| #define MAX_M5_MAXMINTEMP 0x1A |
| #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE (0xff << 8) |
| #define MAX_M5_MAXMINTEMP_MINTEMPERATURE (0xff << 0) |
| |
| #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_MASK 0xff |
| #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_SHIFT 8 |
| #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_CLEAR (~(0xff << 8)) |
| #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_CLR(v) \ |
| ((v) & MAX_M5_MAXMINTEMP_MAXTEMPERATURE_CLEAR) |
| #define MAX_M5_MAXMINTEMP_MAXTEMPERATURE_SET(v) \ |
| (MAX_M5_MAXMINTEMP_MAXTEMPERATURE_CLR(v) | MAX_M5_MAXMINTEMP_MAXTEMPERATURE) |
| #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_MASK 0xff |
| #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_SHIFT 0 |
| #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_CLEAR (~(0xff << 0)) |
| #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_CLR(v) \ |
| ((v) & MAX_M5_MAXMINTEMP_MINTEMPERATURE_CLEAR) |
| #define MAX_M5_MAXMINTEMP_MINTEMPERATURE_SET(v) \ |
| (MAX_M5_MAXMINTEMP_MINTEMPERATURE_CLR(v) | MAX_M5_MAXMINTEMP_MINTEMPERATURE) |
| |
| /* MaxMinVolt,0x1B,0b11111111,0xff |
| * MaxVoltage[7:0],,,,,, |
| */ |
| #define MAX_M5_MAXMINVOLT 0x1B |
| #define MAX_M5_MAXMINVOLT_MAXVOLTAGE (0xff << 8) |
| #define MAX_M5_MAXMINVOLT_MINVOLTAGE (0xff << 0) |
| |
| #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_MASK 0xff |
| #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_SHIFT 8 |
| #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_CLEAR (~(0xff << 8)) |
| #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_CLR(v) \ |
| ((v) & MAX_M5_MAXMINVOLT_MAXVOLTAGE_CLEAR) |
| #define MAX_M5_MAXMINVOLT_MAXVOLTAGE_SET(v) \ |
| (MAX_M5_MAXMINVOLT_MAXVOLTAGE_CLR(v) | MAX_M5_MAXMINVOLT_MAXVOLTAGE) |
| #define MAX_M5_MAXMINVOLT_MINVOLTAGE_MASK 0xff |
| #define MAX_M5_MAXMINVOLT_MINVOLTAGE_SHIFT 0 |
| #define MAX_M5_MAXMINVOLT_MINVOLTAGE_CLEAR (~(0xff << 0)) |
| #define MAX_M5_MAXMINVOLT_MINVOLTAGE_CLR(v) \ |
| ((v) & MAX_M5_MAXMINVOLT_MINVOLTAGE_CLEAR) |
| #define MAX_M5_MAXMINVOLT_MINVOLTAGE_SET(v) \ |
| (MAX_M5_MAXMINVOLT_MINVOLTAGE_CLR(v) | MAX_M5_MAXMINVOLT_MINVOLTAGE) |
| |
| /* MaxMinCurr,0x1C,0b1000000001111111,0x807f |
| * MaxChargeCurrent[7:0],,,,,, |
| */ |
| #define MAX_M5_MAXMINCURR 0x1C |
| #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT (0xff << 8) |
| #define MAX_M5_MAXMINCURR_MAXDISCURRENT (0xff << 0) |
| |
| #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_MASK 0xff |
| #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_SHIFT 8 |
| #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_CLEAR (~(0xff << 8)) |
| #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_CLR(v) \ |
| ((v) & MAX_M5_MAXMINCURR_MAXCHARGECURRENT_CLEAR) |
| #define MAX_M5_MAXMINCURR_MAXCHARGECURRENT_SET(v) \ |
| (MAX_M5_MAXMINCURR_MAXCHARGECURRENT_CLR(v) | MAX_M5_MAXMINCURR_MAXCHARGECURRENT) |
| #define MAX_M5_MAXMINCURR_MAXDISCURRENT_MASK 0xff |
| #define MAX_M5_MAXMINCURR_MAXDISCURRENT_SHIFT 0 |
| #define MAX_M5_MAXMINCURR_MAXDISCURRENT_CLEAR (~(0xff << 0)) |
| #define MAX_M5_MAXMINCURR_MAXDISCURRENT_CLR(v) \ |
| ((v) & MAX_M5_MAXMINCURR_MAXDISCURRENT_CLEAR) |
| #define MAX_M5_MAXMINCURR_MAXDISCURRENT_SET(v) \ |
| (MAX_M5_MAXMINCURR_MAXDISCURRENT_CLR(v) | MAX_M5_MAXMINCURR_MAXDISCURRENT) |
| |
| /* Config,0x1D,0b10001101010000,0x2350 |
| * FCFE,Ss,Ts,Vs,FGCC,AINSH,Ten |
| */ |
| #define MAX_M5_CONFIG 0x1D |
| #define MAX_M5_CONFIG_FCFE (0x1 << 15) |
| #define MAX_M5_CONFIG_SS (0x1 << 14) |
| #define MAX_M5_CONFIG_TS (0x1 << 13) |
| #define MAX_M5_CONFIG_VS (0x1 << 12) |
| #define MAX_M5_CONFIG_FGCC (0x1 << 11) |
| #define MAX_M5_CONFIG_AINSH (0x1 << 10) |
| #define MAX_M5_CONFIG_TEN (0x1 << 9) |
| #define MAX_M5_CONFIG_TEX (0x1 << 8) |
| #define MAX_M5_CONFIG_SHDN (0x1 << 7) |
| #define MAX_M5_CONFIG_I2CSH (0x1 << 6) |
| #define MAX_M5_CONFIG_ICFE (0x1 << 5) |
| #define MAX_M5_CONFIG_ETHRM (0x1 << 4) |
| #define MAX_M5_CONFIG_FTHRM (0x1 << 3) |
| #define MAX_M5_CONFIG_AEN (0x1 << 2) |
| #define MAX_M5_CONFIG_BEI (0x1 << 1) |
| #define MAX_M5_CONFIG_BER (0x1 << 0) |
| |
| #define MAX_M5_CONFIG_FCFE_MASK 0x1 |
| #define MAX_M5_CONFIG_FCFE_SHIFT 15 |
| #define MAX_M5_CONFIG_FCFE_CLEAR (~(0x1 << 15)) |
| #define MAX_M5_CONFIG_FCFE_CLR(v) ((v) & MAX_M5_CONFIG_FCFE_CLEAR) |
| #define MAX_M5_CONFIG_FCFE_SET(v) \ |
| (MAX_M5_CONFIG_FCFE_CLR(v) | MAX_M5_CONFIG_FCFE) |
| #define MAX_M5_CONFIG_SS_MASK 0x1 |
| #define MAX_M5_CONFIG_SS_SHIFT 14 |
| #define MAX_M5_CONFIG_SS_CLEAR (~(0x1 << 14)) |
| #define MAX_M5_CONFIG_SS_CLR(v) ((v) & MAX_M5_CONFIG_SS_CLEAR) |
| #define MAX_M5_CONFIG_SS_SET(v) \ |
| (MAX_M5_CONFIG_SS_CLR(v) | MAX_M5_CONFIG_SS) |
| #define MAX_M5_CONFIG_TS_MASK 0x1 |
| #define MAX_M5_CONFIG_TS_SHIFT 13 |
| #define MAX_M5_CONFIG_TS_CLEAR (~(0x1 << 13)) |
| #define MAX_M5_CONFIG_TS_CLR(v) ((v) & MAX_M5_CONFIG_TS_CLEAR) |
| #define MAX_M5_CONFIG_TS_SET(v) \ |
| (MAX_M5_CONFIG_TS_CLR(v) | MAX_M5_CONFIG_TS) |
| #define MAX_M5_CONFIG_VS_MASK 0x1 |
| #define MAX_M5_CONFIG_VS_SHIFT 12 |
| #define MAX_M5_CONFIG_VS_CLEAR (~(0x1 << 12)) |
| #define MAX_M5_CONFIG_VS_CLR(v) ((v) & MAX_M5_CONFIG_VS_CLEAR) |
| #define MAX_M5_CONFIG_VS_SET(v) \ |
| (MAX_M5_CONFIG_VS_CLR(v) | MAX_M5_CONFIG_VS) |
| #define MAX_M5_CONFIG_FGCC_MASK 0x1 |
| #define MAX_M5_CONFIG_FGCC_SHIFT 11 |
| #define MAX_M5_CONFIG_FGCC_CLEAR (~(0x1 << 11)) |
| #define MAX_M5_CONFIG_FGCC_CLR(v) ((v) & MAX_M5_CONFIG_FGCC_CLEAR) |
| #define MAX_M5_CONFIG_FGCC_SET(v) \ |
| (MAX_M5_CONFIG_FGCC_CLR(v) | MAX_M5_CONFIG_FGCC) |
| #define MAX_M5_CONFIG_AINSH_MASK 0x1 |
| #define MAX_M5_CONFIG_AINSH_SHIFT 10 |
| #define MAX_M5_CONFIG_AINSH_CLEAR (~(0x1 << 10)) |
| #define MAX_M5_CONFIG_AINSH_CLR(v) ((v) & MAX_M5_CONFIG_AINSH_CLEAR) |
| #define MAX_M5_CONFIG_AINSH_SET(v) \ |
| (MAX_M5_CONFIG_AINSH_CLR(v) | MAX_M5_CONFIG_AINSH) |
| #define MAX_M5_CONFIG_TEN_MASK 0x1 |
| #define MAX_M5_CONFIG_TEN_SHIFT 9 |
| #define MAX_M5_CONFIG_TEN_CLEAR (~(0x1 << 9)) |
| #define MAX_M5_CONFIG_TEN_CLR(v) ((v) & MAX_M5_CONFIG_TEN_CLEAR) |
| #define MAX_M5_CONFIG_TEN_SET(v) \ |
| (MAX_M5_CONFIG_TEN_CLR(v) | MAX_M5_CONFIG_TEN) |
| #define MAX_M5_CONFIG_TEX_MASK 0x1 |
| #define MAX_M5_CONFIG_TEX_SHIFT 8 |
| #define MAX_M5_CONFIG_TEX_CLEAR (~(0x1 << 8)) |
| #define MAX_M5_CONFIG_TEX_CLR(v) ((v) & MAX_M5_CONFIG_TEX_CLEAR) |
| #define MAX_M5_CONFIG_TEX_SET(v) \ |
| (MAX_M5_CONFIG_TEX_CLR(v) | MAX_M5_CONFIG_TEX) |
| #define MAX_M5_CONFIG_SHDN_MASK 0x1 |
| #define MAX_M5_CONFIG_SHDN_SHIFT 7 |
| #define MAX_M5_CONFIG_SHDN_CLEAR (~(0x1 << 7)) |
| #define MAX_M5_CONFIG_SHDN_CLR(v) ((v) & MAX_M5_CONFIG_SHDN_CLEAR) |
| #define MAX_M5_CONFIG_SHDN_SET(v) \ |
| (MAX_M5_CONFIG_SHDN_CLR(v) | MAX_M5_CONFIG_SHDN) |
| #define MAX_M5_CONFIG_I2CSH_MASK 0x1 |
| #define MAX_M5_CONFIG_I2CSH_SHIFT 6 |
| #define MAX_M5_CONFIG_I2CSH_CLEAR (~(0x1 << 6)) |
| #define MAX_M5_CONFIG_I2CSH_CLR(v) ((v) & MAX_M5_CONFIG_I2CSH_CLEAR) |
| #define MAX_M5_CONFIG_I2CSH_SET(v) \ |
| (MAX_M5_CONFIG_I2CSH_CLR(v) | MAX_M5_CONFIG_I2CSH) |
| #define MAX_M5_CONFIG_ICFE_MASK 0x1 |
| #define MAX_M5_CONFIG_ICFE_SHIFT 5 |
| #define MAX_M5_CONFIG_ICFE_CLEAR (~(0x1 << 5)) |
| #define MAX_M5_CONFIG_ICFE_CLR(v) ((v) & MAX_M5_CONFIG_ICFE_CLEAR) |
| #define MAX_M5_CONFIG_ICFE_SET(v) \ |
| (MAX_M5_CONFIG_ICFE_CLR(v) | MAX_M5_CONFIG_ICFE) |
| #define MAX_M5_CONFIG_ETHRM_MASK 0x1 |
| #define MAX_M5_CONFIG_ETHRM_SHIFT 4 |
| #define MAX_M5_CONFIG_ETHRM_CLEAR (~(0x1 << 4)) |
| #define MAX_M5_CONFIG_ETHRM_CLR(v) ((v) & MAX_M5_CONFIG_ETHRM_CLEAR) |
| #define MAX_M5_CONFIG_ETHRM_SET(v) \ |
| (MAX_M5_CONFIG_ETHRM_CLR(v) | MAX_M5_CONFIG_ETHRM) |
| #define MAX_M5_CONFIG_FTHRM_MASK 0x1 |
| #define MAX_M5_CONFIG_FTHRM_SHIFT 3 |
| #define MAX_M5_CONFIG_FTHRM_CLEAR (~(0x1 << 3)) |
| #define MAX_M5_CONFIG_FTHRM_CLR(v) ((v) & MAX_M5_CONFIG_FTHRM_CLEAR) |
| #define MAX_M5_CONFIG_FTHRM_SET(v) \ |
| (MAX_M5_CONFIG_FTHRM_CLR(v) | MAX_M5_CONFIG_FTHRM) |
| #define MAX_M5_CONFIG_AEN_MASK 0x1 |
| #define MAX_M5_CONFIG_AEN_SHIFT 2 |
| #define MAX_M5_CONFIG_AEN_CLEAR (~(0x1 << 2)) |
| #define MAX_M5_CONFIG_AEN_CLR(v) ((v) & MAX_M5_CONFIG_AEN_CLEAR) |
| #define MAX_M5_CONFIG_AEN_SET(v) \ |
| (MAX_M5_CONFIG_AEN_CLR(v) | MAX_M5_CONFIG_AEN) |
| #define MAX_M5_CONFIG_BEI_MASK 0x1 |
| #define MAX_M5_CONFIG_BEI_SHIFT 1 |
| #define MAX_M5_CONFIG_BEI_CLEAR (~(0x1 << 1)) |
| #define MAX_M5_CONFIG_BEI_CLR(v) ((v) & MAX_M5_CONFIG_BEI_CLEAR) |
| #define MAX_M5_CONFIG_BEI_SET(v) \ |
| (MAX_M5_CONFIG_BEI_CLR(v) | MAX_M5_CONFIG_BEI) |
| #define MAX_M5_CONFIG_BER_MASK 0x1 |
| #define MAX_M5_CONFIG_BER_SHIFT 0 |
| #define MAX_M5_CONFIG_BER_CLEAR (~(0x1 << 0)) |
| #define MAX_M5_CONFIG_BER_CLR(v) ((v) & MAX_M5_CONFIG_BER_CLEAR) |
| #define MAX_M5_CONFIG_BER_SET(v) \ |
| (MAX_M5_CONFIG_BER_CLR(v) | MAX_M5_CONFIG_BER) |
| |
| /* IChgTerm,0x1E,0b1111000000,0x3c0 |
| * ICHGTerm[15:8],,,,,, |
| */ |
| #define MAX_M5_ICHGTERM 0x1E |
| |
| /* AvCap,0x1F,0b10111011100,0x5dc |
| * AvCap[15:8],,,,,, |
| */ |
| #define MAX_M5_AVCAP 0x1F |
| |
| /* TTF,0x20,0b1111111111111111,0xffff |
| * hr[5:0],,,,,,mn[5:4] |
| */ |
| #define MAX_M5_TTF 0x20 |
| #define MAX_M5_TTF_HR (0x3f << 10) |
| #define MAX_M5_TTF_MN (0x3f << 4) |
| #define MAX_M5_TTF_SEC (0xf << 0) |
| |
| #define MAX_M5_TTF_HR_MASK 0x3f |
| #define MAX_M5_TTF_HR_SHIFT 10 |
| #define MAX_M5_TTF_HR_CLEAR (~(0x3f << 10)) |
| #define MAX_M5_TTF_HR_CLR(v) ((v) & MAX_M5_TTF_HR_CLEAR) |
| #define MAX_M5_TTF_HR_SET(v) (MAX_M5_TTF_HR_CLR(v) | MAX_M5_TTF_HR) |
| #define MAX_M5_TTF_MN_MASK 0x3f |
| #define MAX_M5_TTF_MN_SHIFT 4 |
| #define MAX_M5_TTF_MN_CLEAR (~(0x3f << 4)) |
| #define MAX_M5_TTF_MN_CLR(v) ((v) & MAX_M5_TTF_MN_CLEAR) |
| #define MAX_M5_TTF_MN_SET(v) (MAX_M5_TTF_MN_CLR(v) | MAX_M5_TTF_MN) |
| #define MAX_M5_TTF_SEC_MASK 0xf |
| #define MAX_M5_TTF_SEC_SHIFT 0 |
| #define MAX_M5_TTF_SEC_CLEAR (~(0xf << 0)) |
| #define MAX_M5_TTF_SEC_CLR(v) ((v) & MAX_M5_TTF_SEC_CLEAR) |
| #define MAX_M5_TTF_SEC_SET(v) \ |
| (MAX_M5_TTF_SEC_CLR(v) | MAX_M5_TTF_SEC) |
| |
| /* DevName,0x21,0b110001000000000,0x6200 |
| * DevName[15:8],,,,,, |
| */ |
| #define MAX_M5_DEVNAME 0x21 |
| |
| /* QRTable10,0x22,0b1101110000000,0x1b80 |
| * QRTable10[15:8],,,,,, |
| */ |
| #define MAX_M5_QRTABLE10 0x22 |
| |
| /* FullCapNom,0x23,0b101110111000,0xbb8 |
| * FullCapNom[15:8],,,,,, |
| */ |
| #define MAX_M5_FULLCAPNOM 0x23 |
| |
| /* TempNom,0x24,0b1010000000000,0x1400 |
| * TempNom[9:2],,,,,, |
| */ |
| #define MAX_M5_TEMPNOM 0x24 |
| #define MAX_M5_TEMPNOM_TEMPNOM (0x3ff << 6) |
| #define MAX_M5_TEMPNOM_SPR_5_0 (0x3f << 0) |
| |
| #define MAX_M5_TEMPNOM_TEMPNOM_MASK 0x3ff |
| #define MAX_M5_TEMPNOM_TEMPNOM_SHIFT 6 |
| #define MAX_M5_TEMPNOM_TEMPNOM_CLEAR (~(0x3ff << 6)) |
| #define MAX_M5_TEMPNOM_TEMPNOM_CLR(v) \ |
| ((v) & MAX_M5_TEMPNOM_TEMPNOM_CLEAR) |
| #define MAX_M5_TEMPNOM_TEMPNOM_SET(v) \ |
| (MAX_M5_TEMPNOM_TEMPNOM_CLR(v) | MAX_M5_TEMPNOM_TEMPNOM) |
| #define MAX_M5_TEMPNOM_SPR_5_0_MASK 0x3f |
| #define MAX_M5_TEMPNOM_SPR_5_0_SHIFT 0 |
| #define MAX_M5_TEMPNOM_SPR_5_0_CLEAR (~(0x3f << 0)) |
| #define MAX_M5_TEMPNOM_SPR_5_0_CLR(v) \ |
| ((v) & MAX_M5_TEMPNOM_SPR_5_0_CLEAR) |
| #define MAX_M5_TEMPNOM_SPR_5_0_SET(v) \ |
| (MAX_M5_TEMPNOM_SPR_5_0_CLR(v) | MAX_M5_TEMPNOM_SPR_5_0) |
| |
| /* TempLim,0x25,0b10001100000101,0x2305 |
| * TempHot[7:0],,,,,, |
| */ |
| #define MAX_M5_TEMPLIM 0x25 |
| #define MAX_M5_TEMPLIM_TEMPHOT (0xff << 8) |
| #define MAX_M5_TEMPLIM_TEMPCOLD (0xff << 0) |
| |
| #define MAX_M5_TEMPLIM_TEMPHOT_MASK 0xff |
| #define MAX_M5_TEMPLIM_TEMPHOT_SHIFT 8 |
| #define MAX_M5_TEMPLIM_TEMPHOT_CLEAR (~(0xff << 8)) |
| #define MAX_M5_TEMPLIM_TEMPHOT_CLR(v) \ |
| ((v) & MAX_M5_TEMPLIM_TEMPHOT_CLEAR) |
| #define MAX_M5_TEMPLIM_TEMPHOT_SET(v) \ |
| (MAX_M5_TEMPLIM_TEMPHOT_CLR(v) | MAX_M5_TEMPLIM_TEMPHOT) |
| #define MAX_M5_TEMPLIM_TEMPCOLD_MASK 0xff |
| #define MAX_M5_TEMPLIM_TEMPCOLD_SHIFT 0 |
| #define MAX_M5_TEMPLIM_TEMPCOLD_CLEAR (~(0xff << 0)) |
| #define MAX_M5_TEMPLIM_TEMPCOLD_CLR(v) \ |
| ((v) & MAX_M5_TEMPLIM_TEMPCOLD_CLEAR) |
| #define MAX_M5_TEMPLIM_TEMPCOLD_SET(v) \ |
| (MAX_M5_TEMPLIM_TEMPCOLD_CLR(v) | MAX_M5_TEMPLIM_TEMPCOLD) |
| |
| /* AvgTA0,0x26,0b1011000000000,0x1600 |
| * AvgTA0[15:8],,,,,, |
| */ |
| #define MAX_M5_AVGTA0 0x26 |
| |
| /* AIN0,0x27,0b1000100011010000,0x88d0 |
| * AIN0[15:8],,,,,, |
| */ |
| #define MAX_M5_AIN0 0x27 |
| |
| /* LearnCfg,0x28,0b10011000000011,0x2603 |
| * LearnRCOMP[2:0],,,LearnTCO[2:0],,,FCLm[1:0] |
| */ |
| #define MAX_M5_LEARNCFG 0x28 |
| #define MAX_M5_LEARNCFG_LEARNRCOMP (0x7 << 13) |
| #define MAX_M5_LEARNCFG_LEARNTCO (0x7 << 10) |
| #define MAX_M5_LEARNCFG_FCLM (0x3 << 8) |
| #define MAX_M5_LEARNCFG_FCX (0x1 << 7) |
| #define MAX_M5_LEARNCFG_FCLRNSTAGE (0x7 << 4) |
| #define MAX_M5_LEARNCFG_SPR_3 (0x1 << 3) |
| #define MAX_M5_LEARNCFG_FILLEMPTY (0x1 << 2) |
| #define MAX_M5_LEARNCFG_MIXEN (0x1 << 1) |
| #define MAX_M5_LEARNCFG_SPR_0 (0x1 << 0) |
| |
| #define MAX_M5_LEARNCFG_LEARNRCOMP_MASK 0x7 |
| #define MAX_M5_LEARNCFG_LEARNRCOMP_SHIFT 13 |
| #define MAX_M5_LEARNCFG_LEARNRCOMP_CLEAR (~(0x7 << 13)) |
| #define MAX_M5_LEARNCFG_LEARNRCOMP_CLR(v) \ |
| ((v) & MAX_M5_LEARNCFG_LEARNRCOMP_CLEAR) |
| #define MAX_M5_LEARNCFG_LEARNRCOMP_SET(v) \ |
| (MAX_M5_LEARNCFG_LEARNRCOMP_CLR(v) | MAX_M5_LEARNCFG_LEARNRCOMP) |
| #define MAX_M5_LEARNCFG_LEARNTCO_MASK 0x7 |
| #define MAX_M5_LEARNCFG_LEARNTCO_SHIFT 10 |
| #define MAX_M5_LEARNCFG_LEARNTCO_CLEAR (~(0x7 << 10)) |
| #define MAX_M5_LEARNCFG_LEARNTCO_CLR(v) \ |
| ((v) & MAX_M5_LEARNCFG_LEARNTCO_CLEAR) |
| #define MAX_M5_LEARNCFG_LEARNTCO_SET(v) \ |
| (MAX_M5_LEARNCFG_LEARNTCO_CLR(v) | MAX_M5_LEARNCFG_LEARNTCO) |
| #define MAX_M5_LEARNCFG_FCLM_MASK 0x3 |
| #define MAX_M5_LEARNCFG_FCLM_SHIFT 8 |
| #define MAX_M5_LEARNCFG_FCLM_CLEAR (~(0x3 << 8)) |
| #define MAX_M5_LEARNCFG_FCLM_CLR(v) \ |
| ((v) & MAX_M5_LEARNCFG_FCLM_CLEAR) |
| #define MAX_M5_LEARNCFG_FCLM_SET(v) \ |
| (MAX_M5_LEARNCFG_FCLM_CLR(v) | MAX_M5_LEARNCFG_FCLM) |
| #define MAX_M5_LEARNCFG_FCX_MASK 0x1 |
| #define MAX_M5_LEARNCFG_FCX_SHIFT 7 |
| #define MAX_M5_LEARNCFG_FCX_CLEAR (~(0x1 << 7)) |
| #define MAX_M5_LEARNCFG_FCX_CLR(v) ((v) & MAX_M5_LEARNCFG_FCX_CLEAR) |
| #define MAX_M5_LEARNCFG_FCX_SET(v) \ |
| (MAX_M5_LEARNCFG_FCX_CLR(v) | MAX_M5_LEARNCFG_FCX) |
| #define MAX_M5_LEARNCFG_FCLRNSTAGE_MASK 0x7 |
| #define MAX_M5_LEARNCFG_FCLRNSTAGE_SHIFT 4 |
| #define MAX_M5_LEARNCFG_FCLRNSTAGE_CLEAR (~(0x7 << 4)) |
| #define MAX_M5_LEARNCFG_FCLRNSTAGE_CLR(v) \ |
| ((v) & MAX_M5_LEARNCFG_FCLRNSTAGE_CLEAR) |
| #define MAX_M5_LEARNCFG_FCLRNSTAGE_SET(v) \ |
| (MAX_M5_LEARNCFG_FCLRNSTAGE_CLR(v) | MAX_M5_LEARNCFG_FCLRNSTAGE) |
| #define MAX_M5_LEARNCFG_SPR_3_MASK 0x1 |
| #define MAX_M5_LEARNCFG_SPR_3_SHIFT 3 |
| #define MAX_M5_LEARNCFG_SPR_3_CLEAR (~(0x1 << 3)) |
| #define MAX_M5_LEARNCFG_SPR_3_CLR(v) \ |
| ((v) & MAX_M5_LEARNCFG_SPR_3_CLEAR) |
| #define MAX_M5_LEARNCFG_SPR_3_SET(v) \ |
| (MAX_M5_LEARNCFG_SPR_3_CLR(v) | MAX_M5_LEARNCFG_SPR_3) |
| #define MAX_M5_LEARNCFG_FILLEMPTY_MASK 0x1 |
| #define MAX_M5_LEARNCFG_FILLEMPTY_SHIFT 2 |
| #define MAX_M5_LEARNCFG_FILLEMPTY_CLEAR (~(0x1 << 2)) |
| #define MAX_M5_LEARNCFG_FILLEMPTY_CLR(v) \ |
| ((v) & MAX_M5_LEARNCFG_FILLEMPTY_CLEAR) |
| #define MAX_M5_LEARNCFG_FILLEMPTY_SET(v) \ |
| (MAX_M5_LEARNCFG_FILLEMPTY_CLR(v) | MAX_M5_LEARNCFG_FILLEMPTY) |
| #define MAX_M5_LEARNCFG_MIXEN_MASK 0x1 |
| #define MAX_M5_LEARNCFG_MIXEN_SHIFT 1 |
| #define MAX_M5_LEARNCFG_MIXEN_CLEAR (~(0x1 << 1)) |
| #define MAX_M5_LEARNCFG_MIXEN_CLR(v) \ |
| ((v) & MAX_M5_LEARNCFG_MIXEN_CLEAR) |
| #define MAX_M5_LEARNCFG_MIXEN_SET(v) \ |
| (MAX_M5_LEARNCFG_MIXEN_CLR(v) | MAX_M5_LEARNCFG_MIXEN) |
| #define MAX_M5_LEARNCFG_SPR_0_MASK 0x1 |
| #define MAX_M5_LEARNCFG_SPR_0_SHIFT 0 |
| #define MAX_M5_LEARNCFG_SPR_0_CLEAR (~(0x1 << 0)) |
| #define MAX_M5_LEARNCFG_SPR_0_CLR(v) \ |
| ((v) & MAX_M5_LEARNCFG_SPR_0_CLEAR) |
| #define MAX_M5_LEARNCFG_SPR_0_SET(v) \ |
| (MAX_M5_LEARNCFG_SPR_0_CLR(v) | MAX_M5_LEARNCFG_SPR_0) |
| |
| /* RC is customizable in MWA1+, not in datasheet */ |
| #define MAX_M5_LEARNCFG_RC_VER_MASK MAX_M5_LEARNCFG_SPR_3_MASK |
| #define MAX_M5_LEARNCFG_RC_VER_SHIFT MAX_M5_LEARNCFG_SPR_3_SHIFT |
| #define MAX_M5_LEARNCFG_RC_VER_CLEAR MAX_M5_LEARNCFG_SPR_3_CLEAR |
| #define MAX_M5_LEARNCFG_RC_VER_CLR(v) MAX_M5_LEARNCFG_SPR_3_CLR(v) |
| #define MAX_M5_LEARNCFG_RC_VER_SET(v) MAX_M5_LEARNCFG_SPR_3_SET(v) |
| |
| #define MAX_M5_LEARNCFG_RC_VER MAX_M5_LEARNCFG_SPR_3 |
| #define MAX_M5_LEARNCFG_RC1 (0x0 << MAX_M5_LEARNCFG_RC_VER_SHIFT) |
| #define MAX_M5_LEARNCFG_RC2 (0x1 << MAX_M5_LEARNCFG_RC_VER_SHIFT) |
| |
| /* FilterCfg,0x29,0b1100111010100100,0xcea4 |
| * NEMPTY[1:0],,NTEMP[2:0],,,NMIX[3:1], |
| */ |
| #define MAX_M5_FILTERCFG 0x29 |
| #define MAX_M5_FILTERCFG_NEMPTY (0x3 << 14) |
| #define MAX_M5_FILTERCFG_NTEMP (0x7 << 11) |
| #define MAX_M5_FILTERCFG_NMIX (0x7 << 8) |
| #define MAX_M5_FILTERCFG_NAVGCELL (0x7 << 5) |
| #define MAX_M5_FILTERCFG_NCURR (0xf << 1) |
| |
| #define MAX_M5_FILTERCFG_NEMPTY_MASK 0x3 |
| #define MAX_M5_FILTERCFG_NEMPTY_SHIFT 14 |
| #define MAX_M5_FILTERCFG_NEMPTY_CLEAR (~(0x3 << 14)) |
| #define MAX_M5_FILTERCFG_NEMPTY_CLR(v) \ |
| ((v) & MAX_M5_FILTERCFG_NEMPTY_CLEAR) |
| #define MAX_M5_FILTERCFG_NEMPTY_SET(v) \ |
| (MAX_M5_FILTERCFG_NEMPTY_CLR(v) | MAX_M5_FILTERCFG_NEMPTY) |
| #define MAX_M5_FILTERCFG_NTEMP_MASK 0x7 |
| #define MAX_M5_FILTERCFG_NTEMP_SHIFT 11 |
| #define MAX_M5_FILTERCFG_NTEMP_CLEAR (~(0x7 << 11)) |
| #define MAX_M5_FILTERCFG_NTEMP_CLR(v) \ |
| ((v) & MAX_M5_FILTERCFG_NTEMP_CLEAR) |
| #define MAX_M5_FILTERCFG_NTEMP_SET(v) \ |
| (MAX_M5_FILTERCFG_NTEMP_CLR(v) | MAX_M5_FILTERCFG_NTEMP) |
| #define MAX_M5_FILTERCFG_NMIX_MASK 0x7 |
| #define MAX_M5_FILTERCFG_NMIX_SHIFT 8 |
| #define MAX_M5_FILTERCFG_NMIX_CLEAR (~(0x7 << 8)) |
| #define MAX_M5_FILTERCFG_NMIX_CLR(v) \ |
| ((v) & MAX_M5_FILTERCFG_NMIX_CLEAR) |
| #define MAX_M5_FILTERCFG_NMIX_SET(v) \ |
| (MAX_M5_FILTERCFG_NMIX_CLR(v) | MAX_M5_FILTERCFG_NMIX) |
| #define MAX_M5_FILTERCFG_NAVGCELL_MASK 0x7 |
| #define MAX_M5_FILTERCFG_NAVGCELL_SHIFT 5 |
| #define MAX_M5_FILTERCFG_NAVGCELL_CLEAR (~(0x7 << 5)) |
| #define MAX_M5_FILTERCFG_NAVGCELL_CLR(v) \ |
| ((v) & MAX_M5_FILTERCFG_NAVGCELL_CLEAR) |
| #define MAX_M5_FILTERCFG_NAVGCELL_SET(v) \ |
| (MAX_M5_FILTERCFG_NAVGCELL_CLR(v) | MAX_M5_FILTERCFG_NAVGCELL) |
| #define MAX_M5_FILTERCFG_NCURR_MASK 0xf |
| #define MAX_M5_FILTERCFG_NCURR_SHIFT 1 |
| #define MAX_M5_FILTERCFG_NCURR_CLEAR (~(0xf << 1)) |
| #define MAX_M5_FILTERCFG_NCURR_CLR(v) \ |
| ((v) & MAX_M5_FILTERCFG_NCURR_CLEAR) |
| #define MAX_M5_FILTERCFG_NCURR_SET(v) \ |
| (MAX_M5_FILTERCFG_NCURR_CLR(v) | MAX_M5_FILTERCFG_NCURR) |
| |
| /* RelaxCfg,0x2A,0b10000011001001,0x20c9 |
| * LoadThr[6:0],,,,,, |
| */ |
| #define MAX_M5_RELAXCFG 0x2A |
| #define MAX_M5_RELAXCFG_LOADTHR (0x7f << 9) |
| #define MAX_M5_RELAXCFG_DVTHR (0xf << 4) |
| #define MAX_M5_RELAXCFG_DTTHR (0xf << 0) |
| |
| #define MAX_M5_RELAXCFG_LOADTHR_MASK 0x7f |
| #define MAX_M5_RELAXCFG_LOADTHR_SHIFT 9 |
| #define MAX_M5_RELAXCFG_LOADTHR_CLEAR (~(0x7f << 9)) |
| #define MAX_M5_RELAXCFG_LOADTHR_CLR(v) \ |
| ((v) & MAX_M5_RELAXCFG_LOADTHR_CLEAR) |
| #define MAX_M5_RELAXCFG_LOADTHR_SET(v) \ |
| (MAX_M5_RELAXCFG_LOADTHR_CLR(v) | MAX_M5_RELAXCFG_LOADTHR) |
| #define MAX_M5_RELAXCFG_DVTHR_MASK 0xf |
| #define MAX_M5_RELAXCFG_DVTHR_SHIFT 4 |
| #define MAX_M5_RELAXCFG_DVTHR_CLEAR (~(0xf << 4)) |
| #define MAX_M5_RELAXCFG_DVTHR_CLR(v) \ |
| ((v) & MAX_M5_RELAXCFG_DVTHR_CLEAR) |
| #define MAX_M5_RELAXCFG_DVTHR_SET(v) \ |
| (MAX_M5_RELAXCFG_DVTHR_CLR(v) | MAX_M5_RELAXCFG_DVTHR) |
| #define MAX_M5_RELAXCFG_DTTHR_MASK 0xf |
| #define MAX_M5_RELAXCFG_DTTHR_SHIFT 0 |
| #define MAX_M5_RELAXCFG_DTTHR_CLEAR (~(0xf << 0)) |
| #define MAX_M5_RELAXCFG_DTTHR_CLR(v) \ |
| ((v) & MAX_M5_RELAXCFG_DTTHR_CLEAR) |
| #define MAX_M5_RELAXCFG_DTTHR_SET(v) \ |
| (MAX_M5_RELAXCFG_DTTHR_CLR(v) | MAX_M5_RELAXCFG_DTTHR) |
| |
| /* MiscCfg,0x2B,0b100111010000,0x9d0 |
| * OopsFilter[3:0],,,,EnBi1,InitVFG,MixRate[4:3] |
| */ |
| #define MAX_M5_MISCCFG 0x2B |
| #define MAX_M5_MISCCFG_OOPSFILTER (0xf << 12) |
| #define MAX_M5_MISCCFG_ENBI1 (0x1 << 11) |
| #define MAX_M5_MISCCFG_INITVFG (0x1 << 10) |
| #define MAX_M5_MISCCFG_MIXRATE (0x1f << 5) |
| #define MAX_M5_MISCCFG_RDFCLRN (0x1 << 4) |
| #define MAX_M5_MISCCFG_VTTL (0x1 << 3) |
| #define MAX_M5_MISCCFG_VEX (0x1 << 2) |
| #define MAX_M5_MISCCFG_SACFG (0x3 << 0) |
| |
| #define MAX_M5_MISCCFG_OOPSFILTER_MASK 0xf |
| #define MAX_M5_MISCCFG_OOPSFILTER_SHIFT 12 |
| #define MAX_M5_MISCCFG_OOPSFILTER_CLEAR (~(0xf << 12)) |
| #define MAX_M5_MISCCFG_OOPSFILTER_CLR(v) \ |
| ((v) & MAX_M5_MISCCFG_OOPSFILTER_CLEAR) |
| #define MAX_M5_MISCCFG_OOPSFILTER_SET(v) \ |
| (MAX_M5_MISCCFG_OOPSFILTER_CLR(v) | MAX_M5_MISCCFG_OOPSFILTER) |
| #define MAX_M5_MISCCFG_ENBI1_MASK 0x1 |
| #define MAX_M5_MISCCFG_ENBI1_SHIFT 11 |
| #define MAX_M5_MISCCFG_ENBI1_CLEAR (~(0x1 << 11)) |
| #define MAX_M5_MISCCFG_ENBI1_CLR(v) \ |
| ((v) & MAX_M5_MISCCFG_ENBI1_CLEAR) |
| #define MAX_M5_MISCCFG_ENBI1_SET(v) \ |
| (MAX_M5_MISCCFG_ENBI1_CLR(v) | MAX_M5_MISCCFG_ENBI1) |
| #define MAX_M5_MISCCFG_INITVFG_MASK 0x1 |
| #define MAX_M5_MISCCFG_INITVFG_SHIFT 10 |
| #define MAX_M5_MISCCFG_INITVFG_CLEAR (~(0x1 << 10)) |
| #define MAX_M5_MISCCFG_INITVFG_CLR(v) \ |
| ((v) & MAX_M5_MISCCFG_INITVFG_CLEAR) |
| #define MAX_M5_MISCCFG_INITVFG_SET(v) \ |
| (MAX_M5_MISCCFG_INITVFG_CLR(v) | MAX_M5_MISCCFG_INITVFG) |
| #define MAX_M5_MISCCFG_MIXRATE_MASK 0x1f |
| #define MAX_M5_MISCCFG_MIXRATE_SHIFT 5 |
| #define MAX_M5_MISCCFG_MIXRATE_CLEAR (~(0x1f << 5)) |
| #define MAX_M5_MISCCFG_MIXRATE_CLR(v) \ |
| ((v) & MAX_M5_MISCCFG_MIXRATE_CLEAR) |
| #define MAX_M5_MISCCFG_MIXRATE_SET(v) \ |
| (MAX_M5_MISCCFG_MIXRATE_CLR(v) | MAX_M5_MISCCFG_MIXRATE) |
| #define MAX_M5_MISCCFG_RDFCLRN_MASK 0x1 |
| #define MAX_M5_MISCCFG_RDFCLRN_SHIFT 4 |
| #define MAX_M5_MISCCFG_RDFCLRN_CLEAR (~(0x1 << 4)) |
| #define MAX_M5_MISCCFG_RDFCLRN_CLR(v) \ |
| ((v) & MAX_M5_MISCCFG_RDFCLRN_CLEAR) |
| #define MAX_M5_MISCCFG_RDFCLRN_SET(v) \ |
| (MAX_M5_MISCCFG_RDFCLRN_CLR(v) | MAX_M5_MISCCFG_RDFCLRN) |
| #define MAX_M5_MISCCFG_VTTL_MASK 0x1 |
| #define MAX_M5_MISCCFG_VTTL_SHIFT 3 |
| #define MAX_M5_MISCCFG_VTTL_CLEAR (~(0x1 << 3)) |
| #define MAX_M5_MISCCFG_VTTL_CLR(v) ((v) & MAX_M5_MISCCFG_VTTL_CLEAR) |
| #define MAX_M5_MISCCFG_VTTL_SET(v) \ |
| (MAX_M5_MISCCFG_VTTL_CLR(v) | MAX_M5_MISCCFG_VTTL) |
| #define MAX_M5_MISCCFG_VEX_MASK 0x1 |
| #define MAX_M5_MISCCFG_VEX_SHIFT 2 |
| #define MAX_M5_MISCCFG_VEX_CLEAR (~(0x1 << 2)) |
| #define MAX_M5_MISCCFG_VEX_CLR(v) ((v) & MAX_M5_MISCCFG_VEX_CLEAR) |
| #define MAX_M5_MISCCFG_VEX_SET(v) \ |
| (MAX_M5_MISCCFG_VEX_CLR(v) | MAX_M5_MISCCFG_VEX) |
| #define MAX_M5_MISCCFG_SACFG_MASK 0x3 |
| #define MAX_M5_MISCCFG_SACFG_SHIFT 0 |
| #define MAX_M5_MISCCFG_SACFG_CLEAR (~(0x3 << 0)) |
| #define MAX_M5_MISCCFG_SACFG_CLR(v) \ |
| ((v) & MAX_M5_MISCCFG_SACFG_CLEAR) |
| #define MAX_M5_MISCCFG_SACFG_SET(v) \ |
| (MAX_M5_MISCCFG_SACFG_CLR(v) | MAX_M5_MISCCFG_SACFG) |
| |
| /* TGain,0x2C,0b1110101110001101,0xeb8d |
| * TGAIN[15:8],,,,,, |
| */ |
| #define MAX_M5_TGAIN 0x2C |
| |
| /* TOff,0x2D,0b10000010101010,0x20aa |
| * TOFF[15:8],,,,,, |
| */ |
| #define MAX_M5_TOFF 0x2D |
| |
| /* CGain,0x2E,0b10000000000,0x400 |
| * CGAIN[15:8],,,,,, |
| */ |
| #define MAX_M5_CGAIN 0x2E |
| |
| /* COff,0x2F,0b00000000,0x00 |
| * COFF[15:8],,,,,, |
| */ |
| #define MAX_M5_COFF 0x2F |
| |
| /* dV_acc,0x30,0b10000000000,0x400 |
| * dV_acc[15:8],,,,,, |
| */ |
| #define MAX_M5_DV_ACC 0x30 |
| |
| /* dI_acc,0x31,0b11001000000,0x640 |
| * dI_acc[15:8],,,,,, |
| */ |
| #define MAX_M5_DI_ACC 0x31 |
| |
| /* QRTable20,0x32,0b101100000100,0xb04 |
| * QRTable20[15:8],,,,,, |
| */ |
| #define MAX_M5_QRTABLE20 0x32 |
| |
| /* AtTTF,0x33,0b1111111111111111,0xffff |
| * AtTTF[15:8],,,,,, |
| */ |
| #define MAX_M5_ATTTF 0x33 |
| |
| /* TConvert,0x34,0b1011000000000,0x1600 |
| * TConvert[15:8],,,,,, |
| */ |
| #define MAX_M5_TCONVERT 0x34 |
| |
| /* FullCapRep,0x35,0b101110111000,0xbb8 |
| * FullCapRep[15:8],,,,,, |
| */ |
| #define MAX_M5_FULLCAPREP 0x35 |
| |
| /* IAvgEmpty,0x36,0b1111010001001000,0xf448 |
| * Iavg_empty[15:8],,,,,, |
| */ |
| #define MAX_M5_IAVGEMPTY 0x36 |
| |
| /* FCTC,0x37,0b10111100000,0x5e0 |
| * FCTC[15:8],,,,,, |
| */ |
| #define MAX_M5_FCTC 0x37 |
| |
| /* RComp0,0x38,0b01110000,0x70 |
| * SPR_15_8[7:0],,,,,, |
| */ |
| #define MAX_M5_RCOMP0 0x38 |
| #define MAX_M5_RCOMP0_SPR_15_8 (0xff << 8) |
| #define MAX_M5_RCOMP0_RCOMP0 (0xff << 0) |
| |
| #define MAX_M5_RCOMP0_SPR_15_8_MASK 0xff |
| #define MAX_M5_RCOMP0_SPR_15_8_SHIFT 8 |
| #define MAX_M5_RCOMP0_SPR_15_8_CLEAR (~(0xff << 8)) |
| #define MAX_M5_RCOMP0_SPR_15_8_CLR(v) \ |
| ((v) & MAX_M5_RCOMP0_SPR_15_8_CLEAR) |
| #define MAX_M5_RCOMP0_SPR_15_8_SET(v) \ |
| (MAX_M5_RCOMP0_SPR_15_8_CLR(v) | MAX_M5_RCOMP0_SPR_15_8) |
| #define MAX_M5_RCOMP0_RCOMP0_MASK 0xff |
| #define MAX_M5_RCOMP0_RCOMP0_SHIFT 0 |
| #define MAX_M5_RCOMP0_RCOMP0_CLEAR (~(0xff << 0)) |
| #define MAX_M5_RCOMP0_RCOMP0_CLR(v) \ |
| ((v) & MAX_M5_RCOMP0_RCOMP0_CLEAR) |
| #define MAX_M5_RCOMP0_RCOMP0_SET(v) \ |
| (MAX_M5_RCOMP0_RCOMP0_CLR(v) | MAX_M5_RCOMP0_RCOMP0) |
| |
| /* TempCo,0x39,0b10011000111101,0x263d |
| * TempCoHot[7:0],,,,,, |
| */ |
| #define MAX_M5_TEMPCO 0x39 |
| #define MAX_M5_TEMPCO_TEMPCOHOT (0xff << 8) |
| #define MAX_M5_TEMPCO_TEMPCOCOLD (0xff << 0) |
| |
| #define MAX_M5_TEMPCO_TEMPCOHOT_MASK 0xff |
| #define MAX_M5_TEMPCO_TEMPCOHOT_SHIFT 8 |
| #define MAX_M5_TEMPCO_TEMPCOHOT_CLEAR (~(0xff << 8)) |
| #define MAX_M5_TEMPCO_TEMPCOHOT_CLR(v) \ |
| ((v) & MAX_M5_TEMPCO_TEMPCOHOT_CLEAR) |
| #define MAX_M5_TEMPCO_TEMPCOHOT_SET(v) \ |
| (MAX_M5_TEMPCO_TEMPCOHOT_CLR(v) | MAX_M5_TEMPCO_TEMPCOHOT) |
| #define MAX_M5_TEMPCO_TEMPCOCOLD_MASK 0xff |
| #define MAX_M5_TEMPCO_TEMPCOCOLD_SHIFT 0 |
| #define MAX_M5_TEMPCO_TEMPCOCOLD_CLEAR (~(0xff << 0)) |
| #define MAX_M5_TEMPCO_TEMPCOCOLD_CLR(v) \ |
| ((v) & MAX_M5_TEMPCO_TEMPCOCOLD_CLEAR) |
| #define MAX_M5_TEMPCO_TEMPCOCOLD_SET(v) \ |
| (MAX_M5_TEMPCO_TEMPCOCOLD_CLR(v) | MAX_M5_TEMPCO_TEMPCOCOLD) |
| |
| /* VEmpty,0x3A,0b1010010101100001,0xa561 |
| * V_Empty[8:1],,,,,, |
| */ |
| #define MAX_M5_VEMPTY 0x3A |
| #define MAX_M5_VEMPTY_V_EMPTY (0xff << 8) |
| #define MAX_M5_VEMPTY_V_RECOVER (0x7f << 1) |
| |
| #define MAX_M5_VEMPTY_V_EMPTY_MASK 0xff |
| #define MAX_M5_VEMPTY_V_EMPTY_SHIFT 8 |
| #define MAX_M5_VEMPTY_V_EMPTY_CLEAR (~(0xff << 8)) |
| #define MAX_M5_VEMPTY_V_EMPTY_CLR(v) \ |
| ((v) & MAX_M5_VEMPTY_V_EMPTY_CLEAR) |
| #define MAX_M5_VEMPTY_V_EMPTY_SET(v) \ |
| (MAX_M5_VEMPTY_V_EMPTY_CLR(v) | MAX_M5_VEMPTY_V_EMPTY) |
| #define MAX_M5_VEMPTY_V_RECOVER_MASK 0x7f |
| #define MAX_M5_VEMPTY_V_RECOVER_SHIFT 1 |
| #define MAX_M5_VEMPTY_V_RECOVER_CLEAR (~(0x7f << 1)) |
| #define MAX_M5_VEMPTY_V_RECOVER_CLR(v) \ |
| ((v) & MAX_M5_VEMPTY_V_RECOVER_CLEAR) |
| #define MAX_M5_VEMPTY_V_RECOVER_SET(v) \ |
| (MAX_M5_VEMPTY_V_RECOVER_CLR(v) | MAX_M5_VEMPTY_V_RECOVER) |
| |
| /* AvgCurrent0,0x3B,0b111111111111111,0x7fff |
| * AvgCurrent0[15:8],,,,,, |
| */ |
| #define MAX_M5_AVGCURRENT0 0x3B |
| |
| /* TaskPeriod,0x3C,0b1011010000000,0x1680 |
| * TaskPeriod[15:8],,,,,, |
| */ |
| #define MAX_M5_TASKPERIOD 0x3C |
| |
| /* FStat,0x3D,0b00000001,0x01 |
| * xBr,RDF,tmode,DeBn,xBi,Relck,RelDt |
| */ |
| #define MAX_M5_FSTAT 0x3D |
| #define MAX_M5_FSTAT_XBR (0x1 << 15) |
| #define MAX_M5_FSTAT_RDF (0x1 << 14) |
| #define MAX_M5_FSTAT_TMODE (0x1 << 13) |
| #define MAX_M5_FSTAT_DEBN (0x1 << 12) |
| #define MAX_M5_FSTAT_XBI (0x1 << 11) |
| #define MAX_M5_FSTAT_RELCK (0x1 << 10) |
| #define MAX_M5_FSTAT_RELDT (0x1 << 9) |
| #define MAX_M5_FSTAT_EDET (0x1 << 8) |
| #define MAX_M5_FSTAT_FQ (0x1 << 7) |
| #define MAX_M5_FSTAT_RELDT2 (0x1 << 6) |
| #define MAX_M5_FSTAT_TIMER_START (0x1 << 5) |
| #define MAX_M5_FSTAT_XBST (0x1 << 4) |
| #define MAX_M5_FSTAT_ACCEN (0x1 << 3) |
| #define MAX_M5_FSTAT_WK (0x1 << 2) |
| #define MAX_M5_FSTAT_LDMDL (0x1 << 1) |
| #define MAX_M5_FSTAT_DNR (0x1 << 0) |
| |
| #define MAX_M5_FSTAT_XBR_MASK 0x1 |
| #define MAX_M5_FSTAT_XBR_SHIFT 15 |
| #define MAX_M5_FSTAT_XBR_CLEAR (~(0x1 << 15)) |
| #define MAX_M5_FSTAT_XBR_CLR(v) ((v) & MAX_M5_FSTAT_XBR_CLEAR) |
| #define MAX_M5_FSTAT_XBR_SET(v) \ |
| (MAX_M5_FSTAT_XBR_CLR(v) | MAX_M5_FSTAT_XBR) |
| #define MAX_M5_FSTAT_RDF_MASK 0x1 |
| #define MAX_M5_FSTAT_RDF_SHIFT 14 |
| #define MAX_M5_FSTAT_RDF_CLEAR (~(0x1 << 14)) |
| #define MAX_M5_FSTAT_RDF_CLR(v) ((v) & MAX_M5_FSTAT_RDF_CLEAR) |
| #define MAX_M5_FSTAT_RDF_SET(v) \ |
| (MAX_M5_FSTAT_RDF_CLR(v) | MAX_M5_FSTAT_RDF) |
| #define MAX_M5_FSTAT_TMODE_MASK 0x1 |
| #define MAX_M5_FSTAT_TMODE_SHIFT 13 |
| #define MAX_M5_FSTAT_TMODE_CLEAR (~(0x1 << 13)) |
| #define MAX_M5_FSTAT_TMODE_CLR(v) ((v) & MAX_M5_FSTAT_TMODE_CLEAR) |
| #define MAX_M5_FSTAT_TMODE_SET(v) \ |
| (MAX_M5_FSTAT_TMODE_CLR(v) | MAX_M5_FSTAT_TMODE) |
| #define MAX_M5_FSTAT_DEBN_MASK 0x1 |
| #define MAX_M5_FSTAT_DEBN_SHIFT 12 |
| #define MAX_M5_FSTAT_DEBN_CLEAR (~(0x1 << 12)) |
| #define MAX_M5_FSTAT_DEBN_CLR(v) ((v) & MAX_M5_FSTAT_DEBN_CLEAR) |
| #define MAX_M5_FSTAT_DEBN_SET(v) \ |
| (MAX_M5_FSTAT_DEBN_CLR(v) | MAX_M5_FSTAT_DEBN) |
| #define MAX_M5_FSTAT_XBI_MASK 0x1 |
| #define MAX_M5_FSTAT_XBI_SHIFT 11 |
| #define MAX_M5_FSTAT_XBI_CLEAR (~(0x1 << 11)) |
| #define MAX_M5_FSTAT_XBI_CLR(v) ((v) & MAX_M5_FSTAT_XBI_CLEAR) |
| #define MAX_M5_FSTAT_XBI_SET(v) \ |
| (MAX_M5_FSTAT_XBI_CLR(v) | MAX_M5_FSTAT_XBI) |
| #define MAX_M5_FSTAT_RELCK_MASK 0x1 |
| #define MAX_M5_FSTAT_RELCK_SHIFT 10 |
| #define MAX_M5_FSTAT_RELCK_CLEAR (~(0x1 << 10)) |
| #define MAX_M5_FSTAT_RELCK_CLR(v) ((v) & MAX_M5_FSTAT_RELCK_CLEAR) |
| #define MAX_M5_FSTAT_RELCK_SET(v) \ |
| (MAX_M5_FSTAT_RELCK_CLR(v) | MAX_M5_FSTAT_RELCK) |
| #define MAX_M5_FSTAT_RELDT_MASK 0x1 |
| #define MAX_M5_FSTAT_RELDT_SHIFT 9 |
| #define MAX_M5_FSTAT_RELDT_CLEAR (~(0x1 << 9)) |
| #define MAX_M5_FSTAT_RELDT_CLR(v) ((v) & MAX_M5_FSTAT_RELDT_CLEAR) |
| #define MAX_M5_FSTAT_RELDT_SET(v) \ |
| (MAX_M5_FSTAT_RELDT_CLR(v) | MAX_M5_FSTAT_RELDT) |
| #define MAX_M5_FSTAT_EDET_MASK 0x1 |
| #define MAX_M5_FSTAT_EDET_SHIFT 8 |
| #define MAX_M5_FSTAT_EDET_CLEAR (~(0x1 << 8)) |
| #define MAX_M5_FSTAT_EDET_CLR(v) ((v) & MAX_M5_FSTAT_EDET_CLEAR) |
| #define MAX_M5_FSTAT_EDET_SET(v) \ |
| (MAX_M5_FSTAT_EDET_CLR(v) | MAX_M5_FSTAT_EDET) |
| #define MAX_M5_FSTAT_FQ_MASK 0x1 |
| #define MAX_M5_FSTAT_FQ_SHIFT 7 |
| #define MAX_M5_FSTAT_FQ_CLEAR (~(0x1 << 7)) |
| #define MAX_M5_FSTAT_FQ_CLR(v) ((v) & MAX_M5_FSTAT_FQ_CLEAR) |
| #define MAX_M5_FSTAT_FQ_SET(v) \ |
| (MAX_M5_FSTAT_FQ_CLR(v) | MAX_M5_FSTAT_FQ) |
| #define MAX_M5_FSTAT_RELDT2_MASK 0x1 |
| #define MAX_M5_FSTAT_RELDT2_SHIFT 6 |
| #define MAX_M5_FSTAT_RELDT2_CLEAR (~(0x1 << 6)) |
| #define MAX_M5_FSTAT_RELDT2_CLR(v) ((v) & MAX_M5_FSTAT_RELDT2_CLEAR) |
| #define MAX_M5_FSTAT_RELDT2_SET(v) \ |
| (MAX_M5_FSTAT_RELDT2_CLR(v) | MAX_M5_FSTAT_RELDT2) |
| #define MAX_M5_FSTAT_TIMER_START_MASK 0x1 |
| #define MAX_M5_FSTAT_TIMER_START_SHIFT 5 |
| #define MAX_M5_FSTAT_TIMER_START_CLEAR (~(0x1 << 5)) |
| #define MAX_M5_FSTAT_TIMER_START_CLR(v) \ |
| ((v) & MAX_M5_FSTAT_TIMER_START_CLEAR) |
| #define MAX_M5_FSTAT_TIMER_START_SET(v) \ |
| (MAX_M5_FSTAT_TIMER_START_CLR(v) | MAX_M5_FSTAT_TIMER_START) |
| #define MAX_M5_FSTAT_XBST_MASK 0x1 |
| #define MAX_M5_FSTAT_XBST_SHIFT 4 |
| #define MAX_M5_FSTAT_XBST_CLEAR (~(0x1 << 4)) |
| #define MAX_M5_FSTAT_XBST_CLR(v) ((v) & MAX_M5_FSTAT_XBST_CLEAR) |
| #define MAX_M5_FSTAT_XBST_SET(v) \ |
| (MAX_M5_FSTAT_XBST_CLR(v) | MAX_M5_FSTAT_XBST) |
| #define MAX_M5_FSTAT_ACCEN_MASK 0x1 |
| #define MAX_M5_FSTAT_ACCEN_SHIFT 3 |
| #define MAX_M5_FSTAT_ACCEN_CLEAR (~(0x1 << 3)) |
| #define MAX_M5_FSTAT_ACCEN_CLR(v) ((v) & MAX_M5_FSTAT_ACCEN_CLEAR) |
| #define MAX_M5_FSTAT_ACCEN_SET(v) \ |
| (MAX_M5_FSTAT_ACCEN_CLR(v) | MAX_M5_FSTAT_ACCEN) |
| #define MAX_M5_FSTAT_WK_MASK 0x1 |
| #define MAX_M5_FSTAT_WK_SHIFT 2 |
| #define MAX_M5_FSTAT_WK_CLEAR (~(0x1 << 2)) |
| #define MAX_M5_FSTAT_WK_CLR(v) ((v) & MAX_M5_FSTAT_WK_CLEAR) |
| #define MAX_M5_FSTAT_WK_SET(v) \ |
| (MAX_M5_FSTAT_WK_CLR(v) | MAX_M5_FSTAT_WK) |
| #define MAX_M5_FSTAT_LDMDL_MASK 0x1 |
| #define MAX_M5_FSTAT_LDMDL_SHIFT 1 |
| #define MAX_M5_FSTAT_LDMDL_CLEAR (~(0x1 << 1)) |
| #define MAX_M5_FSTAT_LDMDL_CLR(v) ((v) & MAX_M5_FSTAT_LDMDL_CLEAR) |
| #define MAX_M5_FSTAT_LDMDL_SET(v) \ |
| (MAX_M5_FSTAT_LDMDL_CLR(v) | MAX_M5_FSTAT_LDMDL) |
| #define MAX_M5_FSTAT_DNR_MASK 0x1 |
| #define MAX_M5_FSTAT_DNR_SHIFT 0 |
| #define MAX_M5_FSTAT_DNR_CLEAR (~(0x1 << 0)) |
| #define MAX_M5_FSTAT_DNR_CLR(v) ((v) & MAX_M5_FSTAT_DNR_CLEAR) |
| #define MAX_M5_FSTAT_DNR_SET(v) \ |
| (MAX_M5_FSTAT_DNR_CLR(v) | MAX_M5_FSTAT_DNR) |
| |
| /* Timer,0x3E,0b00000000,0x00 |
| * TIMER[15:8],,,,,, |
| */ |
| #define MAX_M5_TIMER 0x3E |
| |
| /* ShdnTimer,0x3F,0b1110000000000000,0xe000 |
| * SHDN_THR[2:0],,,SHDNCTR[12:8],,, |
| */ |
| #define MAX_M5_SHDNTIMER 0x3F |
| #define MAX_M5_SHDNTIMER_SHDN_THR (0x7 << 13) |
| #define MAX_M5_SHDNTIMER_SHDNCTR (0x1fff << 0) |
| |
| #define MAX_M5_SHDNTIMER_SHDN_THR_MASK 0x7 |
| #define MAX_M5_SHDNTIMER_SHDN_THR_SHIFT 13 |
| #define MAX_M5_SHDNTIMER_SHDN_THR_CLEAR (~(0x7 << 13)) |
| #define MAX_M5_SHDNTIMER_SHDN_THR_CLR(v) \ |
| ((v) & MAX_M5_SHDNTIMER_SHDN_THR_CLEAR) |
| #define MAX_M5_SHDNTIMER_SHDN_THR_SET(v) \ |
| (MAX_M5_SHDNTIMER_SHDN_THR_CLR(v) | MAX_M5_SHDNTIMER_SHDN_THR) |
| #define MAX_M5_SHDNTIMER_SHDNCTR_MASK 0x1fff |
| #define MAX_M5_SHDNTIMER_SHDNCTR_SHIFT 0 |
| #define MAX_M5_SHDNTIMER_SHDNCTR_CLEAR (~(0x1fff << 0)) |
| #define MAX_M5_SHDNTIMER_SHDNCTR_CLR(v) \ |
| ((v) & MAX_M5_SHDNTIMER_SHDNCTR_CLEAR) |
| #define MAX_M5_SHDNTIMER_SHDNCTR_SET(v) \ |
| (MAX_M5_SHDNTIMER_SHDNCTR_CLR(v) | MAX_M5_SHDNTIMER_SHDNCTR) |
| |
| /* THMHOT,0x40,0b11111111100,0x7fc |
| * VR[4:0],,,,,Vhys[2:0], |
| */ |
| #define MAX_M5_THMHOT 0x40 |
| #define MAX_M5_THMHOT_VR (0x1f << 11) |
| #define MAX_M5_THMHOT_VHYS (0x7 << 8) |
| #define MAX_M5_THMHOT_TR (0x1f << 3) |
| #define MAX_M5_THMHOT_THYS (0x7 << 0) |
| |
| #define MAX_M5_THMHOT_VR_MASK 0x1f |
| #define MAX_M5_THMHOT_VR_SHIFT 11 |
| #define MAX_M5_THMHOT_VR_CLEAR (~(0x1f << 11)) |
| #define MAX_M5_THMHOT_VR_CLR(v) ((v) & MAX_M5_THMHOT_VR_CLEAR) |
| #define MAX_M5_THMHOT_VR_SET(v) \ |
| (MAX_M5_THMHOT_VR_CLR(v) | MAX_M5_THMHOT_VR) |
| #define MAX_M5_THMHOT_VHYS_MASK 0x7 |
| #define MAX_M5_THMHOT_VHYS_SHIFT 8 |
| #define MAX_M5_THMHOT_VHYS_CLEAR (~(0x7 << 8)) |
| #define MAX_M5_THMHOT_VHYS_CLR(v) ((v) & MAX_M5_THMHOT_VHYS_CLEAR) |
| #define MAX_M5_THMHOT_VHYS_SET(v) \ |
| (MAX_M5_THMHOT_VHYS_CLR(v) | MAX_M5_THMHOT_VHYS) |
| #define MAX_M5_THMHOT_TR_MASK 0x1f |
| #define MAX_M5_THMHOT_TR_SHIFT 3 |
| #define MAX_M5_THMHOT_TR_CLEAR (~(0x1f << 3)) |
| #define MAX_M5_THMHOT_TR_CLR(v) ((v) & MAX_M5_THMHOT_TR_CLEAR) |
| #define MAX_M5_THMHOT_TR_SET(v) \ |
| (MAX_M5_THMHOT_TR_CLR(v) | MAX_M5_THMHOT_TR) |
| #define MAX_M5_THMHOT_THYS_MASK 0x7 |
| #define MAX_M5_THMHOT_THYS_SHIFT 0 |
| #define MAX_M5_THMHOT_THYS_CLEAR (~(0x7 << 0)) |
| #define MAX_M5_THMHOT_THYS_CLR(v) ((v) & MAX_M5_THMHOT_THYS_CLEAR) |
| #define MAX_M5_THMHOT_THYS_SET(v) \ |
| (MAX_M5_THMHOT_THYS_CLR(v) | MAX_M5_THMHOT_THYS) |
| |
| /* CTESample,0x41,0b00000000,0x00 |
| * CTESample[15:8],,,,,, |
| */ |
| #define MAX_M5_CTESAMPLE 0x41 |
| |
| /* QRTable30,0x42,0b100010000101,0x885 |
| * QRTable30[15:8],,,,,, |
| */ |
| #define MAX_M5_QRTABLE30 0x42 |
| |
| /* ISys,0x43,0b00000000,0x00 |
| * ISYS[15:8],,,,,, |
| */ |
| #define MAX_M5_ISYS 0x43 |
| |
| /* AvgVCell0,0x44,0b1000000000000000,0x8000 |
| * AvgVCELL0[15:8],,,,,, |
| */ |
| #define MAX_M5_AVGVCELL0 0x44 |
| |
| /* dQAcc,0x45,0b00010111,0x17 |
| * dQacc[15:8],,,,,, |
| */ |
| #define MAX_M5_DQACC 0x45 |
| |
| /* dPAcc,0x46,0b110010000,0x190 |
| * dPacc[15:8],,,,,, |
| */ |
| #define MAX_M5_DPACC 0x46 |
| |
| /* RlxSOC,0x47,0b00000000,0x00 |
| * RlxSOC[15:8],,,,,, |
| */ |
| #define MAX_M5_RLXSOC 0x47 |
| |
| /* VFSOC0,0x48,0b11001000000000,0x3200 |
| * VFSOC0[15:8],,,,,, |
| */ |
| #define MAX_M5_VFSOC0 0x48 |
| |
| /* ConvgCfg,0x49,0b10001001000001,0x2241 |
| * RepLow[3:0],,,,VoltLowOff[4:1],, |
| */ |
| #define MAX_M5_CONVGCFG 0x49 |
| #define MAX_M5_CONVGCFG_REPLOW (0xf << 12) |
| #define MAX_M5_CONVGCFG_VOLTLOWOFF (0xf << 8) |
| #define MAX_M5_CONVGCFG_MINSLOPEX (0xf << 4) |
| #define MAX_M5_CONVGCFG_REPL_PER_STAGE (0x7 << 1) |
| |
| #define MAX_M5_CONVGCFG_REPLOW_MASK 0xf |
| #define MAX_M5_CONVGCFG_REPLOW_SHIFT 12 |
| #define MAX_M5_CONVGCFG_REPLOW_CLEAR (~(0xf << 12)) |
| #define MAX_M5_CONVGCFG_REPLOW_CLR(v) \ |
| ((v) & MAX_M5_CONVGCFG_REPLOW_CLEAR) |
| #define MAX_M5_CONVGCFG_REPLOW_SET(v) \ |
| (MAX_M5_CONVGCFG_REPLOW_CLR(v) | MAX_M5_CONVGCFG_REPLOW) |
| #define MAX_M5_CONVGCFG_VOLTLOWOFF_MASK 0xf |
| #define MAX_M5_CONVGCFG_VOLTLOWOFF_SHIFT 8 |
| #define MAX_M5_CONVGCFG_VOLTLOWOFF_CLEAR (~(0xf << 8)) |
| #define MAX_M5_CONVGCFG_VOLTLOWOFF_CLR(v) \ |
| ((v) & MAX_M5_CONVGCFG_VOLTLOWOFF_CLEAR) |
| #define MAX_M5_CONVGCFG_VOLTLOWOFF_SET(v) \ |
| (MAX_M5_CONVGCFG_VOLTLOWOFF_CLR(v) | MAX_M5_CONVGCFG_VOLTLOWOFF) |
| #define MAX_M5_CONVGCFG_MINSLOPEX_MASK 0xf |
| #define MAX_M5_CONVGCFG_MINSLOPEX_SHIFT 4 |
| #define MAX_M5_CONVGCFG_MINSLOPEX_CLEAR (~(0xf << 4)) |
| #define MAX_M5_CONVGCFG_MINSLOPEX_CLR(v) \ |
| ((v) & MAX_M5_CONVGCFG_MINSLOPEX_CLEAR) |
| #define MAX_M5_CONVGCFG_MINSLOPEX_SET(v) \ |
| (MAX_M5_CONVGCFG_MINSLOPEX_CLR(v) | MAX_M5_CONVGCFG_MINSLOPEX) |
| #define MAX_M5_CONVGCFG_REPL_PER_STAGE_MASK 0x7 |
| #define MAX_M5_CONVGCFG_REPL_PER_STAGE_SHIFT 1 |
| #define MAX_M5_CONVGCFG_REPL_PER_STAGE_CLEAR (~(0x7 << 1)) |
| #define MAX_M5_CONVGCFG_REPL_PER_STAGE_CLR(v) \ |
| ((v) & MAX_M5_CONVGCFG_REPL_PER_STAGE_CLEAR) |
| #define MAX_M5_CONVGCFG_REPL_PER_STAGE_SET(v) \ |
| (MAX_M5_CONVGCFG_REPL_PER_STAGE_CLR(v) | MAX_M5_CONVGCFG_REPL_PER_STAGE) |
| |
| /* VFRemCap,0x4A,0b10111011100,0x5dc |
| * VFRemCap[15:8],,,,,, |
| */ |
| #define MAX_M5_VFREMCAP 0x4A |
| |
| /* AvgISys,0x4B,0b00000000,0x00 |
| * AVGISYS[15:8],,,,,, |
| */ |
| #define MAX_M5_AVGISYS 0x4B |
| |
| /* QH0,0x4C,0b00000000,0x00 |
| * QH0[15:8],,,,,, |
| */ |
| #define MAX_M5_QH0 0x4C |
| |
| /* QH,0x4D,0b00000000,0x00 |
| * QH[15:8],,,,,, |
| */ |
| #define MAX_M5_QH 0x4D |
| |
| /* QL,0x4E,0b00000000,0x00 |
| * QL[15:8],,,,,, |
| */ |
| #define MAX_M5_QL 0x4E |
| |
| /* MixAtFull,0x4F,0b101110111000,0xbb8 |
| * MixAtFull[15:8],,,,,, |
| */ |
| #define MAX_M5_MIXATFULL 0x4F |
| |
| /* Status2,0xB0,0b00000000,0x00 |
| * SPR_15_6[9:2],,,,,, |
| */ |
| #define MAX_M5_STATUS2 0xB0 |
| #define MAX_M5_STATUS2_SPR_15_6 (0x3ff << 6) |
| #define MAX_M5_STATUS2_FULLDET (0x1 << 5) |
| #define MAX_M5_STATUS2_SPR_4_2 (0x7 << 2) |
| #define MAX_M5_STATUS2_HIB (0x1 << 1) |
| #define MAX_M5_STATUS2_SPR_0 (0x1 << 0) |
| |
| #define MAX_M5_STATUS2_SPR_15_6_MASK 0x3ff |
| #define MAX_M5_STATUS2_SPR_15_6_SHIFT 6 |
| #define MAX_M5_STATUS2_SPR_15_6_CLEAR (~(0x3ff << 6)) |
| #define MAX_M5_STATUS2_SPR_15_6_CLR(v) \ |
| ((v) & MAX_M5_STATUS2_SPR_15_6_CLEAR) |
| #define MAX_M5_STATUS2_SPR_15_6_SET(v) \ |
| (MAX_M5_STATUS2_SPR_15_6_CLR(v) | MAX_M5_STATUS2_SPR_15_6) |
| #define MAX_M5_STATUS2_FULLDET_MASK 0x1 |
| #define MAX_M5_STATUS2_FULLDET_SHIFT 5 |
| #define MAX_M5_STATUS2_FULLDET_CLEAR (~(0x1 << 5)) |
| #define MAX_M5_STATUS2_FULLDET_CLR(v) \ |
| ((v) & MAX_M5_STATUS2_FULLDET_CLEAR) |
| #define MAX_M5_STATUS2_FULLDET_SET(v) \ |
| (MAX_M5_STATUS2_FULLDET_CLR(v) | MAX_M5_STATUS2_FULLDET) |
| #define MAX_M5_STATUS2_SPR_4_2_MASK 0x7 |
| #define MAX_M5_STATUS2_SPR_4_2_SHIFT 2 |
| #define MAX_M5_STATUS2_SPR_4_2_CLEAR (~(0x7 << 2)) |
| #define MAX_M5_STATUS2_SPR_4_2_CLR(v) \ |
| ((v) & MAX_M5_STATUS2_SPR_4_2_CLEAR) |
| #define MAX_M5_STATUS2_SPR_4_2_SET(v) \ |
| (MAX_M5_STATUS2_SPR_4_2_CLR(v) | MAX_M5_STATUS2_SPR_4_2) |
| #define MAX_M5_STATUS2_HIB_MASK 0x1 |
| #define MAX_M5_STATUS2_HIB_SHIFT 1 |
| #define MAX_M5_STATUS2_HIB_CLEAR (~(0x1 << 1)) |
| #define MAX_M5_STATUS2_HIB_CLR(v) ((v) & MAX_M5_STATUS2_HIB_CLEAR) |
| #define MAX_M5_STATUS2_HIB_SET(v) \ |
| (MAX_M5_STATUS2_HIB_CLR(v) | MAX_M5_STATUS2_HIB) |
| #define MAX_M5_STATUS2_SPR_0_MASK 0x1 |
| #define MAX_M5_STATUS2_SPR_0_SHIFT 0 |
| #define MAX_M5_STATUS2_SPR_0_CLEAR (~(0x1 << 0)) |
| #define MAX_M5_STATUS2_SPR_0_CLR(v) \ |
| ((v) & MAX_M5_STATUS2_SPR_0_CLEAR) |
| #define MAX_M5_STATUS2_SPR_0_SET(v) \ |
| (MAX_M5_STATUS2_SPR_0_CLR(v) | MAX_M5_STATUS2_SPR_0) |
| |
| /* VSys,0xB1,0b00000000,0x00 |
| * VSys[15:8],,,,,, |
| */ |
| #define MAX_M5_VSYS 0xB1 |
| |
| /* TAlrtTh2,0xB2,0b111111110000000,0x7f80 |
| * TempWarm[7:0],,,,,, |
| */ |
| #define MAX_M5_TALRTTH2 0xB2 |
| #define MAX_M5_TALRTTH2_TEMPWARM (0xff << 8) |
| #define MAX_M5_TALRTTH2_TEMPCOOL (0xff << 0) |
| |
| #define MAX_M5_TALRTTH2_TEMPWARM_MASK 0xff |
| #define MAX_M5_TALRTTH2_TEMPWARM_SHIFT 8 |
| #define MAX_M5_TALRTTH2_TEMPWARM_CLEAR (~(0xff << 8)) |
| #define MAX_M5_TALRTTH2_TEMPWARM_CLR(v) \ |
| ((v) & MAX_M5_TALRTTH2_TEMPWARM_CLEAR) |
| #define MAX_M5_TALRTTH2_TEMPWARM_SET(v) \ |
| (MAX_M5_TALRTTH2_TEMPWARM_CLR(v) | MAX_M5_TALRTTH2_TEMPWARM) |
| #define MAX_M5_TALRTTH2_TEMPCOOL_MASK 0xff |
| #define MAX_M5_TALRTTH2_TEMPCOOL_SHIFT 0 |
| #define MAX_M5_TALRTTH2_TEMPCOOL_CLEAR (~(0xff << 0)) |
| #define MAX_M5_TALRTTH2_TEMPCOOL_CLR(v) \ |
| ((v) & MAX_M5_TALRTTH2_TEMPCOOL_CLEAR) |
| #define MAX_M5_TALRTTH2_TEMPCOOL_SET(v) \ |
| (MAX_M5_TALRTTH2_TEMPCOOL_CLR(v) | MAX_M5_TALRTTH2_TEMPCOOL) |
| |
| /* VByp,0xB3,0b00000000,0x00 |
| * VByp[15:8],,,,,, |
| */ |
| #define MAX_M5_VBYP 0xB3 |
| |
| /* IAlrtTh,0xB4,0b111111110000000,0x7f80 |
| * ISYSOCP_TH[7:0],,,,,, |
| */ |
| #define MAX_M5_IALRTTH 0xB4 |
| #define MAX_M5_IALRTTH_ISYSOCP_TH (0xff << 8) |
| #define MAX_M5_IALRTTH_IBATTMIN_TH (0xff << 0) |
| |
| #define MAX_M5_IALRTTH_ISYSOCP_TH_MASK 0xff |
| #define MAX_M5_IALRTTH_ISYSOCP_TH_SHIFT 8 |
| #define MAX_M5_IALRTTH_ISYSOCP_TH_CLEAR (~(0xff << 8)) |
| #define MAX_M5_IALRTTH_ISYSOCP_TH_CLR(v) \ |
| ((v) & MAX_M5_IALRTTH_ISYSOCP_TH_CLEAR) |
| #define MAX_M5_IALRTTH_ISYSOCP_TH_SET(v) \ |
| (MAX_M5_IALRTTH_ISYSOCP_TH_CLR(v) | MAX_M5_IALRTTH_ISYSOCP_TH) |
| #define MAX_M5_IALRTTH_IBATTMIN_TH_MASK 0xff |
| #define MAX_M5_IALRTTH_IBATTMIN_TH_SHIFT 0 |
| #define MAX_M5_IALRTTH_IBATTMIN_TH_CLEAR (~(0xff << 0)) |
| #define MAX_M5_IALRTTH_IBATTMIN_TH_CLR(v) \ |
| ((v) & MAX_M5_IALRTTH_IBATTMIN_TH_CLEAR) |
| #define MAX_M5_IALRTTH_IBATTMIN_TH_SET(v) \ |
| (MAX_M5_IALRTTH_IBATTMIN_TH_CLR(v) | MAX_M5_IALRTTH_IBATTMIN_TH) |
| |
| /* TTF_CFG,0xB5,0b00000101,0x05 |
| * SPR_15_3[12:5],,,,,, |
| */ |
| #define MAX_M5_TTF_CFG 0xB5 |
| #define MAX_M5_TTF_CFG_SPR_15_3 (0x1fff << 3) |
| #define MAX_M5_TTF_CFG_TTF_CFG (0x7 << 0) |
| |
| #define MAX_M5_TTF_CFG_SPR_15_3_MASK 0x1fff |
| #define MAX_M5_TTF_CFG_SPR_15_3_SHIFT 3 |
| #define MAX_M5_TTF_CFG_SPR_15_3_CLEAR (~(0x1fff << 3)) |
| #define MAX_M5_TTF_CFG_SPR_15_3_CLR(v) \ |
| ((v) & MAX_M5_TTF_CFG_SPR_15_3_CLEAR) |
| #define MAX_M5_TTF_CFG_SPR_15_3_SET(v) \ |
| (MAX_M5_TTF_CFG_SPR_15_3_CLR(v) | MAX_M5_TTF_CFG_SPR_15_3) |
| #define MAX_M5_TTF_CFG_TTF_CFG_MASK 0x7 |
| #define MAX_M5_TTF_CFG_TTF_CFG_SHIFT 0 |
| #define MAX_M5_TTF_CFG_TTF_CFG_CLEAR (~(0x7 << 0)) |
| #define MAX_M5_TTF_CFG_TTF_CFG_CLR(v) \ |
| ((v) & MAX_M5_TTF_CFG_TTF_CFG_CLEAR) |
| #define MAX_M5_TTF_CFG_TTF_CFG_SET(v) \ |
| (MAX_M5_TTF_CFG_TTF_CFG_CLR(v) | MAX_M5_TTF_CFG_TTF_CFG) |
| |
| /* CV_MixCap,0xB6,0b100011001010,0x8ca |
| * CV_MixCap[15:8],,,,,, |
| */ |
| #define MAX_M5_CV_MIXCAP 0xB6 |
| |
| /* CV_HalfTime,0xB7,0b101000000000,0xa00 |
| * CV_Halftime[15:8],,,,,, |
| */ |
| #define MAX_M5_CV_HALFTIME 0xB7 |
| |
| /* CGTempCo,0xB8,0b00000000,0x00 |
| * CGTempCo[15:8],,,,,, |
| */ |
| #define MAX_M5_CGTEMPCO 0xB8 |
| |
| /* Curve,0xB9,0b01101011,0x6b |
| * ECURVE[7:0],,,,,, |
| */ |
| #define MAX_M5_CURVE 0xB9 |
| #define MAX_M5_CURVE_ECURVE (0xff << 8) |
| #define MAX_M5_CURVE_TCURVE (0xff << 0) |
| |
| #define MAX_M5_CURVE_ECURVE_MASK 0xff |
| #define MAX_M5_CURVE_ECURVE_SHIFT 8 |
| #define MAX_M5_CURVE_ECURVE_CLEAR (~(0xff << 8)) |
| #define MAX_M5_CURVE_ECURVE_CLR(v) ((v) & MAX_M5_CURVE_ECURVE_CLEAR) |
| #define MAX_M5_CURVE_ECURVE_SET(v) \ |
| (MAX_M5_CURVE_ECURVE_CLR(v) | MAX_M5_CURVE_ECURVE) |
| #define MAX_M5_CURVE_TCURVE_MASK 0xff |
| #define MAX_M5_CURVE_TCURVE_SHIFT 0 |
| #define MAX_M5_CURVE_TCURVE_CLEAR (~(0xff << 0)) |
| #define MAX_M5_CURVE_TCURVE_CLR(v) ((v) & MAX_M5_CURVE_TCURVE_CLEAR) |
| #define MAX_M5_CURVE_TCURVE_SET(v) \ |
| (MAX_M5_CURVE_TCURVE_CLR(v) | MAX_M5_CURVE_TCURVE) |
| |
| /* HibCfg,0xBA,0b100100001100,0x90c |
| * EnHib,HibEnterTime[2:0],,,HibThreshold[3:0],, |
| */ |
| #define MAX_M5_HIBCFG 0xBA |
| #define MAX_M5_HIBCFG_ENHIB (0x1 << 15) |
| #define MAX_M5_HIBCFG_HIBENTERTIME (0x7 << 12) |
| #define MAX_M5_HIBCFG_HIBTHRESHOLD (0xf << 8) |
| #define MAX_M5_HIBCFG_SPR_7_5 (0x7 << 5) |
| #define MAX_M5_HIBCFG_HIBEXITTIME (0x3 << 3) |
| #define MAX_M5_HIBCFG_HIBSCALAR (0x7 << 0) |
| |
| #define MAX_M5_HIBCFG_ENHIB_MASK 0x1 |
| #define MAX_M5_HIBCFG_ENHIB_SHIFT 15 |
| #define MAX_M5_HIBCFG_ENHIB_CLEAR (~(0x1 << 15)) |
| #define MAX_M5_HIBCFG_ENHIB_CLR(v) ((v) & MAX_M5_HIBCFG_ENHIB_CLEAR) |
| #define MAX_M5_HIBCFG_ENHIB_SET(v) \ |
| (MAX_M5_HIBCFG_ENHIB_CLR(v) | MAX_M5_HIBCFG_ENHIB) |
| #define MAX_M5_HIBCFG_HIBENTERTIME_MASK 0x7 |
| #define MAX_M5_HIBCFG_HIBENTERTIME_SHIFT 12 |
| #define MAX_M5_HIBCFG_HIBENTERTIME_CLEAR (~(0x7 << 12)) |
| #define MAX_M5_HIBCFG_HIBENTERTIME_CLR(v) \ |
| ((v) & MAX_M5_HIBCFG_HIBENTERTIME_CLEAR) |
| #define MAX_M5_HIBCFG_HIBENTERTIME_SET(v) \ |
| (MAX_M5_HIBCFG_HIBENTERTIME_CLR(v) | MAX_M5_HIBCFG_HIBENTERTIME) |
| #define MAX_M5_HIBCFG_HIBTHRESHOLD_MASK 0xf |
| #define MAX_M5_HIBCFG_HIBTHRESHOLD_SHIFT 8 |
| #define MAX_M5_HIBCFG_HIBTHRESHOLD_CLEAR (~(0xf << 8)) |
| #define MAX_M5_HIBCFG_HIBTHRESHOLD_CLR(v) \ |
| ((v) & MAX_M5_HIBCFG_HIBTHRESHOLD_CLEAR) |
| #define MAX_M5_HIBCFG_HIBTHRESHOLD_SET(v) \ |
| (MAX_M5_HIBCFG_HIBTHRESHOLD_CLR(v) | MAX_M5_HIBCFG_HIBTHRESHOLD) |
| #define MAX_M5_HIBCFG_SPR_7_5_MASK 0x7 |
| #define MAX_M5_HIBCFG_SPR_7_5_SHIFT 5 |
| #define MAX_M5_HIBCFG_SPR_7_5_CLEAR (~(0x7 << 5)) |
| #define MAX_M5_HIBCFG_SPR_7_5_CLR(v) \ |
| ((v) & MAX_M5_HIBCFG_SPR_7_5_CLEAR) |
| #define MAX_M5_HIBCFG_SPR_7_5_SET(v) \ |
| (MAX_M5_HIBCFG_SPR_7_5_CLR(v) | MAX_M5_HIBCFG_SPR_7_5) |
| #define MAX_M5_HIBCFG_HIBEXITTIME_MASK 0x3 |
| #define MAX_M5_HIBCFG_HIBEXITTIME_SHIFT 3 |
| #define MAX_M5_HIBCFG_HIBEXITTIME_CLEAR (~(0x3 << 3)) |
| #define MAX_M5_HIBCFG_HIBEXITTIME_CLR(v) \ |
| ((v) & MAX_M5_HIBCFG_HIBEXITTIME_CLEAR) |
| #define MAX_M5_HIBCFG_HIBEXITTIME_SET(v) \ |
| (MAX_M5_HIBCFG_HIBEXITTIME_CLR(v) | MAX_M5_HIBCFG_HIBEXITTIME) |
| #define MAX_M5_HIBCFG_HIBSCALAR_MASK 0x7 |
| #define MAX_M5_HIBCFG_HIBSCALAR_SHIFT 0 |
| #define MAX_M5_HIBCFG_HIBSCALAR_CLEAR (~(0x7 << 0)) |
| #define MAX_M5_HIBCFG_HIBSCALAR_CLR(v) \ |
| ((v) & MAX_M5_HIBCFG_HIBSCALAR_CLEAR) |
| #define MAX_M5_HIBCFG_HIBSCALAR_SET(v) \ |
| (MAX_M5_HIBCFG_HIBSCALAR_CLR(v) | MAX_M5_HIBCFG_HIBSCALAR) |
| |
| /* Config2,0xBB,0b01010000,0x50 |
| * SPR_15_11[4:0],,,,,FCThmHot,ThmHotEn |
| */ |
| #define MAX_M5_CONFIG2 0xBB |
| #define MAX_M5_CONFIG2_SPR_15_11 (0x1f << 11) |
| #define MAX_M5_CONFIG2_FCTHMHOT (0x1 << 10) |
| #define MAX_M5_CONFIG2_THMHOTEN (0x1 << 9) |
| #define MAX_M5_CONFIG2_THMHOTALRTEN (0x1 << 8) |
| #define MAX_M5_CONFIG2_DSOCEN (0x1 << 7) |
| #define MAX_M5_CONFIG2_TALRTEN (0x1 << 6) |
| #define MAX_M5_CONFIG2_LDMDL (0x1 << 5) |
| #define MAX_M5_CONFIG2_OCVQEN (0x1 << 4) |
| #define MAX_M5_CONFIG2_ISYSNCURR (0xf << 0) |
| |
| #define MAX_M5_CONFIG2_SPR_15_11_MASK 0x1f |
| #define MAX_M5_CONFIG2_SPR_15_11_SHIFT 11 |
| #define MAX_M5_CONFIG2_SPR_15_11_CLEAR (~(0x1f << 11)) |
| #define MAX_M5_CONFIG2_SPR_15_11_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_SPR_15_11_CLEAR) |
| #define MAX_M5_CONFIG2_SPR_15_11_SET(v) \ |
| (MAX_M5_CONFIG2_SPR_15_11_CLR(v) | MAX_M5_CONFIG2_SPR_15_11) |
| #define MAX_M5_CONFIG2_FCTHMHOT_MASK 0x1 |
| #define MAX_M5_CONFIG2_FCTHMHOT_SHIFT 10 |
| #define MAX_M5_CONFIG2_FCTHMHOT_CLEAR (~(0x1 << 10)) |
| #define MAX_M5_CONFIG2_FCTHMHOT_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_FCTHMHOT_CLEAR) |
| #define MAX_M5_CONFIG2_FCTHMHOT_SET(v) \ |
| (MAX_M5_CONFIG2_FCTHMHOT_CLR(v) | MAX_M5_CONFIG2_FCTHMHOT) |
| #define MAX_M5_CONFIG2_THMHOTEN_MASK 0x1 |
| #define MAX_M5_CONFIG2_THMHOTEN_SHIFT 9 |
| #define MAX_M5_CONFIG2_THMHOTEN_CLEAR (~(0x1 << 9)) |
| #define MAX_M5_CONFIG2_THMHOTEN_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_THMHOTEN_CLEAR) |
| #define MAX_M5_CONFIG2_THMHOTEN_SET(v) \ |
| (MAX_M5_CONFIG2_THMHOTEN_CLR(v) | MAX_M5_CONFIG2_THMHOTEN) |
| #define MAX_M5_CONFIG2_THMHOTALRTEN_MASK 0x1 |
| #define MAX_M5_CONFIG2_THMHOTALRTEN_SHIFT 8 |
| #define MAX_M5_CONFIG2_THMHOTALRTEN_CLEAR (~(0x1 << 8)) |
| #define MAX_M5_CONFIG2_THMHOTALRTEN_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_THMHOTALRTEN_CLEAR) |
| #define MAX_M5_CONFIG2_THMHOTALRTEN_SET(v) \ |
| (MAX_M5_CONFIG2_THMHOTALRTEN_CLR(v) | MAX_M5_CONFIG2_THMHOTALRTEN) |
| #define MAX_M5_CONFIG2_DSOCEN_MASK 0x1 |
| #define MAX_M5_CONFIG2_DSOCEN_SHIFT 7 |
| #define MAX_M5_CONFIG2_DSOCEN_CLEAR (~(0x1 << 7)) |
| #define MAX_M5_CONFIG2_DSOCEN_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_DSOCEN_CLEAR) |
| #define MAX_M5_CONFIG2_DSOCEN_SET(v) \ |
| (MAX_M5_CONFIG2_DSOCEN_CLR(v) | MAX_M5_CONFIG2_DSOCEN) |
| #define MAX_M5_CONFIG2_TALRTEN_MASK 0x1 |
| #define MAX_M5_CONFIG2_TALRTEN_SHIFT 6 |
| #define MAX_M5_CONFIG2_TALRTEN_CLEAR (~(0x1 << 6)) |
| #define MAX_M5_CONFIG2_TALRTEN_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_TALRTEN_CLEAR) |
| #define MAX_M5_CONFIG2_TALRTEN_SET(v) \ |
| (MAX_M5_CONFIG2_TALRTEN_CLR(v) | MAX_M5_CONFIG2_TALRTEN) |
| #define MAX_M5_CONFIG2_LDMDL_MASK 0x1 |
| #define MAX_M5_CONFIG2_LDMDL_SHIFT 5 |
| #define MAX_M5_CONFIG2_LDMDL_CLEAR (~(0x1 << 5)) |
| #define MAX_M5_CONFIG2_LDMDL_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_LDMDL_CLEAR) |
| #define MAX_M5_CONFIG2_LDMDL_SET(v) \ |
| (MAX_M5_CONFIG2_LDMDL_CLR(v) | MAX_M5_CONFIG2_LDMDL) |
| #define MAX_M5_CONFIG2_OCVQEN_MASK 0x1 |
| #define MAX_M5_CONFIG2_OCVQEN_SHIFT 4 |
| #define MAX_M5_CONFIG2_OCVQEN_CLEAR (~(0x1 << 4)) |
| #define MAX_M5_CONFIG2_OCVQEN_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_OCVQEN_CLEAR) |
| #define MAX_M5_CONFIG2_OCVQEN_SET(v) \ |
| (MAX_M5_CONFIG2_OCVQEN_CLR(v) | MAX_M5_CONFIG2_OCVQEN) |
| #define MAX_M5_CONFIG2_ISYSNCURR_MASK 0xf |
| #define MAX_M5_CONFIG2_ISYSNCURR_SHIFT 0 |
| #define MAX_M5_CONFIG2_ISYSNCURR_CLEAR (~(0xf << 0)) |
| #define MAX_M5_CONFIG2_ISYSNCURR_CLR(v) \ |
| ((v) & MAX_M5_CONFIG2_ISYSNCURR_CLEAR) |
| #define MAX_M5_CONFIG2_ISYSNCURR_SET(v) \ |
| (MAX_M5_CONFIG2_ISYSNCURR_CLR(v) | MAX_M5_CONFIG2_ISYSNCURR) |
| |
| /* VRipple,0xBC,0b00000000,0x00 |
| * Vripple[15:8],,,,,, |
| */ |
| #define MAX_M5_VRIPPLE 0xBC |
| |
| /* RippleCfg,0xBD,0b1000000100,0x204 |
| * kDV[12:5],,,,,, |
| */ |
| #define MAX_M5_RIPPLECFG 0xBD |
| #define MAX_M5_RIPPLECFG_KDV (0x1fff << 3) |
| #define MAX_M5_RIPPLECFG_NR (0x7 << 0) |
| |
| #define MAX_M5_RIPPLECFG_KDV_MASK 0x1fff |
| #define MAX_M5_RIPPLECFG_KDV_SHIFT 3 |
| #define MAX_M5_RIPPLECFG_KDV_CLEAR (~(0x1fff << 3)) |
| #define MAX_M5_RIPPLECFG_KDV_CLR(v) \ |
| ((v) & MAX_M5_RIPPLECFG_KDV_CLEAR) |
| #define MAX_M5_RIPPLECFG_KDV_SET(v) \ |
| (MAX_M5_RIPPLECFG_KDV_CLR(v) | MAX_M5_RIPPLECFG_KDV) |
| #define MAX_M5_RIPPLECFG_NR_MASK 0x7 |
| #define MAX_M5_RIPPLECFG_NR_SHIFT 0 |
| #define MAX_M5_RIPPLECFG_NR_CLEAR (~(0x7 << 0)) |
| #define MAX_M5_RIPPLECFG_NR_CLR(v) ((v) & MAX_M5_RIPPLECFG_NR_CLEAR) |
| #define MAX_M5_RIPPLECFG_NR_SET(v) \ |
| (MAX_M5_RIPPLECFG_NR_CLR(v) | MAX_M5_RIPPLECFG_NR) |
| |
| /* TimerH,0xBE,0b00000000,0x00 |
| * TIMERH[15:8],,,,,, |
| */ |
| #define MAX_M5_TIMERH 0xBE |
| |
| /* MaxError,0xBF,0b00000000,0x00 |
| * MaxError[15:8],,,,,, |
| */ |
| #define MAX_M5_MAXERROR 0xBF |
| |
| /* IIn,0xD0,0b00000000,0x00 |
| * IIn[15:8],,,,,, |
| */ |
| #define MAX_M5_IIN 0xD0 |
| |
| /* AtQresidual,0xDC,0b00000000,0x00 |
| * AtQresidual[15:8],,,,,, |
| */ |
| #define MAX_M5_ATQRESIDUAL 0xDC |
| |
| /* AtTTE,0xDD,0b00000000,0x00 |
| * AtTTE[15:8],,,,,, |
| */ |
| #define MAX_M5_ATTTE 0xDD |
| |
| /* AtAvSOC,0xDE,0b00000000,0x00 |
| * AtAvSOC[15:8],,,,,, |
| */ |
| #define MAX_M5_ATAVSOC 0xDE |
| |
| /* AtAvCap,0xDF,0b00000000,0x00 |
| * AtAvCap[15:8],,,,,, |
| */ |
| #define MAX_M5_ATAVCAP 0xDF |
| |
| #endif /* MAX_M5_REG_H_ */ |
