| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * cs40l26.h -- CS40L26 Boosted Haptic Driver with Integrated DSP and |
| * Waveform Memory with Advanced Closed Loop Algorithms and LRA protection |
| * |
| * Copyright 2022 Cirrus Logic, Inc. |
| * |
| * Author: Fred Treven <fred.treven@cirrus.com> |
| */ |
| |
| #ifndef __CS40L26_H__ |
| #define __CS40L26_H__ |
| |
| #include <linux/input.h> |
| #include <linux/regmap.h> |
| #include <linux/mfd/core.h> |
| #include <linux/module.h> |
| #include <linux/moduleparam.h> |
| #include <linux/init.h> |
| #include <linux/version.h> |
| #include <linux/kernel.h> |
| #include <linux/i2c.h> |
| #include <linux/spi/spi.h> |
| #include <linux/string.h> |
| #include <linux/gpio.h> |
| #include <linux/gpio/consumer.h> |
| #include <linux/interrupt.h> |
| #include <linux/of_device.h> |
| #include <linux/platform_device.h> |
| #include <linux/uaccess.h> |
| #include <linux/regulator/consumer.h> |
| #include <linux/delay.h> |
| #include <linux/completion.h> |
| #include <linux/firmware.h> |
| #include <linux/sysfs.h> |
| #include <linux/bitops.h> |
| #include <linux/pm_runtime.h> |
| #include <linux/debugfs.h> |
| #include <sound/core.h> |
| #include <sound/pcm.h> |
| #include <sound/pcm_params.h> |
| #include <sound/soc.h> |
| #include <sound/initval.h> |
| #include <sound/tlv.h> |
| #if IS_ENABLED(CONFIG_GOOG_CUST) |
| #include <linux/timekeeping.h> |
| #endif |
| |
| #include "cl_dsp.h" |
| #include "../../../gs-google/drivers/soc/google/vh/kernel/systrace.h" |
| |
| #define CS40L26_FIRSTREG 0x0 |
| #define CS40L26_LASTREG 0x3C7DFE8 |
| |
| #define CS40L26_DEVID 0x0 |
| #define CS40L26_REVID 0x4 |
| #define CS40L26_FABID 0x8 |
| #define CS40L26_RELID 0xC |
| #define CS40L26_OTPID 0x10 |
| #define CS40L26_SFT_RESET 0x20 |
| #define CS40L26_TEST_KEY_CTRL 0x40 |
| #define CS40L26_USER_KEY_CTRL 0x44 |
| #define CS40L26_CTRL_ASYNC0 0x50 |
| #define CS40L26_CTRL_ASYNC1 0x54 |
| #define CS40L26_CTRL_ASYNC2 0x58 |
| #define CS40L26_CTRL_ASYNC3 0x5C |
| #define CS40L26_CIF_MON1 0x140 |
| #define CS40L26_CIF_MON2 0x144 |
| #define CS40L26_CIF_MON_PADDR 0x148 |
| #define CS40L26_CTRL_IF_SPARE1 0x154 |
| #define CS40L26_CTRL_IF_I2C 0x158 |
| #define CS40L26_CTRL_IF_I2C_1_CONTROL 0x160 |
| #define CS40L26_CTRL_IF_I2C_1_BROADCAST 0x164 |
| #define CS40L26_APB_MSTR_DSP_BRIDGE_ERR 0x174 |
| #define CS40L26_CIF1_BRIDGE_ERR 0x178 |
| #define CS40L26_CIF2_BRIDGE_ERR 0x17C |
| #define CS40L26_OTP_CTRL0 0x400 |
| #define CS40L26_OTP_CTRL1 0x404 |
| #define CS40L26_OTP_CTRL3 0x408 |
| #define CS40L26_OTP_CTRL4 0x40C |
| #define CS40L26_OTP_CTRL5 0x410 |
| #define CS40L26_OTP_CTRL6 0x414 |
| #define CS40L26_OTP_CTRL7 0x418 |
| #define CS40L26_OTP_CTRL8 0x41C |
| #define CS40L26_GLOBAL_ENABLES 0x2014 |
| #define CS40L26_BLOCK_ENABLES 0x2018 |
| #define CS40L26_BLOCK_ENABLES2 0x201C |
| #define CS40L26_GLOBAL_OVERRIDES 0x2020 |
| #define CS40L26_GLOBAL_SYNC 0x2024 |
| #define CS40L26_GLOBAL_STATUS 0x2028 |
| #define CS40L26_DISCH_FILT 0x202C |
| #define CS40L26_OSC_TRIM 0x2030 |
| #define CS40L26_ERROR_RELEASE 0x2034 |
| #define CS40L26_PLL_OVERRIDE 0x2038 |
| #define CS40L26_CHIP_STATUS_1 0x2040 |
| #define CS40L26_CHIP_STATUS_2 0x2044 |
| #define CS40L26_BIAS_PTE_MODE_CONTROL 0x2404 |
| #define CS40L26_SCL_PAD_CONTROL 0x2408 |
| #define CS40L26_SDA_PAD_CONTROL 0x240C |
| #define CS40L26_LRCK_PAD_CONTROL 0x2418 |
| #define CS40L26_SCLK_PAD_CONTROL 0x241C |
| #define CS40L26_SDIN_PAD_CONTROL 0x2420 |
| #define CS40L26_SDOUT_PAD_CONTROL 0x2424 |
| #define CS40L26_GPIO_PAD_CONTROL 0x242C |
| #define CS40L26_MDSYNC_PAD_CONTROL 0x2430 |
| #define CS40L26_JTAG_CONTROL 0x2438 |
| #define CS40L26_GPIO1_PAD_CONTROL 0x243C |
| #define CS40L26_GPIO_GLOBAL_ENABLE_CONTROL 0x2440 |
| #define CS40L26_GPIO_LEVELSHIFT_BYPASS 0x2444 |
| #define CS40L26_I2C_ADDR_DETECT_CNTL0 0x2800 |
| #define CS40L26_I2C_ADDR_DET_STATUS0 0x2820 |
| #define CS40L26_DEVID_METAL 0x2854 |
| #define CS40L26_PWRMGT_CTL 0x2900 |
| #define CS40L26_WAKESRC_CTL 0x2904 |
| #define CS40L26_WAKEI2C_CTL 0x2908 |
| #define CS40L26_PWRMGT_STS 0x290C |
| #define CS40L26_PWRMGT_RST 0x2910 |
| #define CS40L26_REFCLK_INPUT 0x2C04 |
| #define CS40L26_DSP_CLOCK_GEARING 0x2C08 |
| #define CS40L26_GLOBAL_SAMPLE_RATE 0x2C0C |
| #define CS40L26_DATA_FS_SEL 0x2C10 |
| #define CS40L26_FREE_RUN_FORCE 0x2C14 |
| #define CS40L26_ASP_RATE_DOUBLE_CONTROL0 0x2C18 |
| #define CS40L26_NZ_AUDIO_DETECT0 0x2C1C |
| #define CS40L26_NZ_AUDIO_DETECT1 0x2C20 |
| #define CS40L26_NZ_AUDIO_DETECT2 0x2C24 |
| #define CS40L26_PLL_REFCLK_DETECT_0 0x2C28 |
| #define CS40L26_SP_SCLK_CLOCKING 0x2D00 |
| #define CS40L26_CONFIG0 0x2D04 |
| #define CS40L26_CONFIG1 0x2D08 |
| #define CS40L26_CONFIG2 0x2D0C |
| #define CS40L26_FS_MON_0 0x2D10 |
| #define CS40L26_FS_MON_1 0x2D14 |
| #define CS40L26_FS_MON_2 0x2D18 |
| #define CS40L26_FS_MON_OVERRIDE 0x2D1C |
| #define CS40L26_DFT 0x2D20 |
| #define CS40L26_ANALOG_ADC_CONTROLS 0x2D24 |
| #define CS40L26_SPK_CHOP_CLK_CONTROLS 0x2D28 |
| #define CS40L26_DSP1_SAMPLE_RATE_RX1 0x2D3C |
| #define CS40L26_DSP1_SAMPLE_RATE_RX2 0x2D40 |
| #define CS40L26_DSP1_SAMPLE_RATE_TX1 0x2D60 |
| #define CS40L26_DSP1_SAMPLE_RATE_TX2 0x2D64 |
| #define CS40L26_CLOCK_PHASE 0x2D80 |
| #define CS40L26_USER_CONTROL 0x3000 |
| #define CS40L26_CONFIG_RATES 0x3004 |
| #define CS40L26_LOOP_PARAMETERS 0x3008 |
| #define CS40L26_LDOA_CONTROL 0x300C |
| #define CS40L26_DCO_CONTROL 0x3010 |
| #define CS40L26_MISC_CONTROL 0x3014 |
| #define CS40L26_LOOP_OVERRIDES 0x3018 |
| #define CS40L26_DCO_CTRL_OVERRIDES 0x301C |
| #define CS40L26_CONTROL_READ 0x3020 |
| #define CS40L26_CONTROL_READ_2 0x3024 |
| #define CS40L26_DCO_CAL_CONTROL_1 0x3028 |
| #define CS40L26_DCO_CAL_CONTROL_2 0x302C |
| #define CS40L26_DCO_CAL_STATUS 0x3030 |
| #define CS40L26_SYNC_TX_RX_ENABLES 0x3400 |
| #define CS40L26_SYNC_POWER_CTL 0x3404 |
| #define CS40L26_SYNC_SW_TX_ID 0x3408 |
| #define CS40L26_SYNC_SW_RX 0x3414 |
| #define CS40L26_SYNC_SW_TX 0x3418 |
| #define CS40L26_SYNC_LSW_RX 0x3424 |
| #define CS40L26_SYNC_LSW_TX 0x3428 |
| #define CS40L26_SYNC_SW_DATA_TX_STATUS 0x3430 |
| #define CS40L26_SYNC_SW_DATA_RX_STATUS 0x3434 |
| #define CS40L26_SYNC_ERROR_STATUS 0x3438 |
| #define CS40L26_MDSYNC_SYNC_RX_DECODE_CTL_1 0x3500 |
| #define CS40L26_MDSYNC_SYNC_RX_DECODE_CTL_2 0x3504 |
| #define CS40L26_MDSYNC_SYNC_TX_ENCODE_CTL 0x3508 |
| #define CS40L26_MDSYNC_SYNC_IDLE_STATE_CTL 0x350C |
| #define CS40L26_MDSYNC_SYNC_SLEEP_STATE_CTL 0x3510 |
| #define CS40L26_MDSYNC_SYNC_TYPE 0x3514 |
| #define CS40L26_MDSYNC_SYNC_TRIGGER 0x3518 |
| #define CS40L26_MDSYNC_SYNC_PTE0 0x3520 |
| #define CS40L26_MDSYNC_SYNC_PTE1 0x3524 |
| #define CS40L26_SYNC_PTE2 0x3528 |
| #define CS40L26_SYNC_PTE3 0x352C |
| #define CS40L26_VBST_CTL_1 0x3800 |
| #define CS40L26_VBST_CTL_2 0x3804 |
| #define CS40L26_BST_IPK_CTL 0x3808 |
| #define CS40L26_SOFT_RAMP 0x380C |
| #define CS40L26_BST_LOOP_COEFF 0x3810 |
| #define CS40L26_LBST_SLOPE 0x3814 |
| #define CS40L26_BST_SW_FREQ 0x3818 |
| #define CS40L26_BST_DCM_CTL 0x381C |
| #define CS40L26_DCM_FORCE 0x3820 |
| #define CS40L26_VBST_OVP 0x3830 |
| #define CS40L26_BST_DCR 0x3840 |
| #define CS40L26_TEST_LBST 0x391C |
| #define CS40L26_VPI_LIMIT_MODE 0x3C04 |
| #define CS40L26_VPI_LIMITING 0x3C08 |
| #define CS40L26_VPI_VP_THLDS 0x3C0C |
| #define CS40L26_VPI_TRACKING 0x3C10 |
| #define CS40L26_VPI_TRIG_TIME 0x3C14 |
| #define CS40L26_VPI_TRIG_STEPS 0x3C18 |
| #define CS40L26_VPI_STATES 0x3E04 |
| #define CS40L26_VPI_OUTPUT_RATE 0x3E08 |
| #define CS40L26_VMON_IMON_VOL_POL 0x4000 |
| #define CS40L26_SPKMON_RATE_SEL 0x4004 |
| #define CS40L26_MONITOR_FILT 0x4008 |
| #define CS40L26_IMON_COMP 0x4010 |
| #define CS40L26_SPKMON_VMON_DEC_OUT_DATA 0x41B4 |
| #define CS40L26_WARN_LIMIT_THRESHOLD 0x4220 |
| #define CS40L26_CONFIGURATION 0x4224 |
| #define CS40L26_STATUS 0x4300 |
| #define CS40L26_ENABLES_AND_CODES_ANA 0x4304 |
| #define CS40L26_ENABLES_AND_CODES_DIG 0x4308 |
| #define CS40L26_CALIBR_STATUS 0x430C |
| #define CS40L26_TEMP_RESYNC 0x4310 |
| #define CS40L26_ERROR_LIMIT_THLD_OVERRIDE 0x4320 |
| #define CS40L26_WARN_LIMIT_THLD_OVERRIDE 0x4324 |
| #define CS40L26_CALIBR_ROUTINE_CONFIGURATIONS 0x4368 |
| #define CS40L26_STATUS_FS 0x4380 |
| #define CS40L26_ASP_ENABLES1 0x4800 |
| #define CS40L26_ASP_CONTROL1 0x4804 |
| #define CS40L26_ASP_CONTROL2 0x4808 |
| #define CS40L26_ASP_CONTROL3 0x480C |
| #define CS40L26_ASP_FRAME_CONTROL1 0x4810 |
| #define CS40L26_ASP_FRAME_CONTROL5 0x4820 |
| #define CS40L26_ASP_DATA_CONTROL1 0x4830 |
| #define CS40L26_ASP_DATA_CONTROL5 0x4840 |
| #define CS40L26_ASP_LATENCY1 0x4850 |
| #define CS40L26_ASP_CONTROL4 0x4854 |
| #define CS40L26_ASP_FSYNC_CONTROL1 0x4860 |
| #define CS40L26_ASP_FSYNC_CONTROL2 0x4864 |
| #define CS40L26_ASP_FSYNC_STATUS1 0x4868 |
| #define CS40L26_DACPCM1_INPUT 0x4C00 |
| #define CS40L26_DACMETA1_INPUT 0x4C04 |
| #define CS40L26_DACPCM2_INPUT 0x4C08 |
| #define CS40L26_ASPTX1_INPUT 0x4C20 |
| #define CS40L26_ASPTX2_INPUT 0x4C24 |
| #define CS40L26_ASPTX3_INPUT 0x4C28 |
| #define CS40L26_ASPTX4_INPUT 0x4C2C |
| #define CS40L26_DSP1RX1_INPUT 0x4C40 |
| #define CS40L26_DSP1RX2_INPUT 0x4C44 |
| #define CS40L26_DSP1RX3_INPUT 0x4C48 |
| #define CS40L26_DSP1RX4_INPUT 0x4C4C |
| #define CS40L26_DSP1RX5_INPUT 0x4C50 |
| #define CS40L26_DSP1RX6_INPUT 0x4C54 |
| #define CS40L26_NGATE1_INPUT 0x4C60 |
| #define CS40L26_NGATE2_INPUT 0x4C64 |
| #define CS40L26_SPARE_CP_BITS_0 0x5C00 |
| #define CS40L26_VIS_ADDR_CNTL1_4 0x5C40 |
| #define CS40L26_VIS_ADDR_CNTL5_8 0x5C44 |
| #define CS40L26_VIS_ADDR_CNTL9_12 0x5C48 |
| #define CS40L26_VIS_ADDR_CNTL13_16 0x5C4C |
| #define CS40L26_VIS_ADDR_CNTL_17_20 0x5C50 |
| #define CS40L26_BLOCK_SEL_CNTL0_3 0x5C54 |
| #define CS40L26_BIT_SEL_CNTL 0x5C5C |
| #define CS40L26_ANALOG_VIS_CNTL 0x5C60 |
| #define CS40L26_AMP_CTRL 0x6000 |
| #define CS40L26_VPBR_CONFIG 0x6404 |
| #define CS40L26_VBBR_CONFIG 0x6408 |
| #define CS40L26_VPBR_STATUS 0x640C |
| #define CS40L26_VBBR_STATUS 0x6410 |
| #define CS40L26_OTW_CONFIG 0x6414 |
| #define CS40L26_AMP_ERROR_VOL_SEL 0x6418 |
| #define CS40L26_VPBR_FILTER_CONFIG 0x6448 |
| #define CS40L26_VBBR_FILTER_CONFIG 0x644C |
| #define CS40L26_VOL_STATUS_TO_DSP 0x6450 |
| #define CS40L26_AMP_GAIN 0x6C04 |
| #define CS40L26_SVC_CTRL 0x7200 |
| #define CS40L26_SVC_SER_R 0x7204 |
| #define CS40L26_SVC_R_LPF 0x7208 |
| #define CS40L26_SVC_FILT_CFG 0x720C |
| #define CS40L26_SVC_SER_L_CTRL 0x7218 |
| #define CS40L26_SVC_SER_C_CTRL 0x721C |
| #define CS40L26_SVC_PAR_RLC_SF 0x7220 |
| #define CS40L26_SVC_PAR_RLC_C1 0x7224 |
| #define CS40L26_SVC_PAR_RLC_C2 0x7228 |
| #define CS40L26_SVC_PAR_RLC_B1 0x722C |
| #define CS40L26_SVC_GAIN 0x7230 |
| #define CS40L26_SVC_STATUS 0x7238 |
| #define CS40L26_SVC_IMON_SF 0x723C |
| #define CS40L26_DAC_MSM_CONFIG 0x7400 |
| #define CS40L26_TST_DAC_MSM_CONFIG 0x7404 |
| #define CS40L26_ALIVE_DCIN_WD 0x7424 |
| #define CS40L26_IRQ1_CFG 0x10000 |
| #define CS40L26_IRQ1_STATUS 0x10004 |
| #define CS40L26_IRQ1_EINT_1 0x10010 |
| #define CS40L26_IRQ1_EINT_2 0x10014 |
| #define CS40L26_IRQ1_EINT_3 0x10018 |
| #define CS40L26_IRQ1_EINT_4 0x1001C |
| #define CS40L26_IRQ1_EINT_5 0x10020 |
| #define CS40L26_IRQ1_STS_1 0x10090 |
| #define CS40L26_IRQ1_STS_2 0x10094 |
| #define CS40L26_IRQ1_STS_3 0x10098 |
| #define CS40L26_IRQ1_STS_4 0x1009C |
| #define CS40L26_IRQ1_STS_5 0x100A0 |
| #define CS40L26_IRQ1_MASK_1 0x10110 |
| #define CS40L26_IRQ1_MASK_2 0x10114 |
| #define CS40L26_IRQ1_MASK_3 0x10118 |
| #define CS40L26_IRQ1_MASK_4 0x1011C |
| #define CS40L26_IRQ1_MASK_5 0x10120 |
| #define CS40L26_IRQ1_FRC_1 0x10190 |
| #define CS40L26_IRQ1_FRC_2 0x10194 |
| #define CS40L26_IRQ1_FRC_3 0x10198 |
| #define CS40L26_IRQ1_FRC_4 0x1019C |
| #define CS40L26_IRQ1_FRC_5 0x101A0 |
| #define CS40L26_IRQ1_EDGE_1 0x10210 |
| #define CS40L26_IRQ1_POL_1 0x10290 |
| #define CS40L26_IRQ1_POL_2 0x10294 |
| #define CS40L26_IRQ1_POL_3 0x10298 |
| #define CS40L26_IRQ1_POL_5 0x102A0 |
| #define CS40L26_IRQ1_DB_2 0x10314 |
| #define CS40L26_GPIO_STATUS1 0x11000 |
| #define CS40L26_GPIO_FORCE 0x11004 |
| #define CS40L26_GPIO1_CTRL1 0x11008 |
| #define CS40L26_GPIO2_CTRL1 0x1100C |
| #define CS40L26_GPIO3_CTRL1 0x11010 |
| #define CS40L26_GPIO4_CTRL1 0x11014 |
| #define CS40L26_MIXER_NGATE_CFG 0x12000 |
| #define CS40L26_MIXER_NGATE_CH1_CFG 0x12004 |
| #define CS40L26_MIXER_NGATE_CH2_CFG 0x12008 |
| #define CS40L26_DSP_MBOX_1 0x13000 |
| #define CS40L26_DSP_MBOX_2 0x13004 |
| #define CS40L26_DSP_MBOX_3 0x13008 |
| #define CS40L26_DSP_MBOX_4 0x1300C |
| #define CS40L26_DSP_MBOX_5 0x13010 |
| #define CS40L26_DSP_MBOX_6 0x13014 |
| #define CS40L26_DSP_MBOX_7 0x13018 |
| #define CS40L26_DSP_MBOX_8 0x1301C |
| #define CS40L26_DSP_VIRTUAL1_MBOX_1 0x13020 |
| #define CS40L26_DSP_VIRTUAL1_MBOX_2 0x13024 |
| #define CS40L26_DSP_VIRTUAL1_MBOX_3 0x13028 |
| #define CS40L26_DSP_VIRTUAL1_MBOX_4 0x1302C |
| #define CS40L26_DSP_VIRTUAL1_MBOX_5 0x13030 |
| #define CS40L26_DSP_VIRTUAL1_MBOX_6 0x13034 |
| #define CS40L26_DSP_VIRTUAL1_MBOX_7 0x13038 |
| #define CS40L26_DSP_VIRTUAL1_MBOX_8 0x1303C |
| #define CS40L26_DSP_VIRTUAL2_MBOX_1 0x13040 |
| #define CS40L26_DSP_VIRTUAL2_MBOX_2 0x13044 |
| #define CS40L26_DSP_VIRTUAL2_MBOX_3 0x13048 |
| #define CS40L26_DSP_VIRTUAL2_MBOX_4 0x1304C |
| #define CS40L26_DSP_VIRTUAL2_MBOX_5 0x13050 |
| #define CS40L26_DSP_VIRTUAL2_MBOX_6 0x13054 |
| #define CS40L26_DSP_VIRTUAL2_MBOX_7 0x13058 |
| #define CS40L26_DSP_VIRTUAL2_MBOX_8 0x1305C |
| #define CS40L26_TIMER1_CONTROL 0x15000 |
| #define CS40L26_TIMER1_COUNT_PRESET 0x15004 |
| #define CS40L26_TIMER1_START_AND_STOP 0x1500C |
| #define CS40L26_TIMER1_STATUS 0x15010 |
| #define CS40L26_TIMER1_COUNT_READBACK 0x15014 |
| #define CS40L26_TIMER1_DSP_CLOCK_CONFIG 0x15018 |
| #define CS40L26_TIMER1_DSP_CLOCK_STATUS 0x1501C |
| #define CS40L26_TIMER2_CONTROL 0x15100 |
| #define CS40L26_TIMER2_COUNT_PRESET 0x15104 |
| #define CS40L26_TIMER2_START_AND_STOP 0x1510C |
| #define CS40L26_TIMER2_STATUS 0x15110 |
| #define CS40L26_TIMER2_COUNT_READBACK 0x15114 |
| #define CS40L26_TIMER2_DSP_CLOCK_CONFIG 0x15118 |
| #define CS40L26_TIMER2_DSP_CLOCK_STATUS 0x1511C |
| #define CS40L26_DFT_JTAG_CTRL 0x16000 |
| #define CS40L26_TEMP_CAL2 0x1704C |
| #define CS40L26_OTP_MEM0 0x30000 |
| #define CS40L26_OTP_MEM31 0x3007C |
| #define CS40L26_DSP1_XMEM_PACKED_0 0x2000000 |
| #define CS40L26_DSP1_XMEM_PACKED_1 0x2000004 |
| #define CS40L26_DSP1_XMEM_PACKED_2 0x2000008 |
| #define CS40L26_DSP1_XMEM_PACKED_6141 0x2005FF4 |
| #define CS40L26_DSP1_XMEM_PACKED_6142 0x2005FF8 |
| #define CS40L26_DSP1_XMEM_PACKED_6143 0x2005FFC |
| #define CS40L26_DSP1_XROM_PACKED_0 0x2006000 |
| #define CS40L26_DSP1_XROM_PACKED_1 0x2006004 |
| #define CS40L26_DSP1_XROM_PACKED_2 0x2006008 |
| #define CS40L26_DSP1_XROM_PACKED_4602 0x200A7E8 |
| #define CS40L26_DSP1_XROM_PACKED_4603 0x200A7EC |
| #define CS40L26_DSP1_XROM_PACKED_4604 0x200A7F0 |
| #define CS40L26_DSP1_XMEM_UNPACKED32_0 0x2400000 |
| #define CS40L26_DSP1_XMEM_UNPACKED32_1 0x2400004 |
| #define CS40L26_DSP1_XMEM_UNPACKED32_4094 0x2403FF8 |
| #define CS40L26_DSP1_XMEM_UNPACKED32_4095 0x2403FFC |
| #define CS40L26_DSP1_XROM_UNPACKED32_0 0x2404000 |
| #define CS40L26_DSP1_XROM_UNPACKED32_1 0x2404004 |
| #define CS40L26_DSP1_XROM_UNPACKED32_3069 0x2406FF4 |
| #define CS40L26_DSP1_XROM_UNPACKED32_3070 0x2406FF8 |
| #define CS40L26_DSP1_TIMESTAMP_COUNT 0x25C0800 |
| #define CS40L26_DSP1_SYS_INFO_ID 0x25E0000 |
| #define CS40L26_DSP1_SYS_INFO_VERSION 0x25E0004 |
| #define CS40L26_DSP1_SYS_INFO_CORE_ID 0x25E0008 |
| #define CS40L26_DSP1_SYS_INFO_AHB_ADDR 0x25E000C |
| #define CS40L26_DSP1_SYS_INFO_XM_SRAM_SIZE 0x25E0010 |
| #define CS40L26_DSP1_SYS_INFO_XM_ROM_SIZE 0x25E0014 |
| #define CS40L26_DSP1_SYS_INFO_YM_SRAM_SIZE 0x25E0018 |
| #define CS40L26_DSP1_SYS_INFO_YM_ROM_SIZE 0x25E001C |
| #define CS40L26_DSP1_SYS_INFO_PM_SRAM_SIZE 0x25E0020 |
| #define CS40L26_DSP1_SYS_INFO_PM_BOOT_SIZE 0x25E0028 |
| #define CS40L26_DSP1_SYS_INFO_FEATURES 0x25E002C |
| #define CS40L26_DSP1_SYS_INFO_FIR_FILTERS 0x25E0030 |
| #define CS40L26_DSP1_SYS_INFO_LMS_FILTERS 0x25E0034 |
| #define CS40L26_DSP1_SYS_INFO_XM_BANK_SIZE 0x25E0038 |
| #define CS40L26_DSP1_SYS_INFO_YM_BANK_SIZE 0x25E003C |
| #define CS40L26_DSP1_SYS_INFO_PM_BANK_SIZE 0x25E0040 |
| #define CS40L26_DSP1_SYS_INFO_STREAM_ARB 0x25E0044 |
| #define CS40L26_DSP1_SYS_INFO_XM_EMEM_SIZE 0x25E0048 |
| #define CS40L26_DSP1_SYS_INFO_YM_EMEM_SIZE 0x25E004C |
| #define CS40L26_DSP1_AHBM_WINDOW0_CONTROL_0 0x25E2000 |
| #define CS40L26_DSP1_AHBM_WINDOW0_CONTROL_1 0x25E2004 |
| #define CS40L26_DSP1_AHBM_WINDOW1_CONTROL_0 0x25E2008 |
| #define CS40L26_DSP1_AHBM_WINDOW1_CONTROL_1 0x25E200C |
| #define CS40L26_DSP1_AHBM_WINDOW2_CONTROL_0 0x25E2010 |
| #define CS40L26_DSP1_AHBM_WINDOW2_CONTROL_1 0x25E2014 |
| #define CS40L26_DSP1_AHBM_WINDOW3_CONTROL_0 0x25E2018 |
| #define CS40L26_DSP1_AHBM_WINDOW3_CONTROL_1 0x25E201C |
| #define CS40L26_DSP1_AHBM_WINDOW4_CONTROL_0 0x25E2020 |
| #define CS40L26_DSP1_AHBM_WINDOW4_CONTROL_1 0x25E2024 |
| #define CS40L26_DSP1_AHBM_WINDOW5_CONTROL_0 0x25E2028 |
| #define CS40L26_DSP1_AHBM_WINDOW5_CONTROL_1 0x25E202C |
| #define CS40L26_DSP1_AHBM_WINDOW6_CONTROL_0 0x25E2030 |
| #define CS40L26_DSP1_AHBM_WINDOW6_CONTROL_1 0x25E2034 |
| #define CS40L26_DSP1_AHBM_WINDOW7_CONTROL_0 0x25E2038 |
| #define CS40L26_DSP1_AHBM_WINDOW7_CONTROL_1 0x25E203C |
| #define CS40L26_DSP1_AHBM_WINDOW_DEBUG_0 0x25E2040 |
| #define CS40L26_DSP1_AHBM_WINDOW_DEBUG_1 0x25E2044 |
| #define CS40L26_DSP1_XMEM_UNPACKED24_0 0x2800000 |
| #define CS40L26_DSP1_XMEM_UNPACKED24_1 0x2800004 |
| #define CS40L26_DSP1_XMEM_UNPACKED24_2 0x2800008 |
| #define CS40L26_DSP1_XMEM_UNPACKED24_3 0x280000C |
| #define CS40L26_DSP1_XMEM_UNPACKED24_8188 0x2807FF0 |
| #define CS40L26_DSP1_XMEM_UNPACKED24_8189 0x2807FF4 |
| #define CS40L26_DSP1_XMEM_UNPACKED24_8190 0x2807FF8 |
| #define CS40L26_DSP1_XMEM_UNPACKED24_8191 0x2807FFC |
| #define CS40L26_DSP1_XROM_UNPACKED24_0 0x2808000 |
| #define CS40L26_DSP1_XROM_UNPACKED24_1 0x2808004 |
| #define CS40L26_DSP1_XROM_UNPACKED24_2 0x2808008 |
| #define CS40L26_DSP1_XROM_UNPACKED24_3 0x280800C |
| #define CS40L26_DSP1_XROM_UNPACKED24_6138 0x280DFE8 |
| #define CS40L26_DSP1_XROM_UNPACKED24_6139 0x280DFEC |
| #define CS40L26_DSP1_XROM_UNPACKED24_6140 0x280DFF0 |
| #define CS40L26_DSP1_XROM_UNPACKED24_6141 0x280DFF4 |
| #define CS40L26_DSP1_CLOCK_FREQ 0x2B80000 |
| #define CS40L26_DSP1_CLOCK_STATUS 0x2B80008 |
| #define CS40L26_DSP1_CORE_SOFT_RESET 0x2B80010 |
| #define CS40L26_DSP1_CORE_WRAP_STATUS 0x2B80020 |
| #define CS40L26_DSP1_TIMER_CONTROL 0x2B80048 |
| #define CS40L26_DSP1_STREAM_ARB_CONTROL 0x2B80050 |
| #define CS40L26_DSP1_NMI_CONTROL1 0x2B80480 |
| #define CS40L26_DSP1_NMI_CONTROL2 0x2B80488 |
| #define CS40L26_DSP1_NMI_CONTROL3 0x2B80490 |
| #define CS40L26_DSP1_NMI_CONTROL4 0x2B80498 |
| #define CS40L26_DSP1_NMI_CONTROL5 0x2B804A0 |
| #define CS40L26_DSP1_NMI_CONTROL6 0x2B804A8 |
| #define CS40L26_DSP1_NMI_CONTROL7 0x2B804B0 |
| #define CS40L26_DSP1_NMI_CONTROL8 0x2B804B8 |
| #define CS40L26_DSP1_RESUME_CONTROL 0x2B80500 |
| #define CS40L26_DSP1_IRQ1_CONTROL 0x2B80508 |
| #define CS40L26_DSP1_IRQ2_CONTROL 0x2B80510 |
| #define CS40L26_DSP1_IRQ3_CONTROL 0x2B80518 |
| #define CS40L26_DSP1_IRQ4_CONTROL 0x2B80520 |
| #define CS40L26_DSP1_IRQ5_CONTROL 0x2B80528 |
| #define CS40L26_DSP1_IRQ6_CONTROL 0x2B80530 |
| #define CS40L26_DSP1_IRQ7_CONTROL 0x2B80538 |
| #define CS40L26_DSP1_IRQ8_CONTROL 0x2B80540 |
| #define CS40L26_DSP1_IRQ9_CONTROL 0x2B80548 |
| #define CS40L26_DSP1_IRQ10_CONTROL 0x2B80550 |
| #define CS40L26_DSP1_IRQ11_CONTROL 0x2B80558 |
| #define CS40L26_DSP1_IRQ12_CONTROL 0x2B80560 |
| #define CS40L26_DSP1_IRQ13_CONTROL 0x2B80568 |
| #define CS40L26_DSP1_IRQ14_CONTROL 0x2B80570 |
| #define CS40L26_DSP1_IRQ15_CONTROL 0x2B80578 |
| #define CS40L26_DSP1_IRQ16_CONTROL 0x2B80580 |
| #define CS40L26_DSP1_IRQ17_CONTROL 0x2B80588 |
| #define CS40L26_DSP1_IRQ18_CONTROL 0x2B80590 |
| #define CS40L26_DSP1_IRQ19_CONTROL 0x2B80598 |
| #define CS40L26_DSP1_IRQ20_CONTROL 0x2B805A0 |
| #define CS40L26_DSP1_IRQ21_CONTROL 0x2B805A8 |
| #define CS40L26_DSP1_IRQ22_CONTROL 0x2B805B0 |
| #define CS40L26_DSP1_IRQ23_CONTROL 0x2B805B8 |
| #define CS40L26_DSP1_SCRATCH1 0x2B805C0 |
| #define CS40L26_DSP1_SCRATCH2 0x2B805C8 |
| #define CS40L26_DSP1_SCRATCH3 0x2B805D0 |
| #define CS40L26_DSP1_SCRATCH4 0x2B805D8 |
| #define CS40L26_DSP1_CCM_CORE_CONTROL 0x2BC1000 |
| #define CS40L26_DSP1_CCM_CLK_OVERRIDE 0x2BC1008 |
| #define CS40L26_DSP1_MEM_CTRL_XM_MSTR_EN 0x2BC2000 |
| #define CS40L26_DSP1_MEM_CTRL_XM_CORE_PRIO 0x2BC2008 |
| #define CS40L26_DSP1_MEM_CTRL_XM_PL0_PRIO 0x2BC2010 |
| #define CS40L26_DSP1_MEM_CTRL_XM_PL1_PRIO 0x2BC2018 |
| #define CS40L26_DSP1_MEM_CTRL_XM_PL2_PRIO 0x2BC2020 |
| #define CS40L26_DSP1_MEM_CTRL_XM_NPL0_PRIO 0x2BC2078 |
| #define CS40L26_DSP1_MEM_CTRL_YM_MSTR_EN 0x2BC20C0 |
| #define CS40L26_DSP1_MEM_CTRL_YM_CORE_PRIO 0x2BC20C8 |
| #define CS40L26_DSP1_MEM_CTRL_YM_PL0_PRIO 0x2BC20D0 |
| #define CS40L26_DSP1_MEM_CTRL_YM_PL1_PRIO 0x2BC20D8 |
| #define CS40L26_DSP1_MEM_CTRL_YM_PL2_PRIO 0x2BC20E0 |
| #define CS40L26_DSP1_MEM_CTRL_YM_NPL0_PRIO 0x2BC2138 |
| #define CS40L26_DSP1_MEM_CTRL_PM_MSTR_EN 0x2BC2180 |
| #define CS40L26_DSP1_MEM_CTRL_FIXED_PRIO 0x2BC2184 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH0_ADDR 0x2BC2188 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH0_EN 0x2BC218C |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH0_DATA_LO 0x2BC2190 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH0_DATA_HI 0x2BC2194 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH1_ADDR 0x2BC2198 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH1_EN 0x2BC219C |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH1_DATA_LO 0x2BC21A0 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH1_DATA_HI 0x2BC21A4 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH2_ADDR 0x2BC21A8 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH2_EN 0x2BC21AC |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH2_DATA_LO 0x2BC21B0 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH2_DATA_HI 0x2BC21B4 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH3_ADDR 0x2BC21B8 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH3_EN 0x2BC21BC |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH3_DATA_LO 0x2BC21C0 |
| #define CS40L26_DSP1_MEM_CTRL_PM_PATCH3_DATA_HI 0x2BC21C4 |
| #define CS40L26_DSP1_MPU_XMEM_ACCESS_0 0x2BC3000 |
| #define CS40L26_DSP1_MPU_YMEM_ACCESS_0 0x2BC3004 |
| #define CS40L26_DSP1_MPU_WINDOW_ACCESS_0 0x2BC3008 |
| #define CS40L26_DSP1_MPU_XREG_ACCESS_0 0x2BC300C |
| #define CS40L26_DSP1_MPU_YREG_ACCESS_0 0x2BC3014 |
| #define CS40L26_DSP1_MPU_XMEM_ACCESS_1 0x2BC3018 |
| #define CS40L26_DSP1_MPU_YMEM_ACCESS_1 0x2BC301C |
| #define CS40L26_DSP1_MPU_WINDOW_ACCESS_1 0x2BC3020 |
| #define CS40L26_DSP1_MPU_XREG_ACCESS_1 0x2BC3024 |
| #define CS40L26_DSP1_MPU_YREG_ACCESS_1 0x2BC302C |
| #define CS40L26_DSP1_MPU_XMEM_ACCESS_2 0x2BC3030 |
| #define CS40L26_DSP1_MPU_YMEM_ACCESS_2 0x2BC3034 |
| #define CS40L26_DSP1_MPU_WINDOW_ACCESS_2 0x2BC3038 |
| #define CS40L26_DSP1_MPU_XREG_ACCESS_2 0x2BC303C |
| #define CS40L26_DSP1_MPU_YREG_ACCESS_2 0x2BC3044 |
| #define CS40L26_DSP1_MPU_XMEM_ACCESS_3 0x2BC3048 |
| #define CS40L26_DSP1_MPU_YMEM_ACCESS_3 0x2BC304C |
| #define CS40L26_DSP1_MPU_WINDOW_ACCESS_3 0x2BC3050 |
| #define CS40L26_DSP1_MPU_XREG_ACCESS_3 0x2BC3054 |
| #define CS40L26_DSP1_MPU_YREG_ACCESS_3 0x2BC305C |
| #define CS40L26_DSP1_MPU_X_EXT_MEM_ACCESS_0 0x2BC3060 |
| #define CS40L26_DSP1_MPU_Y_EXT_MEM_ACCESS_0 0x2BC3064 |
| #define CS40L26_DSP1_MPU_XM_VIO_ADDR 0x2BC3100 |
| #define CS40L26_DSP1_MPU_XM_VIO_STATUS 0x2BC3104 |
| #define CS40L26_DSP1_MPU_YM_VIO_ADDR 0x2BC3108 |
| #define CS40L26_DSP1_MPU_YM_VIO_STATUS 0x2BC310C |
| #define CS40L26_DSP1_MPU_PM_VIO_ADDR 0x2BC3110 |
| #define CS40L26_DSP1_MPU_PM_VIO_STATUS 0x2BC3114 |
| #define CS40L26_DSP1_MPU_LOCK_CONFIG 0x2BC3140 |
| #define CS40L26_DSP1_MPU_WDT_RESET_CONTROL 0x2BC3180 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR1_CONFIG_0 0x2BC5000 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR1_CONFIG_1 0x2BC5004 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR1_CONFIG_2 0x2BC5008 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR2_CONFIG_0 0x2BC5010 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR2_CONFIG_1 0x2BC5014 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR2_CONFIG_2 0x2BC5018 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR3_CONFIG_0 0x2BC5020 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR3_CONFIG_1 0x2BC5024 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR3_CONFIG_2 0x2BC5028 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR4_CONFIG_0 0x2BC5030 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR4_CONFIG_1 0x2BC5034 |
| #define CS40L26_DSP1_STREAM_ARB_MSTR4_CONFIG_2 0x2BC5038 |
| #define CS40L26_DSP1_STREAM_ARB_TX1_CONFIG_0 0x2BC5200 |
| #define CS40L26_DSP1_STREAM_ARB_TX1_CONFIG_1 0x2BC5204 |
| #define CS40L26_DSP1_STREAM_ARB_TX2_CONFIG_0 0x2BC5208 |
| #define CS40L26_DSP1_STREAM_ARB_TX2_CONFIG_1 0x2BC520C |
| #define CS40L26_DSP1_STREAM_ARB_TX3_CONFIG_0 0x2BC5210 |
| #define CS40L26_DSP1_STREAM_ARB_TX3_CONFIG_1 0x2BC5214 |
| #define CS40L26_DSP1_STREAM_ARB_TX4_CONFIG_0 0x2BC5218 |
| #define CS40L26_DSP1_STREAM_ARB_TX4_CONFIG_1 0x2BC521C |
| #define CS40L26_DSP1_STREAM_ARB_TX5_CONFIG_0 0x2BC5220 |
| #define CS40L26_DSP1_STREAM_ARB_TX5_CONFIG_1 0x2BC5224 |
| #define CS40L26_DSP1_STREAM_ARB_TX6_CONFIG_0 0x2BC5228 |
| #define CS40L26_DSP1_STREAM_ARB_TX6_CONFIG_1 0x2BC522C |
| #define CS40L26_DSP1_STREAM_ARB_RX1_CONFIG_0 0x2BC5400 |
| #define CS40L26_DSP1_STREAM_ARB_RX1_CONFIG_1 0x2BC5404 |
| #define CS40L26_DSP1_STREAM_ARB_RX2_CONFIG_0 0x2BC5408 |
| #define CS40L26_DSP1_STREAM_ARB_RX2_CONFIG_1 0x2BC540C |
| #define CS40L26_DSP1_STREAM_ARB_RX3_CONFIG_0 0x2BC5410 |
| #define CS40L26_DSP1_STREAM_ARB_RX3_CONFIG_1 0x2BC5414 |
| #define CS40L26_DSP1_STREAM_ARB_RX4_CONFIG_0 0x2BC5418 |
| #define CS40L26_DSP1_STREAM_ARB_RX4_CONFIG_1 0x2BC541C |
| #define CS40L26_DSP1_STREAM_ARB_RX5_CONFIG_0 0x2BC5420 |
| #define CS40L26_DSP1_STREAM_ARB_RX5_CONFIG_1 0x2BC5424 |
| #define CS40L26_DSP1_STREAM_ARB_RX6_CONFIG_0 0x2BC5428 |
| #define CS40L26_DSP1_STREAM_ARB_RX6_CONFIG_1 0x2BC542C |
| #define CS40L26_DSP1_STREAM_ARB_IRQ1_CONFIG_0 0x2BC5600 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ1_CONFIG_1 0x2BC5604 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ1_CONFIG_2 0x2BC5608 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ2_CONFIG_0 0x2BC5610 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ2_CONFIG_1 0x2BC5614 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ2_CONFIG_2 0x2BC5618 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ3_CONFIG_0 0x2BC5620 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ3_CONFIG_1 0x2BC5624 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ3_CONFIG_2 0x2BC5628 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ4_CONFIG_0 0x2BC5630 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ4_CONFIG_1 0x2BC5634 |
| #define CS40L26_DSP1_STREAM_ARB_IRQ4_CONFIG_2 0x2BC5638 |
| #define CS40L26_DSP1_STREAM_ARB_RESYNC_MSK1 0x2BC5A00 |
| #define CS40L26_DSP1_STREAM_ARB_ERR_STATUS 0x2BC5A08 |
| #define CS40L26_DSP1_WDT_CONTROL 0x2BC7000 |
| #define CS40L26_DSP1_WDT_STATUS 0x2BC7008 |
| #define CS40L26_DSP1_ACCEL_DB_IN 0x2BCD000 |
| #define CS40L26_DSP1_ACCEL_LINEAR_OUT 0x2BCD008 |
| #define CS40L26_DSP1_ACCEL_LINEAR_IN 0x2BCD010 |
| #define CS40L26_DSP1_ACCEL_DB_OUT 0x2BCD018 |
| #define CS40L26_DSP1_ACCEL_RAND_NUM 0x2BCD020 |
| #define CS40L26_DSP1_YMEM_PACKED_0 0x2C00000 |
| #define CS40L26_DSP1_YMEM_PACKED_1 0x2C00004 |
| #define CS40L26_DSP1_YMEM_PACKED_2 0x2C00008 |
| #define CS40L26_DSP1_YMEM_PACKED_1530 0x2C017E8 |
| #define CS40L26_DSP1_YMEM_PACKED_1531 0x2C017EC |
| #define CS40L26_DSP1_YMEM_PACKED_1532 0x2C017F0 |
| #define CS40L26_DSP1_YMEM_UNPACKED32_0 0x3000000 |
| #define CS40L26_DSP1_YMEM_UNPACKED32_1 0x3000004 |
| #define CS40L26_DSP1_YMEM_UNPACKED32_1021 0x3000FF4 |
| #define CS40L26_DSP1_YMEM_UNPACKED32_1022 0x3000FF8 |
| #define CS40L26_DSP1_YMEM_UNPACKED24_0 0x3400000 |
| #define CS40L26_DSP1_YMEM_UNPACKED24_1 0x3400004 |
| #define CS40L26_DSP1_YMEM_UNPACKED24_2 0x3400008 |
| #define CS40L26_DSP1_YMEM_UNPACKED24_3 0x340000C |
| #define CS40L26_DSP1_YMEM_UNPACKED24_2042 0x3401FE8 |
| #define CS40L26_DSP1_YMEM_UNPACKED24_2043 0x3401FEC |
| #define CS40L26_DSP1_YMEM_UNPACKED24_2044 0x3401FF0 |
| #define CS40L26_DSP1_YMEM_UNPACKED24_2045 0x3401FF4 |
| #define CS40L26_DSP1_PMEM_0 0x3800000 |
| #define CS40L26_DSP1_PMEM_1 0x3800004 |
| #define CS40L26_DSP1_PMEM_2 0x3800008 |
| #define CS40L26_DSP1_PMEM_3 0x380000C |
| #define CS40L26_DSP1_PMEM_4 0x3800010 |
| #define CS40L26_DSP1_PMEM_5110 0x3804FD8 |
| #define CS40L26_DSP1_PMEM_5111 0x3804FDC |
| #define CS40L26_DSP1_PMEM_5112 0x3804FE0 |
| #define CS40L26_DSP1_PMEM_5113 0x3804FE4 |
| #define CS40L26_DSP1_PMEM_5114 0x3804FE8 |
| #define CS40L26_DSP1_PROM_0 0x3C60000 |
| #define CS40L26_DSP1_PROM_1 0x3C60004 |
| #define CS40L26_DSP1_PROM_2 0x3C60008 |
| #define CS40L26_DSP1_PROM_3 0x3C6000C |
| #define CS40L26_DSP1_PROM_4 0x3C60010 |
| #define CS40L26_DSP1_PROM_30710 0x3C7DFD8 |
| #define CS40L26_DSP1_PROM_30711 0x3C7DFDC |
| #define CS40L26_DSP1_PROM_30712 0x3C7DFE0 |
| #define CS40L26_DSP1_PROM_30713 0x3C7DFE4 |
| #define CS40L26_DSP1_PROM_30714 0x3C7DFE8 |
| |
| #define CS40L26_MAX_I2C_READ_SIZE_WORDS 32 |
| |
| /* Register default changes */ |
| #define CS40L26_TST_DAC_MSM_CONFIG_DEFAULT_CHANGE_VALUE_FULL 0x11330000 |
| #define CS40L26_TST_DAC_MSM_CONFIG_DEFAULT_CHANGE_VALUE_H16 (\ |
| CS40L26_TST_DAC_MSM_CONFIG_DEFAULT_CHANGE_VALUE_FULL >> 16) |
| #define CS40L26_SPK_DEFAULT_HIZ_MASK BIT(28) |
| #define CS40L26_SPK_DEFAULT_HIZ_SHIFT 28 |
| |
| /* Device */ |
| #define CS40L26_DEV_NAME "CS40L26" |
| #define CS40L26_INPUT_DEV_NAME "cs40l26_input" |
| #define CS40L26_DEVID_A 0x40A260 |
| #define CS40L26_DEVID_B 0x40A26B |
| #define CS40L26_DEVID_L27_A 0x40A270 |
| #define CS40L26_DEVID_L27_B 0x40A27B |
| #define CS40L26_DEVID_MASK GENMASK(23, 0) |
| #define CS40L26_NUM_DEVS 4 |
| |
| #define CS40L26_REVID_A1 0xA1 |
| #define CS40L26_REVID_B0 0xB0 |
| #define CS40L26_REVID_B1 0xB1 |
| #define CS40L26_REVID_MASK GENMASK(7, 0) |
| |
| #define CS40L26_GLOBAL_EN_MASK BIT(0) |
| |
| #define CS40L26_DSP_CCM_CORE_KILL 0x00000080 |
| #define CS40L26_DSP_CCM_CORE_RESET 0x00000281 |
| |
| #define CS40L26_GLOBAL_FS_MASK GENMASK(4, 0) |
| #define CS40L26_GLOBAL_FS_48K 0x03 |
| #define CS40L26_GLOBAL_FS_96K 0x04 |
| |
| #define CS40L26_MEM_RDY_MASK BIT(1) |
| #define CS40L26_MEM_RDY_SHIFT 1 |
| |
| #define CS40L26_DSP_HALO_STATE_RUN 2 |
| |
| #define CS40L26_NUM_PCT_MAP_VALUES 101 |
| |
| #define CS40L26_TEST_KEY_UNLOCK_CODE1 0x00000055 |
| #define CS40L26_TEST_KEY_UNLOCK_CODE2 0x000000AA |
| |
| #if IS_ENABLED(CONFIG_GOOG_CUST) |
| /* Reset Recovery */ |
| #define CS40L26_RESET_MAX_COUNT 10 |
| #define CS40L26_RESET_COOLDOWN_TIMEOUT_SEC 300 |
| #endif |
| |
| /* DSP State */ |
| #define CS40L26_DSP_STATE_HIBERNATE 0 |
| #define CS40L26_DSP_STATE_SHUTDOWN 1 |
| #define CS40L26_DSP_STATE_STANDBY 2 |
| #define CS40L26_DSP_STATE_ACTIVE 3 |
| |
| #define CS40L26_DSP_STATE_MASK GENMASK(7, 0) |
| |
| #define CS40L26_DSP_STATE_STR_LEN 10 |
| |
| #define CS40L26_DSP_STATE_ATTEMPTS 5 |
| |
| #define CS40L26_DSP_LOCK3_OFFSET 8 |
| #define CS40L26_DSP_LOCK3_MASK BIT(1) |
| #define CS40L26_DSP_PM_ACTIVE BIT(0) |
| |
| #define CS40L26_DSP_SHUTDOWN_MAX_ATTEMPTS 10 |
| |
| /* ROM Controls A1 */ |
| #define CS40L26_A1_PM_CUR_STATE_STATIC_REG 0x02800370 |
| #define CS40L26_A1_PM_STATE_LOCKS_STATIC_REG 0x02800378 |
| #define CS40L26_A1_PM_TIMEOUT_TICKS_STATIC_REG 0x02800350 |
| #define CS40L26_A1_DSP_HALO_STATE_REG 0x02800fa8 |
| #define CS40L26_A1_DSP_REQ_ACTIVE_REG 0x02800c08 |
| #define CS40L26_A1_EVENT_MAP_1 0x02806FC4 |
| #define CS40L26_A1_EVENT_MAP_2 0x02806FC8 |
| |
| |
| /* algorithms */ |
| #define CS40L26_A2H_ALGO_ID 0x00040110 |
| #define CS40L26_BUZZGEN_ALGO_ID 0x0001F202 |
| #define CS40L26_DYNAMIC_F0_ALGO_ID 0x0001F21B |
| #define CS40L26_EVENT_HANDLER_ALGO_ID 0x0001F200 |
| #define CS40L26_F0_EST_ALGO_ID 0x0001F20C |
| #define CS40L26_GPIO_ALGO_ID 0x0001F201 |
| #define CS40L26_MAILBOX_ALGO_ID 0x0001F203 |
| #define CS40L26_MDSYNC_ALGO_ID 0x0001F20F |
| #define CS40L26_PM_ALGO_ID 0x0001F206 |
| #define CS40L26_SVC_ALGO_ID 0x0001F207 |
| #define CS40L26_VIBEGEN_ALGO_ID 0x000100BD |
| #define CS40L26_LOGGER_ALGO_ID 0x0004013D |
| #define CS40L26_EVENT_LOGGER_ALGO_ID 0x0004F222 |
| #define CS40L26_EXT_ALGO_ID 0x0004013C |
| #define CS40L26_DVL_ALGO_ID 0x00040140 |
| #define CS40L26_LF0T_ALGO_ID 0x00040143 |
| |
| /* DebugFS */ |
| #define CS40L26_ALGO_ID_MAX_STR_LEN 12 |
| #define CS40L26_NUM_DEBUGFS 3 |
| |
| /* power management */ |
| #define CS40L26_PSEQ_ROM_END_OF_SCRIPT 0x028003E8 |
| #define CS40L26_PSEQ_MAX_WORDS_PER_OP CS40L26_PSEQ_OP_WRITE_FIELD_WORDS |
| #define CS40L26_PSEQ_MAX_WORDS 129 |
| #define CS40L26_PSEQ_NUM_OPS 8 |
| #define CS40L26_PSEQ_OP_MASK GENMASK(23, 16) |
| #define CS40L26_PSEQ_OP_SHIFT 16 |
| #define CS40L26_PSEQ_OP_WRITE_FULL 0x00 |
| #define CS40L26_PSEQ_OP_WRITE_FULL_WORDS 3 |
| #define CS40L26_PSEQ_OP_WRITE_FIELD 0x01 |
| #define CS40L26_PSEQ_OP_WRITE_FIELD_WORDS 4 |
| #define CS40L26_PSEQ_OP_WRITE_ADDR8 0x02 |
| #define CS40L26_PSEQ_OP_WRITE_ADDR8_WORDS 2 |
| #define CS40L26_PSEQ_OP_WRITE_INCR 0x03 |
| #define CS40L26_PSEQ_OP_WRITE_INCR_WORDS 2 |
| #define CS40L26_PSEQ_OP_WRITE_L16 0x04 |
| #define CS40L26_PSEQ_OP_WRITE_H16 0x05 |
| #define CS40L26_PSEQ_OP_WRITE_X16_WORDS 2 |
| #define CS40L26_PSEQ_OP_DELAY 0xFE |
| #define CS40L26_PSEQ_OP_DELAY_WORDS 1 |
| #define CS40L26_PSEQ_OP_END 0xFF |
| #define CS40L26_PSEQ_OP_END_WORDS 1 |
| #define CS40L26_PSEQ_OP_END_ADDR 0xFFFFFF |
| #define CS40L26_PSEQ_OP_END_DATA 0xFFFFFF |
| #define CS40L26_PSEQ_INVALID_ADDR 0xFF000000 |
| #define CS40L26_PSEQ_WORD1_MASK 0x00FFFF00 |
| #define CS40L26_PSEQ_WORD2_MASK 0x000000FF |
| #define CS40L26_PSEQ_EQ_MASK 0x00FF0000 |
| #define CS40L26_PSEQ_WRITE_FULL_LOWER_ADDR_SHIFT 8 |
| #define CS40L26_PSEQ_WRITE_FULL_UPPER_ADDR_SHIFT 16 |
| #define CS40L26_PSEQ_WRITE_FULL_LOWER_ADDR_MASK GENMASK(15, 0) |
| #define CS40L26_PSEQ_WRITE_FULL_UPPER_ADDR_MASK GENMASK(31, 0) |
| #define CS40L26_PSEQ_WRITE_FULL_UPPER_DATA_SHIFT 24 |
| #define CS40L26_PSEQ_WRITE_FULL_LOWER_DATA_MASK GENMASK(23, 0) |
| #define CS40L26_PSEQ_WRITE_FULL_UPPER_DATA_MASK GENMASK(31, 24) |
| #define CS40L26_PSEQ_WRITE_FULL_OP_MASK GENMASK(31, 8) |
| #define CS40L26_PSEQ_WRITE_X16_LOWER_ADDR_SHIFT 16 |
| #define CS40L26_PSEQ_WRITE_X16_LOWER_ADDR_MASK GENMASK(7, 0) |
| #define CS40L26_PSEQ_WRITE_X16_UPPER_ADDR_SHIFT 8 |
| #define CS40L26_PSEQ_WRITE_X16_UPPER_ADDR_MASK GENMASK(23, 8) |
| #define CS40L26_PSEQ_WRITE_X16_UPPER_DATA_SHIFT 0 |
| #define CS40L26_PSEQ_WRITE_X16_UPPER_DATA_MASK GENMASK(31, 0) |
| #define CS40L26_PSEQ_WRITE_X16_OP_MASK GENMASK(23, 16) |
| |
| #define CS40L26_PM_STDBY_TIMEOUT_LOWER_OFFSET 16 |
| #define CS40L26_PM_STDBY_TIMEOUT_UPPER_OFFSET 20 |
| #define CS40L26_PM_STDBY_TIMEOUT_MS_DEFAULT 100 |
| #define CS40L26_PM_TIMEOUT_MS_MAX 10000 |
| #define CS40L26_PM_ACTIVE_TIMEOUT_LOWER_OFFSET 24 |
| #define CS40L26_PM_ACTIVE_TIMEOUT_UPPER_OFFSET 28 |
| #define CS40L26_PM_ACTIVE_TIMEOUT_MS_DEFAULT 250 |
| #define CS40L26_PM_TIMEOUT_TICKS_LOWER_MASK GENMASK(23, 0) |
| #define CS40L26_PM_TIMEOUT_TICKS_UPPER_MASK GENMASK(7, 0) |
| #define CS40L26_PM_TIMEOUT_TICKS_UPPER_SHIFT 24 |
| #define CS40L26_PM_TICKS_MS_DIV 32 |
| |
| #define CS40L26_AUTOSUSPEND_DELAY_MS 2000 |
| |
| #define CS40L26_WKSRC_STS_MASK GENMASK(9, 4) |
| #define CS40L26_WKSRC_STS_SHIFT 4 |
| |
| #define CS40L26_WKSRC_GPIO_POL_MASK GENMASK(3, 0) |
| |
| #define CS40L26_IRQ1_WKSRC_MASK GENMASK(14, 9) |
| #define CS40L26_IRQ1_WKSRC_SHIFT 9 |
| #define CS40L26_IRQ1_WKSRC_GPIO_MASK GENMASK(3, 0) |
| |
| #define CS40L26_WKSRC_STS_EN BIT(7) |
| |
| /* DSP mailbox controls */ |
| #define CS40L26_DSP_TIMEOUT_US_MIN 1000 |
| #define CS40L26_DSP_TIMEOUT_US_MAX 1100 |
| #if IS_ENABLED(CONFIG_GOOG_CUST) |
| #define CS40L26_DSP_TIMEOUT_COUNT 3 |
| #else |
| #define CS40L26_DSP_TIMEOUT_COUNT 100 |
| #endif |
| |
| #define CS40L26_DSP_MBOX_RESET 0x0 |
| |
| #define CS40L26_DSP_MBOX_CMD_HIBER 0x02000001 |
| #define CS40L26_DSP_MBOX_CMD_WAKEUP 0x02000002 |
| #define CS40L26_DSP_MBOX_CMD_PREVENT_HIBER 0x02000003 |
| #define CS40L26_DSP_MBOX_CMD_ALLOW_HIBER 0x02000004 |
| #define CS40L26_DSP_MBOX_CMD_SHUTDOWN 0x02000005 |
| #define CS40L26_DSP_MBOX_PM_CMD_BASE CS40L26_DSP_MBOX_CMD_HIBER |
| |
| #define CS40L26_DSP_MBOX_CMD_DURATION_REPORT 0x03000001 |
| #define CS40L26_DSP_MBOX_CMD_START_I2S 0x03000002 |
| #define CS40L26_DSP_MBOX_CMD_STOP_I2S 0x03000003 |
| #define CS40L26_DSP_MBOX_CMD_LOGGER_MAX_RESET 0x03000004 |
| #define CS40L26_DSP_MBOX_CMD_A2H_REINIT 0x03000007 |
| #define CS40L26_DSP_MBOX_CMD_OWT_PUSH 0x03000008 |
| #define CS40L26_DSP_MBOX_CMD_OWT_RESET 0x03000009 |
| |
| #define CS40L26_DSP_MBOX_CMD_LE_EST 0x07000004 |
| |
| #define CS40L26_DSP_MBOX_CMD_OWT_DELETE_BASE 0x0D000000 |
| |
| #define CS40L26_DSP_MBOX_CMD_INDEX_MASK GENMASK(28, 24) |
| #define CS40L26_DSP_MBOX_CMD_INDEX_SHIFT 24 |
| |
| #define CS40L26_DSP_MBOX_CMD_PAYLOAD_MASK GENMASK(23, 0) |
| |
| #define CS40L26_DSP_MBOX_CMD_INDEX_CALIBRATION_CONTROL 0x7 |
| |
| #define CS40L26_DSP_MBOX_BUFFER_NUM_REGS 4 |
| |
| #define CS40L26_DSP_MBOX_COMPLETE_MBOX 0x01000000 |
| #define CS40L26_DSP_MBOX_COMPLETE_GPIO 0x01000001 |
| #define CS40L26_DSP_MBOX_COMPLETE_I2S 0x01000002 |
| #define CS40L26_DSP_MBOX_TRIGGER_CP 0x01000010 |
| #define CS40L26_DSP_MBOX_TRIGGER_GPIO 0x01000011 |
| #define CS40L26_DSP_MBOX_TRIGGER_I2S 0x01000012 |
| #define CS40L26_DSP_MBOX_PM_AWAKE 0x02000002 |
| #define CS40L26_DSP_MBOX_F0_EST_START 0x07000011 |
| #define CS40L26_DSP_MBOX_F0_EST_DONE 0x07000021 |
| #define CS40L26_DSP_MBOX_REDC_EST_START 0x07000012 |
| #define CS40L26_DSP_MBOX_REDC_EST_DONE 0x07000022 |
| #define CS40L26_DSP_MBOX_LE_EST_START 0x07000014 |
| #define CS40L26_DSP_MBOX_LE_EST_DONE 0x07000024 |
| #define CS40L26_DSP_MBOX_PEQ_CALCULATION_START 0x07000018 |
| #define CS40L26_DSP_MBOX_PEQ_CALCULATION_DONE 0x07000028 |
| #define CS40L26_DSP_MBOX_SYS_ACK 0x0A000000 |
| #define CS40L26_DSP_MBOX_PANIC 0x0C000000 |
| #define CS40L26_DSP_MBOX_WATERMARK 0x0D000000 |
| |
| /* Firmware Mode */ |
| #define CS40L26_FW_FILE_NAME "cs40l26.wmfw" |
| #define CS40L26_FW_CALIB_NAME "cs40l26-calib.wmfw" |
| |
| #define CS40L26_MAX_TUNING_FILES 6 |
| |
| #define CS40L26_WT_FILE_NAME "cs40l26.bin" |
| #define CS40L26_WT_FILE_PREFIX "cs40l26-wt" |
| #define CS40L26_WT_FILE_PREFIX_LEN 11 |
| #define CS40L26_SVC_TUNING_FILE_PREFIX "cs40l26-svc" |
| #define CS40L26_SVC_TUNING_FILE_PREFIX_LEN 12 |
| #define CS40L26_SVC_TUNING_FILE_NAME "cs40l26-svc.bin" |
| #define CS40L26_A2H_TUNING_FILE_NAME "cs40l26-a2h.bin" |
| #define CS40L26_TUNING_FILE_NAME_MAX_LEN 20 |
| #define CS40L26_TUNING_FILE_SUFFIX ".bin" |
| #define CS40L26_TUNING_FILE_SUFFIX_LEN 4 |
| #define CS40L26_DVL_FILE_NAME "cs40l26-dvl.bin" |
| #define CS40L26_CALIB_BIN_FILE_NAME "cs40l26-calib.bin" |
| #define CS40L26_LF0T_FILE_NAME "cs40l26-lf0t.bin" |
| |
| #define CS40L26_SVC_LE_EST_TIME_US 8000 |
| #define CS40L26_SVC_LE_MAX_ATTEMPTS 2 |
| #define CS40L26_SVC_DT_PREFIX "svc-le" |
| |
| #define CS40L26_FW_ID 0x1800D4 |
| #define CS40L26_FW_MIN_REV 0x07022B |
| #define CS40L26_FW_BRANCH 0x07 |
| #define CS40L26_FW_CALIB_ID 0x1800DA |
| #define CS40L26_FW_CALIB_MIN_REV 0x010123 |
| #define CS40L26_FW_CALIB_BRANCH 0x01 |
| #define CS40L26_FW_MAINT_MIN_REV 0x270216 |
| #define CS40L26_FW_MAINT_BRANCH 0x27 |
| #define CS40L26_FW_MAINT_CALIB_MIN_REV 0x21010D |
| #define CS40L26_FW_MAINT_CALIB_BRANCH 0x21 |
| #define CS40L26_FW_GPI_TIMEOUT_MIN_REV 0x07022A |
| #define CS40L26_FW_GPI_TIMEOUT_CALIB_MIN_REV 0x010122 |
| #define CS40L26_FW_BRANCH_MASK GENMASK(23, 21) |
| |
| #define CS40L26_CCM_CORE_RESET 0x00000200 |
| #define CS40L26_CCM_CORE_ENABLE 0x00000281 |
| |
| /* wavetable */ |
| #define CS40L26_WT_NAME_XM "WAVE_XM_TABLE" |
| #define CS40L26_WT_NAME_YM "WAVE_YM_TABLE" |
| |
| /* power supplies */ |
| #define CS40L26_VP_SUPPLY 0 |
| #define CS40L26_VA_SUPPLY 1 |
| #define CS40L26_NUM_SUPPLIES 2 |
| #define CS40L26_VP_SUPPLY_NAME "VP" |
| #define CS40L26_VA_SUPPLY_NAME "VA" |
| |
| #define CS40L26_MIN_RESET_PULSE_WIDTH 1500 |
| #define CS40L26_CONTROL_PORT_READY_DELAY 6000 |
| |
| /* haptic triggering */ |
| #define CS40L26_TRIGGER_EFFECT 1 |
| |
| #define CS40L26_STOP_PLAYBACK 0x05000000 |
| |
| #define CS40L26_MAX_INDEX_MASK 0x0000FFFF |
| |
| #define CS40L26_CUSTOM_DATA_SIZE 2 |
| |
| #define CS40L26_RAM_INDEX_START 0x01000000 |
| #define CS40L26_RAM_INDEX_END 0x0100007F |
| |
| #define CS40L26_ROM_INDEX_START 0x01800000 |
| #define CS40L26_ROM_INDEX_END 0x01800026 |
| |
| #define CS40L26_OWT_INDEX_START 0x01400000 |
| #define CS40L26_OWT_INDEX_END 0x01400010 |
| |
| |
| #define CS40L26_RAM_BANK_ID 0 |
| #define CS40L26_ROM_BANK_ID 1 |
| #define CS40L26_OWT_BANK_ID 2 |
| #define CS40L26_BUZ_BANK_ID 3 |
| |
| #define CS40L26_BUZZGEN_CONFIG_OFFSET 12 |
| #define CS40L26_BUZZGEN_NUM_CONFIGS (CS40L26_BUZZGEN_INDEX_END - \ |
| CS40L26_BUZZGEN_INDEX_START) |
| |
| #define CS40L26_BUZZGEN_INDEX_START 0x01800080 |
| #define CS40L26_BUZZGEN_INDEX_CP_TRIGGER 0x01800081 |
| #define CS40L26_BUZZGEN_INDEX_END 0x01800085 |
| |
| #define CS40L26_BUZZGEN_FREQ_MAX 250 /* Hz */ |
| #define CS40L26_BUZZGEN_FREQ_MIN 100 |
| |
| #define CS40L26_BUZZGEN_PER_MAX 10 /* ms */ |
| #define CS40L26_BUZZGEN_PER_MIN 4 |
| |
| #define CS40L26_BUZZGEN_DURATION_OFFSET 8 |
| #define CS40L26_BUZZGEN_DURATION_DIV_STEP 4 |
| |
| #define CS40L26_BUZZGEN_LEVEL_OFFSET 4 |
| #define CS40L26_BUZZGEN_LEVEL_MIN 0x00 |
| #define CS40L26_BUZZGEN_LEVEL_MAX 0xFF |
| |
| #define CS40L26_AMP_CTRL_VOL_PCM_MASK GENMASK(13, 3) |
| #define CS40L26_AMP_CTRL_VOL_PCM_SHIFT 3 |
| |
| #define CS40L26_AMP_VOL_PCM_MAX 0x07FF |
| |
| #define CS40L26_ERASE_BUFFER_MS 500 |
| #define CS40L26_MAX_WAIT_VIBE_COMPLETE_MS 10000 |
| |
| /* GPI Triggering */ |
| #define CS40L26_GPIO1 1 |
| #define CS40L26_EVENT_MAP_INDEX_MASK GENMASK(8, 0) |
| #define CS40L26_EVENT_MAP_NUM_GPI_REGS 4 |
| #define CS40L26_EVENT_MAP_GPI_DISABLE 0x1FF |
| |
| #define CS40L26_BTN_INDEX_MASK GENMASK(7, 0) |
| #define CS40L26_BTN_BUZZ_MASK BIT(7) |
| #define CS40L26_BTN_BUZZ_SHIFT 7 |
| #define CS40L26_BTN_BANK_MASK BIT(8) |
| #define CS40L26_BTN_BANK_SHIFT 8 |
| #define CS40L26_BTN_NUM_MASK GENMASK(14, 12) |
| #define CS40L26_BTN_NUM_SHIFT 12 |
| #define CS40L26_BTN_EDGE_MASK BIT(15) |
| #define CS40L26_BTN_EDGE_SHIFT 15 |
| #define CS40L26_BTN_OWT_MASK BIT(16) |
| #define CS40L26_BTN_OWT_SHIFT 16 |
| |
| /* Interrupts */ |
| #define CS40L26_IRQ_STATUS_DEASSERT 0x0 |
| #define CS40L26_IRQ_STATUS_ASSERT 0x1 |
| |
| #define CS40L26_IRQ_EINT1_ALL_MASK 0xFFDC7FFF |
| #define CS40L26_IRQ_EINT2_ALL_MASK 0x07DE0400 |
| |
| /* temp monitoring */ |
| #define CS40L26_TEMPMON_EN_MASK BIT(10) |
| #define CS40L26_TEMPMON_EN_SHIFT 10 |
| #define CS40L26_TEMP_RESULT_FILT_MASK GENMASK(24, 16) |
| #define CS40L26_TEMP_RESULT_FILT_SHIFT 16 |
| |
| /* BST */ |
| #define CS40L26_BST_DCM_EN_DEFAULT 1 |
| #define CS40L26_BST_DCM_EN_MASK BIT(0) |
| #define CS40L26_BST_DCM_EN_SHIFT 0 |
| |
| #define CS40L26_BST_IPK_MILLIAMP_MAX 4800 |
| #define CS40L26_BST_IPK_MILLIAMP_MIN 1600 |
| #define MILLIAMPS_PER_AMPS 1000 |
| |
| #define CS40L26_BST_VOLT_MIN 2550000 |
| #define CS40L26_BST_VOLT_MAX 11000000 |
| #define CS40L26_BST_CTL_DEFAULT 11000000 |
| #define CS40L26_BST_VOLT_STEP 50000 |
| #define CS40L26_BST_CTL_VP 0x00 |
| #define CS40L26_BST_CTL_MASK GENMASK(7, 0) |
| #define CS40L26_BST_CTL_SHIFT 0 |
| #define CS40L26_BST_CTL_SEL_MASK GENMASK(1, 0) |
| #define CS40L26_BST_CTL_SEL_FIXED 0x0 |
| #define CS40L26_BST_CTL_SEL_CLASS_H 0x1 |
| |
| #define CS40L26_BST_TIME_MIN_US 10000 |
| #define CS40L26_BST_TIME_MAX_US 10100 |
| |
| #define CS40L26_BST_CTL_LIM_EN_MASK BIT(2) |
| #define CS40L26_BST_CTL_LIM_EN_SHIFT 2 |
| |
| #define CS40L26_BST_IPK_DEFAULT 0x4A |
| #define CS40L26_BST_IPK_CTL_STEP_SIZE 50 |
| #define CS40L26_BST_IPK_CTL_RESERVED 16 |
| |
| #define CS40L26_BOOST_DISABLE_DELAY_MIN 0 |
| #define CS40L26_BOOST_DISABLE_DELAY_MAX 8388608 |
| |
| /* brownout prevention */ |
| #define CS40L26_VXBR_DEFAULT 0xFFFFFFFF |
| |
| #define CS40L26_VXBR_STATUS_DIV_STEP 625 |
| #define CS40L26_VXBR_STATUS_MASK GENMASK(7, 0) |
| #define CS40L26_VXBR_STATUS_MUTE_MASK BIT(8) |
| #define CS40L26_VXBR_STATUS_MUTE_SHIFT 8 |
| |
| #define CS40L26_VBBR_EN_MASK BIT(13) |
| #define CS40L26_VBBR_EN_SHIFT 13 |
| |
| #define CS40L26_VBBR_FLAG_MASK BIT(19) |
| #define CS40L26_VBBR_FLAG_SHIFT 19 |
| #define CS40L26_VBBR_ATT_CLR_MASK BIT(20) |
| #define CS40L26_VBBR_ATT_CLR_SHIFT 20 |
| |
| #define CS40L26_VPBR_EN_MASK BIT(12) |
| #define CS40L26_VPBR_EN_SHIFT 12 |
| #define CS40L26_VPBR_THLD_MASK GENMASK(4, 0) |
| |
| #define CS40L26_VPBR_THLD_MIN 0x02 |
| #define CS40L26_VPBR_THLD_MAX 0x1F |
| #define CS40L26_VPBR_THLD_MV_DIV 47 |
| #define CS40L26_VPBR_THLD_OFFSET 51 |
| #define CS40L26_VPBR_THLD_MV_MIN 2497 |
| #define CS40L26_VPBR_THLD_MV_MAX 3874 |
| |
| #define CS40L26_VBBR_THLD_MASK GENMASK(5, 0) |
| #define CS40L26_VBBR_THLD_MIN 0x02 |
| #define CS40L26_VBBR_THLD_MAX 0x3F |
| #define CS40L26_VBBR_THLD_MV_STEP 55 |
| #define CS40L26_VBBR_THLD_MV_MIN 109 |
| #define CS40L26_VBBR_THLD_MV_MAX 3445 |
| |
| #define CS40L26_VXBR_MAX_ATT_MASK GENMASK(11, 8) |
| #define CS40L26_VXBR_MAX_ATT_SHIFT 8 |
| #define CS40L26_VXBR_MAX_ATT_MAX 0xF |
| |
| #define CS40L26_VXBR_ATK_STEP_DIV_DB 1000 |
| #define CS40L26_VXBR_ATK_STEP_MIN_DB 250 |
| #define CS40L26_VXBR_ATK_STEP_MAX_DB 6000 |
| #define CS40L26_VXBR_ATK_STEP_MIN 0x0 |
| #define CS40L26_VXBR_ATK_STEP_MAX 0x7 |
| #define CS40L26_VXBR_ATK_STEP_MASK GENMASK(15, 12) |
| #define CS40L26_VXBR_ATK_STEP_SHIFT 12 |
| #define CS40L26_VXBR_ATK_STEP_OFFSET 1 |
| |
| #define CS40L26_VXBR_ATK_RATE_MIN 0x0 |
| #define CS40L26_VXBR_ATK_RATE_MAX 0x7 |
| #define CS40L26_VXBR_ATK_RATE_MASK GENMASK(18, 16) |
| #define CS40L26_VXBR_ATK_RATE_SHIFT 16 |
| #define CS40L26_VXBR_ATK_RATE_OFFSET 1 |
| |
| #define CS40L26_VXBR_WAIT_MAX 0x3 |
| #define CS40L26_VXBR_WAIT_MASK GENMASK(20, 19) |
| #define CS40L26_VXBR_WAIT_SHIFT 19 |
| |
| #define CS40L26_VXBR_REL_RATE_MAX 0x7 |
| #define CS40L26_VXBR_REL_RATE_MASK GENMASK(23, 21) |
| #define CS40L26_VXBR_REL_RATE_SHIFT 21 |
| |
| /* mixer noise gate */ |
| #define CS40L26_MIXER_NGATE_CH1_CFG_DEFAULT_NEW 0x00010003 |
| |
| /* audio */ |
| #define CS40L26_PLL_CLK_CFG_32768 0x00 |
| #define CS40L26_PLL_CLK_CFG_1536000 0x1B |
| #define CS40L26_PLL_CLK_CFG_3072000 0x21 |
| #define CS40L26_PLL_CLK_CFG_6144000 0x28 |
| #define CS40L26_PLL_CLK_CFG_9600000 0x30 |
| #define CS40L26_PLL_CLK_CFG_12288000 0x33 |
| |
| #define CS40L26_PLL_CLK_FRQ_32768 32768 |
| #define CS40L26_PLL_CLK_FRQ_1536000 1536000 |
| #define CS40L26_PLL_CLK_FRQ_3072000 3072000 |
| #define CS40L26_PLL_CLK_FRQ_6144000 6144000 |
| #define CS40L26_PLL_CLK_FRQ_9600000 9600000 |
| #define CS40L26_PLL_CLK_FRQ_12288000 12288000 |
| |
| #define CS40L26_PLL_CLK_SEL_BCLK 0x0 |
| #define CS40L26_PLL_CLK_SEL_FSYNC 0x1 |
| #define CS40L26_PLL_CLK_SEL_MCLK 0x5 |
| |
| #define CS40L26_PLL_CLK_FREQ_MASK GENMASK(31, 0) |
| #define CS40L26_PLL_CLK_CFG_MASK GENMASK(5, 0) |
| |
| #define CS40L26_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) |
| #define CS40L26_RATES (SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000) |
| |
| #define CS40L26_ASP_RX_WIDTH_MASK GENMASK(31, 24) |
| #define CS40L26_ASP_RX_WIDTH_SHIFT 24 |
| #define CS40L26_ASP_FMT_MASK GENMASK(10, 8) |
| #define CS40L26_ASP_FMT_SHIFT 8 |
| #define CS40L26_ASP_BCLK_INV_MASK BIT(6) |
| #define CS40L26_ASP_BCLK_INV_SHIFT 6 |
| #define CS40L26_ASP_FSYNC_INV_MASK BIT(2) |
| #define CS40L26_ASP_FSYNC_INV_SHIFT 2 |
| |
| #define CS40L26_ASP_FMT_TDM1_DSPA 0x0 |
| #define CS40L26_ASP_FMT_I2S 0x2 |
| #define CS40L26_ASP_FMT_TDM1P5 0x4 |
| |
| #define CS40L26_ASP_START_TIMEOUT 50 /* milliseconds */ |
| |
| #define CS40L26_PLL_REFCLK_BCLK 0x0 |
| #define CS40L26_PLL_REFCLK_FSYNC 0x1 |
| #define CS40L26_PLL_REFCLK_MCLK 0x5 |
| |
| #define CS40L26_PLL_REFCLK_SEL_MASK GENMASK(2, 0) |
| #define CS40L26_PLL_REFCLK_EN_MASK BIT(4) |
| #define CS40L26_PLL_REFCLK_EN_SHIFT 4 |
| #define CS40L26_PLL_REFCLK_FREQ_MASK GENMASK(10, 5) |
| #define CS40L26_PLL_REFCLK_FREQ_SHIFT 5 |
| #define CS40L26_PLL_REFCLK_LOOP_MASK BIT(11) |
| #define CS40L26_PLL_REFCLK_LOOP_SHIFT 11 |
| #define CS40L26_PLL_REFCLK_SET_OPEN_LOOP 1 |
| #define CS40L26_PLL_REFCLK_SET_CLOSED_LOOP 0 |
| #define CS40L26_PLL_REFCLK_SET_ATTEMPTS 5 |
| #define CS40L26_PLL_REFCLK_FORCE_EN_MASK BIT(16) |
| #define CS40L26_PLL_REFCLK_FORCE_EN_SHIFT 16 |
| |
| #define CS40L26_ASP_RX_WL_MASK GENMASK(5, 0) |
| |
| #define CS40L26_DATA_SRC_ZERO_FILL 0x00 |
| #define CS40L26_DATA_SRC_DIAG_GEN 0x04 |
| #define CS40L26_DATA_SRC_ASPRX1 0x08 |
| #define CS40L26_DATA_SRC_ASPRX2 0x09 |
| #define CS40L26_DATA_SRC_ASPRX3 0x0A |
| #define CS40L26_DATA_SRC_VMON 0x18 |
| #define CS40L26_DATA_SRC_IMON 0x19 |
| #define CS40L26_DATA_SRC_VMON_FSX2 0x1A |
| #define CS40L26_DATA_SRC_IMON_FSX2 0x1B |
| #define CS40L26_DATA_SRC_ERR_VOL 0x20 |
| #define CS40L26_DATA_SRC_CLASSH_TGT 0x21 |
| #define CS40L26_DATA_SRC_VPMON 0x28 |
| #define CS40L26_DATA_SRC_VBSTMON 0x29 |
| #define CS40L26_DATA_SRC_BOOST_MON_MUX0 0x30 |
| #define CS40L26_DATA_SRC_BOOST_MON_MUX1 0x31 |
| #define CS40L26_DATA_SRC_DSP1TX1 0x32 |
| #define CS40L26_DATA_SRC_DSP1TX2 0x33 |
| #define CS40L26_DATA_SRC_DSP1TX3 0x34 |
| #define CS40L26_DATA_SRC_DSP1TX4 0x35 |
| #define CS40L26_DATA_SRC_DSP1TX5 0x36 |
| #define CS40L26_DATA_SRC_DSP1TX6 0x37 |
| #define CS40L26_DATA_SRC_TEMP_MON 0x3A |
| #define CS40L26_DATA_SRC_AMP_INTP 0x40 |
| |
| #define CS40L26_DATA_SRC_MASK GENMASK(6, 0) |
| |
| #define CS40L26_ASP_TX1_EN_MASK BIT(0) |
| #define CS40L26_ASP_TX2_EN_MASK BIT(1) |
| #define CS40L26_ASP_TX2_EN_SHIFT 1 |
| #define CS40L26_ASP_TX3_EN_MASK BIT(2) |
| #define CS40L26_ASP_TX3_EN_SHIFT 2 |
| #define CS40L26_ASP_TX4_EN_MASK BIT(3) |
| #define CS40L26_ASP_TX4_EN_SHIFT 3 |
| #define CS40L26_ASP_RX1_EN_MASK BIT(16) |
| #define CS40L26_ASP_RX1_EN_SHIFT 16 |
| #define CS40L26_ASP_RX2_EN_MASK BIT(17) |
| #define CS40L26_ASP_RX2_EN_SHIFT 17 |
| #define CS40L26_ASP_RX3_EN_MASK BIT(18) |
| #define CS40L26_ASP_RX3_EN_SHIFT 18 |
| |
| #define CS40L26_ASP_RX1_SLOT_MASK GENMASK(5, 0) |
| #define CS40L26_ASP_RX2_SLOT_MASK GENMASK(13, 8) |
| #define CS40L26_ASP_RX2_SLOT_SHIFT 8 |
| |
| #define CS40L26_A2H_MAX_TUNINGS 5 |
| |
| #define CS40L26_A2H_LEVEL_MAX 0x7FFFFF |
| #define CS40L26_A2H_LEVEL_MIN 0x000001 |
| |
| #define CS40L26_A2H_DELAY_MAX 0x190 |
| |
| #define CS40L26_VMON_DEC_OUT_DATA_MASK GENMASK(23, 0) |
| #define CS40L26_VMON_OVFL_FLAG_MASK BIT(31) |
| #define CS40L26_VMON_DEC_OUT_DATA_MAX CS40L26_VMON_DEC_OUT_DATA_MASK |
| |
| #define CS40L26_GAIN_FULL_SCALE 100 |
| |
| /* OWT */ |
| #define CS40L26_WT_STR_MAX_LEN 512 |
| #define CS40L26_WT_MAX_SEGS 512 |
| #define CS40L26_WT_MAX_SECTS 256 |
| #define CS40L26_WT_MAX_DELAY 10000 |
| #define CS40L26_WT_MAX_FINITE_REPEAT 32 |
| |
| #define CS40L26_WT_REPEAT_LOOP_MARKER 0xFF |
| #define CS40L26_WT_INDEF_TIME_VAL 0xFFFF |
| #define CS40L26_WT_MAX_TIME_VAL 16383 /* ms */ |
| |
| #define CS40L26_WT_HEADER_OFFSET 3 |
| #define CS40L26_WT_METADATA_OFFSET 3 |
| #define CS40L26_WT_HEADER_DEFAULT_FLAGS 0x0000 |
| #define CS40L26_WT_HEADER_PWLE_SIZE 12 |
| #define CS40L26_WT_HEADER_COMP_SIZE 20 |
| #define CS40L26_WT_SVC_METADATA BIT(10) |
| #define CS40L26_WT_TYPE12_IDENTIFIER 0xC00 |
| |
| #define CS40L26_WT_TYPE10_SECTION_BYTES_MIN 8 |
| #define CS40L26_WT_TYPE10_SECTION_BYTES_MAX 12 |
| #define CS40L26_WT_TYPE10_WAVELEN_MAX 0x3FFFFF |
| #define CS40L26_WT_TYPE10_WAVELEN_INDEF 0x400000 |
| #define CS40L26_WT_TYPE10_WAVELEN_CALCULATED 0x800000 |
| #define CS40L26_WT_TYPE10_COMP_DURATION_FLAG 0x80 |
| #define CS40L26_WT_TYPE10_COMP_BUFFER 0x0000 |
| |
| /* F0 Offset represented as Q10.14 format */ |
| #define CS40L26_F0_OFFSET_MAX 0x190000 /* +100 Hz */ |
| #define CS40L26_F0_OFFSET_MIN 0xE70000 /* -100 Hz */ |
| |
| /* Calibration */ |
| #define CS40L26_F0_EST_MIN 0xC8000 |
| #define CS40L26_F0_EST_MAX 0x7FC000 |
| #define CS40L26_Q_EST_MIN 0 |
| #define CS40L26_Q_EST_MAX 0x7FFFFF |
| |
| #define CS40L26_DVL_PEQ_COEFFICIENTS_NUM_REGS 6 |
| |
| #define CS40L26_F0_EST_FREQ_SCALE 16384 |
| |
| #define CS40L26_SVC_INITIALIZATION_PERIOD_MS 6 |
| #define CS40L26_REDC_CALIBRATION_BUFFER_MS 10 |
| #define CS40L26_F0_AND_Q_CALIBRATION_MIN_MS 100 |
| #define CS40L26_F0_AND_Q_CALIBRATION_MAX_MS 1800 |
| #define CS40L26_F0_CHIRP_DURATION_FACTOR 3750 |
| #define CS40L26_CALIBRATION_CONTROL_REQUEST_F0_AND_Q BIT(0) |
| #define CS40L26_CALIBRATION_CONTROL_REQUEST_REDC BIT(1) |
| #define CS40L26_CALIBRATION_CONTROL_REQUEST_DVL_PEQ BIT(3) |
| #define CS40L26_F0_FREQ_SPAN_MASK GENMASK(23, 0) |
| #define CS40L26_F0_FREQ_SPAN_SIGN BIT(23) |
| |
| #define CS40L26_LOGGER_SRC_SIZE_MASK BIT(22) |
| #define CS40L26_LOGGER_SRC_SIZE_SHIFT 22 |
| #define CS40L26_LOGGER_SRC_ID_MASK GENMASK(19, 16) |
| #define CS40L26_LOGGER_SRC_ID_SHIFT 16 |
| #define CS40L26_LOGGER_SRC_COUNT_CALIB 3 |
| #define CS40L26_LOGGER_SRC_COUNT 1 |
| #define CS40L26_LOGGER_SRC_ID_BEMF 1 |
| #define CS40L26_LOGGER_SRC_ID_VBST 2 |
| #define CS40L26_LOGGER_SRC_ID_VMON 3 |
| #define CS40L26_LOGGER_DATA_1_MIN_OFFSET 0 |
| #define CS40L26_LOGGER_DATA_1_MAX_OFFSET 4 |
| #define CS40L26_LOGGER_DATA_1_MEAN_OFFSET 8 |
| #define CS40L26_LOGGER_DATA_2_MIN_OFFSET 12 |
| #define CS40L26_LOGGER_DATA_2_MAX_OFFSET 16 |
| #define CS40L26_LOGGER_DATA_2_MEAN_OFFSET 20 |
| #define CS40L26_LOGGER_DATA_3_MIN_OFFSET 24 |
| #define CS40L26_LOGGER_DATA_3_MAX_OFFSET 28 |
| #define CS40L26_LOGGER_DATA_3_MEAN_OFFSET 32 |
| |
| #define CS40L26_UINT_24_BITS_MAX 16777215 |
| |
| #define CS40L26_CALIBRATION_TIMEOUT_MS 2000 |
| |
| |
| /* Compensation */ |
| #define CS40L26_COMP_EN_REDC_SHIFT 1 |
| #define CS40L26_COMP_EN_F0_SHIFT 0 |
| |
| /* FW EXT */ |
| #define CS40L26_SVC_EN_MASK BIT(0) |
| |
| /* DBC */ |
| #define CS40L26_DBC_ENABLE_MASK BIT(1) |
| #define CS40L26_DBC_ENABLE_SHIFT 1 |
| #define CS40L26_DBC_TX_LVL_HOLD_OFF_MS_MAX 1000 |
| #define CS40L26_DBC_CONTROLS_MAX 0x7FFFFF |
| #define CS40L26_DBC_ENV_REL_COEF_NAME "DBC_ENV_REL_COEF" |
| #define CS40L26_DBC_RISE_HEADROOM_NAME "DBC_RISE_HEADROOM" |
| #define CS40L26_DBC_FALL_HEADROOM_NAME "DBC_FALL_HEADROOM" |
| #define CS40L26_DBC_TX_LVL_THRESH_FS_NAME "DBC_TX_LVL_THRESH_FS" |
| #define CS40L26_DBC_TX_LVL_HOLD_OFF_MS_NAME "DBC_TX_LVL_HOLD_OFF_MS" |
| #define CS40L26_DBC_USE_DEFAULT 0xFFFFFFFF |
| |
| /* Errata */ |
| #define CS40L26_ERRATA_A1_NUM_WRITES 4 |
| #define CS40L26_ERRATA_A1_EXPL_EN_NUM_WRITES 1 |
| #define CS40L26_PLL_REFCLK_DET_EN 0x00000001 |
| #define CS40L26_DISABLE_EXPL_MODE 0x014DC080 |
| |
| /* MFD */ |
| #define CS40L26_NUM_MFD_DEVS 1 |
| |
| /* macros */ |
| #define CS40L26_OTP_MEM(n) (CS40L26_OTP_MEM0 + \ |
| ((n) * CL_DSP_BYTES_PER_WORD)) |
| |
| #define CS40L26_MS_TO_SECS(n) ((n) / 1000) |
| |
| #define CS40L26_MS_TO_US(n) ((n) * 1000) |
| |
| #define CS40L26_MS_TO_NS(n) ((n) * 1000000) |
| |
| #define CS40L26_MS_TO_HZ(n) (1000 / (n)) |
| |
| #define CS40L26_SAMPS_TO_MS(n) ((n) / 8) |
| |
| /* enums */ |
| enum cs40l26_gpio_map { |
| CS40L26_GPIO_MAP_A_PRESS, |
| CS40L26_GPIO_MAP_A_RELEASE, |
| CS40L26_GPIO_MAP_NUM_AVAILABLE, |
| CS40L26_GPIO_MAP_INVALID, |
| }; |
| |
| enum cs40l26_dbc { |
| CS40L26_DBC_ENV_REL_COEF, /* 0 */ |
| CS40L26_DBC_RISE_HEADROOM, |
| CS40L26_DBC_FALL_HEADROOM, |
| CS40L26_DBC_TX_LVL_THRESH_FS, |
| CS40L26_DBC_TX_LVL_HOLD_OFF_MS, |
| CS40L26_DBC_NUM_CONTROLS, /* 5 */ |
| }; |
| |
| enum cs40l26_vibe_state { |
| CS40L26_VIBE_STATE_STOPPED, |
| CS40L26_VIBE_STATE_HAPTIC, |
| CS40L26_VIBE_STATE_ASP, |
| }; |
| |
| enum cs40l26_vibe_state_event { |
| CS40L26_VIBE_STATE_EVENT_MBOX_PLAYBACK, |
| CS40L26_VIBE_STATE_EVENT_MBOX_COMPLETE, |
| CS40L26_VIBE_STATE_EVENT_GPIO_TRIGGER, |
| CS40L26_VIBE_STATE_EVENT_GPIO_COMPLETE, |
| CS40L26_VIBE_STATE_EVENT_ASP_START, |
| CS40L26_VIBE_STATE_EVENT_ASP_STOP, |
| }; |
| |
| enum cs40l26_err_rls { |
| CS40L26_RSRVD_ERR_RLS,/* 0 */ |
| CS40L26_AMP_SHORT_ERR_RLS,/* 1 */ |
| CS40L26_BST_SHORT_ERR_RLS,/* 2 */ |
| CS40L26_BST_OVP_ERR_RLS,/* 3 */ |
| CS40L26_BST_UVP_ERR_RLS,/* 4 */ |
| CS40L26_TEMP_WARN_ERR_RLS,/* 5 */ |
| CS40L26_TEMP_ERR_RLS,/* 6 */ |
| }; |
| |
| enum cs40l26_irq1 { |
| CS40L26_IRQ1_GPIO1_RISE,/* 0 */ |
| CS40L26_IRQ1_GPIO1_FALL,/* 1 */ |
| CS40L26_IRQ1_GPIO2_RISE,/* 2 */ |
| CS40L26_IRQ1_GPIO2_FALL,/* 3 */ |
| CS40L26_IRQ1_GPIO3_RISE,/* 4 */ |
| CS40L26_IRQ1_GPIO3_FALL,/* 5 */ |
| CS40L26_IRQ1_GPIO4_RISE,/* 6 */ |
| CS40L26_IRQ1_GPIO4_FALL,/* 7 */ |
| CS40L26_IRQ1_WKSRC_STS_ANY,/* 8 */ |
| CS40L26_IRQ1_WKSRC_STS_GPIO1,/* 9 */ |
| CS40L26_IRQ1_WKSRC_STS_GPIO2,/* 10 */ |
| CS40L26_IRQ1_WKSRC_STS_GPIO3,/* 11 */ |
| CS40L26_IRQ1_WKSRC_STS_GPIO4,/* 12 */ |
| CS40L26_IRQ1_WKSRC_STS_SPI,/* 13 */ |
| CS40L26_IRQ1_WKSRC_STS_I2C,/* 14 */ |
| CS40L26_IRQ1_GLOBAL_EN_ASSERT,/* 15 */ |
| CS40L26_IRQ1_PDN_DONE,/* 16 */ |
| CS40L26_IRQ1_PUP_DONE,/* 17 */ |
| CS40L26_IRQ1_BST_OVP_FLAG_RISE,/* 18 */ |
| CS40L26_IRQ1_BST_OVP_FLAG_FALL,/* 19 */ |
| CS40L26_IRQ1_BST_OVP_ERR,/* 20 */ |
| CS40L26_IRQ1_BST_DCM_UVP_ERR,/* 21 */ |
| CS40L26_IRQ1_BST_SHORT_ERR,/* 22 */ |
| CS40L26_IRQ1_BST_IPK_FLAG,/* 23 */ |
| CS40L26_IRQ1_TEMP_WARN_RISE,/* 24 */ |
| CS40L26_IRQ1_TEMP_WARN_FALL,/* 25 */ |
| CS40L26_IRQ1_TEMP_ERR,/* 26 */ |
| CS40L26_IRQ1_AMP_ERR,/* 27 */ |
| CS40L26_IRQ1_DC_WATCHDOG_RISE,/* 28 */ |
| CS40L26_IRQ1_DC_WATCHDOG_FALL,/* 29 */ |
| CS40L26_IRQ1_VIRTUAL1_MBOX_WR,/* 30 */ |
| CS40L26_IRQ1_VIRTUAL2_MBOX_WR,/* 31 */ |
| CS40L26_IRQ1_NUM_IRQS, |
| }; |
| |
| enum cs40l26_irq2 { |
| CS40L26_IRQ2_PLL_LOCK,/* 0 */ |
| CS40L26_IRQ2_PLL_PHASE_LOCK,/* 1 */ |
| CS40L26_IRQ2_PLL_FREQ_LOCK,/* 2 */ |
| CS40L26_IRQ2_PLL_UNLOCK_RISE,/* 3 */ |
| CS40L26_IRQ2_PLL_UNLOCK_FALL,/* 4 */ |
| CS40L26_IRQ2_PLL_READY,/* 5 */ |
| CS40L26_IRQ2_PLL_REFCLK_PRESENT,/* 6 */ |
| CS40L26_IRQ2_REFCLK_MISSING_RISE,/* 7 */ |
| CS40L26_IRQ2_REFCLK_MISSING_FALL,/* 8 */ |
| CS40L26_IRQ2_RESERVED,/* 9 */ |
| CS40L26_IRQ2_ASP_RXSLOT_CFG_ERR,/* 10 */ |
| CS40L26_IRQ2_AUX_NG_CH1_ENTRY,/* 11 */ |
| CS40L26_IRQ2_AUX_NG_CH1_EXIT,/* 12 */ |
| CS40L26_IRQ2_AUX_NG_CH2_ENTRY,/* 13 */ |
| CS40L26_IRQ2_AUX_NG_CH2_EXIT,/* 14 */ |
| CS40L26_IRQ2_AMP_NG_ON_RISE,/* 15 */ |
| CS40L26_IRQ2_AMP_NG_ON_FALL,/* 16 */ |
| CS40L26_IRQ2_VPBR_FLAG,/* 17 */ |
| CS40L26_IRQ2_VPBR_ATT_CLR,/* 18 */ |
| CS40L26_IRQ2_VBBR_FLAG,/* 19 */ |
| CS40L26_IRQ2_VBBR_ATT_CLR,/* 20 */ |
| CS40L26_IRQ2_RESERVED2,/* 21 */ |
| CS40L26_IRQ2_I2C_NACK_ERR,/* 22 */ |
| CS40L26_IRQ2_VPMON_CLIPPED,/* 23 */ |
| CS40L26_IRQ2_VBSTMON_CLIPPED,/* 24 */ |
| CS40L26_IRQ2_VMON_CLIPPED,/* 25 */ |
| CS40L26_IRQ2_IMON_CLIPPED,/* 26 */ |
| CS40L26_IRQ2_NUM_IRQS, |
| }; |
| |
| enum cs40l26_pm_state { |
| CS40L26_PM_STATE_HIBERNATE, |
| CS40L26_PM_STATE_WAKEUP, |
| CS40L26_PM_STATE_PREVENT_HIBERNATE, |
| CS40L26_PM_STATE_ALLOW_HIBERNATE, |
| CS40L26_PM_STATE_SHUTDOWN, |
| }; |
| |
| #if IS_ENABLED(CONFIG_GOOG_CUST) |
| enum cs40l26_reset_event { |
| CS40L26_RESET_EVENT_NONEED, |
| CS40L26_RESET_EVENT_TRIGGER, |
| CS40L26_RESET_EVENT_ONGOING, |
| CS40L26_RESET_EVENT_COOLDOWN, |
| CS40L26_RESET_EVENT_FAILED, |
| }; |
| #endif |
| |
| /* structs */ |
| |
| struct cs40l26_owt_section { |
| u8 flags; |
| u8 repeat; |
| u8 amplitude; |
| u8 index; |
| u16 delay; |
| u16 duration; |
| }; |
| |
| struct cs40l26_pseq_op { |
| u8 size; |
| u16 offset; /* offset in bytes from pseq_base */ |
| u8 operation; |
| u32 *words; |
| struct list_head list; |
| }; |
| |
| struct cs40l26_svc_le { |
| s32 gain_adjust; |
| u32 min; |
| u32 max; |
| u32 n; |
| }; |
| |
| struct cs40l26_platform_data { |
| const char *device_name; |
| bool vbbr_en; |
| u32 vbbr_thld_mv; |
| u32 vbbr_max_att; |
| u32 vbbr_atk_step; |
| u32 vbbr_atk_rate; |
| u32 vbbr_wait; |
| u32 vbbr_rel_rate; |
| bool vpbr_en; |
| u32 vpbr_thld_mv; |
| u32 vpbr_max_att; |
| u32 vpbr_atk_step; |
| u32 vpbr_atk_rate; |
| u32 vpbr_wait; |
| u32 vpbr_rel_rate; |
| bool bst_dcm_en; |
| u32 bst_ipk; |
| u32 asp_scale_pct; |
| u32 pm_active_timeout_ms; |
| u32 pm_stdby_timeout_ms; |
| u32 f0_default; |
| u32 redc_default; |
| u32 q_default; |
| u32 boost_ctl; |
| bool expl_mode_enabled; |
| bool dbc_enable_default; |
| u32 dbc_defaults[CS40L26_DBC_NUM_CONTROLS]; |
| bool pwle_zero_cross; |
| u32 press_idx; |
| u32 release_idx; |
| }; |
| |
| struct cs40l26_uploaded_effect { |
| int id; |
| u32 trigger_index; |
| u16 wvfrm_bank; |
| enum cs40l26_gpio_map mapping; |
| struct list_head list; |
| }; |
| struct cs40l26_private { |
| struct device *dev; |
| struct regmap *regmap; |
| u32 devid : 24; |
| u8 revid; |
| struct mutex lock; |
| struct cs40l26_platform_data pdata; |
| struct gpio_desc *reset_gpio; |
| struct input_dev *input; |
| struct cl_dsp *dsp; |
| struct list_head effect_head; |
| unsigned int cur_index; |
| struct ff_effect *trigger_effect; |
| struct ff_effect upload_effect; |
| struct ff_effect *erase_effect; |
| s16 *raw_custom_data; |
| int raw_custom_data_len; |
| struct work_struct vibe_start_work; |
| struct work_struct vibe_stop_work; |
| struct work_struct set_gain_work; |
| struct work_struct upload_work; |
| struct work_struct erase_work; |
| struct workqueue_struct *vibe_workqueue; |
| int irq; |
| bool vibe_init_success; |
| int pseq_num_ops; |
| u32 pseq_base; |
| struct list_head pseq_op_head; |
| enum cs40l26_pm_state pm_state; |
| u32 fw_id; |
| bool fw_defer; |
| bool fw_loaded; |
| bool calib_fw; |
| enum cs40l26_vibe_state vibe_state; |
| bool vibe_state_reporting; |
| bool pm_ready; |
| bool asp_enable; |
| u8 last_wksrc_pol; |
| u8 wksrc_sts; |
| int num_owt_effects; |
| int cal_requested; |
| u16 gain_pct; |
| u16 gain_tmp; |
| bool scaling_applied; |
| u32 event_map_base; |
| struct cs40l26_svc_le **svc_le_vals; |
| int num_svc_le_vals; |
| u32 delay_before_stop_playback_us; |
| int upload_ret; |
| int erase_ret; |
| int effects_in_flight; |
| bool comp_enable_pend; |
| bool comp_enable_redc; |
| bool comp_enable_f0; |
| struct completion i2s_cont; |
| struct completion erase_cont; |
| struct completion cal_f0_cont; |
| struct completion cal_redc_cont; |
| struct completion cal_dvl_peq_cont; |
| u8 vpbr_thld; |
| unsigned int svc_le_est_stored; |
| u32 *no_wait_ram_indices; |
| ssize_t num_no_wait_ram_indices; |
| #ifdef CONFIG_DEBUG_FS |
| struct dentry *debugfs_root; |
| char *dbg_fw_ctrl_name; |
| u32 dbg_fw_algo_id; |
| bool dbg_fw_ym; |
| struct cl_dsp_debugfs *cl_dsp_db; |
| #endif |
| #if IS_ENABLED(CONFIG_GOOG_CUST) |
| struct work_struct reset_work; |
| enum cs40l26_reset_event reset_event; |
| u8 reset_count; |
| time64_t reset_time_s; |
| time64_t reset_time_e; |
| #endif |
| }; |
| |
| struct cs40l26_codec { |
| struct cs40l26_private *core; |
| struct device *dev; |
| struct regmap *regmap; |
| int sysclk_rate; |
| int tuning; |
| int tuning_prev; |
| char *bin_file; |
| u32 daifmt; |
| int tdm_width; |
| int tdm_slots; |
| int tdm_slot[2]; |
| bool dsp_bypass; |
| }; |
| |
| struct cs40l26_pll_sysclk_config { |
| u32 freq; |
| u8 clk_cfg; |
| }; |
| |
| /* exported function prototypes */ |
| int cs40l26_svc_le_estimate(struct cs40l26_private *cs40l26, unsigned int *le); |
| int cs40l26_set_pll_loop(struct cs40l26_private *cs40l26, |
| unsigned int pll_loop); |
| int cs40l26_dbc_enable(struct cs40l26_private *cs40l26, u32 enable); |
| int cs40l26_dbc_get(struct cs40l26_private *cs40l26, enum cs40l26_dbc dbc, |
| unsigned int *val); |
| int cs40l26_dbc_set(struct cs40l26_private *cs40l26, enum cs40l26_dbc dbc, |
| u32 val); |
| int cs40l26_asp_start(struct cs40l26_private *cs40l26); |
| int cs40l26_get_num_waves(struct cs40l26_private *cs40l26, u32 *num_waves); |
| int cs40l26_fw_swap(struct cs40l26_private *cs40l26, const u32 id); |
| void cs40l26_vibe_state_update(struct cs40l26_private *cs40l26, |
| enum cs40l26_vibe_state_event event); |
| int cs40l26_pm_stdby_timeout_ms_get(struct cs40l26_private *cs40l26, |
| u32 *timeout_ms); |
| int cs40l26_pm_stdby_timeout_ms_set(struct cs40l26_private *cs40l26, |
| u32 timeout_ms); |
| int cs40l26_pm_active_timeout_ms_get(struct cs40l26_private *cs40l26, |
| u32 *timeout_ms); |
| int cs40l26_pm_active_timeout_ms_set(struct cs40l26_private *cs40l26, |
| u32 timeout_ms); |
| int cs40l26_pm_state_transition(struct cs40l26_private *cs40l26, |
| enum cs40l26_pm_state state); |
| int cs40l26_ack_write(struct cs40l26_private *cs40l26, u32 reg, u32 write_val, |
| u32 reset_val); |
| int cs40l26_pm_enter(struct device *dev); |
| void cs40l26_pm_exit(struct device *dev); |
| void cs40l26_resume_error_handle(struct device *dev, int ret); |
| int cs40l26_resume(struct device *dev); |
| int cs40l26_sys_resume(struct device *dev); |
| int cs40l26_sys_resume_noirq(struct device *dev); |
| int cs40l26_suspend(struct device *dev); |
| int cs40l26_sys_suspend(struct device *dev); |
| int cs40l26_sys_suspend_noirq(struct device *dev); |
| int cs40l26_dsp_state_get(struct cs40l26_private *cs40l26, u8 *state); |
| int cs40l26_probe(struct cs40l26_private *cs40l26, |
| struct cs40l26_platform_data *pdata); |
| int cs40l26_remove(struct cs40l26_private *cs40l26); |
| bool cs40l26_precious_reg(struct device *dev, unsigned int ret); |
| bool cs40l26_readable_reg(struct device *dev, unsigned int reg); |
| bool cs40l26_volatile_reg(struct device *dev, unsigned int reg); |
| int cs40l26_pseq_write(struct cs40l26_private *cs40l26, u32 addr, |
| u32 data, bool update, u8 op_code); |
| int cs40l26_copy_f0_est_to_dvl(struct cs40l26_private *cs40l26); |
| |
| /* external tables */ |
| extern struct regulator_bulk_data |
| cs40l26_supplies[CS40L26_NUM_SUPPLIES]; |
| extern const struct dev_pm_ops cs40l26_pm_ops; |
| extern const struct regmap_config cs40l26_regmap; |
| extern const struct mfd_cell cs40l26_devs[CS40L26_NUM_MFD_DEVS]; |
| extern const u8 cs40l26_pseq_op_sizes[CS40L26_PSEQ_NUM_OPS][2]; |
| extern const u32 cs40l26_attn_q21_2_vals[CS40L26_NUM_PCT_MAP_VALUES]; |
| extern const struct reg_sequence |
| cs40l26_a1_errata[CS40L26_ERRATA_A1_NUM_WRITES]; |
| extern const char * const cs40l26_dbc_names[CS40L26_DBC_NUM_CONTROLS]; |
| |
| /* sysfs */ |
| extern struct attribute_group cs40l26_dev_attr_group; |
| extern struct attribute_group cs40l26_dev_attr_cal_group; |
| extern struct attribute_group cs40l26_dev_attr_dbc_group; |
| |
| /* debugfs */ |
| #ifdef CONFIG_DEBUG_FS |
| void cs40l26_debugfs_init(struct cs40l26_private *cs40l26); |
| void cs40l26_debugfs_cleanup(struct cs40l26_private *cs40l26); |
| |
| #endif |
| #if IS_ENABLED(CONFIG_GOOG_CUST) |
| void cs40l26_make_reset_decision(struct cs40l26_private *cs40l26, const char *func); |
| #endif |
| |
| #endif /* __CS40L26_H__ */ |
