blob: 3c2d3a8ed10574d33361485a55299a44f0df79bc [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0
/{
dpe: dpe@E8600000 {
compatible = "hisilicon,hi3660-dpe";
status = "ok";
reg = <0x0 0xE8600000 0x0 0x80000>,
<0x0 0xFFF35000 0 0x1000>,
<0x0 0xFFF0A000 0 0x1000>,
<0x0 0xFFF31000 0 0x1000>,
<0x0 0xE86C0000 0 0x10000>;
interrupts = <0 245 4>;
clocks = <&crg_ctrl HI3660_ACLK_GATE_DSS>,
<&crg_ctrl HI3660_PCLK_GATE_DSS>,
<&crg_ctrl HI3660_CLK_GATE_EDC0>,
<&crg_ctrl HI3660_CLK_GATE_LDI0>,
<&crg_ctrl HI3660_CLK_GATE_LDI1>,
<&sctrl HI3660_CLK_GATE_DSS_AXI_MM>,
<&sctrl HI3660_PCLK_GATE_MMBUF>;
clock-names = "aclk_dss",
"pclk_dss",
"clk_edc0",
"clk_ldi0",
"clk_ldi1",
"clk_dss_axi_mm",
"pclk_mmbuf";
dma-coherent;
port {
dpe_out: endpoint {
remote-endpoint = <&dsi_in>;
};
};
iommu_info {
start-addr = <0x8000>;
size = <0xbfff8000>;
};
};
dsi: dsi@E8601000 {
compatible = "hisilicon,hi3660-dsi";
status = "ok";
reg = <0 0xE8601000 0 0x7F000>,
<0 0xFFF35000 0 0x1000>;
clocks = <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_REF>,
<&crg_ctrl HI3660_CLK_GATE_TXDPHY1_REF>,
<&crg_ctrl HI3660_CLK_GATE_TXDPHY0_CFG>,
<&crg_ctrl HI3660_CLK_GATE_TXDPHY1_CFG>,
<&crg_ctrl HI3660_PCLK_GATE_DSI0>,
<&crg_ctrl HI3660_PCLK_GATE_DSI1>;
clock-names = "clk_txdphy0_ref",
"clk_txdphy1_ref",
"clk_txdphy0_cfg",
"clk_txdphy1_cfg",
"pclk_dsi0",
"pclk_dsi1";
#address-cells = <1>;
#size-cells = <0>;
mux-gpio = <&gpio2 4 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&dpe_out>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsi_out0: endpoint@0 {
reg = <0>;
remote-endpoint = <&adv7533_in>;
};
};
};
};
};