| /* |
| * DHD Bus Module for PCIE |
| * |
| * Copyright (C) 1999-2014, Broadcom Corporation |
| * |
| * Unless you and Broadcom execute a separate written software license |
| * agreement governing use of this software, this software is licensed to you |
| * under the terms of the GNU General Public License version 2 (the "GPL"), |
| * available at http://www.broadcom.com/licenses/GPLv2.php, with the |
| * following added to such license: |
| * |
| * As a special exception, the copyright holders of this software give you |
| * permission to link this software with independent modules, and to copy and |
| * distribute the resulting executable under terms of your choice, provided that |
| * you also meet, for each linked independent module, the terms and conditions of |
| * the license of that module. An independent module is a module which is not |
| * derived from this software. The special exception does not apply to any |
| * modifications of the software. |
| * |
| * Notwithstanding the above, under no circumstances may you combine this |
| * software in any way with any other Broadcom software provided under a license |
| * other than the GPL, without Broadcom's express prior written consent. |
| * |
| * $Id: dhd_pcie.c 477711 2014-05-14 08:45:17Z $ |
| */ |
| |
| |
| /* include files */ |
| #include <typedefs.h> |
| #include <bcmutils.h> |
| #include <bcmdevs.h> |
| #include <siutils.h> |
| #include <hndsoc.h> |
| #include <hndpmu.h> |
| #include <sbchipc.h> |
| #if defined(DHD_DEBUG) |
| #include <hnd_armtrap.h> |
| #include <hnd_cons.h> |
| #endif /* defined(DHD_DEBUG) */ |
| #include <dngl_stats.h> |
| #include <pcie_core.h> |
| #include <dhd.h> |
| #include <dhd_bus.h> |
| #include <dhd_flowring.h> |
| #include <dhd_proto.h> |
| #include <dhd_dbg.h> |
| #include <dhd_debug.h> |
| #include <dhdioctl.h> |
| #include <sdiovar.h> |
| #include <bcmmsgbuf.h> |
| #include <pcicfg.h> |
| #include <dhd_pcie.h> |
| #include <bcmpcie.h> |
| #include <bcmendian.h> |
| #ifdef DHDTCPACK_SUPPRESS |
| #include <dhd_ip.h> |
| #endif /* DHDTCPACK_SUPPRESS */ |
| #include <proto/bcmevent.h> |
| |
| #ifdef BCMEMBEDIMAGE |
| #include BCMEMBEDIMAGE |
| #endif /* BCMEMBEDIMAGE */ |
| |
| #define MEMBLOCK 2048 /* Block size used for downloading of dongle image */ |
| #define MAX_NVRAMBUF_SIZE 6144 /* max nvram buf size */ |
| #define MAX_WKLK_IDLE_CHECK 3 /* times wake_lock checked before deciding not to suspend */ |
| |
| |
| #define ARMCR4REG_BANKIDX (0x40/sizeof(uint32)) |
| #define ARMCR4REG_BANKPDA (0x4C/sizeof(uint32)) |
| /* Temporary war to fix precommit till sync issue between trunk & precommit branch is resolved */ |
| #define DHD_FLOW_RING(dhdp, flowid) \ |
| (flow_ring_node_t *)&(((flow_ring_node_t *)((dhdp)->flow_ring_table))[flowid]) |
| |
| int dhd_dongle_memsize; |
| int dhd_dongle_ramsize; |
| #ifdef DHD_DEBUG |
| static int dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size); |
| static int dhdpcie_bus_readconsole(dhd_bus_t *bus); |
| #endif |
| static int dhdpcie_mem_dump(dhd_bus_t *bus); |
| static void dhdpcie_bus_report_pcie_linkdown(dhd_bus_t *bus); |
| static int dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size); |
| static int dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, |
| const char *name, void *params, |
| int plen, void *arg, int len, int val_size); |
| static int dhdpcie_bus_lpback_req(struct dhd_bus *bus, uint32 intval); |
| static int dhdpcie_bus_dmaxfer_req(struct dhd_bus *bus, |
| uint32 len, uint32 srcdelay, uint32 destdelay); |
| static int dhdpcie_bus_download_state(dhd_bus_t *bus, bool enter); |
| static int _dhdpcie_download_firmware(struct dhd_bus *bus); |
| static int dhdpcie_download_firmware(dhd_bus_t *bus, osl_t *osh); |
| static int dhdpcie_bus_write_vars(dhd_bus_t *bus); |
| static void dhdpcie_bus_process_mailbox_intr(dhd_bus_t *bus, uint32 intstatus); |
| static void dhdpci_bus_read_frames(dhd_bus_t *bus); |
| static int dhdpcie_readshared(dhd_bus_t *bus); |
| static void dhdpcie_init_shared_addr(dhd_bus_t *bus); |
| static bool dhdpcie_dongle_attach(dhd_bus_t *bus); |
| static void dhdpcie_bus_intr_enable(dhd_bus_t *bus); |
| static void dhdpcie_bus_dongle_setmemsize(dhd_bus_t *bus, int mem_size); |
| static void dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh, |
| bool dongle_isolation, bool reset_flag); |
| static void dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh); |
| static int dhdpcie_downloadvars(dhd_bus_t *bus, void *arg, int len); |
| static uint8 dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset); |
| static void dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data); |
| static void dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data); |
| static uint16 dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset); |
| static void dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data); |
| static uint32 dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset); |
| static void dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data); |
| static uint64 dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset); |
| static void dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data); |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| static void dhdpcie_bus_cfg_set_bar1_win(dhd_bus_t *bus, uint32 data); |
| static ulong dhd_bus_cmn_check_offset(dhd_bus_t *bus, ulong offset); |
| #endif |
| static void dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size); |
| static int dhdpcie_cc_nvmshadow(dhd_bus_t *bus, struct bcmstrbuf *b); |
| static void dhdpcie_send_mb_data(dhd_bus_t *bus, uint32 h2d_mb_data); |
| static void dhd_fillup_ring_sharedptr_info(dhd_bus_t *bus, ring_info_t *ring_info); |
| |
| #ifdef BCMEMBEDIMAGE |
| static int dhdpcie_download_code_array(dhd_bus_t *bus); |
| #endif /* BCMEMBEDIMAGE */ |
| extern void dhd_dpc_kill(dhd_pub_t *dhdp); |
| |
| |
| |
| #define PCI_VENDOR_ID_BROADCOM 0x14e4 |
| |
| /* IOVar table */ |
| enum { |
| IOV_INTR = 1, |
| IOV_MEMBYTES, |
| IOV_MEMSIZE, |
| IOV_SET_DOWNLOAD_STATE, |
| IOV_DEVRESET, |
| IOV_VARS, |
| IOV_MSI_SIM, |
| IOV_PCIE_LPBK, |
| IOV_CC_NVMSHADOW, |
| IOV_RAMSIZE, |
| IOV_RAMSTART, |
| IOV_SLEEP_ALLOWED, |
| IOV_PCIE_DMAXFER, |
| IOV_PCIE_SUSPEND, |
| IOV_PCIEREG, |
| IOV_PCIECFGREG, |
| IOV_PCIECOREREG, |
| IOV_PCIESERDESREG, |
| IOV_BAR0_SECWIN_REG, |
| IOV_SBREG, |
| IOV_DONGLEISOLATION, |
| IOV_LTRSLEEPON_UNLOOAD, |
| IOV_RX_METADATALEN, |
| IOV_TX_METADATALEN, |
| IOV_TXP_THRESHOLD, |
| IOV_BUZZZ_DUMP, |
| IOV_DUMP_RINGUPD_BLOCK, |
| IOV_DMA_RINGINDICES, |
| IOV_DB1_FOR_MB, |
| IOV_FLOW_PRIO_MAP |
| }; |
| |
| |
| |
| const bcm_iovar_t dhdpcie_iovars[] = { |
| {"intr", IOV_INTR, 0, IOVT_BOOL, 0 }, |
| {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int) }, |
| {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0 }, |
| {"dwnldstate", IOV_SET_DOWNLOAD_STATE, 0, IOVT_BOOL, 0 }, |
| {"vars", IOV_VARS, 0, IOVT_BUFFER, 0 }, |
| {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0 }, |
| {"pcie_lpbk", IOV_PCIE_LPBK, 0, IOVT_UINT32, 0 }, |
| {"cc_nvmshadow", IOV_CC_NVMSHADOW, 0, IOVT_BUFFER, 0 }, |
| {"ramsize", IOV_RAMSIZE, 0, IOVT_UINT32, 0 }, |
| {"ramstart", IOV_RAMSTART, 0, IOVT_UINT32, 0 }, |
| {"pciereg", IOV_PCIEREG, 0, IOVT_BUFFER, 2 * sizeof(int32) }, |
| {"pciecfgreg", IOV_PCIECFGREG, 0, IOVT_BUFFER, 2 * sizeof(int32) }, |
| {"pciecorereg", IOV_PCIECOREREG, 0, IOVT_BUFFER, 2 * sizeof(int32) }, |
| {"bar0secwinreg", IOV_BAR0_SECWIN_REG, 0, IOVT_BUFFER, 2 * sizeof(int32) }, |
| {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t) }, |
| {"pcie_dmaxfer", IOV_PCIE_DMAXFER, 0, IOVT_BUFFER, 3 * sizeof(int32) }, |
| {"pcie_suspend", IOV_PCIE_SUSPEND, 0, IOVT_UINT32, 0 }, |
| {"sleep_allowed", IOV_SLEEP_ALLOWED, 0, IOVT_BOOL, 0 }, |
| {"dngl_isolation", IOV_DONGLEISOLATION, 0, IOVT_UINT32, 0 }, |
| {"ltrsleep_on_unload", IOV_LTRSLEEPON_UNLOOAD, 0, IOVT_UINT32, 0 }, |
| {"dump_ringupdblk", IOV_DUMP_RINGUPD_BLOCK, 0, IOVT_BUFFER, 0 }, |
| {"dma_ring_indices", IOV_DMA_RINGINDICES, 0, IOVT_UINT32, 0}, |
| {"rx_metadata_len", IOV_RX_METADATALEN, 0, IOVT_UINT32, 0 }, |
| {"tx_metadata_len", IOV_TX_METADATALEN, 0, IOVT_UINT32, 0 }, |
| {"txp_thresh", IOV_TXP_THRESHOLD, 0, IOVT_UINT32, 0 }, |
| {"buzzz_dump", IOV_BUZZZ_DUMP, 0, IOVT_UINT32, 0 }, |
| {"flow_prio_map", IOV_FLOW_PRIO_MAP, 0, IOVT_UINT32, 0 }, |
| {NULL, 0, 0, 0, 0 } |
| }; |
| |
| #define MAX_READ_TIMEOUT 5 * 1000 * 1000 |
| |
| /* Register/Unregister functions are called by the main DHD entry |
| * point (e.g. module insertion) to link with the bus driver, in |
| * order to look for or await the device. |
| */ |
| |
| int |
| dhd_bus_register(void) |
| { |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| |
| return dhdpcie_bus_register(); |
| } |
| |
| void |
| dhd_bus_unregister(void) |
| { |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| |
| dhdpcie_bus_unregister(); |
| return; |
| } |
| |
| |
| /** returns a host virtual address */ |
| uint32 * |
| dhdpcie_bus_reg_map(osl_t *osh, ulong addr, int size) |
| { |
| return (uint32 *)REG_MAP(addr, size); |
| } |
| |
| void |
| dhdpcie_bus_reg_unmap(osl_t *osh, ulong addr, int size) |
| { |
| REG_UNMAP((void*)(uintptr)addr); |
| return; |
| } |
| |
| /** |
| * 'regs' is the host virtual address that maps to the start of the PCIe BAR0 window. The first 4096 |
| * bytes in this window are mapped to the backplane address in the PCIEBAR0Window register. The |
| * precondition is that the PCIEBAR0Window register 'points' at the PCIe core. |
| * |
| * 'tcm' is the *host* virtual address at which tcm is mapped. |
| */ |
| dhd_bus_t* dhdpcie_bus_attach(osl_t *osh, volatile char* regs, volatile char* tcm) |
| { |
| dhd_bus_t *bus; |
| |
| DHD_ERROR(("%s: ENTER\n", __FUNCTION__)); |
| |
| do { |
| if (!(bus = MALLOC(osh, sizeof(dhd_bus_t)))) { |
| DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __FUNCTION__)); |
| break; |
| } |
| bzero(bus, sizeof(dhd_bus_t)); |
| bus->regs = regs; |
| bus->tcm = tcm; |
| bus->osh = osh; |
| |
| dll_init(&bus->const_flowring); |
| |
| /* Attach pcie shared structure */ |
| bus->pcie_sh = MALLOC(osh, sizeof(pciedev_shared_t)); |
| |
| /* dhd_common_init(osh); */ |
| |
| if (dhdpcie_dongle_attach(bus)) { |
| DHD_ERROR(("%s: dhdpcie_probe_attach failed\n", __FUNCTION__)); |
| break; |
| } |
| |
| /* software resources */ |
| if (!(bus->dhd = dhd_attach(osh, bus, PCMSGBUF_HDRLEN))) { |
| DHD_ERROR(("%s: dhd_attach failed\n", __FUNCTION__)); |
| |
| break; |
| } |
| bus->dhd->busstate = DHD_BUS_DOWN; |
| bus->db1_for_mb = TRUE; |
| bus->dhd->hang_report = TRUE; |
| |
| DHD_TRACE(("%s: EXIT SUCCESS\n", |
| __FUNCTION__)); |
| |
| return bus; |
| } while (0); |
| |
| DHD_TRACE(("%s: EXIT FAILURE\n", __FUNCTION__)); |
| |
| return NULL; |
| } |
| |
| uint |
| dhd_bus_chip(struct dhd_bus *bus) |
| { |
| ASSERT(bus->sih != NULL); |
| return bus->sih->chip; |
| } |
| |
| uint |
| dhd_bus_chiprev(struct dhd_bus *bus) |
| { |
| ASSERT(bus); |
| ASSERT(bus->sih != NULL); |
| return bus->sih->chiprev; |
| } |
| |
| void * |
| dhd_bus_pub(struct dhd_bus *bus) |
| { |
| return bus->dhd; |
| } |
| |
| void * |
| dhd_bus_sih(struct dhd_bus *bus) |
| { |
| return (void *)bus->sih; |
| } |
| |
| void * |
| dhd_bus_txq(struct dhd_bus *bus) |
| { |
| return &bus->txq; |
| } |
| |
| /* Get Chip ID version */ |
| uint dhd_bus_chip_id(dhd_pub_t *dhdp) |
| { |
| dhd_bus_t *bus = dhdp->bus; |
| return bus->sih->chip; |
| } |
| |
| /* Get Chip Rev ID version */ |
| uint dhd_bus_chiprev_id(dhd_pub_t *dhdp) |
| { |
| dhd_bus_t *bus = dhdp->bus; |
| return bus->sih->chiprev; |
| } |
| |
| /* Get Chip Pkg ID version */ |
| uint dhd_bus_chippkg_id(dhd_pub_t *dhdp) |
| { |
| dhd_bus_t *bus = dhdp->bus; |
| return bus->sih->chippkg; |
| } |
| |
| |
| /* |
| |
| Name: dhdpcie_bus_isr |
| |
| Parametrs: |
| |
| 1: IN int irq -- interrupt vector |
| 2: IN void *arg -- handle to private data structure |
| |
| Return value: |
| |
| Status (TRUE or FALSE) |
| |
| Description: |
| Interrupt Service routine checks for the status register, |
| disable interrupt and queue DPC if mail box interrupts are raised. |
| */ |
| |
| |
| int32 |
| dhdpcie_bus_isr(dhd_bus_t *bus) |
| { |
| |
| do { |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| /* verify argument */ |
| if (!bus) { |
| DHD_ERROR(("%s : bus is null pointer , exit \n", __FUNCTION__)); |
| break; |
| } |
| |
| if (bus->dhd->busstate == DHD_BUS_DOWN) { |
| DHD_INFO(("%s : bus is down. we have nothing to do\n", |
| __FUNCTION__)); |
| break; |
| } |
| |
| /* Overall operation: |
| * - Mask further interrupts |
| * - Read/ack intstatus |
| * - Take action based on bits and state |
| * - Reenable interrupts (as per state) |
| */ |
| |
| /* Count the interrupt call */ |
| bus->intrcount++; |
| |
| /* read interrupt status register!! Status bits will be cleared in DPC !! */ |
| bus->ipend = TRUE; |
| dhdpcie_bus_intr_disable(bus); /* Disable interrupt!! */ |
| bus->intdis = TRUE; |
| |
| #if defined(PCIE_ISR_THREAD) |
| |
| DHD_TRACE(("Calling dhd_bus_dpc() from %s\n", __FUNCTION__)); |
| DHD_OS_WAKE_LOCK(bus->dhd); |
| while (dhd_bus_dpc(bus)); |
| DHD_OS_WAKE_UNLOCK(bus->dhd); |
| #else |
| bus->dpc_sched = TRUE; |
| dhd_sched_dpc(bus->dhd); /* queue DPC now!! */ |
| #endif /* defined(SDIO_ISR_THREAD) */ |
| |
| DHD_TRACE(("%s: Exit Success DPC Queued\n", __FUNCTION__)); |
| return TRUE; |
| |
| } while (0); |
| |
| DHD_TRACE(("%s: Exit Failure\n", __FUNCTION__)); |
| return FALSE; |
| } |
| |
| static bool |
| dhdpcie_dongle_attach(dhd_bus_t *bus) |
| { |
| |
| osl_t *osh = bus->osh; |
| void *regsva = (void*)bus->regs; |
| uint16 devid = bus->cl_devid; |
| uint32 val; |
| sbpcieregs_t *sbpcieregs; |
| |
| DHD_TRACE(("%s: ENTER\n", |
| __FUNCTION__)); |
| |
| bus->alp_only = TRUE; |
| bus->sih = NULL; |
| |
| /* Set bar0 window to si_enum_base */ |
| dhdpcie_bus_cfg_set_bar0_win(bus, SI_ENUM_BASE); |
| |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| /* Read bar1 window */ |
| bus->bar1_win_base = OSL_PCI_READ_CONFIG(bus->osh, PCI_BAR1_WIN, 4); |
| DHD_ERROR(("%s: PCI_BAR1_WIN = %x\n", __FUNCTION__, bus->bar1_win_base)); |
| #endif |
| |
| /* si_attach() will provide an SI handle and scan the backplane */ |
| if (!(bus->sih = si_attach((uint)devid, osh, regsva, PCI_BUS, bus, |
| &bus->vars, &bus->varsz))) { |
| DHD_ERROR(("%s: si_attach failed!\n", __FUNCTION__)); |
| goto fail; |
| } |
| |
| |
| si_setcore(bus->sih, PCIE2_CORE_ID, 0); |
| sbpcieregs = (sbpcieregs_t*)(bus->regs); |
| |
| /* WAR where the BAR1 window may not be sized properly */ |
| W_REG(osh, &sbpcieregs->configaddr, 0x4e0); |
| val = R_REG(osh, &sbpcieregs->configdata); |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| bus->bar1_win_mask = 0xffffffff - (bus->tcm_size - 1); |
| DHD_ERROR(("%s: BAR1 window val=%d mask=%x\n", __FUNCTION__, val, bus->bar1_win_mask)); |
| #endif |
| W_REG(osh, &sbpcieregs->configdata, val); |
| |
| /* Get info on the ARM and SOCRAM cores... */ |
| /* Should really be qualified by device id */ |
| if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) || |
| (si_setcore(bus->sih, ARMCM3_CORE_ID, 0)) || |
| (si_setcore(bus->sih, ARMCR4_CORE_ID, 0))) { |
| bus->armrev = si_corerev(bus->sih); |
| } else { |
| DHD_ERROR(("%s: failed to find ARM core!\n", __FUNCTION__)); |
| goto fail; |
| } |
| |
| if (!si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { |
| if (!(bus->orig_ramsize = si_socram_size(bus->sih))) { |
| DHD_ERROR(("%s: failed to find SOCRAM memory!\n", __FUNCTION__)); |
| goto fail; |
| } |
| } else { |
| /* cr4 has a different way to find the RAM size from TCM's */ |
| if (!(bus->orig_ramsize = si_tcm_size(bus->sih))) { |
| DHD_ERROR(("%s: failed to find CR4-TCM memory!\n", __FUNCTION__)); |
| goto fail; |
| } |
| /* also populate base address */ |
| switch ((uint16)bus->sih->chip) { |
| case BCM4339_CHIP_ID: |
| case BCM4335_CHIP_ID: |
| bus->dongle_ram_base = CR4_4335_RAM_BASE; |
| break; |
| case BCM4358_CHIP_ID: |
| case BCM4356_CHIP_ID: |
| case BCM4354_CHIP_ID: |
| case BCM43569_CHIP_ID: |
| case BCM4350_CHIP_ID: |
| case BCM43570_CHIP_ID: |
| bus->dongle_ram_base = CR4_4350_RAM_BASE; |
| break; |
| case BCM4360_CHIP_ID: |
| bus->dongle_ram_base = CR4_4360_RAM_BASE; |
| break; |
| case BCM4345_CHIP_ID: |
| bus->dongle_ram_base = CR4_4345_RAM_BASE; |
| break; |
| case BCM43602_CHIP_ID: |
| bus->dongle_ram_base = CR4_43602_RAM_BASE; |
| break; |
| case BCM4349_CHIP_GRPID: |
| bus->dongle_ram_base = CR4_4349_RAM_BASE; |
| break; |
| default: |
| bus->dongle_ram_base = 0; |
| DHD_ERROR(("%s: WARNING: Using default ram base at 0x%x\n", |
| __FUNCTION__, bus->dongle_ram_base)); |
| } |
| } |
| bus->ramsize = bus->orig_ramsize; |
| if (dhd_dongle_memsize) |
| dhdpcie_bus_dongle_setmemsize(bus, dhd_dongle_memsize); |
| |
| DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d) at 0x%x\n", |
| bus->ramsize, bus->orig_ramsize, bus->dongle_ram_base)); |
| |
| bus->srmemsize = si_socram_srmem_size(bus->sih); |
| |
| |
| bus->def_intmask = PCIE_MB_D2H_MB_MASK | PCIE_MB_TOPCIE_FN0_0 | PCIE_MB_TOPCIE_FN0_1; |
| |
| /* Set the poll and/or interrupt flags */ |
| bus->intr = (bool)dhd_intr; |
| |
| bus->wait_for_d3_ack = 1; |
| bus->suspended = FALSE; |
| DHD_TRACE(("%s: EXIT: SUCCESS\n", |
| __FUNCTION__)); |
| return 0; |
| |
| fail: |
| if (bus->sih != NULL) |
| si_detach(bus->sih); |
| DHD_TRACE(("%s: EXIT: FAILURE\n", |
| __FUNCTION__)); |
| return -1; |
| } |
| |
| int |
| dhpcie_bus_unmask_interrupt(dhd_bus_t *bus) |
| { |
| dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, I_MB); |
| return 0; |
| } |
| int |
| dhpcie_bus_mask_interrupt(dhd_bus_t *bus) |
| { |
| dhdpcie_bus_cfg_write_dword(bus, PCIIntmask, 4, 0x0); |
| return 0; |
| } |
| |
| void |
| dhdpcie_bus_intr_enable(dhd_bus_t *bus) |
| { |
| DHD_TRACE(("enable interrupts\n")); |
| if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || |
| (bus->sih->buscorerev == 4)) { |
| dhpcie_bus_unmask_interrupt(bus); |
| } |
| else if (bus->sih) { |
| si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, |
| bus->def_intmask, bus->def_intmask); |
| } |
| } |
| |
| void |
| dhdpcie_bus_intr_disable(dhd_bus_t *bus) |
| { |
| |
| DHD_TRACE(("%s Enter\n", __FUNCTION__)); |
| |
| if (bus) { |
| |
| if ((bus->sih->buscorerev == 2) || (bus->sih->buscorerev == 6) || |
| (bus->sih->buscorerev == 4)) { |
| dhpcie_bus_mask_interrupt(bus); |
| } |
| else if (bus->sih) { |
| si_corereg(bus->sih, bus->sih->buscoreidx, PCIMailBoxMask, |
| bus->def_intmask, 0); |
| } |
| } |
| DHD_TRACE(("%s Exit\n", __FUNCTION__)); |
| } |
| |
| |
| /* Detach and free everything */ |
| void |
| dhdpcie_bus_release(dhd_bus_t *bus) |
| { |
| bool dongle_isolation = FALSE; |
| osl_t *osh = NULL; |
| |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| |
| if (bus) { |
| |
| osh = bus->osh; |
| ASSERT(osh); |
| |
| if (bus->dhd) { |
| dongle_isolation = bus->dhd->dongle_isolation; |
| |
| if (bus->intr) { |
| if (bus->dhd->dongle_reset == FALSE) |
| dhdpcie_bus_intr_disable(bus); |
| dhdpcie_free_irq(bus); |
| } |
| /* Disable tasklet, already scheduled tasklet may be executed even though dongle has been released */ |
| dhd_dpc_kill(bus->dhd); |
| dhd_detach(bus->dhd); |
| dhdpcie_bus_release_dongle(bus, osh, dongle_isolation, TRUE); |
| dhd_free(bus->dhd); |
| bus->dhd = NULL; |
| } |
| |
| /* unmap the regs and tcm here!! */ |
| if (bus->regs) { |
| dhdpcie_bus_reg_unmap(osh, (ulong)bus->regs, DONGLE_REG_MAP_SIZE); |
| bus->regs = NULL; |
| } |
| if (bus->tcm) { |
| dhdpcie_bus_reg_unmap(osh, (ulong)bus->tcm, DONGLE_TCM_MAP_SIZE); |
| bus->tcm = NULL; |
| } |
| |
| dhdpcie_bus_release_malloc(bus, osh); |
| /* Detach pcie shared structure */ |
| if (bus->pcie_sh) |
| MFREE(osh, bus->pcie_sh, sizeof(pciedev_shared_t)); |
| |
| #ifdef DHD_DEBUG |
| |
| if (bus->console.buf != NULL) |
| MFREE(osh, bus->console.buf, bus->console.bufsize); |
| #endif |
| |
| |
| /* Finally free bus info */ |
| MFREE(osh, bus, sizeof(dhd_bus_t)); |
| |
| } |
| |
| DHD_TRACE(("%s: Exit\n", __FUNCTION__)); |
| |
| } |
| |
| |
| void |
| dhdpcie_bus_release_dongle(dhd_bus_t *bus, osl_t *osh, bool dongle_isolation, bool reset_flag) |
| { |
| |
| DHD_TRACE(("%s Enter\n", __FUNCTION__)); |
| |
| DHD_TRACE(("%s: Enter bus->dhd %p bus->dhd->dongle_reset %d \n", __FUNCTION__, |
| bus->dhd, bus->dhd->dongle_reset)); |
| |
| if ((bus->dhd && bus->dhd->dongle_reset) && reset_flag) { |
| DHD_TRACE(("%s Exit\n", __FUNCTION__)); |
| return; |
| } |
| |
| if (bus->sih) { |
| |
| if (!dongle_isolation) |
| pcie_watchdog_reset(bus->osh, bus->sih, (sbpcieregs_t *)(bus->regs)); |
| |
| if (bus->ltrsleep_on_unload) { |
| si_corereg(bus->sih, bus->sih->buscoreidx, |
| OFFSETOF(sbpcieregs_t, u.pcie2.ltr_state), ~0, 0); |
| } |
| si_detach(bus->sih); |
| if (bus->vars && bus->varsz) |
| MFREE(osh, bus->vars, bus->varsz); |
| bus->vars = NULL; |
| } |
| |
| DHD_TRACE(("%s Exit\n", __FUNCTION__)); |
| } |
| |
| uint32 |
| dhdpcie_bus_cfg_read_dword(dhd_bus_t *bus, uint32 addr, uint32 size) |
| { |
| uint32 data = OSL_PCI_READ_CONFIG(bus->osh, addr, size); |
| return data; |
| } |
| |
| /* 32 bit config write */ |
| void |
| dhdpcie_bus_cfg_write_dword(dhd_bus_t *bus, uint32 addr, uint32 size, uint32 data) |
| { |
| OSL_PCI_WRITE_CONFIG(bus->osh, addr, size, data); |
| } |
| |
| void |
| dhdpcie_bus_cfg_set_bar0_win(dhd_bus_t *bus, uint32 data) |
| { |
| OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR0_WIN, 4, data); |
| } |
| |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| void |
| dhdpcie_bus_cfg_set_bar1_win(dhd_bus_t *bus, uint32 data) |
| { |
| OSL_PCI_WRITE_CONFIG(bus->osh, PCI_BAR1_WIN, 4, data); |
| } |
| #endif |
| |
| void |
| dhdpcie_bus_dongle_setmemsize(struct dhd_bus *bus, int mem_size) |
| { |
| int32 min_size = DONGLE_MIN_MEMSIZE; |
| /* Restrict the memsize to user specified limit */ |
| DHD_ERROR(("user: Restrict the dongle ram size to %d, min accepted %d\n", |
| dhd_dongle_memsize, min_size)); |
| if ((dhd_dongle_memsize > min_size) && |
| (dhd_dongle_memsize < (int32)bus->orig_ramsize)) |
| bus->ramsize = dhd_dongle_memsize; |
| } |
| |
| void |
| dhdpcie_bus_release_malloc(dhd_bus_t *bus, osl_t *osh) |
| { |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| |
| if (bus->dhd && bus->dhd->dongle_reset) |
| return; |
| |
| if (bus->vars && bus->varsz) { |
| MFREE(osh, bus->vars, bus->varsz); |
| bus->vars = NULL; |
| } |
| |
| DHD_TRACE(("%s: Exit\n", __FUNCTION__)); |
| return; |
| |
| } |
| |
| /* Stop bus module: clear pending frames, disable data flow */ |
| void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex) |
| { |
| uint32 status; |
| |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| |
| if (!bus->dhd) |
| return; |
| |
| if(bus->dhd->busstate == DHD_BUS_DOWN) { |
| DHD_ERROR(("%s: already down by net_dev_reset\n",__FUNCTION__)); |
| goto done; |
| } |
| bus->dhd->busstate = DHD_BUS_DOWN; |
| dhdpcie_bus_intr_disable(bus); |
| status = dhdpcie_bus_cfg_read_dword(bus, PCIIntstatus, 4); |
| dhdpcie_bus_cfg_write_dword(bus, PCIIntstatus, 4, status); |
| if (!dhd_download_fw_on_driverload) |
| dhd_dpc_kill(bus->dhd); |
| |
| /* Clear rx control and wake any waiters */ |
| bus->rxlen = 0; |
| dhd_os_ioctl_resp_wake(bus->dhd); |
| done: |
| |
| return; |
| } |
| |
| /* Watchdog timer function */ |
| bool dhd_bus_watchdog(dhd_pub_t *dhd) |
| { |
| #ifdef DHD_DEBUG |
| dhd_bus_t *bus; |
| bus = dhd->bus; |
| |
| dhd_os_sdlock(bus->dhd); |
| |
| if (!dhd->up) |
| goto wd_end; |
| |
| /* Poll for console output periodically */ |
| if (dhd->busstate == DHD_BUS_DATA && dhd_console_ms != 0) { |
| bus->console.count += dhd_watchdog_ms; |
| if (bus->console.count >= dhd_console_ms) { |
| bus->console.count -= dhd_console_ms; |
| /* Make sure backplane clock is on */ |
| if (dhdpcie_bus_readconsole(bus) < 0) |
| dhd_console_ms = 0; /* On error, stop trying */ |
| } |
| } |
| wd_end: |
| dhd_os_sdunlock(bus->dhd); |
| #endif /* DHD_DEBUG */ |
| |
| return FALSE; |
| } |
| |
| /* Download firmware image and nvram image */ |
| int |
| dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh, |
| char *pfw_path, char *pnv_path) |
| { |
| int ret; |
| |
| bus->fw_path = pfw_path; |
| bus->nv_path = pnv_path; |
| |
| ret = dhdpcie_download_firmware(bus, osh); |
| |
| return ret; |
| } |
| |
| static int |
| dhdpcie_download_firmware(struct dhd_bus *bus, osl_t *osh) |
| { |
| int ret = 0; |
| |
| DHD_OS_WAKE_LOCK(bus->dhd); |
| |
| ret = _dhdpcie_download_firmware(bus); |
| |
| DHD_OS_WAKE_UNLOCK(bus->dhd); |
| return ret; |
| } |
| |
| static int |
| dhdpcie_download_code_file(struct dhd_bus *bus, char *pfw_path) |
| { |
| int bcmerror = -1; |
| int offset = 0; |
| int len; |
| void *image = NULL; |
| uint8 *memblock = NULL, *memptr; |
| |
| DHD_ERROR(("%s: download firmware %s\n", __FUNCTION__, pfw_path)); |
| |
| /* Should succeed in opening image if it is actually given through registry |
| * entry or in module param. |
| */ |
| image = dhd_os_open_image(pfw_path); |
| if (image == NULL) |
| goto err; |
| |
| memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN); |
| if (memblock == NULL) { |
| DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK)); |
| goto err; |
| } |
| if ((uint32)(uintptr)memblock % DHD_SDALIGN) |
| memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN)); |
| |
| /* Download image */ |
| while ((len = dhd_os_get_image_block((char*)memptr, MEMBLOCK, image))) { |
| if (len < 0) { |
| DHD_ERROR(("%s: dhd_os_get_image_block failed (%d)\n", __FUNCTION__, len)); |
| bcmerror = BCME_ERROR; |
| goto err; |
| } |
| /* check if CR4 */ |
| if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { |
| /* if address is 0, store the reset instruction to be written in 0 */ |
| |
| if (offset == 0) { |
| bus->resetinstr = *(((uint32*)memptr)); |
| /* Add start of RAM address to the address given by user */ |
| offset += bus->dongle_ram_base; |
| } |
| } |
| |
| bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, memptr, len); |
| if (bcmerror) { |
| DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", |
| __FUNCTION__, bcmerror, MEMBLOCK, offset)); |
| goto err; |
| } |
| |
| offset += MEMBLOCK; |
| } |
| |
| err: |
| if (memblock) |
| MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN); |
| |
| if (image) |
| dhd_os_close_image(image); |
| |
| return bcmerror; |
| } |
| |
| |
| static int |
| dhdpcie_download_nvram(struct dhd_bus *bus) |
| { |
| int bcmerror = -1; |
| uint len; |
| void * image = NULL; |
| char * memblock = NULL; |
| char *bufp; |
| char *pnv_path; |
| bool nvram_file_exists; |
| |
| pnv_path = bus->nv_path; |
| |
| nvram_file_exists = ((pnv_path != NULL) && (pnv_path[0] != '\0')); |
| if (!nvram_file_exists && (bus->nvram_params == NULL)) |
| return (0); |
| |
| if (nvram_file_exists) { |
| image = dhd_os_open_image(pnv_path); |
| if (image == NULL) |
| goto err; |
| } |
| |
| memblock = MALLOC(bus->dhd->osh, MAX_NVRAMBUF_SIZE); |
| if (memblock == NULL) { |
| DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", |
| __FUNCTION__, MAX_NVRAMBUF_SIZE)); |
| goto err; |
| } |
| |
| /* Download variables */ |
| if (nvram_file_exists) { |
| len = dhd_os_get_image_block(memblock, MAX_NVRAMBUF_SIZE, image); |
| } |
| else { |
| |
| /* nvram is string with null terminated. cannot use strlen */ |
| len = bus->nvram_params_len; |
| ASSERT(len <= MAX_NVRAMBUF_SIZE); |
| memcpy(memblock, bus->nvram_params, len); |
| } |
| if (len > 0 && len < MAX_NVRAMBUF_SIZE) { |
| bufp = (char *)memblock; |
| bufp[len] = 0; |
| |
| if (nvram_file_exists) |
| len = process_nvram_vars(bufp, len); |
| |
| if (len % 4) { |
| len += 4 - (len % 4); |
| } |
| bufp += len; |
| *bufp++ = 0; |
| if (len) |
| bcmerror = dhdpcie_downloadvars(bus, memblock, len + 1); |
| if (bcmerror) { |
| DHD_ERROR(("%s: error downloading vars: %d\n", |
| __FUNCTION__, bcmerror)); |
| } |
| } |
| else { |
| DHD_ERROR(("%s: error reading nvram file: %d\n", |
| __FUNCTION__, len)); |
| bcmerror = BCME_ERROR; |
| } |
| |
| err: |
| if (memblock) |
| MFREE(bus->dhd->osh, memblock, MAX_NVRAMBUF_SIZE); |
| |
| if (image) |
| dhd_os_close_image(image); |
| |
| return bcmerror; |
| } |
| |
| |
| #ifdef BCMEMBEDIMAGE |
| int |
| dhdpcie_download_code_array(struct dhd_bus *bus) |
| { |
| int bcmerror = -1; |
| int offset = 0; |
| unsigned char *p_dlarray = NULL; |
| unsigned int dlarray_size = 0; |
| unsigned int downloded_len, remaining_len, len; |
| char *p_dlimagename, *p_dlimagever, *p_dlimagedate; |
| uint8 *memblock = NULL, *memptr; |
| |
| downloded_len = 0; |
| remaining_len = 0; |
| len = 0; |
| |
| p_dlarray = dlarray; |
| dlarray_size = sizeof(dlarray); |
| p_dlimagename = dlimagename; |
| p_dlimagever = dlimagever; |
| p_dlimagedate = dlimagedate; |
| |
| if ((p_dlarray == 0) || (dlarray_size == 0) ||(dlarray_size > bus->ramsize) || |
| (p_dlimagename == 0) || (p_dlimagever == 0) || (p_dlimagedate == 0)) |
| goto err; |
| |
| memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN); |
| if (memblock == NULL) { |
| DHD_ERROR(("%s: Failed to allocate memory %d bytes\n", __FUNCTION__, MEMBLOCK)); |
| goto err; |
| } |
| if ((uint32)(uintptr)memblock % DHD_SDALIGN) |
| memptr += (DHD_SDALIGN - ((uint32)(uintptr)memblock % DHD_SDALIGN)); |
| |
| while (downloded_len < dlarray_size) { |
| remaining_len = dlarray_size - downloded_len; |
| if (remaining_len >= MEMBLOCK) |
| len = MEMBLOCK; |
| else |
| len = remaining_len; |
| |
| memcpy(memptr, (p_dlarray + downloded_len), len); |
| /* check if CR4 */ |
| if (si_setcore(bus->sih, ARMCR4_CORE_ID, 0)) { |
| /* if address is 0, store the reset instruction to be written in 0 */ |
| if (offset == 0) { |
| bus->resetinstr = *(((uint32*)memptr)); |
| /* Add start of RAM address to the address given by user */ |
| offset += bus->dongle_ram_base; |
| } |
| } |
| bcmerror = dhdpcie_bus_membytes(bus, TRUE, offset, (uint8 *)memptr, len); |
| downloded_len += len; |
| if (bcmerror) { |
| DHD_ERROR(("%s: error %d on writing %d membytes at 0x%08x\n", |
| __FUNCTION__, bcmerror, MEMBLOCK, offset)); |
| goto err; |
| } |
| offset += MEMBLOCK; |
| } |
| |
| #ifdef DHD_DEBUG |
| /* Upload and compare the downloaded code */ |
| { |
| unsigned char *ularray = NULL; |
| unsigned int uploded_len; |
| uploded_len = 0; |
| bcmerror = -1; |
| ularray = MALLOC(bus->dhd->osh, dlarray_size); |
| if (ularray == NULL) |
| goto upload_err; |
| /* Upload image to verify downloaded contents. */ |
| offset = bus->dongle_ram_base; |
| memset(ularray, 0xaa, dlarray_size); |
| while (uploded_len < dlarray_size) { |
| remaining_len = dlarray_size - uploded_len; |
| if (remaining_len >= MEMBLOCK) |
| len = MEMBLOCK; |
| else |
| len = remaining_len; |
| bcmerror = dhdpcie_bus_membytes(bus, FALSE, offset, |
| (uint8 *)(ularray + uploded_len), len); |
| if (bcmerror) { |
| DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n", |
| __FUNCTION__, bcmerror, MEMBLOCK, offset)); |
| goto upload_err; |
| } |
| |
| uploded_len += len; |
| offset += MEMBLOCK; |
| } |
| |
| if (memcmp(p_dlarray, ularray, dlarray_size)) { |
| DHD_ERROR(("%s: Downloaded image is corrupted (%s, %s, %s).\n", |
| __FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate)); |
| goto upload_err; |
| |
| } else |
| DHD_ERROR(("%s: Download, Upload and compare succeeded (%s, %s, %s).\n", |
| __FUNCTION__, p_dlimagename, p_dlimagever, p_dlimagedate)); |
| upload_err: |
| if (ularray) |
| MFREE(bus->dhd->osh, ularray, dlarray_size); |
| } |
| #endif /* DHD_DEBUG */ |
| err: |
| |
| if (memblock) |
| MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN); |
| |
| return bcmerror; |
| } |
| #endif /* BCMEMBEDIMAGE */ |
| |
| |
| static int |
| _dhdpcie_download_firmware(struct dhd_bus *bus) |
| { |
| int bcmerror = -1; |
| dhd_pub_t *dhd = bus->dhd; |
| bool embed = FALSE; /* download embedded firmware */ |
| bool dlok = FALSE; /* download firmware succeeded */ |
| |
| /* Out immediately if no image to download */ |
| if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) { |
| #ifdef BCMEMBEDIMAGE |
| embed = TRUE; |
| #else |
| DHD_ERROR(("%s: no fimrware file\n", __FUNCTION__)); |
| return 0; |
| #endif |
| } |
| |
| /* Keep arm in reset */ |
| if (dhdpcie_bus_download_state(bus, TRUE)) { |
| DHD_ERROR(("%s: error placing ARM core in reset\n", __FUNCTION__)); |
| goto err; |
| } |
| |
| /* External image takes precedence if specified */ |
| if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) { |
| if (dhdpcie_download_code_file(bus, bus->fw_path)) { |
| DHD_ERROR(("%s: dongle image file download failed\n", __FUNCTION__)); |
| #ifdef BCMEMBEDIMAGE |
| embed = TRUE; |
| #else |
| goto err; |
| #endif |
| } |
| else { |
| embed = FALSE; |
| dlok = TRUE; |
| } |
| } |
| |
| #ifdef BCMEMBEDIMAGE |
| if (embed) { |
| if (dhdpcie_download_code_array(bus)) { |
| DHD_ERROR(("%s: dongle image array download failed\n", __FUNCTION__)); |
| goto err; |
| } |
| else { |
| dlok = TRUE; |
| } |
| } |
| #else |
| BCM_REFERENCE(embed); |
| #endif |
| if (!dlok) { |
| DHD_ERROR(("%s: dongle image download failed\n", __FUNCTION__)); |
| goto err; |
| } |
| |
| /* EXAMPLE: nvram_array */ |
| /* If a valid nvram_arry is specified as above, it can be passed down to dongle */ |
| /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */ |
| |
| |
| /* External nvram takes precedence if specified */ |
| if (dhdpcie_download_nvram(bus)) { |
| DHD_ERROR(("%s: dongle nvram file download failed\n", __FUNCTION__)); |
| goto err; |
| } |
| |
| /* Take arm out of reset */ |
| if (dhdpcie_bus_download_state(bus, FALSE)) { |
| DHD_ERROR(("%s: error getting out of ARM core reset\n", __FUNCTION__)); |
| goto err; |
| } |
| if (dhd) { |
| if (!dhd->soc_ram) { |
| dhd->soc_ram = MALLOC(dhd->osh, bus->ramsize); |
| dhd->soc_ram_length = bus->ramsize; |
| } else { |
| memset(dhd->soc_ram, 0, dhd->soc_ram_length); |
| } |
| } |
| bcmerror = 0; |
| err: |
| return bcmerror; |
| } |
| |
| int dhd_bus_rxctl(struct dhd_bus *bus, uchar *msg, uint msglen) |
| { |
| int timeleft; |
| uint rxlen = 0; |
| bool pending; |
| |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| |
| if (bus->dhd->dongle_reset) |
| return -EIO; |
| |
| /* Wait until control frame is available */ |
| timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending); |
| if (timeleft == 0) { |
| DHD_ERROR(("%s: resumed on timeout\n", __FUNCTION__)); |
| bus->ioct_resp.cmn_hdr.request_id = 0; |
| bus->ioct_resp.compl_hdr.status = 0xffff; |
| bus->rxlen = 0; |
| } |
| rxlen = bus->rxlen; |
| bcopy(&bus->ioct_resp, msg, sizeof(ioctl_comp_resp_msg_t)); |
| bus->rxlen = 0; |
| |
| if (rxlen) { |
| DHD_CTL(("%s: resumed on rxctl frame, got %d\n", __FUNCTION__, rxlen)); |
| } else if (timeleft == 0) { |
| DHD_ERROR(("%s: resumed on timeout\n", __FUNCTION__)); |
| } else if (pending == TRUE) { |
| DHD_CTL(("%s: canceled\n", __FUNCTION__)); |
| return -ERESTARTSYS; |
| } else { |
| DHD_CTL(("%s: resumed for unknown reason?\n", __FUNCTION__)); |
| } |
| if (timeleft == 0) { |
| bus->dhd->rxcnt_timeout++; |
| DHD_ERROR(("%s: rxcnt_timeout=%d\n", __FUNCTION__, bus->dhd->rxcnt_timeout)); |
| } |
| else |
| bus->dhd->rxcnt_timeout = 0; |
| |
| if (rxlen) |
| bus->dhd->rx_ctlpkts++; |
| else |
| bus->dhd->rx_ctlerrs++; |
| |
| if (bus->dhd->rxcnt_timeout >= MAX_CNTL_TX_TIMEOUT) { |
| #ifdef MSM_PCIE_LINKDOWN_RECOVERY |
| bus->islinkdown = TRUE; |
| DHD_ERROR(("PCIe link down\n")); |
| #endif /* SUPPORT_LINKDOWN_RECOVERY */ |
| return -ETIMEDOUT; |
| } |
| if (bus->dhd->dongle_trap_occured) |
| return -EREMOTEIO; |
| |
| return rxlen ? (int)rxlen : -EIO; |
| |
| } |
| |
| #define CONSOLE_LINE_MAX 192 |
| |
| #ifdef DHD_DEBUG |
| static int |
| dhdpcie_bus_readconsole(dhd_bus_t *bus) |
| { |
| dhd_console_t *c = &bus->console; |
| uint8 line[CONSOLE_LINE_MAX], ch; |
| uint32 n, idx, addr; |
| int rv; |
| |
| /* Don't do anything until FWREADY updates console address */ |
| if (bus->console_addr == 0) |
| return -1; |
| |
| /* Read console log struct */ |
| addr = bus->console_addr + OFFSETOF(hnd_cons_t, log); |
| |
| if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, (uint8 *)&c->log, sizeof(c->log))) < 0) |
| return rv; |
| |
| /* Allocate console buffer (one time only) */ |
| if (c->buf == NULL) { |
| c->bufsize = ltoh32(c->log.buf_size); |
| if ((c->buf = MALLOC(bus->dhd->osh, c->bufsize)) == NULL) |
| return BCME_NOMEM; |
| } |
| idx = ltoh32(c->log.idx); |
| |
| /* Protect against corrupt value */ |
| if (idx > c->bufsize) |
| return BCME_ERROR; |
| |
| /* Skip reading the console buffer if the index pointer has not moved */ |
| if (idx == c->last) |
| return BCME_OK; |
| |
| /* Read the console buffer */ |
| addr = ltoh32(c->log.buf); |
| if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, c->buf, c->bufsize)) < 0) |
| return rv; |
| |
| while (c->last != idx) { |
| for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { |
| if (c->last == idx) { |
| /* This would output a partial line. Instead, back up |
| * the buffer pointer and output this line next time around. |
| */ |
| if (c->last >= n) |
| c->last -= n; |
| else |
| c->last = c->bufsize - n; |
| goto break2; |
| } |
| ch = c->buf[c->last]; |
| c->last = (c->last + 1) % c->bufsize; |
| if (ch == '\n') |
| break; |
| line[n] = ch; |
| } |
| |
| if (n > 0) { |
| if (line[n - 1] == '\r') |
| n--; |
| line[n] = 0; |
| printf("CONSOLE: %s\n", line); |
| } |
| } |
| break2: |
| |
| return BCME_OK; |
| } |
| |
| static int |
| dhdpcie_checkdied(dhd_bus_t *bus, char *data, uint size) |
| { |
| int bcmerror = 0; |
| uint msize = 512; |
| char *mbuffer = NULL; |
| char *console_buffer = NULL; |
| uint maxstrlen = 256; |
| char *str = NULL; |
| trap_t tr; |
| pciedev_shared_t *pciedev_shared = bus->pcie_sh; |
| struct bcmstrbuf strbuf; |
| uint32 console_ptr, console_size, console_index; |
| uint8 line[CONSOLE_LINE_MAX], ch; |
| uint32 n, i, addr; |
| int rv; |
| |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| |
| if (DHD_NOCHECKDIED_ON()) |
| return 0; |
| |
| if (data == NULL) { |
| /* |
| * Called after a rx ctrl timeout. "data" is NULL. |
| * allocate memory to trace the trap or assert. |
| */ |
| size = msize; |
| mbuffer = data = MALLOC(bus->dhd->osh, msize); |
| |
| if (mbuffer == NULL) { |
| DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, msize)); |
| bcmerror = BCME_NOMEM; |
| goto done; |
| } |
| } |
| |
| if ((str = MALLOC(bus->dhd->osh, maxstrlen)) == NULL) { |
| DHD_ERROR(("%s: MALLOC(%d) failed \n", __FUNCTION__, maxstrlen)); |
| bcmerror = BCME_NOMEM; |
| goto done; |
| } |
| |
| if ((bcmerror = dhdpcie_readshared(bus)) < 0) |
| goto done; |
| |
| bcm_binit(&strbuf, data, size); |
| |
| bcm_bprintf(&strbuf, "msgtrace address : 0x%08X\nconsole address : 0x%08X\n", |
| pciedev_shared->msgtrace_addr, pciedev_shared->console_addr); |
| |
| if ((pciedev_shared->flags & PCIE_SHARED_ASSERT_BUILT) == 0) { |
| /* NOTE: Misspelled assert is intentional - DO NOT FIX. |
| * (Avoids conflict with real asserts for programmatic parsing of output.) |
| */ |
| bcm_bprintf(&strbuf, "Assrt not built in dongle\n"); |
| } |
| |
| if ((bus->pcie_sh->flags & (PCIE_SHARED_ASSERT|PCIE_SHARED_TRAP)) == 0) { |
| /* NOTE: Misspelled assert is intentional - DO NOT FIX. |
| * (Avoids conflict with real asserts for programmatic parsing of output.) |
| */ |
| bcm_bprintf(&strbuf, "No trap%s in dongle", |
| (bus->pcie_sh->flags & PCIE_SHARED_ASSERT_BUILT) |
| ?"/assrt" :""); |
| } else { |
| if (bus->pcie_sh->flags & PCIE_SHARED_ASSERT) { |
| /* Download assert */ |
| bcm_bprintf(&strbuf, "Dongle assert"); |
| if (bus->pcie_sh->assert_exp_addr != 0) { |
| str[0] = '\0'; |
| if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, |
| bus->pcie_sh->assert_exp_addr, |
| (uint8 *)str, maxstrlen)) < 0) |
| goto done; |
| |
| str[maxstrlen - 1] = '\0'; |
| bcm_bprintf(&strbuf, " expr \"%s\"", str); |
| } |
| |
| if (bus->pcie_sh->assert_file_addr != 0) { |
| str[0] = '\0'; |
| if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, |
| bus->pcie_sh->assert_file_addr, |
| (uint8 *)str, maxstrlen)) < 0) |
| goto done; |
| |
| str[maxstrlen - 1] = '\0'; |
| bcm_bprintf(&strbuf, " file \"%s\"", str); |
| } |
| |
| bcm_bprintf(&strbuf, " line %d ", bus->pcie_sh->assert_line); |
| } |
| |
| if (bus->pcie_sh->flags & PCIE_SHARED_TRAP) { |
| bus->dhd->dongle_trap_occured = TRUE; |
| if ((bcmerror = dhdpcie_bus_membytes(bus, FALSE, |
| bus->pcie_sh->trap_addr, |
| (uint8*)&tr, sizeof(trap_t))) < 0) |
| goto done; |
| |
| bcm_bprintf(&strbuf, |
| "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x," |
| "lp 0x%x, rpc 0x%x Trap offset 0x%x, " |
| "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, " |
| "r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n\n", |
| ltoh32(tr.type), ltoh32(tr.epc), ltoh32(tr.cpsr), ltoh32(tr.spsr), |
| ltoh32(tr.r13), ltoh32(tr.r14), ltoh32(tr.pc), |
| ltoh32(bus->pcie_sh->trap_addr), |
| ltoh32(tr.r0), ltoh32(tr.r1), ltoh32(tr.r2), ltoh32(tr.r3), |
| ltoh32(tr.r4), ltoh32(tr.r5), ltoh32(tr.r6), ltoh32(tr.r7)); |
| |
| addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log); |
| if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, |
| (uint8 *)&console_ptr, sizeof(console_ptr))) < 0) |
| goto printbuf; |
| |
| addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.buf_size); |
| if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, |
| (uint8 *)&console_size, sizeof(console_size))) < 0) |
| goto printbuf; |
| |
| addr = bus->pcie_sh->console_addr + OFFSETOF(hnd_cons_t, log.idx); |
| if ((rv = dhdpcie_bus_membytes(bus, FALSE, addr, |
| (uint8 *)&console_index, sizeof(console_index))) < 0) |
| goto printbuf; |
| |
| console_ptr = ltoh32(console_ptr); |
| console_size = ltoh32(console_size); |
| console_index = ltoh32(console_index); |
| |
| if (console_size > CONSOLE_BUFFER_MAX || |
| !(console_buffer = MALLOC(bus->dhd->osh, console_size))) |
| goto printbuf; |
| |
| if ((rv = dhdpcie_bus_membytes(bus, FALSE, console_ptr, |
| (uint8 *)console_buffer, console_size)) < 0) |
| goto printbuf; |
| |
| for (i = 0, n = 0; i < console_size; i += n + 1) { |
| for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { |
| ch = console_buffer[(console_index + i + n) % console_size]; |
| if (ch == '\n') |
| break; |
| line[n] = ch; |
| } |
| |
| if (n > 0) { |
| if (line[n - 1] == '\r') |
| n--; |
| line[n] = 0; |
| /* Don't use DHD_ERROR macro since we print |
| * a lot of information quickly. The macro |
| * will truncate a lot of the printfs |
| */ |
| |
| if (dhd_msg_level & DHD_ERROR_VAL) |
| printf("CONSOLE: %s\n", line); |
| } |
| } |
| } |
| } |
| |
| printbuf: |
| if (bus->pcie_sh->flags & (PCIE_SHARED_ASSERT | PCIE_SHARED_TRAP)) { |
| DHD_ERROR(("%s: %s\n", __FUNCTION__, strbuf.origbuf)); |
| } |
| /* save core dump or write to a file */ |
| if (bus->dhd->memdump_enabled) { |
| dhdpcie_mem_dump(bus); |
| dhd_dbg_send_urgent_evt(bus->dhd, NULL, 0); |
| } |
| |
| done: |
| if (mbuffer) |
| MFREE(bus->dhd->osh, mbuffer, msize); |
| if (str) |
| MFREE(bus->dhd->osh, str, maxstrlen); |
| |
| if (console_buffer) |
| MFREE(bus->dhd->osh, console_buffer, console_size); |
| |
| return bcmerror; |
| } |
| #endif /* DHD_DEBUG */ |
| static void |
| dhdpcie_bus_report_pcie_linkdown(dhd_bus_t *bus) |
| { |
| if (bus == NULL) |
| return; |
| #ifdef MSM_PCIE_LINKDOWN_RECOVERY |
| bus->islinkdown = TRUE; |
| DHD_ERROR(("PCIe link down, Device ID and Vendor ID are 0x%x\n", |
| dhdpcie_bus_cfg_read_dword(bus, PCI_VENDOR_ID, 4))); |
| dhd_os_send_hang_message(bus->dhd); |
| #endif /* SUPPORT_LINKDOWN_RECOVERY */ |
| } |
| static int |
| dhdpcie_mem_dump(dhd_bus_t *bus) |
| { |
| int ret = BCME_OK; |
| int size; /* Full mem size */ |
| int start = bus->dongle_ram_base; /* Start address */ |
| int read_size = 0; /* Read size of each iteration */ |
| uint8 *databuf = NULL; |
| dhd_pub_t *dhd = bus->dhd; |
| if (!dhd->soc_ram) { |
| DHD_ERROR(("%s : dhd->soc_ram is NULL\n", __FUNCTION__)); |
| return -1; |
| } |
| size = dhd->soc_ram_length = bus->ramsize; |
| |
| /* Read mem content */ |
| databuf = dhd->soc_ram; |
| while (size) { |
| read_size = MIN(MEMBLOCK, size); |
| if ((ret = dhdpcie_bus_membytes(bus, FALSE, start, databuf, read_size))) { |
| DHD_ERROR(("%s: Error membytes %d\n", __FUNCTION__, ret)); |
| return BCME_ERROR; |
| } |
| DHD_TRACE((".")); |
| |
| /* Decrement size and increment start address */ |
| size -= read_size; |
| start += read_size; |
| databuf += read_size; |
| } |
| |
| |
| dhd_save_fwdump(bus->dhd, dhd->soc_ram, dhd->soc_ram_length); |
| dhd_schedule_memdump(bus->dhd, dhd->soc_ram, dhd->soc_ram_length); |
| |
| return ret; |
| } |
| |
| int |
| dhd_socram_dump(dhd_bus_t *bus) |
| { |
| return (dhdpcie_mem_dump(bus)); |
| } |
| |
| |
| /** |
| * Transfers bytes from host to dongle using pio mode. |
| * Parameter 'address' is a backplane address. |
| */ |
| static int |
| dhdpcie_bus_membytes(dhd_bus_t *bus, bool write, ulong address, uint8 *data, uint size) |
| { |
| int bcmerror = 0; |
| uint dsize; |
| int detect_endian_flag = 0x01; |
| bool little_endian; |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| bool is_64bit_unaligned; |
| #endif |
| |
| /* Detect endianness. */ |
| little_endian = *(char *)&detect_endian_flag; |
| |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| /* Check 64bit aligned or not. */ |
| is_64bit_unaligned = (address & 0x7); |
| #endif |
| /* In remap mode, adjust address beyond socram and redirect |
| * to devram at SOCDEVRAM_BP_ADDR since remap address > orig_ramsize |
| * is not backplane accessible |
| */ |
| |
| /* Determine initial transfer parameters */ |
| dsize = sizeof(uint64); |
| |
| /* Do the transfer(s) */ |
| if (write) { |
| while (size) { |
| if (size >= sizeof(uint64) && little_endian) { |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| if (is_64bit_unaligned) { |
| DHD_INFO(("%s: write unaligned %lx\n", |
| __FUNCTION__, address)); |
| dhdpcie_bus_wtcm32(bus, address, *((uint32 *)data)); |
| data += 4; |
| size -= 4; |
| address += 4; |
| is_64bit_unaligned = (address & 0x7); |
| continue; |
| } |
| else |
| #endif |
| dhdpcie_bus_wtcm64(bus, address, *((uint64 *)data)); |
| } else { |
| dsize = sizeof(uint8); |
| dhdpcie_bus_wtcm8(bus, address, *data); |
| } |
| |
| /* Adjust for next transfer (if any) */ |
| if ((size -= dsize)) { |
| data += dsize; |
| address += dsize; |
| } |
| } |
| } else { |
| while (size) { |
| if (size >= sizeof(uint64) && little_endian) { |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| if (is_64bit_unaligned) { |
| DHD_INFO(("%s: read unaligned %lx\n", |
| __FUNCTION__, address)); |
| *(uint32 *)data = dhdpcie_bus_rtcm32(bus, address); |
| data += 4; |
| size -= 4; |
| address += 4; |
| is_64bit_unaligned = (address & 0x7); |
| continue; |
| } |
| else |
| #endif |
| *(uint64 *)data = dhdpcie_bus_rtcm64(bus, address); |
| } else { |
| dsize = sizeof(uint8); |
| *data = dhdpcie_bus_rtcm8(bus, address); |
| } |
| |
| /* Adjust for next transfer (if any) */ |
| if ((size -= dsize) > 0) { |
| data += dsize; |
| address += dsize; |
| } |
| } |
| } |
| return bcmerror; |
| } |
| |
| int BCMFASTPATH |
| dhd_bus_schedule_queue(struct dhd_bus *bus, uint16 flow_id, bool txs) |
| { |
| flow_ring_node_t *flow_ring_node; |
| int ret = BCME_OK; |
| |
| DHD_INFO(("%s: flow_id is %d\n", __FUNCTION__, flow_id)); |
| /* ASSERT on flow_id */ |
| if (flow_id >= bus->max_sub_queues) { |
| DHD_ERROR(("%s: flow_id is invalid %d, max %d\n", __FUNCTION__, |
| flow_id, bus->max_sub_queues)); |
| return 0; |
| } |
| |
| flow_ring_node = DHD_FLOW_RING(bus->dhd, flow_id); |
| |
| { |
| unsigned long flags; |
| void *txp = NULL; |
| flow_queue_t *queue; |
| |
| queue = &flow_ring_node->queue; /* queue associated with flow ring */ |
| |
| DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); |
| |
| if (flow_ring_node->status != FLOW_RING_STATUS_OPEN) { |
| DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); |
| return BCME_NOTREADY; |
| } |
| |
| while ((txp = dhd_flow_queue_dequeue(bus->dhd, queue)) != NULL) { |
| #ifdef DHDTCPACK_SUPPRESS |
| dhd_tcpack_check_xmit(bus->dhd, txp); |
| #endif /* DHDTCPACK_SUPPRESS */ |
| /* Attempt to transfer packet over flow ring */ |
| |
| ret = dhd_prot_txdata(bus->dhd, txp, flow_ring_node->flow_info.ifindex); |
| if (ret != BCME_OK) { /* may not have resources in flow ring */ |
| DHD_INFO(("%s: Reinserrt %d\n", __FUNCTION__, ret)); |
| dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE); |
| /* reinsert at head */ |
| dhd_flow_queue_reinsert(bus->dhd, queue, txp); |
| DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); |
| |
| /* If we are able to requeue back, return success */ |
| return BCME_OK; |
| } |
| } |
| |
| dhd_prot_txdata_write_flush(bus->dhd, flow_id, FALSE); |
| |
| DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); |
| } |
| |
| return ret; |
| } |
| |
| /* Send a data frame to the dongle. Callee disposes of txp. */ |
| int BCMFASTPATH |
| dhd_bus_txdata(struct dhd_bus *bus, void *txp, uint8 ifidx) |
| { |
| unsigned long flags; |
| int ret = BCME_OK; |
| void *txp_pend = NULL; |
| if (!bus->txmode_push) { |
| uint16 flowid; |
| flow_queue_t *queue; |
| flow_ring_node_t *flow_ring_node; |
| if (!bus->dhd->flowid_allocator) { |
| DHD_ERROR(("%s: Flow ring not intited yet \n", __FUNCTION__)); |
| goto toss; |
| } |
| |
| flowid = DHD_PKTTAG_FLOWID((dhd_pkttag_fr_t*)PKTTAG(txp)); |
| |
| flow_ring_node = DHD_FLOW_RING(bus->dhd, flowid); |
| |
| DHD_TRACE(("%s: pkt flowid %d, status %d active %d\n", |
| __FUNCTION__, flowid, flow_ring_node->status, |
| flow_ring_node->active)); |
| |
| if ((flowid >= bus->dhd->num_flow_rings) || |
| (!flow_ring_node->active) || |
| (flow_ring_node->status == FLOW_RING_STATUS_DELETE_PENDING)) { |
| DHD_INFO(("%s: Dropping pkt flowid %d, status %d active %d\n", |
| __FUNCTION__, flowid, flow_ring_node->status, |
| flow_ring_node->active)); |
| ret = BCME_ERROR; |
| goto toss; |
| } |
| |
| queue = &flow_ring_node->queue; /* queue associated with flow ring */ |
| |
| DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); |
| |
| if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp)) != BCME_OK) |
| txp_pend = txp; |
| |
| DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); |
| |
| if (flow_ring_node->status) { |
| DHD_INFO(("%s: Enq pkt flowid %d, status %d active %d\n", |
| __FUNCTION__, flowid, flow_ring_node->status, |
| flow_ring_node->active)); |
| if (txp_pend) { |
| txp = txp_pend; |
| goto toss; |
| } |
| return BCME_OK; |
| } |
| ret = dhd_bus_schedule_queue(bus, flowid, FALSE); |
| |
| /* If we have anything pending, try to push into q */ |
| if (txp_pend) { |
| DHD_FLOWRING_LOCK(flow_ring_node->lock, flags); |
| |
| if ((ret = dhd_flow_queue_enqueue(bus->dhd, queue, txp_pend)) != BCME_OK) { |
| DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); |
| txp = txp_pend; |
| goto toss; |
| } |
| |
| DHD_FLOWRING_UNLOCK(flow_ring_node->lock, flags); |
| } |
| |
| return ret; |
| |
| } else { /* bus->txmode_push */ |
| return dhd_prot_txdata(bus->dhd, txp, ifidx); |
| } |
| |
| toss: |
| DHD_INFO(("%s: Toss %d\n", __FUNCTION__, ret)); |
| PKTCFREE(bus->dhd->osh, txp, TRUE); |
| return ret; |
| } |
| |
| |
| void |
| dhd_bus_stop_queue(struct dhd_bus *bus) |
| { |
| dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, ON); |
| bus->bus_flowctrl = TRUE; |
| } |
| |
| void |
| dhd_bus_start_queue(struct dhd_bus *bus) |
| { |
| dhd_txflowcontrol(bus->dhd, ALL_INTERFACES, OFF); |
| bus->bus_flowctrl = TRUE; |
| } |
| |
| void |
| dhd_bus_update_retlen(dhd_bus_t *bus, uint32 retlen, uint32 pkt_id, uint16 status, |
| uint32 resp_len) |
| { |
| bus->rxlen = retlen; |
| bus->ioct_resp.cmn_hdr.request_id = pkt_id; |
| bus->ioct_resp.compl_hdr.status = status; |
| bus->ioct_resp.resp_len = (uint16)resp_len; |
| } |
| |
| #if defined(DHD_DEBUG) |
| /* Device console input function */ |
| int dhd_bus_console_in(dhd_pub_t *dhd, uchar *msg, uint msglen) |
| { |
| dhd_bus_t *bus = dhd->bus; |
| uint32 addr, val; |
| int rv; |
| /* Address could be zero if CONSOLE := 0 in dongle Makefile */ |
| if (bus->console_addr == 0) |
| return BCME_UNSUPPORTED; |
| |
| /* Don't allow input if dongle is in reset */ |
| if (bus->dhd->dongle_reset) { |
| dhd_os_sdunlock(bus->dhd); |
| return BCME_NOTREADY; |
| } |
| |
| /* Zero cbuf_index */ |
| addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf_idx); |
| val = htol32(0); |
| if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0) |
| goto done; |
| |
| /* Write message into cbuf */ |
| addr = bus->console_addr + OFFSETOF(hnd_cons_t, cbuf); |
| if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)msg, msglen)) < 0) |
| goto done; |
| |
| /* Write length into vcons_in */ |
| addr = bus->console_addr + OFFSETOF(hnd_cons_t, vcons_in); |
| val = htol32(msglen); |
| if ((rv = dhdpcie_bus_membytes(bus, TRUE, addr, (uint8 *)&val, sizeof(val))) < 0) |
| goto done; |
| |
| /* generate an interurpt to dongle to indicate that it needs to process cons command */ |
| dhdpcie_send_mb_data(bus, H2D_HOST_CONS_INT); |
| done: |
| return rv; |
| } |
| #endif /* defined(DHD_DEBUG) */ |
| |
| /* Process rx frame , Send up the layer to netif */ |
| void BCMFASTPATH |
| dhd_bus_rx_frame(struct dhd_bus *bus, void* pkt, int ifidx, uint pkt_count, int pkt_wake) |
| { |
| dhd_rx_frame(bus->dhd, ifidx, pkt, pkt_count, 0, pkt_wake, &bus->wake_counts); |
| } |
| |
| #if defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) |
| static ulong dhd_bus_cmn_check_offset(dhd_bus_t *bus, ulong offset) |
| { |
| uint new_bar1_wbase = 0; |
| ulong address = 0; |
| |
| new_bar1_wbase = (uint)offset & bus->bar1_win_mask; |
| if (bus->bar1_win_base != new_bar1_wbase) { |
| bus->bar1_win_base = new_bar1_wbase; |
| dhdpcie_bus_cfg_set_bar1_win(bus, bus->bar1_win_base); |
| DHD_ERROR(("%s: offset=%lx, switch bar1_win_base to %x\n", |
| __FUNCTION__, offset, bus->bar1_win_base)); |
| } |
| |
| address = offset - bus->bar1_win_base; |
| |
| return address; |
| } |
| #else |
| #define dhd_bus_cmn_check_offset(x, y) y |
| #endif /* defined(CONFIG_ARCH_MSM) && defined(CONFIG_64BIT) */ |
| |
| /** 'offset' is a backplane address */ |
| void |
| dhdpcie_bus_wtcm8(dhd_bus_t *bus, ulong offset, uint8 data) |
| { |
| *(volatile uint8 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint8)data; |
| } |
| |
| uint8 |
| dhdpcie_bus_rtcm8(dhd_bus_t *bus, ulong offset) |
| { |
| volatile uint8 data; |
| #ifdef BCM47XX_ACP_WAR |
| data = R_REG(bus->dhd->osh, |
| (volatile uint8 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset))); |
| #else |
| data = *(volatile uint8 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)); |
| #endif |
| return data; |
| } |
| |
| void |
| dhdpcie_bus_wtcm32(dhd_bus_t *bus, ulong offset, uint32 data) |
| { |
| *(volatile uint32 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint32)data; |
| } |
| void |
| dhdpcie_bus_wtcm16(dhd_bus_t *bus, ulong offset, uint16 data) |
| { |
| *(volatile uint16 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint16)data; |
| } |
| void |
| dhdpcie_bus_wtcm64(dhd_bus_t *bus, ulong offset, uint64 data) |
| { |
| *(volatile uint64 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)) = (uint64)data; |
| } |
| |
| uint16 |
| dhdpcie_bus_rtcm16(dhd_bus_t *bus, ulong offset) |
| { |
| volatile uint16 data; |
| #ifdef BCM47XX_ACP_WAR |
| data = R_REG(bus->dhd->osh, |
| (volatile uint16 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset))); |
| #else |
| data = *(volatile uint16 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)); |
| #endif |
| return data; |
| } |
| |
| uint32 |
| dhdpcie_bus_rtcm32(dhd_bus_t *bus, ulong offset) |
| { |
| volatile uint32 data; |
| #ifdef BCM47XX_ACP_WAR |
| data = R_REG(bus->dhd->osh, |
| (volatile uint32 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset))); |
| #else |
| data = *(volatile uint32 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)); |
| #endif |
| return data; |
| } |
| |
| uint64 |
| dhdpcie_bus_rtcm64(dhd_bus_t *bus, ulong offset) |
| { |
| volatile uint64 data; |
| #ifdef BCM47XX_ACP_WAR |
| data = R_REG(bus->dhd->osh, |
| (volatile uint64 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset))); |
| #else |
| data = *(volatile uint64 *)(bus->tcm + dhd_bus_cmn_check_offset(bus, offset)); |
| #endif |
| return data; |
| } |
| |
| void |
| dhd_bus_cmn_writeshared(dhd_bus_t *bus, void * data, uint32 len, uint8 type, uint16 ringid) |
| { |
| uint64 long_data; |
| ulong tcm_offset; |
| pciedev_shared_t *sh; |
| pciedev_shared_t *shmem = NULL; |
| |
| sh = (pciedev_shared_t*)bus->shared_addr; |
| |
| DHD_INFO(("%s: writing to msgbuf type %d, len %d\n", __FUNCTION__, type, len)); |
| |
| switch (type) { |
| case DNGL_TO_HOST_DMA_SCRATCH_BUFFER: |
| long_data = HTOL64(*(uint64 *)data); |
| tcm_offset = (ulong)&(sh->host_dma_scratch_buffer); |
| dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); |
| prhex(__FUNCTION__, data, len); |
| break; |
| |
| case DNGL_TO_HOST_DMA_SCRATCH_BUFFER_LEN : |
| tcm_offset = (ulong)&(sh->host_dma_scratch_buffer_len); |
| dhdpcie_bus_wtcm32(bus, tcm_offset, (uint32) HTOL32(*(uint32 *)data)); |
| prhex(__FUNCTION__, data, len); |
| break; |
| |
| case HOST_TO_DNGL_DMA_WRITEINDX_BUFFER: |
| /* ring_info_ptr stored in pcie_sh */ |
| shmem = (pciedev_shared_t *)bus->pcie_sh; |
| |
| long_data = HTOL64(*(uint64 *)data); |
| tcm_offset = (ulong)shmem->rings_info_ptr; |
| tcm_offset += OFFSETOF(ring_info_t, h2d_w_idx_hostaddr); |
| dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); |
| prhex(__FUNCTION__, data, len); |
| break; |
| |
| case HOST_TO_DNGL_DMA_READINDX_BUFFER: |
| /* ring_info_ptr stored in pcie_sh */ |
| shmem = (pciedev_shared_t *)bus->pcie_sh; |
| |
| long_data = HTOL64(*(uint64 *)data); |
| tcm_offset = (ulong)shmem->rings_info_ptr; |
| tcm_offset += OFFSETOF(ring_info_t, h2d_r_idx_hostaddr); |
| dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); |
| prhex(__FUNCTION__, data, len); |
| break; |
| |
| case DNGL_TO_HOST_DMA_WRITEINDX_BUFFER: |
| /* ring_info_ptr stored in pcie_sh */ |
| shmem = (pciedev_shared_t *)bus->pcie_sh; |
| |
| long_data = HTOL64(*(uint64 *)data); |
| tcm_offset = (ulong)shmem->rings_info_ptr; |
| tcm_offset += OFFSETOF(ring_info_t, d2h_w_idx_hostaddr); |
| dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); |
| prhex(__FUNCTION__, data, len); |
| break; |
| |
| case DNGL_TO_HOST_DMA_READINDX_BUFFER: |
| /* ring_info_ptr stored in pcie_sh */ |
| shmem = (pciedev_shared_t *)bus->pcie_sh; |
| |
| long_data = HTOL64(*(uint64 *)data); |
| tcm_offset = (ulong)shmem->rings_info_ptr; |
| tcm_offset += OFFSETOF(ring_info_t, d2h_r_idx_hostaddr); |
| dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8*) &long_data, len); |
| prhex(__FUNCTION__, data, len); |
| break; |
| |
| case RING_LEN_ITEMS : |
| tcm_offset = bus->ring_sh[ringid].ring_mem_addr; |
| tcm_offset += OFFSETOF(ring_mem_t, len_items); |
| dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data)); |
| break; |
| |
| case RING_MAX_ITEM : |
| tcm_offset = bus->ring_sh[ringid].ring_mem_addr; |
| tcm_offset += OFFSETOF(ring_mem_t, max_item); |
| dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data)); |
| break; |
| |
| case RING_BUF_ADDR : |
| long_data = HTOL64(*(uint64 *)data); |
| tcm_offset = bus->ring_sh[ringid].ring_mem_addr; |
| tcm_offset += OFFSETOF(ring_mem_t, base_addr); |
| dhdpcie_bus_membytes(bus, TRUE, tcm_offset, (uint8 *) &long_data, len); |
| prhex(__FUNCTION__, data, len); |
| break; |
| |
| case RING_WRITE_PTR : |
| tcm_offset = bus->ring_sh[ringid].ring_state_w; |
| dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data)); |
| break; |
| case RING_READ_PTR : |
| tcm_offset = bus->ring_sh[ringid].ring_state_r; |
| dhdpcie_bus_wtcm16(bus, tcm_offset, (uint16) HTOL16(*(uint16 *)data)); |
| break; |
| |
| case DTOH_MB_DATA: |
| dhdpcie_bus_wtcm32(bus, bus->d2h_mb_data_ptr_addr, |
| (uint32) HTOL32(*(uint32 *)data)); |
| break; |
| |
| case HTOD_MB_DATA: |
| dhdpcie_bus_wtcm32(bus, bus->h2d_mb_data_ptr_addr, |
| (uint32) HTOL32(*(uint32 *)data)); |
| break; |
| default: |
| break; |
| } |
| } |
| |
| |
| void |
| dhd_bus_cmn_readshared(dhd_bus_t *bus, void* data, uint8 type, uint16 ringid) |
| { |
| pciedev_shared_t *sh; |
| ulong tcm_offset; |
| |
| sh = (pciedev_shared_t*)bus->shared_addr; |
| |
| switch (type) { |
| case RING_WRITE_PTR : |
| tcm_offset = bus->ring_sh[ringid].ring_state_w; |
| *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset)); |
| break; |
| case RING_READ_PTR : |
| tcm_offset = bus->ring_sh[ringid].ring_state_r; |
| *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, tcm_offset)); |
| break; |
| case TOTAL_LFRAG_PACKET_CNT : |
| *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, |
| (ulong) &sh->total_lfrag_pkt_cnt)); |
| break; |
| case HTOD_MB_DATA: |
| *(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->h2d_mb_data_ptr_addr)); |
| break; |
| case DTOH_MB_DATA: |
| *(uint32*)data = LTOH32(dhdpcie_bus_rtcm32(bus, bus->d2h_mb_data_ptr_addr)); |
| break; |
| case MAX_HOST_RXBUFS : |
| *(uint16*)data = LTOH16(dhdpcie_bus_rtcm16(bus, |
| (ulong) &sh->max_host_rxbufs)); |
| break; |
| default : |
| break; |
| } |
| } |
| |
| uint32 dhd_bus_get_sharedflags(dhd_bus_t *bus) |
| { |
| return ((pciedev_shared_t*)bus->pcie_sh)->flags; |
| } |
| |
| void |
| dhd_bus_clearcounts(dhd_pub_t *dhdp) |
| { |
| } |
| |
| int |
| dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name, |
| void *params, int plen, void *arg, int len, bool set) |
| { |
| dhd_bus_t *bus = dhdp->bus; |
| const bcm_iovar_t *vi = NULL; |
| int bcmerror = 0; |
| int val_size; |
| uint32 actionid; |
| |
| DHD_TRACE(("%s: Enter\n", __FUNCTION__)); |
| |
| ASSERT(name); |
| ASSERT(len >= 0); |
| |
| /* Get MUST have return space */ |
| ASSERT(set || (arg && len)); |
| |
| /* Set does NOT take qualifiers */ |
| ASSERT(!set || (!params && !plen)); |
| |
| DHD_INFO(("%s: %s %s, len %d plen %d\n", __FUNCTION__, |
| name, (set ? "set" : "get"), len, plen)); |
| |
| /* Look up var locally; if not found pass to host driver */ |
| if ((vi = bcm_iovar_lookup(dhdpcie_iovars, name)) == NULL) { |
| goto exit; |
| } |
| |
| |
| /* set up 'params' pointer in case this is a set command so that |
| * the convenience int and bool code can be common to set and get |
| */ |
| if (params == NULL) { |
| params = arg; |
| plen = len; |
| } |
| |
| if (vi->type == IOVT_VOID) |
| val_size = 0; |
| else if (vi->type == IOVT_BUFFER) |
| val_size = len; |
| else |
| /* all other types are integer sized */ |
| val_size = sizeof(int); |
| |
| actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid); |
| bcmerror = dhdpcie_bus_doiovar(bus, vi, actionid, name, params, plen, arg, len, val_size); |
| |
| exit: |
| return bcmerror; |
| } |
| |
| #ifdef BCM_BUZZZ |
| #include <bcm_buzzz.h> |
| |
| int dhd_buzzz_dump_cntrs3(char *p, uint32 *core, uint32 * ovhd, uint32 *log) |
| { |
| int bytes = 0; |
| uint32 ctr, curr[3], prev[3], delta[3]; |
| |
| /* Compute elapsed counter values per counter event type */ |
| for (ctr = 0U; ctr < 3; ctr++) { |
| prev[ctr] = core[ctr]; |
| curr[ctr] = *log++; |
| core[ctr] = curr[ctr]; /* saved for next log */ |
| |
| if (curr[ctr] < prev[ctr]) |
| delta[ctr] = curr[ctr] + (~0U - prev[ctr]); |
| else |
| delta[ctr] = (curr[ctr] - prev[ctr]); |
| |
| /* Adjust for instrumentation overhead */ |
| if (delta[ctr] >= ovhd[ctr]) |
| delta[ctr] -= ovhd[ctr]; |
| else |
| delta[ctr] = 0; |
| |
| bytes += sprintf(p + bytes, "%12u ", delta[ctr]); |
| } |
| |
| return bytes; |
| } |
| |
| typedef union cm3_cnts { /* export this in bcm_buzzz.h */ |
| uint32 u32; |
| uint8 u8[4]; |
| struct { |
| uint8 cpicnt; |
| uint8 exccnt; |
| uint8 sleepcnt; |
| uint8 lsucnt; |
| }; |
| } cm3_cnts_t; |
| |
| int dhd_buzzz_dump_cntrs6(char *p, uint32 *core, uint32 * ovhd, uint32 *log) |
| { |
| int bytes = 0; |
| |
| uint32 cyccnt, instrcnt; |
| cm3_cnts_t cm3_cnts; |
| uint8 foldcnt; |
| |
| { /* 32bit cyccnt */ |
| uint32 curr, prev, delta; |
| prev = core[0]; curr = *log++; core[0] = curr; |
| if (curr < prev) |
| delta = curr + (~0U - prev); |
| else |
| delta = (curr - prev); |
| if (delta >= ovhd[0]) |
| delta -= ovhd[0]; |
| else |
| delta = 0; |
| |
| bytes += sprintf(p + bytes, "%12u ", delta); |
| cyccnt = delta; |
| } |
| |
| { /* Extract the 4 cnts: cpi, exc, sleep and lsu */ |
| int i; |
| uint8 max8 = ~0; |
| cm3_cnts_t curr, prev, delta; |
| prev.u32 = core[1]; curr.u32 = * log++; core[1] = curr.u32; |
| for (i = 0; i < 4; i++) { |
| if (curr.u8[i] < prev.u8[i]) |
| delta.u8[i] = curr.u8[i] + (max8 - prev.u8[i]); |
| else |
| delta.u8[i] = (curr.u8[i] - prev.u8[i]); |
| if (delta.u8[i] >= ovhd[i + 1]) |
| delta.u8[i] -= ovhd[i + 1]; |
| else |
| delta.u8[i] = 0; |
| bytes += sprintf(p + bytes, "%4u ", delta.u8[i]); |
| } |
| cm3_cnts.u32 = delta.u32; |
| } |
| |
| { /* Extract the foldcnt from arg0 */ |
| uint8 curr, prev, delta, max8 = ~0; |
| buzzz_arg0_t arg0; arg0.u32 = *log; |
| prev = core[2]; curr = arg0.klog.cnt; core[2] = curr; |
| if (curr < prev) |
| delta = curr + (max8 - prev); |
| else |
| delta = (curr - prev); |
| if (delta >= ovhd[5]) |
| delta -= ovhd[5]; |
| else |
| delta = 0; |
| bytes += sprintf(p + bytes, "%4u ", delta); |
| foldcnt = delta; |
| } |
| |
| instrcnt = cyccnt - (cm3_cnts.u8[0] + cm3_cnts.u8[1] + cm3_cnts.u8[2] |
| + cm3_cnts.u8[3]) + foldcnt; |
| if (instrcnt > 0xFFFFFF00) |
| bytes += sprintf(p + bytes, "[%10s] ", "~"); |
| else |
| bytes += sprintf(p + bytes, "[%10u] ", instrcnt); |
| return bytes; |
| } |
| |
| int dhd_buzzz_dump_log(char * p, uint32 * core, uint32 * log, buzzz_t * buzzz) |
| { |
| int bytes = 0; |
| buzzz_arg0_t arg0; |
| static uint8 * fmt[] = BUZZZ_FMT_STRINGS; |
| |
| if (buzzz->counters == 6) { |
| bytes += dhd_buzzz_dump_cntrs6(p, core, buzzz->ovhd, log); |
| log += 2; /* 32bit cyccnt + (4 x 8bit) CM3 */ |
| } else { |
| bytes += dhd_buzzz_dump_cntrs3(p, core, buzzz->ovhd, log); |
| log += 3; /* (3 x 32bit) CR4 */ |
| } |
| |
| /* Dump the logged arguments using the registered formats */ |
| arg0.u32 = *log++; |
| |
| switch (arg0.klog.args) { |
| case 0: |
| bytes += sprintf(p + bytes, fmt[arg0.klog.id]); |
| break; |
| case 1: |
| { |
| uint32 arg1 = *log++; |
| bytes += sprintf(p + bytes, fmt[arg0.klog.id], arg1); |
| break; |
| } |
| default: |
| printf("Maximum one argument supported\n"); |
| break; |
| } |
| bytes += sprintf(p + bytes, "\n"); |
| |
| return bytes; |
| } |
| |
| void dhd_buzzz_dump(buzzz_t * buzzz_p, void * buffer_p, char * p) |
| { |
| int i; |
| uint32 total, part1, part2, log_sz, core[BUZZZ_COUNTERS_MAX]; |
| void * log; |
| |
| for (i = 0; i < BUZZZ_COUNTERS_MAX; i++) |
| core[i] = 0; |
| |
| log_sz = buzzz_p->log_sz; |
| |
| part1 = ((uint32)buzzz_p->cur - (uint32)buzzz_p->log) / log_sz; |
| |
| if (buzzz_p->wrap == TRUE) { |
| part2 = ((uint32)buzzz_p->end - (uint32)buzzz_p->cur) / log_sz; |
| total = (buzzz_p->buffer_sz - BUZZZ_LOGENTRY_MAXSZ) / log_sz; |
| } else { |
| part2 = 0U; |
| total = buzzz_p->count; |
| } |
| |
| if (total == 0U) { |
| printf("buzzz_dump total<%u> done\n", total); |
| return; |
| } else { |
| printf("buzzz_dump total<%u> : part2<%u> + part1<%u>\n", |
| total, part2, part1); |
| } |
| |
| if (part2) { /* with wrap */ |
| log = (void*)((size_t)buffer_p + (buzzz_p->cur - buzzz_p->log)); |
| while (part2--) { /* from cur to end : part2 */ |
| p[0] = '\0'; |
| dhd_buzzz_dump_log(p, core, (uint32 *)log, buzzz_p); |
| printf("%s", p); |
| log = (void*)((size_t)log + buzzz_p->log_sz); |
| } |
| } |
| |
| log = (void*)buffer_p; |
| while (part1--) { |
| p[0] = '\0'; |
| dhd_buzzz_dump_log(p, core, (uint32 *)log, buzzz_p); |
| printf("%s", p); |
| log = (void*)((size_t)log + buzzz_p->log_sz); |
| } |
| |
| printf("buzzz_dump done.\n"); |
| } |
| |
| int dhd_buzzz_dump_dngl(dhd_bus_t *bus) |
| { |
| buzzz_t * buzzz_p = NULL; |
| void * buffer_p = NULL; |
| char * page_p = NULL; |
| pciedev_shared_t *sh; |
| int ret = 0; |
| |
| if (bus->dhd->busstate != DHD_BUS_DATA) { |
| return BCME_UNSUPPORTED; |
| } |
| if ((page_p = (char *)MALLOC(bus->dhd->osh, 4096)) == NULL) { |
| printf("Page memory allocation failure\n"); |
| goto done; |
| } |
| if ((buzzz_p = MALLOC(bus->dhd->osh, sizeof(buzzz_t))) == NULL) { |
| printf("Buzzz memory allocation failure\n"); |
| goto done; |
| } |
| |
| ret = dhdpcie_readshared(bus); |
| if (ret < 0) { |
| DHD_ERROR(("%s :Shared area read failed \n", __FUNCTION__)); |
| goto done; |
| } |
| |
| sh = bus->pcie_sh; |
| |
| DHD_INFO(("%s buzzz:%08x\n", __FUNCTION__, sh->buzzz)); |
| |
| if (sh->buzzz != 0U) { /* Fetch and display dongle BUZZZ Trace */ |
| dhdpcie_bus_membytes(bus, FALSE, (ulong)sh->buzzz, |
| (uint8 *)buzzz_p, sizeof(buzzz_t)); |
| if (buzzz_p->count == 0) { |
| printf("Empty dongle BUZZZ trace\n\n"); |
| goto done; |
| } |
| if (buzzz_p->counters != 3) { /* 3 counters for CR4 */ |
| printf("Counters<%u> mismatch\n", buzzz_p->counters); |
| goto done; |
| } |
| /* Allocate memory for trace buffer and format strings */ |
| buffer_p = MALLOC(bus->dhd->osh, buzzz_p->buffer_sz); |
| if (buffer_p == NULL) { |
| printf("Buffer memory allocation failure\n"); |
| goto done; |
| } |
| /* Fetch the trace and format strings */ |
| dhdpcie_bus_membytes(bus, FALSE, (uint32)buzzz_p->log, /* Trace */ |
| (uint8 *)buffer_p, buzzz_p->buffer_sz); |
| /* Process and display the trace using formatted output */ |
| printf("<#cycle> <#instruction> <#ctr3> <event information>\n"); |
| dhd_buzzz_dump(buzzz_p, buffer_p, page_p); |
| printf("----- End of dongle BUZZZ Trace -----\n\n"); |
| MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz); buffer_p = NULL; |
| } |
| |
| done: |
| |
| if (page_p) MFREE(bus->dhd->osh, page_p, 4096); |
| if (buzzz_p) MFREE(bus->dhd->osh, buzzz_p, sizeof(buzzz_t)); |
| if (buffer_p) MFREE(bus->dhd->osh, buffer_p, buzzz_p->buffer_sz); |
| |
| return BCME_OK; |
| } |
| #endif /* BCM_BUZZZ */ |
| int |
| dhd_bus_devreset(dhd_pub_t *dhdp, uint8 flag) |
| { |
| dhd_bus_t *bus = dhdp->bus; |
| int ret = 0; |
| #ifdef CONFIG_ARCH_MSM |
| int retry = POWERUP_MAX_RETRY; |
| #endif /* CONFIG_ARCH_MSM */ |
| |
| if (dhd_download_fw_on_driverload) { |
| ret = dhd_bus_start(dhdp); |
| } else { |
| if (flag == TRUE) { |
| /* Turn off WLAN */ |
| DHD_ERROR(("%s: == Power OFF ==\n", __FUNCTION__)); |
| dhd_os_sdlock(dhdp); |
| bus->dhd->up = FALSE; |
| /* Prevent dhd_bus_watchdog from touching HW */ |
| dhd_os_sdunlock(dhdp); |
| if (bus->dhd->busstate != DHD_BUS_DOWN) { |
| if (bus->intr) { |
| dhdpcie_bus_intr_disable(bus); |
| dhdpcie_free_irq(bus); |
| } |
| |
| dhd_os_wd_timer(dhdp, 0); |
| dhd_dbg_start(dhdp, 0); |
| dhd_bus_stop(bus, TRUE); |
| dhd_prot_clear(dhdp); |
| dhd_clear(dhdp); |
| dhd_bus_release_dongle(bus); |
| dhdpcie_bus_free_resource(bus); |
| ret = dhdpcie_bus_disable_device(bus); |
| if (ret) { |
| DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| |
| #ifdef CONFIG_ARCH_MSM |
| ret = dhdpcie_bus_clock_stop(bus); |
| if (ret) { |
| DHD_ERROR(("%s: host clock stop failed: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| #endif /* CONFIG_ARCH_MSM */ |
| bus->dhd->busstate = DHD_BUS_DOWN; |
| } else { |
| if (bus->intr) { |
| dhdpcie_bus_intr_disable(bus); |
| dhdpcie_free_irq(bus); |
| } |
| |
| dhd_prot_clear(dhdp); |
| dhd_clear(dhdp); |
| dhd_bus_release_dongle(bus); |
| dhdpcie_bus_free_resource(bus); |
| ret = dhdpcie_bus_disable_device(bus); |
| if (ret) { |
| DHD_ERROR(("%s: dhdpcie_bus_disable_device: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| #ifdef CONFIG_ARCH_MSM |
| ret = dhdpcie_bus_clock_stop(bus); |
| if (ret) { |
| DHD_ERROR(("%s: host clock stop failed: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| #endif /* CONFIG_ARCH_MSM */ |
| } |
| |
| bus->dhd->dongle_reset = TRUE; |
| DHD_ERROR(("%s: WLAN OFF Done\n", __FUNCTION__)); |
| |
| } else { |
| if (bus->dhd->busstate == DHD_BUS_DOWN) { |
| /* Turn on WLAN */ |
| DHD_ERROR(("%s: == Power ON ==\n", __FUNCTION__)); |
| #ifdef CONFIG_ARCH_MSM |
| while (retry--) { |
| ret = dhdpcie_bus_clock_start(bus); |
| if (!ret) { |
| DHD_ERROR(("%s: dhdpcie_bus_clock_start OK\n", |
| __FUNCTION__)); |
| break; |
| } |
| else |
| OSL_SLEEP(10); |
| } |
| |
| if (ret && !retry) { |
| DHD_ERROR(("%s: host pcie clock enable failed: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| #endif /* CONFIG_ARCH_MSM */ |
| ret = dhdpcie_bus_enable_device(bus); |
| if (ret) { |
| DHD_ERROR(("%s: host configuration restore failed: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| |
| ret = dhdpcie_bus_alloc_resource(bus); |
| if (ret) { |
| DHD_ERROR(("%s: dhdpcie_bus_resource_alloc failed: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| |
| ret = dhdpcie_bus_dongle_attach(bus); |
| if (ret) { |
| DHD_ERROR(("%s: dhdpcie_bus_dongle_attach failed: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| |
| ret = dhd_bus_request_irq(bus); |
| if (ret) { |
| DHD_ERROR(("%s: dhd_bus_request_irq failed: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| |
| bus->dhd->dongle_reset = FALSE; |
| |
| ret = dhd_bus_start(dhdp); |
| if (ret) { |
| DHD_ERROR(("%s: dhd_bus_start: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| ret = dhd_dbg_start(dhdp, 1); |
| if (ret) { |
| DHD_ERROR(("%s: dhd_dbg_start: %d\n", |
| __FUNCTION__, ret)); |
| goto done; |
| } |
| dhd_os_sdlock(dhdp); |
| bus->dhd->up = TRUE; |
| dhd_os_sdunlock(dhdp); |
| DHD_ERROR(("%s: WLAN Power On Done\n", __FUNCTION__)); |
| } else { |
| DHD_ERROR(("%s: what should we do here\n", __FUNCTION__)); |
| goto done; |
| } |
| } |
| } |
| done: |
| if (ret) |
| bus->dhd->busstate = DHD_BUS_DOWN; |
| |
| return ret; |
| } |
| |
| static int |
| dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, const char *name, |
| void *params, int plen, void *arg, int len, int val_size) |
| { |
| int bcmerror = 0; |
| int32 int_val = 0; |
| int32 int_val2 = 0; |
| int32 int_val3 = 0; |
| bool bool_val = 0; |
| |
| DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p len %d val_size %d\n", |
| __FUNCTION__, actionid, name, params, plen, arg, len, val_size)); |
| |
| if ((bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid))) != 0) |
| goto exit; |
| |
| if (plen >= (int)sizeof(int_val)) |
| bcopy(params, &int_val, sizeof(int_val)); |
| |
| if (plen >= (int)sizeof(int_val) * 2) |
| bcopy((void*)((uintptr)params + sizeof(int_val)), &int_val2, sizeof(int_val2)); |
| |
| if (plen >= (int)sizeof(int_val) * 3) |
| bcopy((void*)((uintptr)params + 2 * sizeof(int_val)), &int_val3, sizeof(int_val3)); |
| |
| bool_val = (int_val != 0) ? TRUE : FALSE; |
| |
| /* Check if dongle is in reset. If so, only allow DEVRESET iovars */ |
| if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) || |
| actionid == IOV_GVAL(IOV_DEVRESET))) { |
| bcmerror = BCME_NOTREADY; |
| goto exit; |
| } |
| |
| switch (actionid) { |
| |
| |
| case IOV_SVAL(IOV_VARS): |
| bcmerror = dhdpcie_downloadvars(bus, arg, len); |
| break; |
| |
| case IOV_SVAL(IOV_PCIEREG): |
| si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, |
| int_val); |
| si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0, |
| int_val2); |
| break; |
| |
| case IOV_GVAL(IOV_PCIEREG): |
| si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, |
| int_val); |
| int_val = si_corereg(bus->sih, bus->sih->buscoreidx, |
| OFFSETOF(sbpcieregs_t, configdata), 0, 0); |
| bcopy(&int_val, arg, sizeof(int_val)); |
| break; |
| |
| case IOV_GVAL(IOV_BAR0_SECWIN_REG): |
| { |
| uint32 cur_base, base; |
| uchar *bar0; |
| volatile uint32 *offset; |
| /* set the bar0 secondary window to this */ |
| /* write the register value */ |
| cur_base = dhdpcie_bus_cfg_read_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint)); |
| base = int_val & 0xFFFFF000; |
| dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), base); |
| bar0 = (uchar *)bus->regs; |
| offset = (uint32 *)(bar0 + 0x4000 + (int_val & 0xFFF)); |
| int_val = *offset; |
| bcopy(&int_val, arg, sizeof(int_val)); |
| dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), cur_base); |
| } |
| break; |
| case IOV_SVAL(IOV_BAR0_SECWIN_REG): |
| { |
| uint32 cur_base, base; |
| uchar *bar0; |
| volatile uint32 *offset; |
| /* set the bar0 secondary window to this */ |
| /* write the register value */ |
|
|