| #ifndef MIPICSI_RX_DPHY_H_ |
| #define MIPICSI_RX_DPHY_H_ |
| |
| /* DesignWare® Cores MIPI D-PHY v1.2 Rx 4L for TSMC 28-nm HPC/1.8V */ |
| |
| /* Test Codes */ |
| #define R_DPHY_TESTCODE_X_REG 0x0 |
| #define R_DPHY_RDWR_RX_SYS_0 0x1 |
| #define R_DPHY_RDWR_RX_SYS_1 0x2 |
| #define R_DPHY_RDWR_RX_SYS_2 0x3 |
| #define R_DPHY_RDWR_RX_SYS_3 0x4 |
| #define R_DPHY_RDWR_RX_SYS_4 0x5 |
| #define R_DPHY_RDWR_RX_SYS_5 0x6 |
| #define R_DPHY_RDWR_RX_SYS_6 0x7 |
| #define R_DPHY_RDWR_RX_SYS_7 0x8 |
| #define R_DPHY_RDWR_RX_SYS_8 0x9 |
| #define R_DPHY_RDWR_RX_SYS_9 0xA |
| #define R_DPHY_RD_RX_SYS_0 0x1E |
| #define R_DPHY_RD_RX_SYS_1 0x1F |
| #define R_DPHY_RD_RX_SYS_2 0x20 |
| #define R_DPHY_RD_RX_SYS_3 0x21 |
| #define R_DPHY_RD_CONT_DATA_0 0x23 |
| #define R_DPHY_RD_CONT_DATA_1 0x24 |
| #define R_DPHY_RD_RX_SYS_4 0x25 |
| #define R_DPHY_RDWR_RX_SYS_DDL_0 0x37 |
| #define R_DPHY_RDWR_RX_SYS_DDL_1 0x38 |
| #define R_DPHY_RDWR_RX_SYS_DDL_2 0x39 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_0 0x4E |
| #define R_DPHY_RDWR_RX_SYSTIMERS_1 0x4F |
| #define R_DPHY_RDWR_RX_SYSTIMERS_2 0x50 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_3 0x51 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_4 0x52 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_5 0x53 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_6 0x54 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_7 0x55 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_8 0x56 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_9 0x57 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_10 0x58 |
| #define R_DPHY_RDWR_RX_SYSTIMERS_11 0x59 |
| #define R_DPHY_RD_RX_SYSTIMERS_0 0x7A |
| #define R_DPHY_RD_RX_RX_STARTUP_OBS_0 0xC7 |
| #define R_DPHY_RD_RX_RX_STARTUP_OBS_1 0xC8 |
| #define R_DPHY_RD_RX_RX_STARTUP_OBS_2 0xC9 |
| #define R_DPHY_RD_RX_RX_STARTUP_OBS_3 0xCA |
| #define R_DPHY_RD_RX_RX_STARTUP_OBS_4 0xCB |
| #define R_DPHY_RDWR_RX_RX_STARTUP_OVR_0 0xE0 |
| #define R_DPHY_RDWR_RX_RX_STARTUP_OVR_1 0xE1 |
| #define R_DPHY_RDWR_RX_RX_STARTUP_OVR_2 0xE2 |
| #define R_DPHY_RDWR_RX_RX_STARTUP_OVR_3 0xE3 |
| #define R_DPHY_RDWR_RX_RX_STARTUP_OVR_4 0xE4 |
| #define R_DPHY_RDWR_RX_RX_STARTUP_OVR_5 0xE5 |
| #define R_DPHY_RDWR_RX_RX_STARTUP_OVR_17 0xF1 |
| #define R_DPHY_RDWR_RX_BIST_0 0x107 |
| #define R_DPHY_RDWR_RX_BIST_1 0x108 |
| #define R_DPHY_RDWR_RX_BIST_2 0x109 |
| #define R_DPHY_RDWR_RX_BIST_3 0x10A |
| #define R_DPHY_RDWR_RX_BIST_4 0x10B |
| #define R_DPHY_RDWR_RX_BIST_OVR_0 0x110 |
| #define R_DPHY_RDWR_RX_BIST_OVR_1 0x111 |
| #define R_DPHY_RDWR_RX_BIST_OVR_2 0x112 |
| #define R_DPHY_RDWR_RX_BIST_OVR_3 0x113 |
| #define R_DPHY_RDWR_RX_BIST_PIPE_TIMER 0x114 |
| #define R_DPHY_RD_RX_BIST_0 0x11E |
| #define R_DPHY_RD_RX_BIST_1 0x11F |
| #define R_DPHY_RD_RX_BIST_2 0x120 |
| #define R_DPHY_RD_RX_BIST_3 0x121 |
| #define R_DPHY_RD_RX_BIST_13 0x12C |
| #define R_DPHY_RDWR_RX_RX_DUAL_PHY_0 0x133 |
| #define R_DPHY_RD_RX_DUAL_PHY_0 0x148 |
| #define R_DPHY_RD_RX_DUAL_PHY_1 0x149 |
| #define R_DPHY_RD_RX_DUAL_PHY_2 0x14A |
| #define R_DPHY_RDWR_RX_PLL_0 0x15D |
| #define R_DPHY_RDWR_RX_PLL_1 0x15E |
| #define R_DPHY_RDWR_RX_PLL_2 0x15F |
| #define R_DPHY_RDWR_RX_PLL_3 0x160 |
| #define R_DPHY_RDWR_RX_PLL_4 0x161 |
| #define R_DPHY_RDWR_RX_PLL_5 0x162 |
| #define R_DPHY_RDWR_RX_PLL_6 0x163 |
| #define R_DPHY_RDWR_RX_PLL_7 0x164 |
| #define R_DPHY_RDWR_RX_PLL_8 0x165 |
| #define R_DPHY_RDWR_RX_PLL_9 0x166 |
| #define R_DPHY_RDWR_RX_PLL_10 0x167 |
| #define R_DPHY_RDWR_RX_PLL_11 0x168 |
| #define R_DPHY_RDWR_RX_PLL_12 0x169 |
| #define R_DPHY_RDWR_RX_PLL_13 0x16A |
| #define R_DPHY_RDWR_RX_PLL_14 0x16B |
| #define R_DPHY_RDWR_RX_PLL_15 0x16C |
| #define R_DPHY_RDWR_RX_PLL_16 0x16D |
| #define R_DPHY_RDWR_RX_PLL_17 0x16E |
| #define R_DPHY_RDWR_RX_PLL_18 0x16F |
| #define R_DPHY_RDWR_RX_PLL_19 0x170 |
| #define R_DPHY_RDWR_RX_PLL_20 0x171 |
| #define R_DPHY_RDWR_RX_PLL_21 0x172 |
| #define R_DPHY_RDWR_RX_PLL_22 0x173 |
| #define R_DPHY_RDWR_RX_PLL_23 0x174 |
| #define R_DPHY_RDWR_RX_PLL_24 0x175 |
| #define R_DPHY_RDWR_RX_PLL_25 0x176 |
| #define R_DPHY_RDWR_RX_PLL_26 0x177 |
| #define R_DPHY_RDWR_RX_PLL_27 0x178 |
| #define R_DPHY_RDWR_RX_PLL_28 0x179 |
| #define R_DPHY_RDWR_RX_PLL_29 0x17A |
| #define R_DPHY_RDWR_RX_PLL_30 0x17B |
| #define R_DPHY_RDWR_RX_PLL_31 0x17C |
| #define R_DPHY_RD_RX_PLL_0 0x191 |
| #define R_DPHY_RD_RX_PLL_1 0x192 |
| #define R_DPHY_RD_RX_PLL_2 0x193 |
| #define R_DPHY_RD_RX_PLL_3 0x194 |
| #define R_DPHY_RD_RX_PLL_4 0x195 |
| #define R_DPHY_RDWR_RX_CB_0 0x1AA |
| #define R_DPHY_RDWR_RX_CB_1 0x1AB |
| #define R_DPHY_RDWR_RX_CB_2 0x1AC |
| #define R_DPHY_RDWR_RX_CB_3 0x1AD |
| #define R_DPHY_RDWR_RX_CB_4 0x1AE |
| #define R_DPHY_RDWR_RX_CB_5 0x1AF |
| #define R_DPHY_RDWR_RX_CB_6 0x1B0 |
| #define R_DPHY_RD_RX_ANA_CB_0 0x1C4 |
| #define R_DPHY_RDWR_RX_DAC_0 0x1DA |
| #define R_DPHY_RDWR_RX_DAC_1 0x1DB |
| #define R_DPHY_RDWR_RX_DAC_2 0x1DC |
| #define R_DPHY_RDWR_RX_DAC_3 0x1DD |
| #define R_DPHY_RD_RX_DAC_0 0x1F2 |
| #define R_DPHY_RD_RX_DAC_1 0x1F3 |
| #define R_DPHY_RD_RX_DAC_2 0x1F4 |
| #define R_DPHY_RDWR_RX_TERM_CAL_0 0x209 |
| #define R_DPHY_RDWR_RX_TERM_CAL_1 0x20A |
| #define R_DPHY_RDWR_RX_TERM_CAL_2 0x20B |
| #define R_DPHY_RD_RX_TERM_CAL_0 0x220 |
| #define R_DPHY_RD_RX_TERM_CAL_1 0x221 |
| #define R_DPHY_RD_RX_TERM_CAL_2 0x222 |
| #define R_DPHY_RDWR_RX_NOREXTTUNE_0 0x237 |
| #define R_DPHY_RDWR_RX_NOREXTTUNE_1 0x238 |
| #define R_DPHY_RDWR_RX_NOREXTTUNE_2 0x239 |
| #define R_DPHY_RDWR_RX_NOREXTTUNE_3 0x23A |
| #define R_DPHY_RDWR_RX_NOREXTTUNE_4 0x23B |
| #define R_DPHY_RDWR_RX_NOREXTTUNE_5 0x23C |
| #define R_DPHY_RDWR_RX_NOREXTTUNE_6 0x23D |
| #define R_DPHY_RD_RX_NOREXTTUNE_0 0x252 |
| #define R_DPHY_RD_RX_NOREXTTUNE_1 0x253 |
| #define R_DPHY_RD_RX_NOREXTTUNE_2 0x254 |
| #define R_DPHY_RD_RX_NOREXTTUNE_3 0x255 |
| #define R_DPHY_RD_RX_NOREXTTUNE_4 0x256 |
| #define R_DPHY_RDWR_RX_CLKLANE_LANE_0 0x301 |
| #define R_DPHY_RDWR_RX_CLKLANE_LANE_1 0x302 |
| #define R_DPHY_RDWR_RX_CLKLANE_LANE_3 0x304 |
| #define R_DPHY_RDWR_RX_CLKLANE_LANE_4 0x305 |
| #define R_DPHY_RDWR_RX_CLKLANE_LANE_6 0x307 |
| #define R_DPHY_RDWR_RX_CLKLANE_LANE_7 0x308 |
| #define R_DPHY_RDWR_RX_CLKLANE_LANE_8 0x309 |
| #define R_DPHY_RD_RX_CLKLANE_LANE_0 0x32B |
| #define R_DPHY_RD_RX_CLKLANE_LANE_1 0x32C |
| #define R_DPHY_RD_RX_CLKLANE_LANE_2 0x32D |
| #define R_DPHY_RD_RX_CLKLANE_LANE_3 0x32E |
| #define R_DPHY_RDWR_RX_CLKLANE_OFFSET_CAL_0 0x37A |
| #define R_DPHY_RDWR_RX_CLKLANE_OFFSET_CAL_1 0x37B |
| #define R_DPHY_RD_RX_CLKLANE_OFFSET_CAL_0 0x39D |
| #define R_DPHY_RD_RX_CLKLANE_OFFSET_CAL_1 0x39E |
| #define R_DPHY_RD_RX_CLKLANE_OFFSET_CAL_2 0x39F |
| #define R_DPHY_RDWR_RX_LANE0_LANE_0 0x501 |
| #define R_DPHY_RDWR_RX_LANE0_LANE_1 0x502 |
| #define R_DPHY_RDWR_RX_LANE0_LANE_3 0x504 |
| #define R_DPHY_RDWR_RX_LANE0_LANE_4 0x505 |
| #define R_DPHY_RDWR_RX_LANE0_LANE_5 0x506 |
| #define R_DPHY_RDWR_RX_LANE0_LANE_6 0x507 |
| #define R_DPHY_RDWR_RX_LANE0_LANE_7 0x508 |
| #define R_DPHY_RDWR_RX_LANE0_LANE_8 0x509 |
| #define R_DPHY_RDWR_RX_LANE0_LANE_9 0x50A |
| #define R_DPHY_RDWR_RX_LANE0_LANE_12 0x50D |
| #define R_DPHY_RD_RX_LANE0_LANE_0 0x52B |
| #define R_DPHY_RD_RX_LANE0_LANE_1 0x52C |
| #define R_DPHY_RD_RX_LANE0_LANE_2 0x52D |
| #define R_DPHY_RD_RX_LANE0_LANE_3 0x52E |
| #define R_DPHY_RD_RX_LANE0_LANE_4 0x52F |
| #define R_DPHY_RD_RX_LANE0_LANE_5 0x530 |
| #define R_DPHY_RD_RX_LANE0_LANE_6 0x531 |
| #define R_DPHY_RD_RX_LANE0_LANE_7 0x532 |
| #define R_DPHY_RD_RX_LANE0_LANE_8 0x533 |
| #define R_DPHY_RD_RX_LANE0_LANE_9 0x534 |
| #define R_DPHY_RD_RX_LANE0_AFE_OBS_2 0x556 |
| #define R_DPHY_RD_TX_LANE0_AFE_OBS_3 0x557 |
| #define R_DPHY_RDWR_RX_LANE0_OFFSET_CAL_0 0x57B |
| #define R_DPHY_RDWR_RX_LANE0_OFFSET_CAL_1 0x57C |
| #define R_DPHY_RDWR_RX_LANE0_OFFSET_CAL_2 0x57D |
| #define R_DPHY_RDWR_RX_LANE0_OFFSET_CAL_3 0x57E |
| #define R_DPHY_RD_RX_LANE0_OFFSET_CAL_0 0x59F |
| #define R_DPHY_RD_RX_LANE0_OFFSET_CAL_1 0x5A0 |
| #define R_DPHY_RD_RX_LANE0_OFFSET_CAL_2 0x5A1 |
| #define R_DPHY_RD_RX_LANE0_OFFSET_CAL_3 0x5A2 |
| #define R_DPHY_RD_RX_LANE0_DDL_0 0x5E0 |
| #define R_DPHY_RD_RX_LANE0_DDL_1 0x5E1 |
| #define R_DPHY_RD_RX_LANE0_DDL_2 0x5E2 |
| #define R_DPHY_RD_RX_LANE0_DDL_3 0x5E3 |
| #define R_DPHY_RD_RX_LANE0_DDL_4 0x5E4 |
| #define R_DPHY_RD_RX_LANE0_DDL_5 0x5E5 |
| #define R_DPHY_RD_RX_LANE0_DDL_6 0x5E6 |
| #define R_DPHY_RD_RX_LANE0_DDL_7 0x5E7 |
| #define R_DPHY_RDWR_RX_LANE0_DDL_0 0x606 |
| #define R_DPHY_RDWR_RX_LANE0_DDL_1 0x607 |
| #define R_DPHY_RDWR_RX_LANE0_DDL_2 0x608 |
| #define R_DPHY_RDWR_RX_LANE0_DDL_3 0x609 |
| #define R_DPHY_RDWR_RX_LANE0_DDL_4 0x60A |
| #define R_DPHY_RDWR_RX_LANE0_DDL_5 0x60B |
| #define R_DPHY_RDWR_RX_LANE0_DDL_6 0x60C |
| #define R_DPHY_RDWR_RX_LANE1_LANE_0 0x701 |
| #define R_DPHY_RDWR_RX_LANE1_LANE_1 0x702 |
| #define R_DPHY_RDWR_RX_LANE1_LANE_3 0x704 |
| #define R_DPHY_RDWR_RX_LANE1_LANE_4 0x705 |
| #define R_DPHY_RDWR_RX_LANE1_LANE_6 0x707 |
| #define R_DPHY_RDWR_RX_LANE1_LANE_7 0x708 |
| #define R_DPHY_RDWR_RX_LANE1_LANE_8 0x709 |
| #define R_DPHY_RDWR_RX_LANE1_LANE_9 0x70A |
| #define R_DPHY_RDWR_RX_LANE1_LANE_10 0x70B |
| #define R_DPHY_RDWR_RX_LANE1_LANE_11 0x70C |
| #define R_DPHY_RDWR_RX_LANE1_LANE_12 0x70D |
| #define R_DPHY_RD_RX_LANE1_LANE_0 0x72B |
| #define R_DPHY_RD_RX_LANE1_LANE_2 0x72D |
| #define R_DPHY_RD_RX_LANE1_LANE_3 0x72E |
| #define R_DPHY_RD_RX_LANE1_LANE_4 0x72F |
| #define R_DPHY_RD_RX_LANE1_LANE_5 0x730 |
| #define R_DPHY_RD_RX_LANE1_LANE_6 0x731 |
| #define R_DPHY_RD_RX_LANE1_LANE_7 0x732 |
| #define R_DPHY_RD_RX_LANE1_LANE_8 0x733 |
| #define R_DPHY_RD_RX_LANE1_LANE_9 0x734 |
| #define R_DPHY_RD_RX_LANE1_LANE_10 0x735 |
| #define R_DPHY_RDWR_RX_LANE1_OFFSET_CAL_0 0x77B |
| #define R_DPHY_RDWR_RX_LANE1_OFFSET_CAL_1 0x77C |
| #define R_DPHY_RDWR_RX_LANE1_OFFSET_CAL_2 0x77D |
| #define R_DPHY_RDWR_RX_LANE1_OFFSET_CAL_3 0x77E |
| #define R_DPHY_RD_RX_LANE1_OFFSET_CAL_0 0x79F |
| #define R_DPHY_RD_RX_LANE1_OFFSET_CAL_1 0x7A0 |
| #define R_DPHY_RD_RX_LANE1_OFFSET_CAL_2 0x7A1 |
| #define R_DPHY_RD_RX_LANE1_OFFSET_CAL_3 0x7A2 |
| #define R_DPHY_RD_RX_LANE1_DDL_0 0x7E0 |
| #define R_DPHY_RD_RX_LANE1_DDL_1 0x7E1 |
| #define R_DPHY_RD_RX_LANE1_DDL_2 0x7E2 |
| #define R_DPHY_RD_RX_LANE1_DDL_3 0x7E3 |
| #define R_DPHY_RD_RX_LANE1_DDL_4 0x7E4 |
| #define R_DPHY_RD_RX_LANE1_DDL_5 0x7E5 |
| #define R_DPHY_RDWR_RX_LANE1_DDL_0 0x806 |
| #define R_DPHY_RDWR_RX_LANE1_DDL_1 0x807 |
| #define R_DPHY_RDWR_RX_LANE1_DDL_4 0x80A |
| #define R_DPHY_RDWR_RX_LANE1_DDL_5 0x80B |
| #define R_DPHY_RDWR_RX_LANE1_DDL_6 0x80C |
| #define R_DPHY_RDWR_RX_LANE2_LANE_0 0x901 |
| #define R_DPHY_RDWR_RX_LANE2_LANE_1 0x902 |
| #define R_DPHY_RDWR_RX_LANE2_LANE_3 0x904 |
| #define R_DPHY_RDWR_RX_LANE2_LANE_4 0x905 |
| #define R_DPHY_RDWR_RX_LANE2_LANE_6 0x907 |
| #define R_DPHY_RDWR_RX_LANE2_LANE_7 0x908 |
| #define R_DPHY_RDWR_RX_LANE2_LANE_8 0x909 |
| #define R_DPHY_RDWR_RX_LANE2_LANE_9 0x90A |
| #define R_DPHY_RDWR_RX_LANE2_LANE_10 0x90B |
| #define R_DPHY_RDWR_RX_LANE2_LANE_11 0x90C |
| #define R_DPHY_RDWR_RX_LANE2_LANE_12 0x90D |
| #define R_DPHY_RD_RX_LANE2_LANE_0 0x92B |
| #define R_DPHY_RD_RX_LANE2_LANE_2 0x92D |
| #define R_DPHY_RD_RX_LANE2_LANE_3 0x92E |
| #define R_DPHY_RD_RX_LANE2_LANE_4 0x92F |
| #define R_DPHY_RD_RX_LANE2_LANE_5 0x930 |
| #define R_DPHY_RD_RX_LANE2_LANE_6 0x931 |
| #define R_DPHY_RD_RX_LANE2_LANE_7 0x932 |
| #define R_DPHY_RD_RX_LANE2_LANE_8 0x933 |
| #define R_DPHY_RD_RX_LANE2_LANE_9 0x934 |
| #define R_DPHY_RD_RX_LANE2_LANE_10 0x935 |
| #define R_DPHY_RDWR_RX_LANE2_OFFSET_CAL_0 0x97B |
| #define R_DPHY_RDWR_RX_LANE2_OFFSET_CAL_1 0x97C |
| #define R_DPHY_RDWR_RX_LANE2_OFFSET_CAL_2 0x97D |
| #define R_DPHY_RDWR_RX_LANE2_OFFSET_CAL_3 0x97E |
| #define R_DPHY_RD_RX_LANE2_OFFSET_CAL_0 0x99F |
| #define R_DPHY_RD_RX_LANE2_OFFSET_CAL_1 0x9A0 |
| #define R_DPHY_RD_RX_LANE2_OFFSET_CAL_2 0x9A1 |
| #define R_DPHY_RD_RX_LANE2_OFFSET_CAL_3 0x9A2 |
| #define R_DPHY_RD_RX_LANE2_DDL_0 0x9E0 |
| #define R_DPHY_RD_RX_LANE2_DDL_1 0x9E1 |
| #define R_DPHY_RD_RX_LANE2_DDL_2 0x9E2 |
| #define R_DPHY_RD_RX_LANE2_DDL_3 0x9E3 |
| #define R_DPHY_RD_RX_LANE2_DDL_4 0x9E4 |
| #define R_DPHY_RD_RX_LANE2_DDL_5 0x9E5 |
| #define R_DPHY_RDWR_RX_LANE2_DDL_0 0xA06 |
| #define R_DPHY_RDWR_RX_LANE2_DDL_1 0xA07 |
| #define R_DPHY_RDWR_RX_LANE2_DDL_4 0xA0A |
| #define R_DPHY_RDWR_RX_LANE2_DDL_5 0xA0B |
| #define R_DPHY_RDWR_RX_LANE2_DDL_6 0xA0C |
| #define R_DPHY_RDWR_RX_LANE3_LANE_0 0xB01 |
| #define R_DPHY_RDWR_RX_LANE3_LANE_1 0xB02 |
| #define R_DPHY_RDWR_RX_LANE3_LANE_3 0xB04 |
| #define R_DPHY_RDWR_RX_LANE3_LANE_4 0xB05 |
| #define R_DPHY_RDWR_RX_LANE3_LANE_6 0xB07 |
| #define R_DPHY_RDWR_RX_LANE3_LANE_7 0xB08 |
| #define R_DPHY_RDWR_RX_LANE3_LANE_8 0xB09 |
| #define R_DPHY_RDWR_RX_LANE3_LANE_9 0xB0A |
| #define R_DPHY_RDWR_RX_LANE3_LANE_10 0xB0B |
| #define R_DPHY_RDWR_RX_LANE3_LANE_11 0xB0C |
| #define R_DPHY_RDWR_RX_LANE3_LANE_12 0xB0D |
| #define R_DPHY_RD_RX_LANE3_LANE_0 0xB2B |
| #define R_DPHY_RD_RX_LANE3_LANE_2 0xB2D |
| #define R_DPHY_RD_RX_LANE3_LANE_3 0xB2E |
| #define R_DPHY_RD_RX_LANE3_LANE_4 0xB2F |
| #define R_DPHY_RD_RX_LANE3_LANE_5 0xB30 |
| #define R_DPHY_RD_RX_LANE3_LANE_6 0xB31 |
| #define R_DPHY_RD_RX_LANE3_LANE_7 0xB32 |
| #define R_DPHY_RD_RX_LANE3_LANE_8 0xB33 |
| #define R_DPHY_RD_RX_LANE3_LANE_9 0xB34 |
| #define R_DPHY_RD_RX_LANE3_LANE_10 0xB35 |
| #define R_DPHY_RDWR_RX_LANE3_OFFSET_CAL_0 0xB7B |
| #define R_DPHY_RDWR_RX_LANE3_OFFSET_CAL_1 0xB7C |
| #define R_DPHY_RDWR_RX_LANE3_OFFSET_CAL_2 0xB7D |
| #define R_DPHY_RDWR_RX_LANE3_OFFSET_CAL_3 0xB7E |
| #define R_DPHY_RD_RX_LANE3_OFFSET_CAL_0 0xB9F |
| #define R_DPHY_RD_RX_LANE3_OFFSET_CAL_1 0xBA0 |
| #define R_DPHY_RD_RX_LANE3_OFFSET_CAL_2 0xBA1 |
| #define R_DPHY_RD_RX_LANE3_OFFSET_CAL_3 0xBA2 |
| #define R_DPHY_RD_RX_LANE3_DDL_0 0xBE0 |
| #define R_DPHY_RD_RX_LANE3_DDL_1 0xBE1 |
| #define R_DPHY_RD_RX_LANE3_DDL_2 0xBE2 |
| #define R_DPHY_RD_RX_LANE3_DDL_3 0xBE3 |
| #define R_DPHY_RD_RX_LANE3_DDL_4 0xBE4 |
| #define R_DPHY_RD_RX_LANE3_DDL_5 0xBE5 |
| #define R_DPHY_RDWR_RX_LANE3_DDL_0 0xC06 |
| #define R_DPHY_RDWR_RX_LANE3_DDL_1 0xC07 |
| #define R_DPHY_RDWR_RX_LANE3_DDL_4 0xC0A |
| #define R_DPHY_RDWR_RX_LANE3_DDL_5 0xC0B |
| #define R_DPHY_RDWR_RX_LANE3_DDL_6 0xC0C |
| |
| #endif /* MIPICSI_RX_DPHY_H_ */ |
