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android / kernel / arm64 / refs/tags/android-q-preview-4_r0.4 / . / drivers / mipicsi / mipicsi_debug.c
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/*
* Copyright (c) 2016, Intel Corporation. All rights reserved.
*
* Author: Archana Vohra <archana.vohra@intel.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of Intel nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include "mipicsi_device.h"
#include "mipicsi_util.h"
#include "mipicsi_debug.h"
#include "mipicsi_rx_dphy.h"
#include "mipicsi_tx_dphy.h"
#include <soc/mnh/mnh-hwio-mipi-rx.h>
#include <soc/mnh/mnh-hwio-mipi-tx.h>
uint16_t valid_rx_ctl_offsets[] = {
HWIO_MIPI_RX_VERSION_REGOFF,
HWIO_MIPI_RX_N_LANES_REGOFF,
HWIO_MIPI_RX_CSI2_RESETN_REGOFF,
HWIO_MIPI_RX_INT_ST_MAIN_REGOFF,
HWIO_MIPI_RX_DATA_IDS_1_REGOFF,
HWIO_MIPI_RX_DATA_IDS_2_REGOFF,
HWIO_MIPI_RX_PHY_SHUTDOWNZ_REGOFF,
HWIO_MIPI_RX_DPHY_RSTZ_REGOFF,
HWIO_MIPI_RX_PHY_RX_REGOFF,
HWIO_MIPI_RX_PHY_STOPSTATE_REGOFF,
HWIO_MIPI_RX_PHY_TEST_CTRL0_REGOFF,
HWIO_MIPI_RX_PHY_TEST_CTRL1_REGOFF,
HWIO_MIPI_RX_PHY_CAL_REGOFF,
HWIO_MIPI_RX_INT_ST_PHY_FATAL_REGOFF,
HWIO_MIPI_RX_INT_MSK_PHY_FATAL_REGOFF,
HWIO_MIPI_RX_INT_FORCE_PHY_FATAL_REGOFF,
HWIO_MIPI_RX_INT_ST_PKT_FATAL_REGOFF,
HWIO_MIPI_RX_INT_MSK_PKT_FATAL_REGOFF,
HWIO_MIPI_RX_INT_FORCE_PKT_FATAL_REGOFF,
HWIO_MIPI_RX_INT_ST_FRAME_FATAL_REGOFF,
HWIO_MIPI_RX_INT_MSK_FRAME_FATAL_REGOFF,
HWIO_MIPI_RX_INT_FORCE_FRAME_FATAL_REGOFF,
HWIO_MIPI_RX_INT_ST_PHY_REGOFF,
HWIO_MIPI_RX_INT_MSK_PHY_REGOFF,
HWIO_MIPI_RX_INT_FORCE_PHY_REGOFF,
HWIO_MIPI_RX_INT_ST_PKT_REGOFF,
HWIO_MIPI_RX_INT_MSK_PKT_REGOFF,
HWIO_MIPI_RX_INT_FORCE_PKT_REGOFF,
HWIO_MIPI_RX_INT_ST_LINE_REGOFF,
HWIO_MIPI_RX_INT_MSK_LINE_REGOFF,
HWIO_MIPI_RX_INT_FORCE_LINE_REGOFF
};
uint16_t valid_tx_ctl_offsets[] = {
HWIO_MIPI_TX_VERSION_REGOFF,
HWIO_MIPI_TX_CSI2_RESETN_REGOFF,
HWIO_MIPI_TX_INT_ST_MAIN_REGOFF,
HWIO_MIPI_TX_INT_ST_VPG_REGOFF,
HWIO_MIPI_TX_INT_ST_IDI_REGOFF,
HWIO_MIPI_TX_INT_ST_PHY_REGOFF,
HWIO_MIPI_TX_INT_MASK_N_VPG_REGOFF,
HWIO_MIPI_TX_INT_FORCE_VPG_REGOFF,
HWIO_MIPI_TX_INT_MASK_N_IDI_REGOFF,
HWIO_MIPI_TX_INT_FORCE_IDI_REGOFF,
HWIO_MIPI_TX_INT_MASK_N_PHY_REGOFF,
HWIO_MIPI_TX_INT_FORCE_PHY_REGOFF,
HWIO_MIPI_TX_VPG_CTRL_REGOFF,
HWIO_MIPI_TX_VPG_STATUS_REGOFF,
HWIO_MIPI_TX_VPG_MODE_CFG_REGOFF,
HWIO_MIPI_TX_VPG_PKT_CFG_REGOFF,
HWIO_MIPI_TX_VPG_PKT_SIZE_REGOFF,
HWIO_MIPI_TX_VPG_HSA_TIME_REGOFF,
HWIO_MIPI_TX_VPG_HBP_TIME_REGOFF,
HWIO_MIPI_TX_VPG_HLINE_TIME_REGOFF,
HWIO_MIPI_TX_VPG_VSA_LINES_REGOFF,
HWIO_MIPI_TX_VPG_VBP_LINES_REGOFF,
HWIO_MIPI_TX_VPG_VFP_LINES_REGOFF,
HWIO_MIPI_TX_VPG_ACT_LINES_REGOFF,
HWIO_MIPI_TX_VPG_MAX_FRAME_NUM_REGOFF,
HWIO_MIPI_TX_VPG_START_LINE_NUM_REGOFF,
HWIO_MIPI_TX_VPG_STEP_LINE_NUM_REGOFF,
HWIO_MIPI_TX_PHY_RSTZ_REGOFF,
HWIO_MIPI_TX_PHY_IF_CFG_REGOFF,
HWIO_MIPI_TX_LPCLK_CTRL_REGOFF,
HWIO_MIPI_TX_PHY_ULPS_CTRL_REGOFF,
HWIO_MIPI_TX_CLKMGR_CFG_REGOFF,
HWIO_MIPI_TX_PHY_TX_TRIGGERS_REGOFF,
HWIO_MIPI_TX_PHY_CAL_REGOFF,
HWIO_MIPI_TX_TO_CNT_CFG_REGOFF,
HWIO_MIPI_TX_PHY_STATUS_REGOFF,
HWIO_MIPI_TX_PHY0_TST_CTRL0_REGOFF,
HWIO_MIPI_TX_PHY0_TST_CTRL1_REGOFF
};
uint16_t valid_rx_g3dphy_offsets[] = {
R_DPHY_TESTCODE_X_REG,
R_DPHY_RDWR_RX_SYS_0,
R_DPHY_RDWR_RX_SYS_1,
R_DPHY_RDWR_RX_SYS_2,
R_DPHY_RDWR_RX_SYS_3,
R_DPHY_RDWR_RX_SYS_4,
R_DPHY_RDWR_RX_SYS_5,
R_DPHY_RDWR_RX_SYS_6,
R_DPHY_RDWR_RX_SYS_7,
R_DPHY_RDWR_RX_SYS_8,
R_DPHY_RDWR_RX_SYS_9,
R_DPHY_RD_RX_SYS_0,
R_DPHY_RD_RX_SYS_1,
R_DPHY_RD_RX_SYS_2,
R_DPHY_RD_RX_SYS_3,
R_DPHY_RD_CONT_DATA_0,
R_DPHY_RD_CONT_DATA_1,
R_DPHY_RD_RX_SYS_4,
R_DPHY_RDWR_RX_SYS_DDL_0,
R_DPHY_RDWR_RX_SYS_DDL_1,
R_DPHY_RDWR_RX_SYS_DDL_2,
R_DPHY_RDWR_RX_SYSTIMERS_0,
R_DPHY_RDWR_RX_SYSTIMERS_1,
R_DPHY_RDWR_RX_SYSTIMERS_2,
R_DPHY_RDWR_RX_SYSTIMERS_3,
R_DPHY_RDWR_RX_SYSTIMERS_4,
R_DPHY_RDWR_RX_SYSTIMERS_5,
R_DPHY_RDWR_RX_SYSTIMERS_6,
R_DPHY_RDWR_RX_SYSTIMERS_7,
R_DPHY_RDWR_RX_SYSTIMERS_8,
R_DPHY_RDWR_RX_SYSTIMERS_9,
R_DPHY_RDWR_RX_SYSTIMERS_10,
R_DPHY_RDWR_RX_SYSTIMERS_11,
R_DPHY_RD_RX_SYSTIMERS_0,
R_DPHY_RD_RX_RX_STARTUP_OBS_0,
R_DPHY_RD_RX_RX_STARTUP_OBS_1,
R_DPHY_RD_RX_RX_STARTUP_OBS_2,
R_DPHY_RD_RX_RX_STARTUP_OBS_3,
R_DPHY_RD_RX_RX_STARTUP_OBS_4,
R_DPHY_RDWR_RX_RX_STARTUP_OVR_0,
R_DPHY_RDWR_RX_RX_STARTUP_OVR_1,
R_DPHY_RDWR_RX_RX_STARTUP_OVR_2,
R_DPHY_RDWR_RX_RX_STARTUP_OVR_3,
R_DPHY_RDWR_RX_RX_STARTUP_OVR_4,
R_DPHY_RDWR_RX_RX_STARTUP_OVR_5,
R_DPHY_RDWR_RX_RX_STARTUP_OVR_17,
R_DPHY_RDWR_RX_BIST_0,
R_DPHY_RDWR_RX_BIST_1,
R_DPHY_RDWR_RX_BIST_2,
R_DPHY_RDWR_RX_BIST_3,
R_DPHY_RDWR_RX_BIST_4,
R_DPHY_RDWR_RX_BIST_OVR_0,
R_DPHY_RDWR_RX_BIST_OVR_1,
R_DPHY_RDWR_RX_BIST_OVR_2,
R_DPHY_RDWR_RX_BIST_OVR_3,
R_DPHY_RDWR_RX_BIST_PIPE_TIMER,
R_DPHY_RD_RX_BIST_0,
R_DPHY_RD_RX_BIST_1,
R_DPHY_RD_RX_BIST_2,
R_DPHY_RD_RX_BIST_3,
R_DPHY_RD_RX_BIST_13,
R_DPHY_RDWR_RX_RX_DUAL_PHY_0,
R_DPHY_RD_RX_DUAL_PHY_0,
R_DPHY_RD_RX_DUAL_PHY_1,
R_DPHY_RD_RX_DUAL_PHY_2,
R_DPHY_RDWR_RX_PLL_0,
R_DPHY_RDWR_RX_PLL_1,
R_DPHY_RDWR_RX_PLL_2,
R_DPHY_RDWR_RX_PLL_3,
R_DPHY_RDWR_RX_PLL_4,
R_DPHY_RDWR_RX_PLL_5,
R_DPHY_RDWR_RX_PLL_6,
R_DPHY_RDWR_RX_PLL_7,
R_DPHY_RDWR_RX_PLL_8,
R_DPHY_RDWR_RX_PLL_9,
R_DPHY_RDWR_RX_PLL_10,
R_DPHY_RDWR_RX_PLL_11,
R_DPHY_RDWR_RX_PLL_12,
R_DPHY_RDWR_RX_PLL_13,
R_DPHY_RDWR_RX_PLL_14,
R_DPHY_RDWR_RX_PLL_15,
R_DPHY_RDWR_RX_PLL_16,
R_DPHY_RDWR_RX_PLL_17,
R_DPHY_RDWR_RX_PLL_18,
R_DPHY_RDWR_RX_PLL_19,
R_DPHY_RDWR_RX_PLL_20,
R_DPHY_RDWR_RX_PLL_21,
R_DPHY_RDWR_RX_PLL_22,
R_DPHY_RDWR_RX_PLL_23,
R_DPHY_RDWR_RX_PLL_24,
R_DPHY_RDWR_RX_PLL_25,
R_DPHY_RDWR_RX_PLL_26,
R_DPHY_RDWR_RX_PLL_27,
R_DPHY_RDWR_RX_PLL_28,
R_DPHY_RDWR_RX_PLL_29,
R_DPHY_RDWR_RX_PLL_30,
R_DPHY_RDWR_RX_PLL_31,
R_DPHY_RD_RX_PLL_0,
R_DPHY_RD_RX_PLL_1,
R_DPHY_RD_RX_PLL_2,
R_DPHY_RD_RX_PLL_3,
R_DPHY_RD_RX_PLL_4,
R_DPHY_RDWR_RX_CB_0,
R_DPHY_RDWR_RX_CB_1,
R_DPHY_RDWR_RX_CB_2,
R_DPHY_RDWR_RX_CB_3,
R_DPHY_RDWR_RX_CB_4,
R_DPHY_RDWR_RX_CB_5,
R_DPHY_RDWR_RX_CB_6,
R_DPHY_RD_RX_ANA_CB_0,
R_DPHY_RDWR_RX_DAC_0,
R_DPHY_RDWR_RX_DAC_1,
R_DPHY_RDWR_RX_DAC_2,
R_DPHY_RDWR_RX_DAC_3,
R_DPHY_RD_RX_DAC_0,
R_DPHY_RD_RX_DAC_1,
R_DPHY_RD_RX_DAC_2,
R_DPHY_RDWR_RX_TERM_CAL_0,
R_DPHY_RDWR_RX_TERM_CAL_1,
R_DPHY_RDWR_RX_TERM_CAL_2,
R_DPHY_RD_RX_TERM_CAL_0,
R_DPHY_RD_RX_TERM_CAL_1,
R_DPHY_RD_RX_TERM_CAL_2,
R_DPHY_RDWR_RX_NOREXTTUNE_0,
R_DPHY_RDWR_RX_NOREXTTUNE_1,
R_DPHY_RDWR_RX_NOREXTTUNE_2,
R_DPHY_RDWR_RX_NOREXTTUNE_3,
R_DPHY_RDWR_RX_NOREXTTUNE_4,
R_DPHY_RDWR_RX_NOREXTTUNE_5,
R_DPHY_RDWR_RX_NOREXTTUNE_6,
R_DPHY_RD_RX_NOREXTTUNE_0,
R_DPHY_RD_RX_NOREXTTUNE_1,
R_DPHY_RD_RX_NOREXTTUNE_2,
R_DPHY_RD_RX_NOREXTTUNE_3,
R_DPHY_RD_RX_NOREXTTUNE_4,
R_DPHY_RDWR_RX_CLKLANE_LANE_0,
R_DPHY_RDWR_RX_CLKLANE_LANE_1,
R_DPHY_RDWR_RX_CLKLANE_LANE_3,
R_DPHY_RDWR_RX_CLKLANE_LANE_4,
R_DPHY_RDWR_RX_CLKLANE_LANE_6,
R_DPHY_RDWR_RX_CLKLANE_LANE_7,
R_DPHY_RDWR_RX_CLKLANE_LANE_8,
R_DPHY_RD_RX_CLKLANE_LANE_0,
R_DPHY_RD_RX_CLKLANE_LANE_1,
R_DPHY_RD_RX_CLKLANE_LANE_2,
R_DPHY_RD_RX_CLKLANE_LANE_3,
R_DPHY_RDWR_RX_CLKLANE_OFFSET_CAL_0,
R_DPHY_RDWR_RX_CLKLANE_OFFSET_CAL_1,
R_DPHY_RD_RX_CLKLANE_OFFSET_CAL_0,
R_DPHY_RD_RX_CLKLANE_OFFSET_CAL_1,
R_DPHY_RD_RX_CLKLANE_OFFSET_CAL_2,
R_DPHY_RDWR_RX_LANE0_LANE_0,
R_DPHY_RDWR_RX_LANE0_LANE_1,
R_DPHY_RDWR_RX_LANE0_LANE_3,
R_DPHY_RDWR_RX_LANE0_LANE_4,
R_DPHY_RDWR_RX_LANE0_LANE_5,
R_DPHY_RDWR_RX_LANE0_LANE_6,
R_DPHY_RDWR_RX_LANE0_LANE_7,
R_DPHY_RDWR_RX_LANE0_LANE_8,
R_DPHY_RDWR_RX_LANE0_LANE_9,
R_DPHY_RDWR_RX_LANE0_LANE_12,
R_DPHY_RD_RX_LANE0_LANE_0,
R_DPHY_RD_RX_LANE0_LANE_1,
R_DPHY_RD_RX_LANE0_LANE_2,
R_DPHY_RD_RX_LANE0_LANE_3,
R_DPHY_RD_RX_LANE0_LANE_4,
R_DPHY_RD_RX_LANE0_LANE_5,
R_DPHY_RD_RX_LANE0_LANE_6,
R_DPHY_RD_RX_LANE0_LANE_7,
R_DPHY_RD_RX_LANE0_LANE_8,
R_DPHY_RD_RX_LANE0_LANE_9,
R_DPHY_RD_RX_LANE0_AFE_OBS_2,
R_DPHY_RD_TX_LANE0_AFE_OBS_3,
R_DPHY_RDWR_RX_LANE0_OFFSET_CAL_0,
R_DPHY_RDWR_RX_LANE0_OFFSET_CAL_1,
R_DPHY_RDWR_RX_LANE0_OFFSET_CAL_2,
R_DPHY_RDWR_RX_LANE0_OFFSET_CAL_3,
R_DPHY_RD_RX_LANE0_OFFSET_CAL_0,
R_DPHY_RD_RX_LANE0_OFFSET_CAL_1,
R_DPHY_RD_RX_LANE0_OFFSET_CAL_2,
R_DPHY_RD_RX_LANE0_OFFSET_CAL_3,
R_DPHY_RD_RX_LANE0_DDL_0,
R_DPHY_RD_RX_LANE0_DDL_1,
R_DPHY_RD_RX_LANE0_DDL_2,
R_DPHY_RD_RX_LANE0_DDL_3,
R_DPHY_RD_RX_LANE0_DDL_4,
R_DPHY_RD_RX_LANE0_DDL_5,
R_DPHY_RD_RX_LANE0_DDL_6,
R_DPHY_RD_RX_LANE0_DDL_7,
R_DPHY_RDWR_RX_LANE0_DDL_0,
R_DPHY_RDWR_RX_LANE0_DDL_1,
R_DPHY_RDWR_RX_LANE0_DDL_2,
R_DPHY_RDWR_RX_LANE0_DDL_3,
R_DPHY_RDWR_RX_LANE0_DDL_4,
R_DPHY_RDWR_RX_LANE0_DDL_5,
R_DPHY_RDWR_RX_LANE0_DDL_6,
R_DPHY_RDWR_RX_LANE1_LANE_0,
R_DPHY_RDWR_RX_LANE1_LANE_1,
R_DPHY_RDWR_RX_LANE1_LANE_3,
R_DPHY_RDWR_RX_LANE1_LANE_4,
R_DPHY_RDWR_RX_LANE1_LANE_6,
R_DPHY_RDWR_RX_LANE1_LANE_7,
R_DPHY_RDWR_RX_LANE1_LANE_8,
R_DPHY_RDWR_RX_LANE1_LANE_9,
R_DPHY_RDWR_RX_LANE1_LANE_10,
R_DPHY_RDWR_RX_LANE1_LANE_11,
R_DPHY_RDWR_RX_LANE1_LANE_12,
R_DPHY_RD_RX_LANE1_LANE_0,
R_DPHY_RD_RX_LANE1_LANE_2,
R_DPHY_RD_RX_LANE1_LANE_3,
R_DPHY_RD_RX_LANE1_LANE_4,
R_DPHY_RD_RX_LANE1_LANE_5,
R_DPHY_RD_RX_LANE1_LANE_6,
R_DPHY_RD_RX_LANE1_LANE_7,
R_DPHY_RD_RX_LANE1_LANE_8,
R_DPHY_RD_RX_LANE1_LANE_9,
R_DPHY_RD_RX_LANE1_LANE_10,
R_DPHY_RDWR_RX_LANE1_OFFSET_CAL_0,
R_DPHY_RDWR_RX_LANE1_OFFSET_CAL_1,
R_DPHY_RDWR_RX_LANE1_OFFSET_CAL_2,
R_DPHY_RDWR_RX_LANE1_OFFSET_CAL_3,
R_DPHY_RD_RX_LANE1_OFFSET_CAL_0,
R_DPHY_RD_RX_LANE1_OFFSET_CAL_1,
R_DPHY_RD_RX_LANE1_OFFSET_CAL_2,
R_DPHY_RD_RX_LANE1_OFFSET_CAL_3,
R_DPHY_RD_RX_LANE1_DDL_0,
R_DPHY_RD_RX_LANE1_DDL_1,
R_DPHY_RD_RX_LANE1_DDL_2,
R_DPHY_RD_RX_LANE1_DDL_3,
R_DPHY_RD_RX_LANE1_DDL_4,
R_DPHY_RD_RX_LANE1_DDL_5,
R_DPHY_RDWR_RX_LANE1_DDL_0,
R_DPHY_RDWR_RX_LANE1_DDL_1,
R_DPHY_RDWR_RX_LANE1_DDL_4,
R_DPHY_RDWR_RX_LANE1_DDL_5,
R_DPHY_RDWR_RX_LANE1_DDL_6,
R_DPHY_RDWR_RX_LANE2_LANE_0,
R_DPHY_RDWR_RX_LANE2_LANE_1,
R_DPHY_RDWR_RX_LANE2_LANE_3,
R_DPHY_RDWR_RX_LANE2_LANE_4,
R_DPHY_RDWR_RX_LANE2_LANE_6,
R_DPHY_RDWR_RX_LANE2_LANE_7,
R_DPHY_RDWR_RX_LANE2_LANE_8,
R_DPHY_RDWR_RX_LANE2_LANE_9,
R_DPHY_RDWR_RX_LANE2_LANE_10,
R_DPHY_RDWR_RX_LANE2_LANE_11,
R_DPHY_RDWR_RX_LANE2_LANE_12,
R_DPHY_RD_RX_LANE2_LANE_0,
R_DPHY_RD_RX_LANE2_LANE_2,
R_DPHY_RD_RX_LANE2_LANE_3,
R_DPHY_RD_RX_LANE2_LANE_4,
R_DPHY_RD_RX_LANE2_LANE_5,
R_DPHY_RD_RX_LANE2_LANE_6,
R_DPHY_RD_RX_LANE2_LANE_7,
R_DPHY_RD_RX_LANE2_LANE_8,
R_DPHY_RD_RX_LANE2_LANE_9,
R_DPHY_RD_RX_LANE2_LANE_10,
R_DPHY_RDWR_RX_LANE2_OFFSET_CAL_0,
R_DPHY_RDWR_RX_LANE2_OFFSET_CAL_1,
R_DPHY_RDWR_RX_LANE2_OFFSET_CAL_2,
R_DPHY_RDWR_RX_LANE2_OFFSET_CAL_3,
R_DPHY_RD_RX_LANE2_OFFSET_CAL_0,
R_DPHY_RD_RX_LANE2_OFFSET_CAL_1,
R_DPHY_RD_RX_LANE2_OFFSET_CAL_2,
R_DPHY_RD_RX_LANE2_OFFSET_CAL_3,
R_DPHY_RD_RX_LANE2_DDL_0,
R_DPHY_RD_RX_LANE2_DDL_1,
R_DPHY_RD_RX_LANE2_DDL_2,
R_DPHY_RD_RX_LANE2_DDL_3,
R_DPHY_RD_RX_LANE2_DDL_4,
R_DPHY_RD_RX_LANE2_DDL_5,
R_DPHY_RDWR_RX_LANE2_DDL_0,
R_DPHY_RDWR_RX_LANE2_DDL_1,
R_DPHY_RDWR_RX_LANE2_DDL_4,
R_DPHY_RDWR_RX_LANE2_DDL_5,
R_DPHY_RDWR_RX_LANE2_DDL_6,
R_DPHY_RDWR_RX_LANE3_LANE_0,
R_DPHY_RDWR_RX_LANE3_LANE_1,
R_DPHY_RDWR_RX_LANE3_LANE_3,
R_DPHY_RDWR_RX_LANE3_LANE_4,
R_DPHY_RDWR_RX_LANE3_LANE_6,
R_DPHY_RDWR_RX_LANE3_LANE_7,
R_DPHY_RDWR_RX_LANE3_LANE_8,
R_DPHY_RDWR_RX_LANE3_LANE_9,
R_DPHY_RDWR_RX_LANE3_LANE_10,
R_DPHY_RDWR_RX_LANE3_LANE_11,
R_DPHY_RDWR_RX_LANE3_LANE_12,
R_DPHY_RD_RX_LANE3_LANE_0,
R_DPHY_RD_RX_LANE3_LANE_2,
R_DPHY_RD_RX_LANE3_LANE_3,
R_DPHY_RD_RX_LANE3_LANE_4,
R_DPHY_RD_RX_LANE3_LANE_5,
R_DPHY_RD_RX_LANE3_LANE_6,
R_DPHY_RD_RX_LANE3_LANE_7,
R_DPHY_RD_RX_LANE3_LANE_8,
R_DPHY_RD_RX_LANE3_LANE_9,
R_DPHY_RD_RX_LANE3_LANE_10,
R_DPHY_RDWR_RX_LANE3_OFFSET_CAL_0,
R_DPHY_RDWR_RX_LANE3_OFFSET_CAL_1,
R_DPHY_RDWR_RX_LANE3_OFFSET_CAL_2,
R_DPHY_RDWR_RX_LANE3_OFFSET_CAL_3,
R_DPHY_RD_RX_LANE3_OFFSET_CAL_0,
R_DPHY_RD_RX_LANE3_OFFSET_CAL_1,
R_DPHY_RD_RX_LANE3_OFFSET_CAL_2,
R_DPHY_RD_RX_LANE3_OFFSET_CAL_3,
R_DPHY_RD_RX_LANE3_DDL_0,
R_DPHY_RD_RX_LANE3_DDL_1,
R_DPHY_RD_RX_LANE3_DDL_2,
R_DPHY_RD_RX_LANE3_DDL_3,
R_DPHY_RD_RX_LANE3_DDL_4,
R_DPHY_RD_RX_LANE3_DDL_5,
R_DPHY_RDWR_RX_LANE3_DDL_0,
R_DPHY_RDWR_RX_LANE3_DDL_1,
R_DPHY_RDWR_RX_LANE3_DDL_4,
R_DPHY_RDWR_RX_LANE3_DDL_5,
R_DPHY_RDWR_RX_LANE3_DDL_6,
};
uint16_t valid_tx_g3dphy_offsets[] = {
R_DPHY_TESTCODE_X_REG,
R_DPHY_RDWR_TX_SYS_0,
R_DPHY_RDWR_TX_SYS_1,
R_DPHY_RDWR_TX_SYS_2,
R_DPHY_RDWR_TX_SYS_3,
R_DPHY_RDWR_TX_SYS_8,
R_DPHY_RD_TX_SYS_0,
R_DPHY_RD_TX_SYS_1,
R_DPHY_RD_TX_SYS_2,
R_DPHY_RD_TX_SYS_3,
R_DPHY_RD_TX_SYS_4,
R_DPHY_RD_CONT_DATA_0,
R_DPHY_RD_CONT_DATA_1,
R_DPHY_RDWR_TX_SYSTIMERS_0,
R_DPHY_RDWR_TX_SYSTIMERS_1,
R_DPHY_RDWR_TX_SYSTIMERS_2,
R_DPHY_RDWR_TX_SYSTIMERS_3,
R_DPHY_RDWR_TX_SYSTIMERS_4,
R_DPHY_RDWR_TX_SYSTIMERS_5,
R_DPHY_RDWR_TX_SYSTIMERS_6,
R_DPHY_RDWR_TX_SYSTIMERS_7,
R_DPHY_RDWR_TX_SYSTIMERS_8,
R_DPHY_RDWR_TX_SYSTIMERS_9,
R_DPHY_RDWR_TX_SYSTIMERS_10,
R_DPHY_RDWR_TX_SYSTIMERS_11,
R_DPHY_RDWR_TX_SYSTIMERS_12,
R_DPHY_RDWR_TX_SYSTIMERS_13,
R_DPHY_RDWR_TX_SYSTIMERS_14,
R_DPHY_RDWR_TX_SYSTIMERS_15,
R_DPHY_RDWR_TX_SYSTIMERS_16,
R_DPHY_RDWR_TX_SYSTIMERS_17,
R_DPHY_RDWR_TX_SYSTIMERS_18,
R_DPHY_RDWR_TX_SYSTIMERS_19,
R_DPHY_RDWR_TX_SYSTIMERS_20,
R_DPHY_RDWR_TX_SYSTIMERS_21,
R_DPHY_RDWR_TX_SYSTIMERS_22,
R_DPHY_RDWR_TX_SYSTIMERS_23,
R_DPHY_RD_TX_SYSTIMERS_0,
R_DPHY_RD_TX_SYSTIMERS_1,
R_DPHY_RD_TX_SYSTIMERS_2,
R_DPHY_RD_TX_SYSTIMERS_3,
R_DPHY_RD_TX_SYSTIMERS_4,
R_DPHY_RD_TX_SYSTIMERS_5,
R_DPHY_RD_TX_SYSTIMERS_6,
R_DPHY_RD_TX_SYSTIMERS_7,
R_DPHY_RD_TX_SYSTIMERS_8,
R_DPHY_RD_TX_SYSTIMERS_9,
R_DPHY_RD_TX_SYSTIMERS_10,
R_DPHY_RD_TX_SYSTIMERS_11,
R_DPHY_RD_TX_SYSTIMERS_12,
R_DPHY_RD_TX_TX_STARTUP_OBS_0,
R_DPHY_RDWR_TX_TX_STARTUP_OVR_0,
R_DPHY_RDWR_TX_TX_STARTUP_OVR_1,
R_DPHY_RDWR_TX_DEEMPHASIS_0,
R_DPHY_RDWR_TX_DEEMPHASIS_1,
R_DPHY_RDWR_TX_DEEMPHASIS_2,
R_DPHY_RDWR_TX_DEEMPHASIS_3,
R_DPHY_RDWR_TX_DEEMPHASIS_4,
R_DPHY_RDWR_TX_DEEMPHASIS_5,
R_DPHY_RDWR_TX_DEEMPHASIS_6,
R_DPHY_RDWR_TX_DEEMPHASIS_7,
R_DPHY_RDWR_TX_DEEMPHASIS_8,
R_DPHY_RDWR_TX_DEEMPHASIS_9,
R_DPHY_RDWR_TX_DEEMPHASIS_10,
R_DPHY_RDWR_TX_DEEMPHASIS_11,
R_DPHY_RDWR_TX_DEEMPHASIS_12,
R_DPHY_RDWR_TX_DEEMPHASIS_13,
R_DPHY_RDWR_TX_DEEMPHASIS_14,
R_DPHY_RDWR_TX_DEEMPHASIS_15,
R_DPHY_RDWR_TX_DEEMPHASIS_CONST_0,
R_DPHY_RDWR_TX_DEEMPHASIS_CONST_1,
R_DPHY_RDWR_TX_DEEMPHASIS_CONST_2,
R_DPHY_RDWR_TX_DEEMPHASIS_CONST_3,
R_DPHY_RDWR_TX_DEEMPHASIS_OFF_CONTROL_0,
R_DPHY_RDWR_TX_DEEMPHASIS_OFF_CONTROL_1,
R_DPHY_RDWR_TX_DEEMPHASIS_OFF_CONTROL_2,
R_DPHY_RDWR_TX_BIST_PM_CONTROL,
R_DPHY_RD_TX_DEEMPHASIS_OBS_0,
R_DPHY_RD_TX_DEEMPHASIS_OBS_1,
R_DPHY_RDWR_TX_BIST_3,
R_DPHY_RDWR_TX_BIST_4,
R_DPHY_RDWR_TX_BIST_OVR_2,
R_DPHY_RDWR_TX_BIST_OVR_3,
R_DPHY_RDWR_TX_BIST_PIPE_TIMER,
R_DPHY_RDWR_TX_CHECK_ERROR_TIMER,
R_DPHY_RD_TX_BIST_0,
R_DPHY_RD_TX_BIST_1,
R_DPHY_RD_TX_BIST_2,
R_DPHY_RD_TX_BIST_3,
R_DPHY_RD_TX_BIST_4,
R_DPHY_RD_TX_BIST_5,
R_DPHY_RD_TX_BIST_6,
R_DPHY_RD_TX_BIST_7,
R_DPHY_RD_TX_BIST_8,
R_DPHY_RD_TX_BIST_9,
R_DPHY_RD_TX_BIST_10,
R_DPHY_RD_TX_BIST_11,
R_DPHY_RD_TX_BIST_12,
R_DPHY_RD_TX_BIST_13,
R_DPHY_RDWR_TX_TX_DUAL_PHY_0,
R_DPHY_RD_TX_TX_DUAL_PHY_0,
R_DPHY_RDWR_TX_PLL_0,
R_DPHY_RDWR_TX_PLL_1,
R_DPHY_RDWR_TX_PLL_2,
R_DPHY_RDWR_TX_PLL_3,
R_DPHY_RDWR_TX_PLL_4,
R_DPHY_RDWR_TX_PLL_5,
R_DPHY_RDWR_TX_PLL_6,
R_DPHY_RDWR_TX_PLL_7,
R_DPHY_RDWR_TX_PLL_8,
R_DPHY_RDWR_TX_PLL_9,
R_DPHY_RDWR_TX_PLL_10,
R_DPHY_RDWR_TX_PLL_11,
R_DPHY_RDWR_TX_PLL_12,
R_DPHY_RDWR_TX_PLL_13,
R_DPHY_RDWR_TX_PLL_14,
R_DPHY_RDWR_TX_PLL_15,
R_DPHY_RDWR_TX_PLL_16,
R_DPHY_RDWR_TX_PLL_17,
R_DPHY_RDWR_TX_PLL_18,
R_DPHY_RDWR_TX_PLL_19,
R_DPHY_RDWR_TX_PLL_20,
R_DPHY_RDWR_TX_PLL_21,
R_DPHY_RDWR_TX_PLL_22,
R_DPHY_RDWR_TX_PLL_23,
R_DPHY_RDWR_TX_PLL_24,
R_DPHY_RDWR_TX_PLL_25,
R_DPHY_RDWR_TX_PLL_26,
R_DPHY_RDWR_TX_PLL_27,
R_DPHY_RDWR_TX_PLL_28,
R_DPHY_RDWR_TX_PLL_29,
R_DPHY_RDWR_TX_PLL_30,
R_DPHY_RDWR_TX_PLL_31,
R_DPHY_RD_TX_PLL_0,
R_DPHY_RD_TX_PLL_1,
R_DPHY_RD_TX_PLL_2,
R_DPHY_RD_TX_PLL_3,
R_DPHY_RD_TX_PLL_4,
R_DPHY_RDWR_TX_CB_0,
R_DPHY_RDWR_TX_CB_1,
R_DPHY_RDWR_TX_CB_2,
R_DPHY_RDWR_TX_CB_3,
R_DPHY_RDWR_TX_CB_4,
R_DPHY_RDWR_TX_CB_5,
R_DPHY_RDWR_TX_CB_6,
R_DPHY_RD_TX_ANA_CB_0,
R_DPHY_RD_TX_ANA_CB_1,
R_DPHY_RD_TX_ANA_CB_2,
R_DPHY_RDWR_TX_ANA_CB_3,
R_DPHY_RDWR_TX_DAC_0,
R_DPHY_RDWR_TX_DAC_1,
R_DPHY_RDWR_TX_DAC_2,
R_DPHY_RDWR_TX_DAC_3,
R_DPHY_RD_TX_DAC_0,
R_DPHY_RD_TX_DAC_1,
R_DPHY_RD_TX_DAC_2,
R_DPHY_RDWR_TX_TERM_CAL_0,
R_DPHY_RDWR_TX_TERM_CAL_1,
R_DPHY_RDWR_TX_TERM_CAL_2,
R_DPHY_RD_TX_TERM_CAL_0,
R_DPHY_RD_TX_TERM_CAL_1,
R_DPHY_RD_TX_TERM_CAL_2,
R_DPHY_RDWR_TX_SLEW_0,
R_DPHY_RDWR_TX_SLEW_1,
R_DPHY_RDWR_TX_SLEW_2,
R_DPHY_RDWR_TX_SLEW_3,
R_DPHY_RDWR_TX_SLEW_4,
R_DPHY_RDWR_TX_SLEW_5,
R_DPHY_RDWR_TX_SLEW_6,
R_DPHY_RDWR_TX_SLEW_7,
R_DPHY_RD_TX_SLEW_0,
R_DPHY_RDWR_TX_CLKLANE_LANE_0,
R_DPHY_RDWR_TX_CLKLANE_LANE_1,
R_DPHY_RDWR_TX_CLKLANE_LANE_2,
R_DPHY_RDWR_TX_CLKLANE_LANE_3,
R_DPHY_RDWR_TX_CLKLANE_LANE_4,
R_DPHY_RDWR_TX_CLKLANE_LANE_5,
R_DPHY_RDWR_TX_CLKLANE_LANE_6,
R_DPHY_RDWR_TX_CLKLANE_LANE_SLEWRATE_0,
R_DPHY_RDWR_TX_CLKLANE_LANE_SLEWRATE_1,
R_DPHY_RDWR_TX_CLKLANE_LANE_SLEWRATE_2,
R_DPHY_RDWR_TX_CLKLANE_LANE_SLEWRATE_3,
R_DPHY_RD_TX_CLKLANE_LANE_SLEWRATE_0,
R_DPHY_RD_TX_CLKLANE_LANE_SLEWRATE_1,
R_DPHY_RD_TX_CLKLANE_LANE_SLEWRATE_2,
R_DPHY_RD_TX_CLKLANE_LANE_SLEWRATE_3,
R_DPHY_RD_TX_CLKLANE_LANE_0,
R_DPHY_RD_TX_CLKLANE_LANE_1,
R_DPHY_RD_TX_CLKLANE_AFE_OBS_0,
R_DPHY_RD_TX_CLKLANE_AFE_OBS_1,
R_DPHY_RD_TX_CLKLANE_AFE_OBS_2,
R_DPHY_RD_TX_CLKLANE_AFE_OBS_3,
R_DPHY_RDWR_TX_CLKLANE_BIST_0,
R_DPHY_RD_TX_CLKLANE_BIST_0,
R_DPHY_RDWR_TX_LANE0_LANE_0,
R_DPHY_RDWR_TX_LANE0_LANE_1,
R_DPHY_RDWR_TX_LANE0_LANE_2,
R_DPHY_RDWR_TX_LANE0_LANE_3,
R_DPHY_RDWR_TX_LANE0_LANE_4,
R_DPHY_RDWR_TX_LANE0_LANE_5,
R_DPHY_RDWR_TX_LANE0_LANE_6,
R_DPHY_RDWR_TX_LANE0_LANE_7,
R_DPHY_RDWR_TX_LANE0_LANE_8,
R_DPHY_RDWR_TX_LANE0_LANE_9,
R_DPHY_RDWR_TX_LANE0_SLEWRATE_0,
R_DPHY_RDWR_TX_LANE0_SLEWRATE_1,
R_DPHY_RDWR_TX_LANE0_SLEWRATE_2,
R_DPHY_RDWR_TX_LANE0_SLEWRATE_3,
R_DPHY_RD_TX_LANE0_SLEWRATE_0,
R_DPHY_RD_TX_LANE0_SLEWRATE_1,
R_DPHY_RD_TX_LANE0_SLEWRATE_2,
R_DPHY_RD_TX_LANE0_SLEWRATE_3,
R_DPHY_RD_TX_LANE0_LANE_0,
R_DPHY_RD_TX_LANE0_LANE_1,
R_DPHY_RD_TX_LANE0_LANE_3,
R_DPHY_RD_TX_LANE0_LANE_4,
R_DPHY_RDWR_TX_LANE0_BIST_0,
R_DPHY_RD_TX_LANE0_BIST_0,
R_DPHY_RD_TX_LANE0_AFE_OBS_0,
R_DPHY_RD_TX_LANE0_AFE_OBS_1,
R_DPHY_RD_TX_LANE0_AFE_OBS_2,
R_DPHY_RD_TX_LANE0_AFE_OBS_3,
R_DPHY_RDWR_TX_LANE1_LANE_0,
R_DPHY_RDWR_TX_LANE1_LANE_1,
R_DPHY_RDWR_TX_LANE1_LANE_2,
R_DPHY_RDWR_TX_LANE1_LANE_3,
R_DPHY_RDWR_TX_LANE1_LANE_4,
R_DPHY_RDWR_TX_LANE1_LANE_5,
R_DPHY_RDWR_TX_LANE1_LANE_6,
R_DPHY_RDWR_TX_LANE1_LANE_7,
R_DPHY_RDWR_TX_LANE1_LANE_8,
R_DPHY_RDWR_TX_LANE1_SLEWRATE_0,
R_DPHY_RDWR_TX_LANE1_SLEWRATE_1,
R_DPHY_RDWR_TX_LANE1_SLEWRATE_2,
R_DPHY_RDWR_TX_LANE1_SLEWRATE_3,
R_DPHY_RD_TX_LANE1_SLEWRATE_0,
R_DPHY_RD_TX_LANE1_SLEWRATE_1,
R_DPHY_RD_TX_LANE1_SLEWRATE_2,
R_DPHY_RD_TX_LANE1_SLEWRATE_3,
R_DPHY_RD_TX_LANE1_LANE_0,
R_DPHY_RD_TX_LANE1_LANE_1,
R_DPHY_RD_TX_LANE1_LANE_4,
R_DPHY_RDWR_TX_LANE1_BIST_0,
R_DPHY_RD_TX_LANE1_BIST_0,
R_DPHY_RD_TX_LANE1_AFE_OBS_4,
R_DPHY_RD_TX_LANE1_AFE_OBS_5,
R_DPHY_RD_TX_LANE1_AFE_OBS_6,
R_DPHY_RD_TX_LANE1_AFE_OBS_7,
R_DPHY_RDWR_TX_LANE2_LANE_0,
R_DPHY_RDWR_TX_LANE2_LANE_1,
R_DPHY_RDWR_TX_LANE2_LANE_2,
R_DPHY_RDWR_TX_LANE2_LANE_3,
R_DPHY_RDWR_TX_LANE2_LANE_4,
R_DPHY_RDWR_TX_LANE2_LANE_5,
R_DPHY_RDWR_TX_LANE2_LANE_6,
R_DPHY_RDWR_TX_LANE2_LANE_7,
R_DPHY_RDWR_TX_LANE2_LANE_8,
R_DPHY_RDWR_TX_LANE2_SLEWRATE_0,
R_DPHY_RDWR_TX_LANE2_SLEWRATE_1,
R_DPHY_RDWR_TX_LANE2_SLEWRATE_2,
R_DPHY_RDWR_TX_LANE2_SLEWRATE_3,
R_DPHY_RD_TX_LANE2_SLEWRATE_0,
R_DPHY_RD_TX_LANE2_SLEWRATE_1,
R_DPHY_RD_TX_LANE2_SLEWRATE_2,
R_DPHY_RD_TX_LANE2_SLEWRATE_3,
R_DPHY_RD_TX_LANE2_LANE_0,
R_DPHY_RD_TX_LANE2_LANE_1,
R_DPHY_RD_TX_LANE2_LANE_4,
R_DPHY_RDWR_TX_LANE2_BIST_0,
R_DPHY_RD_TX_LANE2_BIST_0,
R_DPHY_RD_TX_LANE2_AFE_OBS_4,
R_DPHY_RD_TX_LANE2_AFE_OBS_5,
R_DPHY_RD_TX_LANE2_AFE_OBS_6,
R_DPHY_RD_TX_LANE2_AFE_OBS_7,
R_DPHY_RDWR_TX_LANE3_LANE_0,
R_DPHY_RDWR_TX_LANE3_LANE_1,
R_DPHY_RDWR_TX_LANE3_LANE_2,
R_DPHY_RDWR_TX_LANE3_LANE_3,
R_DPHY_RDWR_TX_LANE3_LANE_4,
R_DPHY_RDWR_TX_LANE3_LANE_5,
R_DPHY_RDWR_TX_LANE3_LANE_6,
R_DPHY_RDWR_TX_LANE3_LANE_7,
R_DPHY_RDWR_TX_LANE3_LANE_8,
R_DPHY_RDWR_TX_LANE3_SLEWRATE_0,
R_DPHY_RDWR_TX_LANE3_SLEWRATE_1,
R_DPHY_RDWR_TX_LANE3_SLEWRATE_2,
R_DPHY_RDWR_TX_LANE3_SLEWRATE_3,
R_DPHY_RD_TX_LANE3_SLEWRATE_0,
R_DPHY_RD_TX_LANE3_SLEWRATE_1,
R_DPHY_RD_TX_LANE3_SLEWRATE_2,
R_DPHY_RD_TX_LANE3_SLEWRATE_3,
R_DPHY_RD_TX_LANE3_LANE_0,
R_DPHY_RD_TX_LANE3_LANE_1,
R_DPHY_RD_TX_LANE3_LANE_4,
R_DPHY_RDWR_TX_LANE3_BIST_0,
R_DPHY_RD_TX_LANE3_BIST_0,
R_DPHY_RD_TX_LANE3_AFE_OBS_4,
R_DPHY_RD_TX_LANE3_AFE_OBS_5,
R_DPHY_RD_TX_LANE3_AFE_OBS_6,
R_DPHY_RD_TX_LANE3_AFE_OBS_7
};
int mipicsi_debug_vpg_preset(struct mipicsi_top_vpg *vpg,
enum mipicsi_debug_vpg_res res)
{
int ret;
/* NOTE Device must be populated in vpg struct before calling this */
pr_info("%s: E\n", __func__);
/* Frame and line numbers increment by 1 */
vpg->pkt_cfg = (0x1<<11) | (0x01<<9) | CSI2_RAW10;
pr_info("%s: VPG pkt=0x%x", __func__, vpg->pkt_cfg);
if (res == VPG_VGA) {
/* VGA Settings */
pr_info("%s: VGA ", __func__);
vpg->mode_cfg = 1;
vpg->pkt_size = 640;
vpg->hsa_time = 120;
vpg->hbp_time = 40;
vpg->hline_time = 800;
vpg->vsa_lines = 80;
vpg->vbp_lines = 20;
vpg->vfp_lines = 20;
vpg->act_lines = 480;
vpg->max_frame = 5;
vpg->start_line = 0;
vpg->step_line = 0;
} else if (res == VPG_1080P) {
/* 1080P Settings */
pr_info("%s: 1080P", __func__);
vpg->mode_cfg = 0;
vpg->pkt_size = 1920;
vpg->hsa_time = 53;
vpg->hbp_time = 10;
vpg->hline_time = 2200;
vpg->vsa_lines = 80;
vpg->vbp_lines = 20;
vpg->vfp_lines = 20;
vpg->act_lines = 1080;
vpg->max_frame = 5;
vpg->start_line = 0;
vpg->step_line = 0;
} else if (res == VPG_12MP) {
/* 12MP Settings */
pr_info("%s: 12MP", __func__);
vpg->mode_cfg = 0;
vpg->pkt_size = 4320;
vpg->hsa_time = 50;
vpg->hbp_time = 20;
vpg->hline_time = 4600;
vpg->vsa_lines = 80;
vpg->vbp_lines = 20;
vpg->vfp_lines = 20;
vpg->act_lines = 2880;
vpg->max_frame = 5;
vpg->start_line = 0;
vpg->step_line = 0;
}
ret = mipicsi_device_vpg(vpg);
pr_info("%s: X\n", __func__);
return ret;
}
int mipicsi_debug_dump(enum mipicsi_top_dev device)
{
uint16_t i, ctl_sz, dphy_sz;
struct mipicsi_top_reg reg;
uint16_t *ctl, *dphy;
reg.dev = device;
if ((device == MIPI_RX0) || (device == MIPI_RX1) ||
(device == MIPI_RX2)) {
ctl = valid_rx_ctl_offsets;
ctl_sz = sizeof(valid_rx_ctl_offsets)/sizeof(uint16_t);
dphy = valid_rx_g3dphy_offsets;
dphy_sz = sizeof(valid_rx_g3dphy_offsets)/sizeof(uint16_t);
} else if ((device == MIPI_TX0) || (device == MIPI_TX1)) {
ctl = valid_tx_ctl_offsets;
ctl_sz = sizeof(valid_tx_ctl_offsets)/sizeof(uint16_t);
dphy = valid_tx_g3dphy_offsets;
dphy_sz = sizeof(valid_tx_g3dphy_offsets)/sizeof(uint16_t);
} else
return -ENODEV;
for (i = 0; i < ctl_sz; i++) {
reg.offset = ctl[i];
mipicsi_top_read(&reg);
pr_err("Controller Reg Read: Offset 0x%x, Value 0x%x\n",
reg.offset, reg.value);
}
if (mipicsi_util_is_emulation()) {
pr_err("\nDaughtercard DPhy Reads\n");
for (i = 0; i <= 0xF4; i++) {
reg.offset = i;
mipicsi_top_dphy_read(&reg);
}
} else {
pr_err("\nGen3 DPhy Reads\n");
for (i = 0; i <= dphy_sz; i++) {
reg.offset = dphy[i];
mipicsi_top_dphy_read(&reg);
}
}
/* Take the device out of shutdown */
if ((reg.dev == MIPI_TX0) ||
(reg.dev == MIPI_TX1)) {
reg.offset = HWIO_MIPI_TX_PHY_RSTZ_REGOFF;
reg.value = 0x07;
mipicsi_top_write(&reg);
} else {
reg.offset = HWIO_MIPI_RX_PHY_SHUTDOWNZ_REGOFF;
reg.value = 1;
mipicsi_top_write(&reg);
reg.offset = HWIO_MIPI_RX_DPHY_RSTZ_REGOFF;
reg.value = 1;
mipicsi_top_write(&reg);
}
return 0;
}