commit 8cce3c9a70b6406542ca3dac4223cdf5af4f7779
author Jeff Fan <jeff.fan@intel.com> Fri Aug 19 10:32:30 2016 +0800
committer Jeff Fan <jeff.fan@intel.com> Fri Aug 19 15:11:01 2016 +0800
tree c2c16f166ed5841a62765c815e581a4bdc71939a
parent 1de28466b043003d389407661d3e01aee286345c

UefiCpuPkg/MpInitLib: MicrocodeData used but maybe uninitialized

Cc: Feng Tian <feng.tian@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>

UefiCpuPkg/Library/MpInitLib/Microcode.c

diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/MpInitLib/Microcode.c
index 0fd8e8c..5bb0145 100644
--- a/UefiCpuPkg/Library/MpInitLib/Microcode.c
+++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c
@@ -92,6 +92,7 @@
   PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId;

 

   LatestRevision = 0;

+  MicrocodeData  = NULL;

   MicrocodeEnd = (UINTN) (MicrocodePatchAddress + MicrocodePatchRegionSize);

   MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (UINTN) MicrocodePatchAddress;

   do {

@@ -198,6 +199,7 @@
     // Revision. A processor with no loaded update is considered to have a

     // revision equal to zero.

     //

+    ASSERT (MicrocodeData != NULL);

     AsmWriteMsr64 (

         MSR_IA32_BIOS_UPDT_TRIG,

         (UINT64) (UINTN) MicrocodeData