commit 0613ccbd1357b1f6aecab27a2e72dde328d36f6d
author Maurice Ma <maurice.ma@intel.com> Mon Oct 17 10:48:04 2016 -0700
committer Maurice Ma <maurice.ma@intel.com> Tue Oct 18 22:21:53 2016 -0700
tree 5d888fb69cb94f2b0f6faa0be140b542e5219ec1
parent 201fbce6fbc69ebb53cc5b1b263059051e561e86

CorebootPayloadPkg/PciHostBridgeLib: Fix the wrong PCI resource limit

The current PCI resource limit calculation in CorebootPayloadPkg
PciHostBridgeLib is wrong. Adjusted it to match the PciHostBridge
driver's expectation.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by : Prince Agyeman <prince.agyeman@intel.com>

CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c

diff --git a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 0f1c8cb..6d94ff7 100644
--- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -91,7 +91,7 @@
   // Align IO  resource at 4K  boundary

   //

   Mask        = 0xFFFULL;

-  Io->Limit   = (Io->Limit + Mask) & ~Mask;

+  Io->Limit   = ((Io->Limit + Mask) & ~Mask) - 1;

   if (Io->Base != MAX_UINT64) {

     Io->Base &= ~Mask;

   }

@@ -100,7 +100,7 @@
   // Align MEM resource at 1MB boundary

   //

   Mask        = 0xFFFFFULL;

-  Mem->Limit  = (Mem->Limit + Mask) & ~Mask;

+  Mem->Limit  = ((Mem->Limit + Mask) & ~Mask) - 1;

   if (Mem->Base != MAX_UINT64) {

     Mem->Base &= ~Mask;

   }