Perform a cache flush after ENTER PSCI timestamp capture
Without an explicit cache flush, the next timestamp captured might have
a bogus value.
This can happen if the following operations happen in order,
on a CPU that's being powered down.
1) ENTER PSCI timestamp is captured with caches enabled.
2) The next timestamp (ENTER_HW_LOW_PWR) is captured with caches
disabled.
3) On a system that uses a write-back cache configuration, the
cache line that holds the PMF timestamps is evicted.
After step 1), the ENTER_PSCI timestamp is cached and not in main memory.
After step 2), the ENTER_HW_LOW_PWR timestamp is stored in main memory.
Before the CPU power down happens, the hardware evicts the cache line that
contains the PMF timestamps for this service. As a result, the timestamp
captured in step 2) is overwritten with a bogus value.
Change-Id: Ic1bd816498d1a6d4dc16540208ed3a5efe43f529
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index 97a9fbd..010bb8f 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -81,9 +81,14 @@
uint64_t ret;
#if ENABLE_RUNTIME_INSTRUMENTATION
+
+ /*
+ * Flush cache line so that even if CPU power down happens
+ * the timestamp update is reflected in memory.
+ */
PMF_WRITE_TIMESTAMP(rt_instr_svc,
RT_INSTR_ENTER_PSCI,
- PMF_NO_CACHE_MAINT,
+ PMF_CACHE_MAINT,
get_cpu_data(cpu_data_pmf_ts[CPU_DATA_PMF_TS0_IDX]));
#endif
