Tegra186: reset power state info during CPU_ON
This patch resets the power state info for CPUs when onlining,
as we set deepest power when offlining a core but that may not
be requested by non-secure sw which controls idle states. It
will re-init this info from non-secure software when the core
come online.
Original change by Prashant Gaikwad <pgaikwad@nvidia.com>
Change-Id: Id6c2fa2b821c7705aafbb561a62348c36fd3abd8
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
index 8911e8f..b518918 100644
--- a/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
+++ b/plat/nvidia/tegra/soc/t186/plat_psci_handlers.c
@@ -247,6 +247,18 @@
gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
/*
+ * Reset power state info for CPUs when onlining, we set deepest power
+ * when offlining a core but that may not be requested by non-secure
+ * sw which controls idle states. It will re-init this info from
+ * non-secure software when the core come online.
+ */
+ write_ctx_reg(gp_regs, CTX_GPREG_X4, 0);
+ write_ctx_reg(gp_regs, CTX_GPREG_X5, 0);
+ write_ctx_reg(gp_regs, CTX_GPREG_X6, 1);
+ mce_command_handler(MCE_CMD_UPDATE_CSTATE_INFO, TEGRA_ARI_CLUSTER_CC1,
+ 0, 0);
+
+ /*
* Check if we are exiting from deep sleep and restore SE
* context if we are.
*/
