commit 5a5dc61713fd563a3bb8a89bd26729f4348bb5d6
author Derek Basehore <dbasehore@chromium.org> Thu Feb 09 22:02:42 2017 -0800
committer Xing Zheng <zhengxing@rock-chips.com> Fri Feb 24 20:07:45 2017 +0800
tree 9b65ed64df3530d3d33aca4274df3da604fb2d81
parent 43f52e92e45823c6967b20fb9e90dd6e3dc7275f

rockchip: rk3399: Fix CAS latency setting

The F1 CAS latency setting was not bit shifted, which resulted in
setting the DRAM additive latency value instead.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

plat/rockchip/rk3399/drivers/dram/dfs.c

diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c
index 37f666a..98ecd51 100644
--- a/plat/rockchip/rk3399/drivers/dram/dfs.c
+++ b/plat/rockchip/rk3399/drivers/dram/dfs.c
@@ -1254,7 +1254,7 @@
 		mmio_clrsetbits_32(PI_REG(i, 44), 0x3f, PI_ADD_LATENCY);
 		/* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */
 		mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8,
-				   pdram_timing->cl * 2);
+				   (pdram_timing->cl * 2) << 8);
 		/* PI_47 PI_TREF_F1:RW:16:16 */
 		mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16,
 				   pdram_timing->trefi << 16);