Use #ifdef for IMAGE_BL* instead of #if
One nasty part of ATF is some of boolean macros are always defined
as 1 or 0, and the rest of them are only defined under certain
conditions.
For the former group, "#if FOO" or "#if !FOO" must be used because
"#ifdef FOO" is always true. (Options passed by $(call add_define,)
are the cases.)
For the latter, "#ifdef FOO" or "#ifndef FOO" should be used because
checking the value of an undefined macro is strange.
Here, IMAGE_BL* is handled by make_helpers/build_macro.mk like
follows:
$(eval IMAGE := IMAGE_BL$(call uppercase,$(3)))
$(OBJ): $(2)
@echo " CC $$<"
$$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) -c $$< -o $$@
This means, IMAGE_BL* is defined when building the corresponding
image, but *undefined* for the other images.
So, IMAGE_BL* belongs to the latter group where we should use #ifdef
or #ifndef.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
diff --git a/drivers/arm/ccn/ccn.c b/drivers/arm/ccn/ccn.c
index 060acdd..d739c6b 100644
--- a/drivers/arm/ccn/ccn.c
+++ b/drivers/arm/ccn/ccn.c
@@ -38,7 +38,7 @@
#include "ccn_private.h"
static const ccn_desc_t *ccn_plat_desc;
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
DEFINE_BAKERY_LOCK(ccn_lock);
#endif
@@ -285,7 +285,7 @@
assert(ccn_plat_desc);
assert(ccn_plat_desc->periphbase);
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
bakery_lock_get(&ccn_lock);
#endif
start_region_id = region_id;
@@ -305,7 +305,7 @@
rn_id_map);
}
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
bakery_lock_release(&ccn_lock);
#endif
}
diff --git a/include/common/aarch32/el3_common_macros.S b/include/common/aarch32/el3_common_macros.S
index dcb4edd..463a080 100644
--- a/include/common/aarch32/el3_common_macros.S
+++ b/include/common/aarch32/el3_common_macros.S
@@ -228,7 +228,7 @@
* ---------------------------------------------------------------------
*/
.if \_init_c_runtime
-#if IMAGE_BL32
+#ifdef IMAGE_BL32
/* -----------------------------------------------------------------
* Invalidate the RW memory used by the BL32 (SP_MIN) image. This
* includes the data and NOBITS sections. This is done to
@@ -253,7 +253,7 @@
bl zeromem
#endif
-#if IMAGE_BL1
+#ifdef IMAGE_BL1
/* -----------------------------------------------------
* Copy data from ROM to RAM.
* -----------------------------------------------------
diff --git a/include/common/aarch64/el3_common_macros.S b/include/common/aarch64/el3_common_macros.S
index a418911..cbfa6ee 100644
--- a/include/common/aarch64/el3_common_macros.S
+++ b/include/common/aarch64/el3_common_macros.S
@@ -49,7 +49,7 @@
msr sctlr_el3, x0
isb
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
/* ---------------------------------------------------------------------
* Initialise the per-cpu cache pointer to the CPU.
* This is done early to enable crash reporting to have access to crash
@@ -235,7 +235,7 @@
* ---------------------------------------------------------------------
*/
.if \_init_c_runtime
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
/* -------------------------------------------------------------
* Invalidate the RW memory used by the BL31 image. This
* includes the data and NOBITS sections. This is done to
@@ -260,7 +260,7 @@
bl zeromem16
#endif
-#if IMAGE_BL1
+#ifdef IMAGE_BL1
ldr x0, =__DATA_RAM_START__
ldr x1, =__DATA_ROM_START__
ldr x2, =__DATA_SIZE__
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 5076dfd..66c20fc 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -170,13 +170,13 @@
extern uintptr_t __RO_END__;
#endif
-#if IMAGE_BL2
+#if defined(IMAGE_BL2)
extern uintptr_t __BL2_END__;
-#elif IMAGE_BL2U
+#elif defined(IMAGE_BL2U)
extern uintptr_t __BL2U_END__;
-#elif IMAGE_BL31
+#elif defined(IMAGE_BL31)
extern uintptr_t __BL31_END__;
-#elif IMAGE_BL32
+#elif defined(IMAGE_BL32)
extern uintptr_t __BL32_END__;
#endif /* IMAGE_BLX */
diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S
index 17dd258..64df236 100644
--- a/include/lib/cpus/aarch32/cpu_macros.S
+++ b/include/lib/cpus/aarch32/cpu_macros.S
@@ -51,11 +51,11 @@
CPU_MIDR: /* cpu_ops midr */
.space 4
/* Reset fn is needed during reset */
-#if IMAGE_BL1 || IMAGE_BL32
+#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
CPU_RESET_FUNC: /* cpu_ops reset_func */
.space 4
#endif
-#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
+#ifdef IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
.space (4 * CPU_MAX_PWR_DWN_OPS)
#endif
@@ -117,10 +117,10 @@
.align 2
.type cpu_ops_\_name, %object
.word \_midr
-#if IMAGE_BL1 || IMAGE_BL32
+#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
.word \_resetfunc
#endif
-#if IMAGE_BL32
+#ifdef IMAGE_BL32
1:
/* Insert list of functions */
fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 570ef88..5012877 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -51,15 +51,15 @@
CPU_MIDR: /* cpu_ops midr */
.space 8
/* Reset fn is needed in BL at reset vector */
-#if IMAGE_BL1 || IMAGE_BL31
+#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
CPU_RESET_FUNC: /* cpu_ops reset_func */
.space 8
#endif
-#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
+#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
CPU_PWR_DWN_OPS: /* cpu_ops power down functions */
.space (8 * CPU_MAX_PWR_DWN_OPS)
#endif
-#if (IMAGE_BL31 && CRASH_REPORTING)
+#if defined(IMAGE_BL31) && CRASH_REPORTING
CPU_REG_DUMP: /* cpu specific register dump for crash reporting */
.space 8
#endif
@@ -121,10 +121,10 @@
.align 3
.type cpu_ops_\_name, %object
.quad \_midr
-#if IMAGE_BL1 || IMAGE_BL31
+#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
.quad \_resetfunc
#endif
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
1:
/* Insert list of functions */
fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
@@ -141,7 +141,7 @@
.endif
.endif
#endif
-#if (IMAGE_BL31 && CRASH_REPORTING)
+#if defined(IMAGE_BL31) && CRASH_REPORTING
.quad \_name\()_cpu_reg_dump
#endif
.endm
diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h
index ad82923..dee868f 100644
--- a/include/plat/arm/board/common/board_arm_def.h
+++ b/include/plat/arm/board/common/board_arm_def.h
@@ -39,23 +39,23 @@
*/
/* Size of cacheable stacks */
-#if IMAGE_BL1
+#if defined(IMAGE_BL1)
#if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
#else
# define PLATFORM_STACK_SIZE 0x440
#endif
-#elif IMAGE_BL2
+#elif defined(IMAGE_BL2)
# if TRUSTED_BOARD_BOOT
# define PLATFORM_STACK_SIZE 0x1000
# else
# define PLATFORM_STACK_SIZE 0x400
# endif
-#elif IMAGE_BL2U
+#elif defined(IMAGE_BL2U)
# define PLATFORM_STACK_SIZE 0x200
-#elif IMAGE_BL31
+#elif defined(IMAGE_BL31)
# define PLATFORM_STACK_SIZE 0x400
-#elif IMAGE_BL32
+#elif defined(IMAGE_BL32)
# define PLATFORM_STACK_SIZE 0x440
#endif
@@ -73,7 +73,7 @@
* Optimisation is less important for the other, transient boot images so a
* common, maximum value is used across these images.
*/
-#if IMAGE_BL31 || IMAGE_BL32
+#if defined(IMAGE_BL31) || defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 6
# define MAX_XLAT_TABLES 4
#else
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index c167aa2..e878f9e 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -64,7 +64,7 @@
#endif
);
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
/*
* Use this macro to instantiate lock before it is used in below
* arm_lock_xxx() macros
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 900d158..d8cabfe 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -34,7 +34,7 @@
#include <cpu_data.h>
#include <cpu_macros.S>
-#if IMAGE_BL1 || IMAGE_BL32
+#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
/*
* The reset handler common to all platforms. After a matching
* cpu_ops structure entry is found, the correponding reset_handler
@@ -68,7 +68,7 @@
#endif /* IMAGE_BL1 || IMAGE_BL32 */
-#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
+#ifdef IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
/*
* void prepare_cpu_pwr_dwn(unsigned int power_level)
*
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 4f47439..7365d35 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -31,14 +31,14 @@
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
#include <cpu_data.h>
#endif
#include <cpu_macros.S>
#include <debug.h>
/* Reset fn is needed in BL at reset vector */
-#if IMAGE_BL1 || IMAGE_BL31
+#if defined(IMAGE_BL1) || defined(IMAGE_BL31)
/*
* The reset handler common to all platforms. After a matching
* cpu_ops structure entry is found, the correponding reset_handler
@@ -72,7 +72,7 @@
#endif /* IMAGE_BL1 || IMAGE_BL31 */
-#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
+#ifdef IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
/*
* void prepare_cpu_pwr_dwn(unsigned int power_level)
*
@@ -130,7 +130,7 @@
endfunc init_cpu_ops
#endif /* IMAGE_BL31 */
-#if IMAGE_BL31 && CRASH_REPORTING
+#if defined(IMAGE_BL31) && CRASH_REPORTING
/*
* The cpu specific registers which need to be reported in a crash
* are reported via cpu_ops cpu_reg_dump function. After a matching
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 35380f3..e26950d 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -116,7 +116,7 @@
scr_el3 &= ~SCR_EA_BIT;
#endif
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
/*
* IRQ/FIQ bits only need setting if interrupt routing
* model has been set up for BL31.
diff --git a/plat/arm/board/common/board_css_common.c b/plat/arm/board/common/board_css_common.c
index 69b744d..3fcc6ee 100644
--- a/plat/arm/board/common/board_css_common.c
+++ b/plat/arm/board/common/board_css_common.c
@@ -35,7 +35,7 @@
* This doesn't include Trusted SRAM as arm_setup_page_tables() already
* takes care of mapping it.
*/
-#if IMAGE_BL1
+#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RO,
@@ -48,7 +48,7 @@
{0}
};
#endif
-#if IMAGE_BL2
+#ifdef IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RO,
@@ -60,7 +60,7 @@
{0}
};
#endif
-#if IMAGE_BL2U
+#ifdef IMAGE_BL2U
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
CSS_MAP_DEVICE,
@@ -68,7 +68,7 @@
{0}
};
#endif
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
@@ -77,7 +77,7 @@
{0}
};
#endif
-#if IMAGE_BL32
+#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
V2M_MAP_IOFPGA,
CSS_MAP_DEVICE,
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 3df472c..e201101 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -73,7 +73,7 @@
* The flash needs to be mapped as writable in order to erase the FIP's Table of
* Contents in case of unrecoverable error (see plat_error_handler()).
*/
-#if IMAGE_BL1
+#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RW,
@@ -87,7 +87,7 @@
{0}
};
#endif
-#if IMAGE_BL2
+#ifdef IMAGE_BL2
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_FLASH0_RW,
@@ -103,14 +103,14 @@
{0}
};
#endif
-#if IMAGE_BL2U
+#ifdef IMAGE_BL2U
const mmap_region_t plat_arm_mmap[] = {
MAP_DEVICE0,
V2M_MAP_IOFPGA,
{0}
};
#endif
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
V2M_MAP_IOFPGA,
@@ -119,7 +119,7 @@
{0}
};
#endif
-#if IMAGE_BL32
+#ifdef IMAGE_BL32
const mmap_region_t plat_arm_mmap[] = {
#ifdef AARCH32
ARM_MAP_SHARED_RAM,
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index adc4704..f89f7b4 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -82,27 +82,27 @@
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.
*/
-#if IMAGE_BL1
+#ifdef IMAGE_BL1
# define PLAT_ARM_MMAP_ENTRIES 7
# define MAX_XLAT_TABLES 4
#endif
-#if IMAGE_BL2
+#ifdef IMAGE_BL2
# define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 3
#endif
-#if IMAGE_BL2U
+#ifdef IMAGE_BL2U
# define PLAT_ARM_MMAP_ENTRIES 4
# define MAX_XLAT_TABLES 3
#endif
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
# define PLAT_ARM_MMAP_ENTRIES 5
# define MAX_XLAT_TABLES 2
#endif
-#if IMAGE_BL32
+#ifdef IMAGE_BL32
# define PLAT_ARM_MMAP_ENTRIES 4
# define MAX_XLAT_TABLES 3
#endif
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 6d68bfb..acfb3a5 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -79,7 +79,7 @@
* can use GIC system registers to manage interrupts and does
* not need GIC interface base addresses to be configured.
*/
-#if (AARCH32 && IMAGE_BL32) || (IMAGE_BL31 && !AARCH32)
+#if (AARCH32 && defined(IMAGE_BL32)) || (defined(IMAGE_BL31) && !AARCH32)
gicv3_driver_init(&arm_gic_data);
#endif
}
diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c
index c961d62..3bea013 100644
--- a/plat/common/plat_gicv3.c
+++ b/plat/common/plat_gicv3.c
@@ -36,7 +36,7 @@
#include <interrupt_mgmt.h>
#include <platform.h>
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
/*
* The following platform GIC functions are weakly defined. They
@@ -180,7 +180,7 @@
}
}
#endif
-#if IMAGE_BL32
+#ifdef IMAGE_BL32
#pragma weak plat_ic_get_pending_interrupt_id
#pragma weak plat_ic_acknowledge_interrupt
diff --git a/plat/mediatek/mt6795/include/platform_def.h b/plat/mediatek/mt6795/include/platform_def.h
index 275333f..16b3d39 100644
--- a/plat/mediatek/mt6795/include/platform_def.h
+++ b/plat/mediatek/mt6795/include/platform_def.h
@@ -156,13 +156,13 @@
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL1
+#elif defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
-#elif IMAGE_BL2
+#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
-#elif IMAGE_BL31
+#elif defined(IMAGE_BL31)
#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL32
+#elif defined(IMAGE_BL32)
#define PLATFORM_STACK_SIZE 0x440
#endif
diff --git a/plat/mediatek/mt8173/include/platform_def.h b/plat/mediatek/mt8173/include/platform_def.h
index dc5b000..8f771e3 100644
--- a/plat/mediatek/mt8173/include/platform_def.h
+++ b/plat/mediatek/mt8173/include/platform_def.h
@@ -43,13 +43,13 @@
******************************************************************************/
/* Size of cacheable stacks */
-#if IMAGE_BL1
+#if defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
-#elif IMAGE_BL2
+#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
-#elif IMAGE_BL31
+#elif defined(IMAGE_BL31)
#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL32
+#elif defined(IMAGE_BL32)
#define PLATFORM_STACK_SIZE 0x440
#endif
diff --git a/plat/nvidia/tegra/include/platform_def.h b/plat/nvidia/tegra/include/platform_def.h
index 70ddaa9..cd06d93 100644
--- a/plat/nvidia/tegra/include/platform_def.h
+++ b/plat/nvidia/tegra/include/platform_def.h
@@ -40,7 +40,7 @@
******************************************************************************/
/* Size of cacheable stacks */
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
#define PLATFORM_STACK_SIZE 0x400
#endif
diff --git a/plat/qemu/qemu_common.c b/plat/qemu/qemu_common.c
index 7ba1d34..0fe7df1 100644
--- a/plat/qemu/qemu_common.c
+++ b/plat/qemu/qemu_common.c
@@ -68,7 +68,7 @@
* This doesn't include TZRAM as the 'mem_layout' argument passed to
* arm_configure_mmu_elx() will give the available subset of that,
*/
-#if IMAGE_BL1
+#ifdef IMAGE_BL1
static const mmap_region_t plat_qemu_mmap[] = {
MAP_FLASH0,
MAP_SHARED_RAM,
@@ -82,7 +82,7 @@
{0}
};
#endif
-#if IMAGE_BL2
+#ifdef IMAGE_BL2
static const mmap_region_t plat_qemu_mmap[] = {
MAP_FLASH0,
MAP_SHARED_RAM,
@@ -98,7 +98,7 @@
{0}
};
#endif
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
static const mmap_region_t plat_qemu_mmap[] = {
MAP_SHARED_RAM,
MAP_DEVICE0,
diff --git a/plat/rockchip/common/rockchip_gicv3.c b/plat/rockchip/common/rockchip_gicv3.c
index 7730896..f3d306e 100644
--- a/plat/rockchip/common/rockchip_gicv3.c
+++ b/plat/rockchip/common/rockchip_gicv3.c
@@ -82,7 +82,7 @@
* can use GIC system registers to manage interrupts and does
* not need GIC interface base addresses to be configured.
*/
-#if IMAGE_BL31
+#ifdef IMAGE_BL31
gicv3_driver_init(&rockchip_gic_data);
#endif
}
diff --git a/plat/rockchip/rk3368/include/platform_def.h b/plat/rockchip/rk3368/include/platform_def.h
index 5d801cf..d72893c 100644
--- a/plat/rockchip/rk3368/include/platform_def.h
+++ b/plat/rockchip/rk3368/include/platform_def.h
@@ -50,13 +50,13 @@
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL1
+#elif defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
-#elif IMAGE_BL2
+#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
-#elif IMAGE_BL31
+#elif defined(IMAGE_BL31)
#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL32
+#elif defined(IMAGE_BL32)
#define PLATFORM_STACK_SIZE 0x440
#endif
diff --git a/plat/rockchip/rk3399/include/platform_def.h b/plat/rockchip/rk3399/include/platform_def.h
index b494824..5ccc532 100644
--- a/plat/rockchip/rk3399/include/platform_def.h
+++ b/plat/rockchip/rk3399/include/platform_def.h
@@ -50,13 +50,13 @@
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL1
+#elif defined(IMAGE_BL1)
#define PLATFORM_STACK_SIZE 0x440
-#elif IMAGE_BL2
+#elif defined(IMAGE_BL2)
#define PLATFORM_STACK_SIZE 0x400
-#elif IMAGE_BL31
+#elif defined(IMAGE_BL31)
#define PLATFORM_STACK_SIZE 0x800
-#elif IMAGE_BL32
+#elif defined(IMAGE_BL32)
#define PLATFORM_STACK_SIZE 0x440
#endif
